drivers/gpu/drm/bochs/bochs_hw.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  */
   7
   8 #include "bochs.h"
   9
  10 /* ---------------------------------------------------------------------- */
  11
  12 static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
  13 {
  14         if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
  15                 return;
  16
  17         if (bochs->mmio) {
  18                 int offset = ioport - 0x3c0 + 0x400;
  19                 writeb(val, bochs->mmio + offset);
  20         } else {
  21                 outb(val, ioport);
  22         }
  23 }
  24
  25 static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg)
  26 {
  27         u16 ret = 0;
  28
  29         if (bochs->mmio) {
  30                 int offset = 0x500 + (reg << 1);
  31                 ret = readw(bochs->mmio + offset);
  32         } else {
  33                 outw(reg, VBE_DISPI_IOPORT_INDEX);
  34                 ret = inw(VBE_DISPI_IOPORT_DATA);
  35         }
  36         return ret;
  37 }
  38
  39 static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
  40 {
  41         if (bochs->mmio) {
  42                 int offset = 0x500 + (reg << 1);
  43                 writew(val, bochs->mmio + offset);
  44         } else {
  45                 outw(reg, VBE_DISPI_IOPORT_INDEX);
  46                 outw(val, VBE_DISPI_IOPORT_DATA);
  47         }
  48 }
  49
  50 static void bochs_hw_set_big_endian(struct bochs_device *bochs)
  51 {
  52         if (bochs->qext_size < 8)
  53                 return;
  54
  55         writel(0xbebebebe, bochs->mmio + 0x604);
  56 }
  57
  58 static void bochs_hw_set_little_endian(struct bochs_device *bochs)
  59 {
  60         if (bochs->qext_size < 8)
  61                 return;
  62
  63         writel(0x1e1e1e1e, bochs->mmio + 0x604);
  64 }
  65
  66 #ifdef __BIG_ENDIAN
  67 #define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b)
  68 #else
  69 #define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b)
  70 #endif
  71
  72 static int bochs_get_edid_block(void *data, u8 *buf,
  73                                 unsigned int block, size_t len)
  74 {
  75         struct bochs_device *bochs = data;
  76         size_t i, start = block * EDID_LENGTH;
  77
  78         if (start + len > 0x400 /* vga register offset */)
  79                 return -1;
  80
  81         for (i = 0; i < len; i++) {
  82                 buf[i] = readb(bochs->mmio + start + i);
  83         }
  84         return 0;
  85 }
  86
  87 int bochs_hw_load_edid(struct bochs_device *bochs)
  88 {
  89         if (!bochs->mmio)
  90                 return -1;
  91
  92         kfree(bochs->edid);
  93         bochs->edid = drm_do_get_edid(&bochs->connector,
  94                                       bochs_get_edid_block, bochs);
  95         if (bochs->edid == NULL)
  96                 return -1;
  97
  98         return 0;
  99 }
 100
 101 int bochs_hw_init(struct drm_device *dev)
 102 {
 103         struct bochs_device *bochs = dev->dev_private;
 104         struct pci_dev *pdev = dev->pdev;
 105         unsigned long addr, size, mem, ioaddr, iosize;
 106         u16 id;
 107
 108         if (pdev->resource[2].flags & IORESOURCE_MEM) {
 109                 /* mmio bar with vga and bochs registers present */
 110                 if (pci_request_region(pdev, 2, "bochs-drm") != 0) {
 111                         DRM_ERROR("Cannot request mmio region\n");
 112                         return -EBUSY;
 113                 }
 114                 ioaddr = pci_resource_start(pdev, 2);
 115                 iosize = pci_resource_len(pdev, 2);
 116                 bochs->mmio = ioremap(ioaddr, iosize);
 117                 if (bochs->mmio == NULL) {
 118                         DRM_ERROR("Cannot map mmio region\n");
 119                         return -ENOMEM;
 120                 }
 121         } else {
 122                 ioaddr = VBE_DISPI_IOPORT_INDEX;
 123                 iosize = 2;
 124                 if (!request_region(ioaddr, iosize, "bochs-drm")) {
 125                         DRM_ERROR("Cannot request ioports\n");
 126                         return -EBUSY;
 127                 }
 128                 bochs->ioports = 1;
 129         }
 130
 131         id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID);
 132         mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K)
 133                 * 64 * 1024;
 134         if ((id & 0xfff0) != VBE_DISPI_ID0) {
 135                 DRM_ERROR("ID mismatch\n");
 136                 return -ENODEV;
 137         }
 138
 139         if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0)
 140                 return -ENODEV;
 141         addr = pci_resource_start(pdev, 0);
 142         size = pci_resource_len(pdev, 0);
 143         if (addr == 0)
 144                 return -ENODEV;
 145         if (size != mem) {
 146                 DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n",
 147                         size, mem);
 148                 size = min(size, mem);
 149         }
 150
 151         if (pci_request_region(pdev, 0, "bochs-drm") != 0) {
 152                 DRM_ERROR("Cannot request framebuffer\n");
 153                 return -EBUSY;
 154         }
 155
 156         bochs->fb_map = ioremap(addr, size);
 157         if (bochs->fb_map == NULL) {
 158                 DRM_ERROR("Cannot map framebuffer\n");
 159                 return -ENOMEM;
 160         }
 161         bochs->fb_base = addr;
 162         bochs->fb_size = size;
 163
 164         DRM_INFO("Found bochs VGA, ID 0x%x.\n", id);
 165         DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
 166                  size / 1024, addr,
 167                  bochs->ioports ? "ioports" : "mmio",
 168                  ioaddr);
 169
 170         if (bochs->mmio && pdev->revision >= 2) {
 171                 bochs->qext_size = readl(bochs->mmio + 0x600);
 172                 if (bochs->qext_size < 4 || bochs->qext_size > iosize) {
 173                         bochs->qext_size = 0;
 174                         goto noext;
 175                 }
 176                 DRM_DEBUG("Found qemu ext regs, size %ld\n",
 177                           bochs->qext_size);
 178                 bochs_hw_set_native_endian(bochs);
 179         }
 180
 181 noext:
 182         return 0;
 183 }
 184
 185 void bochs_hw_fini(struct drm_device *dev)
 186 {
 187         struct bochs_device *bochs = dev->dev_private;
 188
 189         if (bochs->mmio)
 190                 iounmap(bochs->mmio);
 191         if (bochs->ioports)
 192                 release_region(VBE_DISPI_IOPORT_INDEX, 2);
 193         if (bochs->fb_map)
 194                 iounmap(bochs->fb_map);
 195         pci_release_regions(dev->pdev);
 196         kfree(bochs->edid);
 197 }
 198
 199 void bochs_hw_setmode(struct bochs_device *bochs,
 200                       struct drm_display_mode *mode,
 201                       const struct drm_format_info *format)
 202 {
 203         bochs->xres = mode->hdisplay;
 204         bochs->yres = mode->vdisplay;
 205         bochs->bpp = 32;
 206         bochs->stride = mode->hdisplay * (bochs->bpp / 8);
 207         bochs->yres_virtual = bochs->fb_size / bochs->stride;
 208
 209         DRM_DEBUG_DRIVER("%dx%d @ %d bpp, format %c%c%c%c, vy %d\n",
 210                          bochs->xres, bochs->yres, bochs->bpp,
 211                          (format->format >>  0) & 0xff,
 212                          (format->format >>  8) & 0xff,
 213                          (format->format >> 16) & 0xff,
 214                          (format->format >> 24) & 0xff,
 215                          bochs->yres_virtual);
 216
 217         bochs_vga_writeb(bochs, 0x3c0, 0x20); /* unblank */
 218
 219         bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,      0);
 220         bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP,         bochs->bpp);
 221         bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES,        bochs->xres);
 222         bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES,        bochs->yres);
 223         bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK,        0);
 224         bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH,  bochs->xres);
 225         bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT,
 226                           bochs->yres_virtual);
 227         bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET,    0);
 228         bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET,    0);
 229
 230         bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
 231                           VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);
 232
 233         switch (format->format) {
 234         case DRM_FORMAT_XRGB8888:
 235                 bochs_hw_set_little_endian(bochs);
 236                 break;
 237         case DRM_FORMAT_BGRX8888:
 238                 bochs_hw_set_big_endian(bochs);
 239                 break;
 240         default:
 241                 /* should not happen */
 242                 DRM_ERROR("%s: Huh? Got framebuffer format 0x%x",
 243                           __func__, format->format);
 244                 break;
 245         };
 246 }
 247
 248 void bochs_hw_setbase(struct bochs_device *bochs,
 249                       int x, int y, u64 addr)
 250 {
 251         unsigned long offset = (unsigned long)addr +
 252                 y * bochs->stride +
 253                 x * (bochs->bpp / 8);
 254         int vy = offset / bochs->stride;
 255         int vx = (offset % bochs->stride) * 8 / bochs->bpp;
 256
 257         DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
 258                          x, y, addr, offset, vx, vy);
 259         bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
 260         bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
 261 }