drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31
  32 #include "vcn/vcn_1_0_offset.h"
  33 #include "vcn/vcn_1_0_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "mmhub/mmhub_9_1_offset.h"
  36 #include "mmhub/mmhub_9_1_sh_mask.h"
  37
  38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
  39
  40 #define mmUVD_RBC_XX_IB_REG_CHECK                               0x05ab
  41 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX      1
  42 #define mmUVD_REG_XX_MASK                                                       0x05ac
  43 #define mmUVD_REG_XX_MASK_BASE_IDX                              1
  44
  45 static int vcn_v1_0_stop(struct amdgpu_device *adev);
  46 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  47 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  48 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
  49 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
  50 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
  51
  52 /**
  53  * vcn_v1_0_early_init - set function pointers
  54  *
  55  * @handle: amdgpu_device pointer
  56  *
  57  * Set ring and irq function pointers
  58  */
  59 static int vcn_v1_0_early_init(void *handle)
  60 {
  61         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  62
  63         adev->vcn.num_enc_rings = 2;
  64
  65         vcn_v1_0_set_dec_ring_funcs(adev);
  66         vcn_v1_0_set_enc_ring_funcs(adev);
  67         vcn_v1_0_set_jpeg_ring_funcs(adev);
  68         vcn_v1_0_set_irq_funcs(adev);
  69
  70         return 0;
  71 }
  72
  73 /**
  74  * vcn_v1_0_sw_init - sw init for VCN block
  75  *
  76  * @handle: amdgpu_device pointer
  77  *
  78  * Load firmware and sw initialization
  79  */
  80 static int vcn_v1_0_sw_init(void *handle)
  81 {
  82         struct amdgpu_ring *ring;
  83         int i, r;
  84         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85
  86         /* VCN DEC TRAP */
  87         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
  88         if (r)
  89                 return r;
  90
  91         /* VCN ENC TRAP */
  92         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
  93                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
  94                                         &adev->vcn.irq);
  95                 if (r)
  96                         return r;
  97         }
  98
  99         /* VCN JPEG TRAP */
 100         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
 101         if (r)
 102                 return r;
 103
 104         r = amdgpu_vcn_sw_init(adev);
 105         if (r)
 106                 return r;
 107
 108         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 109                 const struct common_firmware_header *hdr;
 110                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 111                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 112                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 113                 adev->firmware.fw_size +=
 114                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 115                 DRM_INFO("PSP loading VCN firmware\n");
 116         }
 117
 118         r = amdgpu_vcn_resume(adev);
 119         if (r)
 120                 return r;
 121
 122         ring = &adev->vcn.ring_dec;
 123         sprintf(ring->name, "vcn_dec");
 124         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 125         if (r)
 126                 return r;
 127
 128         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 129                 ring = &adev->vcn.ring_enc[i];
 130                 sprintf(ring->name, "vcn_enc%d", i);
 131                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 132                 if (r)
 133                         return r;
 134         }
 135
 136         ring = &adev->vcn.ring_jpeg;
 137         sprintf(ring->name, "vcn_jpeg");
 138         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 139         if (r)
 140                 return r;
 141
 142         return r;
 143 }
 144
 145 /**
 146  * vcn_v1_0_sw_fini - sw fini for VCN block
 147  *
 148  * @handle: amdgpu_device pointer
 149  *
 150  * VCN suspend and free up sw allocation
 151  */
 152 static int vcn_v1_0_sw_fini(void *handle)
 153 {
 154         int r;
 155         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 156
 157         r = amdgpu_vcn_suspend(adev);
 158         if (r)
 159                 return r;
 160
 161         r = amdgpu_vcn_sw_fini(adev);
 162
 163         return r;
 164 }
 165
 166 /**
 167  * vcn_v1_0_hw_init - start and test VCN block
 168  *
 169  * @handle: amdgpu_device pointer
 170  *
 171  * Initialize the hardware, boot up the VCPU and do some testing
 172  */
 173 static int vcn_v1_0_hw_init(void *handle)
 174 {
 175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 176         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 177         int i, r;
 178
 179         r = amdgpu_ring_test_helper(ring);
 180         if (r)
 181                 goto done;
 182
 183         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 184                 ring = &adev->vcn.ring_enc[i];
 185                 ring->sched.ready = true;
 186                 r = amdgpu_ring_test_helper(ring);
 187                 if (r)
 188                         goto done;
 189         }
 190
 191         ring = &adev->vcn.ring_jpeg;
 192         r = amdgpu_ring_test_helper(ring);
 193         if (r)
 194                 goto done;
 195
 196 done:
 197         if (!r)
 198                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 199                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 200
 201         return r;
 202 }
 203
 204 /**
 205  * vcn_v1_0_hw_fini - stop the hardware block
 206  *
 207  * @handle: amdgpu_device pointer
 208  *
 209  * Stop the VCN block, mark ring as not ready any more
 210  */
 211 static int vcn_v1_0_hw_fini(void *handle)
 212 {
 213         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 214         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 215
 216         if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
 217                 vcn_v1_0_stop(adev);
 218
 219         ring->sched.ready = false;
 220
 221         return 0;
 222 }
 223
 224 /**
 225  * vcn_v1_0_suspend - suspend VCN block
 226  *
 227  * @handle: amdgpu_device pointer
 228  *
 229  * HW fini and suspend VCN block
 230  */
 231 static int vcn_v1_0_suspend(void *handle)
 232 {
 233         int r;
 234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 235
 236         r = vcn_v1_0_hw_fini(adev);
 237         if (r)
 238                 return r;
 239
 240         r = amdgpu_vcn_suspend(adev);
 241
 242         return r;
 243 }
 244
 245 /**
 246  * vcn_v1_0_resume - resume VCN block
 247  *
 248  * @handle: amdgpu_device pointer
 249  *
 250  * Resume firmware and hw init VCN block
 251  */
 252 static int vcn_v1_0_resume(void *handle)
 253 {
 254         int r;
 255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 256
 257         r = amdgpu_vcn_resume(adev);
 258         if (r)
 259                 return r;
 260
 261         r = vcn_v1_0_hw_init(adev);
 262
 263         return r;
 264 }
 265
 266 /**
 267  * vcn_v1_0_mc_resume_spg_mode - memory controller programming
 268  *
 269  * @adev: amdgpu_device pointer
 270  *
 271  * Let the VCN memory controller know it's offsets
 272  */
 273 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
 274 {
 275         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 276         uint32_t offset;
 277
 278         /* cache window 0: fw */
 279         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 280                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 281                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 282                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 283                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 284                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 285                 offset = 0;
 286         } else {
 287                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 288                         lower_32_bits(adev->vcn.gpu_addr));
 289                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 290                         upper_32_bits(adev->vcn.gpu_addr));
 291                 offset = size;
 292                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 293                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 294         }
 295
 296         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 297
 298         /* cache window 1: stack */
 299         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 300                      lower_32_bits(adev->vcn.gpu_addr + offset));
 301         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 302                      upper_32_bits(adev->vcn.gpu_addr + offset));
 303         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 304         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 305
 306         /* cache window 2: context */
 307         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 308                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 309         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 310                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 311         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 312         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 313
 314         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 315                         adev->gfx.config.gb_addr_config);
 316         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 317                         adev->gfx.config.gb_addr_config);
 318         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 319                         adev->gfx.config.gb_addr_config);
 320         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 321                         adev->gfx.config.gb_addr_config);
 322         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 323                         adev->gfx.config.gb_addr_config);
 324         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 325                         adev->gfx.config.gb_addr_config);
 326         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 327                         adev->gfx.config.gb_addr_config);
 328         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 329                         adev->gfx.config.gb_addr_config);
 330         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 331                         adev->gfx.config.gb_addr_config);
 332         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 333                         adev->gfx.config.gb_addr_config);
 334         WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
 335                         adev->gfx.config.gb_addr_config);
 336         WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
 337                         adev->gfx.config.gb_addr_config);
 338 }
 339
 340 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
 341 {
 342         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 343         uint32_t offset;
 344
 345         /* cache window 0: fw */
 346         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 347                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 348                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
 349                              0xFFFFFFFF, 0);
 350                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 351                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
 352                              0xFFFFFFFF, 0);
 353                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
 354                              0xFFFFFFFF, 0);
 355                 offset = 0;
 356         } else {
 357                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 358                         lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
 359                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 360                         upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
 361                 offset = size;
 362                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 363                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
 364         }
 365
 366         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
 367
 368         /* cache window 1: stack */
 369         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 370                      lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
 371         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 372                      upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
 373         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
 374                              0xFFFFFFFF, 0);
 375         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
 376                              0xFFFFFFFF, 0);
 377
 378         /* cache window 2: context */
 379         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 380                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 381                              0xFFFFFFFF, 0);
 382         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 383                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 384                              0xFFFFFFFF, 0);
 385         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
 386         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
 387                              0xFFFFFFFF, 0);
 388
 389         /* VCN global tiling registers */
 390         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 391                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 392         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 393                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 394         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 395                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 396         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 397                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 398         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 399                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 400         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 401                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 402         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 403                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 404         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 405                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 406         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 407                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 408         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 409                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 410 }
 411
 412 /**
 413  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
 414  *
 415  * @adev: amdgpu_device pointer
 416  * @sw: enable SW clock gating
 417  *
 418  * Disable clock gating for VCN block
 419  */
 420 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 421 {
 422         uint32_t data;
 423
 424         /* JPEG disable CGC */
 425         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 426
 427         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 428                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 429         else
 430                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 431
 432         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 433         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 434         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 435
 436         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 437         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 438         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 439
 440         /* UVD disable CGC */
 441         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 442         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 443                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 444         else
 445                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 446
 447         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 448         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 449         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 450
 451         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 452         data &= ~(UVD_CGC_GATE__SYS_MASK
 453                 | UVD_CGC_GATE__UDEC_MASK
 454                 | UVD_CGC_GATE__MPEG2_MASK
 455                 | UVD_CGC_GATE__REGS_MASK
 456                 | UVD_CGC_GATE__RBC_MASK
 457                 | UVD_CGC_GATE__LMI_MC_MASK
 458                 | UVD_CGC_GATE__LMI_UMC_MASK
 459                 | UVD_CGC_GATE__IDCT_MASK
 460                 | UVD_CGC_GATE__MPRD_MASK
 461                 | UVD_CGC_GATE__MPC_MASK
 462                 | UVD_CGC_GATE__LBSI_MASK
 463                 | UVD_CGC_GATE__LRBBM_MASK
 464                 | UVD_CGC_GATE__UDEC_RE_MASK
 465                 | UVD_CGC_GATE__UDEC_CM_MASK
 466                 | UVD_CGC_GATE__UDEC_IT_MASK
 467                 | UVD_CGC_GATE__UDEC_DB_MASK
 468                 | UVD_CGC_GATE__UDEC_MP_MASK
 469                 | UVD_CGC_GATE__WCB_MASK
 470                 | UVD_CGC_GATE__VCPU_MASK
 471                 | UVD_CGC_GATE__SCPU_MASK);
 472         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 473
 474         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 475         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 476                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 477                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 478                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 479                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 480                 | UVD_CGC_CTRL__SYS_MODE_MASK
 481                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 482                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 483                 | UVD_CGC_CTRL__REGS_MODE_MASK
 484                 | UVD_CGC_CTRL__RBC_MODE_MASK
 485                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 486                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 487                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 488                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 489                 | UVD_CGC_CTRL__MPC_MODE_MASK
 490                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 491                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 492                 | UVD_CGC_CTRL__WCB_MODE_MASK
 493                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 494                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 495         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 496
 497         /* turn on */
 498         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 499         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 500                 | UVD_SUVD_CGC_GATE__SIT_MASK
 501                 | UVD_SUVD_CGC_GATE__SMP_MASK
 502                 | UVD_SUVD_CGC_GATE__SCM_MASK
 503                 | UVD_SUVD_CGC_GATE__SDB_MASK
 504                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 505                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 506                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 507                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 508                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 509                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 510                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 511                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 512                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 513                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 514                 | UVD_SUVD_CGC_GATE__ENT_MASK
 515                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 516                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 517                 | UVD_SUVD_CGC_GATE__SITE_MASK
 518                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 519                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 520                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 521                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 522                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 523         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 524
 525         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 526         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 527                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 528                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 529                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 530                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 531                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 532                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 533                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 534                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 535                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 536         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 537 }
 538
 539 /**
 540  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
 541  *
 542  * @adev: amdgpu_device pointer
 543  * @sw: enable SW clock gating
 544  *
 545  * Enable clock gating for VCN block
 546  */
 547 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 548 {
 549         uint32_t data = 0;
 550
 551         /* enable JPEG CGC */
 552         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 553         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 554                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 555         else
 556                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 557         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 558         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 559         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 560
 561         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 562         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 563         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 564
 565         /* enable UVD CGC */
 566         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 567         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 568                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 569         else
 570                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 571         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 572         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 573         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 574
 575         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 576         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 577                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 578                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 579                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 580                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 581                 | UVD_CGC_CTRL__SYS_MODE_MASK
 582                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 583                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 584                 | UVD_CGC_CTRL__REGS_MODE_MASK
 585                 | UVD_CGC_CTRL__RBC_MODE_MASK
 586                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 587                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 588                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 589                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 590                 | UVD_CGC_CTRL__MPC_MODE_MASK
 591                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 592                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 593                 | UVD_CGC_CTRL__WCB_MODE_MASK
 594                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 595                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 596         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 597
 598         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 599         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 600                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 601                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 602                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 603                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 604                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 605                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 606                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 607                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 608                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 609         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 610 }
 611
 612 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
 613 {
 614         uint32_t reg_data = 0;
 615
 616         /* disable JPEG CGC */
 617         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 618                 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 619         else
 620                 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 621         reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 622         reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 623         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 624
 625         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 626
 627         /* enable sw clock gating control */
 628         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 629                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 630         else
 631                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 632         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 633         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 634         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 635                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 636                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 637                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 638                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 639                  UVD_CGC_CTRL__SYS_MODE_MASK |
 640                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 641                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 642                  UVD_CGC_CTRL__REGS_MODE_MASK |
 643                  UVD_CGC_CTRL__RBC_MODE_MASK |
 644                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 645                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 646                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 647                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 648                  UVD_CGC_CTRL__MPC_MODE_MASK |
 649                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 650                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 651                  UVD_CGC_CTRL__WCB_MODE_MASK |
 652                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 653                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 654         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 655
 656         /* turn off clock gating */
 657         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 658
 659         /* turn on SUVD clock gating */
 660         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
 661
 662         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 663         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
 664 }
 665
 666 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
 667 {
 668         uint32_t data = 0;
 669         int ret;
 670
 671         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 672                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 673                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 674                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 675                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 676                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 677                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 678                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 679                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 680                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 681                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 682                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 683
 684                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 685                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
 686         } else {
 687                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 688                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 689                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 690                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 691                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 692                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 693                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 694                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 695                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 696                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 697                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 698                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 699                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);
 700         }
 701
 702         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
 703
 704         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 705         data &= ~0x103;
 706         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 707                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
 708
 709         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 710 }
 711
 712 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 713 {
 714         uint32_t data = 0;
 715         int ret;
 716
 717         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 718                 /* Before power off, this indicator has to be turned on */
 719                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 720                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 721                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 722                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 723
 724
 725                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 726                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 727                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 728                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 729                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 730                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 731                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 732                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 733                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 734                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 735                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 736
 737                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 738
 739                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 740                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 741                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 742                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 743                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 744                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 745                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 746                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 747                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 748                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 749                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
 750                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
 751         }
 752 }
 753
 754 /**
 755  * vcn_v1_0_start - start VCN block
 756  *
 757  * @adev: amdgpu_device pointer
 758  *
 759  * Setup and start the VCN block
 760  */
 761 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
 762 {
 763         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 764         uint32_t rb_bufsz, tmp;
 765         uint32_t lmi_swap_cntl;
 766         int i, j, r;
 767
 768         /* disable byte swapping */
 769         lmi_swap_cntl = 0;
 770
 771         vcn_1_0_disable_static_power_gating(adev);
 772
 773         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 774         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 775
 776         /* disable clock gating */
 777         vcn_v1_0_disable_clock_gating(adev);
 778
 779         /* disable interupt */
 780         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 781                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 782
 783         /* initialize VCN memory controller */
 784         tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
 785         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp                |
 786                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 787                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK                       |
 788                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK            |
 789                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 790
 791 #ifdef __BIG_ENDIAN
 792         /* swap (8 in 32) RB and IB */
 793         lmi_swap_cntl = 0xa;
 794 #endif
 795         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 796
 797         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 798         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 799         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 800         WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
 801
 802         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 803                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 804                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 805                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 806                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 807
 808         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 809                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 810                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 811                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 812                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 813
 814         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 815                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 816                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 817                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 818
 819         vcn_v1_0_mc_resume_spg_mode(adev);
 820
 821         WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10);
 822         WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK,
 823                 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3);
 824
 825         /* enable VCPU clock */
 826         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 827
 828         /* boot up the VCPU */
 829         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 830                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 831
 832         /* enable UMC */
 833         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 834                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 835
 836         tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
 837         tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 838         tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 839         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
 840
 841         for (i = 0; i < 10; ++i) {
 842                 uint32_t status;
 843
 844                 for (j = 0; j < 100; ++j) {
 845                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 846                         if (status & UVD_STATUS__IDLE)
 847                                 break;
 848                         mdelay(10);
 849                 }
 850                 r = 0;
 851                 if (status & UVD_STATUS__IDLE)
 852                         break;
 853
 854                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 855                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 856                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 857                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 858                 mdelay(10);
 859                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 860                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 861                 mdelay(10);
 862                 r = -1;
 863         }
 864
 865         if (r) {
 866                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 867                 return r;
 868         }
 869         /* enable master interrupt */
 870         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 871                 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
 872
 873         /* enable system interrupt for JRBC, TODO: move to set interrupt*/
 874         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
 875                 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
 876                 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
 877
 878         /* clear the busy bit of UVD_STATUS */
 879         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
 880         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 881
 882         /* force RBC into idle state */
 883         rb_bufsz = order_base_2(ring->ring_size);
 884         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 885         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 886         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 887         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 888         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 889         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 890
 891         /* set the write pointer delay */
 892         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 893
 894         /* set the wb address */
 895         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 896                         (upper_32_bits(ring->gpu_addr) >> 2));
 897
 898         /* programm the RB_BASE for ring buffer */
 899         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 900                         lower_32_bits(ring->gpu_addr));
 901         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 902                         upper_32_bits(ring->gpu_addr));
 903
 904         /* Initialize the ring buffer's read and write pointers */
 905         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 906
 907         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 908
 909         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 910         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 911                         lower_32_bits(ring->wptr));
 912
 913         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
 914                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 915
 916         ring = &adev->vcn.ring_enc[0];
 917         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 918         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 919         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 920         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 921         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 922
 923         ring = &adev->vcn.ring_enc[1];
 924         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 925         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 926         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 927         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 928         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 929
 930         ring = &adev->vcn.ring_jpeg;
 931         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 932         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
 933                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 934         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
 935         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
 936         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
 937         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
 938         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 939
 940         /* initialize wptr */
 941         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
 942
 943         /* copy patch commands to the jpeg ring */
 944         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
 945                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
 946
 947         return 0;
 948 }
 949
 950 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
 951 {
 952         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 953         uint32_t rb_bufsz, tmp;
 954         uint32_t lmi_swap_cntl;
 955
 956         /* disable byte swapping */
 957         lmi_swap_cntl = 0;
 958
 959         vcn_1_0_enable_static_power_gating(adev);
 960
 961         /* enable dynamic power gating mode */
 962         tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 963         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 964         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 965         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
 966
 967         /* enable clock gating */
 968         vcn_v1_0_clock_gating_dpg_mode(adev, 0);
 969
 970         /* enable VCPU clock */
 971         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 972         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 973         tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
 974         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
 975
 976         /* disable interupt */
 977         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
 978                         0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 979
 980         /* initialize VCN memory controller */
 981         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
 982                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 983                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 984                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 985                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 986                 UVD_LMI_CTRL__REQ_MODE_MASK |
 987                 UVD_LMI_CTRL__CRC_RESET_MASK |
 988                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 989                 0x00100000L, 0xFFFFFFFF, 0);
 990
 991 #ifdef __BIG_ENDIAN
 992         /* swap (8 in 32) RB and IB */
 993         lmi_swap_cntl = 0xa;
 994 #endif
 995         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
 996
 997         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
 998                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
 999
1000         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
1001                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1002                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1003                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1004                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1005
1006         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,
1007                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1008                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1009                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1010                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1011
1012         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
1013                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1014                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1015                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1016
1017         vcn_v1_0_mc_resume_dpg_mode(adev);
1018
1019         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1020         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1021
1022         /* boot up the VCPU */
1023         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1024
1025         /* enable UMC */
1026         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
1027                 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1028                 0xFFFFFFFF, 0);
1029
1030         /* enable master interrupt */
1031         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
1032                         UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1033
1034         vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1035         /* setup mmUVD_LMI_CTRL */
1036         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
1037                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1038                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1039                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1040                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1041                 UVD_LMI_CTRL__REQ_MODE_MASK |
1042                 UVD_LMI_CTRL__CRC_RESET_MASK |
1043                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1044                 0x00100000L, 0xFFFFFFFF, 1);
1045
1046         tmp = adev->gfx.config.gb_addr_config;
1047         /* setup VCN global tiling registers */
1048         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1049         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1050
1051         /* enable System Interrupt for JRBC */
1052         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,
1053                                                                         UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1054
1055         /* force RBC into idle state */
1056         rb_bufsz = order_base_2(ring->ring_size);
1057         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1058         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1059         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1060         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1061         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1062         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1063
1064         /* set the write pointer delay */
1065         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1066
1067         /* set the wb address */
1068         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1069                                                                 (upper_32_bits(ring->gpu_addr) >> 2));
1070
1071         /* programm the RB_BASE for ring buffer */
1072         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1073                                                                 lower_32_bits(ring->gpu_addr));
1074         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1075                                                                 upper_32_bits(ring->gpu_addr));
1076
1077         /* Initialize the ring buffer's read and write pointers */
1078         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1079
1080         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1081
1082         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1083         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1084                                                                 lower_32_bits(ring->wptr));
1085
1086         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1087                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1088
1089         /* initialize wptr */
1090         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1091
1092         /* copy patch commands to the jpeg ring */
1093         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
1094                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
1095
1096         return 0;
1097 }
1098
1099 static int vcn_v1_0_start(struct amdgpu_device *adev)
1100 {
1101         int r;
1102
1103         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1104                 r = vcn_v1_0_start_dpg_mode(adev);
1105         else
1106                 r = vcn_v1_0_start_spg_mode(adev);
1107         return r;
1108 }
1109
1110 /**
1111  * vcn_v1_0_stop - stop VCN block
1112  *
1113  * @adev: amdgpu_device pointer
1114  *
1115  * stop the VCN block
1116  */
1117 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1118 {
1119         int ret_code, tmp;
1120
1121         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
1122
1123         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1124                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1125                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1126                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1127         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1128
1129         /* put VCPU into reset */
1130         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1131                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1132                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1133
1134         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1135                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1136         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1137
1138         /* disable VCPU clock */
1139         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1140                 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1141
1142         /* reset LMI UMC/LMI */
1143         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1144                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1145                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1146
1147         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1148                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1149                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1150
1151         WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1152
1153         vcn_v1_0_enable_clock_gating(adev);
1154         vcn_1_0_enable_static_power_gating(adev);
1155         return 0;
1156 }
1157
1158 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1159 {
1160         int ret_code = 0;
1161
1162         /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1163         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1164                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1165                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1166
1167         if (!ret_code) {
1168                 int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1169                 /* wait for read ptr to be equal to write ptr */
1170                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1171
1172                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1173                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1174                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1175         }
1176
1177         /* disable dynamic power gating mode */
1178         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1179                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1180
1181         return 0;
1182 }
1183
1184 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1185 {
1186         int r;
1187
1188         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1189                 r = vcn_v1_0_stop_dpg_mode(adev);
1190         else
1191                 r = vcn_v1_0_stop_spg_mode(adev);
1192
1193         return r;
1194 }
1195
1196 static bool vcn_v1_0_is_idle(void *handle)
1197 {
1198         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1199
1200         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1201 }
1202
1203 static int vcn_v1_0_wait_for_idle(void *handle)
1204 {
1205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206         int ret = 0;
1207
1208         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1209                 UVD_STATUS__IDLE, ret);
1210
1211         return ret;
1212 }
1213
1214 static int vcn_v1_0_set_clockgating_state(void *handle,
1215                                           enum amd_clockgating_state state)
1216 {
1217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1219
1220         if (enable) {
1221                 /* wait for STATUS to clear */
1222                 if (vcn_v1_0_is_idle(handle))
1223                         return -EBUSY;
1224                 vcn_v1_0_enable_clock_gating(adev);
1225         } else {
1226                 /* disable HW gating and enable Sw gating */
1227                 vcn_v1_0_disable_clock_gating(adev);
1228         }
1229         return 0;
1230 }
1231
1232 /**
1233  * vcn_v1_0_dec_ring_get_rptr - get read pointer
1234  *
1235  * @ring: amdgpu_ring pointer
1236  *
1237  * Returns the current hardware read pointer
1238  */
1239 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1240 {
1241         struct amdgpu_device *adev = ring->adev;
1242
1243         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1244 }
1245
1246 /**
1247  * vcn_v1_0_dec_ring_get_wptr - get write pointer
1248  *
1249  * @ring: amdgpu_ring pointer
1250  *
1251  * Returns the current hardware write pointer
1252  */
1253 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1254 {
1255         struct amdgpu_device *adev = ring->adev;
1256
1257         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1258 }
1259
1260 /**
1261  * vcn_v1_0_dec_ring_set_wptr - set write pointer
1262  *
1263  * @ring: amdgpu_ring pointer
1264  *
1265  * Commits the write pointer to the hardware
1266  */
1267 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1268 {
1269         struct amdgpu_device *adev = ring->adev;
1270
1271         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1272                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1273                         lower_32_bits(ring->wptr) | 0x80000000);
1274
1275         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1276 }
1277
1278 /**
1279  * vcn_v1_0_dec_ring_insert_start - insert a start command
1280  *
1281  * @ring: amdgpu_ring pointer
1282  *
1283  * Write a start command to the ring.
1284  */
1285 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1286 {
1287         struct amdgpu_device *adev = ring->adev;
1288
1289         amdgpu_ring_write(ring,
1290                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1291         amdgpu_ring_write(ring, 0);
1292         amdgpu_ring_write(ring,
1293                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1294         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1295 }
1296
1297 /**
1298  * vcn_v1_0_dec_ring_insert_end - insert a end command
1299  *
1300  * @ring: amdgpu_ring pointer
1301  *
1302  * Write a end command to the ring.
1303  */
1304 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1305 {
1306         struct amdgpu_device *adev = ring->adev;
1307
1308         amdgpu_ring_write(ring,
1309                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1310         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1311 }
1312
1313 /**
1314  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1315  *
1316  * @ring: amdgpu_ring pointer
1317  * @fence: fence to emit
1318  *
1319  * Write a fence and a trap command to the ring.
1320  */
1321 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1322                                      unsigned flags)
1323 {
1324         struct amdgpu_device *adev = ring->adev;
1325
1326         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1327
1328         amdgpu_ring_write(ring,
1329                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1330         amdgpu_ring_write(ring, seq);
1331         amdgpu_ring_write(ring,
1332                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1333         amdgpu_ring_write(ring, addr & 0xffffffff);
1334         amdgpu_ring_write(ring,
1335                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1336         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1337         amdgpu_ring_write(ring,
1338                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1339         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1340
1341         amdgpu_ring_write(ring,
1342                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1343         amdgpu_ring_write(ring, 0);
1344         amdgpu_ring_write(ring,
1345                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1346         amdgpu_ring_write(ring, 0);
1347         amdgpu_ring_write(ring,
1348                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1349         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1350 }
1351
1352 /**
1353  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1354  *
1355  * @ring: amdgpu_ring pointer
1356  * @ib: indirect buffer to execute
1357  *
1358  * Write ring commands to execute the indirect buffer
1359  */
1360 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1361                                         struct amdgpu_job *job,
1362                                         struct amdgpu_ib *ib,
1363                                         bool ctx_switch)
1364 {
1365         struct amdgpu_device *adev = ring->adev;
1366         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1367
1368         amdgpu_ring_write(ring,
1369                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1370         amdgpu_ring_write(ring, vmid);
1371
1372         amdgpu_ring_write(ring,
1373                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1374         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1375         amdgpu_ring_write(ring,
1376                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1377         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1378         amdgpu_ring_write(ring,
1379                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1380         amdgpu_ring_write(ring, ib->length_dw);
1381 }
1382
1383 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1384                                             uint32_t reg, uint32_t val,
1385                                             uint32_t mask)
1386 {
1387         struct amdgpu_device *adev = ring->adev;
1388
1389         amdgpu_ring_write(ring,
1390                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1391         amdgpu_ring_write(ring, reg << 2);
1392         amdgpu_ring_write(ring,
1393                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1394         amdgpu_ring_write(ring, val);
1395         amdgpu_ring_write(ring,
1396                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1397         amdgpu_ring_write(ring, mask);
1398         amdgpu_ring_write(ring,
1399                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1400         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1401 }
1402
1403 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1404                                             unsigned vmid, uint64_t pd_addr)
1405 {
1406         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1407         uint32_t data0, data1, mask;
1408
1409         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1410
1411         /* wait for register write */
1412         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1413         data1 = lower_32_bits(pd_addr);
1414         mask = 0xffffffff;
1415         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1416 }
1417
1418 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1419                                         uint32_t reg, uint32_t val)
1420 {
1421         struct amdgpu_device *adev = ring->adev;
1422
1423         amdgpu_ring_write(ring,
1424                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1425         amdgpu_ring_write(ring, reg << 2);
1426         amdgpu_ring_write(ring,
1427                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1428         amdgpu_ring_write(ring, val);
1429         amdgpu_ring_write(ring,
1430                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1431         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1432 }
1433
1434 /**
1435  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1436  *
1437  * @ring: amdgpu_ring pointer
1438  *
1439  * Returns the current hardware enc read pointer
1440  */
1441 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1442 {
1443         struct amdgpu_device *adev = ring->adev;
1444
1445         if (ring == &adev->vcn.ring_enc[0])
1446                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1447         else
1448                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1449 }
1450
1451  /**
1452  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1453  *
1454  * @ring: amdgpu_ring pointer
1455  *
1456  * Returns the current hardware enc write pointer
1457  */
1458 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1459 {
1460         struct amdgpu_device *adev = ring->adev;
1461
1462         if (ring == &adev->vcn.ring_enc[0])
1463                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1464         else
1465                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1466 }
1467
1468  /**
1469  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1470  *
1471  * @ring: amdgpu_ring pointer
1472  *
1473  * Commits the enc write pointer to the hardware
1474  */
1475 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1476 {
1477         struct amdgpu_device *adev = ring->adev;
1478
1479         if (ring == &adev->vcn.ring_enc[0])
1480                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1481                         lower_32_bits(ring->wptr));
1482         else
1483                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1484                         lower_32_bits(ring->wptr));
1485 }
1486
1487 /**
1488  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1489  *
1490  * @ring: amdgpu_ring pointer
1491  * @fence: fence to emit
1492  *
1493  * Write enc a fence and a trap command to the ring.
1494  */
1495 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1496                         u64 seq, unsigned flags)
1497 {
1498         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1499
1500         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1501         amdgpu_ring_write(ring, addr);
1502         amdgpu_ring_write(ring, upper_32_bits(addr));
1503         amdgpu_ring_write(ring, seq);
1504         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1505 }
1506
1507 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1508 {
1509         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1510 }
1511
1512 /**
1513  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1514  *
1515  * @ring: amdgpu_ring pointer
1516  * @ib: indirect buffer to execute
1517  *
1518  * Write enc ring commands to execute the indirect buffer
1519  */
1520 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1521                                         struct amdgpu_job *job,
1522                                         struct amdgpu_ib *ib,
1523                                         bool ctx_switch)
1524 {
1525         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1526
1527         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1528         amdgpu_ring_write(ring, vmid);
1529         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1530         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1531         amdgpu_ring_write(ring, ib->length_dw);
1532 }
1533
1534 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1535                                             uint32_t reg, uint32_t val,
1536                                             uint32_t mask)
1537 {
1538         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1539         amdgpu_ring_write(ring, reg << 2);
1540         amdgpu_ring_write(ring, mask);
1541         amdgpu_ring_write(ring, val);
1542 }
1543
1544 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1545                                             unsigned int vmid, uint64_t pd_addr)
1546 {
1547         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1548
1549         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1550
1551         /* wait for reg writes */
1552         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1553                                         lower_32_bits(pd_addr), 0xffffffff);
1554 }
1555
1556 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1557                                         uint32_t reg, uint32_t val)
1558 {
1559         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1560         amdgpu_ring_write(ring, reg << 2);
1561         amdgpu_ring_write(ring, val);
1562 }
1563
1564
1565 /**
1566  * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
1567  *
1568  * @ring: amdgpu_ring pointer
1569  *
1570  * Returns the current hardware read pointer
1571  */
1572 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1573 {
1574         struct amdgpu_device *adev = ring->adev;
1575
1576         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1577 }
1578
1579 /**
1580  * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
1581  *
1582  * @ring: amdgpu_ring pointer
1583  *
1584  * Returns the current hardware write pointer
1585  */
1586 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1587 {
1588         struct amdgpu_device *adev = ring->adev;
1589
1590         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1591 }
1592
1593 /**
1594  * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
1595  *
1596  * @ring: amdgpu_ring pointer
1597  *
1598  * Commits the write pointer to the hardware
1599  */
1600 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1601 {
1602         struct amdgpu_device *adev = ring->adev;
1603
1604         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1605 }
1606
1607 /**
1608  * vcn_v1_0_jpeg_ring_insert_start - insert a start command
1609  *
1610  * @ring: amdgpu_ring pointer
1611  *
1612  * Write a start command to the ring.
1613  */
1614 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1615 {
1616         struct amdgpu_device *adev = ring->adev;
1617
1618         amdgpu_ring_write(ring,
1619                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1620         amdgpu_ring_write(ring, 0x68e04);
1621
1622         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1623         amdgpu_ring_write(ring, 0x80010000);
1624 }
1625
1626 /**
1627  * vcn_v1_0_jpeg_ring_insert_end - insert a end command
1628  *
1629  * @ring: amdgpu_ring pointer
1630  *
1631  * Write a end command to the ring.
1632  */
1633 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1634 {
1635         struct amdgpu_device *adev = ring->adev;
1636
1637         amdgpu_ring_write(ring,
1638                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1639         amdgpu_ring_write(ring, 0x68e04);
1640
1641         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1642         amdgpu_ring_write(ring, 0x00010000);
1643 }
1644
1645 /**
1646  * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
1647  *
1648  * @ring: amdgpu_ring pointer
1649  * @fence: fence to emit
1650  *
1651  * Write a fence and a trap command to the ring.
1652  */
1653 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1654                                      unsigned flags)
1655 {
1656         struct amdgpu_device *adev = ring->adev;
1657
1658         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1659
1660         amdgpu_ring_write(ring,
1661                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
1662         amdgpu_ring_write(ring, seq);
1663
1664         amdgpu_ring_write(ring,
1665                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
1666         amdgpu_ring_write(ring, seq);
1667
1668         amdgpu_ring_write(ring,
1669                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1670         amdgpu_ring_write(ring, lower_32_bits(addr));
1671
1672         amdgpu_ring_write(ring,
1673                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1674         amdgpu_ring_write(ring, upper_32_bits(addr));
1675
1676         amdgpu_ring_write(ring,
1677                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
1678         amdgpu_ring_write(ring, 0x8);
1679
1680         amdgpu_ring_write(ring,
1681                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
1682         amdgpu_ring_write(ring, 0);
1683
1684         amdgpu_ring_write(ring,
1685                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1686         amdgpu_ring_write(ring, 0x01400200);
1687
1688         amdgpu_ring_write(ring,
1689                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1690         amdgpu_ring_write(ring, seq);
1691
1692         amdgpu_ring_write(ring,
1693                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1694         amdgpu_ring_write(ring, lower_32_bits(addr));
1695
1696         amdgpu_ring_write(ring,
1697                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1698         amdgpu_ring_write(ring, upper_32_bits(addr));
1699
1700         amdgpu_ring_write(ring,
1701                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
1702         amdgpu_ring_write(ring, 0xffffffff);
1703
1704         amdgpu_ring_write(ring,
1705                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1706         amdgpu_ring_write(ring, 0x3fbc);
1707
1708         amdgpu_ring_write(ring,
1709                 PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1710         amdgpu_ring_write(ring, 0x1);
1711
1712         /* emit trap */
1713         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
1714         amdgpu_ring_write(ring, 0);
1715 }
1716
1717 /**
1718  * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
1719  *
1720  * @ring: amdgpu_ring pointer
1721  * @ib: indirect buffer to execute
1722  *
1723  * Write ring commands to execute the indirect buffer.
1724  */
1725 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1726                                         struct amdgpu_job *job,
1727                                         struct amdgpu_ib *ib,
1728                                         bool ctx_switch)
1729 {
1730         struct amdgpu_device *adev = ring->adev;
1731         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1732
1733         amdgpu_ring_write(ring,
1734                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
1735         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1736
1737         amdgpu_ring_write(ring,
1738                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
1739         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1740
1741         amdgpu_ring_write(ring,
1742                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1743         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1744
1745         amdgpu_ring_write(ring,
1746                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1747         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1748
1749         amdgpu_ring_write(ring,
1750                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
1751         amdgpu_ring_write(ring, ib->length_dw);
1752
1753         amdgpu_ring_write(ring,
1754                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1755         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
1756
1757         amdgpu_ring_write(ring,
1758                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1759         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
1760
1761         amdgpu_ring_write(ring,
1762                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
1763         amdgpu_ring_write(ring, 0);
1764
1765         amdgpu_ring_write(ring,
1766                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1767         amdgpu_ring_write(ring, 0x01400200);
1768
1769         amdgpu_ring_write(ring,
1770                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1771         amdgpu_ring_write(ring, 0x2);
1772
1773         amdgpu_ring_write(ring,
1774                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
1775         amdgpu_ring_write(ring, 0x2);
1776 }
1777
1778 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
1779                                             uint32_t reg, uint32_t val,
1780                                             uint32_t mask)
1781 {
1782         struct amdgpu_device *adev = ring->adev;
1783         uint32_t reg_offset = (reg << 2);
1784
1785         amdgpu_ring_write(ring,
1786                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1787         amdgpu_ring_write(ring, 0x01400200);
1788
1789         amdgpu_ring_write(ring,
1790                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1791         amdgpu_ring_write(ring, val);
1792
1793         amdgpu_ring_write(ring,
1794                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1795         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1796                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1797                 amdgpu_ring_write(ring, 0);
1798                 amdgpu_ring_write(ring,
1799                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
1800         } else {
1801                 amdgpu_ring_write(ring, reg_offset);
1802                 amdgpu_ring_write(ring,
1803                         PACKETJ(0, 0, 0, PACKETJ_TYPE3));
1804         }
1805         amdgpu_ring_write(ring, mask);
1806 }
1807
1808 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
1809                 unsigned vmid, uint64_t pd_addr)
1810 {
1811         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1812         uint32_t data0, data1, mask;
1813
1814         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1815
1816         /* wait for register write */
1817         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1818         data1 = lower_32_bits(pd_addr);
1819         mask = 0xffffffff;
1820         vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
1821 }
1822
1823 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
1824                                         uint32_t reg, uint32_t val)
1825 {
1826         struct amdgpu_device *adev = ring->adev;
1827         uint32_t reg_offset = (reg << 2);
1828
1829         amdgpu_ring_write(ring,
1830                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1831         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1832                         ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1833                 amdgpu_ring_write(ring, 0);
1834                 amdgpu_ring_write(ring,
1835                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
1836         } else {
1837                 amdgpu_ring_write(ring, reg_offset);
1838                 amdgpu_ring_write(ring,
1839                         PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1840         }
1841         amdgpu_ring_write(ring, val);
1842 }
1843
1844 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
1845 {
1846         int i;
1847
1848         WARN_ON(ring->wptr % 2 || count % 2);
1849
1850         for (i = 0; i < count / 2; i++) {
1851                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
1852                 amdgpu_ring_write(ring, 0);
1853         }
1854 }
1855
1856 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
1857 {
1858         struct amdgpu_device *adev = ring->adev;
1859         ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1860         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1861                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1862                 ring->ring[(*ptr)++] = 0;
1863                 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
1864         } else {
1865                 ring->ring[(*ptr)++] = reg_offset;
1866                 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
1867         }
1868         ring->ring[(*ptr)++] = val;
1869 }
1870
1871 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
1872 {
1873         struct amdgpu_device *adev = ring->adev;
1874
1875         uint32_t reg, reg_offset, val, mask, i;
1876
1877         // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
1878         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
1879         reg_offset = (reg << 2);
1880         val = lower_32_bits(ring->gpu_addr);
1881         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1882
1883         // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
1884         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
1885         reg_offset = (reg << 2);
1886         val = upper_32_bits(ring->gpu_addr);
1887         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1888
1889         // 3rd to 5th: issue MEM_READ commands
1890         for (i = 0; i <= 2; i++) {
1891                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
1892                 ring->ring[ptr++] = 0;
1893         }
1894
1895         // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
1896         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1897         reg_offset = (reg << 2);
1898         val = 0x13;
1899         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1900
1901         // 7th: program mmUVD_JRBC_RB_REF_DATA
1902         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
1903         reg_offset = (reg << 2);
1904         val = 0x1;
1905         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1906
1907         // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
1908         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1909         reg_offset = (reg << 2);
1910         val = 0x1;
1911         mask = 0x1;
1912
1913         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
1914         ring->ring[ptr++] = 0x01400200;
1915         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
1916         ring->ring[ptr++] = val;
1917         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1918         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1919                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1920                 ring->ring[ptr++] = 0;
1921                 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
1922         } else {
1923                 ring->ring[ptr++] = reg_offset;
1924                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
1925         }
1926         ring->ring[ptr++] = mask;
1927
1928         //9th to 21st: insert no-op
1929         for (i = 0; i <= 12; i++) {
1930                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
1931                 ring->ring[ptr++] = 0;
1932         }
1933
1934         //22nd: reset mmUVD_JRBC_RB_RPTR
1935         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
1936         reg_offset = (reg << 2);
1937         val = 0;
1938         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1939
1940         //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
1941         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1942         reg_offset = (reg << 2);
1943         val = 0x12;
1944         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1945 }
1946
1947 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1948                                         struct amdgpu_irq_src *source,
1949                                         unsigned type,
1950                                         enum amdgpu_interrupt_state state)
1951 {
1952         return 0;
1953 }
1954
1955 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1956                                       struct amdgpu_irq_src *source,
1957                                       struct amdgpu_iv_entry *entry)
1958 {
1959         DRM_DEBUG("IH: VCN TRAP\n");
1960
1961         switch (entry->src_id) {
1962         case 124:
1963                 amdgpu_fence_process(&adev->vcn.ring_dec);
1964                 break;
1965         case 119:
1966                 amdgpu_fence_process(&adev->vcn.ring_enc[0]);
1967                 break;
1968         case 120:
1969                 amdgpu_fence_process(&adev->vcn.ring_enc[1]);
1970                 break;
1971         case 126:
1972                 amdgpu_fence_process(&adev->vcn.ring_jpeg);
1973                 break;
1974         default:
1975                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1976                           entry->src_id, entry->src_data[0]);
1977                 break;
1978         }
1979
1980         return 0;
1981 }
1982
1983 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1984 {
1985         struct amdgpu_device *adev = ring->adev;
1986         int i;
1987
1988         WARN_ON(ring->wptr % 2 || count % 2);
1989
1990         for (i = 0; i < count / 2; i++) {
1991                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1992                 amdgpu_ring_write(ring, 0);
1993         }
1994 }
1995
1996 static int vcn_v1_0_set_powergating_state(void *handle,
1997                                           enum amd_powergating_state state)
1998 {
1999         /* This doesn't actually powergate the VCN block.
2000          * That's done in the dpm code via the SMC.  This
2001          * just re-inits the block as necessary.  The actual
2002          * gating still happens in the dpm code.  We should
2003          * revisit this when there is a cleaner line between
2004          * the smc and the hw blocks
2005          */
2006         int ret;
2007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2008
2009         if(state == adev->vcn.cur_state)
2010                 return 0;
2011
2012         if (state == AMD_PG_STATE_GATE)
2013                 ret = vcn_v1_0_stop(adev);
2014         else
2015                 ret = vcn_v1_0_start(adev);
2016
2017         if(!ret)
2018                 adev->vcn.cur_state = state;
2019         return ret;
2020 }
2021
2022 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
2023         .name = "vcn_v1_0",
2024         .early_init = vcn_v1_0_early_init,
2025         .late_init = NULL,
2026         .sw_init = vcn_v1_0_sw_init,
2027         .sw_fini = vcn_v1_0_sw_fini,
2028         .hw_init = vcn_v1_0_hw_init,
2029         .hw_fini = vcn_v1_0_hw_fini,
2030         .suspend = vcn_v1_0_suspend,
2031         .resume = vcn_v1_0_resume,
2032         .is_idle = vcn_v1_0_is_idle,
2033         .wait_for_idle = vcn_v1_0_wait_for_idle,
2034         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
2035         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
2036         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
2037         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
2038         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
2039         .set_powergating_state = vcn_v1_0_set_powergating_state,
2040 };
2041
2042 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2043         .type = AMDGPU_RING_TYPE_VCN_DEC,
2044         .align_mask = 0xf,
2045         .support_64bit_ptrs = false,
2046         .vmhub = AMDGPU_MMHUB,
2047         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
2048         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
2049         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2050         .emit_frame_size =
2051                 6 + 6 + /* hdp invalidate / flush */
2052                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2053                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2054                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
2055                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
2056                 6,
2057         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
2058         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
2059         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
2060         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
2061         .test_ring = amdgpu_vcn_dec_ring_test_ring,
2062         .test_ib = amdgpu_vcn_dec_ring_test_ib,
2063         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
2064         .insert_start = vcn_v1_0_dec_ring_insert_start,
2065         .insert_end = vcn_v1_0_dec_ring_insert_end,
2066         .pad_ib = amdgpu_ring_generic_pad_ib,
2067         .begin_use = amdgpu_vcn_ring_begin_use,
2068         .end_use = amdgpu_vcn_ring_end_use,
2069         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
2070         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
2071         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2072 };
2073
2074 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
2075         .type = AMDGPU_RING_TYPE_VCN_ENC,
2076         .align_mask = 0x3f,
2077         .nop = VCN_ENC_CMD_NO_OP,
2078         .support_64bit_ptrs = false,
2079         .vmhub = AMDGPU_MMHUB,
2080         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
2081         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
2082         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
2083         .emit_frame_size =
2084                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2085                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2086                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
2087                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
2088                 1, /* vcn_v1_0_enc_ring_insert_end */
2089         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
2090         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
2091         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
2092         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
2093         .test_ring = amdgpu_vcn_enc_ring_test_ring,
2094         .test_ib = amdgpu_vcn_enc_ring_test_ib,
2095         .insert_nop = amdgpu_ring_insert_nop,
2096         .insert_end = vcn_v1_0_enc_ring_insert_end,
2097         .pad_ib = amdgpu_ring_generic_pad_ib,
2098         .begin_use = amdgpu_vcn_ring_begin_use,
2099         .end_use = amdgpu_vcn_ring_end_use,
2100         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
2101         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
2102         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2103 };
2104
2105 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
2106         .type = AMDGPU_RING_TYPE_VCN_JPEG,
2107         .align_mask = 0xf,
2108         .nop = PACKET0(0x81ff, 0),
2109         .support_64bit_ptrs = false,
2110         .vmhub = AMDGPU_MMHUB,
2111         .extra_dw = 64,
2112         .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
2113         .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
2114         .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
2115         .emit_frame_size =
2116                 6 + 6 + /* hdp invalidate / flush */
2117                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2118                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2119                 8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */
2120                 26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */
2121                 6,
2122         .emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */
2123         .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
2124         .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
2125         .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
2126         .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
2127         .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
2128         .insert_nop = vcn_v1_0_jpeg_ring_nop,
2129         .insert_start = vcn_v1_0_jpeg_ring_insert_start,
2130         .insert_end = vcn_v1_0_jpeg_ring_insert_end,
2131         .pad_ib = amdgpu_ring_generic_pad_ib,
2132         .begin_use = amdgpu_vcn_ring_begin_use,
2133         .end_use = amdgpu_vcn_ring_end_use,
2134         .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
2135         .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
2136         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2137 };
2138
2139 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2140 {
2141         adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
2142         DRM_INFO("VCN decode is enabled in VM mode\n");
2143 }
2144
2145 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2146 {
2147         int i;
2148
2149         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2150                 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
2151
2152         DRM_INFO("VCN encode is enabled in VM mode\n");
2153 }
2154
2155 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
2156 {
2157         adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
2158         DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
2159 }
2160
2161 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
2162         .set = vcn_v1_0_set_interrupt_state,
2163         .process = vcn_v1_0_process_interrupt,
2164 };
2165
2166 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
2167 {
2168         adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
2169         adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
2170 }
2171
2172 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
2173 {
2174                 .type = AMD_IP_BLOCK_TYPE_VCN,
2175                 .major = 1,
2176                 .minor = 0,
2177                 .rev = 0,
2178                 .funcs = &vcn_v1_0_ip_funcs,
2179 };