drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/fdtable.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_amdkfd.h"
  30 #include "amdgpu_ucode.h"
  31 #include "gfx_v8_0.h"
  32 #include "gca/gfx_8_0_sh_mask.h"
  33 #include "gca/gfx_8_0_d.h"
  34 #include "gca/gfx_8_0_enum.h"
  35 #include "oss/oss_3_0_sh_mask.h"
  36 #include "oss/oss_3_0_d.h"
  37 #include "gmc/gmc_8_1_sh_mask.h"
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "vi_structs.h"
  40 #include "vid.h"
  41
  42 enum hqd_dequeue_request_type {
  43         NO_ACTION = 0,
  44         DRAIN_PIPE,
  45         RESET_WAVES
  46 };
  47
  48 /*
  49  * Register access functions
  50  */
  51
  52 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  53                 uint32_t sh_mem_config,
  54                 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
  55                 uint32_t sh_mem_bases);
  56 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  57                 unsigned int vmid);
  58 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
  59 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
  60                         uint32_t queue_id, uint32_t __user *wptr,
  61                         uint32_t wptr_shift, uint32_t wptr_mask,
  62                         struct mm_struct *mm);
  63 static int kgd_hqd_dump(struct kgd_dev *kgd,
  64                         uint32_t pipe_id, uint32_t queue_id,
  65                         uint32_t (**dump)[2], uint32_t *n_regs);
  66 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
  67                              uint32_t __user *wptr, struct mm_struct *mm);
  68 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
  69                              uint32_t engine_id, uint32_t queue_id,
  70                              uint32_t (**dump)[2], uint32_t *n_regs);
  71 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
  72                 uint32_t pipe_id, uint32_t queue_id);
  73 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
  74 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
  75                                 enum kfd_preempt_type reset_type,
  76                                 unsigned int utimeout, uint32_t pipe_id,
  77                                 uint32_t queue_id);
  78 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
  79                                 unsigned int utimeout);
  80 static int kgd_address_watch_disable(struct kgd_dev *kgd);
  81 static int kgd_address_watch_execute(struct kgd_dev *kgd,
  82                                         unsigned int watch_point_id,
  83                                         uint32_t cntl_val,
  84                                         uint32_t addr_hi,
  85                                         uint32_t addr_lo);
  86 static int kgd_wave_control_execute(struct kgd_dev *kgd,
  87                                         uint32_t gfx_index_val,
  88                                         uint32_t sq_cmd);
  89 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
  90                                         unsigned int watch_point_id,
  91                                         unsigned int reg_offset);
  92
  93 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
  94                 uint8_t vmid);
  95 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
  96                 uint8_t vmid);
  97 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
  98 static void set_scratch_backing_va(struct kgd_dev *kgd,
  99                                         uint64_t va, uint32_t vmid);
 100 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 101                 uint64_t page_table_base);
 102 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 103 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 104
 105 /* Because of REG_GET_FIELD() being used, we put this function in the
 106  * asic specific file.
 107  */
 108 static int get_tile_config(struct kgd_dev *kgd,
 109                 struct tile_config *config)
 110 {
 111         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 112
 113         config->gb_addr_config = adev->gfx.config.gb_addr_config;
 114         config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 115                                 MC_ARB_RAMCFG, NOOFBANK);
 116         config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
 117                                 MC_ARB_RAMCFG, NOOFRANKS);
 118
 119         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
 120         config->num_tile_configs =
 121                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 122         config->macro_tile_config_ptr =
 123                         adev->gfx.config.macrotile_mode_array;
 124         config->num_macro_tile_configs =
 125                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 126
 127         return 0;
 128 }
 129
 130 static const struct kfd2kgd_calls kfd2kgd = {
 131         .program_sh_mem_settings = kgd_program_sh_mem_settings,
 132         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
 133         .init_interrupts = kgd_init_interrupts,
 134         .hqd_load = kgd_hqd_load,
 135         .hqd_sdma_load = kgd_hqd_sdma_load,
 136         .hqd_dump = kgd_hqd_dump,
 137         .hqd_sdma_dump = kgd_hqd_sdma_dump,
 138         .hqd_is_occupied = kgd_hqd_is_occupied,
 139         .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
 140         .hqd_destroy = kgd_hqd_destroy,
 141         .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
 142         .address_watch_disable = kgd_address_watch_disable,
 143         .address_watch_execute = kgd_address_watch_execute,
 144         .wave_control_execute = kgd_wave_control_execute,
 145         .address_watch_get_offset = kgd_address_watch_get_offset,
 146         .get_atc_vmid_pasid_mapping_pasid =
 147                         get_atc_vmid_pasid_mapping_pasid,
 148         .get_atc_vmid_pasid_mapping_valid =
 149                         get_atc_vmid_pasid_mapping_valid,
 150         .get_fw_version = get_fw_version,
 151         .set_scratch_backing_va = set_scratch_backing_va,
 152         .get_tile_config = get_tile_config,
 153         .set_vm_context_page_table_base = set_vm_context_page_table_base,
 154         .invalidate_tlbs = invalidate_tlbs,
 155         .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
 156 };
 157
 158 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
 159 {
 160         return (struct kfd2kgd_calls *)&kfd2kgd;
 161 }
 162
 163 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 164 {
 165         return (struct amdgpu_device *)kgd;
 166 }
 167
 168 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 169                         uint32_t queue, uint32_t vmid)
 170 {
 171         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 172         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 173
 174         mutex_lock(&adev->srbm_mutex);
 175         WREG32(mmSRBM_GFX_CNTL, value);
 176 }
 177
 178 static void unlock_srbm(struct kgd_dev *kgd)
 179 {
 180         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 181
 182         WREG32(mmSRBM_GFX_CNTL, 0);
 183         mutex_unlock(&adev->srbm_mutex);
 184 }
 185
 186 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 187                                 uint32_t queue_id)
 188 {
 189         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 190
 191         uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 192         uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 193
 194         lock_srbm(kgd, mec, pipe, queue_id, 0);
 195 }
 196
 197 static void release_queue(struct kgd_dev *kgd)
 198 {
 199         unlock_srbm(kgd);
 200 }
 201
 202 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 203                                         uint32_t sh_mem_config,
 204                                         uint32_t sh_mem_ape1_base,
 205                                         uint32_t sh_mem_ape1_limit,
 206                                         uint32_t sh_mem_bases)
 207 {
 208         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 209
 210         lock_srbm(kgd, 0, 0, 0, vmid);
 211
 212         WREG32(mmSH_MEM_CONFIG, sh_mem_config);
 213         WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
 214         WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 215         WREG32(mmSH_MEM_BASES, sh_mem_bases);
 216
 217         unlock_srbm(kgd);
 218 }
 219
 220 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 221                                         unsigned int vmid)
 222 {
 223         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 224
 225         /*
 226          * We have to assume that there is no outstanding mapping.
 227          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
 228          * a mapping is in progress or because a mapping finished
 229          * and the SW cleared it.
 230          * So the protocol is to always wait & clear.
 231          */
 232         uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
 233                         ATC_VMID0_PASID_MAPPING__VALID_MASK;
 234
 235         WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
 236
 237         while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
 238                 cpu_relax();
 239         WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 240
 241         /* Mapping vmid to pasid also for IH block */
 242         WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
 243
 244         return 0;
 245 }
 246
 247 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 248 {
 249         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 250         uint32_t mec;
 251         uint32_t pipe;
 252
 253         mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 254         pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 255
 256         lock_srbm(kgd, mec, pipe, 0, 0);
 257
 258         WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 259                         CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 260
 261         unlock_srbm(kgd);
 262
 263         return 0;
 264 }
 265
 266 static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
 267 {
 268         uint32_t retval;
 269
 270         retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
 271                 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
 272         pr_debug("kfd: sdma base address: 0x%x\n", retval);
 273
 274         return retval;
 275 }
 276
 277 static inline struct vi_mqd *get_mqd(void *mqd)
 278 {
 279         return (struct vi_mqd *)mqd;
 280 }
 281
 282 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
 283 {
 284         return (struct vi_sdma_mqd *)mqd;
 285 }
 286
 287 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 288                         uint32_t queue_id, uint32_t __user *wptr,
 289                         uint32_t wptr_shift, uint32_t wptr_mask,
 290                         struct mm_struct *mm)
 291 {
 292         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 293         struct vi_mqd *m;
 294         uint32_t *mqd_hqd;
 295         uint32_t reg, wptr_val, data;
 296         bool valid_wptr = false;
 297
 298         m = get_mqd(mqd);
 299
 300         acquire_queue(kgd, pipe_id, queue_id);
 301
 302         /* HIQ is set during driver init period with vmid set to 0*/
 303         if (m->cp_hqd_vmid == 0) {
 304                 uint32_t value, mec, pipe;
 305
 306                 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
 307                 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
 308
 309                 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 310                         mec, pipe, queue_id);
 311                 value = RREG32(mmRLC_CP_SCHEDULERS);
 312                 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
 313                         ((mec << 5) | (pipe << 3) | queue_id | 0x80));
 314                 WREG32(mmRLC_CP_SCHEDULERS, value);
 315         }
 316
 317         /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
 318         mqd_hqd = &m->cp_mqd_base_addr_lo;
 319
 320         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
 321                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 322
 323         /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
 324          * This is safe since EOP RPTR==WPTR for any inactive HQD
 325          * on ASICs that do not support context-save.
 326          * EOP writes/reads can start anywhere in the ring.
 327          */
 328         if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) {
 329                 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
 330                 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
 331                 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
 332         }
 333
 334         for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)
 335                 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
 336
 337         /* Copy userspace write pointer value to register.
 338          * Activate doorbell logic to monitor subsequent changes.
 339          */
 340         data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 341                              CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
 342         WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 343
 344         /* read_user_ptr may take the mm->mmap_sem.
 345          * release srbm_mutex to avoid circular dependency between
 346          * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
 347          */
 348         release_queue(kgd);
 349         valid_wptr = read_user_wptr(mm, wptr, wptr_val);
 350         acquire_queue(kgd, pipe_id, queue_id);
 351         if (valid_wptr)
 352                 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
 353
 354         data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
 355         WREG32(mmCP_HQD_ACTIVE, data);
 356
 357         release_queue(kgd);
 358
 359         return 0;
 360 }
 361
 362 static int kgd_hqd_dump(struct kgd_dev *kgd,
 363                         uint32_t pipe_id, uint32_t queue_id,
 364                         uint32_t (**dump)[2], uint32_t *n_regs)
 365 {
 366         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 367         uint32_t i = 0, reg;
 368 #define HQD_N_REGS (54+4)
 369 #define DUMP_REG(addr) do {                             \
 370                 if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
 371                         break;                          \
 372                 (*dump)[i][0] = (addr) << 2;            \
 373                 (*dump)[i++][1] = RREG32(addr);         \
 374         } while (0)
 375
 376         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 377         if (*dump == NULL)
 378                 return -ENOMEM;
 379
 380         acquire_queue(kgd, pipe_id, queue_id);
 381
 382         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
 383         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
 384         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
 385         DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
 386
 387         for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
 388                 DUMP_REG(reg);
 389
 390         release_queue(kgd);
 391
 392         WARN_ON_ONCE(i != HQD_N_REGS);
 393         *n_regs = i;
 394
 395         return 0;
 396 }
 397
 398 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 399                              uint32_t __user *wptr, struct mm_struct *mm)
 400 {
 401         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 402         struct vi_sdma_mqd *m;
 403         unsigned long end_jiffies;
 404         uint32_t sdma_base_addr;
 405         uint32_t data;
 406
 407         m = get_sdma_mqd(mqd);
 408         sdma_base_addr = get_sdma_base_addr(m);
 409         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 410                 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 411
 412         end_jiffies = msecs_to_jiffies(2000) + jiffies;
 413         while (true) {
 414                 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 415                 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 416                         break;
 417                 if (time_after(jiffies, end_jiffies))
 418                         return -ETIME;
 419                 usleep_range(500, 1000);
 420         }
 421         if (m->sdma_engine_id) {
 422                 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
 423                 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
 424                                 RESUME_CTX, 0);
 425                 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
 426         } else {
 427                 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
 428                 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
 429                                 RESUME_CTX, 0);
 430                 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
 431         }
 432
 433         data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
 434                              ENABLE, 1);
 435         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
 436         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
 437
 438         if (read_user_wptr(mm, wptr, data))
 439                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
 440         else
 441                 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
 442                        m->sdmax_rlcx_rb_rptr);
 443
 444         WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
 445                                 m->sdmax_rlcx_virtual_addr);
 446         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
 447         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
 448                         m->sdmax_rlcx_rb_base_hi);
 449         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 450                         m->sdmax_rlcx_rb_rptr_addr_lo);
 451         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 452                         m->sdmax_rlcx_rb_rptr_addr_hi);
 453
 454         data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
 455                              RB_ENABLE, 1);
 456         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
 457
 458         return 0;
 459 }
 460
 461 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
 462                              uint32_t engine_id, uint32_t queue_id,
 463                              uint32_t (**dump)[2], uint32_t *n_regs)
 464 {
 465         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 466         uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
 467                 queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
 468         uint32_t i = 0, reg;
 469 #undef HQD_N_REGS
 470 #define HQD_N_REGS (19+4+2+3+7)
 471
 472         *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
 473         if (*dump == NULL)
 474                 return -ENOMEM;
 475
 476         for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
 477                 DUMP_REG(sdma_offset + reg);
 478         for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
 479              reg++)
 480                 DUMP_REG(sdma_offset + reg);
 481         for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;
 482              reg++)
 483                 DUMP_REG(sdma_offset + reg);
 484         for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;
 485              reg++)
 486                 DUMP_REG(sdma_offset + reg);
 487         for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;
 488              reg++)
 489                 DUMP_REG(sdma_offset + reg);
 490
 491         WARN_ON_ONCE(i != HQD_N_REGS);
 492         *n_regs = i;
 493
 494         return 0;
 495 }
 496
 497 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 498                                 uint32_t pipe_id, uint32_t queue_id)
 499 {
 500         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 501         uint32_t act;
 502         bool retval = false;
 503         uint32_t low, high;
 504
 505         acquire_queue(kgd, pipe_id, queue_id);
 506         act = RREG32(mmCP_HQD_ACTIVE);
 507         if (act) {
 508                 low = lower_32_bits(queue_address >> 8);
 509                 high = upper_32_bits(queue_address >> 8);
 510
 511                 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
 512                                 high == RREG32(mmCP_HQD_PQ_BASE_HI))
 513                         retval = true;
 514         }
 515         release_queue(kgd);
 516         return retval;
 517 }
 518
 519 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 520 {
 521         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 522         struct vi_sdma_mqd *m;
 523         uint32_t sdma_base_addr;
 524         uint32_t sdma_rlc_rb_cntl;
 525
 526         m = get_sdma_mqd(mqd);
 527         sdma_base_addr = get_sdma_base_addr(m);
 528
 529         sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 530
 531         if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
 532                 return true;
 533
 534         return false;
 535 }
 536
 537 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
 538                                 enum kfd_preempt_type reset_type,
 539                                 unsigned int utimeout, uint32_t pipe_id,
 540                                 uint32_t queue_id)
 541 {
 542         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 543         uint32_t temp;
 544         enum hqd_dequeue_request_type type;
 545         unsigned long flags, end_jiffies;
 546         int retry;
 547         struct vi_mqd *m = get_mqd(mqd);
 548
 549         if (adev->in_gpu_reset)
 550                 return -EIO;
 551
 552         acquire_queue(kgd, pipe_id, queue_id);
 553
 554         if (m->cp_hqd_vmid == 0)
 555                 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
 556
 557         switch (reset_type) {
 558         case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
 559                 type = DRAIN_PIPE;
 560                 break;
 561         case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
 562                 type = RESET_WAVES;
 563                 break;
 564         default:
 565                 type = DRAIN_PIPE;
 566                 break;
 567         }
 568
 569         /* Workaround: If IQ timer is active and the wait time is close to or
 570          * equal to 0, dequeueing is not safe. Wait until either the wait time
 571          * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
 572          * cleared before continuing. Also, ensure wait times are set to at
 573          * least 0x3.
 574          */
 575         local_irq_save(flags);
 576         preempt_disable();
 577         retry = 5000; /* wait for 500 usecs at maximum */
 578         while (true) {
 579                 temp = RREG32(mmCP_HQD_IQ_TIMER);
 580                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
 581                         pr_debug("HW is processing IQ\n");
 582                         goto loop;
 583                 }
 584                 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
 585                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
 586                                         == 3) /* SEM-rearm is safe */
 587                                 break;
 588                         /* Wait time 3 is safe for CP, but our MMIO read/write
 589                          * time is close to 1 microsecond, so check for 10 to
 590                          * leave more buffer room
 591                          */
 592                         if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
 593                                         >= 10)
 594                                 break;
 595                         pr_debug("IQ timer is active\n");
 596                 } else
 597                         break;
 598 loop:
 599                 if (!retry) {
 600                         pr_err("CP HQD IQ timer status time out\n");
 601                         break;
 602                 }
 603                 ndelay(100);
 604                 --retry;
 605         }
 606         retry = 1000;
 607         while (true) {
 608                 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
 609                 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
 610                         break;
 611                 pr_debug("Dequeue request is pending\n");
 612
 613                 if (!retry) {
 614                         pr_err("CP HQD dequeue request time out\n");
 615                         break;
 616                 }
 617                 ndelay(100);
 618                 --retry;
 619         }
 620         local_irq_restore(flags);
 621         preempt_enable();
 622
 623         WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
 624
 625         end_jiffies = (utimeout * HZ / 1000) + jiffies;
 626         while (true) {
 627                 temp = RREG32(mmCP_HQD_ACTIVE);
 628                 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 629                         break;
 630                 if (time_after(jiffies, end_jiffies)) {
 631                         pr_err("cp queue preemption time out.\n");
 632                         release_queue(kgd);
 633                         return -ETIME;
 634                 }
 635                 usleep_range(500, 1000);
 636         }
 637
 638         release_queue(kgd);
 639         return 0;
 640 }
 641
 642 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 643                                 unsigned int utimeout)
 644 {
 645         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 646         struct vi_sdma_mqd *m;
 647         uint32_t sdma_base_addr;
 648         uint32_t temp;
 649         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 650
 651         m = get_sdma_mqd(mqd);
 652         sdma_base_addr = get_sdma_base_addr(m);
 653
 654         temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
 655         temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
 656         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
 657
 658         while (true) {
 659                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 660                 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 661                         break;
 662                 if (time_after(jiffies, end_jiffies))
 663                         return -ETIME;
 664                 usleep_range(500, 1000);
 665         }
 666
 667         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
 668         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 669                 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
 670                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 671
 672         m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
 673
 674         return 0;
 675 }
 676
 677 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
 678                                                         uint8_t vmid)
 679 {
 680         uint32_t reg;
 681         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 682
 683         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 684         return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 685 }
 686
 687 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
 688                                                                 uint8_t vmid)
 689 {
 690         uint32_t reg;
 691         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 692
 693         reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 694         return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 695 }
 696
 697 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 698 {
 699         return 0;
 700 }
 701
 702 static int kgd_address_watch_execute(struct kgd_dev *kgd,
 703                                         unsigned int watch_point_id,
 704                                         uint32_t cntl_val,
 705                                         uint32_t addr_hi,
 706                                         uint32_t addr_lo)
 707 {
 708         return 0;
 709 }
 710
 711 static int kgd_wave_control_execute(struct kgd_dev *kgd,
 712                                         uint32_t gfx_index_val,
 713                                         uint32_t sq_cmd)
 714 {
 715         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 716         uint32_t data = 0;
 717
 718         mutex_lock(&adev->grbm_idx_mutex);
 719
 720         WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
 721         WREG32(mmSQ_CMD, sq_cmd);
 722
 723         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 724                 INSTANCE_BROADCAST_WRITES, 1);
 725         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 726                 SH_BROADCAST_WRITES, 1);
 727         data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 728                 SE_BROADCAST_WRITES, 1);
 729
 730         WREG32(mmGRBM_GFX_INDEX, data);
 731         mutex_unlock(&adev->grbm_idx_mutex);
 732
 733         return 0;
 734 }
 735
 736 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
 737                                         unsigned int watch_point_id,
 738                                         unsigned int reg_offset)
 739 {
 740         return 0;
 741 }
 742
 743 static void set_scratch_backing_va(struct kgd_dev *kgd,
 744                                         uint64_t va, uint32_t vmid)
 745 {
 746         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 747
 748         lock_srbm(kgd, 0, 0, 0, vmid);
 749         WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
 750         unlock_srbm(kgd);
 751 }
 752
 753 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 754 {
 755         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 756         const union amdgpu_firmware_header *hdr;
 757
 758         switch (type) {
 759         case KGD_ENGINE_PFP:
 760                 hdr = (const union amdgpu_firmware_header *)
 761                                                 adev->gfx.pfp_fw->data;
 762                 break;
 763
 764         case KGD_ENGINE_ME:
 765                 hdr = (const union amdgpu_firmware_header *)
 766                                                 adev->gfx.me_fw->data;
 767                 break;
 768
 769         case KGD_ENGINE_CE:
 770                 hdr = (const union amdgpu_firmware_header *)
 771                                                 adev->gfx.ce_fw->data;
 772                 break;
 773
 774         case KGD_ENGINE_MEC1:
 775                 hdr = (const union amdgpu_firmware_header *)
 776                                                 adev->gfx.mec_fw->data;
 777                 break;
 778
 779         case KGD_ENGINE_MEC2:
 780                 hdr = (const union amdgpu_firmware_header *)
 781                                                 adev->gfx.mec2_fw->data;
 782                 break;
 783
 784         case KGD_ENGINE_RLC:
 785                 hdr = (const union amdgpu_firmware_header *)
 786                                                 adev->gfx.rlc_fw->data;
 787                 break;
 788
 789         case KGD_ENGINE_SDMA1:
 790                 hdr = (const union amdgpu_firmware_header *)
 791                                                 adev->sdma.instance[0].fw->data;
 792                 break;
 793
 794         case KGD_ENGINE_SDMA2:
 795                 hdr = (const union amdgpu_firmware_header *)
 796                                                 adev->sdma.instance[1].fw->data;
 797                 break;
 798
 799         default:
 800                 return 0;
 801         }
 802
 803         if (hdr == NULL)
 804                 return 0;
 805
 806         /* Only 12 bit in use*/
 807         return hdr->common.ucode_version;
 808 }
 809
 810 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
 811                 uint64_t page_table_base)
 812 {
 813         struct amdgpu_device *adev = get_amdgpu_device(kgd);
 814
 815         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 816                 pr_err("trying to set page table base for wrong VMID\n");
 817                 return;
 818         }
 819         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
 820                         lower_32_bits(page_table_base));
 821 }
 822
 823 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
 824 {
 825         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 826         int vmid;
 827         unsigned int tmp;
 828
 829         if (adev->in_gpu_reset)
 830                 return -EIO;
 831
 832         for (vmid = 0; vmid < 16; vmid++) {
 833                 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
 834                         continue;
 835
 836                 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 837                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 838                         (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
 839                         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 840                         RREG32(mmVM_INVALIDATE_RESPONSE);
 841                         break;
 842                 }
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
 849 {
 850         struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 851
 852         if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
 853                 pr_err("non kfd vmid %d\n", vmid);
 854                 return -EINVAL;
 855         }
 856
 857         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 858         RREG32(mmVM_INVALIDATE_RESPONSE);
 859         return 0;
 860 }