drivers/pinctrl/sunxi/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <[email protected]>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/irqchip/chained_irq.h>
  19 #include <linux/export.h>
  20 #include <linux/of.h>
  21 #include <linux/of_clk.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/pinctrl/machine.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinconf-generic.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33
  34 #include <dt-bindings/pinctrl/sun4i-a10.h>
  35
  36 #include "../core.h"
  37 #include "pinctrl-sunxi.h"
  38
  39 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
  40 static struct irq_chip sunxi_pinctrl_level_irq_chip;
  41
  42 static struct sunxi_pinctrl_group *
  43 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
  44 {
  45         int i;
  46
  47         for (i = 0; i < pctl->ngroups; i++) {
  48                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
  49
  50                 if (!strcmp(grp->name, group))
  51                         return grp;
  52         }
  53
  54         return NULL;
  55 }
  56
  57 static struct sunxi_pinctrl_function *
  58 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
  59                                     const char *name)
  60 {
  61         struct sunxi_pinctrl_function *func = pctl->functions;
  62         int i;
  63
  64         for (i = 0; i < pctl->nfunctions; i++) {
  65                 if (!func[i].name)
  66                         break;
  67
  68                 if (!strcmp(func[i].name, name))
  69                         return func + i;
  70         }
  71
  72         return NULL;
  73 }
  74
  75 static struct sunxi_desc_function *
  76 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
  77                                          const char *pin_name,
  78                                          const char *func_name)
  79 {
  80         int i;
  81
  82         for (i = 0; i < pctl->desc->npins; i++) {
  83                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
  84
  85                 if (!strcmp(pin->pin.name, pin_name)) {
  86                         struct sunxi_desc_function *func = pin->functions;
  87
  88                         while (func->name) {
  89                                 if (!strcmp(func->name, func_name) &&
  90                                         (!func->variant ||
  91                                         func->variant & pctl->variant))
  92                                         return func;
  93
  94                                 func++;
  95                         }
  96                 }
  97         }
  98
  99         return NULL;
 100 }
 101
 102 static struct sunxi_desc_function *
 103 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
 104                                         const u16 pin_num,
 105                                         const char *func_name)
 106 {
 107         int i;
 108
 109         for (i = 0; i < pctl->desc->npins; i++) {
 110                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 111
 112                 if (pin->pin.number == pin_num) {
 113                         struct sunxi_desc_function *func = pin->functions;
 114
 115                         while (func->name) {
 116                                 if (!strcmp(func->name, func_name))
 117                                         return func;
 118
 119                                 func++;
 120                         }
 121                 }
 122         }
 123
 124         return NULL;
 125 }
 126
 127 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 128 {
 129         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 130
 131         return pctl->ngroups;
 132 }
 133
 134 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 135                                               unsigned group)
 136 {
 137         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 138
 139         return pctl->groups[group].name;
 140 }
 141
 142 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 143                                       unsigned group,
 144                                       const unsigned **pins,
 145                                       unsigned *num_pins)
 146 {
 147         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 148
 149         *pins = (unsigned *)&pctl->groups[group].pin;
 150         *num_pins = 1;
 151
 152         return 0;
 153 }
 154
 155 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
 156 {
 157         return of_find_property(node, "bias-pull-up", NULL) ||
 158                 of_find_property(node, "bias-pull-down", NULL) ||
 159                 of_find_property(node, "bias-disable", NULL) ||
 160                 of_find_property(node, "allwinner,pull", NULL);
 161 }
 162
 163 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
 164 {
 165         return of_find_property(node, "drive-strength", NULL) ||
 166                 of_find_property(node, "allwinner,drive", NULL);
 167 }
 168
 169 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
 170 {
 171         u32 val;
 172
 173         /* Try the new style binding */
 174         if (of_find_property(node, "bias-pull-up", NULL))
 175                 return PIN_CONFIG_BIAS_PULL_UP;
 176
 177         if (of_find_property(node, "bias-pull-down", NULL))
 178                 return PIN_CONFIG_BIAS_PULL_DOWN;
 179
 180         if (of_find_property(node, "bias-disable", NULL))
 181                 return PIN_CONFIG_BIAS_DISABLE;
 182
 183         /* And fall back to the old binding */
 184         if (of_property_read_u32(node, "allwinner,pull", &val))
 185                 return -EINVAL;
 186
 187         switch (val) {
 188         case SUN4I_PINCTRL_NO_PULL:
 189                 return PIN_CONFIG_BIAS_DISABLE;
 190         case SUN4I_PINCTRL_PULL_UP:
 191                 return PIN_CONFIG_BIAS_PULL_UP;
 192         case SUN4I_PINCTRL_PULL_DOWN:
 193                 return PIN_CONFIG_BIAS_PULL_DOWN;
 194         }
 195
 196         return -EINVAL;
 197 }
 198
 199 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
 200 {
 201         u32 val;
 202
 203         /* Try the new style binding */
 204         if (!of_property_read_u32(node, "drive-strength", &val)) {
 205                 /* We can't go below 10mA ... */
 206                 if (val < 10)
 207                         return -EINVAL;
 208
 209                 /* ... and only up to 40 mA ... */
 210                 if (val > 40)
 211                         val = 40;
 212
 213                 /* by steps of 10 mA */
 214                 return rounddown(val, 10);
 215         }
 216
 217         /* And then fall back to the old binding */
 218         if (of_property_read_u32(node, "allwinner,drive", &val))
 219                 return -EINVAL;
 220
 221         return (val + 1) * 10;
 222 }
 223
 224 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
 225 {
 226         const char *function;
 227         int ret;
 228
 229         /* Try the generic binding */
 230         ret = of_property_read_string(node, "function", &function);
 231         if (!ret)
 232                 return function;
 233
 234         /* And fall back to our legacy one */
 235         ret = of_property_read_string(node, "allwinner,function", &function);
 236         if (!ret)
 237                 return function;
 238
 239         return NULL;
 240 }
 241
 242 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
 243                                               int *npins)
 244 {
 245         int count;
 246
 247         /* Try the generic binding */
 248         count = of_property_count_strings(node, "pins");
 249         if (count > 0) {
 250                 *npins = count;
 251                 return "pins";
 252         }
 253
 254         /* And fall back to our legacy one */
 255         count = of_property_count_strings(node, "allwinner,pins");
 256         if (count > 0) {
 257                 *npins = count;
 258                 return "allwinner,pins";
 259         }
 260
 261         return NULL;
 262 }
 263
 264 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
 265                                                    unsigned int *len)
 266 {
 267         unsigned long *pinconfig;
 268         unsigned int configlen = 0, idx = 0;
 269         int ret;
 270
 271         if (sunxi_pctrl_has_drive_prop(node))
 272                 configlen++;
 273         if (sunxi_pctrl_has_bias_prop(node))
 274                 configlen++;
 275
 276         /*
 277          * If we don't have any configuration, bail out
 278          */
 279         if (!configlen)
 280                 return NULL;
 281
 282         pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
 283         if (!pinconfig)
 284                 return ERR_PTR(-ENOMEM);
 285
 286         if (sunxi_pctrl_has_drive_prop(node)) {
 287                 int drive = sunxi_pctrl_parse_drive_prop(node);
 288                 if (drive < 0) {
 289                         ret = drive;
 290                         goto err_free;
 291                 }
 292
 293                 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 294                                                           drive);
 295         }
 296
 297         if (sunxi_pctrl_has_bias_prop(node)) {
 298                 int pull = sunxi_pctrl_parse_bias_prop(node);
 299                 int arg = 0;
 300                 if (pull < 0) {
 301                         ret = pull;
 302                         goto err_free;
 303                 }
 304
 305                 if (pull != PIN_CONFIG_BIAS_DISABLE)
 306                         arg = 1; /* hardware uses weak pull resistors */
 307
 308                 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
 309         }
 310
 311
 312         *len = configlen;
 313         return pinconfig;
 314
 315 err_free:
 316         kfree(pinconfig);
 317         return ERR_PTR(ret);
 318 }
 319
 320 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 321                                       struct device_node *node,
 322                                       struct pinctrl_map **map,
 323                                       unsigned *num_maps)
 324 {
 325         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 326         unsigned long *pinconfig;
 327         struct property *prop;
 328         const char *function, *pin_prop;
 329         const char *group;
 330         int ret, npins, nmaps, configlen = 0, i = 0;
 331
 332         *map = NULL;
 333         *num_maps = 0;
 334
 335         function = sunxi_pctrl_parse_function_prop(node);
 336         if (!function) {
 337                 dev_err(pctl->dev, "missing function property in node %pOFn\n",
 338                         node);
 339                 return -EINVAL;
 340         }
 341
 342         pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
 343         if (!pin_prop) {
 344                 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
 345                         node);
 346                 return -EINVAL;
 347         }
 348
 349         /*
 350          * We have two maps for each pin: one for the function, one
 351          * for the configuration (bias, strength, etc).
 352          *
 353          * We might be slightly overshooting, since we might not have
 354          * any configuration.
 355          */
 356         nmaps = npins * 2;
 357         *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
 358         if (!*map)
 359                 return -ENOMEM;
 360
 361         pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
 362         if (IS_ERR(pinconfig)) {
 363                 ret = PTR_ERR(pinconfig);
 364                 goto err_free_map;
 365         }
 366
 367         of_property_for_each_string(node, pin_prop, prop, group) {
 368                 struct sunxi_pinctrl_group *grp =
 369                         sunxi_pinctrl_find_group_by_name(pctl, group);
 370
 371                 if (!grp) {
 372                         dev_err(pctl->dev, "unknown pin %s", group);
 373                         continue;
 374                 }
 375
 376                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 377                                                               grp->name,
 378                                                               function)) {
 379                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 380                                 function, group);
 381                         continue;
 382                 }
 383
 384                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 385                 (*map)[i].data.mux.group = group;
 386                 (*map)[i].data.mux.function = function;
 387
 388                 i++;
 389
 390                 if (pinconfig) {
 391                         (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 392                         (*map)[i].data.configs.group_or_pin = group;
 393                         (*map)[i].data.configs.configs = pinconfig;
 394                         (*map)[i].data.configs.num_configs = configlen;
 395                         i++;
 396                 }
 397         }
 398
 399         *num_maps = i;
 400
 401         /*
 402          * We know have the number of maps we need, we can resize our
 403          * map array
 404          */
 405         *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
 406         if (!*map)
 407                 return -ENOMEM;
 408
 409         return 0;
 410
 411 err_free_map:
 412         kfree(*map);
 413         *map = NULL;
 414         return ret;
 415 }
 416
 417 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 418                                     struct pinctrl_map *map,
 419                                     unsigned num_maps)
 420 {
 421         int i;
 422
 423         /* pin config is never in the first map */
 424         for (i = 1; i < num_maps; i++) {
 425                 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
 426                         continue;
 427
 428                 /*
 429                  * All the maps share the same pin config,
 430                  * free only the first one we find.
 431                  */
 432                 kfree(map[i].data.configs.configs);
 433                 break;
 434         }
 435
 436         kfree(map);
 437 }
 438
 439 static const struct pinctrl_ops sunxi_pctrl_ops = {
 440         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 441         .dt_free_map            = sunxi_pctrl_dt_free_map,
 442         .get_groups_count       = sunxi_pctrl_get_groups_count,
 443         .get_group_name         = sunxi_pctrl_get_group_name,
 444         .get_group_pins         = sunxi_pctrl_get_group_pins,
 445 };
 446
 447 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
 448                            u32 *offset, u32 *shift, u32 *mask)
 449 {
 450         switch (param) {
 451         case PIN_CONFIG_DRIVE_STRENGTH:
 452                 *offset = sunxi_dlevel_reg(pin);
 453                 *shift = sunxi_dlevel_offset(pin);
 454                 *mask = DLEVEL_PINS_MASK;
 455                 break;
 456
 457         case PIN_CONFIG_BIAS_PULL_UP:
 458         case PIN_CONFIG_BIAS_PULL_DOWN:
 459         case PIN_CONFIG_BIAS_DISABLE:
 460                 *offset = sunxi_pull_reg(pin);
 461                 *shift = sunxi_pull_offset(pin);
 462                 *mask = PULL_PINS_MASK;
 463                 break;
 464
 465         default:
 466                 return -ENOTSUPP;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 473                            unsigned long *config)
 474 {
 475         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 476         enum pin_config_param param = pinconf_to_config_param(*config);
 477         u32 offset, shift, mask, val;
 478         u16 arg;
 479         int ret;
 480
 481         pin -= pctl->desc->pin_base;
 482
 483         ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
 484         if (ret < 0)
 485                 return ret;
 486
 487         val = (readl(pctl->membase + offset) >> shift) & mask;
 488
 489         switch (pinconf_to_config_param(*config)) {
 490         case PIN_CONFIG_DRIVE_STRENGTH:
 491                 arg = (val + 1) * 10;
 492                 break;
 493
 494         case PIN_CONFIG_BIAS_PULL_UP:
 495                 if (val != SUN4I_PINCTRL_PULL_UP)
 496                         return -EINVAL;
 497                 arg = 1; /* hardware is weak pull-up */
 498                 break;
 499
 500         case PIN_CONFIG_BIAS_PULL_DOWN:
 501                 if (val != SUN4I_PINCTRL_PULL_DOWN)
 502                         return -EINVAL;
 503                 arg = 1; /* hardware is weak pull-down */
 504                 break;
 505
 506         case PIN_CONFIG_BIAS_DISABLE:
 507                 if (val != SUN4I_PINCTRL_NO_PULL)
 508                         return -EINVAL;
 509                 arg = 0;
 510                 break;
 511
 512         default:
 513                 /* sunxi_pconf_reg should catch anything unsupported */
 514                 WARN_ON(1);
 515                 return -ENOTSUPP;
 516         }
 517
 518         *config = pinconf_to_config_packed(param, arg);
 519
 520         return 0;
 521 }
 522
 523 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 524                                  unsigned group,
 525                                  unsigned long *config)
 526 {
 527         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 528         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 529
 530         /* We only support 1 pin per group. Chain it to the pin callback */
 531         return sunxi_pconf_get(pctldev, g->pin, config);
 532 }
 533
 534 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 535                            unsigned long *configs, unsigned num_configs)
 536 {
 537         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 538         int i;
 539
 540         for (i = 0; i < num_configs; i++) {
 541                 enum pin_config_param param;
 542                 unsigned long flags;
 543                 u32 offset, shift, mask, reg;
 544                 u32 arg, val;
 545                 int ret;
 546
 547                 param = pinconf_to_config_param(configs[i]);
 548                 arg = pinconf_to_config_argument(configs[i]);
 549
 550                 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
 551                 if (ret < 0)
 552                         return ret;
 553
 554                 switch (param) {
 555                 case PIN_CONFIG_DRIVE_STRENGTH:
 556                         if (arg < 10 || arg > 40)
 557                                 return -EINVAL;
 558                         /*
 559                          * We convert from mA to what the register expects:
 560                          *   0: 10mA
 561                          *   1: 20mA
 562                          *   2: 30mA
 563                          *   3: 40mA
 564                          */
 565                         val = arg / 10 - 1;
 566                         break;
 567                 case PIN_CONFIG_BIAS_DISABLE:
 568                         val = 0;
 569                         break;
 570                 case PIN_CONFIG_BIAS_PULL_UP:
 571                         if (arg == 0)
 572                                 return -EINVAL;
 573                         val = 1;
 574                         break;
 575                 case PIN_CONFIG_BIAS_PULL_DOWN:
 576                         if (arg == 0)
 577                                 return -EINVAL;
 578                         val = 2;
 579                         break;
 580                 default:
 581                         /* sunxi_pconf_reg should catch anything unsupported */
 582                         WARN_ON(1);
 583                         return -ENOTSUPP;
 584                 }
 585
 586                 raw_spin_lock_irqsave(&pctl->lock, flags);
 587                 reg = readl(pctl->membase + offset);
 588                 reg &= ~(mask << shift);
 589                 writel(reg | val << shift, pctl->membase + offset);
 590                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 591         } /* for each config */
 592
 593         return 0;
 594 }
 595
 596 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
 597                                  unsigned long *configs, unsigned num_configs)
 598 {
 599         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 600         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 601
 602         /* We only support 1 pin per group. Chain it to the pin callback */
 603         return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
 604 }
 605
 606 static const struct pinconf_ops sunxi_pconf_ops = {
 607         .is_generic             = true,
 608         .pin_config_get         = sunxi_pconf_get,
 609         .pin_config_set         = sunxi_pconf_set,
 610         .pin_config_group_get   = sunxi_pconf_group_get,
 611         .pin_config_group_set   = sunxi_pconf_group_set,
 612 };
 613
 614 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
 615                                          unsigned pin,
 616                                          struct regulator *supply)
 617 {
 618         unsigned short bank = pin / PINS_PER_BANK;
 619         unsigned long flags;
 620         u32 val, reg;
 621         int uV;
 622
 623         if (!pctl->desc->io_bias_cfg_variant)
 624                 return 0;
 625
 626         uV = regulator_get_voltage(supply);
 627         if (uV < 0)
 628                 return uV;
 629
 630         /* Might be dummy regulator with no voltage set */
 631         if (uV == 0)
 632                 return 0;
 633
 634         switch (pctl->desc->io_bias_cfg_variant) {
 635         case BIAS_VOLTAGE_GRP_CONFIG:
 636                 /*
 637                  * Configured value must be equal or greater to actual
 638                  * voltage.
 639                  */
 640                 if (uV <= 1800000)
 641                         val = 0x0; /* 1.8V */
 642                 else if (uV <= 2500000)
 643                         val = 0x6; /* 2.5V */
 644                 else if (uV <= 2800000)
 645                         val = 0x9; /* 2.8V */
 646                 else if (uV <= 3000000)
 647                         val = 0xA; /* 3.0V */
 648                 else
 649                         val = 0xD; /* 3.3V */
 650
 651                 pin -= pctl->desc->pin_base;
 652
 653                 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
 654                 reg &= ~IO_BIAS_MASK;
 655                 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
 656                 return 0;
 657         case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
 658                 val = uV <= 1800000 ? 1 : 0;
 659
 660                 raw_spin_lock_irqsave(&pctl->lock, flags);
 661                 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
 662                 reg &= ~(1 << bank);
 663                 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
 664                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 665                 return 0;
 666         default:
 667                 return -EINVAL;
 668         }
 669 }
 670
 671 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 672 {
 673         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 674
 675         return pctl->nfunctions;
 676 }
 677
 678 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 679                                            unsigned function)
 680 {
 681         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 682
 683         return pctl->functions[function].name;
 684 }
 685
 686 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 687                                      unsigned function,
 688                                      const char * const **groups,
 689                                      unsigned * const num_groups)
 690 {
 691         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 692
 693         *groups = pctl->functions[function].groups;
 694         *num_groups = pctl->functions[function].ngroups;
 695
 696         return 0;
 697 }
 698
 699 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 700                                  unsigned pin,
 701                                  u8 config)
 702 {
 703         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 704         unsigned long flags;
 705         u32 val, mask;
 706
 707         raw_spin_lock_irqsave(&pctl->lock, flags);
 708
 709         pin -= pctl->desc->pin_base;
 710         val = readl(pctl->membase + sunxi_mux_reg(pin));
 711         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 712         writel((val & ~mask) | config << sunxi_mux_offset(pin),
 713                 pctl->membase + sunxi_mux_reg(pin));
 714
 715         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 716 }
 717
 718 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
 719                              unsigned function,
 720                              unsigned group)
 721 {
 722         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 723         struct sunxi_pinctrl_group *g = pctl->groups + group;
 724         struct sunxi_pinctrl_function *func = pctl->functions + function;
 725         struct sunxi_desc_function *desc =
 726                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 727                                                          g->name,
 728                                                          func->name);
 729
 730         if (!desc)
 731                 return -EINVAL;
 732
 733         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 734
 735         return 0;
 736 }
 737
 738 static int
 739 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 740                         struct pinctrl_gpio_range *range,
 741                         unsigned offset,
 742                         bool input)
 743 {
 744         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 745         struct sunxi_desc_function *desc;
 746         const char *func;
 747
 748         if (input)
 749                 func = "gpio_in";
 750         else
 751                 func = "gpio_out";
 752
 753         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 754         if (!desc)
 755                 return -EINVAL;
 756
 757         sunxi_pmx_set(pctldev, offset, desc->muxval);
 758
 759         return 0;
 760 }
 761
 762 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
 763 {
 764         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 765         unsigned short bank = offset / PINS_PER_BANK;
 766         unsigned short bank_offset = bank - pctl->desc->pin_base /
 767                                             PINS_PER_BANK;
 768         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 769         struct regulator *reg = s_reg->regulator;
 770         char supply[16];
 771         int ret;
 772
 773         if (reg) {
 774                 refcount_inc(&s_reg->refcount);
 775                 return 0;
 776         }
 777
 778         snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
 779         reg = regulator_get(pctl->dev, supply);
 780         if (IS_ERR(reg)) {
 781                 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
 782                         'A' + bank);
 783                 return PTR_ERR(reg);
 784         }
 785
 786         ret = regulator_enable(reg);
 787         if (ret) {
 788                 dev_err(pctl->dev,
 789                         "Couldn't enable bank P%c regulator\n", 'A' + bank);
 790                 goto out;
 791         }
 792
 793         sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
 794
 795         s_reg->regulator = reg;
 796         refcount_set(&s_reg->refcount, 1);
 797
 798         return 0;
 799
 800 out:
 801         regulator_put(s_reg->regulator);
 802
 803         return ret;
 804 }
 805
 806 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
 807 {
 808         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 809         unsigned short bank = offset / PINS_PER_BANK;
 810         unsigned short bank_offset = bank - pctl->desc->pin_base /
 811                                             PINS_PER_BANK;
 812         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 813
 814         if (!refcount_dec_and_test(&s_reg->refcount))
 815                 return 0;
 816
 817         regulator_disable(s_reg->regulator);
 818         regulator_put(s_reg->regulator);
 819         s_reg->regulator = NULL;
 820
 821         return 0;
 822 }
 823
 824 static const struct pinmux_ops sunxi_pmx_ops = {
 825         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 826         .get_function_name      = sunxi_pmx_get_func_name,
 827         .get_function_groups    = sunxi_pmx_get_func_groups,
 828         .set_mux                = sunxi_pmx_set_mux,
 829         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 830         .request                = sunxi_pmx_request,
 831         .free                   = sunxi_pmx_free,
 832         .strict                 = true,
 833 };
 834
 835 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 836                                         unsigned offset)
 837 {
 838         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 839
 840         return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, true);
 841 }
 842
 843 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 844 {
 845         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 846         u32 reg = sunxi_data_reg(offset);
 847         u8 index = sunxi_data_offset(offset);
 848         bool set_mux = pctl->desc->irq_read_needs_mux &&
 849                 gpiochip_line_is_irq(chip, offset);
 850         u32 pin = offset + chip->base;
 851         u32 val;
 852
 853         if (set_mux)
 854                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 855
 856         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 857
 858         if (set_mux)
 859                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 860
 861         return !!val;
 862 }
 863
 864 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 865                                 unsigned offset, int value)
 866 {
 867         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 868         u32 reg = sunxi_data_reg(offset);
 869         u8 index = sunxi_data_offset(offset);
 870         unsigned long flags;
 871         u32 regval;
 872
 873         raw_spin_lock_irqsave(&pctl->lock, flags);
 874
 875         regval = readl(pctl->membase + reg);
 876
 877         if (value)
 878                 regval |= BIT(index);
 879         else
 880                 regval &= ~(BIT(index));
 881
 882         writel(regval, pctl->membase + reg);
 883
 884         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 885 }
 886
 887 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 888                                         unsigned offset, int value)
 889 {
 890         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 891
 892         sunxi_pinctrl_gpio_set(chip, offset, value);
 893         return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, false);
 894 }
 895
 896 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 897                                 const struct of_phandle_args *gpiospec,
 898                                 u32 *flags)
 899 {
 900         int pin, base;
 901
 902         base = PINS_PER_BANK * gpiospec->args[0];
 903         pin = base + gpiospec->args[1];
 904
 905         if (pin > gc->ngpio)
 906                 return -EINVAL;
 907
 908         if (flags)
 909                 *flags = gpiospec->args[2];
 910
 911         return pin;
 912 }
 913
 914 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 915 {
 916         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 917         struct sunxi_desc_function *desc;
 918         unsigned pinnum = pctl->desc->pin_base + offset;
 919         unsigned irqnum;
 920
 921         if (offset >= chip->ngpio)
 922                 return -ENXIO;
 923
 924         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
 925         if (!desc)
 926                 return -EINVAL;
 927
 928         irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
 929
 930         dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
 931                 chip->label, offset + chip->base, irqnum);
 932
 933         return irq_find_mapping(pctl->domain, irqnum);
 934 }
 935
 936 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
 937 {
 938         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 939         struct sunxi_desc_function *func;
 940         int ret;
 941
 942         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
 943                                         pctl->irq_array[d->hwirq], "irq");
 944         if (!func)
 945                 return -EINVAL;
 946
 947         ret = gpiochip_lock_as_irq(pctl->chip,
 948                         pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 949         if (ret) {
 950                 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 951                         irqd_to_hwirq(d));
 952                 return ret;
 953         }
 954
 955         /* Change muxing to INT mode */
 956         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 957
 958         return 0;
 959 }
 960
 961 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
 962 {
 963         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 964
 965         gpiochip_unlock_as_irq(pctl->chip,
 966                               pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 967 }
 968
 969 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
 970 {
 971         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 972         u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
 973         u8 index = sunxi_irq_cfg_offset(d->hwirq);
 974         unsigned long flags;
 975         u32 regval;
 976         u8 mode;
 977
 978         switch (type) {
 979         case IRQ_TYPE_EDGE_RISING:
 980                 mode = IRQ_EDGE_RISING;
 981                 break;
 982         case IRQ_TYPE_EDGE_FALLING:
 983                 mode = IRQ_EDGE_FALLING;
 984                 break;
 985         case IRQ_TYPE_EDGE_BOTH:
 986                 mode = IRQ_EDGE_BOTH;
 987                 break;
 988         case IRQ_TYPE_LEVEL_HIGH:
 989                 mode = IRQ_LEVEL_HIGH;
 990                 break;
 991         case IRQ_TYPE_LEVEL_LOW:
 992                 mode = IRQ_LEVEL_LOW;
 993                 break;
 994         default:
 995                 return -EINVAL;
 996         }
 997
 998         raw_spin_lock_irqsave(&pctl->lock, flags);
 999
1000         if (type & IRQ_TYPE_LEVEL_MASK)
1001                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
1002                                                  handle_fasteoi_irq, NULL);
1003         else
1004                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1005                                                  handle_edge_irq, NULL);
1006
1007         regval = readl(pctl->membase + reg);
1008         regval &= ~(IRQ_CFG_IRQ_MASK << index);
1009         writel(regval | (mode << index), pctl->membase + reg);
1010
1011         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1012
1013         return 0;
1014 }
1015
1016 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1017 {
1018         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1019         u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1020         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1021
1022         /* Clear the IRQ */
1023         writel(1 << status_idx, pctl->membase + status_reg);
1024 }
1025
1026 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1027 {
1028         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1029         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1030         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1031         unsigned long flags;
1032         u32 val;
1033
1034         raw_spin_lock_irqsave(&pctl->lock, flags);
1035
1036         /* Mask the IRQ */
1037         val = readl(pctl->membase + reg);
1038         writel(val & ~(1 << idx), pctl->membase + reg);
1039
1040         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1041 }
1042
1043 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1044 {
1045         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1046         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1047         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1048         unsigned long flags;
1049         u32 val;
1050
1051         raw_spin_lock_irqsave(&pctl->lock, flags);
1052
1053         /* Unmask the IRQ */
1054         val = readl(pctl->membase + reg);
1055         writel(val | (1 << idx), pctl->membase + reg);
1056
1057         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1058 }
1059
1060 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1061 {
1062         sunxi_pinctrl_irq_ack(d);
1063         sunxi_pinctrl_irq_unmask(d);
1064 }
1065
1066 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
1067 {
1068         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1069         u8 bank = d->hwirq / IRQ_PER_BANK;
1070
1071         return irq_set_irq_wake(pctl->irq[bank], on);
1072 }
1073
1074 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1075         .name           = "sunxi_pio_edge",
1076         .irq_ack        = sunxi_pinctrl_irq_ack,
1077         .irq_mask       = sunxi_pinctrl_irq_mask,
1078         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1079         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1080         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1081         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1082         .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1083         .flags          = IRQCHIP_MASK_ON_SUSPEND,
1084 };
1085
1086 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1087         .name           = "sunxi_pio_level",
1088         .irq_eoi        = sunxi_pinctrl_irq_ack,
1089         .irq_mask       = sunxi_pinctrl_irq_mask,
1090         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1091         /* Define irq_enable / disable to avoid spurious irqs for drivers
1092          * using these to suppress irqs while they clear the irq source */
1093         .irq_enable     = sunxi_pinctrl_irq_ack_unmask,
1094         .irq_disable    = sunxi_pinctrl_irq_mask,
1095         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1096         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1097         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1098         .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1099         .flags          = IRQCHIP_EOI_THREADED |
1100                           IRQCHIP_MASK_ON_SUSPEND |
1101                           IRQCHIP_EOI_IF_HANDLED,
1102 };
1103
1104 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1105                                       struct device_node *node,
1106                                       const u32 *intspec,
1107                                       unsigned int intsize,
1108                                       unsigned long *out_hwirq,
1109                                       unsigned int *out_type)
1110 {
1111         struct sunxi_pinctrl *pctl = d->host_data;
1112         struct sunxi_desc_function *desc;
1113         int pin, base;
1114
1115         if (intsize < 3)
1116                 return -EINVAL;
1117
1118         base = PINS_PER_BANK * intspec[0];
1119         pin = pctl->desc->pin_base + base + intspec[1];
1120
1121         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1122         if (!desc)
1123                 return -EINVAL;
1124
1125         *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1126         *out_type = intspec[2];
1127
1128         return 0;
1129 }
1130
1131 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1132         .xlate          = sunxi_pinctrl_irq_of_xlate,
1133 };
1134
1135 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1136 {
1137         unsigned int irq = irq_desc_get_irq(desc);
1138         struct irq_chip *chip = irq_desc_get_chip(desc);
1139         struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1140         unsigned long bank, reg, val;
1141
1142         for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1143                 if (irq == pctl->irq[bank])
1144                         break;
1145
1146         WARN_ON(bank == pctl->desc->irq_banks);
1147
1148         chained_irq_enter(chip, desc);
1149
1150         reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1151         val = readl(pctl->membase + reg);
1152
1153         if (val) {
1154                 int irqoffset;
1155
1156                 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
1157                         generic_handle_domain_irq(pctl->domain,
1158                                                   bank * IRQ_PER_BANK + irqoffset);
1159         }
1160
1161         chained_irq_exit(chip, desc);
1162 }
1163
1164 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1165                                         const char *name)
1166 {
1167         struct sunxi_pinctrl_function *func = pctl->functions;
1168
1169         while (func->name) {
1170                 /* function already there */
1171                 if (strcmp(func->name, name) == 0) {
1172                         func->ngroups++;
1173                         return -EEXIST;
1174                 }
1175                 func++;
1176         }
1177
1178         func->name = name;
1179         func->ngroups = 1;
1180
1181         pctl->nfunctions++;
1182
1183         return 0;
1184 }
1185
1186 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1187 {
1188         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1189         void *ptr;
1190         int i;
1191
1192         /*
1193          * Allocate groups
1194          *
1195          * We assume that the number of groups is the number of pins
1196          * given in the data array.
1197
1198          * This will not always be true, since some pins might not be
1199          * available in the current variant, but fortunately for us,
1200          * this means that the number of pins is the maximum group
1201          * number we will ever see.
1202          */
1203         pctl->groups = devm_kcalloc(&pdev->dev,
1204                                     pctl->desc->npins, sizeof(*pctl->groups),
1205                                     GFP_KERNEL);
1206         if (!pctl->groups)
1207                 return -ENOMEM;
1208
1209         for (i = 0; i < pctl->desc->npins; i++) {
1210                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1211                 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1212
1213                 if (pin->variant && !(pctl->variant & pin->variant))
1214                         continue;
1215
1216                 group->name = pin->pin.name;
1217                 group->pin = pin->pin.number;
1218
1219                 /* And now we count the actual number of pins / groups */
1220                 pctl->ngroups++;
1221         }
1222
1223         /*
1224          * Find an upper bound for the maximum number of functions: in
1225          * the worst case we have gpio_in, gpio_out, irq and up to four
1226          * special functions per pin, plus one entry for the sentinel.
1227          * We'll reallocate that later anyway.
1228          */
1229         pctl->functions = kcalloc(4 * pctl->ngroups + 4,
1230                                   sizeof(*pctl->functions),
1231                                   GFP_KERNEL);
1232         if (!pctl->functions)
1233                 return -ENOMEM;
1234
1235         /* Count functions and their associated groups */
1236         for (i = 0; i < pctl->desc->npins; i++) {
1237                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1238                 struct sunxi_desc_function *func;
1239
1240                 if (pin->variant && !(pctl->variant & pin->variant))
1241                         continue;
1242
1243                 for (func = pin->functions; func->name; func++) {
1244                         if (func->variant && !(pctl->variant & func->variant))
1245                                 continue;
1246
1247                         /* Create interrupt mapping while we're at it */
1248                         if (!strcmp(func->name, "irq")) {
1249                                 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1250                                 pctl->irq_array[irqnum] = pin->pin.number;
1251                         }
1252
1253                         sunxi_pinctrl_add_function(pctl, func->name);
1254                 }
1255         }
1256
1257         /* And now allocated and fill the array for real */
1258         ptr = krealloc(pctl->functions,
1259                        pctl->nfunctions * sizeof(*pctl->functions),
1260                        GFP_KERNEL);
1261         if (!ptr) {
1262                 kfree(pctl->functions);
1263                 pctl->functions = NULL;
1264                 return -ENOMEM;
1265         }
1266         pctl->functions = ptr;
1267
1268         for (i = 0; i < pctl->desc->npins; i++) {
1269                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1270                 struct sunxi_desc_function *func;
1271
1272                 if (pin->variant && !(pctl->variant & pin->variant))
1273                         continue;
1274
1275                 for (func = pin->functions; func->name; func++) {
1276                         struct sunxi_pinctrl_function *func_item;
1277                         const char **func_grp;
1278
1279                         if (func->variant && !(pctl->variant & func->variant))
1280                                 continue;
1281
1282                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
1283                                                                         func->name);
1284                         if (!func_item) {
1285                                 kfree(pctl->functions);
1286                                 return -EINVAL;
1287                         }
1288
1289                         if (!func_item->groups) {
1290                                 func_item->groups =
1291                                         devm_kcalloc(&pdev->dev,
1292                                                      func_item->ngroups,
1293                                                      sizeof(*func_item->groups),
1294                                                      GFP_KERNEL);
1295                                 if (!func_item->groups) {
1296                                         kfree(pctl->functions);
1297                                         return -ENOMEM;
1298                                 }
1299                         }
1300
1301                         func_grp = func_item->groups;
1302                         while (*func_grp)
1303                                 func_grp++;
1304
1305                         *func_grp = pin->pin.name;
1306                 }
1307         }
1308
1309         return 0;
1310 }
1311
1312 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1313 {
1314         unsigned long clock = clk_get_rate(clk);
1315         unsigned int best_diff, best_div;
1316         int i;
1317
1318         best_diff = abs(freq - clock);
1319         best_div = 0;
1320
1321         for (i = 1; i < 8; i++) {
1322                 int cur_diff = abs(freq - (clock >> i));
1323
1324                 if (cur_diff < best_diff) {
1325                         best_diff = cur_diff;
1326                         best_div = i;
1327                 }
1328         }
1329
1330         *diff = best_diff;
1331         return best_div;
1332 }
1333
1334 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1335                                         struct device_node *node)
1336 {
1337         unsigned int hosc_diff, losc_diff;
1338         unsigned int hosc_div, losc_div;
1339         struct clk *hosc, *losc;
1340         u8 div, src;
1341         int i, ret;
1342
1343         /* Deal with old DTs that didn't have the oscillators */
1344         if (of_clk_get_parent_count(node) != 3)
1345                 return 0;
1346
1347         /* If we don't have any setup, bail out */
1348         if (!of_find_property(node, "input-debounce", NULL))
1349                 return 0;
1350
1351         losc = devm_clk_get(pctl->dev, "losc");
1352         if (IS_ERR(losc))
1353                 return PTR_ERR(losc);
1354
1355         hosc = devm_clk_get(pctl->dev, "hosc");
1356         if (IS_ERR(hosc))
1357                 return PTR_ERR(hosc);
1358
1359         for (i = 0; i < pctl->desc->irq_banks; i++) {
1360                 unsigned long debounce_freq;
1361                 u32 debounce;
1362
1363                 ret = of_property_read_u32_index(node, "input-debounce",
1364                                                  i, &debounce);
1365                 if (ret)
1366                         return ret;
1367
1368                 if (!debounce)
1369                         continue;
1370
1371                 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1372                 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1373                                                           debounce_freq,
1374                                                           &losc_diff);
1375
1376                 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1377                                                           debounce_freq,
1378                                                           &hosc_diff);
1379
1380                 if (hosc_diff < losc_diff) {
1381                         div = hosc_div;
1382                         src = 1;
1383                 } else {
1384                         div = losc_div;
1385                         src = 0;
1386                 }
1387
1388                 writel(src | div << 4,
1389                        pctl->membase +
1390                        sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1391         }
1392
1393         return 0;
1394 }
1395
1396 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1397                                     const struct sunxi_pinctrl_desc *desc,
1398                                     unsigned long variant)
1399 {
1400         struct device_node *node = pdev->dev.of_node;
1401         struct pinctrl_desc *pctrl_desc;
1402         struct pinctrl_pin_desc *pins;
1403         struct sunxi_pinctrl *pctl;
1404         struct pinmux_ops *pmxops;
1405         int i, ret, last_pin, pin_idx;
1406         struct clk *clk;
1407
1408         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1409         if (!pctl)
1410                 return -ENOMEM;
1411         platform_set_drvdata(pdev, pctl);
1412
1413         raw_spin_lock_init(&pctl->lock);
1414
1415         pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1416         if (IS_ERR(pctl->membase))
1417                 return PTR_ERR(pctl->membase);
1418
1419         pctl->dev = &pdev->dev;
1420         pctl->desc = desc;
1421         pctl->variant = variant;
1422
1423         pctl->irq_array = devm_kcalloc(&pdev->dev,
1424                                        IRQ_PER_BANK * pctl->desc->irq_banks,
1425                                        sizeof(*pctl->irq_array),
1426                                        GFP_KERNEL);
1427         if (!pctl->irq_array)
1428                 return -ENOMEM;
1429
1430         ret = sunxi_pinctrl_build_state(pdev);
1431         if (ret) {
1432                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1433                 return ret;
1434         }
1435
1436         pins = devm_kcalloc(&pdev->dev,
1437                             pctl->desc->npins, sizeof(*pins),
1438                             GFP_KERNEL);
1439         if (!pins)
1440                 return -ENOMEM;
1441
1442         for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1443                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1444
1445                 if (pin->variant && !(pctl->variant & pin->variant))
1446                         continue;
1447
1448                 pins[pin_idx++] = pin->pin;
1449         }
1450
1451         pctrl_desc = devm_kzalloc(&pdev->dev,
1452                                   sizeof(*pctrl_desc),
1453                                   GFP_KERNEL);
1454         if (!pctrl_desc)
1455                 return -ENOMEM;
1456
1457         pctrl_desc->name = dev_name(&pdev->dev);
1458         pctrl_desc->owner = THIS_MODULE;
1459         pctrl_desc->pins = pins;
1460         pctrl_desc->npins = pctl->ngroups;
1461         pctrl_desc->confops = &sunxi_pconf_ops;
1462         pctrl_desc->pctlops = &sunxi_pctrl_ops;
1463
1464         pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1465                               GFP_KERNEL);
1466         if (!pmxops)
1467                 return -ENOMEM;
1468
1469         if (desc->disable_strict_mode)
1470                 pmxops->strict = false;
1471
1472         pctrl_desc->pmxops = pmxops;
1473
1474         pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1475         if (IS_ERR(pctl->pctl_dev)) {
1476                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1477                 return PTR_ERR(pctl->pctl_dev);
1478         }
1479
1480         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1481         if (!pctl->chip)
1482                 return -ENOMEM;
1483
1484         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1485         pctl->chip->owner = THIS_MODULE;
1486         pctl->chip->request = gpiochip_generic_request;
1487         pctl->chip->free = gpiochip_generic_free;
1488         pctl->chip->set_config = gpiochip_generic_config;
1489         pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1490         pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1491         pctl->chip->get = sunxi_pinctrl_gpio_get;
1492         pctl->chip->set = sunxi_pinctrl_gpio_set;
1493         pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1494         pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1495         pctl->chip->of_gpio_n_cells = 3;
1496         pctl->chip->can_sleep = false;
1497         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1498                             pctl->desc->pin_base;
1499         pctl->chip->label = dev_name(&pdev->dev);
1500         pctl->chip->parent = &pdev->dev;
1501         pctl->chip->base = pctl->desc->pin_base;
1502
1503         ret = gpiochip_add_data(pctl->chip, pctl);
1504         if (ret)
1505                 return ret;
1506
1507         for (i = 0; i < pctl->desc->npins; i++) {
1508                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1509
1510                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1511                                              pin->pin.number - pctl->desc->pin_base,
1512                                              pin->pin.number, 1);
1513                 if (ret)
1514                         goto gpiochip_error;
1515         }
1516
1517         ret = of_clk_get_parent_count(node);
1518         clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1519         if (IS_ERR(clk)) {
1520                 ret = PTR_ERR(clk);
1521                 goto gpiochip_error;
1522         }
1523
1524         ret = clk_prepare_enable(clk);
1525         if (ret)
1526                 goto gpiochip_error;
1527
1528         pctl->irq = devm_kcalloc(&pdev->dev,
1529                                  pctl->desc->irq_banks,
1530                                  sizeof(*pctl->irq),
1531                                  GFP_KERNEL);
1532         if (!pctl->irq) {
1533                 ret = -ENOMEM;
1534                 goto clk_error;
1535         }
1536
1537         for (i = 0; i < pctl->desc->irq_banks; i++) {
1538                 pctl->irq[i] = platform_get_irq(pdev, i);
1539                 if (pctl->irq[i] < 0) {
1540                         ret = pctl->irq[i];
1541                         goto clk_error;
1542                 }
1543         }
1544
1545         pctl->domain = irq_domain_add_linear(node,
1546                                              pctl->desc->irq_banks * IRQ_PER_BANK,
1547                                              &sunxi_pinctrl_irq_domain_ops,
1548                                              pctl);
1549         if (!pctl->domain) {
1550                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1551                 ret = -ENOMEM;
1552                 goto clk_error;
1553         }
1554
1555         for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1556                 int irqno = irq_create_mapping(pctl->domain, i);
1557
1558                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1559                                          handle_edge_irq);
1560                 irq_set_chip_data(irqno, pctl);
1561         }
1562
1563         for (i = 0; i < pctl->desc->irq_banks; i++) {
1564                 /* Mask and clear all IRQs before registering a handler */
1565                 writel(0, pctl->membase +
1566                           sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1567                 writel(0xffffffff,
1568                        pctl->membase +
1569                        sunxi_irq_status_reg_from_bank(pctl->desc, i));
1570
1571                 irq_set_chained_handler_and_data(pctl->irq[i],
1572                                                  sunxi_pinctrl_irq_handler,
1573                                                  pctl);
1574         }
1575
1576         sunxi_pinctrl_setup_debounce(pctl, node);
1577
1578         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1579
1580         return 0;
1581
1582 clk_error:
1583         clk_disable_unprepare(clk);
1584 gpiochip_error:
1585         gpiochip_remove(pctl->chip);
1586         return ret;
1587 }