drivers/gpu/drm/ast/ast_mode.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  * Parts based on xf86-video-ast
   4  * Copyright (c) 2005 ASPEED Technology Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  18  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  19  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  *
  26  */
  27 /*
  28  * Authors: Dave Airlie <[email protected]>
  29  */
  30
  31 #include <linux/export.h>
  32 #include <linux/pci.h>
  33
  34 #include <drm/drm_atomic.h>
  35 #include <drm/drm_atomic_helper.h>
  36 #include <drm/drm_atomic_state_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_fourcc.h>
  40 #include <drm/drm_gem_atomic_helper.h>
  41 #include <drm/drm_gem_framebuffer_helper.h>
  42 #include <drm/drm_gem_vram_helper.h>
  43 #include <drm/drm_plane_helper.h>
  44 #include <drm/drm_probe_helper.h>
  45 #include <drm/drm_simple_kms_helper.h>
  46
  47 #include "ast_drv.h"
  48 #include "ast_tables.h"
  49
  50 static inline void ast_load_palette_index(struct ast_private *ast,
  51                                      u8 index, u8 red, u8 green,
  52                                      u8 blue)
  53 {
  54         ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
  55         ast_io_read8(ast, AST_IO_SEQ_PORT);
  56         ast_io_write8(ast, AST_IO_DAC_DATA, red);
  57         ast_io_read8(ast, AST_IO_SEQ_PORT);
  58         ast_io_write8(ast, AST_IO_DAC_DATA, green);
  59         ast_io_read8(ast, AST_IO_SEQ_PORT);
  60         ast_io_write8(ast, AST_IO_DAC_DATA, blue);
  61         ast_io_read8(ast, AST_IO_SEQ_PORT);
  62 }
  63
  64 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
  65 {
  66         u16 *r, *g, *b;
  67         int i;
  68
  69         if (!crtc->enabled)
  70                 return;
  71
  72         r = crtc->gamma_store;
  73         g = r + crtc->gamma_size;
  74         b = g + crtc->gamma_size;
  75
  76         for (i = 0; i < 256; i++)
  77                 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
  78 }
  79
  80 static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
  81                                     const struct drm_display_mode *mode,
  82                                     struct drm_display_mode *adjusted_mode,
  83                                     struct ast_vbios_mode_info *vbios_mode)
  84 {
  85         u32 refresh_rate_index = 0, refresh_rate;
  86         const struct ast_vbios_enhtable *best = NULL;
  87         u32 hborder, vborder;
  88         bool check_sync;
  89
  90         switch (format->cpp[0] * 8) {
  91         case 8:
  92                 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
  93                 break;
  94         case 16:
  95                 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
  96                 break;
  97         case 24:
  98         case 32:
  99                 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
 100                 break;
 101         default:
 102                 return false;
 103         }
 104
 105         switch (mode->crtc_hdisplay) {
 106         case 640:
 107                 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
 108                 break;
 109         case 800:
 110                 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
 111                 break;
 112         case 1024:
 113                 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
 114                 break;
 115         case 1280:
 116                 if (mode->crtc_vdisplay == 800)
 117                         vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
 118                 else
 119                         vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
 120                 break;
 121         case 1360:
 122                 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
 123                 break;
 124         case 1440:
 125                 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
 126                 break;
 127         case 1600:
 128                 if (mode->crtc_vdisplay == 900)
 129                         vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
 130                 else
 131                         vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
 132                 break;
 133         case 1680:
 134                 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
 135                 break;
 136         case 1920:
 137                 if (mode->crtc_vdisplay == 1080)
 138                         vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
 139                 else
 140                         vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
 141                 break;
 142         default:
 143                 return false;
 144         }
 145
 146         refresh_rate = drm_mode_vrefresh(mode);
 147         check_sync = vbios_mode->enh_table->flags & WideScreenMode;
 148
 149         while (1) {
 150                 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
 151
 152                 while (loop->refresh_rate != 0xff) {
 153                         if ((check_sync) &&
 154                             (((mode->flags & DRM_MODE_FLAG_NVSYNC)  &&
 155                               (loop->flags & PVSync))  ||
 156                              ((mode->flags & DRM_MODE_FLAG_PVSYNC)  &&
 157                               (loop->flags & NVSync))  ||
 158                              ((mode->flags & DRM_MODE_FLAG_NHSYNC)  &&
 159                               (loop->flags & PHSync))  ||
 160                              ((mode->flags & DRM_MODE_FLAG_PHSYNC)  &&
 161                               (loop->flags & NHSync)))) {
 162                                 loop++;
 163                                 continue;
 164                         }
 165                         if (loop->refresh_rate <= refresh_rate
 166                             && (!best || loop->refresh_rate > best->refresh_rate))
 167                                 best = loop;
 168                         loop++;
 169                 }
 170                 if (best || !check_sync)
 171                         break;
 172                 check_sync = 0;
 173         }
 174
 175         if (best)
 176                 vbios_mode->enh_table = best;
 177
 178         hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
 179         vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
 180
 181         adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
 182         adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
 183         adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
 184         adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
 185                 vbios_mode->enh_table->hfp;
 186         adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
 187                                          vbios_mode->enh_table->hfp +
 188                                          vbios_mode->enh_table->hsync);
 189
 190         adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
 191         adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
 192         adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
 193         adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
 194                 vbios_mode->enh_table->vfp;
 195         adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
 196                                          vbios_mode->enh_table->vfp +
 197                                          vbios_mode->enh_table->vsync);
 198
 199         return true;
 200 }
 201
 202 static void ast_set_vbios_color_reg(struct ast_private *ast,
 203                                     const struct drm_format_info *format,
 204                                     const struct ast_vbios_mode_info *vbios_mode)
 205 {
 206         u32 color_index;
 207
 208         switch (format->cpp[0]) {
 209         case 1:
 210                 color_index = VGAModeIndex - 1;
 211                 break;
 212         case 2:
 213                 color_index = HiCModeIndex;
 214                 break;
 215         case 3:
 216         case 4:
 217                 color_index = TrueCModeIndex;
 218                 break;
 219         default:
 220                 return;
 221         }
 222
 223         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
 224
 225         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
 226
 227         if (vbios_mode->enh_table->flags & NewModeInfo) {
 228                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
 229                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
 230         }
 231 }
 232
 233 static void ast_set_vbios_mode_reg(struct ast_private *ast,
 234                                    const struct drm_display_mode *adjusted_mode,
 235                                    const struct ast_vbios_mode_info *vbios_mode)
 236 {
 237         u32 refresh_rate_index, mode_id;
 238
 239         refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
 240         mode_id = vbios_mode->enh_table->mode_id;
 241
 242         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
 243         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
 244
 245         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
 246
 247         if (vbios_mode->enh_table->flags & NewModeInfo) {
 248                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
 249                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
 250                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
 251                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
 252                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
 253                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
 254         }
 255 }
 256
 257 static void ast_set_std_reg(struct ast_private *ast,
 258                             struct drm_display_mode *mode,
 259                             struct ast_vbios_mode_info *vbios_mode)
 260 {
 261         const struct ast_vbios_stdtable *stdtable;
 262         u32 i;
 263         u8 jreg;
 264
 265         stdtable = vbios_mode->std_table;
 266
 267         jreg = stdtable->misc;
 268         ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
 269
 270         /* Set SEQ; except Screen Disable field */
 271         ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
 272         ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
 273         for (i = 1; i < 4; i++) {
 274                 jreg = stdtable->seq[i];
 275                 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1), jreg);
 276         }
 277
 278         /* Set CRTC; except base address and offset */
 279         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
 280         for (i = 0; i < 12; i++)
 281                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
 282         for (i = 14; i < 19; i++)
 283                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
 284         for (i = 20; i < 25; i++)
 285                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
 286
 287         /* set AR */
 288         jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
 289         for (i = 0; i < 20; i++) {
 290                 jreg = stdtable->ar[i];
 291                 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
 292                 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
 293         }
 294         ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
 295         ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
 296
 297         jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
 298         ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
 299
 300         /* Set GR */
 301         for (i = 0; i < 9; i++)
 302                 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
 303 }
 304
 305 static void ast_set_crtc_reg(struct ast_private *ast,
 306                              struct drm_display_mode *mode,
 307                              struct ast_vbios_mode_info *vbios_mode)
 308 {
 309         u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
 310         u16 temp, precache = 0;
 311
 312         if ((ast->chip == AST2500) &&
 313             (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
 314                 precache = 40;
 315
 316         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
 317
 318         temp = (mode->crtc_htotal >> 3) - 5;
 319         if (temp & 0x100)
 320                 jregAC |= 0x01; /* HT D[8] */
 321         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
 322
 323         temp = (mode->crtc_hdisplay >> 3) - 1;
 324         if (temp & 0x100)
 325                 jregAC |= 0x04; /* HDE D[8] */
 326         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
 327
 328         temp = (mode->crtc_hblank_start >> 3) - 1;
 329         if (temp & 0x100)
 330                 jregAC |= 0x10; /* HBS D[8] */
 331         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
 332
 333         temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
 334         if (temp & 0x20)
 335                 jreg05 |= 0x80;  /* HBE D[5] */
 336         if (temp & 0x40)
 337                 jregAD |= 0x01;  /* HBE D[5] */
 338         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
 339
 340         temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
 341         if (temp & 0x100)
 342                 jregAC |= 0x40; /* HRS D[5] */
 343         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
 344
 345         temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
 346         if (temp & 0x20)
 347                 jregAD |= 0x04; /* HRE D[5] */
 348         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
 349
 350         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
 351         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
 352
 353         /* vert timings */
 354         temp = (mode->crtc_vtotal) - 2;
 355         if (temp & 0x100)
 356                 jreg07 |= 0x01;
 357         if (temp & 0x200)
 358                 jreg07 |= 0x20;
 359         if (temp & 0x400)
 360                 jregAE |= 0x01;
 361         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
 362
 363         temp = (mode->crtc_vsync_start) - 1;
 364         if (temp & 0x100)
 365                 jreg07 |= 0x04;
 366         if (temp & 0x200)
 367                 jreg07 |= 0x80;
 368         if (temp & 0x400)
 369                 jregAE |= 0x08;
 370         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
 371
 372         temp = (mode->crtc_vsync_end - 1) & 0x3f;
 373         if (temp & 0x10)
 374                 jregAE |= 0x20;
 375         if (temp & 0x20)
 376                 jregAE |= 0x40;
 377         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
 378
 379         temp = mode->crtc_vdisplay - 1;
 380         if (temp & 0x100)
 381                 jreg07 |= 0x02;
 382         if (temp & 0x200)
 383                 jreg07 |= 0x40;
 384         if (temp & 0x400)
 385                 jregAE |= 0x02;
 386         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
 387
 388         temp = mode->crtc_vblank_start - 1;
 389         if (temp & 0x100)
 390                 jreg07 |= 0x08;
 391         if (temp & 0x200)
 392                 jreg09 |= 0x20;
 393         if (temp & 0x400)
 394                 jregAE |= 0x04;
 395         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
 396
 397         temp = mode->crtc_vblank_end - 1;
 398         if (temp & 0x100)
 399                 jregAE |= 0x10;
 400         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
 401
 402         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
 403         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
 404         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
 405
 406         if (precache)
 407                 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
 408         else
 409                 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
 410
 411         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
 412 }
 413
 414 static void ast_set_offset_reg(struct ast_private *ast,
 415                                struct drm_framebuffer *fb)
 416 {
 417         u16 offset;
 418
 419         offset = fb->pitches[0] >> 3;
 420         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
 421         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
 422 }
 423
 424 static void ast_set_dclk_reg(struct ast_private *ast,
 425                              struct drm_display_mode *mode,
 426                              struct ast_vbios_mode_info *vbios_mode)
 427 {
 428         const struct ast_vbios_dclk_info *clk_info;
 429
 430         if (ast->chip == AST2500)
 431                 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
 432         else
 433                 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
 434
 435         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
 436         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
 437         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
 438                                (clk_info->param3 & 0xc0) |
 439                                ((clk_info->param3 & 0x3) << 4));
 440 }
 441
 442 static void ast_set_color_reg(struct ast_private *ast,
 443                               const struct drm_format_info *format)
 444 {
 445         u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
 446
 447         switch (format->cpp[0] * 8) {
 448         case 8:
 449                 jregA0 = 0x70;
 450                 jregA3 = 0x01;
 451                 jregA8 = 0x00;
 452                 break;
 453         case 15:
 454         case 16:
 455                 jregA0 = 0x70;
 456                 jregA3 = 0x04;
 457                 jregA8 = 0x02;
 458                 break;
 459         case 32:
 460                 jregA0 = 0x70;
 461                 jregA3 = 0x08;
 462                 jregA8 = 0x02;
 463                 break;
 464         }
 465
 466         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
 467         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
 468         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
 469 }
 470
 471 static void ast_set_crtthd_reg(struct ast_private *ast)
 472 {
 473         /* Set Threshold */
 474         if (ast->chip == AST2300 || ast->chip == AST2400 ||
 475             ast->chip == AST2500) {
 476                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
 477                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
 478         } else if (ast->chip == AST2100 ||
 479                    ast->chip == AST1100 ||
 480                    ast->chip == AST2200 ||
 481                    ast->chip == AST2150) {
 482                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
 483                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
 484         } else {
 485                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
 486                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
 487         }
 488 }
 489
 490 static void ast_set_sync_reg(struct ast_private *ast,
 491                              struct drm_display_mode *mode,
 492                              struct ast_vbios_mode_info *vbios_mode)
 493 {
 494         u8 jreg;
 495
 496         jreg  = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
 497         jreg &= ~0xC0;
 498         if (vbios_mode->enh_table->flags & NVSync)
 499                 jreg |= 0x80;
 500         if (vbios_mode->enh_table->flags & NHSync)
 501                 jreg |= 0x40;
 502         ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
 503 }
 504
 505 static void ast_set_start_address_crt1(struct ast_private *ast,
 506                                        unsigned int offset)
 507 {
 508         u32 addr;
 509
 510         addr = offset >> 2;
 511         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
 512         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
 513         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
 514
 515 }
 516
 517 static void ast_wait_for_vretrace(struct ast_private *ast)
 518 {
 519         unsigned long timeout = jiffies + HZ;
 520         u8 vgair1;
 521
 522         do {
 523                 vgair1 = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
 524         } while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout));
 525 }
 526
 527 /*
 528  * Primary plane
 529  */
 530
 531 static const uint32_t ast_primary_plane_formats[] = {
 532         DRM_FORMAT_XRGB8888,
 533         DRM_FORMAT_RGB565,
 534         DRM_FORMAT_C8,
 535 };
 536
 537 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
 538                                                  struct drm_atomic_state *state)
 539 {
 540         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 541                                                                                  plane);
 542         struct drm_crtc_state *crtc_state;
 543         struct ast_crtc_state *ast_crtc_state;
 544         int ret;
 545
 546         if (!new_plane_state->crtc)
 547                 return 0;
 548
 549         crtc_state = drm_atomic_get_new_crtc_state(state,
 550                                                    new_plane_state->crtc);
 551
 552         ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 553                                                   DRM_PLANE_HELPER_NO_SCALING,
 554                                                   DRM_PLANE_HELPER_NO_SCALING,
 555                                                   false, true);
 556         if (ret)
 557                 return ret;
 558
 559         if (!new_plane_state->visible)
 560                 return 0;
 561
 562         ast_crtc_state = to_ast_crtc_state(crtc_state);
 563
 564         ast_crtc_state->format = new_plane_state->fb->format;
 565
 566         return 0;
 567 }
 568
 569 static void
 570 ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
 571                                        struct drm_atomic_state *state)
 572 {
 573         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 574                                                                            plane);
 575         struct drm_device *dev = plane->dev;
 576         struct ast_private *ast = to_ast_private(dev);
 577         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 578                                                                            plane);
 579         struct drm_gem_vram_object *gbo;
 580         s64 gpu_addr;
 581         struct drm_framebuffer *fb = new_state->fb;
 582         struct drm_framebuffer *old_fb = old_state->fb;
 583
 584         if (!old_fb || (fb->format != old_fb->format)) {
 585                 struct drm_crtc_state *crtc_state = new_state->crtc->state;
 586                 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
 587                 struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
 588
 589                 ast_set_color_reg(ast, fb->format);
 590                 ast_set_vbios_color_reg(ast, fb->format, vbios_mode_info);
 591         }
 592
 593         gbo = drm_gem_vram_of_gem(fb->obj[0]);
 594         gpu_addr = drm_gem_vram_offset(gbo);
 595         if (drm_WARN_ON_ONCE(dev, gpu_addr < 0))
 596                 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
 597
 598         ast_set_offset_reg(ast, fb);
 599         ast_set_start_address_crt1(ast, (u32)gpu_addr);
 600
 601         ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
 602 }
 603
 604 static void
 605 ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
 606                                         struct drm_atomic_state *state)
 607 {
 608         struct ast_private *ast = to_ast_private(plane->dev);
 609
 610         ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
 611 }
 612
 613 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
 614         DRM_GEM_VRAM_PLANE_HELPER_FUNCS,
 615         .atomic_check = ast_primary_plane_helper_atomic_check,
 616         .atomic_update = ast_primary_plane_helper_atomic_update,
 617         .atomic_disable = ast_primary_plane_helper_atomic_disable,
 618 };
 619
 620 static const struct drm_plane_funcs ast_primary_plane_funcs = {
 621         .update_plane = drm_atomic_helper_update_plane,
 622         .disable_plane = drm_atomic_helper_disable_plane,
 623         .destroy = drm_plane_cleanup,
 624         .reset = drm_atomic_helper_plane_reset,
 625         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 626         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 627 };
 628
 629 static int ast_primary_plane_init(struct ast_private *ast)
 630 {
 631         struct drm_device *dev = &ast->base;
 632         struct drm_plane *primary_plane = &ast->primary_plane;
 633         int ret;
 634
 635         ret = drm_universal_plane_init(dev, primary_plane, 0x01,
 636                                        &ast_primary_plane_funcs,
 637                                        ast_primary_plane_formats,
 638                                        ARRAY_SIZE(ast_primary_plane_formats),
 639                                        NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
 640         if (ret) {
 641                 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
 642                 return ret;
 643         }
 644         drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs);
 645
 646         return 0;
 647 }
 648
 649 /*
 650  * Cursor plane
 651  */
 652
 653 static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height)
 654 {
 655         union {
 656                 u32 ul;
 657                 u8 b[4];
 658         } srcdata32[2], data32;
 659         union {
 660                 u16 us;
 661                 u8 b[2];
 662         } data16;
 663         u32 csum = 0;
 664         s32 alpha_dst_delta, last_alpha_dst_delta;
 665         u8 __iomem *dstxor;
 666         const u8 *srcxor;
 667         int i, j;
 668         u32 per_pixel_copy, two_pixel_copy;
 669
 670         alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
 671         last_alpha_dst_delta = alpha_dst_delta - (width << 1);
 672
 673         srcxor = src;
 674         dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
 675         per_pixel_copy = width & 1;
 676         two_pixel_copy = width >> 1;
 677
 678         for (j = 0; j < height; j++) {
 679                 for (i = 0; i < two_pixel_copy; i++) {
 680                         srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
 681                         srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
 682                         data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
 683                         data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
 684                         data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
 685                         data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
 686
 687                         writel(data32.ul, dstxor);
 688                         csum += data32.ul;
 689
 690                         dstxor += 4;
 691                         srcxor += 8;
 692
 693                 }
 694
 695                 for (i = 0; i < per_pixel_copy; i++) {
 696                         srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
 697                         data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
 698                         data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
 699                         writew(data16.us, dstxor);
 700                         csum += (u32)data16.us;
 701
 702                         dstxor += 2;
 703                         srcxor += 4;
 704                 }
 705                 dstxor += last_alpha_dst_delta;
 706         }
 707
 708         /* write checksum + signature */
 709         dst += AST_HWC_SIZE;
 710         writel(csum, dst);
 711         writel(width, dst + AST_HWC_SIGNATURE_SizeX);
 712         writel(height, dst + AST_HWC_SIGNATURE_SizeY);
 713         writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
 714         writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
 715 }
 716
 717 static void ast_set_cursor_base(struct ast_private *ast, u64 address)
 718 {
 719         u8 addr0 = (address >> 3) & 0xff;
 720         u8 addr1 = (address >> 11) & 0xff;
 721         u8 addr2 = (address >> 19) & 0xff;
 722
 723         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
 724         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
 725         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
 726 }
 727
 728 static void ast_set_cursor_location(struct ast_private *ast, u16 x, u16 y,
 729                                     u8 x_offset, u8 y_offset)
 730 {
 731         u8 x0 = (x & 0x00ff);
 732         u8 x1 = (x & 0x0f00) >> 8;
 733         u8 y0 = (y & 0x00ff);
 734         u8 y1 = (y & 0x0700) >> 8;
 735
 736         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
 737         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
 738         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0);
 739         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1);
 740         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0);
 741         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1);
 742 }
 743
 744 static void ast_set_cursor_enabled(struct ast_private *ast, bool enabled)
 745 {
 746         static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP |
 747                                      AST_IO_VGACRCB_HWC_ENABLED);
 748
 749         u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP;
 750
 751         if (enabled)
 752                 vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED;
 753
 754         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb);
 755 }
 756
 757 static const uint32_t ast_cursor_plane_formats[] = {
 758         DRM_FORMAT_ARGB8888,
 759 };
 760
 761 static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
 762                                                 struct drm_atomic_state *state)
 763 {
 764         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 765                                                                                  plane);
 766         struct drm_framebuffer *fb = new_plane_state->fb;
 767         struct drm_crtc_state *crtc_state;
 768         int ret;
 769
 770         if (!new_plane_state->crtc)
 771                 return 0;
 772
 773         crtc_state = drm_atomic_get_new_crtc_state(state,
 774                                                    new_plane_state->crtc);
 775
 776         ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 777                                                   DRM_PLANE_HELPER_NO_SCALING,
 778                                                   DRM_PLANE_HELPER_NO_SCALING,
 779                                                   true, true);
 780         if (ret)
 781                 return ret;
 782
 783         if (!new_plane_state->visible)
 784                 return 0;
 785
 786         if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
 787                 return -EINVAL;
 788
 789         return 0;
 790 }
 791
 792 static void
 793 ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
 794                                       struct drm_atomic_state *state)
 795 {
 796         struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
 797         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 798                                                                            plane);
 799         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 800                                                                            plane);
 801         struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(new_state);
 802         struct drm_framebuffer *fb = new_state->fb;
 803         struct ast_private *ast = to_ast_private(plane->dev);
 804         struct dma_buf_map dst_map =
 805                 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map;
 806         u64 dst_off =
 807                 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].off;
 808         struct dma_buf_map src_map = shadow_plane_state->data[0];
 809         unsigned int offset_x, offset_y;
 810         u16 x, y;
 811         u8 x_offset, y_offset;
 812         u8 __iomem *dst;
 813         u8 __iomem *sig;
 814         const u8 *src;
 815
 816         src = src_map.vaddr; /* TODO: Use mapping abstraction properly */
 817         dst = dst_map.vaddr_iomem; /* TODO: Use mapping abstraction properly */
 818         sig = dst + AST_HWC_SIZE; /* TODO: Use mapping abstraction properly */
 819
 820         /*
 821          * Do data transfer to HW cursor BO. If a new cursor image was installed,
 822          * point the scanout engine to dst_gbo's offset and page-flip the HWC buffers.
 823          */
 824
 825         ast_update_cursor_image(dst, src, fb->width, fb->height);
 826
 827         if (new_state->fb != old_state->fb) {
 828                 ast_set_cursor_base(ast, dst_off);
 829
 830                 ++ast_cursor_plane->next_hwc_index;
 831                 ast_cursor_plane->next_hwc_index %= ARRAY_SIZE(ast_cursor_plane->hwc);
 832         }
 833
 834         /*
 835          * Update location in HWC signature and registers.
 836          */
 837
 838         writel(new_state->crtc_x, sig + AST_HWC_SIGNATURE_X);
 839         writel(new_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);
 840
 841         offset_x = AST_MAX_HWC_WIDTH - fb->width;
 842         offset_y = AST_MAX_HWC_HEIGHT - fb->height;
 843
 844         if (new_state->crtc_x < 0) {
 845                 x_offset = (-new_state->crtc_x) + offset_x;
 846                 x = 0;
 847         } else {
 848                 x_offset = offset_x;
 849                 x = new_state->crtc_x;
 850         }
 851         if (new_state->crtc_y < 0) {
 852                 y_offset = (-new_state->crtc_y) + offset_y;
 853                 y = 0;
 854         } else {
 855                 y_offset = offset_y;
 856                 y = new_state->crtc_y;
 857         }
 858
 859         ast_set_cursor_location(ast, x, y, x_offset, y_offset);
 860
 861         /* Dummy write to enable HWC and make the HW pick-up the changes. */
 862         ast_set_cursor_enabled(ast, true);
 863 }
 864
 865 static void
 866 ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
 867                                        struct drm_atomic_state *state)
 868 {
 869         struct ast_private *ast = to_ast_private(plane->dev);
 870
 871         ast_set_cursor_enabled(ast, false);
 872 }
 873
 874 static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
 875         DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
 876         .atomic_check = ast_cursor_plane_helper_atomic_check,
 877         .atomic_update = ast_cursor_plane_helper_atomic_update,
 878         .atomic_disable = ast_cursor_plane_helper_atomic_disable,
 879 };
 880
 881 static void ast_cursor_plane_destroy(struct drm_plane *plane)
 882 {
 883         struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
 884         size_t i;
 885         struct drm_gem_vram_object *gbo;
 886         struct dma_buf_map map;
 887
 888         for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
 889                 gbo = ast_cursor_plane->hwc[i].gbo;
 890                 map = ast_cursor_plane->hwc[i].map;
 891                 drm_gem_vram_vunmap(gbo, &map);
 892                 drm_gem_vram_unpin(gbo);
 893                 drm_gem_vram_put(gbo);
 894         }
 895
 896         drm_plane_cleanup(plane);
 897 }
 898
 899 static const struct drm_plane_funcs ast_cursor_plane_funcs = {
 900         .update_plane = drm_atomic_helper_update_plane,
 901         .disable_plane = drm_atomic_helper_disable_plane,
 902         .destroy = ast_cursor_plane_destroy,
 903         DRM_GEM_SHADOW_PLANE_FUNCS,
 904 };
 905
 906 static int ast_cursor_plane_init(struct ast_private *ast)
 907 {
 908         struct drm_device *dev = &ast->base;
 909         struct ast_cursor_plane *ast_cursor_plane = &ast->cursor_plane;
 910         struct drm_plane *cursor_plane = &ast_cursor_plane->base;
 911         size_t size, i;
 912         struct drm_gem_vram_object *gbo;
 913         struct dma_buf_map map;
 914         int ret;
 915         s64 off;
 916
 917         /*
 918          * Allocate backing storage for cursors. The BOs are permanently
 919          * pinned to the top end of the VRAM.
 920          */
 921
 922         size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
 923
 924         for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
 925                 gbo = drm_gem_vram_create(dev, size, 0);
 926                 if (IS_ERR(gbo)) {
 927                         ret = PTR_ERR(gbo);
 928                         goto err_hwc;
 929                 }
 930                 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM |
 931                                             DRM_GEM_VRAM_PL_FLAG_TOPDOWN);
 932                 if (ret)
 933                         goto err_drm_gem_vram_put;
 934                 ret = drm_gem_vram_vmap(gbo, &map);
 935                 if (ret)
 936                         goto err_drm_gem_vram_unpin;
 937                 off = drm_gem_vram_offset(gbo);
 938                 if (off < 0) {
 939                         ret = off;
 940                         goto err_drm_gem_vram_vunmap;
 941                 }
 942                 ast_cursor_plane->hwc[i].gbo = gbo;
 943                 ast_cursor_plane->hwc[i].map = map;
 944                 ast_cursor_plane->hwc[i].off = off;
 945         }
 946
 947         /*
 948          * Create the cursor plane. The plane's destroy callback will release
 949          * the backing storages' BO memory.
 950          */
 951
 952         ret = drm_universal_plane_init(dev, cursor_plane, 0x01,
 953                                        &ast_cursor_plane_funcs,
 954                                        ast_cursor_plane_formats,
 955                                        ARRAY_SIZE(ast_cursor_plane_formats),
 956                                        NULL, DRM_PLANE_TYPE_CURSOR, NULL);
 957         if (ret) {
 958                 drm_err(dev, "drm_universal_plane failed(): %d\n", ret);
 959                 goto err_hwc;
 960         }
 961         drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs);
 962
 963         return 0;
 964
 965 err_hwc:
 966         while (i) {
 967                 --i;
 968                 gbo = ast_cursor_plane->hwc[i].gbo;
 969                 map = ast_cursor_plane->hwc[i].map;
 970 err_drm_gem_vram_vunmap:
 971                 drm_gem_vram_vunmap(gbo, &map);
 972 err_drm_gem_vram_unpin:
 973                 drm_gem_vram_unpin(gbo);
 974 err_drm_gem_vram_put:
 975                 drm_gem_vram_put(gbo);
 976         }
 977         return ret;
 978 }
 979
 980 /*
 981  * CRTC
 982  */
 983
 984 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
 985 {
 986         struct ast_private *ast = to_ast_private(crtc->dev);
 987
 988         /* TODO: Maybe control display signal generation with
 989          *       Sync Enable (bit CR17.7).
 990          */
 991         switch (mode) {
 992         case DRM_MODE_DPMS_ON:
 993         case DRM_MODE_DPMS_STANDBY:
 994         case DRM_MODE_DPMS_SUSPEND:
 995                 if (ast->tx_chip_type == AST_TX_DP501)
 996                         ast_set_dp501_video_output(crtc->dev, 1);
 997                 break;
 998         case DRM_MODE_DPMS_OFF:
 999                 if (ast->tx_chip_type == AST_TX_DP501)
1000                         ast_set_dp501_video_output(crtc->dev, 0);
1001                 break;
1002         }
1003 }
1004
1005 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
1006                                         struct drm_atomic_state *state)
1007 {
1008         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1009                                                                           crtc);
1010         struct drm_device *dev = crtc->dev;
1011         struct ast_crtc_state *ast_state;
1012         const struct drm_format_info *format;
1013         bool succ;
1014
1015         if (!crtc_state->enable)
1016                 return 0; /* no mode checks if CRTC is being disabled */
1017
1018         ast_state = to_ast_crtc_state(crtc_state);
1019
1020         format = ast_state->format;
1021         if (drm_WARN_ON_ONCE(dev, !format))
1022                 return -EINVAL; /* BUG: We didn't set format in primary check(). */
1023
1024         succ = ast_get_vbios_mode_info(format, &crtc_state->mode,
1025                                        &crtc_state->adjusted_mode,
1026                                        &ast_state->vbios_mode_info);
1027         if (!succ)
1028                 return -EINVAL;
1029
1030         return 0;
1031 }
1032
1033 static void
1034 ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
1035                              struct drm_atomic_state *state)
1036 {
1037         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1038                                                                           crtc);
1039         struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1040                                                                               crtc);
1041         struct ast_private *ast = to_ast_private(crtc->dev);
1042         struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1043         struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state);
1044
1045         /*
1046          * The gamma LUT has to be reloaded after changing the primary
1047          * plane's color format.
1048          */
1049         if (old_ast_crtc_state->format != ast_crtc_state->format)
1050                 ast_crtc_load_lut(ast, crtc);
1051 }
1052
1053 static void
1054 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
1055                               struct drm_atomic_state *state)
1056 {
1057         struct drm_device *dev = crtc->dev;
1058         struct ast_private *ast = to_ast_private(dev);
1059         struct drm_crtc_state *crtc_state = crtc->state;
1060         struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1061         struct ast_vbios_mode_info *vbios_mode_info =
1062                 &ast_crtc_state->vbios_mode_info;
1063         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1064
1065         ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
1066         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
1067         ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
1068         ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
1069         ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
1070         ast_set_crtthd_reg(ast);
1071         ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
1072
1073         ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1074 }
1075
1076 static void
1077 ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
1078                                struct drm_atomic_state *state)
1079 {
1080         struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1081                                                                               crtc);
1082         struct drm_device *dev = crtc->dev;
1083         struct ast_private *ast = to_ast_private(dev);
1084
1085         ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1086
1087         /*
1088          * HW cursors require the underlying primary plane and CRTC to
1089          * display a valid mode and image. This is not the case during
1090          * full modeset operations. So we temporarily disable any active
1091          * plane, including the HW cursor. Each plane's atomic_update()
1092          * helper will re-enable it if necessary.
1093          *
1094          * We only do this during *full* modesets. It does not affect
1095          * simple pageflips on the planes.
1096          */
1097         drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1098
1099         /*
1100          * Ensure that no scanout takes place before reprogramming mode
1101          * and format registers.
1102          */
1103         ast_wait_for_vretrace(ast);
1104 }
1105
1106 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
1107         .atomic_check = ast_crtc_helper_atomic_check,
1108         .atomic_flush = ast_crtc_helper_atomic_flush,
1109         .atomic_enable = ast_crtc_helper_atomic_enable,
1110         .atomic_disable = ast_crtc_helper_atomic_disable,
1111 };
1112
1113 static void ast_crtc_reset(struct drm_crtc *crtc)
1114 {
1115         struct ast_crtc_state *ast_state =
1116                 kzalloc(sizeof(*ast_state), GFP_KERNEL);
1117
1118         if (crtc->state)
1119                 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
1120
1121         if (ast_state)
1122                 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
1123         else
1124                 __drm_atomic_helper_crtc_reset(crtc, NULL);
1125 }
1126
1127 static struct drm_crtc_state *
1128 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1129 {
1130         struct ast_crtc_state *new_ast_state, *ast_state;
1131         struct drm_device *dev = crtc->dev;
1132
1133         if (drm_WARN_ON(dev, !crtc->state))
1134                 return NULL;
1135
1136         new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
1137         if (!new_ast_state)
1138                 return NULL;
1139         __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
1140
1141         ast_state = to_ast_crtc_state(crtc->state);
1142
1143         new_ast_state->format = ast_state->format;
1144         memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
1145                sizeof(new_ast_state->vbios_mode_info));
1146
1147         return &new_ast_state->base;
1148 }
1149
1150 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1151                                           struct drm_crtc_state *state)
1152 {
1153         struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
1154
1155         __drm_atomic_helper_crtc_destroy_state(&ast_state->base);
1156         kfree(ast_state);
1157 }
1158
1159 static const struct drm_crtc_funcs ast_crtc_funcs = {
1160         .reset = ast_crtc_reset,
1161         .destroy = drm_crtc_cleanup,
1162         .set_config = drm_atomic_helper_set_config,
1163         .page_flip = drm_atomic_helper_page_flip,
1164         .atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
1165         .atomic_destroy_state = ast_crtc_atomic_destroy_state,
1166 };
1167
1168 static int ast_crtc_init(struct drm_device *dev)
1169 {
1170         struct ast_private *ast = to_ast_private(dev);
1171         struct drm_crtc *crtc = &ast->crtc;
1172         int ret;
1173
1174         ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane,
1175                                         &ast->cursor_plane.base, &ast_crtc_funcs,
1176                                         NULL);
1177         if (ret)
1178                 return ret;
1179
1180         drm_mode_crtc_set_gamma_size(crtc, 256);
1181         drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs);
1182
1183         return 0;
1184 }
1185
1186 /*
1187  * Encoder
1188  */
1189
1190 static int ast_encoder_init(struct drm_device *dev)
1191 {
1192         struct ast_private *ast = to_ast_private(dev);
1193         struct drm_encoder *encoder = &ast->encoder;
1194         int ret;
1195
1196         ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
1197         if (ret)
1198                 return ret;
1199
1200         encoder->possible_crtcs = 1;
1201
1202         return 0;
1203 }
1204
1205 /*
1206  * Connector
1207  */
1208
1209 static int ast_get_modes(struct drm_connector *connector)
1210 {
1211         struct ast_connector *ast_connector = to_ast_connector(connector);
1212         struct ast_private *ast = to_ast_private(connector->dev);
1213         struct edid *edid = NULL;
1214         bool flags = false;
1215         int ret;
1216
1217         if (ast->tx_chip_type == AST_TX_DP501) {
1218                 ast->dp501_maxclk = 0xff;
1219                 edid = kmalloc(128, GFP_KERNEL);
1220                 if (!edid)
1221                         return -ENOMEM;
1222
1223                 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
1224                 if (flags)
1225                         ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1226                 else
1227                         kfree(edid);
1228         }
1229         if (!flags && ast_connector->i2c)
1230                 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
1231         if (edid) {
1232                 drm_connector_update_edid_property(&ast_connector->base, edid);
1233                 ret = drm_add_edid_modes(connector, edid);
1234                 kfree(edid);
1235                 return ret;
1236         }
1237         drm_connector_update_edid_property(&ast_connector->base, NULL);
1238         return 0;
1239 }
1240
1241 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
1242                           struct drm_display_mode *mode)
1243 {
1244         struct ast_private *ast = to_ast_private(connector->dev);
1245         int flags = MODE_NOMODE;
1246         uint32_t jtemp;
1247
1248         if (ast->support_wide_screen) {
1249                 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1250                         return MODE_OK;
1251                 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1252                         return MODE_OK;
1253                 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1254                         return MODE_OK;
1255                 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1256                         return MODE_OK;
1257                 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1258                         return MODE_OK;
1259
1260                 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1261                     (ast->chip == AST2300) || (ast->chip == AST2400) ||
1262                     (ast->chip == AST2500)) {
1263                         if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1264                                 return MODE_OK;
1265
1266                         if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1267                                 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1268                                 if (jtemp & 0x01)
1269                                         return MODE_NOMODE;
1270                                 else
1271                                         return MODE_OK;
1272                         }
1273                 }
1274         }
1275         switch (mode->hdisplay) {
1276         case 640:
1277                 if (mode->vdisplay == 480)
1278                         flags = MODE_OK;
1279                 break;
1280         case 800:
1281                 if (mode->vdisplay == 600)
1282                         flags = MODE_OK;
1283                 break;
1284         case 1024:
1285                 if (mode->vdisplay == 768)
1286                         flags = MODE_OK;
1287                 break;
1288         case 1280:
1289                 if (mode->vdisplay == 1024)
1290                         flags = MODE_OK;
1291                 break;
1292         case 1600:
1293                 if (mode->vdisplay == 1200)
1294                         flags = MODE_OK;
1295                 break;
1296         default:
1297                 return flags;
1298         }
1299
1300         return flags;
1301 }
1302
1303 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
1304         .get_modes = ast_get_modes,
1305         .mode_valid = ast_mode_valid,
1306 };
1307
1308 static const struct drm_connector_funcs ast_connector_funcs = {
1309         .reset = drm_atomic_helper_connector_reset,
1310         .fill_modes = drm_helper_probe_single_connector_modes,
1311         .destroy = drm_connector_cleanup,
1312         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1313         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1314 };
1315
1316 static int ast_connector_init(struct drm_device *dev)
1317 {
1318         struct ast_private *ast = to_ast_private(dev);
1319         struct ast_connector *ast_connector = &ast->connector;
1320         struct drm_connector *connector = &ast_connector->base;
1321         struct drm_encoder *encoder = &ast->encoder;
1322
1323         ast_connector->i2c = ast_i2c_create(dev);
1324         if (!ast_connector->i2c)
1325                 drm_err(dev, "failed to add ddc bus for connector\n");
1326
1327         if (ast_connector->i2c)
1328                 drm_connector_init_with_ddc(dev, connector, &ast_connector_funcs,
1329                                             DRM_MODE_CONNECTOR_VGA,
1330                                             &ast_connector->i2c->adapter);
1331         else
1332                 drm_connector_init(dev, connector, &ast_connector_funcs,
1333                                    DRM_MODE_CONNECTOR_VGA);
1334
1335         drm_connector_helper_add(connector, &ast_connector_helper_funcs);
1336
1337         connector->interlace_allowed = 0;
1338         connector->doublescan_allowed = 0;
1339
1340         connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1341
1342         drm_connector_attach_encoder(connector, encoder);
1343
1344         return 0;
1345 }
1346
1347 /*
1348  * Mode config
1349  */
1350
1351 static const struct drm_mode_config_helper_funcs
1352 ast_mode_config_helper_funcs = {
1353         .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
1354 };
1355
1356 static const struct drm_mode_config_funcs ast_mode_config_funcs = {
1357         .fb_create = drm_gem_fb_create,
1358         .mode_valid = drm_vram_helper_mode_valid,
1359         .atomic_check = drm_atomic_helper_check,
1360         .atomic_commit = drm_atomic_helper_commit,
1361 };
1362
1363 int ast_mode_config_init(struct ast_private *ast)
1364 {
1365         struct drm_device *dev = &ast->base;
1366         struct pci_dev *pdev = to_pci_dev(dev->dev);
1367         int ret;
1368
1369         ret = drmm_mode_config_init(dev);
1370         if (ret)
1371                 return ret;
1372
1373         dev->mode_config.funcs = &ast_mode_config_funcs;
1374         dev->mode_config.min_width = 0;
1375         dev->mode_config.min_height = 0;
1376         dev->mode_config.preferred_depth = 24;
1377         dev->mode_config.prefer_shadow = 1;
1378         dev->mode_config.fb_base = pci_resource_start(pdev, 0);
1379
1380         if (ast->chip == AST2100 ||
1381             ast->chip == AST2200 ||
1382             ast->chip == AST2300 ||
1383             ast->chip == AST2400 ||
1384             ast->chip == AST2500) {
1385                 dev->mode_config.max_width = 1920;
1386                 dev->mode_config.max_height = 2048;
1387         } else {
1388                 dev->mode_config.max_width = 1600;
1389                 dev->mode_config.max_height = 1200;
1390         }
1391
1392         dev->mode_config.helper_private = &ast_mode_config_helper_funcs;
1393
1394
1395         ret = ast_primary_plane_init(ast);
1396         if (ret)
1397                 return ret;
1398
1399         ret = ast_cursor_plane_init(ast);
1400         if (ret)
1401                 return ret;
1402
1403         ast_crtc_init(dev);
1404         ast_encoder_init(dev);
1405         ast_connector_init(dev);
1406
1407         drm_mode_config_reset(dev);
1408
1409         return 0;
1410 }