drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 101                                   struct drm_i915_gem_object *obj,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125
 126 struct intel_limit {
 127         struct {
 128                 int min, max;
 129         } dot, vco, n, m, m1, m2, p, p1;
 130
 131         struct {
 132                 int dot_limit;
 133                 int p2_slow, p2_fast;
 134         } p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 152                       const char *name, u32 reg, int ref_freq)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         mutex_lock(&dev_priv->sb_lock);
 158         val = vlv_cck_read(dev_priv, reg);
 159         mutex_unlock(&dev_priv->sb_lock);
 160
 161         divider = val & CCK_FREQUENCY_VALUES;
 162
 163         WARN((val & CCK_FREQUENCY_STATUS) !=
 164              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 165              "%s change in progress\n", name);
 166
 167         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 168 }
 169
 170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 171                            const char *name, u32 reg)
 172 {
 173         if (dev_priv->hpll_freq == 0)
 174                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 175
 176         return vlv_get_cck_clock(dev_priv, name, reg,
 177                                  dev_priv->hpll_freq);
 178 }
 179
 180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 181 {
 182         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 183                 return;
 184
 185         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 186                                                       CCK_CZ_CLOCK_CONTROL);
 187
 188         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 189 }
 190
 191 static inline u32 /* units of 100MHz */
 192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 193                     const struct intel_crtc_state *pipe_config)
 194 {
 195         if (HAS_DDI(dev_priv))
 196                 return pipe_config->port_clock; /* SPLL */
 197         else if (IS_GEN5(dev_priv))
 198                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 199         else
 200                 return 270000;
 201 }
 202
 203 static const struct intel_limit intel_limits_i8xx_dac = {
 204         .dot = { .min = 25000, .max = 350000 },
 205         .vco = { .min = 908000, .max = 1512000 },
 206         .n = { .min = 2, .max = 16 },
 207         .m = { .min = 96, .max = 140 },
 208         .m1 = { .min = 18, .max = 26 },
 209         .m2 = { .min = 6, .max = 16 },
 210         .p = { .min = 4, .max = 128 },
 211         .p1 = { .min = 2, .max = 33 },
 212         .p2 = { .dot_limit = 165000,
 213                 .p2_slow = 4, .p2_fast = 2 },
 214 };
 215
 216 static const struct intel_limit intel_limits_i8xx_dvo = {
 217         .dot = { .min = 25000, .max = 350000 },
 218         .vco = { .min = 908000, .max = 1512000 },
 219         .n = { .min = 2, .max = 16 },
 220         .m = { .min = 96, .max = 140 },
 221         .m1 = { .min = 18, .max = 26 },
 222         .m2 = { .min = 6, .max = 16 },
 223         .p = { .min = 4, .max = 128 },
 224         .p1 = { .min = 2, .max = 33 },
 225         .p2 = { .dot_limit = 165000,
 226                 .p2_slow = 4, .p2_fast = 4 },
 227 };
 228
 229 static const struct intel_limit intel_limits_i8xx_lvds = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 908000, .max = 1512000 },
 232         .n = { .min = 2, .max = 16 },
 233         .m = { .min = 96, .max = 140 },
 234         .m1 = { .min = 18, .max = 26 },
 235         .m2 = { .min = 6, .max = 16 },
 236         .p = { .min = 4, .max = 128 },
 237         .p1 = { .min = 1, .max = 6 },
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 14, .p2_fast = 7 },
 240 };
 241
 242 static const struct intel_limit intel_limits_i9xx_sdvo = {
 243         .dot = { .min = 20000, .max = 400000 },
 244         .vco = { .min = 1400000, .max = 2800000 },
 245         .n = { .min = 1, .max = 6 },
 246         .m = { .min = 70, .max = 120 },
 247         .m1 = { .min = 8, .max = 18 },
 248         .m2 = { .min = 3, .max = 7 },
 249         .p = { .min = 5, .max = 80 },
 250         .p1 = { .min = 1, .max = 8 },
 251         .p2 = { .dot_limit = 200000,
 252                 .p2_slow = 10, .p2_fast = 5 },
 253 };
 254
 255 static const struct intel_limit intel_limits_i9xx_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1400000, .max = 2800000 },
 258         .n = { .min = 1, .max = 6 },
 259         .m = { .min = 70, .max = 120 },
 260         .m1 = { .min = 8, .max = 18 },
 261         .m2 = { .min = 3, .max = 7 },
 262         .p = { .min = 7, .max = 98 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 7 },
 266 };
 267
 268
 269 static const struct intel_limit intel_limits_g4x_sdvo = {
 270         .dot = { .min = 25000, .max = 270000 },
 271         .vco = { .min = 1750000, .max = 3500000},
 272         .n = { .min = 1, .max = 4 },
 273         .m = { .min = 104, .max = 138 },
 274         .m1 = { .min = 17, .max = 23 },
 275         .m2 = { .min = 5, .max = 11 },
 276         .p = { .min = 10, .max = 30 },
 277         .p1 = { .min = 1, .max = 3},
 278         .p2 = { .dot_limit = 270000,
 279                 .p2_slow = 10,
 280                 .p2_fast = 10
 281         },
 282 };
 283
 284 static const struct intel_limit intel_limits_g4x_hdmi = {
 285         .dot = { .min = 22000, .max = 400000 },
 286         .vco = { .min = 1750000, .max = 3500000},
 287         .n = { .min = 1, .max = 4 },
 288         .m = { .min = 104, .max = 138 },
 289         .m1 = { .min = 16, .max = 23 },
 290         .m2 = { .min = 5, .max = 11 },
 291         .p = { .min = 5, .max = 80 },
 292         .p1 = { .min = 1, .max = 8},
 293         .p2 = { .dot_limit = 165000,
 294                 .p2_slow = 10, .p2_fast = 5 },
 295 };
 296
 297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 298         .dot = { .min = 20000, .max = 115000 },
 299         .vco = { .min = 1750000, .max = 3500000 },
 300         .n = { .min = 1, .max = 3 },
 301         .m = { .min = 104, .max = 138 },
 302         .m1 = { .min = 17, .max = 23 },
 303         .m2 = { .min = 5, .max = 11 },
 304         .p = { .min = 28, .max = 112 },
 305         .p1 = { .min = 2, .max = 8 },
 306         .p2 = { .dot_limit = 0,
 307                 .p2_slow = 14, .p2_fast = 14
 308         },
 309 };
 310
 311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 312         .dot = { .min = 80000, .max = 224000 },
 313         .vco = { .min = 1750000, .max = 3500000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 104, .max = 138 },
 316         .m1 = { .min = 17, .max = 23 },
 317         .m2 = { .min = 5, .max = 11 },
 318         .p = { .min = 14, .max = 42 },
 319         .p1 = { .min = 2, .max = 6 },
 320         .p2 = { .dot_limit = 0,
 321                 .p2_slow = 7, .p2_fast = 7
 322         },
 323 };
 324
 325 static const struct intel_limit intel_limits_pineview_sdvo = {
 326         .dot = { .min = 20000, .max = 400000},
 327         .vco = { .min = 1700000, .max = 3500000 },
 328         /* Pineview's Ncounter is a ring counter */
 329         .n = { .min = 3, .max = 6 },
 330         .m = { .min = 2, .max = 256 },
 331         /* Pineview only has one combined m divider, which we treat as m2. */
 332         .m1 = { .min = 0, .max = 0 },
 333         .m2 = { .min = 0, .max = 254 },
 334         .p = { .min = 5, .max = 80 },
 335         .p1 = { .min = 1, .max = 8 },
 336         .p2 = { .dot_limit = 200000,
 337                 .p2_slow = 10, .p2_fast = 5 },
 338 };
 339
 340 static const struct intel_limit intel_limits_pineview_lvds = {
 341         .dot = { .min = 20000, .max = 400000 },
 342         .vco = { .min = 1700000, .max = 3500000 },
 343         .n = { .min = 3, .max = 6 },
 344         .m = { .min = 2, .max = 256 },
 345         .m1 = { .min = 0, .max = 0 },
 346         .m2 = { .min = 0, .max = 254 },
 347         .p = { .min = 7, .max = 112 },
 348         .p1 = { .min = 1, .max = 8 },
 349         .p2 = { .dot_limit = 112000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 /* Ironlake / Sandybridge
 354  *
 355  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 356  * the range value for them is (actual_value - 2).
 357  */
 358 static const struct intel_limit intel_limits_ironlake_dac = {
 359         .dot = { .min = 25000, .max = 350000 },
 360         .vco = { .min = 1760000, .max = 3510000 },
 361         .n = { .min = 1, .max = 5 },
 362         .m = { .min = 79, .max = 127 },
 363         .m1 = { .min = 12, .max = 22 },
 364         .m2 = { .min = 5, .max = 9 },
 365         .p = { .min = 5, .max = 80 },
 366         .p1 = { .min = 1, .max = 8 },
 367         .p2 = { .dot_limit = 225000,
 368                 .p2_slow = 10, .p2_fast = 5 },
 369 };
 370
 371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 372         .dot = { .min = 25000, .max = 350000 },
 373         .vco = { .min = 1760000, .max = 3510000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 79, .max = 118 },
 376         .m1 = { .min = 12, .max = 22 },
 377         .m2 = { .min = 5, .max = 9 },
 378         .p = { .min = 28, .max = 112 },
 379         .p1 = { .min = 2, .max = 8 },
 380         .p2 = { .dot_limit = 225000,
 381                 .p2_slow = 14, .p2_fast = 14 },
 382 };
 383
 384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 385         .dot = { .min = 25000, .max = 350000 },
 386         .vco = { .min = 1760000, .max = 3510000 },
 387         .n = { .min = 1, .max = 3 },
 388         .m = { .min = 79, .max = 127 },
 389         .m1 = { .min = 12, .max = 22 },
 390         .m2 = { .min = 5, .max = 9 },
 391         .p = { .min = 14, .max = 56 },
 392         .p1 = { .min = 2, .max = 8 },
 393         .p2 = { .dot_limit = 225000,
 394                 .p2_slow = 7, .p2_fast = 7 },
 395 };
 396
 397 /* LVDS 100mhz refclk limits. */
 398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 399         .dot = { .min = 25000, .max = 350000 },
 400         .vco = { .min = 1760000, .max = 3510000 },
 401         .n = { .min = 1, .max = 2 },
 402         .m = { .min = 79, .max = 126 },
 403         .m1 = { .min = 12, .max = 22 },
 404         .m2 = { .min = 5, .max = 9 },
 405         .p = { .min = 28, .max = 112 },
 406         .p1 = { .min = 2, .max = 8 },
 407         .p2 = { .dot_limit = 225000,
 408                 .p2_slow = 14, .p2_fast = 14 },
 409 };
 410
 411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 412         .dot = { .min = 25000, .max = 350000 },
 413         .vco = { .min = 1760000, .max = 3510000 },
 414         .n = { .min = 1, .max = 3 },
 415         .m = { .min = 79, .max = 126 },
 416         .m1 = { .min = 12, .max = 22 },
 417         .m2 = { .min = 5, .max = 9 },
 418         .p = { .min = 14, .max = 42 },
 419         .p1 = { .min = 2, .max = 6 },
 420         .p2 = { .dot_limit = 225000,
 421                 .p2_slow = 7, .p2_fast = 7 },
 422 };
 423
 424 static const struct intel_limit intel_limits_vlv = {
 425          /*
 426           * These are the data rate limits (measured in fast clocks)
 427           * since those are the strictest limits we have. The fast
 428           * clock and actual rate limits are more relaxed, so checking
 429           * them would make no difference.
 430           */
 431         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 432         .vco = { .min = 4000000, .max = 6000000 },
 433         .n = { .min = 1, .max = 7 },
 434         .m1 = { .min = 2, .max = 3 },
 435         .m2 = { .min = 11, .max = 156 },
 436         .p1 = { .min = 2, .max = 3 },
 437         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 438 };
 439
 440 static const struct intel_limit intel_limits_chv = {
 441         /*
 442          * These are the data rate limits (measured in fast clocks)
 443          * since those are the strictest limits we have.  The fast
 444          * clock and actual rate limits are more relaxed, so checking
 445          * them would make no difference.
 446          */
 447         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 448         .vco = { .min = 4800000, .max = 6480000 },
 449         .n = { .min = 1, .max = 1 },
 450         .m1 = { .min = 2, .max = 2 },
 451         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 452         .p1 = { .min = 2, .max = 4 },
 453         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 454 };
 455
 456 static const struct intel_limit intel_limits_bxt = {
 457         /* FIXME: find real dot limits */
 458         .dot = { .min = 0, .max = INT_MAX },
 459         .vco = { .min = 4800000, .max = 6700000 },
 460         .n = { .min = 1, .max = 1 },
 461         .m1 = { .min = 2, .max = 2 },
 462         /* FIXME: find real m2 limits */
 463         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 464         .p1 = { .min = 2, .max = 4 },
 465         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 466 };
 467
 468 static bool
 469 needs_modeset(struct drm_crtc_state *state)
 470 {
 471         return drm_atomic_crtc_needs_modeset(state);
 472 }
 473
 474 /*
 475  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 476  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 477  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 478  * The helpers' return value is the rate of the clock that is fed to the
 479  * display engine's pipe which can be the above fast dot clock rate or a
 480  * divided-down version of it.
 481  */
 482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 484 {
 485         clock->m = clock->m2 + 2;
 486         clock->p = clock->p1 * clock->p2;
 487         if (WARN_ON(clock->n == 0 || clock->p == 0))
 488                 return 0;
 489         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 490         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 491
 492         return clock->dot;
 493 }
 494
 495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 496 {
 497         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 498 }
 499
 500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 501 {
 502         clock->m = i9xx_dpll_compute_m(clock);
 503         clock->p = clock->p1 * clock->p2;
 504         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 505                 return 0;
 506         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 507         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 508
 509         return clock->dot;
 510 }
 511
 512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 513 {
 514         clock->m = clock->m1 * clock->m2;
 515         clock->p = clock->p1 * clock->p2;
 516         if (WARN_ON(clock->n == 0 || clock->p == 0))
 517                 return 0;
 518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 520
 521         return clock->dot / 5;
 522 }
 523
 524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 525 {
 526         clock->m = clock->m1 * clock->m2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return 0;
 530         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 531                         clock->n << 22);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot / 5;
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 544                                const struct intel_limit *limit,
 545                                const struct dpll *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 557             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 558                 if (clock->m1 <= clock->m2)
 559                         INTELPllInvalid("m1 <= m2\n");
 560
 561         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 562             !IS_GEN9_LP(dev_priv)) {
 563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 564                         INTELPllInvalid("p out of range\n");
 565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 566                         INTELPllInvalid("m out of range\n");
 567         }
 568
 569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 570                 INTELPllInvalid("vco out of range\n");
 571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 572          * connector, etc., rather than just a single range.
 573          */
 574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 575                 INTELPllInvalid("dot out of range\n");
 576
 577         return true;
 578 }
 579
 580 static int
 581 i9xx_select_p2_div(const struct intel_limit *limit,
 582                    const struct intel_crtc_state *crtc_state,
 583                    int target)
 584 {
 585         struct drm_device *dev = crtc_state->base.crtc->dev;
 586
 587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         return limit->p2.p2_fast;
 595                 else
 596                         return limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         return limit->p2.p2_slow;
 600                 else
 601                         return limit->p2.p2_fast;
 602         }
 603 }
 604
 605 /*
 606  * Returns a set of divisors for the desired target clock with the given
 607  * refclk, or FALSE.  The returned values represent the clock equation:
 608  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 609  *
 610  * Target and reference clocks are specified in kHz.
 611  *
 612  * If match_clock is provided, then best_clock P divider must match the P
 613  * divider from @match_clock used for LVDS downclocking.
 614  */
 615 static bool
 616 i9xx_find_best_dpll(const struct intel_limit *limit,
 617                     struct intel_crtc_state *crtc_state,
 618                     int target, int refclk, struct dpll *match_clock,
 619                     struct dpll *best_clock)
 620 {
 621         struct drm_device *dev = crtc_state->base.crtc->dev;
 622         struct dpll clock;
 623         int err = target;
 624
 625         memset(best_clock, 0, sizeof(*best_clock));
 626
 627         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_calc_dpll_params(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(to_i915(dev),
 643                                                                 limit,
 644                                                                 &clock))
 645                                                 continue;
 646                                         if (match_clock &&
 647                                             clock.p != match_clock->p)
 648                                                 continue;
 649
 650                                         this_err = abs(clock.dot - target);
 651                                         if (this_err < err) {
 652                                                 *best_clock = clock;
 653                                                 err = this_err;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         return (err != target);
 661 }
 662
 663 /*
 664  * Returns a set of divisors for the desired target clock with the given
 665  * refclk, or FALSE.  The returned values represent the clock equation:
 666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 667  *
 668  * Target and reference clocks are specified in kHz.
 669  *
 670  * If match_clock is provided, then best_clock P divider must match the P
 671  * divider from @match_clock used for LVDS downclocking.
 672  */
 673 static bool
 674 pnv_find_best_dpll(const struct intel_limit *limit,
 675                    struct intel_crtc_state *crtc_state,
 676                    int target, int refclk, struct dpll *match_clock,
 677                    struct dpll *best_clock)
 678 {
 679         struct drm_device *dev = crtc_state->base.crtc->dev;
 680         struct dpll clock;
 681         int err = target;
 682
 683         memset(best_clock, 0, sizeof(*best_clock));
 684
 685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pnv_calc_dpll_params(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(to_i915(dev),
 699                                                                 limit,
 700                                                                 &clock))
 701                                                 continue;
 702                                         if (match_clock &&
 703                                             clock.p != match_clock->p)
 704                                                 continue;
 705
 706                                         this_err = abs(clock.dot - target);
 707                                         if (this_err < err) {
 708                                                 *best_clock = clock;
 709                                                 err = this_err;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715
 716         return (err != target);
 717 }
 718
 719 /*
 720  * Returns a set of divisors for the desired target clock with the given
 721  * refclk, or FALSE.  The returned values represent the clock equation:
 722  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 723  *
 724  * Target and reference clocks are specified in kHz.
 725  *
 726  * If match_clock is provided, then best_clock P divider must match the P
 727  * divider from @match_clock used for LVDS downclocking.
 728  */
 729 static bool
 730 g4x_find_best_dpll(const struct intel_limit *limit,
 731                    struct intel_crtc_state *crtc_state,
 732                    int target, int refclk, struct dpll *match_clock,
 733                    struct dpll *best_clock)
 734 {
 735         struct drm_device *dev = crtc_state->base.crtc->dev;
 736         struct dpll clock;
 737         int max_n;
 738         bool found = false;
 739         /* approximately equals target * 0.00585 */
 740         int err_most = (target >> 8) + (target >> 9);
 741
 742         memset(best_clock, 0, sizeof(*best_clock));
 743
 744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 745
 746         max_n = limit->n.max;
 747         /* based on hardware requirement, prefer smaller n to precision */
 748         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 749                 /* based on hardware requirement, prefere larger m1,m2 */
 750                 for (clock.m1 = limit->m1.max;
 751                      clock.m1 >= limit->m1.min; clock.m1--) {
 752                         for (clock.m2 = limit->m2.max;
 753                              clock.m2 >= limit->m2.min; clock.m2--) {
 754                                 for (clock.p1 = limit->p1.max;
 755                                      clock.p1 >= limit->p1.min; clock.p1--) {
 756                                         int this_err;
 757
 758                                         i9xx_calc_dpll_params(refclk, &clock);
 759                                         if (!intel_PLL_is_valid(to_i915(dev),
 760                                                                 limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 /*
 779  * Check if the calculated PLL configuration is more optimal compared to the
 780  * best configuration and error found so far. Return the calculated error.
 781  */
 782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 783                                const struct dpll *calculated_clock,
 784                                const struct dpll *best_clock,
 785                                unsigned int best_error_ppm,
 786                                unsigned int *error_ppm)
 787 {
 788         /*
 789          * For CHV ignore the error and consider only the P value.
 790          * Prefer a bigger P value based on HW requirements.
 791          */
 792         if (IS_CHERRYVIEW(to_i915(dev))) {
 793                 *error_ppm = 0;
 794
 795                 return calculated_clock->p > best_clock->p;
 796         }
 797
 798         if (WARN_ON_ONCE(!target_freq))
 799                 return false;
 800
 801         *error_ppm = div_u64(1000000ULL *
 802                                 abs(target_freq - calculated_clock->dot),
 803                              target_freq);
 804         /*
 805          * Prefer a better P value over a better (smaller) error if the error
 806          * is small. Ensure this preference for future configurations too by
 807          * setting the error to 0.
 808          */
 809         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 810                 *error_ppm = 0;
 811
 812                 return true;
 813         }
 814
 815         return *error_ppm + 10 < best_error_ppm;
 816 }
 817
 818 /*
 819  * Returns a set of divisors for the desired target clock with the given
 820  * refclk, or FALSE.  The returned values represent the clock equation:
 821  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 822  */
 823 static bool
 824 vlv_find_best_dpll(const struct intel_limit *limit,
 825                    struct intel_crtc_state *crtc_state,
 826                    int target, int refclk, struct dpll *match_clock,
 827                    struct dpll *best_clock)
 828 {
 829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 830         struct drm_device *dev = crtc->base.dev;
 831         struct dpll clock;
 832         unsigned int bestppm = 1000000;
 833         /* min update 19.2 MHz */
 834         int max_n = min(limit->n.max, refclk / 19200);
 835         bool found = false;
 836
 837         target *= 5; /* fast clock */
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         /* based on hardware requirement, prefer smaller n to precision */
 842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 843                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 844                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 845                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 846                                 clock.p = clock.p1 * clock.p2;
 847                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 848                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 849                                         unsigned int ppm;
 850
 851                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 852                                                                      refclk * clock.m1);
 853
 854                                         vlv_calc_dpll_params(refclk, &clock);
 855
 856                                         if (!intel_PLL_is_valid(to_i915(dev),
 857                                                                 limit,
 858                                                                 &clock))
 859                                                 continue;
 860
 861                                         if (!vlv_PLL_is_optimal(dev, target,
 862                                                                 &clock,
 863                                                                 best_clock,
 864                                                                 bestppm, &ppm))
 865                                                 continue;
 866
 867                                         *best_clock = clock;
 868                                         bestppm = ppm;
 869                                         found = true;
 870                                 }
 871                         }
 872                 }
 873         }
 874
 875         return found;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 chv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         unsigned int best_error_ppm;
 892         struct dpll clock;
 893         uint64_t m2;
 894         int found = false;
 895
 896         memset(best_clock, 0, sizeof(*best_clock));
 897         best_error_ppm = 1000000;
 898
 899         /*
 900          * Based on hardware doc, the n always set to 1, and m1 always
 901          * set to 2.  If requires to support 200Mhz refclk, we need to
 902          * revisit this because n may not 1 anymore.
 903          */
 904         clock.n = 1, clock.m1 = 2;
 905         target *= 5;    /* fast clock */
 906
 907         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 908                 for (clock.p2 = limit->p2.p2_fast;
 909                                 clock.p2 >= limit->p2.p2_slow;
 910                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 911                         unsigned int error_ppm;
 912
 913                         clock.p = clock.p1 * clock.p2;
 914
 915                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 916                                         clock.n) << 22, refclk * clock.m1);
 917
 918                         if (m2 > INT_MAX/clock.m1)
 919                                 continue;
 920
 921                         clock.m2 = m2;
 922
 923                         chv_calc_dpll_params(refclk, &clock);
 924
 925                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 926                                 continue;
 927
 928                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 929                                                 best_error_ppm, &error_ppm))
 930                                 continue;
 931
 932                         *best_clock = clock;
 933                         best_error_ppm = error_ppm;
 934                         found = true;
 935                 }
 936         }
 937
 938         return found;
 939 }
 940
 941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 942                         struct dpll *best_clock)
 943 {
 944         int refclk = 100000;
 945         const struct intel_limit *limit = &intel_limits_bxt;
 946
 947         return chv_find_best_dpll(limit, crtc_state,
 948                                   target_clock, refclk, NULL, best_clock);
 949 }
 950
 951 bool intel_crtc_active(struct intel_crtc *crtc)
 952 {
 953         /* Be paranoid as we can arrive here with only partial
 954          * state retrieved from the hardware during setup.
 955          *
 956          * We can ditch the adjusted_mode.crtc_clock check as soon
 957          * as Haswell has gained clock readout/fastboot support.
 958          *
 959          * We can ditch the crtc->primary->fb check as soon as we can
 960          * properly reconstruct framebuffers.
 961          *
 962          * FIXME: The intel_crtc->active here should be switched to
 963          * crtc->state->active once we have proper CRTC states wired up
 964          * for atomic.
 965          */
 966         return crtc->active && crtc->base.primary->state->fb &&
 967                 crtc->config->base.adjusted_mode.crtc_clock;
 968 }
 969
 970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 971                                              enum pipe pipe)
 972 {
 973         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 974
 975         return crtc->config->cpu_transcoder;
 976 }
 977
 978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
 979 {
 980         i915_reg_t reg = PIPEDSL(pipe);
 981         u32 line1, line2;
 982         u32 line_mask;
 983
 984         if (IS_GEN2(dev_priv))
 985                 line_mask = DSL_LINEMASK_GEN2;
 986         else
 987                 line_mask = DSL_LINEMASK_GEN3;
 988
 989         line1 = I915_READ(reg) & line_mask;
 990         msleep(5);
 991         line2 = I915_READ(reg) & line_mask;
 992
 993         return line1 == line2;
 994 }
 995
 996 /*
 997  * intel_wait_for_pipe_off - wait for pipe to turn off
 998  * @crtc: crtc whose pipe to wait for
 999  *
1000  * After disabling a pipe, we can't wait for vblank in the usual way,
1001  * spinning on the vblank interrupt status bit, since we won't actually
1002  * see an interrupt when the pipe is disabled.
1003  *
1004  * On Gen4 and above:
1005  *   wait for the pipe register state bit to turn off
1006  *
1007  * Otherwise:
1008  *   wait for the display line value to settle (it usually
1009  *   ends up stopping at the start of the next frame).
1010  *
1011  */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016         enum pipe pipe = crtc->pipe;
1017
1018         if (INTEL_GEN(dev_priv) >= 4) {
1019                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021                 /* Wait for the Pipe State to go off */
1022                 if (intel_wait_for_register(dev_priv,
1023                                             reg, I965_PIPECONF_ACTIVE, 0,
1024                                             100))
1025                         WARN(1, "pipe_off wait timed out\n");
1026         } else {
1027                 /* Wait for the display line to settle */
1028                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029                         WARN(1, "pipe_off wait timed out\n");
1030         }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035                 enum pipe pipe, bool state)
1036 {
1037         u32 val;
1038         bool cur_state;
1039
1040         val = I915_READ(DPLL(pipe));
1041         cur_state = !!(val & DPLL_VCO_ENABLE);
1042         I915_STATE_WARN(cur_state != state,
1043              "PLL state assertion failure (expected %s, current %s)\n",
1044                         onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050         u32 val;
1051         bool cur_state;
1052
1053         mutex_lock(&dev_priv->sb_lock);
1054         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055         mutex_unlock(&dev_priv->sb_lock);
1056
1057         cur_state = val & DSI_PLL_VCO_EN;
1058         I915_STATE_WARN(cur_state != state,
1059              "DSI PLL state assertion failure (expected %s, current %s)\n",
1060                         onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064                           enum pipe pipe, bool state)
1065 {
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074         } else {
1075                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         I915_STATE_WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080                         onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         u32 val;
1089         bool cur_state;
1090
1091         val = I915_READ(FDI_RX_CTL(pipe));
1092         cur_state = !!(val & FDI_RX_ENABLE);
1093         I915_STATE_WARN(cur_state != state,
1094              "FDI RX state assertion failure (expected %s, current %s)\n",
1095                         onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101                                       enum pipe pipe)
1102 {
1103         u32 val;
1104
1105         /* ILK FDI PLL is always enabled */
1106         if (IS_GEN5(dev_priv))
1107                 return;
1108
1109         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110         if (HAS_DDI(dev_priv))
1111                 return;
1112
1113         val = I915_READ(FDI_TX_CTL(pipe));
1114         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118                        enum pipe pipe, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         val = I915_READ(FDI_RX_CTL(pipe));
1124         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127                         onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132         i915_reg_t pp_reg;
1133         u32 val;
1134         enum pipe panel_pipe = PIPE_A;
1135         bool locked = true;
1136
1137         if (WARN_ON(HAS_DDI(dev_priv)))
1138                 return;
1139
1140         if (HAS_PCH_SPLIT(dev_priv)) {
1141                 u32 port_sel;
1142
1143                 pp_reg = PP_CONTROL(0);
1144                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148                         panel_pipe = PIPE_B;
1149                 /* XXX: else fix for eDP */
1150         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151                 /* presumably write lock depends on pipe, not port select */
1152                 pp_reg = PP_CONTROL(pipe);
1153                 panel_pipe = pipe;
1154         } else {
1155                 pp_reg = PP_CONTROL(0);
1156                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157                         panel_pipe = PIPE_B;
1158         }
1159
1160         val = I915_READ(pp_reg);
1161         if (!(val & PANEL_POWER_ON) ||
1162             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163                 locked = false;
1164
1165         I915_STATE_WARN(panel_pipe == pipe && locked,
1166              "panel assertion failure, pipe %c regs locked\n",
1167              pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171                           enum pipe pipe, bool state)
1172 {
1173         bool cur_state;
1174
1175         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177         else
1178                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180         I915_STATE_WARN(cur_state != state,
1181              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182                         pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188                  enum pipe pipe, bool state)
1189 {
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193         enum intel_display_power_domain power_domain;
1194
1195         /* if we need the pipe quirk it must be always on */
1196         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553         assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555         /* PLL is protected by panel, make sure we can write it */
1556         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557                 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559         /* Enable DVO 2x clock on both PLLs if necessary */
1560         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561                 /*
1562                  * It appears to be important that we don't enable this
1563                  * for the current pipe before otherwise configuring the
1564                  * PLL. No idea how this should be handled if multiple
1565                  * DVO outputs are enabled simultaneosly.
1566                  */
1567                 dpll |= DPLL_DVO_2X_MODE;
1568                 I915_WRITE(DPLL(!crtc->pipe),
1569                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570         }
1571
1572         /*
1573          * Apparently we need to have VGA mode enabled prior to changing
1574          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575          * dividers, even though the register value does change.
1576          */
1577         I915_WRITE(reg, 0);
1578
1579         I915_WRITE(reg, dpll);
1580
1581         /* Wait for the clocks to stabilize. */
1582         POSTING_READ(reg);
1583         udelay(150);
1584
1585         if (INTEL_GEN(dev_priv) >= 4) {
1586                 I915_WRITE(DPLL_MD(crtc->pipe),
1587                            crtc->config->dpll_hw_state.dpll_md);
1588         } else {
1589                 /* The pixel multiplier can only be updated once the
1590                  * DPLL is enabled and the clocks are stable.
1591                  *
1592                  * So write it again.
1593                  */
1594                 I915_WRITE(reg, dpll);
1595         }
1596
1597         /* We do this three times for luck */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604         I915_WRITE(reg, dpll);
1605         POSTING_READ(reg);
1606         udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610  * i9xx_disable_pll - disable a PLL
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe PLL to disable
1613  *
1614  * Disable the PLL for @pipe, making sure the pipe is off first.
1615  *
1616  * Note!  This is for pre-ILK only.
1617  */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621         enum pipe pipe = crtc->pipe;
1622
1623         /* Disable DVO 2x clock on both PLLs if necessary */
1624         if (IS_I830(dev_priv) &&
1625             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626             !intel_num_dvo_pipes(dev_priv)) {
1627                 I915_WRITE(DPLL(PIPE_B),
1628                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629                 I915_WRITE(DPLL(PIPE_A),
1630                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Don't disable pipe or pipe PLLs if needed */
1634         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636                 return;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642         POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647         u32 val;
1648
1649         /* Make sure the pipe isn't still relying on us */
1650         assert_pipe_disabled(dev_priv, pipe);
1651
1652         val = DPLL_INTEGRATED_REF_CLK_VLV |
1653                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654         if (pipe != PIPE_A)
1655                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657         I915_WRITE(DPLL(pipe), val);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664         u32 val;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         val = DPLL_SSC_REF_CLK_CHV |
1670                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671         if (pipe != PIPE_A)
1672                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677         mutex_lock(&dev_priv->sb_lock);
1678
1679         /* Disable 10bit clock to display controller */
1680         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681         val &= ~DPIO_DCLKP_EN;
1682         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684         mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688                          struct intel_digital_port *dport,
1689                          unsigned int expected_mask)
1690 {
1691         u32 port_mask;
1692         i915_reg_t dpll_reg;
1693
1694         switch (dport->port) {
1695         case PORT_B:
1696                 port_mask = DPLL_PORTB_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 break;
1699         case PORT_C:
1700                 port_mask = DPLL_PORTC_READY_MASK;
1701                 dpll_reg = DPLL(0);
1702                 expected_mask <<= 4;
1703                 break;
1704         case PORT_D:
1705                 port_mask = DPLL_PORTD_READY_MASK;
1706                 dpll_reg = DPIO_PHY_STATUS;
1707                 break;
1708         default:
1709                 BUG();
1710         }
1711
1712         if (intel_wait_for_register(dev_priv,
1713                                     dpll_reg, port_mask, expected_mask,
1714                                     1000))
1715                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720                                            enum pipe pipe)
1721 {
1722         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723                                                                 pipe);
1724         i915_reg_t reg;
1725         uint32_t val, pipeconf_val;
1726
1727         /* Make sure PCH DPLL is enabled */
1728         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, pipe);
1732         assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_CPT(dev_priv)) {
1735                 /* Workaround: Set the timing override bit before enabling the
1736                  * pch transcoder. */
1737                 reg = TRANS_CHICKEN2(pipe);
1738                 val = I915_READ(reg);
1739                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740                 I915_WRITE(reg, val);
1741         }
1742
1743         reg = PCH_TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         if (HAS_PCH_IBX(dev_priv)) {
1748                 /*
1749                  * Make the BPC in transcoder be consistent with
1750                  * that in pipeconf reg. For HDMI we must use 8bpc
1751                  * here for both 8bpc and 12bpc.
1752                  */
1753                 val &= ~PIPECONF_BPC_MASK;
1754                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755                         val |= PIPECONF_8BPC;
1756                 else
1757                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1758         }
1759
1760         val &= ~TRANS_INTERLACE_MASK;
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762                 if (HAS_PCH_IBX(dev_priv) &&
1763                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764                         val |= TRANS_LEGACY_INTERLACED_ILK;
1765                 else
1766                         val |= TRANS_INTERLACED;
1767         else
1768                 val |= TRANS_PROGRESSIVE;
1769
1770         I915_WRITE(reg, val | TRANS_ENABLE);
1771         if (intel_wait_for_register(dev_priv,
1772                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773                                     100))
1774                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778                                       enum transcoder cpu_transcoder)
1779 {
1780         u32 val, pipeconf_val;
1781
1782         /* FDI must be feeding us bits for PCH ports */
1783         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786         /* Workaround: set timing override bit. */
1787         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791         val = TRANS_ENABLE;
1792         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795             PIPECONF_INTERLACED_ILK)
1796                 val |= TRANS_INTERLACED;
1797         else
1798                 val |= TRANS_PROGRESSIVE;
1799
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         if (intel_wait_for_register(dev_priv,
1802                                     LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE,
1804                                     TRANS_STATE_ENABLE,
1805                                     100))
1806                 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810                                             enum pipe pipe)
1811 {
1812         i915_reg_t reg;
1813         uint32_t val;
1814
1815         /* FDI relies on the transcoder */
1816         assert_fdi_tx_disabled(dev_priv, pipe);
1817         assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819         /* Ports must be off as well */
1820         assert_pch_ports_disabled(dev_priv, pipe);
1821
1822         reg = PCH_TRANSCONF(pipe);
1823         val = I915_READ(reg);
1824         val &= ~TRANS_ENABLE;
1825         I915_WRITE(reg, val);
1826         /* wait for PCH transcoder off, transcoder state */
1827         if (intel_wait_for_register(dev_priv,
1828                                     reg, TRANS_STATE_ENABLE, 0,
1829                                     50))
1830                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832         if (HAS_PCH_CPT(dev_priv)) {
1833                 /* Workaround: Clear the timing override chicken bit again. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843         u32 val;
1844
1845         val = I915_READ(LPT_TRANSCONF);
1846         val &= ~TRANS_ENABLE;
1847         I915_WRITE(LPT_TRANSCONF, val);
1848         /* wait for PCH transcoder off, transcoder state */
1849         if (intel_wait_for_register(dev_priv,
1850                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851                                     50))
1852                 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854         /* Workaround: clear timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864         WARN_ON(!crtc->config->has_pch_encoder);
1865
1866         if (HAS_PCH_LPT(dev_priv))
1867                 return TRANSCODER_A;
1868         else
1869                 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873  * intel_enable_pipe - enable a pipe, asserting requirements
1874  * @crtc: crtc responsible for the pipe
1875  *
1876  * Enable @crtc's pipe, making sure that various hardware specific requirements
1877  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878  */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881         struct drm_device *dev = crtc->base.dev;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         enum pipe pipe = crtc->pipe;
1884         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885         i915_reg_t reg;
1886         u32 val;
1887
1888         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890         assert_planes_disabled(dev_priv, pipe);
1891         assert_cursor_disabled(dev_priv, pipe);
1892         assert_sprites_disabled(dev_priv, pipe);
1893
1894         /*
1895          * A pipe without a PLL won't actually be able to drive bits from
1896          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1897          * need the check.
1898          */
1899         if (HAS_GMCH_DISPLAY(dev_priv)) {
1900                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901                         assert_dsi_pll_enabled(dev_priv);
1902                 else
1903                         assert_pll_enabled(dev_priv, pipe);
1904         } else {
1905                 if (crtc->config->has_pch_encoder) {
1906                         /* if driving the PCH, we need FDI enabled */
1907                         assert_fdi_rx_pll_enabled(dev_priv,
1908                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1909                         assert_fdi_tx_pll_enabled(dev_priv,
1910                                                   (enum pipe) cpu_transcoder);
1911                 }
1912                 /* FIXME: assert CPU port conditions for SNB+ */
1913         }
1914
1915         reg = PIPECONF(cpu_transcoder);
1916         val = I915_READ(reg);
1917         if (val & PIPECONF_ENABLE) {
1918                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920                 return;
1921         }
1922
1923         I915_WRITE(reg, val | PIPECONF_ENABLE);
1924         POSTING_READ(reg);
1925
1926         /*
1927          * Until the pipe starts DSL will read as 0, which would cause
1928          * an apparent vblank timestamp jump, which messes up also the
1929          * frame count when it's derived from the timestamps. So let's
1930          * wait for the pipe to start properly before we call
1931          * drm_crtc_vblank_on()
1932          */
1933         if (dev->max_vblank_count == 0 &&
1934             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939  * intel_disable_pipe - disable a pipe, asserting requirements
1940  * @crtc: crtc whose pipes is to be disabled
1941  *
1942  * Disable the pipe of @crtc, making sure that various hardware
1943  * specific requirements are met, if applicable, e.g. plane
1944  * disabled, panel fitter off, etc.
1945  *
1946  * Will wait until the pipe has shut down before returning.
1947  */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952         enum pipe pipe = crtc->pipe;
1953         i915_reg_t reg;
1954         u32 val;
1955
1956         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958         /*
1959          * Make sure planes won't keep trying to pump pixels to us,
1960          * or we might hang the display.
1961          */
1962         assert_planes_disabled(dev_priv, pipe);
1963         assert_cursor_disabled(dev_priv, pipe);
1964         assert_sprites_disabled(dev_priv, pipe);
1965
1966         reg = PIPECONF(cpu_transcoder);
1967         val = I915_READ(reg);
1968         if ((val & PIPECONF_ENABLE) == 0)
1969                 return;
1970
1971         /*
1972          * Double wide has implications for planes
1973          * so best keep it disabled when not needed.
1974          */
1975         if (crtc->config->double_wide)
1976                 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978         /* Don't disable pipe or pipe PLLs if needed */
1979         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981                 val &= ~PIPECONF_ENABLE;
1982
1983         I915_WRITE(reg, val);
1984         if ((val & PIPECONF_ENABLE) == 0)
1985                 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990         return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997         unsigned int cpp = fb->format->cpp[plane];
1998
1999         switch (fb->modifier) {
2000         case DRM_FORMAT_MOD_LINEAR:
2001                 return cpp;
2002         case I915_FORMAT_MOD_X_TILED:
2003                 if (IS_GEN2(dev_priv))
2004                         return 128;
2005                 else
2006                         return 512;
2007         case I915_FORMAT_MOD_Y_TILED:
2008                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009                         return 128;
2010                 else
2011                         return 512;
2012         case I915_FORMAT_MOD_Yf_TILED:
2013                 switch (cpp) {
2014                 case 1:
2015                         return 64;
2016                 case 2:
2017                 case 4:
2018                         return 128;
2019                 case 8:
2020                 case 16:
2021                         return 256;
2022                 default:
2023                         MISSING_CASE(cpp);
2024                         return cpp;
2025                 }
2026                 break;
2027         default:
2028                 MISSING_CASE(fb->modifier);
2029                 return cpp;
2030         }
2031 }
2032
2033 static unsigned int
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2035 {
2036         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2037                 return 1;
2038         else
2039                 return intel_tile_size(to_i915(fb->dev)) /
2040                         intel_tile_width_bytes(fb, plane);
2041 }
2042
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045                             unsigned int *tile_width,
2046                             unsigned int *tile_height)
2047 {
2048         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049         unsigned int cpp = fb->format->cpp[plane];
2050
2051         *tile_width = tile_width_bytes / cpp;
2052         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2053 }
2054
2055 unsigned int
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057                       int plane, unsigned int height)
2058 {
2059         unsigned int tile_height = intel_tile_height(fb, plane);
2060
2061         return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066         unsigned int size = 0;
2067         int i;
2068
2069         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072         return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077                         const struct drm_framebuffer *fb,
2078                         unsigned int rotation)
2079 {
2080         view->type = I915_GGTT_VIEW_NORMAL;
2081         if (drm_rotation_90_or_270(rotation)) {
2082                 view->type = I915_GGTT_VIEW_ROTATED;
2083                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084         }
2085 }
2086
2087 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089         if (IS_I830(dev_priv))
2090                 return 16 * 1024;
2091         else if (IS_I85X(dev_priv))
2092                 return 256;
2093         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2094                 return 32;
2095         else
2096                 return 4 * 1024;
2097 }
2098
2099 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2100 {
2101         if (INTEL_INFO(dev_priv)->gen >= 9)
2102                 return 256 * 1024;
2103         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2104                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2105                 return 128 * 1024;
2106         else if (INTEL_INFO(dev_priv)->gen >= 4)
2107                 return 4 * 1024;
2108         else
2109                 return 0;
2110 }
2111
2112 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2113                                          int plane)
2114 {
2115         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2116
2117         /* AUX_DIST needs only 4K alignment */
2118         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2119                 return 4096;
2120
2121         switch (fb->modifier) {
2122         case DRM_FORMAT_MOD_LINEAR:
2123                 return intel_linear_alignment(dev_priv);
2124         case I915_FORMAT_MOD_X_TILED:
2125                 if (INTEL_GEN(dev_priv) >= 9)
2126                         return 256 * 1024;
2127                 return 0;
2128         case I915_FORMAT_MOD_Y_TILED:
2129         case I915_FORMAT_MOD_Yf_TILED:
2130                 return 1 * 1024 * 1024;
2131         default:
2132                 MISSING_CASE(fb->modifier);
2133                 return 0;
2134         }
2135 }
2136
2137 struct i915_vma *
2138 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2139 {
2140         struct drm_device *dev = fb->dev;
2141         struct drm_i915_private *dev_priv = to_i915(dev);
2142         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2143         struct i915_ggtt_view view;
2144         struct i915_vma *vma;
2145         u32 alignment;
2146
2147         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2148
2149         alignment = intel_surf_alignment(fb, 0);
2150
2151         intel_fill_fb_ggtt_view(&view, fb, rotation);
2152
2153         /* Note that the w/a also requires 64 PTE of padding following the
2154          * bo. We currently fill all unused PTE with the shadow page and so
2155          * we should always have valid PTE following the scanout preventing
2156          * the VT-d warning.
2157          */
2158         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2159                 alignment = 256 * 1024;
2160
2161         /*
2162          * Global gtt pte registers are special registers which actually forward
2163          * writes to a chunk of system memory. Which means that there is no risk
2164          * that the register values disappear as soon as we call
2165          * intel_runtime_pm_put(), so it is correct to wrap only the
2166          * pin/unpin/fence and not more.
2167          */
2168         intel_runtime_pm_get(dev_priv);
2169
2170         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2171         if (IS_ERR(vma))
2172                 goto err;
2173
2174         if (i915_vma_is_map_and_fenceable(vma)) {
2175                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2176                  * fence, whereas 965+ only requires a fence if using
2177                  * framebuffer compression.  For simplicity, we always, when
2178                  * possible, install a fence as the cost is not that onerous.
2179                  *
2180                  * If we fail to fence the tiled scanout, then either the
2181                  * modeset will reject the change (which is highly unlikely as
2182                  * the affected systems, all but one, do not have unmappable
2183                  * space) or we will not be able to enable full powersaving
2184                  * techniques (also likely not to apply due to various limits
2185                  * FBC and the like impose on the size of the buffer, which
2186                  * presumably we violated anyway with this unmappable buffer).
2187                  * Anyway, it is presumably better to stumble onwards with
2188                  * something and try to run the system in a "less than optimal"
2189                  * mode that matches the user configuration.
2190                  */
2191                 if (i915_vma_get_fence(vma) == 0)
2192                         i915_vma_pin_fence(vma);
2193         }
2194
2195         i915_vma_get(vma);
2196 err:
2197         intel_runtime_pm_put(dev_priv);
2198         return vma;
2199 }
2200
2201 void intel_unpin_fb_vma(struct i915_vma *vma)
2202 {
2203         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2204
2205         i915_vma_unpin_fence(vma);
2206         i915_gem_object_unpin_from_display_plane(vma);
2207         i915_vma_put(vma);
2208 }
2209
2210 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2211                           unsigned int rotation)
2212 {
2213         if (drm_rotation_90_or_270(rotation))
2214                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2215         else
2216                 return fb->pitches[plane];
2217 }
2218
2219 /*
2220  * Convert the x/y offsets into a linear offset.
2221  * Only valid with 0/180 degree rotation, which is fine since linear
2222  * offset is only used with linear buffers on pre-hsw and tiled buffers
2223  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2224  */
2225 u32 intel_fb_xy_to_linear(int x, int y,
2226                           const struct intel_plane_state *state,
2227                           int plane)
2228 {
2229         const struct drm_framebuffer *fb = state->base.fb;
2230         unsigned int cpp = fb->format->cpp[plane];
2231         unsigned int pitch = fb->pitches[plane];
2232
2233         return y * pitch + x * cpp;
2234 }
2235
2236 /*
2237  * Add the x/y offsets derived from fb->offsets[] to the user
2238  * specified plane src x/y offsets. The resulting x/y offsets
2239  * specify the start of scanout from the beginning of the gtt mapping.
2240  */
2241 void intel_add_fb_offsets(int *x, int *y,
2242                           const struct intel_plane_state *state,
2243                           int plane)
2244
2245 {
2246         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2247         unsigned int rotation = state->base.rotation;
2248
2249         if (drm_rotation_90_or_270(rotation)) {
2250                 *x += intel_fb->rotated[plane].x;
2251                 *y += intel_fb->rotated[plane].y;
2252         } else {
2253                 *x += intel_fb->normal[plane].x;
2254                 *y += intel_fb->normal[plane].y;
2255         }
2256 }
2257
2258 /*
2259  * Input tile dimensions and pitch must already be
2260  * rotated to match x and y, and in pixel units.
2261  */
2262 static u32 _intel_adjust_tile_offset(int *x, int *y,
2263                                      unsigned int tile_width,
2264                                      unsigned int tile_height,
2265                                      unsigned int tile_size,
2266                                      unsigned int pitch_tiles,
2267                                      u32 old_offset,
2268                                      u32 new_offset)
2269 {
2270         unsigned int pitch_pixels = pitch_tiles * tile_width;
2271         unsigned int tiles;
2272
2273         WARN_ON(old_offset & (tile_size - 1));
2274         WARN_ON(new_offset & (tile_size - 1));
2275         WARN_ON(new_offset > old_offset);
2276
2277         tiles = (old_offset - new_offset) / tile_size;
2278
2279         *y += tiles / pitch_tiles * tile_height;
2280         *x += tiles % pitch_tiles * tile_width;
2281
2282         /* minimize x in case it got needlessly big */
2283         *y += *x / pitch_pixels * tile_height;
2284         *x %= pitch_pixels;
2285
2286         return new_offset;
2287 }
2288
2289 /*
2290  * Adjust the tile offset by moving the difference into
2291  * the x/y offsets.
2292  */
2293 static u32 intel_adjust_tile_offset(int *x, int *y,
2294                                     const struct intel_plane_state *state, int plane,
2295                                     u32 old_offset, u32 new_offset)
2296 {
2297         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2298         const struct drm_framebuffer *fb = state->base.fb;
2299         unsigned int cpp = fb->format->cpp[plane];
2300         unsigned int rotation = state->base.rotation;
2301         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2302
2303         WARN_ON(new_offset > old_offset);
2304
2305         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2306                 unsigned int tile_size, tile_width, tile_height;
2307                 unsigned int pitch_tiles;
2308
2309                 tile_size = intel_tile_size(dev_priv);
2310                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2311
2312                 if (drm_rotation_90_or_270(rotation)) {
2313                         pitch_tiles = pitch / tile_height;
2314                         swap(tile_width, tile_height);
2315                 } else {
2316                         pitch_tiles = pitch / (tile_width * cpp);
2317                 }
2318
2319                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2320                                           tile_size, pitch_tiles,
2321                                           old_offset, new_offset);
2322         } else {
2323                 old_offset += *y * pitch + *x * cpp;
2324
2325                 *y = (old_offset - new_offset) / pitch;
2326                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2327         }
2328
2329         return new_offset;
2330 }
2331
2332 /*
2333  * Computes the linear offset to the base tile and adjusts
2334  * x, y. bytes per pixel is assumed to be a power-of-two.
2335  *
2336  * In the 90/270 rotated case, x and y are assumed
2337  * to be already rotated to match the rotated GTT view, and
2338  * pitch is the tile_height aligned framebuffer height.
2339  *
2340  * This function is used when computing the derived information
2341  * under intel_framebuffer, so using any of that information
2342  * here is not allowed. Anything under drm_framebuffer can be
2343  * used. This is why the user has to pass in the pitch since it
2344  * is specified in the rotated orientation.
2345  */
2346 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2347                                       int *x, int *y,
2348                                       const struct drm_framebuffer *fb, int plane,
2349                                       unsigned int pitch,
2350                                       unsigned int rotation,
2351                                       u32 alignment)
2352 {
2353         uint64_t fb_modifier = fb->modifier;
2354         unsigned int cpp = fb->format->cpp[plane];
2355         u32 offset, offset_aligned;
2356
2357         if (alignment)
2358                 alignment--;
2359
2360         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2361                 unsigned int tile_size, tile_width, tile_height;
2362                 unsigned int tile_rows, tiles, pitch_tiles;
2363
2364                 tile_size = intel_tile_size(dev_priv);
2365                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2366
2367                 if (drm_rotation_90_or_270(rotation)) {
2368                         pitch_tiles = pitch / tile_height;
2369                         swap(tile_width, tile_height);
2370                 } else {
2371                         pitch_tiles = pitch / (tile_width * cpp);
2372                 }
2373
2374                 tile_rows = *y / tile_height;
2375                 *y %= tile_height;
2376
2377                 tiles = *x / tile_width;
2378                 *x %= tile_width;
2379
2380                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2381                 offset_aligned = offset & ~alignment;
2382
2383                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2384                                           tile_size, pitch_tiles,
2385                                           offset, offset_aligned);
2386         } else {
2387                 offset = *y * pitch + *x * cpp;
2388                 offset_aligned = offset & ~alignment;
2389
2390                 *y = (offset & alignment) / pitch;
2391                 *x = ((offset & alignment) - *y * pitch) / cpp;
2392         }
2393
2394         return offset_aligned;
2395 }
2396
2397 u32 intel_compute_tile_offset(int *x, int *y,
2398                               const struct intel_plane_state *state,
2399                               int plane)
2400 {
2401         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2402         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2403         const struct drm_framebuffer *fb = state->base.fb;
2404         unsigned int rotation = state->base.rotation;
2405         int pitch = intel_fb_pitch(fb, plane, rotation);
2406         u32 alignment;
2407
2408         if (intel_plane->id == PLANE_CURSOR)
2409                 alignment = intel_cursor_alignment(dev_priv);
2410         else
2411                 alignment = intel_surf_alignment(fb, plane);
2412
2413         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2414                                           rotation, alignment);
2415 }
2416
2417 /* Convert the fb->offset[] linear offset into x/y offsets */
2418 static void intel_fb_offset_to_xy(int *x, int *y,
2419                                   const struct drm_framebuffer *fb, int plane)
2420 {
2421         unsigned int cpp = fb->format->cpp[plane];
2422         unsigned int pitch = fb->pitches[plane];
2423         u32 linear_offset = fb->offsets[plane];
2424
2425         *y = linear_offset / pitch;
2426         *x = linear_offset % pitch / cpp;
2427 }
2428
2429 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2430 {
2431         switch (fb_modifier) {
2432         case I915_FORMAT_MOD_X_TILED:
2433                 return I915_TILING_X;
2434         case I915_FORMAT_MOD_Y_TILED:
2435                 return I915_TILING_Y;
2436         default:
2437                 return I915_TILING_NONE;
2438         }
2439 }
2440
2441 static int
2442 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2443                    struct drm_framebuffer *fb)
2444 {
2445         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2446         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2447         u32 gtt_offset_rotated = 0;
2448         unsigned int max_size = 0;
2449         int i, num_planes = fb->format->num_planes;
2450         unsigned int tile_size = intel_tile_size(dev_priv);
2451
2452         for (i = 0; i < num_planes; i++) {
2453                 unsigned int width, height;
2454                 unsigned int cpp, size;
2455                 u32 offset;
2456                 int x, y;
2457
2458                 cpp = fb->format->cpp[i];
2459                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2460                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2461
2462                 intel_fb_offset_to_xy(&x, &y, fb, i);
2463
2464                 /*
2465                  * The fence (if used) is aligned to the start of the object
2466                  * so having the framebuffer wrap around across the edge of the
2467                  * fenced region doesn't really work. We have no API to configure
2468                  * the fence start offset within the object (nor could we probably
2469                  * on gen2/3). So it's just easier if we just require that the
2470                  * fb layout agrees with the fence layout. We already check that the
2471                  * fb stride matches the fence stride elsewhere.
2472                  */
2473                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2474                     (x + width) * cpp > fb->pitches[i]) {
2475                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2476                                       i, fb->offsets[i]);
2477                         return -EINVAL;
2478                 }
2479
2480                 /*
2481                  * First pixel of the framebuffer from
2482                  * the start of the normal gtt mapping.
2483                  */
2484                 intel_fb->normal[i].x = x;
2485                 intel_fb->normal[i].y = y;
2486
2487                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2488                                                     fb, i, fb->pitches[i],
2489                                                     DRM_MODE_ROTATE_0, tile_size);
2490                 offset /= tile_size;
2491
2492                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2493                         unsigned int tile_width, tile_height;
2494                         unsigned int pitch_tiles;
2495                         struct drm_rect r;
2496
2497                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2498
2499                         rot_info->plane[i].offset = offset;
2500                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2501                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2502                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2503
2504                         intel_fb->rotated[i].pitch =
2505                                 rot_info->plane[i].height * tile_height;
2506
2507                         /* how many tiles does this plane need */
2508                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2509                         /*
2510                          * If the plane isn't horizontally tile aligned,
2511                          * we need one more tile.
2512                          */
2513                         if (x != 0)
2514                                 size++;
2515
2516                         /* rotate the x/y offsets to match the GTT view */
2517                         r.x1 = x;
2518                         r.y1 = y;
2519                         r.x2 = x + width;
2520                         r.y2 = y + height;
2521                         drm_rect_rotate(&r,
2522                                         rot_info->plane[i].width * tile_width,
2523                                         rot_info->plane[i].height * tile_height,
2524                                         DRM_MODE_ROTATE_270);
2525                         x = r.x1;
2526                         y = r.y1;
2527
2528                         /* rotate the tile dimensions to match the GTT view */
2529                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2530                         swap(tile_width, tile_height);
2531
2532                         /*
2533                          * We only keep the x/y offsets, so push all of the
2534                          * gtt offset into the x/y offsets.
2535                          */
2536                         _intel_adjust_tile_offset(&x, &y,
2537                                                   tile_width, tile_height,
2538                                                   tile_size, pitch_tiles,
2539                                                   gtt_offset_rotated * tile_size, 0);
2540
2541                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2542
2543                         /*
2544                          * First pixel of the framebuffer from
2545                          * the start of the rotated gtt mapping.
2546                          */
2547                         intel_fb->rotated[i].x = x;
2548                         intel_fb->rotated[i].y = y;
2549                 } else {
2550                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2551                                             x * cpp, tile_size);
2552                 }
2553
2554                 /* how many tiles in total needed in the bo */
2555                 max_size = max(max_size, offset + size);
2556         }
2557
2558         if (max_size * tile_size > intel_fb->obj->base.size) {
2559                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2560                               max_size * tile_size, intel_fb->obj->base.size);
2561                 return -EINVAL;
2562         }
2563
2564         return 0;
2565 }
2566
2567 static int i9xx_format_to_fourcc(int format)
2568 {
2569         switch (format) {
2570         case DISPPLANE_8BPP:
2571                 return DRM_FORMAT_C8;
2572         case DISPPLANE_BGRX555:
2573                 return DRM_FORMAT_XRGB1555;
2574         case DISPPLANE_BGRX565:
2575                 return DRM_FORMAT_RGB565;
2576         default:
2577         case DISPPLANE_BGRX888:
2578                 return DRM_FORMAT_XRGB8888;
2579         case DISPPLANE_RGBX888:
2580                 return DRM_FORMAT_XBGR8888;
2581         case DISPPLANE_BGRX101010:
2582                 return DRM_FORMAT_XRGB2101010;
2583         case DISPPLANE_RGBX101010:
2584                 return DRM_FORMAT_XBGR2101010;
2585         }
2586 }
2587
2588 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2589 {
2590         switch (format) {
2591         case PLANE_CTL_FORMAT_RGB_565:
2592                 return DRM_FORMAT_RGB565;
2593         default:
2594         case PLANE_CTL_FORMAT_XRGB_8888:
2595                 if (rgb_order) {
2596                         if (alpha)
2597                                 return DRM_FORMAT_ABGR8888;
2598                         else
2599                                 return DRM_FORMAT_XBGR8888;
2600                 } else {
2601                         if (alpha)
2602                                 return DRM_FORMAT_ARGB8888;
2603                         else
2604                                 return DRM_FORMAT_XRGB8888;
2605                 }
2606         case PLANE_CTL_FORMAT_XRGB_2101010:
2607                 if (rgb_order)
2608                         return DRM_FORMAT_XBGR2101010;
2609                 else
2610                         return DRM_FORMAT_XRGB2101010;
2611         }
2612 }
2613
2614 static bool
2615 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2616                               struct intel_initial_plane_config *plane_config)
2617 {
2618         struct drm_device *dev = crtc->base.dev;
2619         struct drm_i915_private *dev_priv = to_i915(dev);
2620         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2621         struct drm_i915_gem_object *obj = NULL;
2622         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2623         struct drm_framebuffer *fb = &plane_config->fb->base;
2624         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2625         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2626                                     PAGE_SIZE);
2627
2628         size_aligned -= base_aligned;
2629
2630         if (plane_config->size == 0)
2631                 return false;
2632
2633         /* If the FB is too big, just don't use it since fbdev is not very
2634          * important and we should probably use that space with FBC or other
2635          * features. */
2636         if (size_aligned * 2 > ggtt->stolen_usable_size)
2637                 return false;
2638
2639         mutex_lock(&dev->struct_mutex);
2640         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2641                                                              base_aligned,
2642                                                              base_aligned,
2643                                                              size_aligned);
2644         mutex_unlock(&dev->struct_mutex);
2645         if (!obj)
2646                 return false;
2647
2648         if (plane_config->tiling == I915_TILING_X)
2649                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2650
2651         mode_cmd.pixel_format = fb->format->format;
2652         mode_cmd.width = fb->width;
2653         mode_cmd.height = fb->height;
2654         mode_cmd.pitches[0] = fb->pitches[0];
2655         mode_cmd.modifier[0] = fb->modifier;
2656         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2657
2658         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2659                 DRM_DEBUG_KMS("intel fb init failed\n");
2660                 goto out_unref_obj;
2661         }
2662
2663
2664         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2665         return true;
2666
2667 out_unref_obj:
2668         i915_gem_object_put(obj);
2669         return false;
2670 }
2671
2672 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2673 static void
2674 update_state_fb(struct drm_plane *plane)
2675 {
2676         if (plane->fb == plane->state->fb)
2677                 return;
2678
2679         if (plane->state->fb)
2680                 drm_framebuffer_unreference(plane->state->fb);
2681         plane->state->fb = plane->fb;
2682         if (plane->state->fb)
2683                 drm_framebuffer_reference(plane->state->fb);
2684 }
2685
2686 static void
2687 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2688                         struct intel_plane_state *plane_state,
2689                         bool visible)
2690 {
2691         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2692
2693         plane_state->base.visible = visible;
2694
2695         /* FIXME pre-g4x don't work like this */
2696         if (visible) {
2697                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2698                 crtc_state->active_planes |= BIT(plane->id);
2699         } else {
2700                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2701                 crtc_state->active_planes &= ~BIT(plane->id);
2702         }
2703
2704         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2705                       crtc_state->base.crtc->name,
2706                       crtc_state->active_planes);
2707 }
2708
2709 static void
2710 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2711                              struct intel_initial_plane_config *plane_config)
2712 {
2713         struct drm_device *dev = intel_crtc->base.dev;
2714         struct drm_i915_private *dev_priv = to_i915(dev);
2715         struct drm_crtc *c;
2716         struct drm_i915_gem_object *obj;
2717         struct drm_plane *primary = intel_crtc->base.primary;
2718         struct drm_plane_state *plane_state = primary->state;
2719         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2720         struct intel_plane *intel_plane = to_intel_plane(primary);
2721         struct intel_plane_state *intel_state =
2722                 to_intel_plane_state(plane_state);
2723         struct drm_framebuffer *fb;
2724
2725         if (!plane_config->fb)
2726                 return;
2727
2728         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2729                 fb = &plane_config->fb->base;
2730                 goto valid_fb;
2731         }
2732
2733         kfree(plane_config->fb);
2734
2735         /*
2736          * Failed to alloc the obj, check to see if we should share
2737          * an fb with another CRTC instead
2738          */
2739         for_each_crtc(dev, c) {
2740                 struct intel_plane_state *state;
2741
2742                 if (c == &intel_crtc->base)
2743                         continue;
2744
2745                 if (!to_intel_crtc(c)->active)
2746                         continue;
2747
2748                 state = to_intel_plane_state(c->primary->state);
2749                 if (!state->vma)
2750                         continue;
2751
2752                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2753                         fb = c->primary->fb;
2754                         drm_framebuffer_reference(fb);
2755                         goto valid_fb;
2756                 }
2757         }
2758
2759         /*
2760          * We've failed to reconstruct the BIOS FB.  Current display state
2761          * indicates that the primary plane is visible, but has a NULL FB,
2762          * which will lead to problems later if we don't fix it up.  The
2763          * simplest solution is to just disable the primary plane now and
2764          * pretend the BIOS never had it enabled.
2765          */
2766         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2767                                 to_intel_plane_state(plane_state),
2768                                 false);
2769         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2770         trace_intel_disable_plane(primary, intel_crtc);
2771         intel_plane->disable_plane(intel_plane, intel_crtc);
2772
2773         return;
2774
2775 valid_fb:
2776         mutex_lock(&dev->struct_mutex);
2777         intel_state->vma =
2778                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2779         mutex_unlock(&dev->struct_mutex);
2780         if (IS_ERR(intel_state->vma)) {
2781                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2782                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2783
2784                 intel_state->vma = NULL;
2785                 drm_framebuffer_unreference(fb);
2786                 return;
2787         }
2788
2789         plane_state->src_x = 0;
2790         plane_state->src_y = 0;
2791         plane_state->src_w = fb->width << 16;
2792         plane_state->src_h = fb->height << 16;
2793
2794         plane_state->crtc_x = 0;
2795         plane_state->crtc_y = 0;
2796         plane_state->crtc_w = fb->width;
2797         plane_state->crtc_h = fb->height;
2798
2799         intel_state->base.src = drm_plane_state_src(plane_state);
2800         intel_state->base.dst = drm_plane_state_dest(plane_state);
2801
2802         obj = intel_fb_obj(fb);
2803         if (i915_gem_object_is_tiled(obj))
2804                 dev_priv->preserve_bios_swizzle = true;
2805
2806         drm_framebuffer_reference(fb);
2807         primary->fb = primary->state->fb = fb;
2808         primary->crtc = primary->state->crtc = &intel_crtc->base;
2809
2810         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2811                                 to_intel_plane_state(plane_state),
2812                                 true);
2813
2814         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2815                   &obj->frontbuffer_bits);
2816 }
2817
2818 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2819                                unsigned int rotation)
2820 {
2821         int cpp = fb->format->cpp[plane];
2822
2823         switch (fb->modifier) {
2824         case DRM_FORMAT_MOD_LINEAR:
2825         case I915_FORMAT_MOD_X_TILED:
2826                 switch (cpp) {
2827                 case 8:
2828                         return 4096;
2829                 case 4:
2830                 case 2:
2831                 case 1:
2832                         return 8192;
2833                 default:
2834                         MISSING_CASE(cpp);
2835                         break;
2836                 }
2837                 break;
2838         case I915_FORMAT_MOD_Y_TILED:
2839         case I915_FORMAT_MOD_Yf_TILED:
2840                 switch (cpp) {
2841                 case 8:
2842                         return 2048;
2843                 case 4:
2844                         return 4096;
2845                 case 2:
2846                 case 1:
2847                         return 8192;
2848                 default:
2849                         MISSING_CASE(cpp);
2850                         break;
2851                 }
2852                 break;
2853         default:
2854                 MISSING_CASE(fb->modifier);
2855         }
2856
2857         return 2048;
2858 }
2859
2860 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2861 {
2862         const struct drm_framebuffer *fb = plane_state->base.fb;
2863         unsigned int rotation = plane_state->base.rotation;
2864         int x = plane_state->base.src.x1 >> 16;
2865         int y = plane_state->base.src.y1 >> 16;
2866         int w = drm_rect_width(&plane_state->base.src) >> 16;
2867         int h = drm_rect_height(&plane_state->base.src) >> 16;
2868         int max_width = skl_max_plane_width(fb, 0, rotation);
2869         int max_height = 4096;
2870         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2871
2872         if (w > max_width || h > max_height) {
2873                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2874                               w, h, max_width, max_height);
2875                 return -EINVAL;
2876         }
2877
2878         intel_add_fb_offsets(&x, &y, plane_state, 0);
2879         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2880         alignment = intel_surf_alignment(fb, 0);
2881
2882         /*
2883          * AUX surface offset is specified as the distance from the
2884          * main surface offset, and it must be non-negative. Make
2885          * sure that is what we will get.
2886          */
2887         if (offset > aux_offset)
2888                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889                                                   offset, aux_offset & ~(alignment - 1));
2890
2891         /*
2892          * When using an X-tiled surface, the plane blows up
2893          * if the x offset + width exceed the stride.
2894          *
2895          * TODO: linear and Y-tiled seem fine, Yf untested,
2896          */
2897         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2898                 int cpp = fb->format->cpp[0];
2899
2900                 while ((x + w) * cpp > fb->pitches[0]) {
2901                         if (offset == 0) {
2902                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2903                                 return -EINVAL;
2904                         }
2905
2906                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2907                                                           offset, offset - alignment);
2908                 }
2909         }
2910
2911         plane_state->main.offset = offset;
2912         plane_state->main.x = x;
2913         plane_state->main.y = y;
2914
2915         return 0;
2916 }
2917
2918 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2919 {
2920         const struct drm_framebuffer *fb = plane_state->base.fb;
2921         unsigned int rotation = plane_state->base.rotation;
2922         int max_width = skl_max_plane_width(fb, 1, rotation);
2923         int max_height = 4096;
2924         int x = plane_state->base.src.x1 >> 17;
2925         int y = plane_state->base.src.y1 >> 17;
2926         int w = drm_rect_width(&plane_state->base.src) >> 17;
2927         int h = drm_rect_height(&plane_state->base.src) >> 17;
2928         u32 offset;
2929
2930         intel_add_fb_offsets(&x, &y, plane_state, 1);
2931         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2932
2933         /* FIXME not quite sure how/if these apply to the chroma plane */
2934         if (w > max_width || h > max_height) {
2935                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2936                               w, h, max_width, max_height);
2937                 return -EINVAL;
2938         }
2939
2940         plane_state->aux.offset = offset;
2941         plane_state->aux.x = x;
2942         plane_state->aux.y = y;
2943
2944         return 0;
2945 }
2946
2947 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2948 {
2949         const struct drm_framebuffer *fb = plane_state->base.fb;
2950         unsigned int rotation = plane_state->base.rotation;
2951         int ret;
2952
2953         if (!plane_state->base.visible)
2954                 return 0;
2955
2956         /* Rotate src coordinates to match rotated GTT view */
2957         if (drm_rotation_90_or_270(rotation))
2958                 drm_rect_rotate(&plane_state->base.src,
2959                                 fb->width << 16, fb->height << 16,
2960                                 DRM_MODE_ROTATE_270);
2961
2962         /*
2963          * Handle the AUX surface first since
2964          * the main surface setup depends on it.
2965          */
2966         if (fb->format->format == DRM_FORMAT_NV12) {
2967                 ret = skl_check_nv12_aux_surface(plane_state);
2968                 if (ret)
2969                         return ret;
2970         } else {
2971                 plane_state->aux.offset = ~0xfff;
2972                 plane_state->aux.x = 0;
2973                 plane_state->aux.y = 0;
2974         }
2975
2976         ret = skl_check_main_surface(plane_state);
2977         if (ret)
2978                 return ret;
2979
2980         return 0;
2981 }
2982
2983 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2984                           const struct intel_plane_state *plane_state)
2985 {
2986         struct drm_i915_private *dev_priv =
2987                 to_i915(plane_state->base.plane->dev);
2988         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2989         const struct drm_framebuffer *fb = plane_state->base.fb;
2990         unsigned int rotation = plane_state->base.rotation;
2991         u32 dspcntr;
2992
2993         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2994
2995         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2996             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2997                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2998
2999         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3000                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3001
3002         if (INTEL_GEN(dev_priv) < 4)
3003                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3004
3005         switch (fb->format->format) {
3006         case DRM_FORMAT_C8:
3007                 dspcntr |= DISPPLANE_8BPP;
3008                 break;
3009         case DRM_FORMAT_XRGB1555:
3010                 dspcntr |= DISPPLANE_BGRX555;
3011                 break;
3012         case DRM_FORMAT_RGB565:
3013                 dspcntr |= DISPPLANE_BGRX565;
3014                 break;
3015         case DRM_FORMAT_XRGB8888:
3016                 dspcntr |= DISPPLANE_BGRX888;
3017                 break;
3018         case DRM_FORMAT_XBGR8888:
3019                 dspcntr |= DISPPLANE_RGBX888;
3020                 break;
3021         case DRM_FORMAT_XRGB2101010:
3022                 dspcntr |= DISPPLANE_BGRX101010;
3023                 break;
3024         case DRM_FORMAT_XBGR2101010:
3025                 dspcntr |= DISPPLANE_RGBX101010;
3026                 break;
3027         default:
3028                 MISSING_CASE(fb->format->format);
3029                 return 0;
3030         }
3031
3032         if (INTEL_GEN(dev_priv) >= 4 &&
3033             fb->modifier == I915_FORMAT_MOD_X_TILED)
3034                 dspcntr |= DISPPLANE_TILED;
3035
3036         if (rotation & DRM_MODE_ROTATE_180)
3037                 dspcntr |= DISPPLANE_ROTATE_180;
3038
3039         if (rotation & DRM_MODE_REFLECT_X)
3040                 dspcntr |= DISPPLANE_MIRROR;
3041
3042         return dspcntr;
3043 }
3044
3045 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3046 {
3047         struct drm_i915_private *dev_priv =
3048                 to_i915(plane_state->base.plane->dev);
3049         int src_x = plane_state->base.src.x1 >> 16;
3050         int src_y = plane_state->base.src.y1 >> 16;
3051         u32 offset;
3052
3053         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3054
3055         if (INTEL_GEN(dev_priv) >= 4)
3056                 offset = intel_compute_tile_offset(&src_x, &src_y,
3057                                                    plane_state, 0);
3058         else
3059                 offset = 0;
3060
3061         /* HSW/BDW do this automagically in hardware */
3062         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3063                 unsigned int rotation = plane_state->base.rotation;
3064                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3065                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3066
3067                 if (rotation & DRM_MODE_ROTATE_180) {
3068                         src_x += src_w - 1;
3069                         src_y += src_h - 1;
3070                 } else if (rotation & DRM_MODE_REFLECT_X) {
3071                         src_x += src_w - 1;
3072                 }
3073         }
3074
3075         plane_state->main.offset = offset;
3076         plane_state->main.x = src_x;
3077         plane_state->main.y = src_y;
3078
3079         return 0;
3080 }
3081
3082 static void i9xx_update_primary_plane(struct intel_plane *primary,
3083                                       const struct intel_crtc_state *crtc_state,
3084                                       const struct intel_plane_state *plane_state)
3085 {
3086         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3087         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3088         const struct drm_framebuffer *fb = plane_state->base.fb;
3089         enum plane plane = primary->plane;
3090         u32 linear_offset;
3091         u32 dspcntr = plane_state->ctl;
3092         i915_reg_t reg = DSPCNTR(plane);
3093         int x = plane_state->main.x;
3094         int y = plane_state->main.y;
3095         unsigned long irqflags;
3096
3097         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3098
3099         if (INTEL_GEN(dev_priv) >= 4)
3100                 crtc->dspaddr_offset = plane_state->main.offset;
3101         else
3102                 crtc->dspaddr_offset = linear_offset;
3103
3104         crtc->adjusted_x = x;
3105         crtc->adjusted_y = y;
3106
3107         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3108
3109         if (INTEL_GEN(dev_priv) < 4) {
3110                 /* pipesrc and dspsize control the size that is scaled from,
3111                  * which should always be the user's requested size.
3112                  */
3113                 I915_WRITE_FW(DSPSIZE(plane),
3114                               ((crtc_state->pipe_src_h - 1) << 16) |
3115                               (crtc_state->pipe_src_w - 1));
3116                 I915_WRITE_FW(DSPPOS(plane), 0);
3117         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3118                 I915_WRITE_FW(PRIMSIZE(plane),
3119                               ((crtc_state->pipe_src_h - 1) << 16) |
3120                               (crtc_state->pipe_src_w - 1));
3121                 I915_WRITE_FW(PRIMPOS(plane), 0);
3122                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3123         }
3124
3125         I915_WRITE_FW(reg, dspcntr);
3126
3127         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3128         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3129                 I915_WRITE_FW(DSPSURF(plane),
3130                               intel_plane_ggtt_offset(plane_state) +
3131                               crtc->dspaddr_offset);
3132                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3133         } else if (INTEL_GEN(dev_priv) >= 4) {
3134                 I915_WRITE_FW(DSPSURF(plane),
3135                               intel_plane_ggtt_offset(plane_state) +
3136                               crtc->dspaddr_offset);
3137                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3138                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3139         } else {
3140                 I915_WRITE_FW(DSPADDR(plane),
3141                               intel_plane_ggtt_offset(plane_state) +
3142                               crtc->dspaddr_offset);
3143         }
3144         POSTING_READ_FW(reg);
3145
3146         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3147 }
3148
3149 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3150                                        struct intel_crtc *crtc)
3151 {
3152         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3153         enum plane plane = primary->plane;
3154         unsigned long irqflags;
3155
3156         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3157
3158         I915_WRITE_FW(DSPCNTR(plane), 0);
3159         if (INTEL_INFO(dev_priv)->gen >= 4)
3160                 I915_WRITE_FW(DSPSURF(plane), 0);
3161         else
3162                 I915_WRITE_FW(DSPADDR(plane), 0);
3163         POSTING_READ_FW(DSPCNTR(plane));
3164
3165         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3166 }
3167
3168 static u32
3169 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3170 {
3171         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3172                 return 64;
3173         else
3174                 return intel_tile_width_bytes(fb, plane);
3175 }
3176
3177 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3178 {
3179         struct drm_device *dev = intel_crtc->base.dev;
3180         struct drm_i915_private *dev_priv = to_i915(dev);
3181
3182         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3183         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3184         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3185 }
3186
3187 /*
3188  * This function detaches (aka. unbinds) unused scalers in hardware
3189  */
3190 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3191 {
3192         struct intel_crtc_scaler_state *scaler_state;
3193         int i;
3194
3195         scaler_state = &intel_crtc->config->scaler_state;
3196
3197         /* loop through and disable scalers that aren't in use */
3198         for (i = 0; i < intel_crtc->num_scalers; i++) {
3199                 if (!scaler_state->scalers[i].in_use)
3200                         skl_detach_scaler(intel_crtc, i);
3201         }
3202 }
3203
3204 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3205                      unsigned int rotation)
3206 {
3207         u32 stride;
3208
3209         if (plane >= fb->format->num_planes)
3210                 return 0;
3211
3212         stride = intel_fb_pitch(fb, plane, rotation);
3213
3214         /*
3215          * The stride is either expressed as a multiple of 64 bytes chunks for
3216          * linear buffers or in number of tiles for tiled buffers.
3217          */
3218         if (drm_rotation_90_or_270(rotation))
3219                 stride /= intel_tile_height(fb, plane);
3220         else
3221                 stride /= intel_fb_stride_alignment(fb, plane);
3222
3223         return stride;
3224 }
3225
3226 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3227 {
3228         switch (pixel_format) {
3229         case DRM_FORMAT_C8:
3230                 return PLANE_CTL_FORMAT_INDEXED;
3231         case DRM_FORMAT_RGB565:
3232                 return PLANE_CTL_FORMAT_RGB_565;
3233         case DRM_FORMAT_XBGR8888:
3234                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3235         case DRM_FORMAT_XRGB8888:
3236                 return PLANE_CTL_FORMAT_XRGB_8888;
3237         /*
3238          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3239          * to be already pre-multiplied. We need to add a knob (or a different
3240          * DRM_FORMAT) for user-space to configure that.
3241          */
3242         case DRM_FORMAT_ABGR8888:
3243                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3244                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3245         case DRM_FORMAT_ARGB8888:
3246                 return PLANE_CTL_FORMAT_XRGB_8888 |
3247                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3248         case DRM_FORMAT_XRGB2101010:
3249                 return PLANE_CTL_FORMAT_XRGB_2101010;
3250         case DRM_FORMAT_XBGR2101010:
3251                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3252         case DRM_FORMAT_YUYV:
3253                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3254         case DRM_FORMAT_YVYU:
3255                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3256         case DRM_FORMAT_UYVY:
3257                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3258         case DRM_FORMAT_VYUY:
3259                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3260         default:
3261                 MISSING_CASE(pixel_format);
3262         }
3263
3264         return 0;
3265 }
3266
3267 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3268 {
3269         switch (fb_modifier) {
3270         case DRM_FORMAT_MOD_LINEAR:
3271                 break;
3272         case I915_FORMAT_MOD_X_TILED:
3273                 return PLANE_CTL_TILED_X;
3274         case I915_FORMAT_MOD_Y_TILED:
3275                 return PLANE_CTL_TILED_Y;
3276         case I915_FORMAT_MOD_Yf_TILED:
3277                 return PLANE_CTL_TILED_YF;
3278         default:
3279                 MISSING_CASE(fb_modifier);
3280         }
3281
3282         return 0;
3283 }
3284
3285 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3286 {
3287         switch (rotation) {
3288         case DRM_MODE_ROTATE_0:
3289                 break;
3290         /*
3291          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3292          * while i915 HW rotation is clockwise, thats why this swapping.
3293          */
3294         case DRM_MODE_ROTATE_90:
3295                 return PLANE_CTL_ROTATE_270;
3296         case DRM_MODE_ROTATE_180:
3297                 return PLANE_CTL_ROTATE_180;
3298         case DRM_MODE_ROTATE_270:
3299                 return PLANE_CTL_ROTATE_90;
3300         default:
3301                 MISSING_CASE(rotation);
3302         }
3303
3304         return 0;
3305 }
3306
3307 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3308                   const struct intel_plane_state *plane_state)
3309 {
3310         struct drm_i915_private *dev_priv =
3311                 to_i915(plane_state->base.plane->dev);
3312         const struct drm_framebuffer *fb = plane_state->base.fb;
3313         unsigned int rotation = plane_state->base.rotation;
3314         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3315         u32 plane_ctl;
3316
3317         plane_ctl = PLANE_CTL_ENABLE;
3318
3319         if (!IS_GEMINILAKE(dev_priv)) {
3320                 plane_ctl |=
3321                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3322                         PLANE_CTL_PIPE_CSC_ENABLE |
3323                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3324         }
3325
3326         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3327         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3328         plane_ctl |= skl_plane_ctl_rotation(rotation);
3329
3330         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3331                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3332         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3333                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3334
3335         return plane_ctl;
3336 }
3337
3338 static void skylake_update_primary_plane(struct intel_plane *plane,
3339                                          const struct intel_crtc_state *crtc_state,
3340                                          const struct intel_plane_state *plane_state)
3341 {
3342         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3343         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3344         const struct drm_framebuffer *fb = plane_state->base.fb;
3345         enum plane_id plane_id = plane->id;
3346         enum pipe pipe = plane->pipe;
3347         u32 plane_ctl = plane_state->ctl;
3348         unsigned int rotation = plane_state->base.rotation;
3349         u32 stride = skl_plane_stride(fb, 0, rotation);
3350         u32 surf_addr = plane_state->main.offset;
3351         int scaler_id = plane_state->scaler_id;
3352         int src_x = plane_state->main.x;
3353         int src_y = plane_state->main.y;
3354         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3355         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3356         int dst_x = plane_state->base.dst.x1;
3357         int dst_y = plane_state->base.dst.y1;
3358         int dst_w = drm_rect_width(&plane_state->base.dst);
3359         int dst_h = drm_rect_height(&plane_state->base.dst);
3360         unsigned long irqflags;
3361
3362         /* Sizes are 0 based */
3363         src_w--;
3364         src_h--;
3365         dst_w--;
3366         dst_h--;
3367
3368         crtc->dspaddr_offset = surf_addr;
3369
3370         crtc->adjusted_x = src_x;
3371         crtc->adjusted_y = src_y;
3372
3373         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3374
3375         if (IS_GEMINILAKE(dev_priv)) {
3376                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3377                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3378                               PLANE_COLOR_PIPE_CSC_ENABLE |
3379                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3380         }
3381
3382         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3383         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3384         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3385         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3386
3387         if (scaler_id >= 0) {
3388                 uint32_t ps_ctrl = 0;
3389
3390                 WARN_ON(!dst_w || !dst_h);
3391                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3392                         crtc_state->scaler_state.scalers[scaler_id].mode;
3393                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3394                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3395                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3396                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3397                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3398         } else {
3399                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3400         }
3401
3402         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3403                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3404
3405         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3406
3407         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3408 }
3409
3410 static void skylake_disable_primary_plane(struct intel_plane *primary,
3411                                           struct intel_crtc *crtc)
3412 {
3413         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3414         enum plane_id plane_id = primary->id;
3415         enum pipe pipe = primary->pipe;
3416         unsigned long irqflags;
3417
3418         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3419
3420         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3421         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3422         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3423
3424         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3425 }
3426
3427 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3428 {
3429         struct intel_crtc *crtc;
3430
3431         for_each_intel_crtc(&dev_priv->drm, crtc)
3432                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3433 }
3434
3435 static void intel_update_primary_planes(struct drm_device *dev)
3436 {
3437         struct drm_crtc *crtc;
3438
3439         for_each_crtc(dev, crtc) {
3440                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3441                 struct intel_plane_state *plane_state =
3442                         to_intel_plane_state(plane->base.state);
3443
3444                 if (plane_state->base.visible) {
3445                         trace_intel_update_plane(&plane->base,
3446                                                  to_intel_crtc(crtc));
3447
3448                         plane->update_plane(plane,
3449                                             to_intel_crtc_state(crtc->state),
3450                                             plane_state);
3451                 }
3452         }
3453 }
3454
3455 static int
3456 __intel_display_resume(struct drm_device *dev,
3457                        struct drm_atomic_state *state,
3458                        struct drm_modeset_acquire_ctx *ctx)
3459 {
3460         struct drm_crtc_state *crtc_state;
3461         struct drm_crtc *crtc;
3462         int i, ret;
3463
3464         intel_modeset_setup_hw_state(dev);
3465         i915_redisable_vga(to_i915(dev));
3466
3467         if (!state)
3468                 return 0;
3469
3470         /*
3471          * We've duplicated the state, pointers to the old state are invalid.
3472          *
3473          * Don't attempt to use the old state until we commit the duplicated state.
3474          */
3475         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3476                 /*
3477                  * Force recalculation even if we restore
3478                  * current state. With fast modeset this may not result
3479                  * in a modeset when the state is compatible.
3480                  */
3481                 crtc_state->mode_changed = true;
3482         }
3483
3484         /* ignore any reset values/BIOS leftovers in the WM registers */
3485         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3486                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3487
3488         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3489
3490         WARN_ON(ret == -EDEADLK);
3491         return ret;
3492 }
3493
3494 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3495 {
3496         return intel_has_gpu_reset(dev_priv) &&
3497                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3498 }
3499
3500 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3501 {
3502         struct drm_device *dev = &dev_priv->drm;
3503         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3504         struct drm_atomic_state *state;
3505         int ret;
3506
3507         /*
3508          * Need mode_config.mutex so that we don't
3509          * trample ongoing ->detect() and whatnot.
3510          */
3511         mutex_lock(&dev->mode_config.mutex);
3512         drm_modeset_acquire_init(ctx, 0);
3513         while (1) {
3514                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3515                 if (ret != -EDEADLK)
3516                         break;
3517
3518                 drm_modeset_backoff(ctx);
3519         }
3520
3521         /* reset doesn't touch the display, but flips might get nuked anyway, */
3522         if (!i915.force_reset_modeset_test &&
3523             !gpu_reset_clobbers_display(dev_priv))
3524                 return;
3525
3526         /*
3527          * Disabling the crtcs gracefully seems nicer. Also the
3528          * g33 docs say we should at least disable all the planes.
3529          */
3530         state = drm_atomic_helper_duplicate_state(dev, ctx);
3531         if (IS_ERR(state)) {
3532                 ret = PTR_ERR(state);
3533                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3534                 return;
3535         }
3536
3537         ret = drm_atomic_helper_disable_all(dev, ctx);
3538         if (ret) {
3539                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3540                 drm_atomic_state_put(state);
3541                 return;
3542         }
3543
3544         dev_priv->modeset_restore_state = state;
3545         state->acquire_ctx = ctx;
3546 }
3547
3548 void intel_finish_reset(struct drm_i915_private *dev_priv)
3549 {
3550         struct drm_device *dev = &dev_priv->drm;
3551         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3552         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3553         int ret;
3554
3555         /*
3556          * Flips in the rings will be nuked by the reset,
3557          * so complete all pending flips so that user space
3558          * will get its events and not get stuck.
3559          */
3560         intel_complete_page_flips(dev_priv);
3561
3562         dev_priv->modeset_restore_state = NULL;
3563
3564         /* reset doesn't touch the display */
3565         if (!gpu_reset_clobbers_display(dev_priv)) {
3566                 if (!state) {
3567                         /*
3568                          * Flips in the rings have been nuked by the reset,
3569                          * so update the base address of all primary
3570                          * planes to the the last fb to make sure we're
3571                          * showing the correct fb after a reset.
3572                          *
3573                          * FIXME: Atomic will make this obsolete since we won't schedule
3574                          * CS-based flips (which might get lost in gpu resets) any more.
3575                          */
3576                         intel_update_primary_planes(dev);
3577                 } else {
3578                         ret = __intel_display_resume(dev, state, ctx);
3579                         if (ret)
3580                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3581                 }
3582         } else {
3583                 /*
3584                  * The display has been reset as well,
3585                  * so need a full re-initialization.
3586                  */
3587                 intel_runtime_pm_disable_interrupts(dev_priv);
3588                 intel_runtime_pm_enable_interrupts(dev_priv);
3589
3590                 intel_pps_unlock_regs_wa(dev_priv);
3591                 intel_modeset_init_hw(dev);
3592
3593                 spin_lock_irq(&dev_priv->irq_lock);
3594                 if (dev_priv->display.hpd_irq_setup)
3595                         dev_priv->display.hpd_irq_setup(dev_priv);
3596                 spin_unlock_irq(&dev_priv->irq_lock);
3597
3598                 ret = __intel_display_resume(dev, state, ctx);
3599                 if (ret)
3600                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3601
3602                 intel_hpd_init(dev_priv);
3603         }
3604
3605         if (state)
3606                 drm_atomic_state_put(state);
3607         drm_modeset_drop_locks(ctx);
3608         drm_modeset_acquire_fini(ctx);
3609         mutex_unlock(&dev->mode_config.mutex);
3610 }
3611
3612 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3613 {
3614         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3615
3616         if (i915_reset_backoff(error))
3617                 return true;
3618
3619         if (crtc->reset_count != i915_reset_count(error))
3620                 return true;
3621
3622         return false;
3623 }
3624
3625 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3626 {
3627         struct drm_device *dev = crtc->dev;
3628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629         bool pending;
3630
3631         if (abort_flip_on_reset(intel_crtc))
3632                 return false;
3633
3634         spin_lock_irq(&dev->event_lock);
3635         pending = to_intel_crtc(crtc)->flip_work != NULL;
3636         spin_unlock_irq(&dev->event_lock);
3637
3638         return pending;
3639 }
3640
3641 static void intel_update_pipe_config(struct intel_crtc *crtc,
3642                                      struct intel_crtc_state *old_crtc_state)
3643 {
3644         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3645         struct intel_crtc_state *pipe_config =
3646                 to_intel_crtc_state(crtc->base.state);
3647
3648         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3649         crtc->base.mode = crtc->base.state->mode;
3650
3651         /*
3652          * Update pipe size and adjust fitter if needed: the reason for this is
3653          * that in compute_mode_changes we check the native mode (not the pfit
3654          * mode) to see if we can flip rather than do a full mode set. In the
3655          * fastboot case, we'll flip, but if we don't update the pipesrc and
3656          * pfit state, we'll end up with a big fb scanned out into the wrong
3657          * sized surface.
3658          */
3659
3660         I915_WRITE(PIPESRC(crtc->pipe),
3661                    ((pipe_config->pipe_src_w - 1) << 16) |
3662                    (pipe_config->pipe_src_h - 1));
3663
3664         /* on skylake this is done by detaching scalers */
3665         if (INTEL_GEN(dev_priv) >= 9) {
3666                 skl_detach_scalers(crtc);
3667
3668                 if (pipe_config->pch_pfit.enabled)
3669                         skylake_pfit_enable(crtc);
3670         } else if (HAS_PCH_SPLIT(dev_priv)) {
3671                 if (pipe_config->pch_pfit.enabled)
3672                         ironlake_pfit_enable(crtc);
3673                 else if (old_crtc_state->pch_pfit.enabled)
3674                         ironlake_pfit_disable(crtc, true);
3675         }
3676 }
3677
3678 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3679 {
3680         struct drm_device *dev = crtc->base.dev;
3681         struct drm_i915_private *dev_priv = to_i915(dev);
3682         int pipe = crtc->pipe;
3683         i915_reg_t reg;
3684         u32 temp;
3685
3686         /* enable normal train */
3687         reg = FDI_TX_CTL(pipe);
3688         temp = I915_READ(reg);
3689         if (IS_IVYBRIDGE(dev_priv)) {
3690                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3691                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3692         } else {
3693                 temp &= ~FDI_LINK_TRAIN_NONE;
3694                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3695         }
3696         I915_WRITE(reg, temp);
3697
3698         reg = FDI_RX_CTL(pipe);
3699         temp = I915_READ(reg);
3700         if (HAS_PCH_CPT(dev_priv)) {
3701                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3702                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3703         } else {
3704                 temp &= ~FDI_LINK_TRAIN_NONE;
3705                 temp |= FDI_LINK_TRAIN_NONE;
3706         }
3707         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3708
3709         /* wait one idle pattern time */
3710         POSTING_READ(reg);
3711         udelay(1000);
3712
3713         /* IVB wants error correction enabled */
3714         if (IS_IVYBRIDGE(dev_priv))
3715                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3716                            FDI_FE_ERRC_ENABLE);
3717 }
3718
3719 /* The FDI link training functions for ILK/Ibexpeak. */
3720 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3721                                     const struct intel_crtc_state *crtc_state)
3722 {
3723         struct drm_device *dev = crtc->base.dev;
3724         struct drm_i915_private *dev_priv = to_i915(dev);
3725         int pipe = crtc->pipe;
3726         i915_reg_t reg;
3727         u32 temp, tries;
3728
3729         /* FDI needs bits from pipe first */
3730         assert_pipe_enabled(dev_priv, pipe);
3731
3732         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3733            for train result */
3734         reg = FDI_RX_IMR(pipe);
3735         temp = I915_READ(reg);
3736         temp &= ~FDI_RX_SYMBOL_LOCK;
3737         temp &= ~FDI_RX_BIT_LOCK;
3738         I915_WRITE(reg, temp);
3739         I915_READ(reg);
3740         udelay(150);
3741
3742         /* enable CPU FDI TX and PCH FDI RX */
3743         reg = FDI_TX_CTL(pipe);
3744         temp = I915_READ(reg);
3745         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3746         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3747         temp &= ~FDI_LINK_TRAIN_NONE;
3748         temp |= FDI_LINK_TRAIN_PATTERN_1;
3749         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3750
3751         reg = FDI_RX_CTL(pipe);
3752         temp = I915_READ(reg);
3753         temp &= ~FDI_LINK_TRAIN_NONE;
3754         temp |= FDI_LINK_TRAIN_PATTERN_1;
3755         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3756
3757         POSTING_READ(reg);
3758         udelay(150);
3759
3760         /* Ironlake workaround, enable clock pointer after FDI enable*/
3761         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3762         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3763                    FDI_RX_PHASE_SYNC_POINTER_EN);
3764
3765         reg = FDI_RX_IIR(pipe);
3766         for (tries = 0; tries < 5; tries++) {
3767                 temp = I915_READ(reg);
3768                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3769
3770                 if ((temp & FDI_RX_BIT_LOCK)) {
3771                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3772                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3773                         break;
3774                 }
3775         }
3776         if (tries == 5)
3777                 DRM_ERROR("FDI train 1 fail!\n");
3778
3779         /* Train 2 */
3780         reg = FDI_TX_CTL(pipe);
3781         temp = I915_READ(reg);
3782         temp &= ~FDI_LINK_TRAIN_NONE;
3783         temp |= FDI_LINK_TRAIN_PATTERN_2;
3784         I915_WRITE(reg, temp);
3785
3786         reg = FDI_RX_CTL(pipe);
3787         temp = I915_READ(reg);
3788         temp &= ~FDI_LINK_TRAIN_NONE;
3789         temp |= FDI_LINK_TRAIN_PATTERN_2;
3790         I915_WRITE(reg, temp);
3791
3792         POSTING_READ(reg);
3793         udelay(150);
3794
3795         reg = FDI_RX_IIR(pipe);
3796         for (tries = 0; tries < 5; tries++) {
3797                 temp = I915_READ(reg);
3798                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3799
3800                 if (temp & FDI_RX_SYMBOL_LOCK) {
3801                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3802                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3803                         break;
3804                 }
3805         }
3806         if (tries == 5)
3807                 DRM_ERROR("FDI train 2 fail!\n");
3808
3809         DRM_DEBUG_KMS("FDI train done\n");
3810
3811 }
3812
3813 static const int snb_b_fdi_train_param[] = {
3814         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3815         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3816         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3817         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3818 };
3819
3820 /* The FDI link training functions for SNB/Cougarpoint. */
3821 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3822                                 const struct intel_crtc_state *crtc_state)
3823 {
3824         struct drm_device *dev = crtc->base.dev;
3825         struct drm_i915_private *dev_priv = to_i915(dev);
3826         int pipe = crtc->pipe;
3827         i915_reg_t reg;
3828         u32 temp, i, retry;
3829
3830         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3831            for train result */
3832         reg = FDI_RX_IMR(pipe);
3833         temp = I915_READ(reg);
3834         temp &= ~FDI_RX_SYMBOL_LOCK;
3835         temp &= ~FDI_RX_BIT_LOCK;
3836         I915_WRITE(reg, temp);
3837
3838         POSTING_READ(reg);
3839         udelay(150);
3840
3841         /* enable CPU FDI TX and PCH FDI RX */
3842         reg = FDI_TX_CTL(pipe);
3843         temp = I915_READ(reg);
3844         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3845         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3846         temp &= ~FDI_LINK_TRAIN_NONE;
3847         temp |= FDI_LINK_TRAIN_PATTERN_1;
3848         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3849         /* SNB-B */
3850         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3851         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3852
3853         I915_WRITE(FDI_RX_MISC(pipe),
3854                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3855
3856         reg = FDI_RX_CTL(pipe);
3857         temp = I915_READ(reg);
3858         if (HAS_PCH_CPT(dev_priv)) {
3859                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861         } else {
3862                 temp &= ~FDI_LINK_TRAIN_NONE;
3863                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864         }
3865         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3866
3867         POSTING_READ(reg);
3868         udelay(150);
3869
3870         for (i = 0; i < 4; i++) {
3871                 reg = FDI_TX_CTL(pipe);
3872                 temp = I915_READ(reg);
3873                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3874                 temp |= snb_b_fdi_train_param[i];
3875                 I915_WRITE(reg, temp);
3876
3877                 POSTING_READ(reg);
3878                 udelay(500);
3879
3880                 for (retry = 0; retry < 5; retry++) {
3881                         reg = FDI_RX_IIR(pipe);
3882                         temp = I915_READ(reg);
3883                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3884                         if (temp & FDI_RX_BIT_LOCK) {
3885                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3886                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3887                                 break;
3888                         }
3889                         udelay(50);
3890                 }
3891                 if (retry < 5)
3892                         break;
3893         }
3894         if (i == 4)
3895                 DRM_ERROR("FDI train 1 fail!\n");
3896
3897         /* Train 2 */
3898         reg = FDI_TX_CTL(pipe);
3899         temp = I915_READ(reg);
3900         temp &= ~FDI_LINK_TRAIN_NONE;
3901         temp |= FDI_LINK_TRAIN_PATTERN_2;
3902         if (IS_GEN6(dev_priv)) {
3903                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3904                 /* SNB-B */
3905                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3906         }
3907         I915_WRITE(reg, temp);
3908
3909         reg = FDI_RX_CTL(pipe);
3910         temp = I915_READ(reg);
3911         if (HAS_PCH_CPT(dev_priv)) {
3912                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3913                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3914         } else {
3915                 temp &= ~FDI_LINK_TRAIN_NONE;
3916                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3917         }
3918         I915_WRITE(reg, temp);
3919
3920         POSTING_READ(reg);
3921         udelay(150);
3922
3923         for (i = 0; i < 4; i++) {
3924                 reg = FDI_TX_CTL(pipe);
3925                 temp = I915_READ(reg);
3926                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3927                 temp |= snb_b_fdi_train_param[i];
3928                 I915_WRITE(reg, temp);
3929
3930                 POSTING_READ(reg);
3931                 udelay(500);
3932
3933                 for (retry = 0; retry < 5; retry++) {
3934                         reg = FDI_RX_IIR(pipe);
3935                         temp = I915_READ(reg);
3936                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3937                         if (temp & FDI_RX_SYMBOL_LOCK) {
3938                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3939                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3940                                 break;
3941                         }
3942                         udelay(50);
3943                 }
3944                 if (retry < 5)
3945                         break;
3946         }
3947         if (i == 4)
3948                 DRM_ERROR("FDI train 2 fail!\n");
3949
3950         DRM_DEBUG_KMS("FDI train done.\n");
3951 }
3952
3953 /* Manual link training for Ivy Bridge A0 parts */
3954 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3955                                       const struct intel_crtc_state *crtc_state)
3956 {
3957         struct drm_device *dev = crtc->base.dev;
3958         struct drm_i915_private *dev_priv = to_i915(dev);
3959         int pipe = crtc->pipe;
3960         i915_reg_t reg;
3961         u32 temp, i, j;
3962
3963         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3964            for train result */
3965         reg = FDI_RX_IMR(pipe);
3966         temp = I915_READ(reg);
3967         temp &= ~FDI_RX_SYMBOL_LOCK;
3968         temp &= ~FDI_RX_BIT_LOCK;
3969         I915_WRITE(reg, temp);
3970
3971         POSTING_READ(reg);
3972         udelay(150);
3973
3974         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3975                       I915_READ(FDI_RX_IIR(pipe)));
3976
3977         /* Try each vswing and preemphasis setting twice before moving on */
3978         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3979                 /* disable first in case we need to retry */
3980                 reg = FDI_TX_CTL(pipe);
3981                 temp = I915_READ(reg);
3982                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3983                 temp &= ~FDI_TX_ENABLE;
3984                 I915_WRITE(reg, temp);
3985
3986                 reg = FDI_RX_CTL(pipe);
3987                 temp = I915_READ(reg);
3988                 temp &= ~FDI_LINK_TRAIN_AUTO;
3989                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3990                 temp &= ~FDI_RX_ENABLE;
3991                 I915_WRITE(reg, temp);
3992
3993                 /* enable CPU FDI TX and PCH FDI RX */
3994                 reg = FDI_TX_CTL(pipe);
3995                 temp = I915_READ(reg);
3996                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3997                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3998                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3999                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4000                 temp |= snb_b_fdi_train_param[j/2];
4001                 temp |= FDI_COMPOSITE_SYNC;
4002                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4003
4004                 I915_WRITE(FDI_RX_MISC(pipe),
4005                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4006
4007                 reg = FDI_RX_CTL(pipe);
4008                 temp = I915_READ(reg);
4009                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4010                 temp |= FDI_COMPOSITE_SYNC;
4011                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4012
4013                 POSTING_READ(reg);
4014                 udelay(1); /* should be 0.5us */
4015
4016                 for (i = 0; i < 4; i++) {
4017                         reg = FDI_RX_IIR(pipe);
4018                         temp = I915_READ(reg);
4019                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4020
4021                         if (temp & FDI_RX_BIT_LOCK ||
4022                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4023                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4024                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4025                                               i);
4026                                 break;
4027                         }
4028                         udelay(1); /* should be 0.5us */
4029                 }
4030                 if (i == 4) {
4031                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4032                         continue;
4033                 }
4034
4035                 /* Train 2 */
4036                 reg = FDI_TX_CTL(pipe);
4037                 temp = I915_READ(reg);
4038                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4039                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4040                 I915_WRITE(reg, temp);
4041
4042                 reg = FDI_RX_CTL(pipe);
4043                 temp = I915_READ(reg);
4044                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4045                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4046                 I915_WRITE(reg, temp);
4047
4048                 POSTING_READ(reg);
4049                 udelay(2); /* should be 1.5us */
4050
4051                 for (i = 0; i < 4; i++) {
4052                         reg = FDI_RX_IIR(pipe);
4053                         temp = I915_READ(reg);
4054                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4055
4056                         if (temp & FDI_RX_SYMBOL_LOCK ||
4057                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4058                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4059                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4060                                               i);
4061                                 goto train_done;
4062                         }
4063                         udelay(2); /* should be 1.5us */
4064                 }
4065                 if (i == 4)
4066                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4067         }
4068
4069 train_done:
4070         DRM_DEBUG_KMS("FDI train done.\n");
4071 }
4072
4073 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4074 {
4075         struct drm_device *dev = intel_crtc->base.dev;
4076         struct drm_i915_private *dev_priv = to_i915(dev);
4077         int pipe = intel_crtc->pipe;
4078         i915_reg_t reg;
4079         u32 temp;
4080
4081         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4082         reg = FDI_RX_CTL(pipe);
4083         temp = I915_READ(reg);
4084         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4085         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4086         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4087         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4088
4089         POSTING_READ(reg);
4090         udelay(200);
4091
4092         /* Switch from Rawclk to PCDclk */
4093         temp = I915_READ(reg);
4094         I915_WRITE(reg, temp | FDI_PCDCLK);
4095
4096         POSTING_READ(reg);
4097         udelay(200);
4098
4099         /* Enable CPU FDI TX PLL, always on for Ironlake */
4100         reg = FDI_TX_CTL(pipe);
4101         temp = I915_READ(reg);
4102         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4103                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4104
4105                 POSTING_READ(reg);
4106                 udelay(100);
4107         }
4108 }
4109
4110 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4111 {
4112         struct drm_device *dev = intel_crtc->base.dev;
4113         struct drm_i915_private *dev_priv = to_i915(dev);
4114         int pipe = intel_crtc->pipe;
4115         i915_reg_t reg;
4116         u32 temp;
4117
4118         /* Switch from PCDclk to Rawclk */
4119         reg = FDI_RX_CTL(pipe);
4120         temp = I915_READ(reg);
4121         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4122
4123         /* Disable CPU FDI TX PLL */
4124         reg = FDI_TX_CTL(pipe);
4125         temp = I915_READ(reg);
4126         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4127
4128         POSTING_READ(reg);
4129         udelay(100);
4130
4131         reg = FDI_RX_CTL(pipe);
4132         temp = I915_READ(reg);
4133         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4134
4135         /* Wait for the clocks to turn off. */
4136         POSTING_READ(reg);
4137         udelay(100);
4138 }
4139
4140 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4141 {
4142         struct drm_device *dev = crtc->dev;
4143         struct drm_i915_private *dev_priv = to_i915(dev);
4144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145         int pipe = intel_crtc->pipe;
4146         i915_reg_t reg;
4147         u32 temp;
4148
4149         /* disable CPU FDI tx and PCH FDI rx */
4150         reg = FDI_TX_CTL(pipe);
4151         temp = I915_READ(reg);
4152         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4153         POSTING_READ(reg);
4154
4155         reg = FDI_RX_CTL(pipe);
4156         temp = I915_READ(reg);
4157         temp &= ~(0x7 << 16);
4158         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4159         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4160
4161         POSTING_READ(reg);
4162         udelay(100);
4163
4164         /* Ironlake workaround, disable clock pointer after downing FDI */
4165         if (HAS_PCH_IBX(dev_priv))
4166                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4167
4168         /* still set train pattern 1 */
4169         reg = FDI_TX_CTL(pipe);
4170         temp = I915_READ(reg);
4171         temp &= ~FDI_LINK_TRAIN_NONE;
4172         temp |= FDI_LINK_TRAIN_PATTERN_1;
4173         I915_WRITE(reg, temp);
4174
4175         reg = FDI_RX_CTL(pipe);
4176         temp = I915_READ(reg);
4177         if (HAS_PCH_CPT(dev_priv)) {
4178                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4179                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4180         } else {
4181                 temp &= ~FDI_LINK_TRAIN_NONE;
4182                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4183         }
4184         /* BPC in FDI rx is consistent with that in PIPECONF */
4185         temp &= ~(0x07 << 16);
4186         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4187         I915_WRITE(reg, temp);
4188
4189         POSTING_READ(reg);
4190         udelay(100);
4191 }
4192
4193 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4194 {
4195         struct intel_crtc *crtc;
4196
4197         /* Note that we don't need to be called with mode_config.lock here
4198          * as our list of CRTC objects is static for the lifetime of the
4199          * device and so cannot disappear as we iterate. Similarly, we can
4200          * happily treat the predicates as racy, atomic checks as userspace
4201          * cannot claim and pin a new fb without at least acquring the
4202          * struct_mutex and so serialising with us.
4203          */
4204         for_each_intel_crtc(&dev_priv->drm, crtc) {
4205                 if (atomic_read(&crtc->unpin_work_count) == 0)
4206                         continue;
4207
4208                 if (crtc->flip_work)
4209                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4210
4211                 return true;
4212         }
4213
4214         return false;
4215 }
4216
4217 static void page_flip_completed(struct intel_crtc *intel_crtc)
4218 {
4219         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4220         struct intel_flip_work *work = intel_crtc->flip_work;
4221
4222         intel_crtc->flip_work = NULL;
4223
4224         if (work->event)
4225                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4226
4227         drm_crtc_vblank_put(&intel_crtc->base);
4228
4229         wake_up_all(&dev_priv->pending_flip_queue);
4230         trace_i915_flip_complete(intel_crtc->plane,
4231                                  work->pending_flip_obj);
4232
4233         queue_work(dev_priv->wq, &work->unpin_work);
4234 }
4235
4236 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4237 {
4238         struct drm_device *dev = crtc->dev;
4239         struct drm_i915_private *dev_priv = to_i915(dev);
4240         long ret;
4241
4242         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4243
4244         ret = wait_event_interruptible_timeout(
4245                                         dev_priv->pending_flip_queue,
4246                                         !intel_crtc_has_pending_flip(crtc),
4247                                         60*HZ);
4248
4249         if (ret < 0)
4250                 return ret;
4251
4252         if (ret == 0) {
4253                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4254                 struct intel_flip_work *work;
4255
4256                 spin_lock_irq(&dev->event_lock);
4257                 work = intel_crtc->flip_work;
4258                 if (work && !is_mmio_work(work)) {
4259                         WARN_ONCE(1, "Removing stuck page flip\n");
4260                         page_flip_completed(intel_crtc);
4261                 }
4262                 spin_unlock_irq(&dev->event_lock);
4263         }
4264
4265         return 0;
4266 }
4267
4268 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4269 {
4270         u32 temp;
4271
4272         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4273
4274         mutex_lock(&dev_priv->sb_lock);
4275
4276         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4277         temp |= SBI_SSCCTL_DISABLE;
4278         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4279
4280         mutex_unlock(&dev_priv->sb_lock);
4281 }
4282
4283 /* Program iCLKIP clock to the desired frequency */
4284 static void lpt_program_iclkip(struct intel_crtc *crtc)
4285 {
4286         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4287         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4288         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4289         u32 temp;
4290
4291         lpt_disable_iclkip(dev_priv);
4292
4293         /* The iCLK virtual clock root frequency is in MHz,
4294          * but the adjusted_mode->crtc_clock in in KHz. To get the
4295          * divisors, it is necessary to divide one by another, so we
4296          * convert the virtual clock precision to KHz here for higher
4297          * precision.
4298          */
4299         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4300                 u32 iclk_virtual_root_freq = 172800 * 1000;
4301                 u32 iclk_pi_range = 64;
4302                 u32 desired_divisor;
4303
4304                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4305                                                     clock << auxdiv);
4306                 divsel = (desired_divisor / iclk_pi_range) - 2;
4307                 phaseinc = desired_divisor % iclk_pi_range;
4308
4309                 /*
4310                  * Near 20MHz is a corner case which is
4311                  * out of range for the 7-bit divisor
4312                  */
4313                 if (divsel <= 0x7f)
4314                         break;
4315         }
4316
4317         /* This should not happen with any sane values */
4318         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4319                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4320         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4321                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4322
4323         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4324                         clock,
4325                         auxdiv,
4326                         divsel,
4327                         phasedir,
4328                         phaseinc);
4329
4330         mutex_lock(&dev_priv->sb_lock);
4331
4332         /* Program SSCDIVINTPHASE6 */
4333         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4334         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4335         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4336         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4337         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4338         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4339         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4340         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4341
4342         /* Program SSCAUXDIV */
4343         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4344         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4345         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4346         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4347
4348         /* Enable modulator and associated divider */
4349         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4350         temp &= ~SBI_SSCCTL_DISABLE;
4351         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4352
4353         mutex_unlock(&dev_priv->sb_lock);
4354
4355         /* Wait for initialization time */
4356         udelay(24);
4357
4358         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4359 }
4360
4361 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4362 {
4363         u32 divsel, phaseinc, auxdiv;
4364         u32 iclk_virtual_root_freq = 172800 * 1000;
4365         u32 iclk_pi_range = 64;
4366         u32 desired_divisor;
4367         u32 temp;
4368
4369         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4370                 return 0;
4371
4372         mutex_lock(&dev_priv->sb_lock);
4373
4374         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4375         if (temp & SBI_SSCCTL_DISABLE) {
4376                 mutex_unlock(&dev_priv->sb_lock);
4377                 return 0;
4378         }
4379
4380         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4381         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4382                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4383         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4384                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4385
4386         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4387         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4388                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4389
4390         mutex_unlock(&dev_priv->sb_lock);
4391
4392         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4393
4394         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4395                                  desired_divisor << auxdiv);
4396 }
4397
4398 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4399                                                 enum pipe pch_transcoder)
4400 {
4401         struct drm_device *dev = crtc->base.dev;
4402         struct drm_i915_private *dev_priv = to_i915(dev);
4403         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4404
4405         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4406                    I915_READ(HTOTAL(cpu_transcoder)));
4407         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4408                    I915_READ(HBLANK(cpu_transcoder)));
4409         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4410                    I915_READ(HSYNC(cpu_transcoder)));
4411
4412         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4413                    I915_READ(VTOTAL(cpu_transcoder)));
4414         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4415                    I915_READ(VBLANK(cpu_transcoder)));
4416         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4417                    I915_READ(VSYNC(cpu_transcoder)));
4418         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4419                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4420 }
4421
4422 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4423 {
4424         struct drm_i915_private *dev_priv = to_i915(dev);
4425         uint32_t temp;
4426
4427         temp = I915_READ(SOUTH_CHICKEN1);
4428         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4429                 return;
4430
4431         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4432         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4433
4434         temp &= ~FDI_BC_BIFURCATION_SELECT;
4435         if (enable)
4436                 temp |= FDI_BC_BIFURCATION_SELECT;
4437
4438         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4439         I915_WRITE(SOUTH_CHICKEN1, temp);
4440         POSTING_READ(SOUTH_CHICKEN1);
4441 }
4442
4443 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4444 {
4445         struct drm_device *dev = intel_crtc->base.dev;
4446
4447         switch (intel_crtc->pipe) {
4448         case PIPE_A:
4449                 break;
4450         case PIPE_B:
4451                 if (intel_crtc->config->fdi_lanes > 2)
4452                         cpt_set_fdi_bc_bifurcation(dev, false);
4453                 else
4454                         cpt_set_fdi_bc_bifurcation(dev, true);
4455
4456                 break;
4457         case PIPE_C:
4458                 cpt_set_fdi_bc_bifurcation(dev, true);
4459
4460                 break;
4461         default:
4462                 BUG();
4463         }
4464 }
4465
4466 /* Return which DP Port should be selected for Transcoder DP control */
4467 static enum port
4468 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4469 {
4470         struct drm_device *dev = crtc->base.dev;
4471         struct intel_encoder *encoder;
4472
4473         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4474                 if (encoder->type == INTEL_OUTPUT_DP ||
4475                     encoder->type == INTEL_OUTPUT_EDP)
4476                         return enc_to_dig_port(&encoder->base)->port;
4477         }
4478
4479         return -1;
4480 }
4481
4482 /*
4483  * Enable PCH resources required for PCH ports:
4484  *   - PCH PLLs
4485  *   - FDI training & RX/TX
4486  *   - update transcoder timings
4487  *   - DP transcoding bits
4488  *   - transcoder
4489  */
4490 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4491 {
4492         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4493         struct drm_device *dev = crtc->base.dev;
4494         struct drm_i915_private *dev_priv = to_i915(dev);
4495         int pipe = crtc->pipe;
4496         u32 temp;
4497
4498         assert_pch_transcoder_disabled(dev_priv, pipe);
4499
4500         if (IS_IVYBRIDGE(dev_priv))
4501                 ivybridge_update_fdi_bc_bifurcation(crtc);
4502
4503         /* Write the TU size bits before fdi link training, so that error
4504          * detection works. */
4505         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4506                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4507
4508         /* For PCH output, training FDI link */
4509         dev_priv->display.fdi_link_train(crtc, crtc_state);
4510
4511         /* We need to program the right clock selection before writing the pixel
4512          * mutliplier into the DPLL. */
4513         if (HAS_PCH_CPT(dev_priv)) {
4514                 u32 sel;
4515
4516                 temp = I915_READ(PCH_DPLL_SEL);
4517                 temp |= TRANS_DPLL_ENABLE(pipe);
4518                 sel = TRANS_DPLLB_SEL(pipe);
4519                 if (crtc_state->shared_dpll ==
4520                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4521                         temp |= sel;
4522                 else
4523                         temp &= ~sel;
4524                 I915_WRITE(PCH_DPLL_SEL, temp);
4525         }
4526
4527         /* XXX: pch pll's can be enabled any time before we enable the PCH
4528          * transcoder, and we actually should do this to not upset any PCH
4529          * transcoder that already use the clock when we share it.
4530          *
4531          * Note that enable_shared_dpll tries to do the right thing, but
4532          * get_shared_dpll unconditionally resets the pll - we need that to have
4533          * the right LVDS enable sequence. */
4534         intel_enable_shared_dpll(crtc);
4535
4536         /* set transcoder timing, panel must allow it */
4537         assert_panel_unlocked(dev_priv, pipe);
4538         ironlake_pch_transcoder_set_timings(crtc, pipe);
4539
4540         intel_fdi_normal_train(crtc);
4541
4542         /* For PCH DP, enable TRANS_DP_CTL */
4543         if (HAS_PCH_CPT(dev_priv) &&
4544             intel_crtc_has_dp_encoder(crtc_state)) {
4545                 const struct drm_display_mode *adjusted_mode =
4546                         &crtc_state->base.adjusted_mode;
4547                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4548                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4549                 temp = I915_READ(reg);
4550                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4551                           TRANS_DP_SYNC_MASK |
4552                           TRANS_DP_BPC_MASK);
4553                 temp |= TRANS_DP_OUTPUT_ENABLE;
4554                 temp |= bpc << 9; /* same format but at 11:9 */
4555
4556                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4557                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4558                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4559                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4560
4561                 switch (intel_trans_dp_port_sel(crtc)) {
4562                 case PORT_B:
4563                         temp |= TRANS_DP_PORT_SEL_B;
4564                         break;
4565                 case PORT_C:
4566                         temp |= TRANS_DP_PORT_SEL_C;
4567                         break;
4568                 case PORT_D:
4569                         temp |= TRANS_DP_PORT_SEL_D;
4570                         break;
4571                 default:
4572                         BUG();
4573                 }
4574
4575                 I915_WRITE(reg, temp);
4576         }
4577
4578         ironlake_enable_pch_transcoder(dev_priv, pipe);
4579 }
4580
4581 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4582 {
4583         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4584         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4585         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4586
4587         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4588
4589         lpt_program_iclkip(crtc);
4590
4591         /* Set transcoder timing. */
4592         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4593
4594         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4595 }
4596
4597 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4598 {
4599         struct drm_i915_private *dev_priv = to_i915(dev);
4600         i915_reg_t dslreg = PIPEDSL(pipe);
4601         u32 temp;
4602
4603         temp = I915_READ(dslreg);
4604         udelay(500);
4605         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4606                 if (wait_for(I915_READ(dslreg) != temp, 5))
4607                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4608         }
4609 }
4610
4611 static int
4612 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4613                   unsigned int scaler_user, int *scaler_id,
4614                   int src_w, int src_h, int dst_w, int dst_h)
4615 {
4616         struct intel_crtc_scaler_state *scaler_state =
4617                 &crtc_state->scaler_state;
4618         struct intel_crtc *intel_crtc =
4619                 to_intel_crtc(crtc_state->base.crtc);
4620         int need_scaling;
4621
4622         /*
4623          * Src coordinates are already rotated by 270 degrees for
4624          * the 90/270 degree plane rotation cases (to match the
4625          * GTT mapping), hence no need to account for rotation here.
4626          */
4627         need_scaling = src_w != dst_w || src_h != dst_h;
4628
4629         /*
4630          * if plane is being disabled or scaler is no more required or force detach
4631          *  - free scaler binded to this plane/crtc
4632          *  - in order to do this, update crtc->scaler_usage
4633          *
4634          * Here scaler state in crtc_state is set free so that
4635          * scaler can be assigned to other user. Actual register
4636          * update to free the scaler is done in plane/panel-fit programming.
4637          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4638          */
4639         if (force_detach || !need_scaling) {
4640                 if (*scaler_id >= 0) {
4641                         scaler_state->scaler_users &= ~(1 << scaler_user);
4642                         scaler_state->scalers[*scaler_id].in_use = 0;
4643
4644                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4645                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4646                                 intel_crtc->pipe, scaler_user, *scaler_id,
4647                                 scaler_state->scaler_users);
4648                         *scaler_id = -1;
4649                 }
4650                 return 0;
4651         }
4652
4653         /* range checks */
4654         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4655                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4656
4657                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4658                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4659                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4660                         "size is out of scaler range\n",
4661                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4662                 return -EINVAL;
4663         }
4664
4665         /* mark this plane as a scaler user in crtc_state */
4666         scaler_state->scaler_users |= (1 << scaler_user);
4667         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4668                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4669                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4670                 scaler_state->scaler_users);
4671
4672         return 0;
4673 }
4674
4675 /**
4676  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4677  *
4678  * @state: crtc's scaler state
4679  *
4680  * Return
4681  *     0 - scaler_usage updated successfully
4682  *    error - requested scaling cannot be supported or other error condition
4683  */
4684 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4685 {
4686         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4687
4688         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4689                 &state->scaler_state.scaler_id,
4690                 state->pipe_src_w, state->pipe_src_h,
4691                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4692 }
4693
4694 /**
4695  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4696  *
4697  * @state: crtc's scaler state
4698  * @plane_state: atomic plane state to update
4699  *
4700  * Return
4701  *     0 - scaler_usage updated successfully
4702  *    error - requested scaling cannot be supported or other error condition
4703  */
4704 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4705                                    struct intel_plane_state *plane_state)
4706 {
4707
4708         struct intel_plane *intel_plane =
4709                 to_intel_plane(plane_state->base.plane);
4710         struct drm_framebuffer *fb = plane_state->base.fb;
4711         int ret;
4712
4713         bool force_detach = !fb || !plane_state->base.visible;
4714
4715         ret = skl_update_scaler(crtc_state, force_detach,
4716                                 drm_plane_index(&intel_plane->base),
4717                                 &plane_state->scaler_id,
4718                                 drm_rect_width(&plane_state->base.src) >> 16,
4719                                 drm_rect_height(&plane_state->base.src) >> 16,
4720                                 drm_rect_width(&plane_state->base.dst),
4721                                 drm_rect_height(&plane_state->base.dst));
4722
4723         if (ret || plane_state->scaler_id < 0)
4724                 return ret;
4725
4726         /* check colorkey */
4727         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4728                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4729                               intel_plane->base.base.id,
4730                               intel_plane->base.name);
4731                 return -EINVAL;
4732         }
4733
4734         /* Check src format */
4735         switch (fb->format->format) {
4736         case DRM_FORMAT_RGB565:
4737         case DRM_FORMAT_XBGR8888:
4738         case DRM_FORMAT_XRGB8888:
4739         case DRM_FORMAT_ABGR8888:
4740         case DRM_FORMAT_ARGB8888:
4741         case DRM_FORMAT_XRGB2101010:
4742         case DRM_FORMAT_XBGR2101010:
4743         case DRM_FORMAT_YUYV:
4744         case DRM_FORMAT_YVYU:
4745         case DRM_FORMAT_UYVY:
4746         case DRM_FORMAT_VYUY:
4747                 break;
4748         default:
4749                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4750                               intel_plane->base.base.id, intel_plane->base.name,
4751                               fb->base.id, fb->format->format);
4752                 return -EINVAL;
4753         }
4754
4755         return 0;
4756 }
4757
4758 static void skylake_scaler_disable(struct intel_crtc *crtc)
4759 {
4760         int i;
4761
4762         for (i = 0; i < crtc->num_scalers; i++)
4763                 skl_detach_scaler(crtc, i);
4764 }
4765
4766 static void skylake_pfit_enable(struct intel_crtc *crtc)
4767 {
4768         struct drm_device *dev = crtc->base.dev;
4769         struct drm_i915_private *dev_priv = to_i915(dev);
4770         int pipe = crtc->pipe;
4771         struct intel_crtc_scaler_state *scaler_state =
4772                 &crtc->config->scaler_state;
4773
4774         if (crtc->config->pch_pfit.enabled) {
4775                 int id;
4776
4777                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4778                         return;
4779
4780                 id = scaler_state->scaler_id;
4781                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4782                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4783                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4784                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4785         }
4786 }
4787
4788 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4789 {
4790         struct drm_device *dev = crtc->base.dev;
4791         struct drm_i915_private *dev_priv = to_i915(dev);
4792         int pipe = crtc->pipe;
4793
4794         if (crtc->config->pch_pfit.enabled) {
4795                 /* Force use of hard-coded filter coefficients
4796                  * as some pre-programmed values are broken,
4797                  * e.g. x201.
4798                  */
4799                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4800                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4801                                                  PF_PIPE_SEL_IVB(pipe));
4802                 else
4803                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4804                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4805                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4806         }
4807 }
4808
4809 void hsw_enable_ips(struct intel_crtc *crtc)
4810 {
4811         struct drm_device *dev = crtc->base.dev;
4812         struct drm_i915_private *dev_priv = to_i915(dev);
4813
4814         if (!crtc->config->ips_enabled)
4815                 return;
4816
4817         /*
4818          * We can only enable IPS after we enable a plane and wait for a vblank
4819          * This function is called from post_plane_update, which is run after
4820          * a vblank wait.
4821          */
4822
4823         assert_plane_enabled(dev_priv, crtc->plane);
4824         if (IS_BROADWELL(dev_priv)) {
4825                 mutex_lock(&dev_priv->rps.hw_lock);
4826                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4827                 mutex_unlock(&dev_priv->rps.hw_lock);
4828                 /* Quoting Art Runyan: "its not safe to expect any particular
4829                  * value in IPS_CTL bit 31 after enabling IPS through the
4830                  * mailbox." Moreover, the mailbox may return a bogus state,
4831                  * so we need to just enable it and continue on.
4832                  */
4833         } else {
4834                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4835                 /* The bit only becomes 1 in the next vblank, so this wait here
4836                  * is essentially intel_wait_for_vblank. If we don't have this
4837                  * and don't wait for vblanks until the end of crtc_enable, then
4838                  * the HW state readout code will complain that the expected
4839                  * IPS_CTL value is not the one we read. */
4840                 if (intel_wait_for_register(dev_priv,
4841                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4842                                             50))
4843                         DRM_ERROR("Timed out waiting for IPS enable\n");
4844         }
4845 }
4846
4847 void hsw_disable_ips(struct intel_crtc *crtc)
4848 {
4849         struct drm_device *dev = crtc->base.dev;
4850         struct drm_i915_private *dev_priv = to_i915(dev);
4851
4852         if (!crtc->config->ips_enabled)
4853                 return;
4854
4855         assert_plane_enabled(dev_priv, crtc->plane);
4856         if (IS_BROADWELL(dev_priv)) {
4857                 mutex_lock(&dev_priv->rps.hw_lock);
4858                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4859                 mutex_unlock(&dev_priv->rps.hw_lock);
4860                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4861                 if (intel_wait_for_register(dev_priv,
4862                                             IPS_CTL, IPS_ENABLE, 0,
4863                                             42))
4864                         DRM_ERROR("Timed out waiting for IPS disable\n");
4865         } else {
4866                 I915_WRITE(IPS_CTL, 0);
4867                 POSTING_READ(IPS_CTL);
4868         }
4869
4870         /* We need to wait for a vblank before we can disable the plane. */
4871         intel_wait_for_vblank(dev_priv, crtc->pipe);
4872 }
4873
4874 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4875 {
4876         if (intel_crtc->overlay) {
4877                 struct drm_device *dev = intel_crtc->base.dev;
4878
4879                 mutex_lock(&dev->struct_mutex);
4880                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4881                 mutex_unlock(&dev->struct_mutex);
4882         }
4883
4884         /* Let userspace switch the overlay on again. In most cases userspace
4885          * has to recompute where to put it anyway.
4886          */
4887 }
4888
4889 /**
4890  * intel_post_enable_primary - Perform operations after enabling primary plane
4891  * @crtc: the CRTC whose primary plane was just enabled
4892  *
4893  * Performs potentially sleeping operations that must be done after the primary
4894  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4895  * called due to an explicit primary plane update, or due to an implicit
4896  * re-enable that is caused when a sprite plane is updated to no longer
4897  * completely hide the primary plane.
4898  */
4899 static void
4900 intel_post_enable_primary(struct drm_crtc *crtc)
4901 {
4902         struct drm_device *dev = crtc->dev;
4903         struct drm_i915_private *dev_priv = to_i915(dev);
4904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905         int pipe = intel_crtc->pipe;
4906
4907         /*
4908          * FIXME IPS should be fine as long as one plane is
4909          * enabled, but in practice it seems to have problems
4910          * when going from primary only to sprite only and vice
4911          * versa.
4912          */
4913         hsw_enable_ips(intel_crtc);
4914
4915         /*
4916          * Gen2 reports pipe underruns whenever all planes are disabled.
4917          * So don't enable underrun reporting before at least some planes
4918          * are enabled.
4919          * FIXME: Need to fix the logic to work when we turn off all planes
4920          * but leave the pipe running.
4921          */
4922         if (IS_GEN2(dev_priv))
4923                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4924
4925         /* Underruns don't always raise interrupts, so check manually. */
4926         intel_check_cpu_fifo_underruns(dev_priv);
4927         intel_check_pch_fifo_underruns(dev_priv);
4928 }
4929
4930 /* FIXME move all this to pre_plane_update() with proper state tracking */
4931 static void
4932 intel_pre_disable_primary(struct drm_crtc *crtc)
4933 {
4934         struct drm_device *dev = crtc->dev;
4935         struct drm_i915_private *dev_priv = to_i915(dev);
4936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4937         int pipe = intel_crtc->pipe;
4938
4939         /*
4940          * Gen2 reports pipe underruns whenever all planes are disabled.
4941          * So diasble underrun reporting before all the planes get disabled.
4942          * FIXME: Need to fix the logic to work when we turn off all planes
4943          * but leave the pipe running.
4944          */
4945         if (IS_GEN2(dev_priv))
4946                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4947
4948         /*
4949          * FIXME IPS should be fine as long as one plane is
4950          * enabled, but in practice it seems to have problems
4951          * when going from primary only to sprite only and vice
4952          * versa.
4953          */
4954         hsw_disable_ips(intel_crtc);
4955 }
4956
4957 /* FIXME get rid of this and use pre_plane_update */
4958 static void
4959 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4960 {
4961         struct drm_device *dev = crtc->dev;
4962         struct drm_i915_private *dev_priv = to_i915(dev);
4963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4964         int pipe = intel_crtc->pipe;
4965
4966         intel_pre_disable_primary(crtc);
4967
4968         /*
4969          * Vblank time updates from the shadow to live plane control register
4970          * are blocked if the memory self-refresh mode is active at that
4971          * moment. So to make sure the plane gets truly disabled, disable
4972          * first the self-refresh mode. The self-refresh enable bit in turn
4973          * will be checked/applied by the HW only at the next frame start
4974          * event which is after the vblank start event, so we need to have a
4975          * wait-for-vblank between disabling the plane and the pipe.
4976          */
4977         if (HAS_GMCH_DISPLAY(dev_priv) &&
4978             intel_set_memory_cxsr(dev_priv, false))
4979                 intel_wait_for_vblank(dev_priv, pipe);
4980 }
4981
4982 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4983 {
4984         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4985         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4986         struct intel_crtc_state *pipe_config =
4987                 to_intel_crtc_state(crtc->base.state);
4988         struct drm_plane *primary = crtc->base.primary;
4989         struct drm_plane_state *old_pri_state =
4990                 drm_atomic_get_existing_plane_state(old_state, primary);
4991
4992         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4993
4994         if (pipe_config->update_wm_post && pipe_config->base.active)
4995                 intel_update_watermarks(crtc);
4996
4997         if (old_pri_state) {
4998                 struct intel_plane_state *primary_state =
4999                         to_intel_plane_state(primary->state);
5000                 struct intel_plane_state *old_primary_state =
5001                         to_intel_plane_state(old_pri_state);
5002
5003                 intel_fbc_post_update(crtc);
5004
5005                 if (primary_state->base.visible &&
5006                     (needs_modeset(&pipe_config->base) ||
5007                      !old_primary_state->base.visible))
5008                         intel_post_enable_primary(&crtc->base);
5009         }
5010 }
5011
5012 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5013                                    struct intel_crtc_state *pipe_config)
5014 {
5015         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5016         struct drm_device *dev = crtc->base.dev;
5017         struct drm_i915_private *dev_priv = to_i915(dev);
5018         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5019         struct drm_plane *primary = crtc->base.primary;
5020         struct drm_plane_state *old_pri_state =
5021                 drm_atomic_get_existing_plane_state(old_state, primary);
5022         bool modeset = needs_modeset(&pipe_config->base);
5023         struct intel_atomic_state *old_intel_state =
5024                 to_intel_atomic_state(old_state);
5025
5026         if (old_pri_state) {
5027                 struct intel_plane_state *primary_state =
5028                         to_intel_plane_state(primary->state);
5029                 struct intel_plane_state *old_primary_state =
5030                         to_intel_plane_state(old_pri_state);
5031
5032                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5033
5034                 if (old_primary_state->base.visible &&
5035                     (modeset || !primary_state->base.visible))
5036                         intel_pre_disable_primary(&crtc->base);
5037         }
5038
5039         /*
5040          * Vblank time updates from the shadow to live plane control register
5041          * are blocked if the memory self-refresh mode is active at that
5042          * moment. So to make sure the plane gets truly disabled, disable
5043          * first the self-refresh mode. The self-refresh enable bit in turn
5044          * will be checked/applied by the HW only at the next frame start
5045          * event which is after the vblank start event, so we need to have a
5046          * wait-for-vblank between disabling the plane and the pipe.
5047          */
5048         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5049             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5050                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5051
5052         /*
5053          * IVB workaround: must disable low power watermarks for at least
5054          * one frame before enabling scaling.  LP watermarks can be re-enabled
5055          * when scaling is disabled.
5056          *
5057          * WaCxSRDisabledForSpriteScaling:ivb
5058          */
5059         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5060                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5061
5062         /*
5063          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5064          * watermark programming here.
5065          */
5066         if (needs_modeset(&pipe_config->base))
5067                 return;
5068
5069         /*
5070          * For platforms that support atomic watermarks, program the
5071          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5072          * will be the intermediate values that are safe for both pre- and
5073          * post- vblank; when vblank happens, the 'active' values will be set
5074          * to the final 'target' values and we'll do this again to get the
5075          * optimal watermarks.  For gen9+ platforms, the values we program here
5076          * will be the final target values which will get automatically latched
5077          * at vblank time; no further programming will be necessary.
5078          *
5079          * If a platform hasn't been transitioned to atomic watermarks yet,
5080          * we'll continue to update watermarks the old way, if flags tell
5081          * us to.
5082          */
5083         if (dev_priv->display.initial_watermarks != NULL)
5084                 dev_priv->display.initial_watermarks(old_intel_state,
5085                                                      pipe_config);
5086         else if (pipe_config->update_wm_pre)
5087                 intel_update_watermarks(crtc);
5088 }
5089
5090 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5091 {
5092         struct drm_device *dev = crtc->dev;
5093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5094         struct drm_plane *p;
5095         int pipe = intel_crtc->pipe;
5096
5097         intel_crtc_dpms_overlay_disable(intel_crtc);
5098
5099         drm_for_each_plane_mask(p, dev, plane_mask)
5100                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5101
5102         /*
5103          * FIXME: Once we grow proper nuclear flip support out of this we need
5104          * to compute the mask of flip planes precisely. For the time being
5105          * consider this a flip to a NULL plane.
5106          */
5107         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5108 }
5109
5110 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5111                                           struct intel_crtc_state *crtc_state,
5112                                           struct drm_atomic_state *old_state)
5113 {
5114         struct drm_connector_state *conn_state;
5115         struct drm_connector *conn;
5116         int i;
5117
5118         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5119                 struct intel_encoder *encoder =
5120                         to_intel_encoder(conn_state->best_encoder);
5121
5122                 if (conn_state->crtc != crtc)
5123                         continue;
5124
5125                 if (encoder->pre_pll_enable)
5126                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5127         }
5128 }
5129
5130 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5131                                       struct intel_crtc_state *crtc_state,
5132                                       struct drm_atomic_state *old_state)
5133 {
5134         struct drm_connector_state *conn_state;
5135         struct drm_connector *conn;
5136         int i;
5137
5138         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5139                 struct intel_encoder *encoder =
5140                         to_intel_encoder(conn_state->best_encoder);
5141
5142                 if (conn_state->crtc != crtc)
5143                         continue;
5144
5145                 if (encoder->pre_enable)
5146                         encoder->pre_enable(encoder, crtc_state, conn_state);
5147         }
5148 }
5149
5150 static void intel_encoders_enable(struct drm_crtc *crtc,
5151                                   struct intel_crtc_state *crtc_state,
5152                                   struct drm_atomic_state *old_state)
5153 {
5154         struct drm_connector_state *conn_state;
5155         struct drm_connector *conn;
5156         int i;
5157
5158         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5159                 struct intel_encoder *encoder =
5160                         to_intel_encoder(conn_state->best_encoder);
5161
5162                 if (conn_state->crtc != crtc)
5163                         continue;
5164
5165                 encoder->enable(encoder, crtc_state, conn_state);
5166                 intel_opregion_notify_encoder(encoder, true);
5167         }
5168 }
5169
5170 static void intel_encoders_disable(struct drm_crtc *crtc,
5171                                    struct intel_crtc_state *old_crtc_state,
5172                                    struct drm_atomic_state *old_state)
5173 {
5174         struct drm_connector_state *old_conn_state;
5175         struct drm_connector *conn;
5176         int i;
5177
5178         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5179                 struct intel_encoder *encoder =
5180                         to_intel_encoder(old_conn_state->best_encoder);
5181
5182                 if (old_conn_state->crtc != crtc)
5183                         continue;
5184
5185                 intel_opregion_notify_encoder(encoder, false);
5186                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5187         }
5188 }
5189
5190 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5191                                         struct intel_crtc_state *old_crtc_state,
5192                                         struct drm_atomic_state *old_state)
5193 {
5194         struct drm_connector_state *old_conn_state;
5195         struct drm_connector *conn;
5196         int i;
5197
5198         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5199                 struct intel_encoder *encoder =
5200                         to_intel_encoder(old_conn_state->best_encoder);
5201
5202                 if (old_conn_state->crtc != crtc)
5203                         continue;
5204
5205                 if (encoder->post_disable)
5206                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5207         }
5208 }
5209
5210 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5211                                             struct intel_crtc_state *old_crtc_state,
5212                                             struct drm_atomic_state *old_state)
5213 {
5214         struct drm_connector_state *old_conn_state;
5215         struct drm_connector *conn;
5216         int i;
5217
5218         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5219                 struct intel_encoder *encoder =
5220                         to_intel_encoder(old_conn_state->best_encoder);
5221
5222                 if (old_conn_state->crtc != crtc)
5223                         continue;
5224
5225                 if (encoder->post_pll_disable)
5226                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5227         }
5228 }
5229
5230 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5231                                  struct drm_atomic_state *old_state)
5232 {
5233         struct drm_crtc *crtc = pipe_config->base.crtc;
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_i915_private *dev_priv = to_i915(dev);
5236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237         int pipe = intel_crtc->pipe;
5238         struct intel_atomic_state *old_intel_state =
5239                 to_intel_atomic_state(old_state);
5240
5241         if (WARN_ON(intel_crtc->active))
5242                 return;
5243
5244         /*
5245          * Sometimes spurious CPU pipe underruns happen during FDI
5246          * training, at least with VGA+HDMI cloning. Suppress them.
5247          *
5248          * On ILK we get an occasional spurious CPU pipe underruns
5249          * between eDP port A enable and vdd enable. Also PCH port
5250          * enable seems to result in the occasional CPU pipe underrun.
5251          *
5252          * Spurious PCH underruns also occur during PCH enabling.
5253          */
5254         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5255                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5256         if (intel_crtc->config->has_pch_encoder)
5257                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5258
5259         if (intel_crtc->config->has_pch_encoder)
5260                 intel_prepare_shared_dpll(intel_crtc);
5261
5262         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5263                 intel_dp_set_m_n(intel_crtc, M1_N1);
5264
5265         intel_set_pipe_timings(intel_crtc);
5266         intel_set_pipe_src_size(intel_crtc);
5267
5268         if (intel_crtc->config->has_pch_encoder) {
5269                 intel_cpu_transcoder_set_m_n(intel_crtc,
5270                                      &intel_crtc->config->fdi_m_n, NULL);
5271         }
5272
5273         ironlake_set_pipeconf(crtc);
5274
5275         intel_crtc->active = true;
5276
5277         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5278
5279         if (intel_crtc->config->has_pch_encoder) {
5280                 /* Note: FDI PLL enabling _must_ be done before we enable the
5281                  * cpu pipes, hence this is separate from all the other fdi/pch
5282                  * enabling. */
5283                 ironlake_fdi_pll_enable(intel_crtc);
5284         } else {
5285                 assert_fdi_tx_disabled(dev_priv, pipe);
5286                 assert_fdi_rx_disabled(dev_priv, pipe);
5287         }
5288
5289         ironlake_pfit_enable(intel_crtc);
5290
5291         /*
5292          * On ILK+ LUT must be loaded before the pipe is running but with
5293          * clocks enabled
5294          */
5295         intel_color_load_luts(&pipe_config->base);
5296
5297         if (dev_priv->display.initial_watermarks != NULL)
5298                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5299         intel_enable_pipe(intel_crtc);
5300
5301         if (intel_crtc->config->has_pch_encoder)
5302                 ironlake_pch_enable(pipe_config);
5303
5304         assert_vblank_disabled(crtc);
5305         drm_crtc_vblank_on(crtc);
5306
5307         intel_encoders_enable(crtc, pipe_config, old_state);
5308
5309         if (HAS_PCH_CPT(dev_priv))
5310                 cpt_verify_modeset(dev, intel_crtc->pipe);
5311
5312         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5313         if (intel_crtc->config->has_pch_encoder)
5314                 intel_wait_for_vblank(dev_priv, pipe);
5315         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5316         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5317 }
5318
5319 /* IPS only exists on ULT machines and is tied to pipe A. */
5320 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5321 {
5322         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5323 }
5324
5325 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5326                                 struct drm_atomic_state *old_state)
5327 {
5328         struct drm_crtc *crtc = pipe_config->base.crtc;
5329         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5332         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5333         struct intel_atomic_state *old_intel_state =
5334                 to_intel_atomic_state(old_state);
5335
5336         if (WARN_ON(intel_crtc->active))
5337                 return;
5338
5339         if (intel_crtc->config->has_pch_encoder)
5340                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5341                                                       false);
5342
5343         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5344
5345         if (intel_crtc->config->shared_dpll)
5346                 intel_enable_shared_dpll(intel_crtc);
5347
5348         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5349                 intel_dp_set_m_n(intel_crtc, M1_N1);
5350
5351         if (!transcoder_is_dsi(cpu_transcoder))
5352                 intel_set_pipe_timings(intel_crtc);
5353
5354         intel_set_pipe_src_size(intel_crtc);
5355
5356         if (cpu_transcoder != TRANSCODER_EDP &&
5357             !transcoder_is_dsi(cpu_transcoder)) {
5358                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5359                            intel_crtc->config->pixel_multiplier - 1);
5360         }
5361
5362         if (intel_crtc->config->has_pch_encoder) {
5363                 intel_cpu_transcoder_set_m_n(intel_crtc,
5364                                      &intel_crtc->config->fdi_m_n, NULL);
5365         }
5366
5367         if (!transcoder_is_dsi(cpu_transcoder))
5368                 haswell_set_pipeconf(crtc);
5369
5370         haswell_set_pipemisc(crtc);
5371
5372         intel_color_set_csc(&pipe_config->base);
5373
5374         intel_crtc->active = true;
5375
5376         if (intel_crtc->config->has_pch_encoder)
5377                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5378         else
5379                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5380
5381         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5382
5383         if (intel_crtc->config->has_pch_encoder)
5384                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5385
5386         if (!transcoder_is_dsi(cpu_transcoder))
5387                 intel_ddi_enable_pipe_clock(pipe_config);
5388
5389         if (INTEL_GEN(dev_priv) >= 9)
5390                 skylake_pfit_enable(intel_crtc);
5391         else
5392                 ironlake_pfit_enable(intel_crtc);
5393
5394         /*
5395          * On ILK+ LUT must be loaded before the pipe is running but with
5396          * clocks enabled
5397          */
5398         intel_color_load_luts(&pipe_config->base);
5399
5400         intel_ddi_set_pipe_settings(pipe_config);
5401         if (!transcoder_is_dsi(cpu_transcoder))
5402                 intel_ddi_enable_transcoder_func(pipe_config);
5403
5404         if (dev_priv->display.initial_watermarks != NULL)
5405                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5406
5407         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5408         if (!transcoder_is_dsi(cpu_transcoder))
5409                 intel_enable_pipe(intel_crtc);
5410
5411         if (intel_crtc->config->has_pch_encoder)
5412                 lpt_pch_enable(pipe_config);
5413
5414         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5415                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5416
5417         assert_vblank_disabled(crtc);
5418         drm_crtc_vblank_on(crtc);
5419
5420         intel_encoders_enable(crtc, pipe_config, old_state);
5421
5422         if (intel_crtc->config->has_pch_encoder) {
5423                 intel_wait_for_vblank(dev_priv, pipe);
5424                 intel_wait_for_vblank(dev_priv, pipe);
5425                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5426                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5427                                                       true);
5428         }
5429
5430         /* If we change the relative order between pipe/planes enabling, we need
5431          * to change the workaround. */
5432         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5433         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5434                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5435                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5436         }
5437 }
5438
5439 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5440 {
5441         struct drm_device *dev = crtc->base.dev;
5442         struct drm_i915_private *dev_priv = to_i915(dev);
5443         int pipe = crtc->pipe;
5444
5445         /* To avoid upsetting the power well on haswell only disable the pfit if
5446          * it's in use. The hw state code will make sure we get this right. */
5447         if (force || crtc->config->pch_pfit.enabled) {
5448                 I915_WRITE(PF_CTL(pipe), 0);
5449                 I915_WRITE(PF_WIN_POS(pipe), 0);
5450                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5451         }
5452 }
5453
5454 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5455                                   struct drm_atomic_state *old_state)
5456 {
5457         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5458         struct drm_device *dev = crtc->dev;
5459         struct drm_i915_private *dev_priv = to_i915(dev);
5460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5461         int pipe = intel_crtc->pipe;
5462
5463         /*
5464          * Sometimes spurious CPU pipe underruns happen when the
5465          * pipe is already disabled, but FDI RX/TX is still enabled.
5466          * Happens at least with VGA+HDMI cloning. Suppress them.
5467          */
5468         if (intel_crtc->config->has_pch_encoder) {
5469                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5470                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5471         }
5472
5473         intel_encoders_disable(crtc, old_crtc_state, old_state);
5474
5475         drm_crtc_vblank_off(crtc);
5476         assert_vblank_disabled(crtc);
5477
5478         intel_disable_pipe(intel_crtc);
5479
5480         ironlake_pfit_disable(intel_crtc, false);
5481
5482         if (intel_crtc->config->has_pch_encoder)
5483                 ironlake_fdi_disable(crtc);
5484
5485         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5486
5487         if (intel_crtc->config->has_pch_encoder) {
5488                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5489
5490                 if (HAS_PCH_CPT(dev_priv)) {
5491                         i915_reg_t reg;
5492                         u32 temp;
5493
5494                         /* disable TRANS_DP_CTL */
5495                         reg = TRANS_DP_CTL(pipe);
5496                         temp = I915_READ(reg);
5497                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5498                                   TRANS_DP_PORT_SEL_MASK);
5499                         temp |= TRANS_DP_PORT_SEL_NONE;
5500                         I915_WRITE(reg, temp);
5501
5502                         /* disable DPLL_SEL */
5503                         temp = I915_READ(PCH_DPLL_SEL);
5504                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5505                         I915_WRITE(PCH_DPLL_SEL, temp);
5506                 }
5507
5508                 ironlake_fdi_pll_disable(intel_crtc);
5509         }
5510
5511         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5512         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5513 }
5514
5515 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5516                                  struct drm_atomic_state *old_state)
5517 {
5518         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5519         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5521         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5522
5523         if (intel_crtc->config->has_pch_encoder)
5524                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5525                                                       false);
5526
5527         intel_encoders_disable(crtc, old_crtc_state, old_state);
5528
5529         drm_crtc_vblank_off(crtc);
5530         assert_vblank_disabled(crtc);
5531
5532         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5533         if (!transcoder_is_dsi(cpu_transcoder))
5534                 intel_disable_pipe(intel_crtc);
5535
5536         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5537                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5538
5539         if (!transcoder_is_dsi(cpu_transcoder))
5540                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5541
5542         if (INTEL_GEN(dev_priv) >= 9)
5543                 skylake_scaler_disable(intel_crtc);
5544         else
5545                 ironlake_pfit_disable(intel_crtc, false);
5546
5547         if (!transcoder_is_dsi(cpu_transcoder))
5548                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5549
5550         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5551
5552         if (old_crtc_state->has_pch_encoder)
5553                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5554                                                       true);
5555 }
5556
5557 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5558 {
5559         struct drm_device *dev = crtc->base.dev;
5560         struct drm_i915_private *dev_priv = to_i915(dev);
5561         struct intel_crtc_state *pipe_config = crtc->config;
5562
5563         if (!pipe_config->gmch_pfit.control)
5564                 return;
5565
5566         /*
5567          * The panel fitter should only be adjusted whilst the pipe is disabled,
5568          * according to register description and PRM.
5569          */
5570         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5571         assert_pipe_disabled(dev_priv, crtc->pipe);
5572
5573         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5574         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5575
5576         /* Border color in case we don't scale up to the full screen. Black by
5577          * default, change to something else for debugging. */
5578         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5579 }
5580
5581 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5582 {
5583         switch (port) {
5584         case PORT_A:
5585                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5586         case PORT_B:
5587                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5588         case PORT_C:
5589                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5590         case PORT_D:
5591                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5592         case PORT_E:
5593                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5594         default:
5595                 MISSING_CASE(port);
5596                 return POWER_DOMAIN_PORT_OTHER;
5597         }
5598 }
5599
5600 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5601                                   struct intel_crtc_state *crtc_state)
5602 {
5603         struct drm_device *dev = crtc->dev;
5604         struct drm_i915_private *dev_priv = to_i915(dev);
5605         struct drm_encoder *encoder;
5606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5607         enum pipe pipe = intel_crtc->pipe;
5608         u64 mask;
5609         enum transcoder transcoder = crtc_state->cpu_transcoder;
5610
5611         if (!crtc_state->base.active)
5612                 return 0;
5613
5614         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5615         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5616         if (crtc_state->pch_pfit.enabled ||
5617             crtc_state->pch_pfit.force_thru)
5618                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5619
5620         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5621                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5622
5623                 mask |= BIT_ULL(intel_encoder->power_domain);
5624         }
5625
5626         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5627                 mask |= BIT(POWER_DOMAIN_AUDIO);
5628
5629         if (crtc_state->shared_dpll)
5630                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5631
5632         return mask;
5633 }
5634
5635 static u64
5636 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5637                                struct intel_crtc_state *crtc_state)
5638 {
5639         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5641         enum intel_display_power_domain domain;
5642         u64 domains, new_domains, old_domains;
5643
5644         old_domains = intel_crtc->enabled_power_domains;
5645         intel_crtc->enabled_power_domains = new_domains =
5646                 get_crtc_power_domains(crtc, crtc_state);
5647
5648         domains = new_domains & ~old_domains;
5649
5650         for_each_power_domain(domain, domains)
5651                 intel_display_power_get(dev_priv, domain);
5652
5653         return old_domains & ~new_domains;
5654 }
5655
5656 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5657                                       u64 domains)
5658 {
5659         enum intel_display_power_domain domain;
5660
5661         for_each_power_domain(domain, domains)
5662                 intel_display_power_put(dev_priv, domain);
5663 }
5664
5665 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5666                                    struct drm_atomic_state *old_state)
5667 {
5668         struct intel_atomic_state *old_intel_state =
5669                 to_intel_atomic_state(old_state);
5670         struct drm_crtc *crtc = pipe_config->base.crtc;
5671         struct drm_device *dev = crtc->dev;
5672         struct drm_i915_private *dev_priv = to_i915(dev);
5673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5674         int pipe = intel_crtc->pipe;
5675
5676         if (WARN_ON(intel_crtc->active))
5677                 return;
5678
5679         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5680                 intel_dp_set_m_n(intel_crtc, M1_N1);
5681
5682         intel_set_pipe_timings(intel_crtc);
5683         intel_set_pipe_src_size(intel_crtc);
5684
5685         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5686                 struct drm_i915_private *dev_priv = to_i915(dev);
5687
5688                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5689                 I915_WRITE(CHV_CANVAS(pipe), 0);
5690         }
5691
5692         i9xx_set_pipeconf(intel_crtc);
5693
5694         intel_crtc->active = true;
5695
5696         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5697
5698         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5699
5700         if (IS_CHERRYVIEW(dev_priv)) {
5701                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5702                 chv_enable_pll(intel_crtc, intel_crtc->config);
5703         } else {
5704                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5705                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5706         }
5707
5708         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5709
5710         i9xx_pfit_enable(intel_crtc);
5711
5712         intel_color_load_luts(&pipe_config->base);
5713
5714         dev_priv->display.initial_watermarks(old_intel_state,
5715                                              pipe_config);
5716         intel_enable_pipe(intel_crtc);
5717
5718         assert_vblank_disabled(crtc);
5719         drm_crtc_vblank_on(crtc);
5720
5721         intel_encoders_enable(crtc, pipe_config, old_state);
5722 }
5723
5724 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5725 {
5726         struct drm_device *dev = crtc->base.dev;
5727         struct drm_i915_private *dev_priv = to_i915(dev);
5728
5729         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5730         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5731 }
5732
5733 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5734                              struct drm_atomic_state *old_state)
5735 {
5736         struct intel_atomic_state *old_intel_state =
5737                 to_intel_atomic_state(old_state);
5738         struct drm_crtc *crtc = pipe_config->base.crtc;
5739         struct drm_device *dev = crtc->dev;
5740         struct drm_i915_private *dev_priv = to_i915(dev);
5741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5742         enum pipe pipe = intel_crtc->pipe;
5743
5744         if (WARN_ON(intel_crtc->active))
5745                 return;
5746
5747         i9xx_set_pll_dividers(intel_crtc);
5748
5749         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5750                 intel_dp_set_m_n(intel_crtc, M1_N1);
5751
5752         intel_set_pipe_timings(intel_crtc);
5753         intel_set_pipe_src_size(intel_crtc);
5754
5755         i9xx_set_pipeconf(intel_crtc);
5756
5757         intel_crtc->active = true;
5758
5759         if (!IS_GEN2(dev_priv))
5760                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5761
5762         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5763
5764         i9xx_enable_pll(intel_crtc);
5765
5766         i9xx_pfit_enable(intel_crtc);
5767
5768         intel_color_load_luts(&pipe_config->base);
5769
5770         if (dev_priv->display.initial_watermarks != NULL)
5771                 dev_priv->display.initial_watermarks(old_intel_state,
5772                                                      intel_crtc->config);
5773         else
5774                 intel_update_watermarks(intel_crtc);
5775         intel_enable_pipe(intel_crtc);
5776
5777         assert_vblank_disabled(crtc);
5778         drm_crtc_vblank_on(crtc);
5779
5780         intel_encoders_enable(crtc, pipe_config, old_state);
5781 }
5782
5783 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5784 {
5785         struct drm_device *dev = crtc->base.dev;
5786         struct drm_i915_private *dev_priv = to_i915(dev);
5787
5788         if (!crtc->config->gmch_pfit.control)
5789                 return;
5790
5791         assert_pipe_disabled(dev_priv, crtc->pipe);
5792
5793         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5794                          I915_READ(PFIT_CONTROL));
5795         I915_WRITE(PFIT_CONTROL, 0);
5796 }
5797
5798 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5799                               struct drm_atomic_state *old_state)
5800 {
5801         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5802         struct drm_device *dev = crtc->dev;
5803         struct drm_i915_private *dev_priv = to_i915(dev);
5804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5805         int pipe = intel_crtc->pipe;
5806
5807         /*
5808          * On gen2 planes are double buffered but the pipe isn't, so we must
5809          * wait for planes to fully turn off before disabling the pipe.
5810          */
5811         if (IS_GEN2(dev_priv))
5812                 intel_wait_for_vblank(dev_priv, pipe);
5813
5814         intel_encoders_disable(crtc, old_crtc_state, old_state);
5815
5816         drm_crtc_vblank_off(crtc);
5817         assert_vblank_disabled(crtc);
5818
5819         intel_disable_pipe(intel_crtc);
5820
5821         i9xx_pfit_disable(intel_crtc);
5822
5823         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5824
5825         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5826                 if (IS_CHERRYVIEW(dev_priv))
5827                         chv_disable_pll(dev_priv, pipe);
5828                 else if (IS_VALLEYVIEW(dev_priv))
5829                         vlv_disable_pll(dev_priv, pipe);
5830                 else
5831                         i9xx_disable_pll(intel_crtc);
5832         }
5833
5834         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5835
5836         if (!IS_GEN2(dev_priv))
5837                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5838
5839         if (!dev_priv->display.initial_watermarks)
5840                 intel_update_watermarks(intel_crtc);
5841 }
5842
5843 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5844 {
5845         struct intel_encoder *encoder;
5846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5847         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5848         enum intel_display_power_domain domain;
5849         u64 domains;
5850         struct drm_atomic_state *state;
5851         struct intel_crtc_state *crtc_state;
5852         int ret;
5853
5854         if (!intel_crtc->active)
5855                 return;
5856
5857         if (crtc->primary->state->visible) {
5858                 WARN_ON(intel_crtc->flip_work);
5859
5860                 intel_pre_disable_primary_noatomic(crtc);
5861
5862                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5863                 crtc->primary->state->visible = false;
5864         }
5865
5866         state = drm_atomic_state_alloc(crtc->dev);
5867         if (!state) {
5868                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5869                               crtc->base.id, crtc->name);
5870                 return;
5871         }
5872
5873         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5874
5875         /* Everything's already locked, -EDEADLK can't happen. */
5876         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5877         ret = drm_atomic_add_affected_connectors(state, crtc);
5878
5879         WARN_ON(IS_ERR(crtc_state) || ret);
5880
5881         dev_priv->display.crtc_disable(crtc_state, state);
5882
5883         drm_atomic_state_put(state);
5884
5885         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5886                       crtc->base.id, crtc->name);
5887
5888         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5889         crtc->state->active = false;
5890         intel_crtc->active = false;
5891         crtc->enabled = false;
5892         crtc->state->connector_mask = 0;
5893         crtc->state->encoder_mask = 0;
5894
5895         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5896                 encoder->base.crtc = NULL;
5897
5898         intel_fbc_disable(intel_crtc);
5899         intel_update_watermarks(intel_crtc);
5900         intel_disable_shared_dpll(intel_crtc);
5901
5902         domains = intel_crtc->enabled_power_domains;
5903         for_each_power_domain(domain, domains)
5904                 intel_display_power_put(dev_priv, domain);
5905         intel_crtc->enabled_power_domains = 0;
5906
5907         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5908         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5909 }
5910
5911 /*
5912  * turn all crtc's off, but do not adjust state
5913  * This has to be paired with a call to intel_modeset_setup_hw_state.
5914  */
5915 int intel_display_suspend(struct drm_device *dev)
5916 {
5917         struct drm_i915_private *dev_priv = to_i915(dev);
5918         struct drm_atomic_state *state;
5919         int ret;
5920
5921         state = drm_atomic_helper_suspend(dev);
5922         ret = PTR_ERR_OR_ZERO(state);
5923         if (ret)
5924                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5925         else
5926                 dev_priv->modeset_restore_state = state;
5927         return ret;
5928 }
5929
5930 void intel_encoder_destroy(struct drm_encoder *encoder)
5931 {
5932         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5933
5934         drm_encoder_cleanup(encoder);
5935         kfree(intel_encoder);
5936 }
5937
5938 /* Cross check the actual hw state with our own modeset state tracking (and it's
5939  * internal consistency). */
5940 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5941                                          struct drm_connector_state *conn_state)
5942 {
5943         struct intel_connector *connector = to_intel_connector(conn_state->connector);
5944
5945         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5946                       connector->base.base.id,
5947                       connector->base.name);
5948
5949         if (connector->get_hw_state(connector)) {
5950                 struct intel_encoder *encoder = connector->encoder;
5951
5952                 I915_STATE_WARN(!crtc_state,
5953                          "connector enabled without attached crtc\n");
5954
5955                 if (!crtc_state)
5956                         return;
5957
5958                 I915_STATE_WARN(!crtc_state->active,
5959                       "connector is active, but attached crtc isn't\n");
5960
5961                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5962                         return;
5963
5964                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5965                         "atomic encoder doesn't match attached encoder\n");
5966
5967                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5968                         "attached encoder crtc differs from connector crtc\n");
5969         } else {
5970                 I915_STATE_WARN(crtc_state && crtc_state->active,
5971                         "attached crtc is active, but connector isn't\n");
5972                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5973                         "best encoder set without crtc!\n");
5974         }
5975 }
5976
5977 int intel_connector_init(struct intel_connector *connector)
5978 {
5979         drm_atomic_helper_connector_reset(&connector->base);
5980
5981         if (!connector->base.state)
5982                 return -ENOMEM;
5983
5984         return 0;
5985 }
5986
5987 struct intel_connector *intel_connector_alloc(void)
5988 {
5989         struct intel_connector *connector;
5990
5991         connector = kzalloc(sizeof *connector, GFP_KERNEL);
5992         if (!connector)
5993                 return NULL;
5994
5995         if (intel_connector_init(connector) < 0) {
5996                 kfree(connector);
5997                 return NULL;
5998         }
5999
6000         return connector;
6001 }
6002
6003 /* Simple connector->get_hw_state implementation for encoders that support only
6004  * one connector and no cloning and hence the encoder state determines the state
6005  * of the connector. */
6006 bool intel_connector_get_hw_state(struct intel_connector *connector)
6007 {
6008         enum pipe pipe = 0;
6009         struct intel_encoder *encoder = connector->encoder;
6010
6011         return encoder->get_hw_state(encoder, &pipe);
6012 }
6013
6014 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6015 {
6016         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6017                 return crtc_state->fdi_lanes;
6018
6019         return 0;
6020 }
6021
6022 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6023                                      struct intel_crtc_state *pipe_config)
6024 {
6025         struct drm_i915_private *dev_priv = to_i915(dev);
6026         struct drm_atomic_state *state = pipe_config->base.state;
6027         struct intel_crtc *other_crtc;
6028         struct intel_crtc_state *other_crtc_state;
6029
6030         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6031                       pipe_name(pipe), pipe_config->fdi_lanes);
6032         if (pipe_config->fdi_lanes > 4) {
6033                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6034                               pipe_name(pipe), pipe_config->fdi_lanes);
6035                 return -EINVAL;
6036         }
6037
6038         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6039                 if (pipe_config->fdi_lanes > 2) {
6040                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6041                                       pipe_config->fdi_lanes);
6042                         return -EINVAL;
6043                 } else {
6044                         return 0;
6045                 }
6046         }
6047
6048         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6049                 return 0;
6050
6051         /* Ivybridge 3 pipe is really complicated */
6052         switch (pipe) {
6053         case PIPE_A:
6054                 return 0;
6055         case PIPE_B:
6056                 if (pipe_config->fdi_lanes <= 2)
6057                         return 0;
6058
6059                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6060                 other_crtc_state =
6061                         intel_atomic_get_crtc_state(state, other_crtc);
6062                 if (IS_ERR(other_crtc_state))
6063                         return PTR_ERR(other_crtc_state);
6064
6065                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6066                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6067                                       pipe_name(pipe), pipe_config->fdi_lanes);
6068                         return -EINVAL;
6069                 }
6070                 return 0;
6071         case PIPE_C:
6072                 if (pipe_config->fdi_lanes > 2) {
6073                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6074                                       pipe_name(pipe), pipe_config->fdi_lanes);
6075                         return -EINVAL;
6076                 }
6077
6078                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6079                 other_crtc_state =
6080                         intel_atomic_get_crtc_state(state, other_crtc);
6081                 if (IS_ERR(other_crtc_state))
6082                         return PTR_ERR(other_crtc_state);
6083
6084                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6085                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6086                         return -EINVAL;
6087                 }
6088                 return 0;
6089         default:
6090                 BUG();
6091         }
6092 }
6093
6094 #define RETRY 1
6095 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6096                                        struct intel_crtc_state *pipe_config)
6097 {
6098         struct drm_device *dev = intel_crtc->base.dev;
6099         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6100         int lane, link_bw, fdi_dotclock, ret;
6101         bool needs_recompute = false;
6102
6103 retry:
6104         /* FDI is a binary signal running at ~2.7GHz, encoding
6105          * each output octet as 10 bits. The actual frequency
6106          * is stored as a divider into a 100MHz clock, and the
6107          * mode pixel clock is stored in units of 1KHz.
6108          * Hence the bw of each lane in terms of the mode signal
6109          * is:
6110          */
6111         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6112
6113         fdi_dotclock = adjusted_mode->crtc_clock;
6114
6115         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6116                                            pipe_config->pipe_bpp);
6117
6118         pipe_config->fdi_lanes = lane;
6119
6120         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6121                                link_bw, &pipe_config->fdi_m_n, false);
6122
6123         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6124         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6125                 pipe_config->pipe_bpp -= 2*3;
6126                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6127                               pipe_config->pipe_bpp);
6128                 needs_recompute = true;
6129                 pipe_config->bw_constrained = true;
6130
6131                 goto retry;
6132         }
6133
6134         if (needs_recompute)
6135                 return RETRY;
6136
6137         return ret;
6138 }
6139
6140 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6141                                      struct intel_crtc_state *pipe_config)
6142 {
6143         if (pipe_config->pipe_bpp > 24)
6144                 return false;
6145
6146         /* HSW can handle pixel rate up to cdclk? */
6147         if (IS_HASWELL(dev_priv))
6148                 return true;
6149
6150         /*
6151          * We compare against max which means we must take
6152          * the increased cdclk requirement into account when
6153          * calculating the new cdclk.
6154          *
6155          * Should measure whether using a lower cdclk w/o IPS
6156          */
6157         return pipe_config->pixel_rate <=
6158                 dev_priv->max_cdclk_freq * 95 / 100;
6159 }
6160
6161 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6162                                    struct intel_crtc_state *pipe_config)
6163 {
6164         struct drm_device *dev = crtc->base.dev;
6165         struct drm_i915_private *dev_priv = to_i915(dev);
6166
6167         pipe_config->ips_enabled = i915.enable_ips &&
6168                 hsw_crtc_supports_ips(crtc) &&
6169                 pipe_config_supports_ips(dev_priv, pipe_config);
6170 }
6171
6172 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6173 {
6174         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6175
6176         /* GDG double wide on either pipe, otherwise pipe A only */
6177         return INTEL_INFO(dev_priv)->gen < 4 &&
6178                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6179 }
6180
6181 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6182 {
6183         uint32_t pixel_rate;
6184
6185         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6186
6187         /*
6188          * We only use IF-ID interlacing. If we ever use
6189          * PF-ID we'll need to adjust the pixel_rate here.
6190          */
6191
6192         if (pipe_config->pch_pfit.enabled) {
6193                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6194                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6195
6196                 pipe_w = pipe_config->pipe_src_w;
6197                 pipe_h = pipe_config->pipe_src_h;
6198
6199                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6200                 pfit_h = pfit_size & 0xFFFF;
6201                 if (pipe_w < pfit_w)
6202                         pipe_w = pfit_w;
6203                 if (pipe_h < pfit_h)
6204                         pipe_h = pfit_h;
6205
6206                 if (WARN_ON(!pfit_w || !pfit_h))
6207                         return pixel_rate;
6208
6209                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6210                                      pfit_w * pfit_h);
6211         }
6212
6213         return pixel_rate;
6214 }
6215
6216 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6217 {
6218         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6219
6220         if (HAS_GMCH_DISPLAY(dev_priv))
6221                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6222                 crtc_state->pixel_rate =
6223                         crtc_state->base.adjusted_mode.crtc_clock;
6224         else
6225                 crtc_state->pixel_rate =
6226                         ilk_pipe_pixel_rate(crtc_state);
6227 }
6228
6229 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6230                                      struct intel_crtc_state *pipe_config)
6231 {
6232         struct drm_device *dev = crtc->base.dev;
6233         struct drm_i915_private *dev_priv = to_i915(dev);
6234         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6235         int clock_limit = dev_priv->max_dotclk_freq;
6236
6237         if (INTEL_GEN(dev_priv) < 4) {
6238                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6239
6240                 /*
6241                  * Enable double wide mode when the dot clock
6242                  * is > 90% of the (display) core speed.
6243                  */
6244                 if (intel_crtc_supports_double_wide(crtc) &&
6245                     adjusted_mode->crtc_clock > clock_limit) {
6246                         clock_limit = dev_priv->max_dotclk_freq;
6247                         pipe_config->double_wide = true;
6248                 }
6249         }
6250
6251         if (adjusted_mode->crtc_clock > clock_limit) {
6252                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6253                               adjusted_mode->crtc_clock, clock_limit,
6254                               yesno(pipe_config->double_wide));
6255                 return -EINVAL;
6256         }
6257
6258         /*
6259          * Pipe horizontal size must be even in:
6260          * - DVO ganged mode
6261          * - LVDS dual channel mode
6262          * - Double wide pipe
6263          */
6264         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6265              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6266                 pipe_config->pipe_src_w &= ~1;
6267
6268         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6269          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6270          */
6271         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6272                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6273                 return -EINVAL;
6274
6275         intel_crtc_compute_pixel_rate(pipe_config);
6276
6277         if (HAS_IPS(dev_priv))
6278                 hsw_compute_ips_config(crtc, pipe_config);
6279
6280         if (pipe_config->has_pch_encoder)
6281                 return ironlake_fdi_compute_config(crtc, pipe_config);
6282
6283         return 0;
6284 }
6285
6286 static void
6287 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6288 {
6289         while (*num > DATA_LINK_M_N_MASK ||
6290                *den > DATA_LINK_M_N_MASK) {
6291                 *num >>= 1;
6292                 *den >>= 1;
6293         }
6294 }
6295
6296 static void compute_m_n(unsigned int m, unsigned int n,
6297                         uint32_t *ret_m, uint32_t *ret_n,
6298                         bool reduce_m_n)
6299 {
6300         /*
6301          * Reduce M/N as much as possible without loss in precision. Several DP
6302          * dongles in particular seem to be fussy about too large *link* M/N
6303          * values. The passed in values are more likely to have the least
6304          * significant bits zero than M after rounding below, so do this first.
6305          */
6306         if (reduce_m_n) {
6307                 while ((m & 1) == 0 && (n & 1) == 0) {
6308                         m >>= 1;
6309                         n >>= 1;
6310                 }
6311         }
6312
6313         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6314         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6315         intel_reduce_m_n_ratio(ret_m, ret_n);
6316 }
6317
6318 void
6319 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6320                        int pixel_clock, int link_clock,
6321                        struct intel_link_m_n *m_n,
6322                        bool reduce_m_n)
6323 {
6324         m_n->tu = 64;
6325
6326         compute_m_n(bits_per_pixel * pixel_clock,
6327                     link_clock * nlanes * 8,
6328                     &m_n->gmch_m, &m_n->gmch_n,
6329                     reduce_m_n);
6330
6331         compute_m_n(pixel_clock, link_clock,
6332                     &m_n->link_m, &m_n->link_n,
6333                     reduce_m_n);
6334 }
6335
6336 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6337 {
6338         if (i915.panel_use_ssc >= 0)
6339                 return i915.panel_use_ssc != 0;
6340         return dev_priv->vbt.lvds_use_ssc
6341                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6342 }
6343
6344 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6345 {
6346         return (1 << dpll->n) << 16 | dpll->m2;
6347 }
6348
6349 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6350 {
6351         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6352 }
6353
6354 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6355                                      struct intel_crtc_state *crtc_state,
6356                                      struct dpll *reduced_clock)
6357 {
6358         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6359         u32 fp, fp2 = 0;
6360
6361         if (IS_PINEVIEW(dev_priv)) {
6362                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6363                 if (reduced_clock)
6364                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6365         } else {
6366                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6367                 if (reduced_clock)
6368                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6369         }
6370
6371         crtc_state->dpll_hw_state.fp0 = fp;
6372
6373         crtc->lowfreq_avail = false;
6374         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6375             reduced_clock) {
6376                 crtc_state->dpll_hw_state.fp1 = fp2;
6377                 crtc->lowfreq_avail = true;
6378         } else {
6379                 crtc_state->dpll_hw_state.fp1 = fp;
6380         }
6381 }
6382
6383 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6384                 pipe)
6385 {
6386         u32 reg_val;
6387
6388         /*
6389          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6390          * and set it to a reasonable value instead.
6391          */
6392         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6393         reg_val &= 0xffffff00;
6394         reg_val |= 0x00000030;
6395         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6396
6397         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6398         reg_val &= 0x00ffffff;
6399         reg_val |= 0x8c000000;
6400         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6401
6402         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6403         reg_val &= 0xffffff00;
6404         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6405
6406         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6407         reg_val &= 0x00ffffff;
6408         reg_val |= 0xb0000000;
6409         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6410 }
6411
6412 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6413                                          struct intel_link_m_n *m_n)
6414 {
6415         struct drm_device *dev = crtc->base.dev;
6416         struct drm_i915_private *dev_priv = to_i915(dev);
6417         int pipe = crtc->pipe;
6418
6419         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6420         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6421         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6422         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6423 }
6424
6425 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6426                                          struct intel_link_m_n *m_n,
6427                                          struct intel_link_m_n *m2_n2)
6428 {
6429         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6430         int pipe = crtc->pipe;
6431         enum transcoder transcoder = crtc->config->cpu_transcoder;
6432
6433         if (INTEL_GEN(dev_priv) >= 5) {
6434                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6435                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6436                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6437                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6438                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6439                  * for gen < 8) and if DRRS is supported (to make sure the
6440                  * registers are not unnecessarily accessed).
6441                  */
6442                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6443                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6444                         I915_WRITE(PIPE_DATA_M2(transcoder),
6445                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6446                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6447                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6448                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6449                 }
6450         } else {
6451                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6452                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6453                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6454                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6455         }
6456 }
6457
6458 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6459 {
6460         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6461
6462         if (m_n == M1_N1) {
6463                 dp_m_n = &crtc->config->dp_m_n;
6464                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6465         } else if (m_n == M2_N2) {
6466
6467                 /*
6468                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6469                  * needs to be programmed into M1_N1.
6470                  */
6471                 dp_m_n = &crtc->config->dp_m2_n2;
6472         } else {
6473                 DRM_ERROR("Unsupported divider value\n");
6474                 return;
6475         }
6476
6477         if (crtc->config->has_pch_encoder)
6478                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6479         else
6480                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6481 }
6482
6483 static void vlv_compute_dpll(struct intel_crtc *crtc,
6484                              struct intel_crtc_state *pipe_config)
6485 {
6486         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6487                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6488         if (crtc->pipe != PIPE_A)
6489                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6490
6491         /* DPLL not used with DSI, but still need the rest set up */
6492         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6493                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6494                         DPLL_EXT_BUFFER_ENABLE_VLV;
6495
6496         pipe_config->dpll_hw_state.dpll_md =
6497                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6498 }
6499
6500 static void chv_compute_dpll(struct intel_crtc *crtc,
6501                              struct intel_crtc_state *pipe_config)
6502 {
6503         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6504                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6505         if (crtc->pipe != PIPE_A)
6506                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6507
6508         /* DPLL not used with DSI, but still need the rest set up */
6509         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6510                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6511
6512         pipe_config->dpll_hw_state.dpll_md =
6513                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6514 }
6515
6516 static void vlv_prepare_pll(struct intel_crtc *crtc,
6517                             const struct intel_crtc_state *pipe_config)
6518 {
6519         struct drm_device *dev = crtc->base.dev;
6520         struct drm_i915_private *dev_priv = to_i915(dev);
6521         enum pipe pipe = crtc->pipe;
6522         u32 mdiv;
6523         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6524         u32 coreclk, reg_val;
6525
6526         /* Enable Refclk */
6527         I915_WRITE(DPLL(pipe),
6528                    pipe_config->dpll_hw_state.dpll &
6529                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6530
6531         /* No need to actually set up the DPLL with DSI */
6532         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6533                 return;
6534
6535         mutex_lock(&dev_priv->sb_lock);
6536
6537         bestn = pipe_config->dpll.n;
6538         bestm1 = pipe_config->dpll.m1;
6539         bestm2 = pipe_config->dpll.m2;
6540         bestp1 = pipe_config->dpll.p1;
6541         bestp2 = pipe_config->dpll.p2;
6542
6543         /* See eDP HDMI DPIO driver vbios notes doc */
6544
6545         /* PLL B needs special handling */
6546         if (pipe == PIPE_B)
6547                 vlv_pllb_recal_opamp(dev_priv, pipe);
6548
6549         /* Set up Tx target for periodic Rcomp update */
6550         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6551
6552         /* Disable target IRef on PLL */
6553         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6554         reg_val &= 0x00ffffff;
6555         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6556
6557         /* Disable fast lock */
6558         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6559
6560         /* Set idtafcrecal before PLL is enabled */
6561         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6562         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6563         mdiv |= ((bestn << DPIO_N_SHIFT));
6564         mdiv |= (1 << DPIO_K_SHIFT);
6565
6566         /*
6567          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6568          * but we don't support that).
6569          * Note: don't use the DAC post divider as it seems unstable.
6570          */
6571         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6572         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6573
6574         mdiv |= DPIO_ENABLE_CALIBRATION;
6575         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6576
6577         /* Set HBR and RBR LPF coefficients */
6578         if (pipe_config->port_clock == 162000 ||
6579             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6580             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6581                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6582                                  0x009f0003);
6583         else
6584                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6585                                  0x00d0000f);
6586
6587         if (intel_crtc_has_dp_encoder(pipe_config)) {
6588                 /* Use SSC source */
6589                 if (pipe == PIPE_A)
6590                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6591                                          0x0df40000);
6592                 else
6593                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6594                                          0x0df70000);
6595         } else { /* HDMI or VGA */
6596                 /* Use bend source */
6597                 if (pipe == PIPE_A)
6598                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6599                                          0x0df70000);
6600                 else
6601                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6602                                          0x0df40000);
6603         }
6604
6605         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6606         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6607         if (intel_crtc_has_dp_encoder(crtc->config))
6608                 coreclk |= 0x01000000;
6609         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6610
6611         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6612         mutex_unlock(&dev_priv->sb_lock);
6613 }
6614
6615 static void chv_prepare_pll(struct intel_crtc *crtc,
6616                             const struct intel_crtc_state *pipe_config)
6617 {
6618         struct drm_device *dev = crtc->base.dev;
6619         struct drm_i915_private *dev_priv = to_i915(dev);
6620         enum pipe pipe = crtc->pipe;
6621         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6622         u32 loopfilter, tribuf_calcntr;
6623         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6624         u32 dpio_val;
6625         int vco;
6626
6627         /* Enable Refclk and SSC */
6628         I915_WRITE(DPLL(pipe),
6629                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6630
6631         /* No need to actually set up the DPLL with DSI */
6632         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6633                 return;
6634
6635         bestn = pipe_config->dpll.n;
6636         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6637         bestm1 = pipe_config->dpll.m1;
6638         bestm2 = pipe_config->dpll.m2 >> 22;
6639         bestp1 = pipe_config->dpll.p1;
6640         bestp2 = pipe_config->dpll.p2;
6641         vco = pipe_config->dpll.vco;
6642         dpio_val = 0;
6643         loopfilter = 0;
6644
6645         mutex_lock(&dev_priv->sb_lock);
6646
6647         /* p1 and p2 divider */
6648         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6649                         5 << DPIO_CHV_S1_DIV_SHIFT |
6650                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6651                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6652                         1 << DPIO_CHV_K_DIV_SHIFT);
6653
6654         /* Feedback post-divider - m2 */
6655         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6656
6657         /* Feedback refclk divider - n and m1 */
6658         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6659                         DPIO_CHV_M1_DIV_BY_2 |
6660                         1 << DPIO_CHV_N_DIV_SHIFT);
6661
6662         /* M2 fraction division */
6663         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6664
6665         /* M2 fraction division enable */
6666         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6667         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6668         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6669         if (bestm2_frac)
6670                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6671         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6672
6673         /* Program digital lock detect threshold */
6674         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6675         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6676                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6677         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6678         if (!bestm2_frac)
6679                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6680         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6681
6682         /* Loop filter */
6683         if (vco == 5400000) {
6684                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6685                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6686                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6687                 tribuf_calcntr = 0x9;
6688         } else if (vco <= 6200000) {
6689                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6690                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6691                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6692                 tribuf_calcntr = 0x9;
6693         } else if (vco <= 6480000) {
6694                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6695                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6696                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6697                 tribuf_calcntr = 0x8;
6698         } else {
6699                 /* Not supported. Apply the same limits as in the max case */
6700                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6701                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6702                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6703                 tribuf_calcntr = 0;
6704         }
6705         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6706
6707         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6708         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6709         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6710         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6711
6712         /* AFC Recal */
6713         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6714                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6715                         DPIO_AFC_RECAL);
6716
6717         mutex_unlock(&dev_priv->sb_lock);
6718 }
6719
6720 /**
6721  * vlv_force_pll_on - forcibly enable just the PLL
6722  * @dev_priv: i915 private structure
6723  * @pipe: pipe PLL to enable
6724  * @dpll: PLL configuration
6725  *
6726  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6727  * in cases where we need the PLL enabled even when @pipe is not going to
6728  * be enabled.
6729  */
6730 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6731                      const struct dpll *dpll)
6732 {
6733         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6734         struct intel_crtc_state *pipe_config;
6735
6736         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6737         if (!pipe_config)
6738                 return -ENOMEM;
6739
6740         pipe_config->base.crtc = &crtc->base;
6741         pipe_config->pixel_multiplier = 1;
6742         pipe_config->dpll = *dpll;
6743
6744         if (IS_CHERRYVIEW(dev_priv)) {
6745                 chv_compute_dpll(crtc, pipe_config);
6746                 chv_prepare_pll(crtc, pipe_config);
6747                 chv_enable_pll(crtc, pipe_config);
6748         } else {
6749                 vlv_compute_dpll(crtc, pipe_config);
6750                 vlv_prepare_pll(crtc, pipe_config);
6751                 vlv_enable_pll(crtc, pipe_config);
6752         }
6753
6754         kfree(pipe_config);
6755
6756         return 0;
6757 }
6758
6759 /**
6760  * vlv_force_pll_off - forcibly disable just the PLL
6761  * @dev_priv: i915 private structure
6762  * @pipe: pipe PLL to disable
6763  *
6764  * Disable the PLL for @pipe. To be used in cases where we need
6765  * the PLL enabled even when @pipe is not going to be enabled.
6766  */
6767 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6768 {
6769         if (IS_CHERRYVIEW(dev_priv))
6770                 chv_disable_pll(dev_priv, pipe);
6771         else
6772                 vlv_disable_pll(dev_priv, pipe);
6773 }
6774
6775 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6776                               struct intel_crtc_state *crtc_state,
6777                               struct dpll *reduced_clock)
6778 {
6779         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6780         u32 dpll;
6781         struct dpll *clock = &crtc_state->dpll;
6782
6783         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6784
6785         dpll = DPLL_VGA_MODE_DIS;
6786
6787         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6788                 dpll |= DPLLB_MODE_LVDS;
6789         else
6790                 dpll |= DPLLB_MODE_DAC_SERIAL;
6791
6792         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6793             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6794                 dpll |= (crtc_state->pixel_multiplier - 1)
6795                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6796         }
6797
6798         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6799             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6800                 dpll |= DPLL_SDVO_HIGH_SPEED;
6801
6802         if (intel_crtc_has_dp_encoder(crtc_state))
6803                 dpll |= DPLL_SDVO_HIGH_SPEED;
6804
6805         /* compute bitmask from p1 value */
6806         if (IS_PINEVIEW(dev_priv))
6807                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6808         else {
6809                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6810                 if (IS_G4X(dev_priv) && reduced_clock)
6811                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6812         }
6813         switch (clock->p2) {
6814         case 5:
6815                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6816                 break;
6817         case 7:
6818                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6819                 break;
6820         case 10:
6821                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6822                 break;
6823         case 14:
6824                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6825                 break;
6826         }
6827         if (INTEL_GEN(dev_priv) >= 4)
6828                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6829
6830         if (crtc_state->sdvo_tv_clock)
6831                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6832         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6833                  intel_panel_use_ssc(dev_priv))
6834                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6835         else
6836                 dpll |= PLL_REF_INPUT_DREFCLK;
6837
6838         dpll |= DPLL_VCO_ENABLE;
6839         crtc_state->dpll_hw_state.dpll = dpll;
6840
6841         if (INTEL_GEN(dev_priv) >= 4) {
6842                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6843                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6844                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6845         }
6846 }
6847
6848 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6849                               struct intel_crtc_state *crtc_state,
6850                               struct dpll *reduced_clock)
6851 {
6852         struct drm_device *dev = crtc->base.dev;
6853         struct drm_i915_private *dev_priv = to_i915(dev);
6854         u32 dpll;
6855         struct dpll *clock = &crtc_state->dpll;
6856
6857         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6858
6859         dpll = DPLL_VGA_MODE_DIS;
6860
6861         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6862                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6863         } else {
6864                 if (clock->p1 == 2)
6865                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6866                 else
6867                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6868                 if (clock->p2 == 4)
6869                         dpll |= PLL_P2_DIVIDE_BY_4;
6870         }
6871
6872         if (!IS_I830(dev_priv) &&
6873             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6874                 dpll |= DPLL_DVO_2X_MODE;
6875
6876         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6877             intel_panel_use_ssc(dev_priv))
6878                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6879         else
6880                 dpll |= PLL_REF_INPUT_DREFCLK;
6881
6882         dpll |= DPLL_VCO_ENABLE;
6883         crtc_state->dpll_hw_state.dpll = dpll;
6884 }
6885
6886 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6887 {
6888         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6889         enum pipe pipe = intel_crtc->pipe;
6890         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6891         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6892         uint32_t crtc_vtotal, crtc_vblank_end;
6893         int vsyncshift = 0;
6894
6895         /* We need to be careful not to changed the adjusted mode, for otherwise
6896          * the hw state checker will get angry at the mismatch. */
6897         crtc_vtotal = adjusted_mode->crtc_vtotal;
6898         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6899
6900         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6901                 /* the chip adds 2 halflines automatically */
6902                 crtc_vtotal -= 1;
6903                 crtc_vblank_end -= 1;
6904
6905                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6906                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6907                 else
6908                         vsyncshift = adjusted_mode->crtc_hsync_start -
6909                                 adjusted_mode->crtc_htotal / 2;
6910                 if (vsyncshift < 0)
6911                         vsyncshift += adjusted_mode->crtc_htotal;
6912         }
6913
6914         if (INTEL_GEN(dev_priv) > 3)
6915                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6916
6917         I915_WRITE(HTOTAL(cpu_transcoder),
6918                    (adjusted_mode->crtc_hdisplay - 1) |
6919                    ((adjusted_mode->crtc_htotal - 1) << 16));
6920         I915_WRITE(HBLANK(cpu_transcoder),
6921                    (adjusted_mode->crtc_hblank_start - 1) |
6922                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6923         I915_WRITE(HSYNC(cpu_transcoder),
6924                    (adjusted_mode->crtc_hsync_start - 1) |
6925                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6926
6927         I915_WRITE(VTOTAL(cpu_transcoder),
6928                    (adjusted_mode->crtc_vdisplay - 1) |
6929                    ((crtc_vtotal - 1) << 16));
6930         I915_WRITE(VBLANK(cpu_transcoder),
6931                    (adjusted_mode->crtc_vblank_start - 1) |
6932                    ((crtc_vblank_end - 1) << 16));
6933         I915_WRITE(VSYNC(cpu_transcoder),
6934                    (adjusted_mode->crtc_vsync_start - 1) |
6935                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6936
6937         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6938          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6939          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6940          * bits. */
6941         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6942             (pipe == PIPE_B || pipe == PIPE_C))
6943                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6944
6945 }
6946
6947 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6948 {
6949         struct drm_device *dev = intel_crtc->base.dev;
6950         struct drm_i915_private *dev_priv = to_i915(dev);
6951         enum pipe pipe = intel_crtc->pipe;
6952
6953         /* pipesrc controls the size that is scaled from, which should
6954          * always be the user's requested size.
6955          */
6956         I915_WRITE(PIPESRC(pipe),
6957                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6958                    (intel_crtc->config->pipe_src_h - 1));
6959 }
6960
6961 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6962                                    struct intel_crtc_state *pipe_config)
6963 {
6964         struct drm_device *dev = crtc->base.dev;
6965         struct drm_i915_private *dev_priv = to_i915(dev);
6966         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6967         uint32_t tmp;
6968
6969         tmp = I915_READ(HTOTAL(cpu_transcoder));
6970         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6971         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6972         tmp = I915_READ(HBLANK(cpu_transcoder));
6973         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6974         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6975         tmp = I915_READ(HSYNC(cpu_transcoder));
6976         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6977         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6978
6979         tmp = I915_READ(VTOTAL(cpu_transcoder));
6980         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6981         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6982         tmp = I915_READ(VBLANK(cpu_transcoder));
6983         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6984         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6985         tmp = I915_READ(VSYNC(cpu_transcoder));
6986         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6987         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6988
6989         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6990                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6991                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6992                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6993         }
6994 }
6995
6996 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6997                                     struct intel_crtc_state *pipe_config)
6998 {
6999         struct drm_device *dev = crtc->base.dev;
7000         struct drm_i915_private *dev_priv = to_i915(dev);
7001         u32 tmp;
7002
7003         tmp = I915_READ(PIPESRC(crtc->pipe));
7004         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7005         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7006
7007         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7008         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7009 }
7010
7011 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7012                                  struct intel_crtc_state *pipe_config)
7013 {
7014         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7015         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7016         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7017         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7018
7019         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7020         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7021         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7022         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7023
7024         mode->flags = pipe_config->base.adjusted_mode.flags;
7025         mode->type = DRM_MODE_TYPE_DRIVER;
7026
7027         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7028
7029         mode->hsync = drm_mode_hsync(mode);
7030         mode->vrefresh = drm_mode_vrefresh(mode);
7031         drm_mode_set_name(mode);
7032 }
7033
7034 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7035 {
7036         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7037         uint32_t pipeconf;
7038
7039         pipeconf = 0;
7040
7041         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7042             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7043                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7044
7045         if (intel_crtc->config->double_wide)
7046                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7047
7048         /* only g4x and later have fancy bpc/dither controls */
7049         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7050             IS_CHERRYVIEW(dev_priv)) {
7051                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7052                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7053                         pipeconf |= PIPECONF_DITHER_EN |
7054                                     PIPECONF_DITHER_TYPE_SP;
7055
7056                 switch (intel_crtc->config->pipe_bpp) {
7057                 case 18:
7058                         pipeconf |= PIPECONF_6BPC;
7059                         break;
7060                 case 24:
7061                         pipeconf |= PIPECONF_8BPC;
7062                         break;
7063                 case 30:
7064                         pipeconf |= PIPECONF_10BPC;
7065                         break;
7066                 default:
7067                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7068                         BUG();
7069                 }
7070         }
7071
7072         if (HAS_PIPE_CXSR(dev_priv)) {
7073                 if (intel_crtc->lowfreq_avail) {
7074                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7075                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7076                 } else {
7077                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7078                 }
7079         }
7080
7081         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7082                 if (INTEL_GEN(dev_priv) < 4 ||
7083                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7084                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7085                 else
7086                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7087         } else
7088                 pipeconf |= PIPECONF_PROGRESSIVE;
7089
7090         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7091              intel_crtc->config->limited_color_range)
7092                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7093
7094         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7095         POSTING_READ(PIPECONF(intel_crtc->pipe));
7096 }
7097
7098 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7099                                    struct intel_crtc_state *crtc_state)
7100 {
7101         struct drm_device *dev = crtc->base.dev;
7102         struct drm_i915_private *dev_priv = to_i915(dev);
7103         const struct intel_limit *limit;
7104         int refclk = 48000;
7105
7106         memset(&crtc_state->dpll_hw_state, 0,
7107                sizeof(crtc_state->dpll_hw_state));
7108
7109         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7110                 if (intel_panel_use_ssc(dev_priv)) {
7111                         refclk = dev_priv->vbt.lvds_ssc_freq;
7112                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7113                 }
7114
7115                 limit = &intel_limits_i8xx_lvds;
7116         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7117                 limit = &intel_limits_i8xx_dvo;
7118         } else {
7119                 limit = &intel_limits_i8xx_dac;
7120         }
7121
7122         if (!crtc_state->clock_set &&
7123             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7124                                  refclk, NULL, &crtc_state->dpll)) {
7125                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7126                 return -EINVAL;
7127         }
7128
7129         i8xx_compute_dpll(crtc, crtc_state, NULL);
7130
7131         return 0;
7132 }
7133
7134 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7135                                   struct intel_crtc_state *crtc_state)
7136 {
7137         struct drm_device *dev = crtc->base.dev;
7138         struct drm_i915_private *dev_priv = to_i915(dev);
7139         const struct intel_limit *limit;
7140         int refclk = 96000;
7141
7142         memset(&crtc_state->dpll_hw_state, 0,
7143                sizeof(crtc_state->dpll_hw_state));
7144
7145         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7146                 if (intel_panel_use_ssc(dev_priv)) {
7147                         refclk = dev_priv->vbt.lvds_ssc_freq;
7148                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7149                 }
7150
7151                 if (intel_is_dual_link_lvds(dev))
7152                         limit = &intel_limits_g4x_dual_channel_lvds;
7153                 else
7154                         limit = &intel_limits_g4x_single_channel_lvds;
7155         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7156                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7157                 limit = &intel_limits_g4x_hdmi;
7158         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7159                 limit = &intel_limits_g4x_sdvo;
7160         } else {
7161                 /* The option is for other outputs */
7162                 limit = &intel_limits_i9xx_sdvo;
7163         }
7164
7165         if (!crtc_state->clock_set &&
7166             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7167                                 refclk, NULL, &crtc_state->dpll)) {
7168                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7169                 return -EINVAL;
7170         }
7171
7172         i9xx_compute_dpll(crtc, crtc_state, NULL);
7173
7174         return 0;
7175 }
7176
7177 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7178                                   struct intel_crtc_state *crtc_state)
7179 {
7180         struct drm_device *dev = crtc->base.dev;
7181         struct drm_i915_private *dev_priv = to_i915(dev);
7182         const struct intel_limit *limit;
7183         int refclk = 96000;
7184
7185         memset(&crtc_state->dpll_hw_state, 0,
7186                sizeof(crtc_state->dpll_hw_state));
7187
7188         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7189                 if (intel_panel_use_ssc(dev_priv)) {
7190                         refclk = dev_priv->vbt.lvds_ssc_freq;
7191                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7192                 }
7193
7194                 limit = &intel_limits_pineview_lvds;
7195         } else {
7196                 limit = &intel_limits_pineview_sdvo;
7197         }
7198
7199         if (!crtc_state->clock_set &&
7200             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7201                                 refclk, NULL, &crtc_state->dpll)) {
7202                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7203                 return -EINVAL;
7204         }
7205
7206         i9xx_compute_dpll(crtc, crtc_state, NULL);
7207
7208         return 0;
7209 }
7210
7211 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7212                                    struct intel_crtc_state *crtc_state)
7213 {
7214         struct drm_device *dev = crtc->base.dev;
7215         struct drm_i915_private *dev_priv = to_i915(dev);
7216         const struct intel_limit *limit;
7217         int refclk = 96000;
7218
7219         memset(&crtc_state->dpll_hw_state, 0,
7220                sizeof(crtc_state->dpll_hw_state));
7221
7222         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7223                 if (intel_panel_use_ssc(dev_priv)) {
7224                         refclk = dev_priv->vbt.lvds_ssc_freq;
7225                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7226                 }
7227
7228                 limit = &intel_limits_i9xx_lvds;
7229         } else {
7230                 limit = &intel_limits_i9xx_sdvo;
7231         }
7232
7233         if (!crtc_state->clock_set &&
7234             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7235                                  refclk, NULL, &crtc_state->dpll)) {
7236                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7237                 return -EINVAL;
7238         }
7239
7240         i9xx_compute_dpll(crtc, crtc_state, NULL);
7241
7242         return 0;
7243 }
7244
7245 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7246                                   struct intel_crtc_state *crtc_state)
7247 {
7248         int refclk = 100000;
7249         const struct intel_limit *limit = &intel_limits_chv;
7250
7251         memset(&crtc_state->dpll_hw_state, 0,
7252                sizeof(crtc_state->dpll_hw_state));
7253
7254         if (!crtc_state->clock_set &&
7255             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7256                                 refclk, NULL, &crtc_state->dpll)) {
7257                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7258                 return -EINVAL;
7259         }
7260
7261         chv_compute_dpll(crtc, crtc_state);
7262
7263         return 0;
7264 }
7265
7266 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7267                                   struct intel_crtc_state *crtc_state)
7268 {
7269         int refclk = 100000;
7270         const struct intel_limit *limit = &intel_limits_vlv;
7271
7272         memset(&crtc_state->dpll_hw_state, 0,
7273                sizeof(crtc_state->dpll_hw_state));
7274
7275         if (!crtc_state->clock_set &&
7276             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7277                                 refclk, NULL, &crtc_state->dpll)) {
7278                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7279                 return -EINVAL;
7280         }
7281
7282         vlv_compute_dpll(crtc, crtc_state);
7283
7284         return 0;
7285 }
7286
7287 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7288                                  struct intel_crtc_state *pipe_config)
7289 {
7290         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7291         uint32_t tmp;
7292
7293         if (INTEL_GEN(dev_priv) <= 3 &&
7294             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7295                 return;
7296
7297         tmp = I915_READ(PFIT_CONTROL);
7298         if (!(tmp & PFIT_ENABLE))
7299                 return;
7300
7301         /* Check whether the pfit is attached to our pipe. */
7302         if (INTEL_GEN(dev_priv) < 4) {
7303                 if (crtc->pipe != PIPE_B)
7304                         return;
7305         } else {
7306                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7307                         return;
7308         }
7309
7310         pipe_config->gmch_pfit.control = tmp;
7311         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7312 }
7313
7314 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7315                                struct intel_crtc_state *pipe_config)
7316 {
7317         struct drm_device *dev = crtc->base.dev;
7318         struct drm_i915_private *dev_priv = to_i915(dev);
7319         int pipe = pipe_config->cpu_transcoder;
7320         struct dpll clock;
7321         u32 mdiv;
7322         int refclk = 100000;
7323
7324         /* In case of DSI, DPLL will not be used */
7325         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7326                 return;
7327
7328         mutex_lock(&dev_priv->sb_lock);
7329         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7330         mutex_unlock(&dev_priv->sb_lock);
7331
7332         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7333         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7334         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7335         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7336         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7337
7338         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7339 }
7340
7341 static void
7342 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7343                               struct intel_initial_plane_config *plane_config)
7344 {
7345         struct drm_device *dev = crtc->base.dev;
7346         struct drm_i915_private *dev_priv = to_i915(dev);
7347         u32 val, base, offset;
7348         int pipe = crtc->pipe, plane = crtc->plane;
7349         int fourcc, pixel_format;
7350         unsigned int aligned_height;
7351         struct drm_framebuffer *fb;
7352         struct intel_framebuffer *intel_fb;
7353
7354         val = I915_READ(DSPCNTR(plane));
7355         if (!(val & DISPLAY_PLANE_ENABLE))
7356                 return;
7357
7358         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7359         if (!intel_fb) {
7360                 DRM_DEBUG_KMS("failed to alloc fb\n");
7361                 return;
7362         }
7363
7364         fb = &intel_fb->base;
7365
7366         fb->dev = dev;
7367
7368         if (INTEL_GEN(dev_priv) >= 4) {
7369                 if (val & DISPPLANE_TILED) {
7370                         plane_config->tiling = I915_TILING_X;
7371                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7372                 }
7373         }
7374
7375         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7376         fourcc = i9xx_format_to_fourcc(pixel_format);
7377         fb->format = drm_format_info(fourcc);
7378
7379         if (INTEL_GEN(dev_priv) >= 4) {
7380                 if (plane_config->tiling)
7381                         offset = I915_READ(DSPTILEOFF(plane));
7382                 else
7383                         offset = I915_READ(DSPLINOFF(plane));
7384                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7385         } else {
7386                 base = I915_READ(DSPADDR(plane));
7387         }
7388         plane_config->base = base;
7389
7390         val = I915_READ(PIPESRC(pipe));
7391         fb->width = ((val >> 16) & 0xfff) + 1;
7392         fb->height = ((val >> 0) & 0xfff) + 1;
7393
7394         val = I915_READ(DSPSTRIDE(pipe));
7395         fb->pitches[0] = val & 0xffffffc0;
7396
7397         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7398
7399         plane_config->size = fb->pitches[0] * aligned_height;
7400
7401         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7402                       pipe_name(pipe), plane, fb->width, fb->height,
7403                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7404                       plane_config->size);
7405
7406         plane_config->fb = intel_fb;
7407 }
7408
7409 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7410                                struct intel_crtc_state *pipe_config)
7411 {
7412         struct drm_device *dev = crtc->base.dev;
7413         struct drm_i915_private *dev_priv = to_i915(dev);
7414         int pipe = pipe_config->cpu_transcoder;
7415         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7416         struct dpll clock;
7417         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7418         int refclk = 100000;
7419
7420         /* In case of DSI, DPLL will not be used */
7421         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7422                 return;
7423
7424         mutex_lock(&dev_priv->sb_lock);
7425         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7426         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7427         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7428         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7429         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7430         mutex_unlock(&dev_priv->sb_lock);
7431
7432         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7433         clock.m2 = (pll_dw0 & 0xff) << 22;
7434         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7435                 clock.m2 |= pll_dw2 & 0x3fffff;
7436         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7437         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7438         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7439
7440         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7441 }
7442
7443 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7444                                  struct intel_crtc_state *pipe_config)
7445 {
7446         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7447         enum intel_display_power_domain power_domain;
7448         uint32_t tmp;
7449         bool ret;
7450
7451         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7452         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7453                 return false;
7454
7455         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7456         pipe_config->shared_dpll = NULL;
7457
7458         ret = false;
7459
7460         tmp = I915_READ(PIPECONF(crtc->pipe));
7461         if (!(tmp & PIPECONF_ENABLE))
7462                 goto out;
7463
7464         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7465             IS_CHERRYVIEW(dev_priv)) {
7466                 switch (tmp & PIPECONF_BPC_MASK) {
7467                 case PIPECONF_6BPC:
7468                         pipe_config->pipe_bpp = 18;
7469                         break;
7470                 case PIPECONF_8BPC:
7471                         pipe_config->pipe_bpp = 24;
7472                         break;
7473                 case PIPECONF_10BPC:
7474                         pipe_config->pipe_bpp = 30;
7475                         break;
7476                 default:
7477                         break;
7478                 }
7479         }
7480
7481         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7482             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7483                 pipe_config->limited_color_range = true;
7484
7485         if (INTEL_GEN(dev_priv) < 4)
7486                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7487
7488         intel_get_pipe_timings(crtc, pipe_config);
7489         intel_get_pipe_src_size(crtc, pipe_config);
7490
7491         i9xx_get_pfit_config(crtc, pipe_config);
7492
7493         if (INTEL_GEN(dev_priv) >= 4) {
7494                 /* No way to read it out on pipes B and C */
7495                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7496                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7497                 else
7498                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7499                 pipe_config->pixel_multiplier =
7500                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7501                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7502                 pipe_config->dpll_hw_state.dpll_md = tmp;
7503         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7504                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7505                 tmp = I915_READ(DPLL(crtc->pipe));
7506                 pipe_config->pixel_multiplier =
7507                         ((tmp & SDVO_MULTIPLIER_MASK)
7508                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7509         } else {
7510                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7511                  * port and will be fixed up in the encoder->get_config
7512                  * function. */
7513                 pipe_config->pixel_multiplier = 1;
7514         }
7515         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7516         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7517                 /*
7518                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7519                  * on 830. Filter it out here so that we don't
7520                  * report errors due to that.
7521                  */
7522                 if (IS_I830(dev_priv))
7523                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7524
7525                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7526                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7527         } else {
7528                 /* Mask out read-only status bits. */
7529                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7530                                                      DPLL_PORTC_READY_MASK |
7531                                                      DPLL_PORTB_READY_MASK);
7532         }
7533
7534         if (IS_CHERRYVIEW(dev_priv))
7535                 chv_crtc_clock_get(crtc, pipe_config);
7536         else if (IS_VALLEYVIEW(dev_priv))
7537                 vlv_crtc_clock_get(crtc, pipe_config);
7538         else
7539                 i9xx_crtc_clock_get(crtc, pipe_config);
7540
7541         /*
7542          * Normally the dotclock is filled in by the encoder .get_config()
7543          * but in case the pipe is enabled w/o any ports we need a sane
7544          * default.
7545          */
7546         pipe_config->base.adjusted_mode.crtc_clock =
7547                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7548
7549         ret = true;
7550
7551 out:
7552         intel_display_power_put(dev_priv, power_domain);
7553
7554         return ret;
7555 }
7556
7557 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7558 {
7559         struct intel_encoder *encoder;
7560         int i;
7561         u32 val, final;
7562         bool has_lvds = false;
7563         bool has_cpu_edp = false;
7564         bool has_panel = false;
7565         bool has_ck505 = false;
7566         bool can_ssc = false;
7567         bool using_ssc_source = false;
7568
7569         /* We need to take the global config into account */
7570         for_each_intel_encoder(&dev_priv->drm, encoder) {
7571                 switch (encoder->type) {
7572                 case INTEL_OUTPUT_LVDS:
7573                         has_panel = true;
7574                         has_lvds = true;
7575                         break;
7576                 case INTEL_OUTPUT_EDP:
7577                         has_panel = true;
7578                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7579                                 has_cpu_edp = true;
7580                         break;
7581                 default:
7582                         break;
7583                 }
7584         }
7585
7586         if (HAS_PCH_IBX(dev_priv)) {
7587                 has_ck505 = dev_priv->vbt.display_clock_mode;
7588                 can_ssc = has_ck505;
7589         } else {
7590                 has_ck505 = false;
7591                 can_ssc = true;
7592         }
7593
7594         /* Check if any DPLLs are using the SSC source */
7595         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7596                 u32 temp = I915_READ(PCH_DPLL(i));
7597
7598                 if (!(temp & DPLL_VCO_ENABLE))
7599                         continue;
7600
7601                 if ((temp & PLL_REF_INPUT_MASK) ==
7602                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7603                         using_ssc_source = true;
7604                         break;
7605                 }
7606         }
7607
7608         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7609                       has_panel, has_lvds, has_ck505, using_ssc_source);
7610
7611         /* Ironlake: try to setup display ref clock before DPLL
7612          * enabling. This is only under driver's control after
7613          * PCH B stepping, previous chipset stepping should be
7614          * ignoring this setting.
7615          */
7616         val = I915_READ(PCH_DREF_CONTROL);
7617
7618         /* As we must carefully and slowly disable/enable each source in turn,
7619          * compute the final state we want first and check if we need to
7620          * make any changes at all.
7621          */
7622         final = val;
7623         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7624         if (has_ck505)
7625                 final |= DREF_NONSPREAD_CK505_ENABLE;
7626         else
7627                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7628
7629         final &= ~DREF_SSC_SOURCE_MASK;
7630         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7631         final &= ~DREF_SSC1_ENABLE;
7632
7633         if (has_panel) {
7634                 final |= DREF_SSC_SOURCE_ENABLE;
7635
7636                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7637                         final |= DREF_SSC1_ENABLE;
7638
7639                 if (has_cpu_edp) {
7640                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7641                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7642                         else
7643                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7644                 } else
7645                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7646         } else if (using_ssc_source) {
7647                 final |= DREF_SSC_SOURCE_ENABLE;
7648                 final |= DREF_SSC1_ENABLE;
7649         }
7650
7651         if (final == val)
7652                 return;
7653
7654         /* Always enable nonspread source */
7655         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7656
7657         if (has_ck505)
7658                 val |= DREF_NONSPREAD_CK505_ENABLE;
7659         else
7660                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7661
7662         if (has_panel) {
7663                 val &= ~DREF_SSC_SOURCE_MASK;
7664                 val |= DREF_SSC_SOURCE_ENABLE;
7665
7666                 /* SSC must be turned on before enabling the CPU output  */
7667                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7668                         DRM_DEBUG_KMS("Using SSC on panel\n");
7669                         val |= DREF_SSC1_ENABLE;
7670                 } else
7671                         val &= ~DREF_SSC1_ENABLE;
7672
7673                 /* Get SSC going before enabling the outputs */
7674                 I915_WRITE(PCH_DREF_CONTROL, val);
7675                 POSTING_READ(PCH_DREF_CONTROL);
7676                 udelay(200);
7677
7678                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7679
7680                 /* Enable CPU source on CPU attached eDP */
7681                 if (has_cpu_edp) {
7682                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7683                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7684                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7685                         } else
7686                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7687                 } else
7688                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7689
7690                 I915_WRITE(PCH_DREF_CONTROL, val);
7691                 POSTING_READ(PCH_DREF_CONTROL);
7692                 udelay(200);
7693         } else {
7694                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7695
7696                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7697
7698                 /* Turn off CPU output */
7699                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7700
7701                 I915_WRITE(PCH_DREF_CONTROL, val);
7702                 POSTING_READ(PCH_DREF_CONTROL);
7703                 udelay(200);
7704
7705                 if (!using_ssc_source) {
7706                         DRM_DEBUG_KMS("Disabling SSC source\n");
7707
7708                         /* Turn off the SSC source */
7709                         val &= ~DREF_SSC_SOURCE_MASK;
7710                         val |= DREF_SSC_SOURCE_DISABLE;
7711
7712                         /* Turn off SSC1 */
7713                         val &= ~DREF_SSC1_ENABLE;
7714
7715                         I915_WRITE(PCH_DREF_CONTROL, val);
7716                         POSTING_READ(PCH_DREF_CONTROL);
7717                         udelay(200);
7718                 }
7719         }
7720
7721         BUG_ON(val != final);
7722 }
7723
7724 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7725 {
7726         uint32_t tmp;
7727
7728         tmp = I915_READ(SOUTH_CHICKEN2);
7729         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7730         I915_WRITE(SOUTH_CHICKEN2, tmp);
7731
7732         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7733                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7734                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7735
7736         tmp = I915_READ(SOUTH_CHICKEN2);
7737         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7738         I915_WRITE(SOUTH_CHICKEN2, tmp);
7739
7740         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7741                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7742                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7743 }
7744
7745 /* WaMPhyProgramming:hsw */
7746 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7747 {
7748         uint32_t tmp;
7749
7750         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7751         tmp &= ~(0xFF << 24);
7752         tmp |= (0x12 << 24);
7753         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7754
7755         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7756         tmp |= (1 << 11);
7757         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7758
7759         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7760         tmp |= (1 << 11);
7761         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7762
7763         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7764         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7765         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7766
7767         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7768         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7769         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7770
7771         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7772         tmp &= ~(7 << 13);
7773         tmp |= (5 << 13);
7774         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7775
7776         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7777         tmp &= ~(7 << 13);
7778         tmp |= (5 << 13);
7779         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7780
7781         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7782         tmp &= ~0xFF;
7783         tmp |= 0x1C;
7784         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7785
7786         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7787         tmp &= ~0xFF;
7788         tmp |= 0x1C;
7789         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7790
7791         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7792         tmp &= ~(0xFF << 16);
7793         tmp |= (0x1C << 16);
7794         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7795
7796         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7797         tmp &= ~(0xFF << 16);
7798         tmp |= (0x1C << 16);
7799         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7800
7801         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7802         tmp |= (1 << 27);
7803         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7804
7805         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7806         tmp |= (1 << 27);
7807         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7808
7809         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7810         tmp &= ~(0xF << 28);
7811         tmp |= (4 << 28);
7812         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7813
7814         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7815         tmp &= ~(0xF << 28);
7816         tmp |= (4 << 28);
7817         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7818 }
7819
7820 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7821  * Programming" based on the parameters passed:
7822  * - Sequence to enable CLKOUT_DP
7823  * - Sequence to enable CLKOUT_DP without spread
7824  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7825  */
7826 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7827                                  bool with_spread, bool with_fdi)
7828 {
7829         uint32_t reg, tmp;
7830
7831         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7832                 with_spread = true;
7833         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7834             with_fdi, "LP PCH doesn't have FDI\n"))
7835                 with_fdi = false;
7836
7837         mutex_lock(&dev_priv->sb_lock);
7838
7839         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7840         tmp &= ~SBI_SSCCTL_DISABLE;
7841         tmp |= SBI_SSCCTL_PATHALT;
7842         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7843
7844         udelay(24);
7845
7846         if (with_spread) {
7847                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7848                 tmp &= ~SBI_SSCCTL_PATHALT;
7849                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7850
7851                 if (with_fdi) {
7852                         lpt_reset_fdi_mphy(dev_priv);
7853                         lpt_program_fdi_mphy(dev_priv);
7854                 }
7855         }
7856
7857         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7858         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7859         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7860         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7861
7862         mutex_unlock(&dev_priv->sb_lock);
7863 }
7864
7865 /* Sequence to disable CLKOUT_DP */
7866 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7867 {
7868         uint32_t reg, tmp;
7869
7870         mutex_lock(&dev_priv->sb_lock);
7871
7872         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7873         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7874         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7875         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7876
7877         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7878         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7879                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7880                         tmp |= SBI_SSCCTL_PATHALT;
7881                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7882                         udelay(32);
7883                 }
7884                 tmp |= SBI_SSCCTL_DISABLE;
7885                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7886         }
7887
7888         mutex_unlock(&dev_priv->sb_lock);
7889 }
7890
7891 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7892
7893 static const uint16_t sscdivintphase[] = {
7894         [BEND_IDX( 50)] = 0x3B23,
7895         [BEND_IDX( 45)] = 0x3B23,
7896         [BEND_IDX( 40)] = 0x3C23,
7897         [BEND_IDX( 35)] = 0x3C23,
7898         [BEND_IDX( 30)] = 0x3D23,
7899         [BEND_IDX( 25)] = 0x3D23,
7900         [BEND_IDX( 20)] = 0x3E23,
7901         [BEND_IDX( 15)] = 0x3E23,
7902         [BEND_IDX( 10)] = 0x3F23,
7903         [BEND_IDX(  5)] = 0x3F23,
7904         [BEND_IDX(  0)] = 0x0025,
7905         [BEND_IDX( -5)] = 0x0025,
7906         [BEND_IDX(-10)] = 0x0125,
7907         [BEND_IDX(-15)] = 0x0125,
7908         [BEND_IDX(-20)] = 0x0225,
7909         [BEND_IDX(-25)] = 0x0225,
7910         [BEND_IDX(-30)] = 0x0325,
7911         [BEND_IDX(-35)] = 0x0325,
7912         [BEND_IDX(-40)] = 0x0425,
7913         [BEND_IDX(-45)] = 0x0425,
7914         [BEND_IDX(-50)] = 0x0525,
7915 };
7916
7917 /*
7918  * Bend CLKOUT_DP
7919  * steps -50 to 50 inclusive, in steps of 5
7920  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7921  * change in clock period = -(steps / 10) * 5.787 ps
7922  */
7923 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7924 {
7925         uint32_t tmp;
7926         int idx = BEND_IDX(steps);
7927
7928         if (WARN_ON(steps % 5 != 0))
7929                 return;
7930
7931         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7932                 return;
7933
7934         mutex_lock(&dev_priv->sb_lock);
7935
7936         if (steps % 10 != 0)
7937                 tmp = 0xAAAAAAAB;
7938         else
7939                 tmp = 0x00000000;
7940         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7941
7942         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7943         tmp &= 0xffff0000;
7944         tmp |= sscdivintphase[idx];
7945         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7946
7947         mutex_unlock(&dev_priv->sb_lock);
7948 }
7949
7950 #undef BEND_IDX
7951
7952 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7953 {
7954         struct intel_encoder *encoder;
7955         bool has_vga = false;
7956
7957         for_each_intel_encoder(&dev_priv->drm, encoder) {
7958                 switch (encoder->type) {
7959                 case INTEL_OUTPUT_ANALOG:
7960                         has_vga = true;
7961                         break;
7962                 default:
7963                         break;
7964                 }
7965         }
7966
7967         if (has_vga) {
7968                 lpt_bend_clkout_dp(dev_priv, 0);
7969                 lpt_enable_clkout_dp(dev_priv, true, true);
7970         } else {
7971                 lpt_disable_clkout_dp(dev_priv);
7972         }
7973 }
7974
7975 /*
7976  * Initialize reference clocks when the driver loads
7977  */
7978 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7979 {
7980         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7981                 ironlake_init_pch_refclk(dev_priv);
7982         else if (HAS_PCH_LPT(dev_priv))
7983                 lpt_init_pch_refclk(dev_priv);
7984 }
7985
7986 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7987 {
7988         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7990         int pipe = intel_crtc->pipe;
7991         uint32_t val;
7992
7993         val = 0;
7994
7995         switch (intel_crtc->config->pipe_bpp) {
7996         case 18:
7997                 val |= PIPECONF_6BPC;
7998                 break;
7999         case 24:
8000                 val |= PIPECONF_8BPC;
8001                 break;
8002         case 30:
8003                 val |= PIPECONF_10BPC;
8004                 break;
8005         case 36:
8006                 val |= PIPECONF_12BPC;
8007                 break;
8008         default:
8009                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8010                 BUG();
8011         }
8012
8013         if (intel_crtc->config->dither)
8014                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8015
8016         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8017                 val |= PIPECONF_INTERLACED_ILK;
8018         else
8019                 val |= PIPECONF_PROGRESSIVE;
8020
8021         if (intel_crtc->config->limited_color_range)
8022                 val |= PIPECONF_COLOR_RANGE_SELECT;
8023
8024         I915_WRITE(PIPECONF(pipe), val);
8025         POSTING_READ(PIPECONF(pipe));
8026 }
8027
8028 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8029 {
8030         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8032         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8033         u32 val = 0;
8034
8035         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8036                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8037
8038         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8039                 val |= PIPECONF_INTERLACED_ILK;
8040         else
8041                 val |= PIPECONF_PROGRESSIVE;
8042
8043         I915_WRITE(PIPECONF(cpu_transcoder), val);
8044         POSTING_READ(PIPECONF(cpu_transcoder));
8045 }
8046
8047 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8048 {
8049         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8051
8052         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8053                 u32 val = 0;
8054
8055                 switch (intel_crtc->config->pipe_bpp) {
8056                 case 18:
8057                         val |= PIPEMISC_DITHER_6_BPC;
8058                         break;
8059                 case 24:
8060                         val |= PIPEMISC_DITHER_8_BPC;
8061                         break;
8062                 case 30:
8063                         val |= PIPEMISC_DITHER_10_BPC;
8064                         break;
8065                 case 36:
8066                         val |= PIPEMISC_DITHER_12_BPC;
8067                         break;
8068                 default:
8069                         /* Case prevented by pipe_config_set_bpp. */
8070                         BUG();
8071                 }
8072
8073                 if (intel_crtc->config->dither)
8074                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8075
8076                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8077         }
8078 }
8079
8080 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8081 {
8082         /*
8083          * Account for spread spectrum to avoid
8084          * oversubscribing the link. Max center spread
8085          * is 2.5%; use 5% for safety's sake.
8086          */
8087         u32 bps = target_clock * bpp * 21 / 20;
8088         return DIV_ROUND_UP(bps, link_bw * 8);
8089 }
8090
8091 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8092 {
8093         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8094 }
8095
8096 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8097                                   struct intel_crtc_state *crtc_state,
8098                                   struct dpll *reduced_clock)
8099 {
8100         struct drm_crtc *crtc = &intel_crtc->base;
8101         struct drm_device *dev = crtc->dev;
8102         struct drm_i915_private *dev_priv = to_i915(dev);
8103         u32 dpll, fp, fp2;
8104         int factor;
8105
8106         /* Enable autotuning of the PLL clock (if permissible) */
8107         factor = 21;
8108         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8109                 if ((intel_panel_use_ssc(dev_priv) &&
8110                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8111                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8112                         factor = 25;
8113         } else if (crtc_state->sdvo_tv_clock)
8114                 factor = 20;
8115
8116         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8117
8118         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8119                 fp |= FP_CB_TUNE;
8120
8121         if (reduced_clock) {
8122                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8123
8124                 if (reduced_clock->m < factor * reduced_clock->n)
8125                         fp2 |= FP_CB_TUNE;
8126         } else {
8127                 fp2 = fp;
8128         }
8129
8130         dpll = 0;
8131
8132         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8133                 dpll |= DPLLB_MODE_LVDS;
8134         else
8135                 dpll |= DPLLB_MODE_DAC_SERIAL;
8136
8137         dpll |= (crtc_state->pixel_multiplier - 1)
8138                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8139
8140         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8141             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8142                 dpll |= DPLL_SDVO_HIGH_SPEED;
8143
8144         if (intel_crtc_has_dp_encoder(crtc_state))
8145                 dpll |= DPLL_SDVO_HIGH_SPEED;
8146
8147         /*
8148          * The high speed IO clock is only really required for
8149          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8150          * possible to share the DPLL between CRT and HDMI. Enabling
8151          * the clock needlessly does no real harm, except use up a
8152          * bit of power potentially.
8153          *
8154          * We'll limit this to IVB with 3 pipes, since it has only two
8155          * DPLLs and so DPLL sharing is the only way to get three pipes
8156          * driving PCH ports at the same time. On SNB we could do this,
8157          * and potentially avoid enabling the second DPLL, but it's not
8158          * clear if it''s a win or loss power wise. No point in doing
8159          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8160          */
8161         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8162             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8163                 dpll |= DPLL_SDVO_HIGH_SPEED;
8164
8165         /* compute bitmask from p1 value */
8166         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8167         /* also FPA1 */
8168         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8169
8170         switch (crtc_state->dpll.p2) {
8171         case 5:
8172                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8173                 break;
8174         case 7:
8175                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8176                 break;
8177         case 10:
8178                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8179                 break;
8180         case 14:
8181                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8182                 break;
8183         }
8184
8185         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8186             intel_panel_use_ssc(dev_priv))
8187                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8188         else
8189                 dpll |= PLL_REF_INPUT_DREFCLK;
8190
8191         dpll |= DPLL_VCO_ENABLE;
8192
8193         crtc_state->dpll_hw_state.dpll = dpll;
8194         crtc_state->dpll_hw_state.fp0 = fp;
8195         crtc_state->dpll_hw_state.fp1 = fp2;
8196 }
8197
8198 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8199                                        struct intel_crtc_state *crtc_state)
8200 {
8201         struct drm_device *dev = crtc->base.dev;
8202         struct drm_i915_private *dev_priv = to_i915(dev);
8203         const struct intel_limit *limit;
8204         int refclk = 120000;
8205
8206         memset(&crtc_state->dpll_hw_state, 0,
8207                sizeof(crtc_state->dpll_hw_state));
8208
8209         crtc->lowfreq_avail = false;
8210
8211         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8212         if (!crtc_state->has_pch_encoder)
8213                 return 0;
8214
8215         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8216                 if (intel_panel_use_ssc(dev_priv)) {
8217                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8218                                       dev_priv->vbt.lvds_ssc_freq);
8219                         refclk = dev_priv->vbt.lvds_ssc_freq;
8220                 }
8221
8222                 if (intel_is_dual_link_lvds(dev)) {
8223                         if (refclk == 100000)
8224                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8225                         else
8226                                 limit = &intel_limits_ironlake_dual_lvds;
8227                 } else {
8228                         if (refclk == 100000)
8229                                 limit = &intel_limits_ironlake_single_lvds_100m;
8230                         else
8231                                 limit = &intel_limits_ironlake_single_lvds;
8232                 }
8233         } else {
8234                 limit = &intel_limits_ironlake_dac;
8235         }
8236
8237         if (!crtc_state->clock_set &&
8238             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8239                                 refclk, NULL, &crtc_state->dpll)) {
8240                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8241                 return -EINVAL;
8242         }
8243
8244         ironlake_compute_dpll(crtc, crtc_state, NULL);
8245
8246         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8247                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8248                                  pipe_name(crtc->pipe));
8249                 return -EINVAL;
8250         }
8251
8252         return 0;
8253 }
8254
8255 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8256                                          struct intel_link_m_n *m_n)
8257 {
8258         struct drm_device *dev = crtc->base.dev;
8259         struct drm_i915_private *dev_priv = to_i915(dev);
8260         enum pipe pipe = crtc->pipe;
8261
8262         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8263         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8264         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8265                 & ~TU_SIZE_MASK;
8266         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8267         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8268                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8269 }
8270
8271 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8272                                          enum transcoder transcoder,
8273                                          struct intel_link_m_n *m_n,
8274                                          struct intel_link_m_n *m2_n2)
8275 {
8276         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8277         enum pipe pipe = crtc->pipe;
8278
8279         if (INTEL_GEN(dev_priv) >= 5) {
8280                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8281                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8282                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8283                         & ~TU_SIZE_MASK;
8284                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8285                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8286                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8287                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8288                  * gen < 8) and if DRRS is supported (to make sure the
8289                  * registers are not unnecessarily read).
8290                  */
8291                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8292                         crtc->config->has_drrs) {
8293                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8294                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8295                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8296                                         & ~TU_SIZE_MASK;
8297                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8298                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8299                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8300                 }
8301         } else {
8302                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8303                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8304                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8305                         & ~TU_SIZE_MASK;
8306                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8307                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8308                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8309         }
8310 }
8311
8312 void intel_dp_get_m_n(struct intel_crtc *crtc,
8313                       struct intel_crtc_state *pipe_config)
8314 {
8315         if (pipe_config->has_pch_encoder)
8316                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8317         else
8318                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8319                                              &pipe_config->dp_m_n,
8320                                              &pipe_config->dp_m2_n2);
8321 }
8322
8323 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8324                                         struct intel_crtc_state *pipe_config)
8325 {
8326         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8327                                      &pipe_config->fdi_m_n, NULL);
8328 }
8329
8330 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8331                                     struct intel_crtc_state *pipe_config)
8332 {
8333         struct drm_device *dev = crtc->base.dev;
8334         struct drm_i915_private *dev_priv = to_i915(dev);
8335         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8336         uint32_t ps_ctrl = 0;
8337         int id = -1;
8338         int i;
8339
8340         /* find scaler attached to this pipe */
8341         for (i = 0; i < crtc->num_scalers; i++) {
8342                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8343                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8344                         id = i;
8345                         pipe_config->pch_pfit.enabled = true;
8346                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8347                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8348                         break;
8349                 }
8350         }
8351
8352         scaler_state->scaler_id = id;
8353         if (id >= 0) {
8354                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8355         } else {
8356                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8357         }
8358 }
8359
8360 static void
8361 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8362                                  struct intel_initial_plane_config *plane_config)
8363 {
8364         struct drm_device *dev = crtc->base.dev;
8365         struct drm_i915_private *dev_priv = to_i915(dev);
8366         u32 val, base, offset, stride_mult, tiling;
8367         int pipe = crtc->pipe;
8368         int fourcc, pixel_format;
8369         unsigned int aligned_height;
8370         struct drm_framebuffer *fb;
8371         struct intel_framebuffer *intel_fb;
8372
8373         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8374         if (!intel_fb) {
8375                 DRM_DEBUG_KMS("failed to alloc fb\n");
8376                 return;
8377         }
8378
8379         fb = &intel_fb->base;
8380
8381         fb->dev = dev;
8382
8383         val = I915_READ(PLANE_CTL(pipe, 0));
8384         if (!(val & PLANE_CTL_ENABLE))
8385                 goto error;
8386
8387         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8388         fourcc = skl_format_to_fourcc(pixel_format,
8389                                       val & PLANE_CTL_ORDER_RGBX,
8390                                       val & PLANE_CTL_ALPHA_MASK);
8391         fb->format = drm_format_info(fourcc);
8392
8393         tiling = val & PLANE_CTL_TILED_MASK;
8394         switch (tiling) {
8395         case PLANE_CTL_TILED_LINEAR:
8396                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8397                 break;
8398         case PLANE_CTL_TILED_X:
8399                 plane_config->tiling = I915_TILING_X;
8400                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8401                 break;
8402         case PLANE_CTL_TILED_Y:
8403                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8404                 break;
8405         case PLANE_CTL_TILED_YF:
8406                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8407                 break;
8408         default:
8409                 MISSING_CASE(tiling);
8410                 goto error;
8411         }
8412
8413         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8414         plane_config->base = base;
8415
8416         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8417
8418         val = I915_READ(PLANE_SIZE(pipe, 0));
8419         fb->height = ((val >> 16) & 0xfff) + 1;
8420         fb->width = ((val >> 0) & 0x1fff) + 1;
8421
8422         val = I915_READ(PLANE_STRIDE(pipe, 0));
8423         stride_mult = intel_fb_stride_alignment(fb, 0);
8424         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8425
8426         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8427
8428         plane_config->size = fb->pitches[0] * aligned_height;
8429
8430         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8431                       pipe_name(pipe), fb->width, fb->height,
8432                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8433                       plane_config->size);
8434
8435         plane_config->fb = intel_fb;
8436         return;
8437
8438 error:
8439         kfree(intel_fb);
8440 }
8441
8442 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8443                                      struct intel_crtc_state *pipe_config)
8444 {
8445         struct drm_device *dev = crtc->base.dev;
8446         struct drm_i915_private *dev_priv = to_i915(dev);
8447         uint32_t tmp;
8448
8449         tmp = I915_READ(PF_CTL(crtc->pipe));
8450
8451         if (tmp & PF_ENABLE) {
8452                 pipe_config->pch_pfit.enabled = true;
8453                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8454                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8455
8456                 /* We currently do not free assignements of panel fitters on
8457                  * ivb/hsw (since we don't use the higher upscaling modes which
8458                  * differentiates them) so just WARN about this case for now. */
8459                 if (IS_GEN7(dev_priv)) {
8460                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8461                                 PF_PIPE_SEL_IVB(crtc->pipe));
8462                 }
8463         }
8464 }
8465
8466 static void
8467 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8468                                   struct intel_initial_plane_config *plane_config)
8469 {
8470         struct drm_device *dev = crtc->base.dev;
8471         struct drm_i915_private *dev_priv = to_i915(dev);
8472         u32 val, base, offset;
8473         int pipe = crtc->pipe;
8474         int fourcc, pixel_format;
8475         unsigned int aligned_height;
8476         struct drm_framebuffer *fb;
8477         struct intel_framebuffer *intel_fb;
8478
8479         val = I915_READ(DSPCNTR(pipe));
8480         if (!(val & DISPLAY_PLANE_ENABLE))
8481                 return;
8482
8483         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8484         if (!intel_fb) {
8485                 DRM_DEBUG_KMS("failed to alloc fb\n");
8486                 return;
8487         }
8488
8489         fb = &intel_fb->base;
8490
8491         fb->dev = dev;
8492
8493         if (INTEL_GEN(dev_priv) >= 4) {
8494                 if (val & DISPPLANE_TILED) {
8495                         plane_config->tiling = I915_TILING_X;
8496                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8497                 }
8498         }
8499
8500         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8501         fourcc = i9xx_format_to_fourcc(pixel_format);
8502         fb->format = drm_format_info(fourcc);
8503
8504         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8505         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8506                 offset = I915_READ(DSPOFFSET(pipe));
8507         } else {
8508                 if (plane_config->tiling)
8509                         offset = I915_READ(DSPTILEOFF(pipe));
8510                 else
8511                         offset = I915_READ(DSPLINOFF(pipe));
8512         }
8513         plane_config->base = base;
8514
8515         val = I915_READ(PIPESRC(pipe));
8516         fb->width = ((val >> 16) & 0xfff) + 1;
8517         fb->height = ((val >> 0) & 0xfff) + 1;
8518
8519         val = I915_READ(DSPSTRIDE(pipe));
8520         fb->pitches[0] = val & 0xffffffc0;
8521
8522         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8523
8524         plane_config->size = fb->pitches[0] * aligned_height;
8525
8526         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8527                       pipe_name(pipe), fb->width, fb->height,
8528                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8529                       plane_config->size);
8530
8531         plane_config->fb = intel_fb;
8532 }
8533
8534 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8535                                      struct intel_crtc_state *pipe_config)
8536 {
8537         struct drm_device *dev = crtc->base.dev;
8538         struct drm_i915_private *dev_priv = to_i915(dev);
8539         enum intel_display_power_domain power_domain;
8540         uint32_t tmp;
8541         bool ret;
8542
8543         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8544         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8545                 return false;
8546
8547         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8548         pipe_config->shared_dpll = NULL;
8549
8550         ret = false;
8551         tmp = I915_READ(PIPECONF(crtc->pipe));
8552         if (!(tmp & PIPECONF_ENABLE))
8553                 goto out;
8554
8555         switch (tmp & PIPECONF_BPC_MASK) {
8556         case PIPECONF_6BPC:
8557                 pipe_config->pipe_bpp = 18;
8558                 break;
8559         case PIPECONF_8BPC:
8560                 pipe_config->pipe_bpp = 24;
8561                 break;
8562         case PIPECONF_10BPC:
8563                 pipe_config->pipe_bpp = 30;
8564                 break;
8565         case PIPECONF_12BPC:
8566                 pipe_config->pipe_bpp = 36;
8567                 break;
8568         default:
8569                 break;
8570         }
8571
8572         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8573                 pipe_config->limited_color_range = true;
8574
8575         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8576                 struct intel_shared_dpll *pll;
8577                 enum intel_dpll_id pll_id;
8578
8579                 pipe_config->has_pch_encoder = true;
8580
8581                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8582                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8583                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8584
8585                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8586
8587                 if (HAS_PCH_IBX(dev_priv)) {
8588                         /*
8589                          * The pipe->pch transcoder and pch transcoder->pll
8590                          * mapping is fixed.
8591                          */
8592                         pll_id = (enum intel_dpll_id) crtc->pipe;
8593                 } else {
8594                         tmp = I915_READ(PCH_DPLL_SEL);
8595                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8596                                 pll_id = DPLL_ID_PCH_PLL_B;
8597                         else
8598                                 pll_id= DPLL_ID_PCH_PLL_A;
8599                 }
8600
8601                 pipe_config->shared_dpll =
8602                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8603                 pll = pipe_config->shared_dpll;
8604
8605                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8606                                                  &pipe_config->dpll_hw_state));
8607
8608                 tmp = pipe_config->dpll_hw_state.dpll;
8609                 pipe_config->pixel_multiplier =
8610                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8611                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8612
8613                 ironlake_pch_clock_get(crtc, pipe_config);
8614         } else {
8615                 pipe_config->pixel_multiplier = 1;
8616         }
8617
8618         intel_get_pipe_timings(crtc, pipe_config);
8619         intel_get_pipe_src_size(crtc, pipe_config);
8620
8621         ironlake_get_pfit_config(crtc, pipe_config);
8622
8623         ret = true;
8624
8625 out:
8626         intel_display_power_put(dev_priv, power_domain);
8627
8628         return ret;
8629 }
8630
8631 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8632 {
8633         struct drm_device *dev = &dev_priv->drm;
8634         struct intel_crtc *crtc;
8635
8636         for_each_intel_crtc(dev, crtc)
8637                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8638                      pipe_name(crtc->pipe));
8639
8640         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8641         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8642         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8643         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8644         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8645         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8646              "CPU PWM1 enabled\n");
8647         if (IS_HASWELL(dev_priv))
8648                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8649                      "CPU PWM2 enabled\n");
8650         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8651              "PCH PWM1 enabled\n");
8652         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8653              "Utility pin enabled\n");
8654         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8655
8656         /*
8657          * In theory we can still leave IRQs enabled, as long as only the HPD
8658          * interrupts remain enabled. We used to check for that, but since it's
8659          * gen-specific and since we only disable LCPLL after we fully disable
8660          * the interrupts, the check below should be enough.
8661          */
8662         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8663 }
8664
8665 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8666 {
8667         if (IS_HASWELL(dev_priv))
8668                 return I915_READ(D_COMP_HSW);
8669         else
8670                 return I915_READ(D_COMP_BDW);
8671 }
8672
8673 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8674 {
8675         if (IS_HASWELL(dev_priv)) {
8676                 mutex_lock(&dev_priv->rps.hw_lock);
8677                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8678                                             val))
8679                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8680                 mutex_unlock(&dev_priv->rps.hw_lock);
8681         } else {
8682                 I915_WRITE(D_COMP_BDW, val);
8683                 POSTING_READ(D_COMP_BDW);
8684         }
8685 }
8686
8687 /*
8688  * This function implements pieces of two sequences from BSpec:
8689  * - Sequence for display software to disable LCPLL
8690  * - Sequence for display software to allow package C8+
8691  * The steps implemented here are just the steps that actually touch the LCPLL
8692  * register. Callers should take care of disabling all the display engine
8693  * functions, doing the mode unset, fixing interrupts, etc.
8694  */
8695 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8696                               bool switch_to_fclk, bool allow_power_down)
8697 {
8698         uint32_t val;
8699
8700         assert_can_disable_lcpll(dev_priv);
8701
8702         val = I915_READ(LCPLL_CTL);
8703
8704         if (switch_to_fclk) {
8705                 val |= LCPLL_CD_SOURCE_FCLK;
8706                 I915_WRITE(LCPLL_CTL, val);
8707
8708                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8709                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8710                         DRM_ERROR("Switching to FCLK failed\n");
8711
8712                 val = I915_READ(LCPLL_CTL);
8713         }
8714
8715         val |= LCPLL_PLL_DISABLE;
8716         I915_WRITE(LCPLL_CTL, val);
8717         POSTING_READ(LCPLL_CTL);
8718
8719         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8720                 DRM_ERROR("LCPLL still locked\n");
8721
8722         val = hsw_read_dcomp(dev_priv);
8723         val |= D_COMP_COMP_DISABLE;
8724         hsw_write_dcomp(dev_priv, val);
8725         ndelay(100);
8726
8727         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8728                      1))
8729                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8730
8731         if (allow_power_down) {
8732                 val = I915_READ(LCPLL_CTL);
8733                 val |= LCPLL_POWER_DOWN_ALLOW;
8734                 I915_WRITE(LCPLL_CTL, val);
8735                 POSTING_READ(LCPLL_CTL);
8736         }
8737 }
8738
8739 /*
8740  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8741  * source.
8742  */
8743 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8744 {
8745         uint32_t val;
8746
8747         val = I915_READ(LCPLL_CTL);
8748
8749         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8750                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8751                 return;
8752
8753         /*
8754          * Make sure we're not on PC8 state before disabling PC8, otherwise
8755          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8756          */
8757         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8758
8759         if (val & LCPLL_POWER_DOWN_ALLOW) {
8760                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8761                 I915_WRITE(LCPLL_CTL, val);
8762                 POSTING_READ(LCPLL_CTL);
8763         }
8764
8765         val = hsw_read_dcomp(dev_priv);
8766         val |= D_COMP_COMP_FORCE;
8767         val &= ~D_COMP_COMP_DISABLE;
8768         hsw_write_dcomp(dev_priv, val);
8769
8770         val = I915_READ(LCPLL_CTL);
8771         val &= ~LCPLL_PLL_DISABLE;
8772         I915_WRITE(LCPLL_CTL, val);
8773
8774         if (intel_wait_for_register(dev_priv,
8775                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8776                                     5))
8777                 DRM_ERROR("LCPLL not locked yet\n");
8778
8779         if (val & LCPLL_CD_SOURCE_FCLK) {
8780                 val = I915_READ(LCPLL_CTL);
8781                 val &= ~LCPLL_CD_SOURCE_FCLK;
8782                 I915_WRITE(LCPLL_CTL, val);
8783
8784                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8785                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8786                         DRM_ERROR("Switching back to LCPLL failed\n");
8787         }
8788
8789         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8790         intel_update_cdclk(dev_priv);
8791 }
8792
8793 /*
8794  * Package states C8 and deeper are really deep PC states that can only be
8795  * reached when all the devices on the system allow it, so even if the graphics
8796  * device allows PC8+, it doesn't mean the system will actually get to these
8797  * states. Our driver only allows PC8+ when going into runtime PM.
8798  *
8799  * The requirements for PC8+ are that all the outputs are disabled, the power
8800  * well is disabled and most interrupts are disabled, and these are also
8801  * requirements for runtime PM. When these conditions are met, we manually do
8802  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8803  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8804  * hang the machine.
8805  *
8806  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8807  * the state of some registers, so when we come back from PC8+ we need to
8808  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8809  * need to take care of the registers kept by RC6. Notice that this happens even
8810  * if we don't put the device in PCI D3 state (which is what currently happens
8811  * because of the runtime PM support).
8812  *
8813  * For more, read "Display Sequences for Package C8" on the hardware
8814  * documentation.
8815  */
8816 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8817 {
8818         uint32_t val;
8819
8820         DRM_DEBUG_KMS("Enabling package C8+\n");
8821
8822         if (HAS_PCH_LPT_LP(dev_priv)) {
8823                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8824                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8825                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8826         }
8827
8828         lpt_disable_clkout_dp(dev_priv);
8829         hsw_disable_lcpll(dev_priv, true, true);
8830 }
8831
8832 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8833 {
8834         uint32_t val;
8835
8836         DRM_DEBUG_KMS("Disabling package C8+\n");
8837
8838         hsw_restore_lcpll(dev_priv);
8839         lpt_init_pch_refclk(dev_priv);
8840
8841         if (HAS_PCH_LPT_LP(dev_priv)) {
8842                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8843                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8844                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8845         }
8846 }
8847
8848 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8849                                       struct intel_crtc_state *crtc_state)
8850 {
8851         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8852                 struct intel_encoder *encoder =
8853                         intel_ddi_get_crtc_new_encoder(crtc_state);
8854
8855                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8856                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8857                                          pipe_name(crtc->pipe));
8858                         return -EINVAL;
8859                 }
8860         }
8861
8862         crtc->lowfreq_avail = false;
8863
8864         return 0;
8865 }
8866
8867 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8868                                 enum port port,
8869                                 struct intel_crtc_state *pipe_config)
8870 {
8871         enum intel_dpll_id id;
8872
8873         switch (port) {
8874         case PORT_A:
8875                 id = DPLL_ID_SKL_DPLL0;
8876                 break;
8877         case PORT_B:
8878                 id = DPLL_ID_SKL_DPLL1;
8879                 break;
8880         case PORT_C:
8881                 id = DPLL_ID_SKL_DPLL2;
8882                 break;
8883         default:
8884                 DRM_ERROR("Incorrect port type\n");
8885                 return;
8886         }
8887
8888         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8889 }
8890
8891 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8892                                 enum port port,
8893                                 struct intel_crtc_state *pipe_config)
8894 {
8895         enum intel_dpll_id id;
8896         u32 temp;
8897
8898         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8899         id = temp >> (port * 3 + 1);
8900
8901         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8902                 return;
8903
8904         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8905 }
8906
8907 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8908                                 enum port port,
8909                                 struct intel_crtc_state *pipe_config)
8910 {
8911         enum intel_dpll_id id;
8912         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8913
8914         switch (ddi_pll_sel) {
8915         case PORT_CLK_SEL_WRPLL1:
8916                 id = DPLL_ID_WRPLL1;
8917                 break;
8918         case PORT_CLK_SEL_WRPLL2:
8919                 id = DPLL_ID_WRPLL2;
8920                 break;
8921         case PORT_CLK_SEL_SPLL:
8922                 id = DPLL_ID_SPLL;
8923                 break;
8924         case PORT_CLK_SEL_LCPLL_810:
8925                 id = DPLL_ID_LCPLL_810;
8926                 break;
8927         case PORT_CLK_SEL_LCPLL_1350:
8928                 id = DPLL_ID_LCPLL_1350;
8929                 break;
8930         case PORT_CLK_SEL_LCPLL_2700:
8931                 id = DPLL_ID_LCPLL_2700;
8932                 break;
8933         default:
8934                 MISSING_CASE(ddi_pll_sel);
8935                 /* fall through */
8936         case PORT_CLK_SEL_NONE:
8937                 return;
8938         }
8939
8940         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8941 }
8942
8943 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8944                                      struct intel_crtc_state *pipe_config,
8945                                      u64 *power_domain_mask)
8946 {
8947         struct drm_device *dev = crtc->base.dev;
8948         struct drm_i915_private *dev_priv = to_i915(dev);
8949         enum intel_display_power_domain power_domain;
8950         u32 tmp;
8951
8952         /*
8953          * The pipe->transcoder mapping is fixed with the exception of the eDP
8954          * transcoder handled below.
8955          */
8956         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8957
8958         /*
8959          * XXX: Do intel_display_power_get_if_enabled before reading this (for
8960          * consistency and less surprising code; it's in always on power).
8961          */
8962         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8963         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8964                 enum pipe trans_edp_pipe;
8965                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8966                 default:
8967                         WARN(1, "unknown pipe linked to edp transcoder\n");
8968                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8969                 case TRANS_DDI_EDP_INPUT_A_ON:
8970                         trans_edp_pipe = PIPE_A;
8971                         break;
8972                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8973                         trans_edp_pipe = PIPE_B;
8974                         break;
8975                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8976                         trans_edp_pipe = PIPE_C;
8977                         break;
8978                 }
8979
8980                 if (trans_edp_pipe == crtc->pipe)
8981                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8982         }
8983
8984         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8985         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8986                 return false;
8987         *power_domain_mask |= BIT_ULL(power_domain);
8988
8989         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8990
8991         return tmp & PIPECONF_ENABLE;
8992 }
8993
8994 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8995                                          struct intel_crtc_state *pipe_config,
8996                                          u64 *power_domain_mask)
8997 {
8998         struct drm_device *dev = crtc->base.dev;
8999         struct drm_i915_private *dev_priv = to_i915(dev);
9000         enum intel_display_power_domain power_domain;
9001         enum port port;
9002         enum transcoder cpu_transcoder;
9003         u32 tmp;
9004
9005         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9006                 if (port == PORT_A)
9007                         cpu_transcoder = TRANSCODER_DSI_A;
9008                 else
9009                         cpu_transcoder = TRANSCODER_DSI_C;
9010
9011                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9012                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9013                         continue;
9014                 *power_domain_mask |= BIT_ULL(power_domain);
9015
9016                 /*
9017                  * The PLL needs to be enabled with a valid divider
9018                  * configuration, otherwise accessing DSI registers will hang
9019                  * the machine. See BSpec North Display Engine
9020                  * registers/MIPI[BXT]. We can break out here early, since we
9021                  * need the same DSI PLL to be enabled for both DSI ports.
9022                  */
9023                 if (!intel_dsi_pll_is_enabled(dev_priv))
9024                         break;
9025
9026                 /* XXX: this works for video mode only */
9027                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9028                 if (!(tmp & DPI_ENABLE))
9029                         continue;
9030
9031                 tmp = I915_READ(MIPI_CTRL(port));
9032                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9033                         continue;
9034
9035                 pipe_config->cpu_transcoder = cpu_transcoder;
9036                 break;
9037         }
9038
9039         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9040 }
9041
9042 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9043                                        struct intel_crtc_state *pipe_config)
9044 {
9045         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9046         struct intel_shared_dpll *pll;
9047         enum port port;
9048         uint32_t tmp;
9049
9050         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9051
9052         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9053
9054         if (IS_GEN9_BC(dev_priv))
9055                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9056         else if (IS_GEN9_LP(dev_priv))
9057                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9058         else
9059                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9060
9061         pll = pipe_config->shared_dpll;
9062         if (pll) {
9063                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9064                                                  &pipe_config->dpll_hw_state));
9065         }
9066
9067         /*
9068          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9069          * DDI E. So just check whether this pipe is wired to DDI E and whether
9070          * the PCH transcoder is on.
9071          */
9072         if (INTEL_GEN(dev_priv) < 9 &&
9073             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9074                 pipe_config->has_pch_encoder = true;
9075
9076                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9077                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9078                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9079
9080                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9081         }
9082 }
9083
9084 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9085                                     struct intel_crtc_state *pipe_config)
9086 {
9087         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9088         enum intel_display_power_domain power_domain;
9089         u64 power_domain_mask;
9090         bool active;
9091
9092         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9093         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9094                 return false;
9095         power_domain_mask = BIT_ULL(power_domain);
9096
9097         pipe_config->shared_dpll = NULL;
9098
9099         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9100
9101         if (IS_GEN9_LP(dev_priv) &&
9102             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9103                 WARN_ON(active);
9104                 active = true;
9105         }
9106
9107         if (!active)
9108                 goto out;
9109
9110         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9111                 haswell_get_ddi_port_state(crtc, pipe_config);
9112                 intel_get_pipe_timings(crtc, pipe_config);
9113         }
9114
9115         intel_get_pipe_src_size(crtc, pipe_config);
9116
9117         pipe_config->gamma_mode =
9118                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9119
9120         if (INTEL_GEN(dev_priv) >= 9) {
9121                 intel_crtc_init_scalers(crtc, pipe_config);
9122
9123                 pipe_config->scaler_state.scaler_id = -1;
9124                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9125         }
9126
9127         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9128         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9129                 power_domain_mask |= BIT_ULL(power_domain);
9130                 if (INTEL_GEN(dev_priv) >= 9)
9131                         skylake_get_pfit_config(crtc, pipe_config);
9132                 else
9133                         ironlake_get_pfit_config(crtc, pipe_config);
9134         }
9135
9136         if (IS_HASWELL(dev_priv))
9137                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9138                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9139
9140         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9141             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9142                 pipe_config->pixel_multiplier =
9143                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9144         } else {
9145                 pipe_config->pixel_multiplier = 1;
9146         }
9147
9148 out:
9149         for_each_power_domain(power_domain, power_domain_mask)
9150                 intel_display_power_put(dev_priv, power_domain);
9151
9152         return active;
9153 }
9154
9155 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9156 {
9157         struct drm_i915_private *dev_priv =
9158                 to_i915(plane_state->base.plane->dev);
9159         const struct drm_framebuffer *fb = plane_state->base.fb;
9160         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9161         u32 base;
9162
9163         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9164                 base = obj->phys_handle->busaddr;
9165         else
9166                 base = intel_plane_ggtt_offset(plane_state);
9167
9168         base += plane_state->main.offset;
9169
9170         /* ILK+ do this automagically */
9171         if (HAS_GMCH_DISPLAY(dev_priv) &&
9172             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9173                 base += (plane_state->base.crtc_h *
9174                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9175
9176         return base;
9177 }
9178
9179 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9180 {
9181         int x = plane_state->base.crtc_x;
9182         int y = plane_state->base.crtc_y;
9183         u32 pos = 0;
9184
9185         if (x < 0) {
9186                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9187                 x = -x;
9188         }
9189         pos |= x << CURSOR_X_SHIFT;
9190
9191         if (y < 0) {
9192                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9193                 y = -y;
9194         }
9195         pos |= y << CURSOR_Y_SHIFT;
9196
9197         return pos;
9198 }
9199
9200 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9201 {
9202         const struct drm_mode_config *config =
9203                 &plane_state->base.plane->dev->mode_config;
9204         int width = plane_state->base.crtc_w;
9205         int height = plane_state->base.crtc_h;
9206
9207         return width > 0 && width <= config->cursor_width &&
9208                 height > 0 && height <= config->cursor_height;
9209 }
9210
9211 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9212                               struct intel_plane_state *plane_state)
9213 {
9214         const struct drm_framebuffer *fb = plane_state->base.fb;
9215         int src_x, src_y;
9216         u32 offset;
9217         int ret;
9218
9219         ret = drm_plane_helper_check_state(&plane_state->base,
9220                                            &plane_state->clip,
9221                                            DRM_PLANE_HELPER_NO_SCALING,
9222                                            DRM_PLANE_HELPER_NO_SCALING,
9223                                            true, true);
9224         if (ret)
9225                 return ret;
9226
9227         if (!fb)
9228                 return 0;
9229
9230         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9231                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9232                 return -EINVAL;
9233         }
9234
9235         src_x = plane_state->base.src_x >> 16;
9236         src_y = plane_state->base.src_y >> 16;
9237
9238         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9239         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9240
9241         if (src_x != 0 || src_y != 0) {
9242                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9243                 return -EINVAL;
9244         }
9245
9246         plane_state->main.offset = offset;
9247
9248         return 0;
9249 }
9250
9251 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9252                            const struct intel_plane_state *plane_state)
9253 {
9254         const struct drm_framebuffer *fb = plane_state->base.fb;
9255
9256         return CURSOR_ENABLE |
9257                 CURSOR_GAMMA_ENABLE |
9258                 CURSOR_FORMAT_ARGB |
9259                 CURSOR_STRIDE(fb->pitches[0]);
9260 }
9261
9262 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9263 {
9264         int width = plane_state->base.crtc_w;
9265
9266         /*
9267          * 845g/865g are only limited by the width of their cursors,
9268          * the height is arbitrary up to the precision of the register.
9269          */
9270         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9271 }
9272
9273 static int i845_check_cursor(struct intel_plane *plane,
9274                              struct intel_crtc_state *crtc_state,
9275                              struct intel_plane_state *plane_state)
9276 {
9277         const struct drm_framebuffer *fb = plane_state->base.fb;
9278         int ret;
9279
9280         ret = intel_check_cursor(crtc_state, plane_state);
9281         if (ret)
9282                 return ret;
9283
9284         /* if we want to turn off the cursor ignore width and height */
9285         if (!fb)
9286                 return 0;
9287
9288         /* Check for which cursor types we support */
9289         if (!i845_cursor_size_ok(plane_state)) {
9290                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9291                           plane_state->base.crtc_w,
9292                           plane_state->base.crtc_h);
9293                 return -EINVAL;
9294         }
9295
9296         switch (fb->pitches[0]) {
9297         case 256:
9298         case 512:
9299         case 1024:
9300         case 2048:
9301                 break;
9302         default:
9303                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9304                               fb->pitches[0]);
9305                 return -EINVAL;
9306         }
9307
9308         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9309
9310         return 0;
9311 }
9312
9313 static void i845_update_cursor(struct intel_plane *plane,
9314                                const struct intel_crtc_state *crtc_state,
9315                                const struct intel_plane_state *plane_state)
9316 {
9317         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9318         u32 cntl = 0, base = 0, pos = 0, size = 0;
9319         unsigned long irqflags;
9320
9321         if (plane_state && plane_state->base.visible) {
9322                 unsigned int width = plane_state->base.crtc_w;
9323                 unsigned int height = plane_state->base.crtc_h;
9324
9325                 cntl = plane_state->ctl;
9326                 size = (height << 12) | width;
9327
9328                 base = intel_cursor_base(plane_state);
9329                 pos = intel_cursor_position(plane_state);
9330         }
9331
9332         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9333
9334         /* On these chipsets we can only modify the base/size/stride
9335          * whilst the cursor is disabled.
9336          */
9337         if (plane->cursor.base != base ||
9338             plane->cursor.size != size ||
9339             plane->cursor.cntl != cntl) {
9340                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9341                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9342                 I915_WRITE_FW(CURSIZE, size);
9343                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9344                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9345
9346                 plane->cursor.base = base;
9347                 plane->cursor.size = size;
9348                 plane->cursor.cntl = cntl;
9349         } else {
9350                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9351         }
9352
9353         POSTING_READ_FW(CURCNTR(PIPE_A));
9354
9355         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9356 }
9357
9358 static void i845_disable_cursor(struct intel_plane *plane,
9359                                 struct intel_crtc *crtc)
9360 {
9361         i845_update_cursor(plane, NULL, NULL);
9362 }
9363
9364 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9365                            const struct intel_plane_state *plane_state)
9366 {
9367         struct drm_i915_private *dev_priv =
9368                 to_i915(plane_state->base.plane->dev);
9369         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9370         u32 cntl;
9371
9372         cntl = MCURSOR_GAMMA_ENABLE;
9373
9374         if (HAS_DDI(dev_priv))
9375                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9376
9377         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9378
9379         switch (plane_state->base.crtc_w) {
9380         case 64:
9381                 cntl |= CURSOR_MODE_64_ARGB_AX;
9382                 break;
9383         case 128:
9384                 cntl |= CURSOR_MODE_128_ARGB_AX;
9385                 break;
9386         case 256:
9387                 cntl |= CURSOR_MODE_256_ARGB_AX;
9388                 break;
9389         default:
9390                 MISSING_CASE(plane_state->base.crtc_w);
9391                 return 0;
9392         }
9393
9394         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9395                 cntl |= CURSOR_ROTATE_180;
9396
9397         return cntl;
9398 }
9399
9400 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9401 {
9402         struct drm_i915_private *dev_priv =
9403                 to_i915(plane_state->base.plane->dev);
9404         int width = plane_state->base.crtc_w;
9405         int height = plane_state->base.crtc_h;
9406
9407         if (!intel_cursor_size_ok(plane_state))
9408                 return false;
9409
9410         /* Cursor width is limited to a few power-of-two sizes */
9411         switch (width) {
9412         case 256:
9413         case 128:
9414         case 64:
9415                 break;
9416         default:
9417                 return false;
9418         }
9419
9420         /*
9421          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9422          * height from 8 lines up to the cursor width, when the
9423          * cursor is not rotated. Everything else requires square
9424          * cursors.
9425          */
9426         if (HAS_CUR_FBC(dev_priv) &&
9427             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9428                 if (height < 8 || height > width)
9429                         return false;
9430         } else {
9431                 if (height != width)
9432                         return false;
9433         }
9434
9435         return true;
9436 }
9437
9438 static int i9xx_check_cursor(struct intel_plane *plane,
9439                              struct intel_crtc_state *crtc_state,
9440                              struct intel_plane_state *plane_state)
9441 {
9442         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9443         const struct drm_framebuffer *fb = plane_state->base.fb;
9444         enum pipe pipe = plane->pipe;
9445         int ret;
9446
9447         ret = intel_check_cursor(crtc_state, plane_state);
9448         if (ret)
9449                 return ret;
9450
9451         /* if we want to turn off the cursor ignore width and height */
9452         if (!fb)
9453                 return 0;
9454
9455         /* Check for which cursor types we support */
9456         if (!i9xx_cursor_size_ok(plane_state)) {
9457                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9458                           plane_state->base.crtc_w,
9459                           plane_state->base.crtc_h);
9460                 return -EINVAL;
9461         }
9462
9463         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9464                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9465                               fb->pitches[0], plane_state->base.crtc_w);
9466                 return -EINVAL;
9467         }
9468
9469         /*
9470          * There's something wrong with the cursor on CHV pipe C.
9471          * If it straddles the left edge of the screen then
9472          * moving it away from the edge or disabling it often
9473          * results in a pipe underrun, and often that can lead to
9474          * dead pipe (constant underrun reported, and it scans
9475          * out just a solid color). To recover from that, the
9476          * display power well must be turned off and on again.
9477          * Refuse the put the cursor into that compromised position.
9478          */
9479         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9480             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9481                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9482                 return -EINVAL;
9483         }
9484
9485         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9486
9487         return 0;
9488 }
9489
9490 static void i9xx_update_cursor(struct intel_plane *plane,
9491                                const struct intel_crtc_state *crtc_state,
9492                                const struct intel_plane_state *plane_state)
9493 {
9494         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9495         enum pipe pipe = plane->pipe;
9496         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9497         unsigned long irqflags;
9498
9499         if (plane_state && plane_state->base.visible) {
9500                 cntl = plane_state->ctl;
9501
9502                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9503                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9504
9505                 base = intel_cursor_base(plane_state);
9506                 pos = intel_cursor_position(plane_state);
9507         }
9508
9509         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9510
9511         /*
9512          * On some platforms writing CURCNTR first will also
9513          * cause CURPOS to be armed by the CURBASE write.
9514          * Without the CURCNTR write the CURPOS write would
9515          * arm itself.
9516          *
9517          * CURCNTR and CUR_FBC_CTL are always
9518          * armed by the CURBASE write only.
9519          */
9520         if (plane->cursor.base != base ||
9521             plane->cursor.size != fbc_ctl ||
9522             plane->cursor.cntl != cntl) {
9523                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9524                 if (HAS_CUR_FBC(dev_priv))
9525                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9526                 I915_WRITE_FW(CURPOS(pipe), pos);
9527                 I915_WRITE_FW(CURBASE(pipe), base);
9528
9529                 plane->cursor.base = base;
9530                 plane->cursor.size = fbc_ctl;
9531                 plane->cursor.cntl = cntl;
9532         } else {
9533                 I915_WRITE_FW(CURPOS(pipe), pos);
9534         }
9535
9536         POSTING_READ_FW(CURBASE(pipe));
9537
9538         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9539 }
9540
9541 static void i9xx_disable_cursor(struct intel_plane *plane,
9542                                 struct intel_crtc *crtc)
9543 {
9544         i9xx_update_cursor(plane, NULL, NULL);
9545 }
9546
9547
9548 /* VESA 640x480x72Hz mode to set on the pipe */
9549 static struct drm_display_mode load_detect_mode = {
9550         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9551                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9552 };
9553
9554 struct drm_framebuffer *
9555 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9556                          struct drm_mode_fb_cmd2 *mode_cmd)
9557 {
9558         struct intel_framebuffer *intel_fb;
9559         int ret;
9560
9561         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9562         if (!intel_fb)
9563                 return ERR_PTR(-ENOMEM);
9564
9565         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9566         if (ret)
9567                 goto err;
9568
9569         return &intel_fb->base;
9570
9571 err:
9572         kfree(intel_fb);
9573         return ERR_PTR(ret);
9574 }
9575
9576 static u32
9577 intel_framebuffer_pitch_for_width(int width, int bpp)
9578 {
9579         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9580         return ALIGN(pitch, 64);
9581 }
9582
9583 static u32
9584 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9585 {
9586         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9587         return PAGE_ALIGN(pitch * mode->vdisplay);
9588 }
9589
9590 static struct drm_framebuffer *
9591 intel_framebuffer_create_for_mode(struct drm_device *dev,
9592                                   struct drm_display_mode *mode,
9593                                   int depth, int bpp)
9594 {
9595         struct drm_framebuffer *fb;
9596         struct drm_i915_gem_object *obj;
9597         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9598
9599         obj = i915_gem_object_create(to_i915(dev),
9600                                     intel_framebuffer_size_for_mode(mode, bpp));
9601         if (IS_ERR(obj))
9602                 return ERR_CAST(obj);
9603
9604         mode_cmd.width = mode->hdisplay;
9605         mode_cmd.height = mode->vdisplay;
9606         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9607                                                                 bpp);
9608         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9609
9610         fb = intel_framebuffer_create(obj, &mode_cmd);
9611         if (IS_ERR(fb))
9612                 i915_gem_object_put(obj);
9613
9614         return fb;
9615 }
9616
9617 static struct drm_framebuffer *
9618 mode_fits_in_fbdev(struct drm_device *dev,
9619                    struct drm_display_mode *mode)
9620 {
9621 #ifdef CONFIG_DRM_FBDEV_EMULATION
9622         struct drm_i915_private *dev_priv = to_i915(dev);
9623         struct drm_i915_gem_object *obj;
9624         struct drm_framebuffer *fb;
9625
9626         if (!dev_priv->fbdev)
9627                 return NULL;
9628
9629         if (!dev_priv->fbdev->fb)
9630                 return NULL;
9631
9632         obj = dev_priv->fbdev->fb->obj;
9633         BUG_ON(!obj);
9634
9635         fb = &dev_priv->fbdev->fb->base;
9636         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9637                                                                fb->format->cpp[0] * 8))
9638                 return NULL;
9639
9640         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9641                 return NULL;
9642
9643         drm_framebuffer_reference(fb);
9644         return fb;
9645 #else
9646         return NULL;
9647 #endif
9648 }
9649
9650 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9651                                            struct drm_crtc *crtc,
9652                                            struct drm_display_mode *mode,
9653                                            struct drm_framebuffer *fb,
9654                                            int x, int y)
9655 {
9656         struct drm_plane_state *plane_state;
9657         int hdisplay, vdisplay;
9658         int ret;
9659
9660         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9661         if (IS_ERR(plane_state))
9662                 return PTR_ERR(plane_state);
9663
9664         if (mode)
9665                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9666         else
9667                 hdisplay = vdisplay = 0;
9668
9669         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9670         if (ret)
9671                 return ret;
9672         drm_atomic_set_fb_for_plane(plane_state, fb);
9673         plane_state->crtc_x = 0;
9674         plane_state->crtc_y = 0;
9675         plane_state->crtc_w = hdisplay;
9676         plane_state->crtc_h = vdisplay;
9677         plane_state->src_x = x << 16;
9678         plane_state->src_y = y << 16;
9679         plane_state->src_w = hdisplay << 16;
9680         plane_state->src_h = vdisplay << 16;
9681
9682         return 0;
9683 }
9684
9685 int intel_get_load_detect_pipe(struct drm_connector *connector,
9686                                struct drm_display_mode *mode,
9687                                struct intel_load_detect_pipe *old,
9688                                struct drm_modeset_acquire_ctx *ctx)
9689 {
9690         struct intel_crtc *intel_crtc;
9691         struct intel_encoder *intel_encoder =
9692                 intel_attached_encoder(connector);
9693         struct drm_crtc *possible_crtc;
9694         struct drm_encoder *encoder = &intel_encoder->base;
9695         struct drm_crtc *crtc = NULL;
9696         struct drm_device *dev = encoder->dev;
9697         struct drm_i915_private *dev_priv = to_i915(dev);
9698         struct drm_framebuffer *fb;
9699         struct drm_mode_config *config = &dev->mode_config;
9700         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9701         struct drm_connector_state *connector_state;
9702         struct intel_crtc_state *crtc_state;
9703         int ret, i = -1;
9704
9705         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9706                       connector->base.id, connector->name,
9707                       encoder->base.id, encoder->name);
9708
9709         old->restore_state = NULL;
9710
9711         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9712
9713         /*
9714          * Algorithm gets a little messy:
9715          *
9716          *   - if the connector already has an assigned crtc, use it (but make
9717          *     sure it's on first)
9718          *
9719          *   - try to find the first unused crtc that can drive this connector,
9720          *     and use that if we find one
9721          */
9722
9723         /* See if we already have a CRTC for this connector */
9724         if (connector->state->crtc) {
9725                 crtc = connector->state->crtc;
9726
9727                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9728                 if (ret)
9729                         goto fail;
9730
9731                 /* Make sure the crtc and connector are running */
9732                 goto found;
9733         }
9734
9735         /* Find an unused one (if possible) */
9736         for_each_crtc(dev, possible_crtc) {
9737                 i++;
9738                 if (!(encoder->possible_crtcs & (1 << i)))
9739                         continue;
9740
9741                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9742                 if (ret)
9743                         goto fail;
9744
9745                 if (possible_crtc->state->enable) {
9746                         drm_modeset_unlock(&possible_crtc->mutex);
9747                         continue;
9748                 }
9749
9750                 crtc = possible_crtc;
9751                 break;
9752         }
9753
9754         /*
9755          * If we didn't find an unused CRTC, don't use any.
9756          */
9757         if (!crtc) {
9758                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9759                 ret = -ENODEV;
9760                 goto fail;
9761         }
9762
9763 found:
9764         intel_crtc = to_intel_crtc(crtc);
9765
9766         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9767         if (ret)
9768                 goto fail;
9769
9770         state = drm_atomic_state_alloc(dev);
9771         restore_state = drm_atomic_state_alloc(dev);
9772         if (!state || !restore_state) {
9773                 ret = -ENOMEM;
9774                 goto fail;
9775         }
9776
9777         state->acquire_ctx = ctx;
9778         restore_state->acquire_ctx = ctx;
9779
9780         connector_state = drm_atomic_get_connector_state(state, connector);
9781         if (IS_ERR(connector_state)) {
9782                 ret = PTR_ERR(connector_state);
9783                 goto fail;
9784         }
9785
9786         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9787         if (ret)
9788                 goto fail;
9789
9790         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9791         if (IS_ERR(crtc_state)) {
9792                 ret = PTR_ERR(crtc_state);
9793                 goto fail;
9794         }
9795
9796         crtc_state->base.active = crtc_state->base.enable = true;
9797
9798         if (!mode)
9799                 mode = &load_detect_mode;
9800
9801         /* We need a framebuffer large enough to accommodate all accesses
9802          * that the plane may generate whilst we perform load detection.
9803          * We can not rely on the fbcon either being present (we get called
9804          * during its initialisation to detect all boot displays, or it may
9805          * not even exist) or that it is large enough to satisfy the
9806          * requested mode.
9807          */
9808         fb = mode_fits_in_fbdev(dev, mode);
9809         if (fb == NULL) {
9810                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9811                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9812         } else
9813                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9814         if (IS_ERR(fb)) {
9815                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9816                 ret = PTR_ERR(fb);
9817                 goto fail;
9818         }
9819
9820         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9821         if (ret)
9822                 goto fail;
9823
9824         drm_framebuffer_unreference(fb);
9825
9826         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9827         if (ret)
9828                 goto fail;
9829
9830         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9831         if (!ret)
9832                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9833         if (!ret)
9834                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9835         if (ret) {
9836                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9837                 goto fail;
9838         }
9839
9840         ret = drm_atomic_commit(state);
9841         if (ret) {
9842                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9843                 goto fail;
9844         }
9845
9846         old->restore_state = restore_state;
9847         drm_atomic_state_put(state);
9848
9849         /* let the connector get through one full cycle before testing */
9850         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9851         return true;
9852
9853 fail:
9854         if (state) {
9855                 drm_atomic_state_put(state);
9856                 state = NULL;
9857         }
9858         if (restore_state) {
9859                 drm_atomic_state_put(restore_state);
9860                 restore_state = NULL;
9861         }
9862
9863         if (ret == -EDEADLK)
9864                 return ret;
9865
9866         return false;
9867 }
9868
9869 void intel_release_load_detect_pipe(struct drm_connector *connector,
9870                                     struct intel_load_detect_pipe *old,
9871                                     struct drm_modeset_acquire_ctx *ctx)
9872 {
9873         struct intel_encoder *intel_encoder =
9874                 intel_attached_encoder(connector);
9875         struct drm_encoder *encoder = &intel_encoder->base;
9876         struct drm_atomic_state *state = old->restore_state;
9877         int ret;
9878
9879         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9880                       connector->base.id, connector->name,
9881                       encoder->base.id, encoder->name);
9882
9883         if (!state)
9884                 return;
9885
9886         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9887         if (ret)
9888                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9889         drm_atomic_state_put(state);
9890 }
9891
9892 static int i9xx_pll_refclk(struct drm_device *dev,
9893                            const struct intel_crtc_state *pipe_config)
9894 {
9895         struct drm_i915_private *dev_priv = to_i915(dev);
9896         u32 dpll = pipe_config->dpll_hw_state.dpll;
9897
9898         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9899                 return dev_priv->vbt.lvds_ssc_freq;
9900         else if (HAS_PCH_SPLIT(dev_priv))
9901                 return 120000;
9902         else if (!IS_GEN2(dev_priv))
9903                 return 96000;
9904         else
9905                 return 48000;
9906 }
9907
9908 /* Returns the clock of the currently programmed mode of the given pipe. */
9909 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9910                                 struct intel_crtc_state *pipe_config)
9911 {
9912         struct drm_device *dev = crtc->base.dev;
9913         struct drm_i915_private *dev_priv = to_i915(dev);
9914         int pipe = pipe_config->cpu_transcoder;
9915         u32 dpll = pipe_config->dpll_hw_state.dpll;
9916         u32 fp;
9917         struct dpll clock;
9918         int port_clock;
9919         int refclk = i9xx_pll_refclk(dev, pipe_config);
9920
9921         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9922                 fp = pipe_config->dpll_hw_state.fp0;
9923         else
9924                 fp = pipe_config->dpll_hw_state.fp1;
9925
9926         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9927         if (IS_PINEVIEW(dev_priv)) {
9928                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9929                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9930         } else {
9931                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9932                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9933         }
9934
9935         if (!IS_GEN2(dev_priv)) {
9936                 if (IS_PINEVIEW(dev_priv))
9937                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9938                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9939                 else
9940                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9941                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9942
9943                 switch (dpll & DPLL_MODE_MASK) {
9944                 case DPLLB_MODE_DAC_SERIAL:
9945                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9946                                 5 : 10;
9947                         break;
9948                 case DPLLB_MODE_LVDS:
9949                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9950                                 7 : 14;
9951                         break;
9952                 default:
9953                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9954                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9955                         return;
9956                 }
9957
9958                 if (IS_PINEVIEW(dev_priv))
9959                         port_clock = pnv_calc_dpll_params(refclk, &clock);
9960                 else
9961                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
9962         } else {
9963                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9964                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9965
9966                 if (is_lvds) {
9967                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9968                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9969
9970                         if (lvds & LVDS_CLKB_POWER_UP)
9971                                 clock.p2 = 7;
9972                         else
9973                                 clock.p2 = 14;
9974                 } else {
9975                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9976                                 clock.p1 = 2;
9977                         else {
9978                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9979                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9980                         }
9981                         if (dpll & PLL_P2_DIVIDE_BY_4)
9982                                 clock.p2 = 4;
9983                         else
9984                                 clock.p2 = 2;
9985                 }
9986
9987                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9988         }
9989
9990         /*
9991          * This value includes pixel_multiplier. We will use
9992          * port_clock to compute adjusted_mode.crtc_clock in the
9993          * encoder's get_config() function.
9994          */
9995         pipe_config->port_clock = port_clock;
9996 }
9997
9998 int intel_dotclock_calculate(int link_freq,
9999                              const struct intel_link_m_n *m_n)
10000 {
10001         /*
10002          * The calculation for the data clock is:
10003          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10004          * But we want to avoid losing precison if possible, so:
10005          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10006          *
10007          * and the link clock is simpler:
10008          * link_clock = (m * link_clock) / n
10009          */
10010
10011         if (!m_n->link_n)
10012                 return 0;
10013
10014         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10015 }
10016
10017 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10018                                    struct intel_crtc_state *pipe_config)
10019 {
10020         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10021
10022         /* read out port_clock from the DPLL */
10023         i9xx_crtc_clock_get(crtc, pipe_config);
10024
10025         /*
10026          * In case there is an active pipe without active ports,
10027          * we may need some idea for the dotclock anyway.
10028          * Calculate one based on the FDI configuration.
10029          */
10030         pipe_config->base.adjusted_mode.crtc_clock =
10031                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10032                                          &pipe_config->fdi_m_n);
10033 }
10034
10035 /** Returns the currently programmed mode of the given pipe. */
10036 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10037                                              struct drm_crtc *crtc)
10038 {
10039         struct drm_i915_private *dev_priv = to_i915(dev);
10040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10041         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10042         struct drm_display_mode *mode;
10043         struct intel_crtc_state *pipe_config;
10044         int htot = I915_READ(HTOTAL(cpu_transcoder));
10045         int hsync = I915_READ(HSYNC(cpu_transcoder));
10046         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10047         int vsync = I915_READ(VSYNC(cpu_transcoder));
10048         enum pipe pipe = intel_crtc->pipe;
10049
10050         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10051         if (!mode)
10052                 return NULL;
10053
10054         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10055         if (!pipe_config) {
10056                 kfree(mode);
10057                 return NULL;
10058         }
10059
10060         /*
10061          * Construct a pipe_config sufficient for getting the clock info
10062          * back out of crtc_clock_get.
10063          *
10064          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10065          * to use a real value here instead.
10066          */
10067         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10068         pipe_config->pixel_multiplier = 1;
10069         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10070         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10071         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10072         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10073
10074         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10075         mode->hdisplay = (htot & 0xffff) + 1;
10076         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10077         mode->hsync_start = (hsync & 0xffff) + 1;
10078         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10079         mode->vdisplay = (vtot & 0xffff) + 1;
10080         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10081         mode->vsync_start = (vsync & 0xffff) + 1;
10082         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10083
10084         drm_mode_set_name(mode);
10085
10086         kfree(pipe_config);
10087
10088         return mode;
10089 }
10090
10091 static void intel_crtc_destroy(struct drm_crtc *crtc)
10092 {
10093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10094         struct drm_device *dev = crtc->dev;
10095         struct intel_flip_work *work;
10096
10097         spin_lock_irq(&dev->event_lock);
10098         work = intel_crtc->flip_work;
10099         intel_crtc->flip_work = NULL;
10100         spin_unlock_irq(&dev->event_lock);
10101
10102         if (work) {
10103                 cancel_work_sync(&work->mmio_work);
10104                 cancel_work_sync(&work->unpin_work);
10105                 kfree(work);
10106         }
10107
10108         drm_crtc_cleanup(crtc);
10109
10110         kfree(intel_crtc);
10111 }
10112
10113 static void intel_unpin_work_fn(struct work_struct *__work)
10114 {
10115         struct intel_flip_work *work =
10116                 container_of(__work, struct intel_flip_work, unpin_work);
10117         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10118         struct drm_device *dev = crtc->base.dev;
10119         struct drm_plane *primary = crtc->base.primary;
10120
10121         if (is_mmio_work(work))
10122                 flush_work(&work->mmio_work);
10123
10124         mutex_lock(&dev->struct_mutex);
10125         intel_unpin_fb_vma(work->old_vma);
10126         i915_gem_object_put(work->pending_flip_obj);
10127         mutex_unlock(&dev->struct_mutex);
10128
10129         i915_gem_request_put(work->flip_queued_req);
10130
10131         intel_frontbuffer_flip_complete(to_i915(dev),
10132                                         to_intel_plane(primary)->frontbuffer_bit);
10133         intel_fbc_post_update(crtc);
10134         drm_framebuffer_unreference(work->old_fb);
10135
10136         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10137         atomic_dec(&crtc->unpin_work_count);
10138
10139         kfree(work);
10140 }
10141
10142 /* Is 'a' after or equal to 'b'? */
10143 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10144 {
10145         return !((a - b) & 0x80000000);
10146 }
10147
10148 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10149                                    struct intel_flip_work *work)
10150 {
10151         struct drm_device *dev = crtc->base.dev;
10152         struct drm_i915_private *dev_priv = to_i915(dev);
10153
10154         if (abort_flip_on_reset(crtc))
10155                 return true;
10156
10157         /*
10158          * The relevant registers doen't exist on pre-ctg.
10159          * As the flip done interrupt doesn't trigger for mmio
10160          * flips on gmch platforms, a flip count check isn't
10161          * really needed there. But since ctg has the registers,
10162          * include it in the check anyway.
10163          */
10164         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10165                 return true;
10166
10167         /*
10168          * BDW signals flip done immediately if the plane
10169          * is disabled, even if the plane enable is already
10170          * armed to occur at the next vblank :(
10171          */
10172
10173         /*
10174          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10175          * used the same base address. In that case the mmio flip might
10176          * have completed, but the CS hasn't even executed the flip yet.
10177          *
10178          * A flip count check isn't enough as the CS might have updated
10179          * the base address just after start of vblank, but before we
10180          * managed to process the interrupt. This means we'd complete the
10181          * CS flip too soon.
10182          *
10183          * Combining both checks should get us a good enough result. It may
10184          * still happen that the CS flip has been executed, but has not
10185          * yet actually completed. But in case the base address is the same
10186          * anyway, we don't really care.
10187          */
10188         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10189                 crtc->flip_work->gtt_offset &&
10190                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10191                                     crtc->flip_work->flip_count);
10192 }
10193
10194 static bool
10195 __pageflip_finished_mmio(struct intel_crtc *crtc,
10196                                struct intel_flip_work *work)
10197 {
10198         /*
10199          * MMIO work completes when vblank is different from
10200          * flip_queued_vblank.
10201          *
10202          * Reset counter value doesn't matter, this is handled by
10203          * i915_wait_request finishing early, so no need to handle
10204          * reset here.
10205          */
10206         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10207 }
10208
10209
10210 static bool pageflip_finished(struct intel_crtc *crtc,
10211                               struct intel_flip_work *work)
10212 {
10213         if (!atomic_read(&work->pending))
10214                 return false;
10215
10216         smp_rmb();
10217
10218         if (is_mmio_work(work))
10219                 return __pageflip_finished_mmio(crtc, work);
10220         else
10221                 return __pageflip_finished_cs(crtc, work);
10222 }
10223
10224 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10225 {
10226         struct drm_device *dev = &dev_priv->drm;
10227         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10228         struct intel_flip_work *work;
10229         unsigned long flags;
10230
10231         /* Ignore early vblank irqs */
10232         if (!crtc)
10233                 return;
10234
10235         /*
10236          * This is called both by irq handlers and the reset code (to complete
10237          * lost pageflips) so needs the full irqsave spinlocks.
10238          */
10239         spin_lock_irqsave(&dev->event_lock, flags);
10240         work = crtc->flip_work;
10241
10242         if (work != NULL &&
10243             !is_mmio_work(work) &&
10244             pageflip_finished(crtc, work))
10245                 page_flip_completed(crtc);
10246
10247         spin_unlock_irqrestore(&dev->event_lock, flags);
10248 }
10249
10250 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10251 {
10252         struct drm_device *dev = &dev_priv->drm;
10253         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10254         struct intel_flip_work *work;
10255         unsigned long flags;
10256
10257         /* Ignore early vblank irqs */
10258         if (!crtc)
10259                 return;
10260
10261         /*
10262          * This is called both by irq handlers and the reset code (to complete
10263          * lost pageflips) so needs the full irqsave spinlocks.
10264          */
10265         spin_lock_irqsave(&dev->event_lock, flags);
10266         work = crtc->flip_work;
10267
10268         if (work != NULL &&
10269             is_mmio_work(work) &&
10270             pageflip_finished(crtc, work))
10271                 page_flip_completed(crtc);
10272
10273         spin_unlock_irqrestore(&dev->event_lock, flags);
10274 }
10275
10276 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10277                                                struct intel_flip_work *work)
10278 {
10279         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10280
10281         /* Ensure that the work item is consistent when activating it ... */
10282         smp_mb__before_atomic();
10283         atomic_set(&work->pending, 1);
10284 }
10285
10286 static int intel_gen2_queue_flip(struct drm_device *dev,
10287                                  struct drm_crtc *crtc,
10288                                  struct drm_framebuffer *fb,
10289                                  struct drm_i915_gem_object *obj,
10290                                  struct drm_i915_gem_request *req,
10291                                  uint32_t flags)
10292 {
10293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10294         u32 flip_mask, *cs;
10295
10296         cs = intel_ring_begin(req, 6);
10297         if (IS_ERR(cs))
10298                 return PTR_ERR(cs);
10299
10300         /* Can't queue multiple flips, so wait for the previous
10301          * one to finish before executing the next.
10302          */
10303         if (intel_crtc->plane)
10304                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10305         else
10306                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10307         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10308         *cs++ = MI_NOOP;
10309         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10310         *cs++ = fb->pitches[0];
10311         *cs++ = intel_crtc->flip_work->gtt_offset;
10312         *cs++ = 0; /* aux display base address, unused */
10313
10314         return 0;
10315 }
10316
10317 static int intel_gen3_queue_flip(struct drm_device *dev,
10318                                  struct drm_crtc *crtc,
10319                                  struct drm_framebuffer *fb,
10320                                  struct drm_i915_gem_object *obj,
10321                                  struct drm_i915_gem_request *req,
10322                                  uint32_t flags)
10323 {
10324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10325         u32 flip_mask, *cs;
10326
10327         cs = intel_ring_begin(req, 6);
10328         if (IS_ERR(cs))
10329                 return PTR_ERR(cs);
10330
10331         if (intel_crtc->plane)
10332                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10333         else
10334                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10335         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10336         *cs++ = MI_NOOP;
10337         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10338         *cs++ = fb->pitches[0];
10339         *cs++ = intel_crtc->flip_work->gtt_offset;
10340         *cs++ = MI_NOOP;
10341
10342         return 0;
10343 }
10344
10345 static int intel_gen4_queue_flip(struct drm_device *dev,
10346                                  struct drm_crtc *crtc,
10347                                  struct drm_framebuffer *fb,
10348                                  struct drm_i915_gem_object *obj,
10349                                  struct drm_i915_gem_request *req,
10350                                  uint32_t flags)
10351 {
10352         struct drm_i915_private *dev_priv = to_i915(dev);
10353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10354         u32 pf, pipesrc, *cs;
10355
10356         cs = intel_ring_begin(req, 4);
10357         if (IS_ERR(cs))
10358                 return PTR_ERR(cs);
10359
10360         /* i965+ uses the linear or tiled offsets from the
10361          * Display Registers (which do not change across a page-flip)
10362          * so we need only reprogram the base address.
10363          */
10364         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10365         *cs++ = fb->pitches[0];
10366         *cs++ = intel_crtc->flip_work->gtt_offset |
10367                 intel_fb_modifier_to_tiling(fb->modifier);
10368
10369         /* XXX Enabling the panel-fitter across page-flip is so far
10370          * untested on non-native modes, so ignore it for now.
10371          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10372          */
10373         pf = 0;
10374         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10375         *cs++ = pf | pipesrc;
10376
10377         return 0;
10378 }
10379
10380 static int intel_gen6_queue_flip(struct drm_device *dev,
10381                                  struct drm_crtc *crtc,
10382                                  struct drm_framebuffer *fb,
10383                                  struct drm_i915_gem_object *obj,
10384                                  struct drm_i915_gem_request *req,
10385                                  uint32_t flags)
10386 {
10387         struct drm_i915_private *dev_priv = to_i915(dev);
10388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10389         u32 pf, pipesrc, *cs;
10390
10391         cs = intel_ring_begin(req, 4);
10392         if (IS_ERR(cs))
10393                 return PTR_ERR(cs);
10394
10395         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10396         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10397         *cs++ = intel_crtc->flip_work->gtt_offset;
10398
10399         /* Contrary to the suggestions in the documentation,
10400          * "Enable Panel Fitter" does not seem to be required when page
10401          * flipping with a non-native mode, and worse causes a normal
10402          * modeset to fail.
10403          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10404          */
10405         pf = 0;
10406         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10407         *cs++ = pf | pipesrc;
10408
10409         return 0;
10410 }
10411
10412 static int intel_gen7_queue_flip(struct drm_device *dev,
10413                                  struct drm_crtc *crtc,
10414                                  struct drm_framebuffer *fb,
10415                                  struct drm_i915_gem_object *obj,
10416                                  struct drm_i915_gem_request *req,
10417                                  uint32_t flags)
10418 {
10419         struct drm_i915_private *dev_priv = to_i915(dev);
10420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10421         u32 *cs, plane_bit = 0;
10422         int len, ret;
10423
10424         switch (intel_crtc->plane) {
10425         case PLANE_A:
10426                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10427                 break;
10428         case PLANE_B:
10429                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10430                 break;
10431         case PLANE_C:
10432                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10433                 break;
10434         default:
10435                 WARN_ONCE(1, "unknown plane in flip command\n");
10436                 return -ENODEV;
10437         }
10438
10439         len = 4;
10440         if (req->engine->id == RCS) {
10441                 len += 6;
10442                 /*
10443                  * On Gen 8, SRM is now taking an extra dword to accommodate
10444                  * 48bits addresses, and we need a NOOP for the batch size to
10445                  * stay even.
10446                  */
10447                 if (IS_GEN8(dev_priv))
10448                         len += 2;
10449         }
10450
10451         /*
10452          * BSpec MI_DISPLAY_FLIP for IVB:
10453          * "The full packet must be contained within the same cache line."
10454          *
10455          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10456          * cacheline, if we ever start emitting more commands before
10457          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10458          * then do the cacheline alignment, and finally emit the
10459          * MI_DISPLAY_FLIP.
10460          */
10461         ret = intel_ring_cacheline_align(req);
10462         if (ret)
10463                 return ret;
10464
10465         cs = intel_ring_begin(req, len);
10466         if (IS_ERR(cs))
10467                 return PTR_ERR(cs);
10468
10469         /* Unmask the flip-done completion message. Note that the bspec says that
10470          * we should do this for both the BCS and RCS, and that we must not unmask
10471          * more than one flip event at any time (or ensure that one flip message
10472          * can be sent by waiting for flip-done prior to queueing new flips).
10473          * Experimentation says that BCS works despite DERRMR masking all
10474          * flip-done completion events and that unmasking all planes at once
10475          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10476          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10477          */
10478         if (req->engine->id == RCS) {
10479                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10480                 *cs++ = i915_mmio_reg_offset(DERRMR);
10481                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10482                           DERRMR_PIPEB_PRI_FLIP_DONE |
10483                           DERRMR_PIPEC_PRI_FLIP_DONE);
10484                 if (IS_GEN8(dev_priv))
10485                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10486                                 MI_SRM_LRM_GLOBAL_GTT;
10487                 else
10488                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10489                 *cs++ = i915_mmio_reg_offset(DERRMR);
10490                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10491                 if (IS_GEN8(dev_priv)) {
10492                         *cs++ = 0;
10493                         *cs++ = MI_NOOP;
10494                 }
10495         }
10496
10497         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10498         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10499         *cs++ = intel_crtc->flip_work->gtt_offset;
10500         *cs++ = MI_NOOP;
10501
10502         return 0;
10503 }
10504
10505 static bool use_mmio_flip(struct intel_engine_cs *engine,
10506                           struct drm_i915_gem_object *obj)
10507 {
10508         /*
10509          * This is not being used for older platforms, because
10510          * non-availability of flip done interrupt forces us to use
10511          * CS flips. Older platforms derive flip done using some clever
10512          * tricks involving the flip_pending status bits and vblank irqs.
10513          * So using MMIO flips there would disrupt this mechanism.
10514          */
10515
10516         if (engine == NULL)
10517                 return true;
10518
10519         if (INTEL_GEN(engine->i915) < 5)
10520                 return false;
10521
10522         if (i915.use_mmio_flip < 0)
10523                 return false;
10524         else if (i915.use_mmio_flip > 0)
10525                 return true;
10526         else if (i915.enable_execlists)
10527                 return true;
10528
10529         return engine != i915_gem_object_last_write_engine(obj);
10530 }
10531
10532 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10533                              unsigned int rotation,
10534                              struct intel_flip_work *work)
10535 {
10536         struct drm_device *dev = intel_crtc->base.dev;
10537         struct drm_i915_private *dev_priv = to_i915(dev);
10538         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10539         const enum pipe pipe = intel_crtc->pipe;
10540         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10541
10542         ctl = I915_READ(PLANE_CTL(pipe, 0));
10543         ctl &= ~PLANE_CTL_TILED_MASK;
10544         switch (fb->modifier) {
10545         case DRM_FORMAT_MOD_LINEAR:
10546                 break;
10547         case I915_FORMAT_MOD_X_TILED:
10548                 ctl |= PLANE_CTL_TILED_X;
10549                 break;
10550         case I915_FORMAT_MOD_Y_TILED:
10551                 ctl |= PLANE_CTL_TILED_Y;
10552                 break;
10553         case I915_FORMAT_MOD_Yf_TILED:
10554                 ctl |= PLANE_CTL_TILED_YF;
10555                 break;
10556         default:
10557                 MISSING_CASE(fb->modifier);
10558         }
10559
10560         /*
10561          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10562          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10563          */
10564         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10565         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10566
10567         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10568         POSTING_READ(PLANE_SURF(pipe, 0));
10569 }
10570
10571 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10572                              struct intel_flip_work *work)
10573 {
10574         struct drm_device *dev = intel_crtc->base.dev;
10575         struct drm_i915_private *dev_priv = to_i915(dev);
10576         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10577         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10578         u32 dspcntr;
10579
10580         dspcntr = I915_READ(reg);
10581
10582         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10583                 dspcntr |= DISPPLANE_TILED;
10584         else
10585                 dspcntr &= ~DISPPLANE_TILED;
10586
10587         I915_WRITE(reg, dspcntr);
10588
10589         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10590         POSTING_READ(DSPSURF(intel_crtc->plane));
10591 }
10592
10593 static void intel_mmio_flip_work_func(struct work_struct *w)
10594 {
10595         struct intel_flip_work *work =
10596                 container_of(w, struct intel_flip_work, mmio_work);
10597         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10598         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10599         struct intel_framebuffer *intel_fb =
10600                 to_intel_framebuffer(crtc->base.primary->fb);
10601         struct drm_i915_gem_object *obj = intel_fb->obj;
10602
10603         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10604
10605         intel_pipe_update_start(crtc);
10606
10607         if (INTEL_GEN(dev_priv) >= 9)
10608                 skl_do_mmio_flip(crtc, work->rotation, work);
10609         else
10610                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10611                 ilk_do_mmio_flip(crtc, work);
10612
10613         intel_pipe_update_end(crtc, work);
10614 }
10615
10616 static int intel_default_queue_flip(struct drm_device *dev,
10617                                     struct drm_crtc *crtc,
10618                                     struct drm_framebuffer *fb,
10619                                     struct drm_i915_gem_object *obj,
10620                                     struct drm_i915_gem_request *req,
10621                                     uint32_t flags)
10622 {
10623         return -ENODEV;
10624 }
10625
10626 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10627                                       struct intel_crtc *intel_crtc,
10628                                       struct intel_flip_work *work)
10629 {
10630         u32 addr, vblank;
10631
10632         if (!atomic_read(&work->pending))
10633                 return false;
10634
10635         smp_rmb();
10636
10637         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10638         if (work->flip_ready_vblank == 0) {
10639                 if (work->flip_queued_req &&
10640                     !i915_gem_request_completed(work->flip_queued_req))
10641                         return false;
10642
10643                 work->flip_ready_vblank = vblank;
10644         }
10645
10646         if (vblank - work->flip_ready_vblank < 3)
10647                 return false;
10648
10649         /* Potential stall - if we see that the flip has happened,
10650          * assume a missed interrupt. */
10651         if (INTEL_GEN(dev_priv) >= 4)
10652                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10653         else
10654                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10655
10656         /* There is a potential issue here with a false positive after a flip
10657          * to the same address. We could address this by checking for a
10658          * non-incrementing frame counter.
10659          */
10660         return addr == work->gtt_offset;
10661 }
10662
10663 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10664 {
10665         struct drm_device *dev = &dev_priv->drm;
10666         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10667         struct intel_flip_work *work;
10668
10669         WARN_ON(!in_interrupt());
10670
10671         if (crtc == NULL)
10672                 return;
10673
10674         spin_lock(&dev->event_lock);
10675         work = crtc->flip_work;
10676
10677         if (work != NULL && !is_mmio_work(work) &&
10678             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10679                 WARN_ONCE(1,
10680                           "Kicking stuck page flip: queued at %d, now %d\n",
10681                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10682                 page_flip_completed(crtc);
10683                 work = NULL;
10684         }
10685
10686         if (work != NULL && !is_mmio_work(work) &&
10687             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10688                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10689         spin_unlock(&dev->event_lock);
10690 }
10691
10692 __maybe_unused
10693 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10694                                 struct drm_framebuffer *fb,
10695                                 struct drm_pending_vblank_event *event,
10696                                 uint32_t page_flip_flags)
10697 {
10698         struct drm_device *dev = crtc->dev;
10699         struct drm_i915_private *dev_priv = to_i915(dev);
10700         struct drm_framebuffer *old_fb = crtc->primary->fb;
10701         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10703         struct drm_plane *primary = crtc->primary;
10704         enum pipe pipe = intel_crtc->pipe;
10705         struct intel_flip_work *work;
10706         struct intel_engine_cs *engine;
10707         bool mmio_flip;
10708         struct drm_i915_gem_request *request;
10709         struct i915_vma *vma;
10710         int ret;
10711
10712         /*
10713          * drm_mode_page_flip_ioctl() should already catch this, but double
10714          * check to be safe.  In the future we may enable pageflipping from
10715          * a disabled primary plane.
10716          */
10717         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10718                 return -EBUSY;
10719
10720         /* Can't change pixel format via MI display flips. */
10721         if (fb->format != crtc->primary->fb->format)
10722                 return -EINVAL;
10723
10724         /*
10725          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10726          * Note that pitch changes could also affect these register.
10727          */
10728         if (INTEL_GEN(dev_priv) > 3 &&
10729             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10730              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10731                 return -EINVAL;
10732
10733         if (i915_terminally_wedged(&dev_priv->gpu_error))
10734                 goto out_hang;
10735
10736         work = kzalloc(sizeof(*work), GFP_KERNEL);
10737         if (work == NULL)
10738                 return -ENOMEM;
10739
10740         work->event = event;
10741         work->crtc = crtc;
10742         work->old_fb = old_fb;
10743         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10744
10745         ret = drm_crtc_vblank_get(crtc);
10746         if (ret)
10747                 goto free_work;
10748
10749         /* We borrow the event spin lock for protecting flip_work */
10750         spin_lock_irq(&dev->event_lock);
10751         if (intel_crtc->flip_work) {
10752                 /* Before declaring the flip queue wedged, check if
10753                  * the hardware completed the operation behind our backs.
10754                  */
10755                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10756                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10757                         page_flip_completed(intel_crtc);
10758                 } else {
10759                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10760                         spin_unlock_irq(&dev->event_lock);
10761
10762                         drm_crtc_vblank_put(crtc);
10763                         kfree(work);
10764                         return -EBUSY;
10765                 }
10766         }
10767         intel_crtc->flip_work = work;
10768         spin_unlock_irq(&dev->event_lock);
10769
10770         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10771                 flush_workqueue(dev_priv->wq);
10772
10773         /* Reference the objects for the scheduled work. */
10774         drm_framebuffer_reference(work->old_fb);
10775
10776         crtc->primary->fb = fb;
10777         update_state_fb(crtc->primary);
10778
10779         work->pending_flip_obj = i915_gem_object_get(obj);
10780
10781         ret = i915_mutex_lock_interruptible(dev);
10782         if (ret)
10783                 goto cleanup;
10784
10785         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10786         if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10787                 ret = -EIO;
10788                 goto unlock;
10789         }
10790
10791         atomic_inc(&intel_crtc->unpin_work_count);
10792
10793         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10794                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10795
10796         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10797                 engine = dev_priv->engine[BCS];
10798                 if (fb->modifier != old_fb->modifier)
10799                         /* vlv: DISPLAY_FLIP fails to change tiling */
10800                         engine = NULL;
10801         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10802                 engine = dev_priv->engine[BCS];
10803         } else if (INTEL_GEN(dev_priv) >= 7) {
10804                 engine = i915_gem_object_last_write_engine(obj);
10805                 if (engine == NULL || engine->id != RCS)
10806                         engine = dev_priv->engine[BCS];
10807         } else {
10808                 engine = dev_priv->engine[RCS];
10809         }
10810
10811         mmio_flip = use_mmio_flip(engine, obj);
10812
10813         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10814         if (IS_ERR(vma)) {
10815                 ret = PTR_ERR(vma);
10816                 goto cleanup_pending;
10817         }
10818
10819         work->old_vma = to_intel_plane_state(primary->state)->vma;
10820         to_intel_plane_state(primary->state)->vma = vma;
10821
10822         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10823         work->rotation = crtc->primary->state->rotation;
10824
10825         /*
10826          * There's the potential that the next frame will not be compatible with
10827          * FBC, so we want to call pre_update() before the actual page flip.
10828          * The problem is that pre_update() caches some information about the fb
10829          * object, so we want to do this only after the object is pinned. Let's
10830          * be on the safe side and do this immediately before scheduling the
10831          * flip.
10832          */
10833         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10834                              to_intel_plane_state(primary->state));
10835
10836         if (mmio_flip) {
10837                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10838                 queue_work(system_unbound_wq, &work->mmio_work);
10839         } else {
10840                 request = i915_gem_request_alloc(engine,
10841                                                  dev_priv->kernel_context);
10842                 if (IS_ERR(request)) {
10843                         ret = PTR_ERR(request);
10844                         goto cleanup_unpin;
10845                 }
10846
10847                 ret = i915_gem_request_await_object(request, obj, false);
10848                 if (ret)
10849                         goto cleanup_request;
10850
10851                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10852                                                    page_flip_flags);
10853                 if (ret)
10854                         goto cleanup_request;
10855
10856                 intel_mark_page_flip_active(intel_crtc, work);
10857
10858                 work->flip_queued_req = i915_gem_request_get(request);
10859                 i915_add_request(request);
10860         }
10861
10862         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10863         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10864                           to_intel_plane(primary)->frontbuffer_bit);
10865         mutex_unlock(&dev->struct_mutex);
10866
10867         intel_frontbuffer_flip_prepare(to_i915(dev),
10868                                        to_intel_plane(primary)->frontbuffer_bit);
10869
10870         trace_i915_flip_request(intel_crtc->plane, obj);
10871
10872         return 0;
10873
10874 cleanup_request:
10875         i915_add_request(request);
10876 cleanup_unpin:
10877         to_intel_plane_state(primary->state)->vma = work->old_vma;
10878         intel_unpin_fb_vma(vma);
10879 cleanup_pending:
10880         atomic_dec(&intel_crtc->unpin_work_count);
10881 unlock:
10882         mutex_unlock(&dev->struct_mutex);
10883 cleanup:
10884         crtc->primary->fb = old_fb;
10885         update_state_fb(crtc->primary);
10886
10887         i915_gem_object_put(obj);
10888         drm_framebuffer_unreference(work->old_fb);
10889
10890         spin_lock_irq(&dev->event_lock);
10891         intel_crtc->flip_work = NULL;
10892         spin_unlock_irq(&dev->event_lock);
10893
10894         drm_crtc_vblank_put(crtc);
10895 free_work:
10896         kfree(work);
10897
10898         if (ret == -EIO) {
10899                 struct drm_atomic_state *state;
10900                 struct drm_plane_state *plane_state;
10901
10902 out_hang:
10903                 state = drm_atomic_state_alloc(dev);
10904                 if (!state)
10905                         return -ENOMEM;
10906                 state->acquire_ctx = dev->mode_config.acquire_ctx;
10907
10908 retry:
10909                 plane_state = drm_atomic_get_plane_state(state, primary);
10910                 ret = PTR_ERR_OR_ZERO(plane_state);
10911                 if (!ret) {
10912                         drm_atomic_set_fb_for_plane(plane_state, fb);
10913
10914                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10915                         if (!ret)
10916                                 ret = drm_atomic_commit(state);
10917                 }
10918
10919                 if (ret == -EDEADLK) {
10920                         drm_modeset_backoff(state->acquire_ctx);
10921                         drm_atomic_state_clear(state);
10922                         goto retry;
10923                 }
10924
10925                 drm_atomic_state_put(state);
10926
10927                 if (ret == 0 && event) {
10928                         spin_lock_irq(&dev->event_lock);
10929                         drm_crtc_send_vblank_event(crtc, event);
10930                         spin_unlock_irq(&dev->event_lock);
10931                 }
10932         }
10933         return ret;
10934 }
10935
10936
10937 /**
10938  * intel_wm_need_update - Check whether watermarks need updating
10939  * @plane: drm plane
10940  * @state: new plane state
10941  *
10942  * Check current plane state versus the new one to determine whether
10943  * watermarks need to be recalculated.
10944  *
10945  * Returns true or false.
10946  */
10947 static bool intel_wm_need_update(struct drm_plane *plane,
10948                                  struct drm_plane_state *state)
10949 {
10950         struct intel_plane_state *new = to_intel_plane_state(state);
10951         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10952
10953         /* Update watermarks on tiling or size changes. */
10954         if (new->base.visible != cur->base.visible)
10955                 return true;
10956
10957         if (!cur->base.fb || !new->base.fb)
10958                 return false;
10959
10960         if (cur->base.fb->modifier != new->base.fb->modifier ||
10961             cur->base.rotation != new->base.rotation ||
10962             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10963             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10964             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10965             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10966                 return true;
10967
10968         return false;
10969 }
10970
10971 static bool needs_scaling(struct intel_plane_state *state)
10972 {
10973         int src_w = drm_rect_width(&state->base.src) >> 16;
10974         int src_h = drm_rect_height(&state->base.src) >> 16;
10975         int dst_w = drm_rect_width(&state->base.dst);
10976         int dst_h = drm_rect_height(&state->base.dst);
10977
10978         return (src_w != dst_w || src_h != dst_h);
10979 }
10980
10981 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10982                                     struct drm_plane_state *plane_state)
10983 {
10984         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10985         struct drm_crtc *crtc = crtc_state->crtc;
10986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10987         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10988         struct drm_device *dev = crtc->dev;
10989         struct drm_i915_private *dev_priv = to_i915(dev);
10990         struct intel_plane_state *old_plane_state =
10991                 to_intel_plane_state(plane->base.state);
10992         bool mode_changed = needs_modeset(crtc_state);
10993         bool was_crtc_enabled = crtc->state->active;
10994         bool is_crtc_enabled = crtc_state->active;
10995         bool turn_off, turn_on, visible, was_visible;
10996         struct drm_framebuffer *fb = plane_state->fb;
10997         int ret;
10998
10999         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11000                 ret = skl_update_scaler_plane(
11001                         to_intel_crtc_state(crtc_state),
11002                         to_intel_plane_state(plane_state));
11003                 if (ret)
11004                         return ret;
11005         }
11006
11007         was_visible = old_plane_state->base.visible;
11008         visible = plane_state->visible;
11009
11010         if (!was_crtc_enabled && WARN_ON(was_visible))
11011                 was_visible = false;
11012
11013         /*
11014          * Visibility is calculated as if the crtc was on, but
11015          * after scaler setup everything depends on it being off
11016          * when the crtc isn't active.
11017          *
11018          * FIXME this is wrong for watermarks. Watermarks should also
11019          * be computed as if the pipe would be active. Perhaps move
11020          * per-plane wm computation to the .check_plane() hook, and
11021          * only combine the results from all planes in the current place?
11022          */
11023         if (!is_crtc_enabled) {
11024                 plane_state->visible = visible = false;
11025                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11026         }
11027
11028         if (!was_visible && !visible)
11029                 return 0;
11030
11031         if (fb != old_plane_state->base.fb)
11032                 pipe_config->fb_changed = true;
11033
11034         turn_off = was_visible && (!visible || mode_changed);
11035         turn_on = visible && (!was_visible || mode_changed);
11036
11037         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11038                          intel_crtc->base.base.id, intel_crtc->base.name,
11039                          plane->base.base.id, plane->base.name,
11040                          fb ? fb->base.id : -1);
11041
11042         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11043                          plane->base.base.id, plane->base.name,
11044                          was_visible, visible,
11045                          turn_off, turn_on, mode_changed);
11046
11047         if (turn_on) {
11048                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11049                         pipe_config->update_wm_pre = true;
11050
11051                 /* must disable cxsr around plane enable/disable */
11052                 if (plane->id != PLANE_CURSOR)
11053                         pipe_config->disable_cxsr = true;
11054         } else if (turn_off) {
11055                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11056                         pipe_config->update_wm_post = true;
11057
11058                 /* must disable cxsr around plane enable/disable */
11059                 if (plane->id != PLANE_CURSOR)
11060                         pipe_config->disable_cxsr = true;
11061         } else if (intel_wm_need_update(&plane->base, plane_state)) {
11062                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11063                         /* FIXME bollocks */
11064                         pipe_config->update_wm_pre = true;
11065                         pipe_config->update_wm_post = true;
11066                 }
11067         }
11068
11069         if (visible || was_visible)
11070                 pipe_config->fb_bits |= plane->frontbuffer_bit;
11071
11072         /*
11073          * WaCxSRDisabledForSpriteScaling:ivb
11074          *
11075          * cstate->update_wm was already set above, so this flag will
11076          * take effect when we commit and program watermarks.
11077          */
11078         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
11079             needs_scaling(to_intel_plane_state(plane_state)) &&
11080             !needs_scaling(old_plane_state))
11081                 pipe_config->disable_lp_wm = true;
11082
11083         return 0;
11084 }
11085
11086 static bool encoders_cloneable(const struct intel_encoder *a,
11087                                const struct intel_encoder *b)
11088 {
11089         /* masks could be asymmetric, so check both ways */
11090         return a == b || (a->cloneable & (1 << b->type) &&
11091                           b->cloneable & (1 << a->type));
11092 }
11093
11094 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11095                                          struct intel_crtc *crtc,
11096                                          struct intel_encoder *encoder)
11097 {
11098         struct intel_encoder *source_encoder;
11099         struct drm_connector *connector;
11100         struct drm_connector_state *connector_state;
11101         int i;
11102
11103         for_each_new_connector_in_state(state, connector, connector_state, i) {
11104                 if (connector_state->crtc != &crtc->base)
11105                         continue;
11106
11107                 source_encoder =
11108                         to_intel_encoder(connector_state->best_encoder);
11109                 if (!encoders_cloneable(encoder, source_encoder))
11110                         return false;
11111         }
11112
11113         return true;
11114 }
11115
11116 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11117                                    struct drm_crtc_state *crtc_state)
11118 {
11119         struct drm_device *dev = crtc->dev;
11120         struct drm_i915_private *dev_priv = to_i915(dev);
11121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11122         struct intel_crtc_state *pipe_config =
11123                 to_intel_crtc_state(crtc_state);
11124         struct drm_atomic_state *state = crtc_state->state;
11125         int ret;
11126         bool mode_changed = needs_modeset(crtc_state);
11127
11128         if (mode_changed && !crtc_state->active)
11129                 pipe_config->update_wm_post = true;
11130
11131         if (mode_changed && crtc_state->enable &&
11132             dev_priv->display.crtc_compute_clock &&
11133             !WARN_ON(pipe_config->shared_dpll)) {
11134                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11135                                                            pipe_config);
11136                 if (ret)
11137                         return ret;
11138         }
11139
11140         if (crtc_state->color_mgmt_changed) {
11141                 ret = intel_color_check(crtc, crtc_state);
11142                 if (ret)
11143                         return ret;
11144
11145                 /*
11146                  * Changing color management on Intel hardware is
11147                  * handled as part of planes update.
11148                  */
11149                 crtc_state->planes_changed = true;
11150         }
11151
11152         ret = 0;
11153         if (dev_priv->display.compute_pipe_wm) {
11154                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11155                 if (ret) {
11156                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11157                         return ret;
11158                 }
11159         }
11160
11161         if (dev_priv->display.compute_intermediate_wm &&
11162             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11163                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11164                         return 0;
11165
11166                 /*
11167                  * Calculate 'intermediate' watermarks that satisfy both the
11168                  * old state and the new state.  We can program these
11169                  * immediately.
11170                  */
11171                 ret = dev_priv->display.compute_intermediate_wm(dev,
11172                                                                 intel_crtc,
11173                                                                 pipe_config);
11174                 if (ret) {
11175                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11176                         return ret;
11177                 }
11178         } else if (dev_priv->display.compute_intermediate_wm) {
11179                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11180                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11181         }
11182
11183         if (INTEL_GEN(dev_priv) >= 9) {
11184                 if (mode_changed)
11185                         ret = skl_update_scaler_crtc(pipe_config);
11186
11187                 if (!ret)
11188                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11189                                                          pipe_config);
11190         }
11191
11192         return ret;
11193 }
11194
11195 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11196         .atomic_begin = intel_begin_crtc_commit,
11197         .atomic_flush = intel_finish_crtc_commit,
11198         .atomic_check = intel_crtc_atomic_check,
11199 };
11200
11201 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11202 {
11203         struct intel_connector *connector;
11204         struct drm_connector_list_iter conn_iter;
11205
11206         drm_connector_list_iter_begin(dev, &conn_iter);
11207         for_each_intel_connector_iter(connector, &conn_iter) {
11208                 if (connector->base.state->crtc)
11209                         drm_connector_unreference(&connector->base);
11210
11211                 if (connector->base.encoder) {
11212                         connector->base.state->best_encoder =
11213                                 connector->base.encoder;
11214                         connector->base.state->crtc =
11215                                 connector->base.encoder->crtc;
11216
11217                         drm_connector_reference(&connector->base);
11218                 } else {
11219                         connector->base.state->best_encoder = NULL;
11220                         connector->base.state->crtc = NULL;
11221                 }
11222         }
11223         drm_connector_list_iter_end(&conn_iter);
11224 }
11225
11226 static void
11227 connected_sink_compute_bpp(struct intel_connector *connector,
11228                            struct intel_crtc_state *pipe_config)
11229 {
11230         const struct drm_display_info *info = &connector->base.display_info;
11231         int bpp = pipe_config->pipe_bpp;
11232
11233         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11234                       connector->base.base.id,
11235                       connector->base.name);
11236
11237         /* Don't use an invalid EDID bpc value */
11238         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11239                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11240                               bpp, info->bpc * 3);
11241                 pipe_config->pipe_bpp = info->bpc * 3;
11242         }
11243
11244         /* Clamp bpp to 8 on screens without EDID 1.4 */
11245         if (info->bpc == 0 && bpp > 24) {
11246                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11247                               bpp);
11248                 pipe_config->pipe_bpp = 24;
11249         }
11250 }
11251
11252 static int
11253 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11254                           struct intel_crtc_state *pipe_config)
11255 {
11256         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11257         struct drm_atomic_state *state;
11258         struct drm_connector *connector;
11259         struct drm_connector_state *connector_state;
11260         int bpp, i;
11261
11262         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11263             IS_CHERRYVIEW(dev_priv)))
11264                 bpp = 10*3;
11265         else if (INTEL_GEN(dev_priv) >= 5)
11266                 bpp = 12*3;
11267         else
11268                 bpp = 8*3;
11269
11270
11271         pipe_config->pipe_bpp = bpp;
11272
11273         state = pipe_config->base.state;
11274
11275         /* Clamp display bpp to EDID value */
11276         for_each_new_connector_in_state(state, connector, connector_state, i) {
11277                 if (connector_state->crtc != &crtc->base)
11278                         continue;
11279
11280                 connected_sink_compute_bpp(to_intel_connector(connector),
11281                                            pipe_config);
11282         }
11283
11284         return bpp;
11285 }
11286
11287 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11288 {
11289         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11290                         "type: 0x%x flags: 0x%x\n",
11291                 mode->crtc_clock,
11292                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11293                 mode->crtc_hsync_end, mode->crtc_htotal,
11294                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11295                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11296 }
11297
11298 static inline void
11299 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11300                       unsigned int lane_count, struct intel_link_m_n *m_n)
11301 {
11302         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11303                       id, lane_count,
11304                       m_n->gmch_m, m_n->gmch_n,
11305                       m_n->link_m, m_n->link_n, m_n->tu);
11306 }
11307
11308 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11309                                    struct intel_crtc_state *pipe_config,
11310                                    const char *context)
11311 {
11312         struct drm_device *dev = crtc->base.dev;
11313         struct drm_i915_private *dev_priv = to_i915(dev);
11314         struct drm_plane *plane;
11315         struct intel_plane *intel_plane;
11316         struct intel_plane_state *state;
11317         struct drm_framebuffer *fb;
11318
11319         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11320                       crtc->base.base.id, crtc->base.name, context);
11321
11322         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11323                       transcoder_name(pipe_config->cpu_transcoder),
11324                       pipe_config->pipe_bpp, pipe_config->dither);
11325
11326         if (pipe_config->has_pch_encoder)
11327                 intel_dump_m_n_config(pipe_config, "fdi",
11328                                       pipe_config->fdi_lanes,
11329                                       &pipe_config->fdi_m_n);
11330
11331         if (intel_crtc_has_dp_encoder(pipe_config)) {
11332                 intel_dump_m_n_config(pipe_config, "dp m_n",
11333                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11334                 if (pipe_config->has_drrs)
11335                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11336                                               pipe_config->lane_count,
11337                                               &pipe_config->dp_m2_n2);
11338         }
11339
11340         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11341                       pipe_config->has_audio, pipe_config->has_infoframe);
11342
11343         DRM_DEBUG_KMS("requested mode:\n");
11344         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11345         DRM_DEBUG_KMS("adjusted mode:\n");
11346         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11347         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11348         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11349                       pipe_config->port_clock,
11350                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11351                       pipe_config->pixel_rate);
11352
11353         if (INTEL_GEN(dev_priv) >= 9)
11354                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11355                               crtc->num_scalers,
11356                               pipe_config->scaler_state.scaler_users,
11357                               pipe_config->scaler_state.scaler_id);
11358
11359         if (HAS_GMCH_DISPLAY(dev_priv))
11360                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11361                               pipe_config->gmch_pfit.control,
11362                               pipe_config->gmch_pfit.pgm_ratios,
11363                               pipe_config->gmch_pfit.lvds_border_bits);
11364         else
11365                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11366                               pipe_config->pch_pfit.pos,
11367                               pipe_config->pch_pfit.size,
11368                               enableddisabled(pipe_config->pch_pfit.enabled));
11369
11370         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11371                       pipe_config->ips_enabled, pipe_config->double_wide);
11372
11373         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11374
11375         DRM_DEBUG_KMS("planes on this crtc\n");
11376         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11377                 struct drm_format_name_buf format_name;
11378                 intel_plane = to_intel_plane(plane);
11379                 if (intel_plane->pipe != crtc->pipe)
11380                         continue;
11381
11382                 state = to_intel_plane_state(plane->state);
11383                 fb = state->base.fb;
11384                 if (!fb) {
11385                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11386                                       plane->base.id, plane->name, state->scaler_id);
11387                         continue;
11388                 }
11389
11390                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11391                               plane->base.id, plane->name,
11392                               fb->base.id, fb->width, fb->height,
11393                               drm_get_format_name(fb->format->format, &format_name));
11394                 if (INTEL_GEN(dev_priv) >= 9)
11395                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11396                                       state->scaler_id,
11397                                       state->base.src.x1 >> 16,
11398                                       state->base.src.y1 >> 16,
11399                                       drm_rect_width(&state->base.src) >> 16,
11400                                       drm_rect_height(&state->base.src) >> 16,
11401                                       state->base.dst.x1, state->base.dst.y1,
11402                                       drm_rect_width(&state->base.dst),
11403                                       drm_rect_height(&state->base.dst));
11404         }
11405 }
11406
11407 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11408 {
11409         struct drm_device *dev = state->dev;
11410         struct drm_connector *connector;
11411         struct drm_connector_list_iter conn_iter;
11412         unsigned int used_ports = 0;
11413         unsigned int used_mst_ports = 0;
11414
11415         /*
11416          * Walk the connector list instead of the encoder
11417          * list to detect the problem on ddi platforms
11418          * where there's just one encoder per digital port.
11419          */
11420         drm_connector_list_iter_begin(dev, &conn_iter);
11421         drm_for_each_connector_iter(connector, &conn_iter) {
11422                 struct drm_connector_state *connector_state;
11423                 struct intel_encoder *encoder;
11424
11425                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11426                 if (!connector_state)
11427                         connector_state = connector->state;
11428
11429                 if (!connector_state->best_encoder)
11430                         continue;
11431
11432                 encoder = to_intel_encoder(connector_state->best_encoder);
11433
11434                 WARN_ON(!connector_state->crtc);
11435
11436                 switch (encoder->type) {
11437                         unsigned int port_mask;
11438                 case INTEL_OUTPUT_UNKNOWN:
11439                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11440                                 break;
11441                 case INTEL_OUTPUT_DP:
11442                 case INTEL_OUTPUT_HDMI:
11443                 case INTEL_OUTPUT_EDP:
11444                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11445
11446                         /* the same port mustn't appear more than once */
11447                         if (used_ports & port_mask)
11448                                 return false;
11449
11450                         used_ports |= port_mask;
11451                         break;
11452                 case INTEL_OUTPUT_DP_MST:
11453                         used_mst_ports |=
11454                                 1 << enc_to_mst(&encoder->base)->primary->port;
11455                         break;
11456                 default:
11457                         break;
11458                 }
11459         }
11460         drm_connector_list_iter_end(&conn_iter);
11461
11462         /* can't mix MST and SST/HDMI on the same port */
11463         if (used_ports & used_mst_ports)
11464                 return false;
11465
11466         return true;
11467 }
11468
11469 static void
11470 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11471 {
11472         struct drm_i915_private *dev_priv =
11473                 to_i915(crtc_state->base.crtc->dev);
11474         struct intel_crtc_scaler_state scaler_state;
11475         struct intel_dpll_hw_state dpll_hw_state;
11476         struct intel_shared_dpll *shared_dpll;
11477         struct intel_crtc_wm_state wm_state;
11478         bool force_thru;
11479
11480         /* FIXME: before the switch to atomic started, a new pipe_config was
11481          * kzalloc'd. Code that depends on any field being zero should be
11482          * fixed, so that the crtc_state can be safely duplicated. For now,
11483          * only fields that are know to not cause problems are preserved. */
11484
11485         scaler_state = crtc_state->scaler_state;
11486         shared_dpll = crtc_state->shared_dpll;
11487         dpll_hw_state = crtc_state->dpll_hw_state;
11488         force_thru = crtc_state->pch_pfit.force_thru;
11489         if (IS_G4X(dev_priv) ||
11490             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11491                 wm_state = crtc_state->wm;
11492
11493         /* Keep base drm_crtc_state intact, only clear our extended struct */
11494         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11495         memset(&crtc_state->base + 1, 0,
11496                sizeof(*crtc_state) - sizeof(crtc_state->base));
11497
11498         crtc_state->scaler_state = scaler_state;
11499         crtc_state->shared_dpll = shared_dpll;
11500         crtc_state->dpll_hw_state = dpll_hw_state;
11501         crtc_state->pch_pfit.force_thru = force_thru;
11502         if (IS_G4X(dev_priv) ||
11503             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11504                 crtc_state->wm = wm_state;
11505 }
11506
11507 static int
11508 intel_modeset_pipe_config(struct drm_crtc *crtc,
11509                           struct intel_crtc_state *pipe_config)
11510 {
11511         struct drm_atomic_state *state = pipe_config->base.state;
11512         struct intel_encoder *encoder;
11513         struct drm_connector *connector;
11514         struct drm_connector_state *connector_state;
11515         int base_bpp, ret = -EINVAL;
11516         int i;
11517         bool retry = true;
11518
11519         clear_intel_crtc_state(pipe_config);
11520
11521         pipe_config->cpu_transcoder =
11522                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11523
11524         /*
11525          * Sanitize sync polarity flags based on requested ones. If neither
11526          * positive or negative polarity is requested, treat this as meaning
11527          * negative polarity.
11528          */
11529         if (!(pipe_config->base.adjusted_mode.flags &
11530               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11531                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11532
11533         if (!(pipe_config->base.adjusted_mode.flags &
11534               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11535                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11536
11537         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11538                                              pipe_config);
11539         if (base_bpp < 0)
11540                 goto fail;
11541
11542         /*
11543          * Determine the real pipe dimensions. Note that stereo modes can
11544          * increase the actual pipe size due to the frame doubling and
11545          * insertion of additional space for blanks between the frame. This
11546          * is stored in the crtc timings. We use the requested mode to do this
11547          * computation to clearly distinguish it from the adjusted mode, which
11548          * can be changed by the connectors in the below retry loop.
11549          */
11550         drm_mode_get_hv_timing(&pipe_config->base.mode,
11551                                &pipe_config->pipe_src_w,
11552                                &pipe_config->pipe_src_h);
11553
11554         for_each_new_connector_in_state(state, connector, connector_state, i) {
11555                 if (connector_state->crtc != crtc)
11556                         continue;
11557
11558                 encoder = to_intel_encoder(connector_state->best_encoder);
11559
11560                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11561                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11562                         goto fail;
11563                 }
11564
11565                 /*
11566                  * Determine output_types before calling the .compute_config()
11567                  * hooks so that the hooks can use this information safely.
11568                  */
11569                 pipe_config->output_types |= 1 << encoder->type;
11570         }
11571
11572 encoder_retry:
11573         /* Ensure the port clock defaults are reset when retrying. */
11574         pipe_config->port_clock = 0;
11575         pipe_config->pixel_multiplier = 1;
11576
11577         /* Fill in default crtc timings, allow encoders to overwrite them. */
11578         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11579                               CRTC_STEREO_DOUBLE);
11580
11581         /* Pass our mode to the connectors and the CRTC to give them a chance to
11582          * adjust it according to limitations or connector properties, and also
11583          * a chance to reject the mode entirely.
11584          */
11585         for_each_new_connector_in_state(state, connector, connector_state, i) {
11586                 if (connector_state->crtc != crtc)
11587                         continue;
11588
11589                 encoder = to_intel_encoder(connector_state->best_encoder);
11590
11591                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11592                         DRM_DEBUG_KMS("Encoder config failure\n");
11593                         goto fail;
11594                 }
11595         }
11596
11597         /* Set default port clock if not overwritten by the encoder. Needs to be
11598          * done afterwards in case the encoder adjusts the mode. */
11599         if (!pipe_config->port_clock)
11600                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11601                         * pipe_config->pixel_multiplier;
11602
11603         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11604         if (ret < 0) {
11605                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11606                 goto fail;
11607         }
11608
11609         if (ret == RETRY) {
11610                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11611                         ret = -EINVAL;
11612                         goto fail;
11613                 }
11614
11615                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11616                 retry = false;
11617                 goto encoder_retry;
11618         }
11619
11620         /* Dithering seems to not pass-through bits correctly when it should, so
11621          * only enable it on 6bpc panels and when its not a compliance
11622          * test requesting 6bpc video pattern.
11623          */
11624         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11625                 !pipe_config->dither_force_disable;
11626         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11627                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11628
11629 fail:
11630         return ret;
11631 }
11632
11633 static void
11634 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11635 {
11636         struct drm_crtc *crtc;
11637         struct drm_crtc_state *new_crtc_state;
11638         int i;
11639
11640         /* Double check state. */
11641         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11642                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11643
11644                 /*
11645                  * Update legacy state to satisfy fbc code. This can
11646                  * be removed when fbc uses the atomic state.
11647                  */
11648                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11649                         struct drm_plane_state *plane_state = crtc->primary->state;
11650
11651                         crtc->primary->fb = plane_state->fb;
11652                         crtc->x = plane_state->src_x >> 16;
11653                         crtc->y = plane_state->src_y >> 16;
11654                 }
11655         }
11656 }
11657
11658 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11659 {
11660         int diff;
11661
11662         if (clock1 == clock2)
11663                 return true;
11664
11665         if (!clock1 || !clock2)
11666                 return false;
11667
11668         diff = abs(clock1 - clock2);
11669
11670         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11671                 return true;
11672
11673         return false;
11674 }
11675
11676 static bool
11677 intel_compare_m_n(unsigned int m, unsigned int n,
11678                   unsigned int m2, unsigned int n2,
11679                   bool exact)
11680 {
11681         if (m == m2 && n == n2)
11682                 return true;
11683
11684         if (exact || !m || !n || !m2 || !n2)
11685                 return false;
11686
11687         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11688
11689         if (n > n2) {
11690                 while (n > n2) {
11691                         m2 <<= 1;
11692                         n2 <<= 1;
11693                 }
11694         } else if (n < n2) {
11695                 while (n < n2) {
11696                         m <<= 1;
11697                         n <<= 1;
11698                 }
11699         }
11700
11701         if (n != n2)
11702                 return false;
11703
11704         return intel_fuzzy_clock_check(m, m2);
11705 }
11706
11707 static bool
11708 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11709                        struct intel_link_m_n *m2_n2,
11710                        bool adjust)
11711 {
11712         if (m_n->tu == m2_n2->tu &&
11713             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11714                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11715             intel_compare_m_n(m_n->link_m, m_n->link_n,
11716                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11717                 if (adjust)
11718                         *m2_n2 = *m_n;
11719
11720                 return true;
11721         }
11722
11723         return false;
11724 }
11725
11726 static void __printf(3, 4)
11727 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11728 {
11729         char *level;
11730         unsigned int category;
11731         struct va_format vaf;
11732         va_list args;
11733
11734         if (adjust) {
11735                 level = KERN_DEBUG;
11736                 category = DRM_UT_KMS;
11737         } else {
11738                 level = KERN_ERR;
11739                 category = DRM_UT_NONE;
11740         }
11741
11742         va_start(args, format);
11743         vaf.fmt = format;
11744         vaf.va = &args;
11745
11746         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11747
11748         va_end(args);
11749 }
11750
11751 static bool
11752 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11753                           struct intel_crtc_state *current_config,
11754                           struct intel_crtc_state *pipe_config,
11755                           bool adjust)
11756 {
11757         bool ret = true;
11758
11759 #define PIPE_CONF_CHECK_X(name) \
11760         if (current_config->name != pipe_config->name) { \
11761                 pipe_config_err(adjust, __stringify(name), \
11762                           "(expected 0x%08x, found 0x%08x)\n", \
11763                           current_config->name, \
11764                           pipe_config->name); \
11765                 ret = false; \
11766         }
11767
11768 #define PIPE_CONF_CHECK_I(name) \
11769         if (current_config->name != pipe_config->name) { \
11770                 pipe_config_err(adjust, __stringify(name), \
11771                           "(expected %i, found %i)\n", \
11772                           current_config->name, \
11773                           pipe_config->name); \
11774                 ret = false; \
11775         }
11776
11777 #define PIPE_CONF_CHECK_P(name) \
11778         if (current_config->name != pipe_config->name) { \
11779                 pipe_config_err(adjust, __stringify(name), \
11780                           "(expected %p, found %p)\n", \
11781                           current_config->name, \
11782                           pipe_config->name); \
11783                 ret = false; \
11784         }
11785
11786 #define PIPE_CONF_CHECK_M_N(name) \
11787         if (!intel_compare_link_m_n(&current_config->name, \
11788                                     &pipe_config->name,\
11789                                     adjust)) { \
11790                 pipe_config_err(adjust, __stringify(name), \
11791                           "(expected tu %i gmch %i/%i link %i/%i, " \
11792                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11793                           current_config->name.tu, \
11794                           current_config->name.gmch_m, \
11795                           current_config->name.gmch_n, \
11796                           current_config->name.link_m, \
11797                           current_config->name.link_n, \
11798                           pipe_config->name.tu, \
11799                           pipe_config->name.gmch_m, \
11800                           pipe_config->name.gmch_n, \
11801                           pipe_config->name.link_m, \
11802                           pipe_config->name.link_n); \
11803                 ret = false; \
11804         }
11805
11806 /* This is required for BDW+ where there is only one set of registers for
11807  * switching between high and low RR.
11808  * This macro can be used whenever a comparison has to be made between one
11809  * hw state and multiple sw state variables.
11810  */
11811 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11812         if (!intel_compare_link_m_n(&current_config->name, \
11813                                     &pipe_config->name, adjust) && \
11814             !intel_compare_link_m_n(&current_config->alt_name, \
11815                                     &pipe_config->name, adjust)) { \
11816                 pipe_config_err(adjust, __stringify(name), \
11817                           "(expected tu %i gmch %i/%i link %i/%i, " \
11818                           "or tu %i gmch %i/%i link %i/%i, " \
11819                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11820                           current_config->name.tu, \
11821                           current_config->name.gmch_m, \
11822                           current_config->name.gmch_n, \
11823                           current_config->name.link_m, \
11824                           current_config->name.link_n, \
11825                           current_config->alt_name.tu, \
11826                           current_config->alt_name.gmch_m, \
11827                           current_config->alt_name.gmch_n, \
11828                           current_config->alt_name.link_m, \
11829                           current_config->alt_name.link_n, \
11830                           pipe_config->name.tu, \
11831                           pipe_config->name.gmch_m, \
11832                           pipe_config->name.gmch_n, \
11833                           pipe_config->name.link_m, \
11834                           pipe_config->name.link_n); \
11835                 ret = false; \
11836         }
11837
11838 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11839         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11840                 pipe_config_err(adjust, __stringify(name), \
11841                           "(%x) (expected %i, found %i)\n", \
11842                           (mask), \
11843                           current_config->name & (mask), \
11844                           pipe_config->name & (mask)); \
11845                 ret = false; \
11846         }
11847
11848 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11849         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11850                 pipe_config_err(adjust, __stringify(name), \
11851                           "(expected %i, found %i)\n", \
11852                           current_config->name, \
11853                           pipe_config->name); \
11854                 ret = false; \
11855         }
11856
11857 #define PIPE_CONF_QUIRK(quirk)  \
11858         ((current_config->quirks | pipe_config->quirks) & (quirk))
11859
11860         PIPE_CONF_CHECK_I(cpu_transcoder);
11861
11862         PIPE_CONF_CHECK_I(has_pch_encoder);
11863         PIPE_CONF_CHECK_I(fdi_lanes);
11864         PIPE_CONF_CHECK_M_N(fdi_m_n);
11865
11866         PIPE_CONF_CHECK_I(lane_count);
11867         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11868
11869         if (INTEL_GEN(dev_priv) < 8) {
11870                 PIPE_CONF_CHECK_M_N(dp_m_n);
11871
11872                 if (current_config->has_drrs)
11873                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11874         } else
11875                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11876
11877         PIPE_CONF_CHECK_X(output_types);
11878
11879         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11880         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11881         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11882         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11883         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11884         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11885
11886         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11887         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11888         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11889         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11890         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11891         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11892
11893         PIPE_CONF_CHECK_I(pixel_multiplier);
11894         PIPE_CONF_CHECK_I(has_hdmi_sink);
11895         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11896             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11897                 PIPE_CONF_CHECK_I(limited_color_range);
11898
11899         PIPE_CONF_CHECK_I(hdmi_scrambling);
11900         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11901         PIPE_CONF_CHECK_I(has_infoframe);
11902
11903         PIPE_CONF_CHECK_I(has_audio);
11904
11905         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11906                               DRM_MODE_FLAG_INTERLACE);
11907
11908         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11909                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11910                                       DRM_MODE_FLAG_PHSYNC);
11911                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11912                                       DRM_MODE_FLAG_NHSYNC);
11913                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11914                                       DRM_MODE_FLAG_PVSYNC);
11915                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11916                                       DRM_MODE_FLAG_NVSYNC);
11917         }
11918
11919         PIPE_CONF_CHECK_X(gmch_pfit.control);
11920         /* pfit ratios are autocomputed by the hw on gen4+ */
11921         if (INTEL_GEN(dev_priv) < 4)
11922                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11923         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11924
11925         if (!adjust) {
11926                 PIPE_CONF_CHECK_I(pipe_src_w);
11927                 PIPE_CONF_CHECK_I(pipe_src_h);
11928
11929                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11930                 if (current_config->pch_pfit.enabled) {
11931                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11932                         PIPE_CONF_CHECK_X(pch_pfit.size);
11933                 }
11934
11935                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11936                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11937         }
11938
11939         /* BDW+ don't expose a synchronous way to read the state */
11940         if (IS_HASWELL(dev_priv))
11941                 PIPE_CONF_CHECK_I(ips_enabled);
11942
11943         PIPE_CONF_CHECK_I(double_wide);
11944
11945         PIPE_CONF_CHECK_P(shared_dpll);
11946         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11947         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11948         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11949         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11950         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11951         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11952         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11953         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11954         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11955
11956         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11957         PIPE_CONF_CHECK_X(dsi_pll.div);
11958
11959         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11960                 PIPE_CONF_CHECK_I(pipe_bpp);
11961
11962         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11963         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11964
11965 #undef PIPE_CONF_CHECK_X
11966 #undef PIPE_CONF_CHECK_I
11967 #undef PIPE_CONF_CHECK_P
11968 #undef PIPE_CONF_CHECK_FLAGS
11969 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11970 #undef PIPE_CONF_QUIRK
11971
11972         return ret;
11973 }
11974
11975 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11976                                            const struct intel_crtc_state *pipe_config)
11977 {
11978         if (pipe_config->has_pch_encoder) {
11979                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11980                                                             &pipe_config->fdi_m_n);
11981                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11982
11983                 /*
11984                  * FDI already provided one idea for the dotclock.
11985                  * Yell if the encoder disagrees.
11986                  */
11987                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11988                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11989                      fdi_dotclock, dotclock);
11990         }
11991 }
11992
11993 static void verify_wm_state(struct drm_crtc *crtc,
11994                             struct drm_crtc_state *new_state)
11995 {
11996         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11997         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11998         struct skl_pipe_wm hw_wm, *sw_wm;
11999         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12000         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12002         const enum pipe pipe = intel_crtc->pipe;
12003         int plane, level, max_level = ilk_wm_max_level(dev_priv);
12004
12005         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12006                 return;
12007
12008         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
12009         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12010
12011         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12012         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12013
12014         /* planes */
12015         for_each_universal_plane(dev_priv, pipe, plane) {
12016                 hw_plane_wm = &hw_wm.planes[plane];
12017                 sw_plane_wm = &sw_wm->planes[plane];
12018
12019                 /* Watermarks */
12020                 for (level = 0; level <= max_level; level++) {
12021                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12022                                                 &sw_plane_wm->wm[level]))
12023                                 continue;
12024
12025                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12026                                   pipe_name(pipe), plane + 1, level,
12027                                   sw_plane_wm->wm[level].plane_en,
12028                                   sw_plane_wm->wm[level].plane_res_b,
12029                                   sw_plane_wm->wm[level].plane_res_l,
12030                                   hw_plane_wm->wm[level].plane_en,
12031                                   hw_plane_wm->wm[level].plane_res_b,
12032                                   hw_plane_wm->wm[level].plane_res_l);
12033                 }
12034
12035                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12036                                          &sw_plane_wm->trans_wm)) {
12037                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12038                                   pipe_name(pipe), plane + 1,
12039                                   sw_plane_wm->trans_wm.plane_en,
12040                                   sw_plane_wm->trans_wm.plane_res_b,
12041                                   sw_plane_wm->trans_wm.plane_res_l,
12042                                   hw_plane_wm->trans_wm.plane_en,
12043                                   hw_plane_wm->trans_wm.plane_res_b,
12044                                   hw_plane_wm->trans_wm.plane_res_l);
12045                 }
12046
12047                 /* DDB */
12048                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
12049                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
12050
12051                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12052                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12053                                   pipe_name(pipe), plane + 1,
12054                                   sw_ddb_entry->start, sw_ddb_entry->end,
12055                                   hw_ddb_entry->start, hw_ddb_entry->end);
12056                 }
12057         }
12058
12059         /*
12060          * cursor
12061          * If the cursor plane isn't active, we may not have updated it's ddb
12062          * allocation. In that case since the ddb allocation will be updated
12063          * once the plane becomes visible, we can skip this check
12064          */
12065         if (1) {
12066                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
12067                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12068
12069                 /* Watermarks */
12070                 for (level = 0; level <= max_level; level++) {
12071                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12072                                                 &sw_plane_wm->wm[level]))
12073                                 continue;
12074
12075                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12076                                   pipe_name(pipe), level,
12077                                   sw_plane_wm->wm[level].plane_en,
12078                                   sw_plane_wm->wm[level].plane_res_b,
12079                                   sw_plane_wm->wm[level].plane_res_l,
12080                                   hw_plane_wm->wm[level].plane_en,
12081                                   hw_plane_wm->wm[level].plane_res_b,
12082                                   hw_plane_wm->wm[level].plane_res_l);
12083                 }
12084
12085                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12086                                          &sw_plane_wm->trans_wm)) {
12087                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12088                                   pipe_name(pipe),
12089                                   sw_plane_wm->trans_wm.plane_en,
12090                                   sw_plane_wm->trans_wm.plane_res_b,
12091                                   sw_plane_wm->trans_wm.plane_res_l,
12092                                   hw_plane_wm->trans_wm.plane_en,
12093                                   hw_plane_wm->trans_wm.plane_res_b,
12094                                   hw_plane_wm->trans_wm.plane_res_l);
12095                 }
12096
12097                 /* DDB */
12098                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12099                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12100
12101                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12102                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12103                                   pipe_name(pipe),
12104                                   sw_ddb_entry->start, sw_ddb_entry->end,
12105                                   hw_ddb_entry->start, hw_ddb_entry->end);
12106                 }
12107         }
12108 }
12109
12110 static void
12111 verify_connector_state(struct drm_device *dev,
12112                        struct drm_atomic_state *state,
12113                        struct drm_crtc *crtc)
12114 {
12115         struct drm_connector *connector;
12116         struct drm_connector_state *new_conn_state;
12117         int i;
12118
12119         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12120                 struct drm_encoder *encoder = connector->encoder;
12121                 struct drm_crtc_state *crtc_state = NULL;
12122
12123                 if (new_conn_state->crtc != crtc)
12124                         continue;
12125
12126                 if (crtc)
12127                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12128
12129                 intel_connector_verify_state(crtc_state, new_conn_state);
12130
12131                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12132                      "connector's atomic encoder doesn't match legacy encoder\n");
12133         }
12134 }
12135
12136 static void
12137 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12138 {
12139         struct intel_encoder *encoder;
12140         struct drm_connector *connector;
12141         struct drm_connector_state *old_conn_state, *new_conn_state;
12142         int i;
12143
12144         for_each_intel_encoder(dev, encoder) {
12145                 bool enabled = false, found = false;
12146                 enum pipe pipe;
12147
12148                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12149                               encoder->base.base.id,
12150                               encoder->base.name);
12151
12152                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12153                                                    new_conn_state, i) {
12154                         if (old_conn_state->best_encoder == &encoder->base)
12155                                 found = true;
12156
12157                         if (new_conn_state->best_encoder != &encoder->base)
12158                                 continue;
12159                         found = enabled = true;
12160
12161                         I915_STATE_WARN(new_conn_state->crtc !=
12162                                         encoder->base.crtc,
12163                              "connector's crtc doesn't match encoder crtc\n");
12164                 }
12165
12166                 if (!found)
12167                         continue;
12168
12169                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12170                      "encoder's enabled state mismatch "
12171                      "(expected %i, found %i)\n",
12172                      !!encoder->base.crtc, enabled);
12173
12174                 if (!encoder->base.crtc) {
12175                         bool active;
12176
12177                         active = encoder->get_hw_state(encoder, &pipe);
12178                         I915_STATE_WARN(active,
12179                              "encoder detached but still enabled on pipe %c.\n",
12180                              pipe_name(pipe));
12181                 }
12182         }
12183 }
12184
12185 static void
12186 verify_crtc_state(struct drm_crtc *crtc,
12187                   struct drm_crtc_state *old_crtc_state,
12188                   struct drm_crtc_state *new_crtc_state)
12189 {
12190         struct drm_device *dev = crtc->dev;
12191         struct drm_i915_private *dev_priv = to_i915(dev);
12192         struct intel_encoder *encoder;
12193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12194         struct intel_crtc_state *pipe_config, *sw_config;
12195         struct drm_atomic_state *old_state;
12196         bool active;
12197
12198         old_state = old_crtc_state->state;
12199         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12200         pipe_config = to_intel_crtc_state(old_crtc_state);
12201         memset(pipe_config, 0, sizeof(*pipe_config));
12202         pipe_config->base.crtc = crtc;
12203         pipe_config->base.state = old_state;
12204
12205         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12206
12207         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12208
12209         /* hw state is inconsistent with the pipe quirk */
12210         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12211             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12212                 active = new_crtc_state->active;
12213
12214         I915_STATE_WARN(new_crtc_state->active != active,
12215              "crtc active state doesn't match with hw state "
12216              "(expected %i, found %i)\n", new_crtc_state->active, active);
12217
12218         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12219              "transitional active state does not match atomic hw state "
12220              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12221
12222         for_each_encoder_on_crtc(dev, crtc, encoder) {
12223                 enum pipe pipe;
12224
12225                 active = encoder->get_hw_state(encoder, &pipe);
12226                 I915_STATE_WARN(active != new_crtc_state->active,
12227                         "[ENCODER:%i] active %i with crtc active %i\n",
12228                         encoder->base.base.id, active, new_crtc_state->active);
12229
12230                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12231                                 "Encoder connected to wrong pipe %c\n",
12232                                 pipe_name(pipe));
12233
12234                 if (active) {
12235                         pipe_config->output_types |= 1 << encoder->type;
12236                         encoder->get_config(encoder, pipe_config);
12237                 }
12238         }
12239
12240         intel_crtc_compute_pixel_rate(pipe_config);
12241
12242         if (!new_crtc_state->active)
12243                 return;
12244
12245         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12246
12247         sw_config = to_intel_crtc_state(new_crtc_state);
12248         if (!intel_pipe_config_compare(dev_priv, sw_config,
12249                                        pipe_config, false)) {
12250                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12251                 intel_dump_pipe_config(intel_crtc, pipe_config,
12252                                        "[hw state]");
12253                 intel_dump_pipe_config(intel_crtc, sw_config,
12254                                        "[sw state]");
12255         }
12256 }
12257
12258 static void
12259 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12260                          struct intel_shared_dpll *pll,
12261                          struct drm_crtc *crtc,
12262                          struct drm_crtc_state *new_state)
12263 {
12264         struct intel_dpll_hw_state dpll_hw_state;
12265         unsigned crtc_mask;
12266         bool active;
12267
12268         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12269
12270         DRM_DEBUG_KMS("%s\n", pll->name);
12271
12272         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12273
12274         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12275                 I915_STATE_WARN(!pll->on && pll->active_mask,
12276                      "pll in active use but not on in sw tracking\n");
12277                 I915_STATE_WARN(pll->on && !pll->active_mask,
12278                      "pll is on but not used by any active crtc\n");
12279                 I915_STATE_WARN(pll->on != active,
12280                      "pll on state mismatch (expected %i, found %i)\n",
12281                      pll->on, active);
12282         }
12283
12284         if (!crtc) {
12285                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12286                                 "more active pll users than references: %x vs %x\n",
12287                                 pll->active_mask, pll->state.crtc_mask);
12288
12289                 return;
12290         }
12291
12292         crtc_mask = 1 << drm_crtc_index(crtc);
12293
12294         if (new_state->active)
12295                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12296                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12297                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12298         else
12299                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12300                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12301                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12302
12303         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12304                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12305                         crtc_mask, pll->state.crtc_mask);
12306
12307         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12308                                           &dpll_hw_state,
12309                                           sizeof(dpll_hw_state)),
12310                         "pll hw state mismatch\n");
12311 }
12312
12313 static void
12314 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12315                          struct drm_crtc_state *old_crtc_state,
12316                          struct drm_crtc_state *new_crtc_state)
12317 {
12318         struct drm_i915_private *dev_priv = to_i915(dev);
12319         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12320         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12321
12322         if (new_state->shared_dpll)
12323                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12324
12325         if (old_state->shared_dpll &&
12326             old_state->shared_dpll != new_state->shared_dpll) {
12327                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12328                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12329
12330                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12331                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12332                                 pipe_name(drm_crtc_index(crtc)));
12333                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12334                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12335                                 pipe_name(drm_crtc_index(crtc)));
12336         }
12337 }
12338
12339 static void
12340 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12341                           struct drm_atomic_state *state,
12342                           struct drm_crtc_state *old_state,
12343                           struct drm_crtc_state *new_state)
12344 {
12345         if (!needs_modeset(new_state) &&
12346             !to_intel_crtc_state(new_state)->update_pipe)
12347                 return;
12348
12349         verify_wm_state(crtc, new_state);
12350         verify_connector_state(crtc->dev, state, crtc);
12351         verify_crtc_state(crtc, old_state, new_state);
12352         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12353 }
12354
12355 static void
12356 verify_disabled_dpll_state(struct drm_device *dev)
12357 {
12358         struct drm_i915_private *dev_priv = to_i915(dev);
12359         int i;
12360
12361         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12362                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12363 }
12364
12365 static void
12366 intel_modeset_verify_disabled(struct drm_device *dev,
12367                               struct drm_atomic_state *state)
12368 {
12369         verify_encoder_state(dev, state);
12370         verify_connector_state(dev, state, NULL);
12371         verify_disabled_dpll_state(dev);
12372 }
12373
12374 static void update_scanline_offset(struct intel_crtc *crtc)
12375 {
12376         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12377
12378         /*
12379          * The scanline counter increments at the leading edge of hsync.
12380          *
12381          * On most platforms it starts counting from vtotal-1 on the
12382          * first active line. That means the scanline counter value is
12383          * always one less than what we would expect. Ie. just after
12384          * start of vblank, which also occurs at start of hsync (on the
12385          * last active line), the scanline counter will read vblank_start-1.
12386          *
12387          * On gen2 the scanline counter starts counting from 1 instead
12388          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12389          * to keep the value positive), instead of adding one.
12390          *
12391          * On HSW+ the behaviour of the scanline counter depends on the output
12392          * type. For DP ports it behaves like most other platforms, but on HDMI
12393          * there's an extra 1 line difference. So we need to add two instead of
12394          * one to the value.
12395          *
12396          * On VLV/CHV DSI the scanline counter would appear to increment
12397          * approx. 1/3 of a scanline before start of vblank. Unfortunately
12398          * that means we can't tell whether we're in vblank or not while
12399          * we're on that particular line. We must still set scanline_offset
12400          * to 1 so that the vblank timestamps come out correct when we query
12401          * the scanline counter from within the vblank interrupt handler.
12402          * However if queried just before the start of vblank we'll get an
12403          * answer that's slightly in the future.
12404          */
12405         if (IS_GEN2(dev_priv)) {
12406                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12407                 int vtotal;
12408
12409                 vtotal = adjusted_mode->crtc_vtotal;
12410                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12411                         vtotal /= 2;
12412
12413                 crtc->scanline_offset = vtotal - 1;
12414         } else if (HAS_DDI(dev_priv) &&
12415                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12416                 crtc->scanline_offset = 2;
12417         } else
12418                 crtc->scanline_offset = 1;
12419 }
12420
12421 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12422 {
12423         struct drm_device *dev = state->dev;
12424         struct drm_i915_private *dev_priv = to_i915(dev);
12425         struct drm_crtc *crtc;
12426         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12427         int i;
12428
12429         if (!dev_priv->display.crtc_compute_clock)
12430                 return;
12431
12432         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12433                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12434                 struct intel_shared_dpll *old_dpll =
12435                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12436
12437                 if (!needs_modeset(new_crtc_state))
12438                         continue;
12439
12440                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12441
12442                 if (!old_dpll)
12443                         continue;
12444
12445                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12446         }
12447 }
12448
12449 /*
12450  * This implements the workaround described in the "notes" section of the mode
12451  * set sequence documentation. When going from no pipes or single pipe to
12452  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12453  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12454  */
12455 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12456 {
12457         struct drm_crtc_state *crtc_state;
12458         struct intel_crtc *intel_crtc;
12459         struct drm_crtc *crtc;
12460         struct intel_crtc_state *first_crtc_state = NULL;
12461         struct intel_crtc_state *other_crtc_state = NULL;
12462         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12463         int i;
12464
12465         /* look at all crtc's that are going to be enabled in during modeset */
12466         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12467                 intel_crtc = to_intel_crtc(crtc);
12468
12469                 if (!crtc_state->active || !needs_modeset(crtc_state))
12470                         continue;
12471
12472                 if (first_crtc_state) {
12473                         other_crtc_state = to_intel_crtc_state(crtc_state);
12474                         break;
12475                 } else {
12476                         first_crtc_state = to_intel_crtc_state(crtc_state);
12477                         first_pipe = intel_crtc->pipe;
12478                 }
12479         }
12480
12481         /* No workaround needed? */
12482         if (!first_crtc_state)
12483                 return 0;
12484
12485         /* w/a possibly needed, check how many crtc's are already enabled. */
12486         for_each_intel_crtc(state->dev, intel_crtc) {
12487                 struct intel_crtc_state *pipe_config;
12488
12489                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12490                 if (IS_ERR(pipe_config))
12491                         return PTR_ERR(pipe_config);
12492
12493                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12494
12495                 if (!pipe_config->base.active ||
12496                     needs_modeset(&pipe_config->base))
12497                         continue;
12498
12499                 /* 2 or more enabled crtcs means no need for w/a */
12500                 if (enabled_pipe != INVALID_PIPE)
12501                         return 0;
12502
12503                 enabled_pipe = intel_crtc->pipe;
12504         }
12505
12506         if (enabled_pipe != INVALID_PIPE)
12507                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12508         else if (other_crtc_state)
12509                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12510
12511         return 0;
12512 }
12513
12514 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12515 {
12516         struct drm_crtc *crtc;
12517
12518         /* Add all pipes to the state */
12519         for_each_crtc(state->dev, crtc) {
12520                 struct drm_crtc_state *crtc_state;
12521
12522                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12523                 if (IS_ERR(crtc_state))
12524                         return PTR_ERR(crtc_state);
12525         }
12526
12527         return 0;
12528 }
12529
12530 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12531 {
12532         struct drm_crtc *crtc;
12533
12534         /*
12535          * Add all pipes to the state, and force
12536          * a modeset on all the active ones.
12537          */
12538         for_each_crtc(state->dev, crtc) {
12539                 struct drm_crtc_state *crtc_state;
12540                 int ret;
12541
12542                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12543                 if (IS_ERR(crtc_state))
12544                         return PTR_ERR(crtc_state);
12545
12546                 if (!crtc_state->active || needs_modeset(crtc_state))
12547                         continue;
12548
12549                 crtc_state->mode_changed = true;
12550
12551                 ret = drm_atomic_add_affected_connectors(state, crtc);
12552                 if (ret)
12553                         return ret;
12554
12555                 ret = drm_atomic_add_affected_planes(state, crtc);
12556                 if (ret)
12557                         return ret;
12558         }
12559
12560         return 0;
12561 }
12562
12563 static int intel_modeset_checks(struct drm_atomic_state *state)
12564 {
12565         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12566         struct drm_i915_private *dev_priv = to_i915(state->dev);
12567         struct drm_crtc *crtc;
12568         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12569         int ret = 0, i;
12570
12571         if (!check_digital_port_conflicts(state)) {
12572                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12573                 return -EINVAL;
12574         }
12575
12576         intel_state->modeset = true;
12577         intel_state->active_crtcs = dev_priv->active_crtcs;
12578         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12579         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12580
12581         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12582                 if (new_crtc_state->active)
12583                         intel_state->active_crtcs |= 1 << i;
12584                 else
12585                         intel_state->active_crtcs &= ~(1 << i);
12586
12587                 if (old_crtc_state->active != new_crtc_state->active)
12588                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12589         }
12590
12591         /*
12592          * See if the config requires any additional preparation, e.g.
12593          * to adjust global state with pipes off.  We need to do this
12594          * here so we can get the modeset_pipe updated config for the new
12595          * mode set on this crtc.  For other crtcs we need to use the
12596          * adjusted_mode bits in the crtc directly.
12597          */
12598         if (dev_priv->display.modeset_calc_cdclk) {
12599                 ret = dev_priv->display.modeset_calc_cdclk(state);
12600                 if (ret < 0)
12601                         return ret;
12602
12603                 /*
12604                  * Writes to dev_priv->cdclk.logical must protected by
12605                  * holding all the crtc locks, even if we don't end up
12606                  * touching the hardware
12607                  */
12608                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12609                                                &intel_state->cdclk.logical)) {
12610                         ret = intel_lock_all_pipes(state);
12611                         if (ret < 0)
12612                                 return ret;
12613                 }
12614
12615                 /* All pipes must be switched off while we change the cdclk. */
12616                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12617                                                &intel_state->cdclk.actual)) {
12618                         ret = intel_modeset_all_pipes(state);
12619                         if (ret < 0)
12620                                 return ret;
12621                 }
12622
12623                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12624                               intel_state->cdclk.logical.cdclk,
12625                               intel_state->cdclk.actual.cdclk);
12626         } else {
12627                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12628         }
12629
12630         intel_modeset_clear_plls(state);
12631
12632         if (IS_HASWELL(dev_priv))
12633                 return haswell_mode_set_planes_workaround(state);
12634
12635         return 0;
12636 }
12637
12638 /*
12639  * Handle calculation of various watermark data at the end of the atomic check
12640  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12641  * handlers to ensure that all derived state has been updated.
12642  */
12643 static int calc_watermark_data(struct drm_atomic_state *state)
12644 {
12645         struct drm_device *dev = state->dev;
12646         struct drm_i915_private *dev_priv = to_i915(dev);
12647
12648         /* Is there platform-specific watermark information to calculate? */
12649         if (dev_priv->display.compute_global_watermarks)
12650                 return dev_priv->display.compute_global_watermarks(state);
12651
12652         return 0;
12653 }
12654
12655 /**
12656  * intel_atomic_check - validate state object
12657  * @dev: drm device
12658  * @state: state to validate
12659  */
12660 static int intel_atomic_check(struct drm_device *dev,
12661                               struct drm_atomic_state *state)
12662 {
12663         struct drm_i915_private *dev_priv = to_i915(dev);
12664         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12665         struct drm_crtc *crtc;
12666         struct drm_crtc_state *old_crtc_state, *crtc_state;
12667         int ret, i;
12668         bool any_ms = false;
12669
12670         ret = drm_atomic_helper_check_modeset(dev, state);
12671         if (ret)
12672                 return ret;
12673
12674         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12675                 struct intel_crtc_state *pipe_config =
12676                         to_intel_crtc_state(crtc_state);
12677
12678                 /* Catch I915_MODE_FLAG_INHERITED */
12679                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12680                         crtc_state->mode_changed = true;
12681
12682                 if (!needs_modeset(crtc_state))
12683                         continue;
12684
12685                 if (!crtc_state->enable) {
12686                         any_ms = true;
12687                         continue;
12688                 }
12689
12690                 /* FIXME: For only active_changed we shouldn't need to do any
12691                  * state recomputation at all. */
12692
12693                 ret = drm_atomic_add_affected_connectors(state, crtc);
12694                 if (ret)
12695                         return ret;
12696
12697                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12698                 if (ret) {
12699                         intel_dump_pipe_config(to_intel_crtc(crtc),
12700                                                pipe_config, "[failed]");
12701                         return ret;
12702                 }
12703
12704                 if (i915.fastboot &&
12705                     intel_pipe_config_compare(dev_priv,
12706                                         to_intel_crtc_state(old_crtc_state),
12707                                         pipe_config, true)) {
12708                         crtc_state->mode_changed = false;
12709                         pipe_config->update_pipe = true;
12710                 }
12711
12712                 if (needs_modeset(crtc_state))
12713                         any_ms = true;
12714
12715                 ret = drm_atomic_add_affected_planes(state, crtc);
12716                 if (ret)
12717                         return ret;
12718
12719                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12720                                        needs_modeset(crtc_state) ?
12721                                        "[modeset]" : "[fastset]");
12722         }
12723
12724         if (any_ms) {
12725                 ret = intel_modeset_checks(state);
12726
12727                 if (ret)
12728                         return ret;
12729         } else {
12730                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12731         }
12732
12733         ret = drm_atomic_helper_check_planes(dev, state);
12734         if (ret)
12735                 return ret;
12736
12737         intel_fbc_choose_crtc(dev_priv, state);
12738         return calc_watermark_data(state);
12739 }
12740
12741 static int intel_atomic_prepare_commit(struct drm_device *dev,
12742                                        struct drm_atomic_state *state)
12743 {
12744         struct drm_i915_private *dev_priv = to_i915(dev);
12745         struct drm_crtc_state *crtc_state;
12746         struct drm_crtc *crtc;
12747         int i, ret;
12748
12749         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12750                 if (state->legacy_cursor_update)
12751                         continue;
12752
12753                 ret = intel_crtc_wait_for_pending_flips(crtc);
12754                 if (ret)
12755                         return ret;
12756
12757                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12758                         flush_workqueue(dev_priv->wq);
12759         }
12760
12761         ret = mutex_lock_interruptible(&dev->struct_mutex);
12762         if (ret)
12763                 return ret;
12764
12765         ret = drm_atomic_helper_prepare_planes(dev, state);
12766         mutex_unlock(&dev->struct_mutex);
12767
12768         return ret;
12769 }
12770
12771 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12772 {
12773         struct drm_device *dev = crtc->base.dev;
12774
12775         if (!dev->max_vblank_count)
12776                 return drm_accurate_vblank_count(&crtc->base);
12777
12778         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12779 }
12780
12781 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12782                                           struct drm_i915_private *dev_priv,
12783                                           unsigned crtc_mask)
12784 {
12785         unsigned last_vblank_count[I915_MAX_PIPES];
12786         enum pipe pipe;
12787         int ret;
12788
12789         if (!crtc_mask)
12790                 return;
12791
12792         for_each_pipe(dev_priv, pipe) {
12793                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12794                                                                   pipe);
12795
12796                 if (!((1 << pipe) & crtc_mask))
12797                         continue;
12798
12799                 ret = drm_crtc_vblank_get(&crtc->base);
12800                 if (WARN_ON(ret != 0)) {
12801                         crtc_mask &= ~(1 << pipe);
12802                         continue;
12803                 }
12804
12805                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12806         }
12807
12808         for_each_pipe(dev_priv, pipe) {
12809                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12810                                                                   pipe);
12811                 long lret;
12812
12813                 if (!((1 << pipe) & crtc_mask))
12814                         continue;
12815
12816                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12817                                 last_vblank_count[pipe] !=
12818                                         drm_crtc_vblank_count(&crtc->base),
12819                                 msecs_to_jiffies(50));
12820
12821                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12822
12823                 drm_crtc_vblank_put(&crtc->base);
12824         }
12825 }
12826
12827 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12828 {
12829         /* fb updated, need to unpin old fb */
12830         if (crtc_state->fb_changed)
12831                 return true;
12832
12833         /* wm changes, need vblank before final wm's */
12834         if (crtc_state->update_wm_post)
12835                 return true;
12836
12837         if (crtc_state->wm.need_postvbl_update)
12838                 return true;
12839
12840         return false;
12841 }
12842
12843 static void intel_update_crtc(struct drm_crtc *crtc,
12844                               struct drm_atomic_state *state,
12845                               struct drm_crtc_state *old_crtc_state,
12846                               struct drm_crtc_state *new_crtc_state,
12847                               unsigned int *crtc_vblank_mask)
12848 {
12849         struct drm_device *dev = crtc->dev;
12850         struct drm_i915_private *dev_priv = to_i915(dev);
12851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12852         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12853         bool modeset = needs_modeset(new_crtc_state);
12854
12855         if (modeset) {
12856                 update_scanline_offset(intel_crtc);
12857                 dev_priv->display.crtc_enable(pipe_config, state);
12858         } else {
12859                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12860                                        pipe_config);
12861         }
12862
12863         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12864                 intel_fbc_enable(
12865                     intel_crtc, pipe_config,
12866                     to_intel_plane_state(crtc->primary->state));
12867         }
12868
12869         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12870
12871         if (needs_vblank_wait(pipe_config))
12872                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12873 }
12874
12875 static void intel_update_crtcs(struct drm_atomic_state *state,
12876                                unsigned int *crtc_vblank_mask)
12877 {
12878         struct drm_crtc *crtc;
12879         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12880         int i;
12881
12882         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12883                 if (!new_crtc_state->active)
12884                         continue;
12885
12886                 intel_update_crtc(crtc, state, old_crtc_state,
12887                                   new_crtc_state, crtc_vblank_mask);
12888         }
12889 }
12890
12891 static void skl_update_crtcs(struct drm_atomic_state *state,
12892                              unsigned int *crtc_vblank_mask)
12893 {
12894         struct drm_i915_private *dev_priv = to_i915(state->dev);
12895         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12896         struct drm_crtc *crtc;
12897         struct intel_crtc *intel_crtc;
12898         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12899         struct intel_crtc_state *cstate;
12900         unsigned int updated = 0;
12901         bool progress;
12902         enum pipe pipe;
12903         int i;
12904
12905         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12906
12907         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12908                 /* ignore allocations for crtc's that have been turned off. */
12909                 if (new_crtc_state->active)
12910                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12911
12912         /*
12913          * Whenever the number of active pipes changes, we need to make sure we
12914          * update the pipes in the right order so that their ddb allocations
12915          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12916          * cause pipe underruns and other bad stuff.
12917          */
12918         do {
12919                 progress = false;
12920
12921                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12922                         bool vbl_wait = false;
12923                         unsigned int cmask = drm_crtc_mask(crtc);
12924
12925                         intel_crtc = to_intel_crtc(crtc);
12926                         cstate = to_intel_crtc_state(crtc->state);
12927                         pipe = intel_crtc->pipe;
12928
12929                         if (updated & cmask || !cstate->base.active)
12930                                 continue;
12931
12932                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12933                                 continue;
12934
12935                         updated |= cmask;
12936                         entries[i] = &cstate->wm.skl.ddb;
12937
12938                         /*
12939                          * If this is an already active pipe, it's DDB changed,
12940                          * and this isn't the last pipe that needs updating
12941                          * then we need to wait for a vblank to pass for the
12942                          * new ddb allocation to take effect.
12943                          */
12944                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12945                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12946                             !new_crtc_state->active_changed &&
12947                             intel_state->wm_results.dirty_pipes != updated)
12948                                 vbl_wait = true;
12949
12950                         intel_update_crtc(crtc, state, old_crtc_state,
12951                                           new_crtc_state, crtc_vblank_mask);
12952
12953                         if (vbl_wait)
12954                                 intel_wait_for_vblank(dev_priv, pipe);
12955
12956                         progress = true;
12957                 }
12958         } while (progress);
12959 }
12960
12961 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12962 {
12963         struct intel_atomic_state *state, *next;
12964         struct llist_node *freed;
12965
12966         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12967         llist_for_each_entry_safe(state, next, freed, freed)
12968                 drm_atomic_state_put(&state->base);
12969 }
12970
12971 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12972 {
12973         struct drm_i915_private *dev_priv =
12974                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12975
12976         intel_atomic_helper_free_state(dev_priv);
12977 }
12978
12979 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12980 {
12981         struct drm_device *dev = state->dev;
12982         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12983         struct drm_i915_private *dev_priv = to_i915(dev);
12984         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12985         struct drm_crtc *crtc;
12986         struct intel_crtc_state *intel_cstate;
12987         bool hw_check = intel_state->modeset;
12988         u64 put_domains[I915_MAX_PIPES] = {};
12989         unsigned crtc_vblank_mask = 0;
12990         int i;
12991
12992         drm_atomic_helper_wait_for_dependencies(state);
12993
12994         if (intel_state->modeset)
12995                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12996
12997         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12998                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12999
13000                 if (needs_modeset(new_crtc_state) ||
13001                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
13002                         hw_check = true;
13003
13004                         put_domains[to_intel_crtc(crtc)->pipe] =
13005                                 modeset_get_crtc_power_domains(crtc,
13006                                         to_intel_crtc_state(new_crtc_state));
13007                 }
13008
13009                 if (!needs_modeset(new_crtc_state))
13010                         continue;
13011
13012                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
13013                                        to_intel_crtc_state(new_crtc_state));
13014
13015                 if (old_crtc_state->active) {
13016                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13017                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
13018                         intel_crtc->active = false;
13019                         intel_fbc_disable(intel_crtc);
13020                         intel_disable_shared_dpll(intel_crtc);
13021
13022                         /*
13023                          * Underruns don't always raise
13024                          * interrupts, so check manually.
13025                          */
13026                         intel_check_cpu_fifo_underruns(dev_priv);
13027                         intel_check_pch_fifo_underruns(dev_priv);
13028
13029                         if (!crtc->state->active) {
13030                                 /*
13031                                  * Make sure we don't call initial_watermarks
13032                                  * for ILK-style watermark updates.
13033                                  *
13034                                  * No clue what this is supposed to achieve.
13035                                  */
13036                                 if (INTEL_GEN(dev_priv) >= 9)
13037                                         dev_priv->display.initial_watermarks(intel_state,
13038                                                                              to_intel_crtc_state(crtc->state));
13039                         }
13040                 }
13041         }
13042
13043         /* Only after disabling all output pipelines that will be changed can we
13044          * update the the output configuration. */
13045         intel_modeset_update_crtc_state(state);
13046
13047         if (intel_state->modeset) {
13048                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13049
13050                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
13051
13052                 /*
13053                  * SKL workaround: bspec recommends we disable the SAGV when we
13054                  * have more then one pipe enabled
13055                  */
13056                 if (!intel_can_enable_sagv(state))
13057                         intel_disable_sagv(dev_priv);
13058
13059                 intel_modeset_verify_disabled(dev, state);
13060         }
13061
13062         /* Complete the events for pipes that have now been disabled */
13063         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13064                 bool modeset = needs_modeset(new_crtc_state);
13065
13066                 /* Complete events for now disable pipes here. */
13067                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13068                         spin_lock_irq(&dev->event_lock);
13069                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13070                         spin_unlock_irq(&dev->event_lock);
13071
13072                         new_crtc_state->event = NULL;
13073                 }
13074         }
13075
13076         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13077         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
13078
13079         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13080          * already, but still need the state for the delayed optimization. To
13081          * fix this:
13082          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13083          * - schedule that vblank worker _before_ calling hw_done
13084          * - at the start of commit_tail, cancel it _synchrously
13085          * - switch over to the vblank wait helper in the core after that since
13086          *   we don't need out special handling any more.
13087          */
13088         if (!state->legacy_cursor_update)
13089                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13090
13091         /*
13092          * Now that the vblank has passed, we can go ahead and program the
13093          * optimal watermarks on platforms that need two-step watermark
13094          * programming.
13095          *
13096          * TODO: Move this (and other cleanup) to an async worker eventually.
13097          */
13098         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13099                 intel_cstate = to_intel_crtc_state(new_crtc_state);
13100
13101                 if (dev_priv->display.optimize_watermarks)
13102                         dev_priv->display.optimize_watermarks(intel_state,
13103                                                               intel_cstate);
13104         }
13105
13106         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13107                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13108
13109                 if (put_domains[i])
13110                         modeset_put_power_domains(dev_priv, put_domains[i]);
13111
13112                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13113         }
13114
13115         if (intel_state->modeset && intel_can_enable_sagv(state))
13116                 intel_enable_sagv(dev_priv);
13117
13118         drm_atomic_helper_commit_hw_done(state);
13119
13120         if (intel_state->modeset)
13121                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13122
13123         mutex_lock(&dev->struct_mutex);
13124         drm_atomic_helper_cleanup_planes(dev, state);
13125         mutex_unlock(&dev->struct_mutex);
13126
13127         drm_atomic_helper_commit_cleanup_done(state);
13128
13129         drm_atomic_state_put(state);
13130
13131         /* As one of the primary mmio accessors, KMS has a high likelihood
13132          * of triggering bugs in unclaimed access. After we finish
13133          * modesetting, see if an error has been flagged, and if so
13134          * enable debugging for the next modeset - and hope we catch
13135          * the culprit.
13136          *
13137          * XXX note that we assume display power is on at this point.
13138          * This might hold true now but we need to add pm helper to check
13139          * unclaimed only when the hardware is on, as atomic commits
13140          * can happen also when the device is completely off.
13141          */
13142         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13143
13144         intel_atomic_helper_free_state(dev_priv);
13145 }
13146
13147 static void intel_atomic_commit_work(struct work_struct *work)
13148 {
13149         struct drm_atomic_state *state =
13150                 container_of(work, struct drm_atomic_state, commit_work);
13151
13152         intel_atomic_commit_tail(state);
13153 }
13154
13155 static int __i915_sw_fence_call
13156 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13157                           enum i915_sw_fence_notify notify)
13158 {
13159         struct intel_atomic_state *state =
13160                 container_of(fence, struct intel_atomic_state, commit_ready);
13161
13162         switch (notify) {
13163         case FENCE_COMPLETE:
13164                 if (state->base.commit_work.func)
13165                         queue_work(system_unbound_wq, &state->base.commit_work);
13166                 break;
13167
13168         case FENCE_FREE:
13169                 {
13170                         struct intel_atomic_helper *helper =
13171                                 &to_i915(state->base.dev)->atomic_helper;
13172
13173                         if (llist_add(&state->freed, &helper->free_list))
13174                                 schedule_work(&helper->free_work);
13175                         break;
13176                 }
13177         }
13178
13179         return NOTIFY_DONE;
13180 }
13181
13182 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13183 {
13184         struct drm_plane_state *old_plane_state, *new_plane_state;
13185         struct drm_plane *plane;
13186         int i;
13187
13188         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13189                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13190                                   intel_fb_obj(new_plane_state->fb),
13191                                   to_intel_plane(plane)->frontbuffer_bit);
13192 }
13193
13194 /**
13195  * intel_atomic_commit - commit validated state object
13196  * @dev: DRM device
13197  * @state: the top-level driver state object
13198  * @nonblock: nonblocking commit
13199  *
13200  * This function commits a top-level state object that has been validated
13201  * with drm_atomic_helper_check().
13202  *
13203  * RETURNS
13204  * Zero for success or -errno.
13205  */
13206 static int intel_atomic_commit(struct drm_device *dev,
13207                                struct drm_atomic_state *state,
13208                                bool nonblock)
13209 {
13210         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13211         struct drm_i915_private *dev_priv = to_i915(dev);
13212         int ret = 0;
13213
13214         ret = drm_atomic_helper_setup_commit(state, nonblock);
13215         if (ret)
13216                 return ret;
13217
13218         drm_atomic_state_get(state);
13219         i915_sw_fence_init(&intel_state->commit_ready,
13220                            intel_atomic_commit_ready);
13221
13222         ret = intel_atomic_prepare_commit(dev, state);
13223         if (ret) {
13224                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13225                 i915_sw_fence_commit(&intel_state->commit_ready);
13226                 return ret;
13227         }
13228
13229         /*
13230          * The intel_legacy_cursor_update() fast path takes care
13231          * of avoiding the vblank waits for simple cursor
13232          * movement and flips. For cursor on/off and size changes,
13233          * we want to perform the vblank waits so that watermark
13234          * updates happen during the correct frames. Gen9+ have
13235          * double buffered watermarks and so shouldn't need this.
13236          *
13237          * Do this after drm_atomic_helper_setup_commit() and
13238          * intel_atomic_prepare_commit() because we still want
13239          * to skip the flip and fb cleanup waits. Although that
13240          * does risk yanking the mapping from under the display
13241          * engine.
13242          *
13243          * FIXME doing watermarks and fb cleanup from a vblank worker
13244          * (assuming we had any) would solve these problems.
13245          */
13246         if (INTEL_GEN(dev_priv) < 9)
13247                 state->legacy_cursor_update = false;
13248
13249         drm_atomic_helper_swap_state(state, true);
13250         dev_priv->wm.distrust_bios_wm = false;
13251         intel_shared_dpll_swap_state(state);
13252         intel_atomic_track_fbs(state);
13253
13254         if (intel_state->modeset) {
13255                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13256                        sizeof(intel_state->min_pixclk));
13257                 dev_priv->active_crtcs = intel_state->active_crtcs;
13258                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13259                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13260         }
13261
13262         drm_atomic_state_get(state);
13263         INIT_WORK(&state->commit_work,
13264                   nonblock ? intel_atomic_commit_work : NULL);
13265
13266         i915_sw_fence_commit(&intel_state->commit_ready);
13267         if (!nonblock) {
13268                 i915_sw_fence_wait(&intel_state->commit_ready);
13269                 intel_atomic_commit_tail(state);
13270         }
13271
13272         return 0;
13273 }
13274
13275 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13276 {
13277         struct drm_device *dev = crtc->dev;
13278         struct drm_atomic_state *state;
13279         struct drm_crtc_state *crtc_state;
13280         int ret;
13281
13282         state = drm_atomic_state_alloc(dev);
13283         if (!state) {
13284                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13285                               crtc->base.id, crtc->name);
13286                 return;
13287         }
13288
13289         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
13290
13291 retry:
13292         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13293         ret = PTR_ERR_OR_ZERO(crtc_state);
13294         if (!ret) {
13295                 if (!crtc_state->active)
13296                         goto out;
13297
13298                 crtc_state->mode_changed = true;
13299                 ret = drm_atomic_commit(state);
13300         }
13301
13302         if (ret == -EDEADLK) {
13303                 drm_atomic_state_clear(state);
13304                 drm_modeset_backoff(state->acquire_ctx);
13305                 goto retry;
13306         }
13307
13308 out:
13309         drm_atomic_state_put(state);
13310 }
13311
13312 static const struct drm_crtc_funcs intel_crtc_funcs = {
13313         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13314         .set_config = drm_atomic_helper_set_config,
13315         .set_property = drm_atomic_helper_crtc_set_property,
13316         .destroy = intel_crtc_destroy,
13317         .page_flip = drm_atomic_helper_page_flip,
13318         .atomic_duplicate_state = intel_crtc_duplicate_state,
13319         .atomic_destroy_state = intel_crtc_destroy_state,
13320         .set_crc_source = intel_crtc_set_crc_source,
13321 };
13322
13323 /**
13324  * intel_prepare_plane_fb - Prepare fb for usage on plane
13325  * @plane: drm plane to prepare for
13326  * @fb: framebuffer to prepare for presentation
13327  *
13328  * Prepares a framebuffer for usage on a display plane.  Generally this
13329  * involves pinning the underlying object and updating the frontbuffer tracking
13330  * bits.  Some older platforms need special physical address handling for
13331  * cursor planes.
13332  *
13333  * Must be called with struct_mutex held.
13334  *
13335  * Returns 0 on success, negative error code on failure.
13336  */
13337 int
13338 intel_prepare_plane_fb(struct drm_plane *plane,
13339                        struct drm_plane_state *new_state)
13340 {
13341         struct intel_atomic_state *intel_state =
13342                 to_intel_atomic_state(new_state->state);
13343         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13344         struct drm_framebuffer *fb = new_state->fb;
13345         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13346         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13347         int ret;
13348
13349         if (obj) {
13350                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13351                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13352                         const int align = intel_cursor_alignment(dev_priv);
13353
13354                         ret = i915_gem_object_attach_phys(obj, align);
13355                         if (ret) {
13356                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13357                                 return ret;
13358                         }
13359                 } else {
13360                         struct i915_vma *vma;
13361
13362                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13363                         if (IS_ERR(vma)) {
13364                                 DRM_DEBUG_KMS("failed to pin object\n");
13365                                 return PTR_ERR(vma);
13366                         }
13367
13368                         to_intel_plane_state(new_state)->vma = vma;
13369                 }
13370         }
13371
13372         if (!obj && !old_obj)
13373                 return 0;
13374
13375         if (old_obj) {
13376                 struct drm_crtc_state *crtc_state =
13377                         drm_atomic_get_existing_crtc_state(new_state->state,
13378                                                            plane->state->crtc);
13379
13380                 /* Big Hammer, we also need to ensure that any pending
13381                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13382                  * current scanout is retired before unpinning the old
13383                  * framebuffer. Note that we rely on userspace rendering
13384                  * into the buffer attached to the pipe they are waiting
13385                  * on. If not, userspace generates a GPU hang with IPEHR
13386                  * point to the MI_WAIT_FOR_EVENT.
13387                  *
13388                  * This should only fail upon a hung GPU, in which case we
13389                  * can safely continue.
13390                  */
13391                 if (needs_modeset(crtc_state)) {
13392                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13393                                                               old_obj->resv, NULL,
13394                                                               false, 0,
13395                                                               GFP_KERNEL);
13396                         if (ret < 0)
13397                                 return ret;
13398                 }
13399         }
13400
13401         if (new_state->fence) { /* explicit fencing */
13402                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13403                                                     new_state->fence,
13404                                                     I915_FENCE_TIMEOUT,
13405                                                     GFP_KERNEL);
13406                 if (ret < 0)
13407                         return ret;
13408         }
13409
13410         if (!obj)
13411                 return 0;
13412
13413         if (!new_state->fence) { /* implicit fencing */
13414                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13415                                                       obj->resv, NULL,
13416                                                       false, I915_FENCE_TIMEOUT,
13417                                                       GFP_KERNEL);
13418                 if (ret < 0)
13419                         return ret;
13420
13421                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13422         }
13423
13424         return 0;
13425 }
13426
13427 /**
13428  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13429  * @plane: drm plane to clean up for
13430  * @fb: old framebuffer that was on plane
13431  *
13432  * Cleans up a framebuffer that has just been removed from a plane.
13433  *
13434  * Must be called with struct_mutex held.
13435  */
13436 void
13437 intel_cleanup_plane_fb(struct drm_plane *plane,
13438                        struct drm_plane_state *old_state)
13439 {
13440         struct i915_vma *vma;
13441
13442         /* Should only be called after a successful intel_prepare_plane_fb()! */
13443         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13444         if (vma)
13445                 intel_unpin_fb_vma(vma);
13446 }
13447
13448 int
13449 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13450 {
13451         struct drm_i915_private *dev_priv;
13452         int max_scale;
13453         int crtc_clock, max_dotclk;
13454
13455         if (!intel_crtc || !crtc_state->base.enable)
13456                 return DRM_PLANE_HELPER_NO_SCALING;
13457
13458         dev_priv = to_i915(intel_crtc->base.dev);
13459
13460         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13461         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13462
13463         if (IS_GEMINILAKE(dev_priv))
13464                 max_dotclk *= 2;
13465
13466         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13467                 return DRM_PLANE_HELPER_NO_SCALING;
13468
13469         /*
13470          * skl max scale is lower of:
13471          *    close to 3 but not 3, -1 is for that purpose
13472          *            or
13473          *    cdclk/crtc_clock
13474          */
13475         max_scale = min((1 << 16) * 3 - 1,
13476                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13477
13478         return max_scale;
13479 }
13480
13481 static int
13482 intel_check_primary_plane(struct intel_plane *plane,
13483                           struct intel_crtc_state *crtc_state,
13484                           struct intel_plane_state *state)
13485 {
13486         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13487         struct drm_crtc *crtc = state->base.crtc;
13488         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13489         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13490         bool can_position = false;
13491         int ret;
13492
13493         if (INTEL_GEN(dev_priv) >= 9) {
13494                 /* use scaler when colorkey is not required */
13495                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13496                         min_scale = 1;
13497                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13498                 }
13499                 can_position = true;
13500         }
13501
13502         ret = drm_plane_helper_check_state(&state->base,
13503                                            &state->clip,
13504                                            min_scale, max_scale,
13505                                            can_position, true);
13506         if (ret)
13507                 return ret;
13508
13509         if (!state->base.fb)
13510                 return 0;
13511
13512         if (INTEL_GEN(dev_priv) >= 9) {
13513                 ret = skl_check_plane_surface(state);
13514                 if (ret)
13515                         return ret;
13516
13517                 state->ctl = skl_plane_ctl(crtc_state, state);
13518         } else {
13519                 ret = i9xx_check_plane_surface(state);
13520                 if (ret)
13521                         return ret;
13522
13523                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13524         }
13525
13526         return 0;
13527 }
13528
13529 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13530                                     struct drm_crtc_state *old_crtc_state)
13531 {
13532         struct drm_device *dev = crtc->dev;
13533         struct drm_i915_private *dev_priv = to_i915(dev);
13534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13535         struct intel_crtc_state *intel_cstate =
13536                 to_intel_crtc_state(crtc->state);
13537         struct intel_crtc_state *old_intel_cstate =
13538                 to_intel_crtc_state(old_crtc_state);
13539         struct intel_atomic_state *old_intel_state =
13540                 to_intel_atomic_state(old_crtc_state->state);
13541         bool modeset = needs_modeset(crtc->state);
13542
13543         if (!modeset &&
13544             (intel_cstate->base.color_mgmt_changed ||
13545              intel_cstate->update_pipe)) {
13546                 intel_color_set_csc(crtc->state);
13547                 intel_color_load_luts(crtc->state);
13548         }
13549
13550         /* Perform vblank evasion around commit operation */
13551         intel_pipe_update_start(intel_crtc);
13552
13553         if (modeset)
13554                 goto out;
13555
13556         if (intel_cstate->update_pipe)
13557                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13558         else if (INTEL_GEN(dev_priv) >= 9)
13559                 skl_detach_scalers(intel_crtc);
13560
13561 out:
13562         if (dev_priv->display.atomic_update_watermarks)
13563                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13564                                                            intel_cstate);
13565 }
13566
13567 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13568                                      struct drm_crtc_state *old_crtc_state)
13569 {
13570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13571
13572         intel_pipe_update_end(intel_crtc, NULL);
13573 }
13574
13575 /**
13576  * intel_plane_destroy - destroy a plane
13577  * @plane: plane to destroy
13578  *
13579  * Common destruction function for all types of planes (primary, cursor,
13580  * sprite).
13581  */
13582 void intel_plane_destroy(struct drm_plane *plane)
13583 {
13584         drm_plane_cleanup(plane);
13585         kfree(to_intel_plane(plane));
13586 }
13587
13588 const struct drm_plane_funcs intel_plane_funcs = {
13589         .update_plane = drm_atomic_helper_update_plane,
13590         .disable_plane = drm_atomic_helper_disable_plane,
13591         .destroy = intel_plane_destroy,
13592         .set_property = drm_atomic_helper_plane_set_property,
13593         .atomic_get_property = intel_plane_atomic_get_property,
13594         .atomic_set_property = intel_plane_atomic_set_property,
13595         .atomic_duplicate_state = intel_plane_duplicate_state,
13596         .atomic_destroy_state = intel_plane_destroy_state,
13597 };
13598
13599 static int
13600 intel_legacy_cursor_update(struct drm_plane *plane,
13601                            struct drm_crtc *crtc,
13602                            struct drm_framebuffer *fb,
13603                            int crtc_x, int crtc_y,
13604                            unsigned int crtc_w, unsigned int crtc_h,
13605                            uint32_t src_x, uint32_t src_y,
13606                            uint32_t src_w, uint32_t src_h,
13607                            struct drm_modeset_acquire_ctx *ctx)
13608 {
13609         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13610         int ret;
13611         struct drm_plane_state *old_plane_state, *new_plane_state;
13612         struct intel_plane *intel_plane = to_intel_plane(plane);
13613         struct drm_framebuffer *old_fb;
13614         struct drm_crtc_state *crtc_state = crtc->state;
13615         struct i915_vma *old_vma;
13616
13617         /*
13618          * When crtc is inactive or there is a modeset pending,
13619          * wait for it to complete in the slowpath
13620          */
13621         if (!crtc_state->active || needs_modeset(crtc_state) ||
13622             to_intel_crtc_state(crtc_state)->update_pipe)
13623                 goto slow;
13624
13625         old_plane_state = plane->state;
13626
13627         /*
13628          * If any parameters change that may affect watermarks,
13629          * take the slowpath. Only changing fb or position should be
13630          * in the fastpath.
13631          */
13632         if (old_plane_state->crtc != crtc ||
13633             old_plane_state->src_w != src_w ||
13634             old_plane_state->src_h != src_h ||
13635             old_plane_state->crtc_w != crtc_w ||
13636             old_plane_state->crtc_h != crtc_h ||
13637             !old_plane_state->fb != !fb)
13638                 goto slow;
13639
13640         new_plane_state = intel_plane_duplicate_state(plane);
13641         if (!new_plane_state)
13642                 return -ENOMEM;
13643
13644         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13645
13646         new_plane_state->src_x = src_x;
13647         new_plane_state->src_y = src_y;
13648         new_plane_state->src_w = src_w;
13649         new_plane_state->src_h = src_h;
13650         new_plane_state->crtc_x = crtc_x;
13651         new_plane_state->crtc_y = crtc_y;
13652         new_plane_state->crtc_w = crtc_w;
13653         new_plane_state->crtc_h = crtc_h;
13654
13655         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13656                                                   to_intel_plane_state(new_plane_state));
13657         if (ret)
13658                 goto out_free;
13659
13660         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13661         if (ret)
13662                 goto out_free;
13663
13664         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13665                 int align = intel_cursor_alignment(dev_priv);
13666
13667                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13668                 if (ret) {
13669                         DRM_DEBUG_KMS("failed to attach phys object\n");
13670                         goto out_unlock;
13671                 }
13672         } else {
13673                 struct i915_vma *vma;
13674
13675                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13676                 if (IS_ERR(vma)) {
13677                         DRM_DEBUG_KMS("failed to pin object\n");
13678
13679                         ret = PTR_ERR(vma);
13680                         goto out_unlock;
13681                 }
13682
13683                 to_intel_plane_state(new_plane_state)->vma = vma;
13684         }
13685
13686         old_fb = old_plane_state->fb;
13687         old_vma = to_intel_plane_state(old_plane_state)->vma;
13688
13689         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13690                           intel_plane->frontbuffer_bit);
13691
13692         /* Swap plane state */
13693         new_plane_state->fence = old_plane_state->fence;
13694         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13695         new_plane_state->fence = NULL;
13696         new_plane_state->fb = old_fb;
13697         to_intel_plane_state(new_plane_state)->vma = old_vma;
13698
13699         if (plane->state->visible) {
13700                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13701                 intel_plane->update_plane(intel_plane,
13702                                           to_intel_crtc_state(crtc->state),
13703                                           to_intel_plane_state(plane->state));
13704         } else {
13705                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13706                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13707         }
13708
13709         intel_cleanup_plane_fb(plane, new_plane_state);
13710
13711 out_unlock:
13712         mutex_unlock(&dev_priv->drm.struct_mutex);
13713 out_free:
13714         intel_plane_destroy_state(plane, new_plane_state);
13715         return ret;
13716
13717 slow:
13718         return drm_atomic_helper_update_plane(plane, crtc, fb,
13719                                               crtc_x, crtc_y, crtc_w, crtc_h,
13720                                               src_x, src_y, src_w, src_h, ctx);
13721 }
13722
13723 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13724         .update_plane = intel_legacy_cursor_update,
13725         .disable_plane = drm_atomic_helper_disable_plane,
13726         .destroy = intel_plane_destroy,
13727         .set_property = drm_atomic_helper_plane_set_property,
13728         .atomic_get_property = intel_plane_atomic_get_property,
13729         .atomic_set_property = intel_plane_atomic_set_property,
13730         .atomic_duplicate_state = intel_plane_duplicate_state,
13731         .atomic_destroy_state = intel_plane_destroy_state,
13732 };
13733
13734 static struct intel_plane *
13735 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13736 {
13737         struct intel_plane *primary = NULL;
13738         struct intel_plane_state *state = NULL;
13739         const uint32_t *intel_primary_formats;
13740         unsigned int supported_rotations;
13741         unsigned int num_formats;
13742         int ret;
13743
13744         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13745         if (!primary) {
13746                 ret = -ENOMEM;
13747                 goto fail;
13748         }
13749
13750         state = intel_create_plane_state(&primary->base);
13751         if (!state) {
13752                 ret = -ENOMEM;
13753                 goto fail;
13754         }
13755
13756         primary->base.state = &state->base;
13757
13758         primary->can_scale = false;
13759         primary->max_downscale = 1;
13760         if (INTEL_GEN(dev_priv) >= 9) {
13761                 primary->can_scale = true;
13762                 state->scaler_id = -1;
13763         }
13764         primary->pipe = pipe;
13765         /*
13766          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13767          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13768          */
13769         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13770                 primary->plane = (enum plane) !pipe;
13771         else
13772                 primary->plane = (enum plane) pipe;
13773         primary->id = PLANE_PRIMARY;
13774         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13775         primary->check_plane = intel_check_primary_plane;
13776
13777         if (INTEL_GEN(dev_priv) >= 9) {
13778                 intel_primary_formats = skl_primary_formats;
13779                 num_formats = ARRAY_SIZE(skl_primary_formats);
13780
13781                 primary->update_plane = skylake_update_primary_plane;
13782                 primary->disable_plane = skylake_disable_primary_plane;
13783         } else if (INTEL_GEN(dev_priv) >= 4) {
13784                 intel_primary_formats = i965_primary_formats;
13785                 num_formats = ARRAY_SIZE(i965_primary_formats);
13786
13787                 primary->update_plane = i9xx_update_primary_plane;
13788                 primary->disable_plane = i9xx_disable_primary_plane;
13789         } else {
13790                 intel_primary_formats = i8xx_primary_formats;
13791                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13792
13793                 primary->update_plane = i9xx_update_primary_plane;
13794                 primary->disable_plane = i9xx_disable_primary_plane;
13795         }
13796
13797         if (INTEL_GEN(dev_priv) >= 9)
13798                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13799                                                0, &intel_plane_funcs,
13800                                                intel_primary_formats, num_formats,
13801                                                DRM_PLANE_TYPE_PRIMARY,
13802                                                "plane 1%c", pipe_name(pipe));
13803         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13804                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13805                                                0, &intel_plane_funcs,
13806                                                intel_primary_formats, num_formats,
13807                                                DRM_PLANE_TYPE_PRIMARY,
13808                                                "primary %c", pipe_name(pipe));
13809         else
13810                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13811                                                0, &intel_plane_funcs,
13812                                                intel_primary_formats, num_formats,
13813                                                DRM_PLANE_TYPE_PRIMARY,
13814                                                "plane %c", plane_name(primary->plane));
13815         if (ret)
13816                 goto fail;
13817
13818         if (INTEL_GEN(dev_priv) >= 9) {
13819                 supported_rotations =
13820                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13821                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13822         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13823                 supported_rotations =
13824                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13825                         DRM_MODE_REFLECT_X;
13826         } else if (INTEL_GEN(dev_priv) >= 4) {
13827                 supported_rotations =
13828                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13829         } else {
13830                 supported_rotations = DRM_MODE_ROTATE_0;
13831         }
13832
13833         if (INTEL_GEN(dev_priv) >= 4)
13834                 drm_plane_create_rotation_property(&primary->base,
13835                                                    DRM_MODE_ROTATE_0,
13836                                                    supported_rotations);
13837
13838         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13839
13840         return primary;
13841
13842 fail:
13843         kfree(state);
13844         kfree(primary);
13845
13846         return ERR_PTR(ret);
13847 }
13848
13849 static struct intel_plane *
13850 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13851                           enum pipe pipe)
13852 {
13853         struct intel_plane *cursor = NULL;
13854         struct intel_plane_state *state = NULL;
13855         int ret;
13856
13857         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13858         if (!cursor) {
13859                 ret = -ENOMEM;
13860                 goto fail;
13861         }
13862
13863         state = intel_create_plane_state(&cursor->base);
13864         if (!state) {
13865                 ret = -ENOMEM;
13866                 goto fail;
13867         }
13868
13869         cursor->base.state = &state->base;
13870
13871         cursor->can_scale = false;
13872         cursor->max_downscale = 1;
13873         cursor->pipe = pipe;
13874         cursor->plane = pipe;
13875         cursor->id = PLANE_CURSOR;
13876         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13877
13878         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13879                 cursor->update_plane = i845_update_cursor;
13880                 cursor->disable_plane = i845_disable_cursor;
13881                 cursor->check_plane = i845_check_cursor;
13882         } else {
13883                 cursor->update_plane = i9xx_update_cursor;
13884                 cursor->disable_plane = i9xx_disable_cursor;
13885                 cursor->check_plane = i9xx_check_cursor;
13886         }
13887
13888         cursor->cursor.base = ~0;
13889         cursor->cursor.cntl = ~0;
13890
13891         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13892                 cursor->cursor.size = ~0;
13893
13894         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13895                                        0, &intel_cursor_plane_funcs,
13896                                        intel_cursor_formats,
13897                                        ARRAY_SIZE(intel_cursor_formats),
13898                                        DRM_PLANE_TYPE_CURSOR,
13899                                        "cursor %c", pipe_name(pipe));
13900         if (ret)
13901                 goto fail;
13902
13903         if (INTEL_GEN(dev_priv) >= 4)
13904                 drm_plane_create_rotation_property(&cursor->base,
13905                                                    DRM_MODE_ROTATE_0,
13906                                                    DRM_MODE_ROTATE_0 |
13907                                                    DRM_MODE_ROTATE_180);
13908
13909         if (INTEL_GEN(dev_priv) >= 9)
13910                 state->scaler_id = -1;
13911
13912         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13913
13914         return cursor;
13915
13916 fail:
13917         kfree(state);
13918         kfree(cursor);
13919
13920         return ERR_PTR(ret);
13921 }
13922
13923 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13924                                     struct intel_crtc_state *crtc_state)
13925 {
13926         struct intel_crtc_scaler_state *scaler_state =
13927                 &crtc_state->scaler_state;
13928         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13929         int i;
13930
13931         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13932         if (!crtc->num_scalers)
13933                 return;
13934
13935         for (i = 0; i < crtc->num_scalers; i++) {
13936                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13937
13938                 scaler->in_use = 0;
13939                 scaler->mode = PS_SCALER_MODE_DYN;
13940         }
13941
13942         scaler_state->scaler_id = -1;
13943 }
13944
13945 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13946 {
13947         struct intel_crtc *intel_crtc;
13948         struct intel_crtc_state *crtc_state = NULL;
13949         struct intel_plane *primary = NULL;
13950         struct intel_plane *cursor = NULL;
13951         int sprite, ret;
13952
13953         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13954         if (!intel_crtc)
13955                 return -ENOMEM;
13956
13957         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13958         if (!crtc_state) {
13959                 ret = -ENOMEM;
13960                 goto fail;
13961         }
13962         intel_crtc->config = crtc_state;
13963         intel_crtc->base.state = &crtc_state->base;
13964         crtc_state->base.crtc = &intel_crtc->base;
13965
13966         primary = intel_primary_plane_create(dev_priv, pipe);
13967         if (IS_ERR(primary)) {
13968                 ret = PTR_ERR(primary);
13969                 goto fail;
13970         }
13971         intel_crtc->plane_ids_mask |= BIT(primary->id);
13972
13973         for_each_sprite(dev_priv, pipe, sprite) {
13974                 struct intel_plane *plane;
13975
13976                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13977                 if (IS_ERR(plane)) {
13978                         ret = PTR_ERR(plane);
13979                         goto fail;
13980                 }
13981                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13982         }
13983
13984         cursor = intel_cursor_plane_create(dev_priv, pipe);
13985         if (IS_ERR(cursor)) {
13986                 ret = PTR_ERR(cursor);
13987                 goto fail;
13988         }
13989         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13990
13991         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13992                                         &primary->base, &cursor->base,
13993                                         &intel_crtc_funcs,
13994                                         "pipe %c", pipe_name(pipe));
13995         if (ret)
13996                 goto fail;
13997
13998         intel_crtc->pipe = pipe;
13999         intel_crtc->plane = primary->plane;
14000
14001         /* initialize shared scalers */
14002         intel_crtc_init_scalers(intel_crtc, crtc_state);
14003
14004         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14005                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14006         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
14007         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
14008
14009         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14010
14011         intel_color_init(&intel_crtc->base);
14012
14013         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14014
14015         return 0;
14016
14017 fail:
14018         /*
14019          * drm_mode_config_cleanup() will free up any
14020          * crtcs/planes already initialized.
14021          */
14022         kfree(crtc_state);
14023         kfree(intel_crtc);
14024
14025         return ret;
14026 }
14027
14028 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14029 {
14030         struct drm_device *dev = connector->base.dev;
14031
14032         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14033
14034         if (!connector->base.state->crtc)
14035                 return INVALID_PIPE;
14036
14037         return to_intel_crtc(connector->base.state->crtc)->pipe;
14038 }
14039
14040 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14041                                 struct drm_file *file)
14042 {
14043         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14044         struct drm_crtc *drmmode_crtc;
14045         struct intel_crtc *crtc;
14046
14047         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14048         if (!drmmode_crtc)
14049                 return -ENOENT;
14050
14051         crtc = to_intel_crtc(drmmode_crtc);
14052         pipe_from_crtc_id->pipe = crtc->pipe;
14053
14054         return 0;
14055 }
14056
14057 static int intel_encoder_clones(struct intel_encoder *encoder)
14058 {
14059         struct drm_device *dev = encoder->base.dev;
14060         struct intel_encoder *source_encoder;
14061         int index_mask = 0;
14062         int entry = 0;
14063
14064         for_each_intel_encoder(dev, source_encoder) {
14065                 if (encoders_cloneable(encoder, source_encoder))
14066                         index_mask |= (1 << entry);
14067
14068                 entry++;
14069         }
14070
14071         return index_mask;
14072 }
14073
14074 static bool has_edp_a(struct drm_i915_private *dev_priv)
14075 {
14076         if (!IS_MOBILE(dev_priv))
14077                 return false;
14078
14079         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14080                 return false;
14081
14082         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14083                 return false;
14084
14085         return true;
14086 }
14087
14088 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14089 {
14090         if (INTEL_GEN(dev_priv) >= 9)
14091                 return false;
14092
14093         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14094                 return false;
14095
14096         if (IS_CHERRYVIEW(dev_priv))
14097                 return false;
14098
14099         if (HAS_PCH_LPT_H(dev_priv) &&
14100             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14101                 return false;
14102
14103         /* DDI E can't be used if DDI A requires 4 lanes */
14104         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14105                 return false;
14106
14107         if (!dev_priv->vbt.int_crt_support)
14108                 return false;
14109
14110         return true;
14111 }
14112
14113 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14114 {
14115         int pps_num;
14116         int pps_idx;
14117
14118         if (HAS_DDI(dev_priv))
14119                 return;
14120         /*
14121          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14122          * everywhere where registers can be write protected.
14123          */
14124         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14125                 pps_num = 2;
14126         else
14127                 pps_num = 1;
14128
14129         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14130                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14131
14132                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14133                 I915_WRITE(PP_CONTROL(pps_idx), val);
14134         }
14135 }
14136
14137 static void intel_pps_init(struct drm_i915_private *dev_priv)
14138 {
14139         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14140                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14141         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14142                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14143         else
14144                 dev_priv->pps_mmio_base = PPS_BASE;
14145
14146         intel_pps_unlock_regs_wa(dev_priv);
14147 }
14148
14149 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14150 {
14151         struct intel_encoder *encoder;
14152         bool dpd_is_edp = false;
14153
14154         intel_pps_init(dev_priv);
14155
14156         /*
14157          * intel_edp_init_connector() depends on this completing first, to
14158          * prevent the registeration of both eDP and LVDS and the incorrect
14159          * sharing of the PPS.
14160          */
14161         intel_lvds_init(dev_priv);
14162
14163         if (intel_crt_present(dev_priv))
14164                 intel_crt_init(dev_priv);
14165
14166         if (IS_GEN9_LP(dev_priv)) {
14167                 /*
14168                  * FIXME: Broxton doesn't support port detection via the
14169                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14170                  * detect the ports.
14171                  */
14172                 intel_ddi_init(dev_priv, PORT_A);
14173                 intel_ddi_init(dev_priv, PORT_B);
14174                 intel_ddi_init(dev_priv, PORT_C);
14175
14176                 intel_dsi_init(dev_priv);
14177         } else if (HAS_DDI(dev_priv)) {
14178                 int found;
14179
14180                 /*
14181                  * Haswell uses DDI functions to detect digital outputs.
14182                  * On SKL pre-D0 the strap isn't connected, so we assume
14183                  * it's there.
14184                  */
14185                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14186                 /* WaIgnoreDDIAStrap: skl */
14187                 if (found || IS_GEN9_BC(dev_priv))
14188                         intel_ddi_init(dev_priv, PORT_A);
14189
14190                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14191                  * register */
14192                 found = I915_READ(SFUSE_STRAP);
14193
14194                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14195                         intel_ddi_init(dev_priv, PORT_B);
14196                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14197                         intel_ddi_init(dev_priv, PORT_C);
14198                 if (found & SFUSE_STRAP_DDID_DETECTED)
14199                         intel_ddi_init(dev_priv, PORT_D);
14200                 /*
14201                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14202                  */
14203                 if (IS_GEN9_BC(dev_priv) &&
14204                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14205                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14206                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14207                         intel_ddi_init(dev_priv, PORT_E);
14208
14209         } else if (HAS_PCH_SPLIT(dev_priv)) {
14210                 int found;
14211                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14212
14213                 if (has_edp_a(dev_priv))
14214                         intel_dp_init(dev_priv, DP_A, PORT_A);
14215
14216                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14217                         /* PCH SDVOB multiplex with HDMIB */
14218                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14219                         if (!found)
14220                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14221                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14222                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14223                 }
14224
14225                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14226                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14227
14228                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14229                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14230
14231                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14232                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14233
14234                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14235                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14236         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14237                 bool has_edp, has_port;
14238
14239                 /*
14240                  * The DP_DETECTED bit is the latched state of the DDC
14241                  * SDA pin at boot. However since eDP doesn't require DDC
14242                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14243                  * eDP ports may have been muxed to an alternate function.
14244                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14245                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14246                  * detect eDP ports.
14247                  *
14248                  * Sadly the straps seem to be missing sometimes even for HDMI
14249                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14250                  * and VBT for the presence of the port. Additionally we can't
14251                  * trust the port type the VBT declares as we've seen at least
14252                  * HDMI ports that the VBT claim are DP or eDP.
14253                  */
14254                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14255                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14256                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14257                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14258                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14259                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14260
14261                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14262                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14263                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14264                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14265                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14266                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14267
14268                 if (IS_CHERRYVIEW(dev_priv)) {
14269                         /*
14270                          * eDP not supported on port D,
14271                          * so no need to worry about it
14272                          */
14273                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14274                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14275                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14276                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14277                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14278                 }
14279
14280                 intel_dsi_init(dev_priv);
14281         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14282                 bool found = false;
14283
14284                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14285                         DRM_DEBUG_KMS("probing SDVOB\n");
14286                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14287                         if (!found && IS_G4X(dev_priv)) {
14288                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14289                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14290                         }
14291
14292                         if (!found && IS_G4X(dev_priv))
14293                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14294                 }
14295
14296                 /* Before G4X SDVOC doesn't have its own detect register */
14297
14298                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14299                         DRM_DEBUG_KMS("probing SDVOC\n");
14300                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14301                 }
14302
14303                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14304
14305                         if (IS_G4X(dev_priv)) {
14306                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14307                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14308                         }
14309                         if (IS_G4X(dev_priv))
14310                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14311                 }
14312
14313                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14314                         intel_dp_init(dev_priv, DP_D, PORT_D);
14315         } else if (IS_GEN2(dev_priv))
14316                 intel_dvo_init(dev_priv);
14317
14318         if (SUPPORTS_TV(dev_priv))
14319                 intel_tv_init(dev_priv);
14320
14321         intel_psr_init(dev_priv);
14322
14323         for_each_intel_encoder(&dev_priv->drm, encoder) {
14324                 encoder->base.possible_crtcs = encoder->crtc_mask;
14325                 encoder->base.possible_clones =
14326                         intel_encoder_clones(encoder);
14327         }
14328
14329         intel_init_pch_refclk(dev_priv);
14330
14331         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14332 }
14333
14334 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14335 {
14336         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14337
14338         drm_framebuffer_cleanup(fb);
14339
14340         i915_gem_object_lock(intel_fb->obj);
14341         WARN_ON(!intel_fb->obj->framebuffer_references--);
14342         i915_gem_object_unlock(intel_fb->obj);
14343
14344         i915_gem_object_put(intel_fb->obj);
14345
14346         kfree(intel_fb);
14347 }
14348
14349 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14350                                                 struct drm_file *file,
14351                                                 unsigned int *handle)
14352 {
14353         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14354         struct drm_i915_gem_object *obj = intel_fb->obj;
14355
14356         if (obj->userptr.mm) {
14357                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14358                 return -EINVAL;
14359         }
14360
14361         return drm_gem_handle_create(file, &obj->base, handle);
14362 }
14363
14364 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14365                                         struct drm_file *file,
14366                                         unsigned flags, unsigned color,
14367                                         struct drm_clip_rect *clips,
14368                                         unsigned num_clips)
14369 {
14370         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14371
14372         i915_gem_object_flush_if_display(obj);
14373         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14374
14375         return 0;
14376 }
14377
14378 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14379         .destroy = intel_user_framebuffer_destroy,
14380         .create_handle = intel_user_framebuffer_create_handle,
14381         .dirty = intel_user_framebuffer_dirty,
14382 };
14383
14384 static
14385 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14386                          uint64_t fb_modifier, uint32_t pixel_format)
14387 {
14388         u32 gen = INTEL_GEN(dev_priv);
14389
14390         if (gen >= 9) {
14391                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14392
14393                 /* "The stride in bytes must not exceed the of the size of 8K
14394                  *  pixels and 32K bytes."
14395                  */
14396                 return min(8192 * cpp, 32768);
14397         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14398                 return 32*1024;
14399         } else if (gen >= 4) {
14400                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14401                         return 16*1024;
14402                 else
14403                         return 32*1024;
14404         } else if (gen >= 3) {
14405                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14406                         return 8*1024;
14407                 else
14408                         return 16*1024;
14409         } else {
14410                 /* XXX DSPC is limited to 4k tiled */
14411                 return 8*1024;
14412         }
14413 }
14414
14415 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14416                                   struct drm_i915_gem_object *obj,
14417                                   struct drm_mode_fb_cmd2 *mode_cmd)
14418 {
14419         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14420         struct drm_format_name_buf format_name;
14421         u32 pitch_limit, stride_alignment;
14422         unsigned int tiling, stride;
14423         int ret = -EINVAL;
14424
14425         i915_gem_object_lock(obj);
14426         obj->framebuffer_references++;
14427         tiling = i915_gem_object_get_tiling(obj);
14428         stride = i915_gem_object_get_stride(obj);
14429         i915_gem_object_unlock(obj);
14430
14431         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14432                 /*
14433                  * If there's a fence, enforce that
14434                  * the fb modifier and tiling mode match.
14435                  */
14436                 if (tiling != I915_TILING_NONE &&
14437                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14438                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14439                         goto err;
14440                 }
14441         } else {
14442                 if (tiling == I915_TILING_X) {
14443                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14444                 } else if (tiling == I915_TILING_Y) {
14445                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14446                         goto err;
14447                 }
14448         }
14449
14450         /* Passed in modifier sanity checking. */
14451         switch (mode_cmd->modifier[0]) {
14452         case I915_FORMAT_MOD_Y_TILED:
14453         case I915_FORMAT_MOD_Yf_TILED:
14454                 if (INTEL_GEN(dev_priv) < 9) {
14455                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14456                                       mode_cmd->modifier[0]);
14457                         goto err;
14458                 }
14459         case DRM_FORMAT_MOD_LINEAR:
14460         case I915_FORMAT_MOD_X_TILED:
14461                 break;
14462         default:
14463                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14464                               mode_cmd->modifier[0]);
14465                 goto err;
14466         }
14467
14468         /*
14469          * gen2/3 display engine uses the fence if present,
14470          * so the tiling mode must match the fb modifier exactly.
14471          */
14472         if (INTEL_INFO(dev_priv)->gen < 4 &&
14473             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14474                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14475                 goto err;
14476         }
14477
14478         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14479                                            mode_cmd->pixel_format);
14480         if (mode_cmd->pitches[0] > pitch_limit) {
14481                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14482                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14483                               "tiled" : "linear",
14484                               mode_cmd->pitches[0], pitch_limit);
14485                 goto err;
14486         }
14487
14488         /*
14489          * If there's a fence, enforce that
14490          * the fb pitch and fence stride match.
14491          */
14492         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14493                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14494                               mode_cmd->pitches[0], stride);
14495                 goto err;
14496         }
14497
14498         /* Reject formats not supported by any plane early. */
14499         switch (mode_cmd->pixel_format) {
14500         case DRM_FORMAT_C8:
14501         case DRM_FORMAT_RGB565:
14502         case DRM_FORMAT_XRGB8888:
14503         case DRM_FORMAT_ARGB8888:
14504                 break;
14505         case DRM_FORMAT_XRGB1555:
14506                 if (INTEL_GEN(dev_priv) > 3) {
14507                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14508                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14509                         goto err;
14510                 }
14511                 break;
14512         case DRM_FORMAT_ABGR8888:
14513                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14514                     INTEL_GEN(dev_priv) < 9) {
14515                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14516                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14517                         goto err;
14518                 }
14519                 break;
14520         case DRM_FORMAT_XBGR8888:
14521         case DRM_FORMAT_XRGB2101010:
14522         case DRM_FORMAT_XBGR2101010:
14523                 if (INTEL_GEN(dev_priv) < 4) {
14524                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14525                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14526                         goto err;
14527                 }
14528                 break;
14529         case DRM_FORMAT_ABGR2101010:
14530                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14531                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14532                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14533                         goto err;
14534                 }
14535                 break;
14536         case DRM_FORMAT_YUYV:
14537         case DRM_FORMAT_UYVY:
14538         case DRM_FORMAT_YVYU:
14539         case DRM_FORMAT_VYUY:
14540                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14541                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14542                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14543                         goto err;
14544                 }
14545                 break;
14546         default:
14547                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14548                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14549                 goto err;
14550         }
14551
14552         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14553         if (mode_cmd->offsets[0] != 0)
14554                 goto err;
14555
14556         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14557                                        &intel_fb->base, mode_cmd);
14558
14559         stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14560         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14561                 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14562                               mode_cmd->pitches[0], stride_alignment);
14563                 goto err;
14564         }
14565
14566         intel_fb->obj = obj;
14567
14568         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14569         if (ret)
14570                 goto err;
14571
14572         ret = drm_framebuffer_init(obj->base.dev,
14573                                    &intel_fb->base,
14574                                    &intel_fb_funcs);
14575         if (ret) {
14576                 DRM_ERROR("framebuffer init failed %d\n", ret);
14577                 goto err;
14578         }
14579
14580         return 0;
14581
14582 err:
14583         i915_gem_object_lock(obj);
14584         obj->framebuffer_references--;
14585         i915_gem_object_unlock(obj);
14586         return ret;
14587 }
14588
14589 static struct drm_framebuffer *
14590 intel_user_framebuffer_create(struct drm_device *dev,
14591                               struct drm_file *filp,
14592                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14593 {
14594         struct drm_framebuffer *fb;
14595         struct drm_i915_gem_object *obj;
14596         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14597
14598         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14599         if (!obj)
14600                 return ERR_PTR(-ENOENT);
14601
14602         fb = intel_framebuffer_create(obj, &mode_cmd);
14603         if (IS_ERR(fb))
14604                 i915_gem_object_put(obj);
14605
14606         return fb;
14607 }
14608
14609 static void intel_atomic_state_free(struct drm_atomic_state *state)
14610 {
14611         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14612
14613         drm_atomic_state_default_release(state);
14614
14615         i915_sw_fence_fini(&intel_state->commit_ready);
14616
14617         kfree(state);
14618 }
14619
14620 static const struct drm_mode_config_funcs intel_mode_funcs = {
14621         .fb_create = intel_user_framebuffer_create,
14622         .output_poll_changed = intel_fbdev_output_poll_changed,
14623         .atomic_check = intel_atomic_check,
14624         .atomic_commit = intel_atomic_commit,
14625         .atomic_state_alloc = intel_atomic_state_alloc,
14626         .atomic_state_clear = intel_atomic_state_clear,
14627         .atomic_state_free = intel_atomic_state_free,
14628 };
14629
14630 /**
14631  * intel_init_display_hooks - initialize the display modesetting hooks
14632  * @dev_priv: device private
14633  */
14634 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14635 {
14636         intel_init_cdclk_hooks(dev_priv);
14637
14638         if (INTEL_INFO(dev_priv)->gen >= 9) {
14639                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14640                 dev_priv->display.get_initial_plane_config =
14641                         skylake_get_initial_plane_config;
14642                 dev_priv->display.crtc_compute_clock =
14643                         haswell_crtc_compute_clock;
14644                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14645                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14646         } else if (HAS_DDI(dev_priv)) {
14647                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14648                 dev_priv->display.get_initial_plane_config =
14649                         ironlake_get_initial_plane_config;
14650                 dev_priv->display.crtc_compute_clock =
14651                         haswell_crtc_compute_clock;
14652                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14653                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14654         } else if (HAS_PCH_SPLIT(dev_priv)) {
14655                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14656                 dev_priv->display.get_initial_plane_config =
14657                         ironlake_get_initial_plane_config;
14658                 dev_priv->display.crtc_compute_clock =
14659                         ironlake_crtc_compute_clock;
14660                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14661                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14662         } else if (IS_CHERRYVIEW(dev_priv)) {
14663                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14664                 dev_priv->display.get_initial_plane_config =
14665                         i9xx_get_initial_plane_config;
14666                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14667                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14668                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14669         } else if (IS_VALLEYVIEW(dev_priv)) {
14670                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14671                 dev_priv->display.get_initial_plane_config =
14672                         i9xx_get_initial_plane_config;
14673                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14674                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14675                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14676         } else if (IS_G4X(dev_priv)) {
14677                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14678                 dev_priv->display.get_initial_plane_config =
14679                         i9xx_get_initial_plane_config;
14680                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14681                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14682                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14683         } else if (IS_PINEVIEW(dev_priv)) {
14684                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14685                 dev_priv->display.get_initial_plane_config =
14686                         i9xx_get_initial_plane_config;
14687                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14688                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14689                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14690         } else if (!IS_GEN2(dev_priv)) {
14691                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14692                 dev_priv->display.get_initial_plane_config =
14693                         i9xx_get_initial_plane_config;
14694                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14695                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14696                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14697         } else {
14698                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14699                 dev_priv->display.get_initial_plane_config =
14700                         i9xx_get_initial_plane_config;
14701                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14702                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14703                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14704         }
14705
14706         if (IS_GEN5(dev_priv)) {
14707                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14708         } else if (IS_GEN6(dev_priv)) {
14709                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14710         } else if (IS_IVYBRIDGE(dev_priv)) {
14711                 /* FIXME: detect B0+ stepping and use auto training */
14712                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14713         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14714                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14715         }
14716
14717         if (dev_priv->info.gen >= 9)
14718                 dev_priv->display.update_crtcs = skl_update_crtcs;
14719         else
14720                 dev_priv->display.update_crtcs = intel_update_crtcs;
14721
14722         switch (INTEL_INFO(dev_priv)->gen) {
14723         case 2:
14724                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14725                 break;
14726
14727         case 3:
14728                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14729                 break;
14730
14731         case 4:
14732         case 5:
14733                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14734                 break;
14735
14736         case 6:
14737                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14738                 break;
14739         case 7:
14740         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14741                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14742                 break;
14743         case 9:
14744                 /* Drop through - unsupported since execlist only. */
14745         default:
14746                 /* Default just returns -ENODEV to indicate unsupported */
14747                 dev_priv->display.queue_flip = intel_default_queue_flip;
14748         }
14749 }
14750
14751 /*
14752  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14753  * resume, or other times.  This quirk makes sure that's the case for
14754  * affected systems.
14755  */
14756 static void quirk_pipea_force(struct drm_device *dev)
14757 {
14758         struct drm_i915_private *dev_priv = to_i915(dev);
14759
14760         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14761         DRM_INFO("applying pipe a force quirk\n");
14762 }
14763
14764 static void quirk_pipeb_force(struct drm_device *dev)
14765 {
14766         struct drm_i915_private *dev_priv = to_i915(dev);
14767
14768         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14769         DRM_INFO("applying pipe b force quirk\n");
14770 }
14771
14772 /*
14773  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14774  */
14775 static void quirk_ssc_force_disable(struct drm_device *dev)
14776 {
14777         struct drm_i915_private *dev_priv = to_i915(dev);
14778         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14779         DRM_INFO("applying lvds SSC disable quirk\n");
14780 }
14781
14782 /*
14783  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14784  * brightness value
14785  */
14786 static void quirk_invert_brightness(struct drm_device *dev)
14787 {
14788         struct drm_i915_private *dev_priv = to_i915(dev);
14789         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14790         DRM_INFO("applying inverted panel brightness quirk\n");
14791 }
14792
14793 /* Some VBT's incorrectly indicate no backlight is present */
14794 static void quirk_backlight_present(struct drm_device *dev)
14795 {
14796         struct drm_i915_private *dev_priv = to_i915(dev);
14797         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14798         DRM_INFO("applying backlight present quirk\n");
14799 }
14800
14801 struct intel_quirk {
14802         int device;
14803         int subsystem_vendor;
14804         int subsystem_device;
14805         void (*hook)(struct drm_device *dev);
14806 };
14807
14808 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14809 struct intel_dmi_quirk {
14810         void (*hook)(struct drm_device *dev);
14811         const struct dmi_system_id (*dmi_id_list)[];
14812 };
14813
14814 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14815 {
14816         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14817         return 1;
14818 }
14819
14820 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14821         {
14822                 .dmi_id_list = &(const struct dmi_system_id[]) {
14823                         {
14824                                 .callback = intel_dmi_reverse_brightness,
14825                                 .ident = "NCR Corporation",
14826                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14827                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14828                                 },
14829                         },
14830                         { }  /* terminating entry */
14831                 },
14832                 .hook = quirk_invert_brightness,
14833         },
14834 };
14835
14836 static struct intel_quirk intel_quirks[] = {
14837         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14838         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14839
14840         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14841         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14842
14843         /* 830 needs to leave pipe A & dpll A up */
14844         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14845
14846         /* 830 needs to leave pipe B & dpll B up */
14847         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14848
14849         /* Lenovo U160 cannot use SSC on LVDS */
14850         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14851
14852         /* Sony Vaio Y cannot use SSC on LVDS */
14853         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14854
14855         /* Acer Aspire 5734Z must invert backlight brightness */
14856         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14857
14858         /* Acer/eMachines G725 */
14859         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14860
14861         /* Acer/eMachines e725 */
14862         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14863
14864         /* Acer/Packard Bell NCL20 */
14865         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14866
14867         /* Acer Aspire 4736Z */
14868         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14869
14870         /* Acer Aspire 5336 */
14871         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14872
14873         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14874         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14875
14876         /* Acer C720 Chromebook (Core i3 4005U) */
14877         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14878
14879         /* Apple Macbook 2,1 (Core 2 T7400) */
14880         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14881
14882         /* Apple Macbook 4,1 */
14883         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14884
14885         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14886         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14887
14888         /* HP Chromebook 14 (Celeron 2955U) */
14889         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14890
14891         /* Dell Chromebook 11 */
14892         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14893
14894         /* Dell Chromebook 11 (2015 version) */
14895         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14896 };
14897
14898 static void intel_init_quirks(struct drm_device *dev)
14899 {
14900         struct pci_dev *d = dev->pdev;
14901         int i;
14902
14903         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14904                 struct intel_quirk *q = &intel_quirks[i];
14905
14906                 if (d->device == q->device &&
14907                     (d->subsystem_vendor == q->subsystem_vendor ||
14908                      q->subsystem_vendor == PCI_ANY_ID) &&
14909                     (d->subsystem_device == q->subsystem_device ||
14910                      q->subsystem_device == PCI_ANY_ID))
14911                         q->hook(dev);
14912         }
14913         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14914                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14915                         intel_dmi_quirks[i].hook(dev);
14916         }
14917 }
14918
14919 /* Disable the VGA plane that we never use */
14920 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14921 {
14922         struct pci_dev *pdev = dev_priv->drm.pdev;
14923         u8 sr1;
14924         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14925
14926         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14927         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14928         outb(SR01, VGA_SR_INDEX);
14929         sr1 = inb(VGA_SR_DATA);
14930         outb(sr1 | 1<<5, VGA_SR_DATA);
14931         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14932         udelay(300);
14933
14934         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14935         POSTING_READ(vga_reg);
14936 }
14937
14938 void intel_modeset_init_hw(struct drm_device *dev)
14939 {
14940         struct drm_i915_private *dev_priv = to_i915(dev);
14941
14942         intel_update_cdclk(dev_priv);
14943         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14944
14945         intel_init_clock_gating(dev_priv);
14946 }
14947
14948 /*
14949  * Calculate what we think the watermarks should be for the state we've read
14950  * out of the hardware and then immediately program those watermarks so that
14951  * we ensure the hardware settings match our internal state.
14952  *
14953  * We can calculate what we think WM's should be by creating a duplicate of the
14954  * current state (which was constructed during hardware readout) and running it
14955  * through the atomic check code to calculate new watermark values in the
14956  * state object.
14957  */
14958 static void sanitize_watermarks(struct drm_device *dev)
14959 {
14960         struct drm_i915_private *dev_priv = to_i915(dev);
14961         struct drm_atomic_state *state;
14962         struct intel_atomic_state *intel_state;
14963         struct drm_crtc *crtc;
14964         struct drm_crtc_state *cstate;
14965         struct drm_modeset_acquire_ctx ctx;
14966         int ret;
14967         int i;
14968
14969         /* Only supported on platforms that use atomic watermark design */
14970         if (!dev_priv->display.optimize_watermarks)
14971                 return;
14972
14973         /*
14974          * We need to hold connection_mutex before calling duplicate_state so
14975          * that the connector loop is protected.
14976          */
14977         drm_modeset_acquire_init(&ctx, 0);
14978 retry:
14979         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14980         if (ret == -EDEADLK) {
14981                 drm_modeset_backoff(&ctx);
14982                 goto retry;
14983         } else if (WARN_ON(ret)) {
14984                 goto fail;
14985         }
14986
14987         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14988         if (WARN_ON(IS_ERR(state)))
14989                 goto fail;
14990
14991         intel_state = to_intel_atomic_state(state);
14992
14993         /*
14994          * Hardware readout is the only time we don't want to calculate
14995          * intermediate watermarks (since we don't trust the current
14996          * watermarks).
14997          */
14998         if (!HAS_GMCH_DISPLAY(dev_priv))
14999                 intel_state->skip_intermediate_wm = true;
15000
15001         ret = intel_atomic_check(dev, state);
15002         if (ret) {
15003                 /*
15004                  * If we fail here, it means that the hardware appears to be
15005                  * programmed in a way that shouldn't be possible, given our
15006                  * understanding of watermark requirements.  This might mean a
15007                  * mistake in the hardware readout code or a mistake in the
15008                  * watermark calculations for a given platform.  Raise a WARN
15009                  * so that this is noticeable.
15010                  *
15011                  * If this actually happens, we'll have to just leave the
15012                  * BIOS-programmed watermarks untouched and hope for the best.
15013                  */
15014                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15015                 goto put_state;
15016         }
15017
15018         /* Write calculated watermark values back */
15019         for_each_new_crtc_in_state(state, crtc, cstate, i) {
15020                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15021
15022                 cs->wm.need_postvbl_update = true;
15023                 dev_priv->display.optimize_watermarks(intel_state, cs);
15024         }
15025
15026 put_state:
15027         drm_atomic_state_put(state);
15028 fail:
15029         drm_modeset_drop_locks(&ctx);
15030         drm_modeset_acquire_fini(&ctx);
15031 }
15032
15033 int intel_modeset_init(struct drm_device *dev)
15034 {
15035         struct drm_i915_private *dev_priv = to_i915(dev);
15036         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15037         enum pipe pipe;
15038         struct intel_crtc *crtc;
15039
15040         drm_mode_config_init(dev);
15041
15042         dev->mode_config.min_width = 0;
15043         dev->mode_config.min_height = 0;
15044
15045         dev->mode_config.preferred_depth = 24;
15046         dev->mode_config.prefer_shadow = 1;
15047
15048         dev->mode_config.allow_fb_modifiers = true;
15049
15050         dev->mode_config.funcs = &intel_mode_funcs;
15051
15052         init_llist_head(&dev_priv->atomic_helper.free_list);
15053         INIT_WORK(&dev_priv->atomic_helper.free_work,
15054                   intel_atomic_helper_free_state_worker);
15055
15056         intel_init_quirks(dev);
15057
15058         intel_init_pm(dev_priv);
15059
15060         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15061                 return 0;
15062
15063         /*
15064          * There may be no VBT; and if the BIOS enabled SSC we can
15065          * just keep using it to avoid unnecessary flicker.  Whereas if the
15066          * BIOS isn't using it, don't assume it will work even if the VBT
15067          * indicates as much.
15068          */
15069         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15070                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15071                                             DREF_SSC1_ENABLE);
15072
15073                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15074                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15075                                      bios_lvds_use_ssc ? "en" : "dis",
15076                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15077                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15078                 }
15079         }
15080
15081         if (IS_GEN2(dev_priv)) {
15082                 dev->mode_config.max_width = 2048;
15083                 dev->mode_config.max_height = 2048;
15084         } else if (IS_GEN3(dev_priv)) {
15085                 dev->mode_config.max_width = 4096;
15086                 dev->mode_config.max_height = 4096;
15087         } else {
15088                 dev->mode_config.max_width = 8192;
15089                 dev->mode_config.max_height = 8192;
15090         }
15091
15092         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15093                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15094                 dev->mode_config.cursor_height = 1023;
15095         } else if (IS_GEN2(dev_priv)) {
15096                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15097                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15098         } else {
15099                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15100                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15101         }
15102
15103         dev->mode_config.fb_base = ggtt->mappable_base;
15104
15105         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15106                       INTEL_INFO(dev_priv)->num_pipes,
15107                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15108
15109         for_each_pipe(dev_priv, pipe) {
15110                 int ret;
15111
15112                 ret = intel_crtc_init(dev_priv, pipe);
15113                 if (ret) {
15114                         drm_mode_config_cleanup(dev);
15115                         return ret;
15116                 }
15117         }
15118
15119         intel_shared_dpll_init(dev);
15120
15121         intel_update_czclk(dev_priv);
15122         intel_modeset_init_hw(dev);
15123
15124         if (dev_priv->max_cdclk_freq == 0)
15125                 intel_update_max_cdclk(dev_priv);
15126
15127         /* Just disable it once at startup */
15128         i915_disable_vga(dev_priv);
15129         intel_setup_outputs(dev_priv);
15130
15131         drm_modeset_lock_all(dev);
15132         intel_modeset_setup_hw_state(dev);
15133         drm_modeset_unlock_all(dev);
15134
15135         for_each_intel_crtc(dev, crtc) {
15136                 struct intel_initial_plane_config plane_config = {};
15137
15138                 if (!crtc->active)
15139                         continue;
15140
15141                 /*
15142                  * Note that reserving the BIOS fb up front prevents us
15143                  * from stuffing other stolen allocations like the ring
15144                  * on top.  This prevents some ugliness at boot time, and
15145                  * can even allow for smooth boot transitions if the BIOS
15146                  * fb is large enough for the active pipe configuration.
15147                  */
15148                 dev_priv->display.get_initial_plane_config(crtc,
15149                                                            &plane_config);
15150
15151                 /*
15152                  * If the fb is shared between multiple heads, we'll
15153                  * just get the first one.
15154                  */
15155                 intel_find_initial_plane_obj(crtc, &plane_config);
15156         }
15157
15158         /*
15159          * Make sure hardware watermarks really match the state we read out.
15160          * Note that we need to do this after reconstructing the BIOS fb's
15161          * since the watermark calculation done here will use pstate->fb.
15162          */
15163         if (!HAS_GMCH_DISPLAY(dev_priv))
15164                 sanitize_watermarks(dev);
15165
15166         return 0;
15167 }
15168
15169 static void intel_enable_pipe_a(struct drm_device *dev)
15170 {
15171         struct intel_connector *connector;
15172         struct drm_connector_list_iter conn_iter;
15173         struct drm_connector *crt = NULL;
15174         struct intel_load_detect_pipe load_detect_temp;
15175         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15176         int ret;
15177
15178         /* We can't just switch on the pipe A, we need to set things up with a
15179          * proper mode and output configuration. As a gross hack, enable pipe A
15180          * by enabling the load detect pipe once. */
15181         drm_connector_list_iter_begin(dev, &conn_iter);
15182         for_each_intel_connector_iter(connector, &conn_iter) {
15183                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15184                         crt = &connector->base;
15185                         break;
15186                 }
15187         }
15188         drm_connector_list_iter_end(&conn_iter);
15189
15190         if (!crt)
15191                 return;
15192
15193         ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx);
15194         WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n");
15195
15196         if (ret > 0)
15197                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15198 }
15199
15200 static bool
15201 intel_check_plane_mapping(struct intel_crtc *crtc)
15202 {
15203         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15204         u32 val;
15205
15206         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15207                 return true;
15208
15209         val = I915_READ(DSPCNTR(!crtc->plane));
15210
15211         if ((val & DISPLAY_PLANE_ENABLE) &&
15212             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15213                 return false;
15214
15215         return true;
15216 }
15217
15218 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15219 {
15220         struct drm_device *dev = crtc->base.dev;
15221         struct intel_encoder *encoder;
15222
15223         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15224                 return true;
15225
15226         return false;
15227 }
15228
15229 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15230 {
15231         struct drm_device *dev = encoder->base.dev;
15232         struct intel_connector *connector;
15233
15234         for_each_connector_on_encoder(dev, &encoder->base, connector)
15235                 return connector;
15236
15237         return NULL;
15238 }
15239
15240 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15241                               enum transcoder pch_transcoder)
15242 {
15243         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15244                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15245 }
15246
15247 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15248 {
15249         struct drm_device *dev = crtc->base.dev;
15250         struct drm_i915_private *dev_priv = to_i915(dev);
15251         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15252
15253         /* Clear any frame start delays used for debugging left by the BIOS */
15254         if (!transcoder_is_dsi(cpu_transcoder)) {
15255                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15256
15257                 I915_WRITE(reg,
15258                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15259         }
15260
15261         /* restore vblank interrupts to correct state */
15262         drm_crtc_vblank_reset(&crtc->base);
15263         if (crtc->active) {
15264                 struct intel_plane *plane;
15265
15266                 drm_crtc_vblank_on(&crtc->base);
15267
15268                 /* Disable everything but the primary plane */
15269                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15270                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15271                                 continue;
15272
15273                         trace_intel_disable_plane(&plane->base, crtc);
15274                         plane->disable_plane(plane, crtc);
15275                 }
15276         }
15277
15278         /* We need to sanitize the plane -> pipe mapping first because this will
15279          * disable the crtc (and hence change the state) if it is wrong. Note
15280          * that gen4+ has a fixed plane -> pipe mapping.  */
15281         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15282                 bool plane;
15283
15284                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15285                               crtc->base.base.id, crtc->base.name);
15286
15287                 /* Pipe has the wrong plane attached and the plane is active.
15288                  * Temporarily change the plane mapping and disable everything
15289                  * ...  */
15290                 plane = crtc->plane;
15291                 crtc->base.primary->state->visible = true;
15292                 crtc->plane = !plane;
15293                 intel_crtc_disable_noatomic(&crtc->base);
15294                 crtc->plane = plane;
15295         }
15296
15297         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15298             crtc->pipe == PIPE_A && !crtc->active) {
15299                 /* BIOS forgot to enable pipe A, this mostly happens after
15300                  * resume. Force-enable the pipe to fix this, the update_dpms
15301                  * call below we restore the pipe to the right state, but leave
15302                  * the required bits on. */
15303                 intel_enable_pipe_a(dev);
15304         }
15305
15306         /* Adjust the state of the output pipe according to whether we
15307          * have active connectors/encoders. */
15308         if (crtc->active && !intel_crtc_has_encoders(crtc))
15309                 intel_crtc_disable_noatomic(&crtc->base);
15310
15311         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15312                 /*
15313                  * We start out with underrun reporting disabled to avoid races.
15314                  * For correct bookkeeping mark this on active crtcs.
15315                  *
15316                  * Also on gmch platforms we dont have any hardware bits to
15317                  * disable the underrun reporting. Which means we need to start
15318                  * out with underrun reporting disabled also on inactive pipes,
15319                  * since otherwise we'll complain about the garbage we read when
15320                  * e.g. coming up after runtime pm.
15321                  *
15322                  * No protection against concurrent access is required - at
15323                  * worst a fifo underrun happens which also sets this to false.
15324                  */
15325                 crtc->cpu_fifo_underrun_disabled = true;
15326                 /*
15327                  * We track the PCH trancoder underrun reporting state
15328                  * within the crtc. With crtc for pipe A housing the underrun
15329                  * reporting state for PCH transcoder A, crtc for pipe B housing
15330                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15331                  * and marking underrun reporting as disabled for the non-existing
15332                  * PCH transcoders B and C would prevent enabling the south
15333                  * error interrupt (see cpt_can_enable_serr_int()).
15334                  */
15335                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15336                         crtc->pch_fifo_underrun_disabled = true;
15337         }
15338 }
15339
15340 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15341 {
15342         struct intel_connector *connector;
15343
15344         /* We need to check both for a crtc link (meaning that the
15345          * encoder is active and trying to read from a pipe) and the
15346          * pipe itself being active. */
15347         bool has_active_crtc = encoder->base.crtc &&
15348                 to_intel_crtc(encoder->base.crtc)->active;
15349
15350         connector = intel_encoder_find_connector(encoder);
15351         if (connector && !has_active_crtc) {
15352                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15353                               encoder->base.base.id,
15354                               encoder->base.name);
15355
15356                 /* Connector is active, but has no active pipe. This is
15357                  * fallout from our resume register restoring. Disable
15358                  * the encoder manually again. */
15359                 if (encoder->base.crtc) {
15360                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15361
15362                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15363                                       encoder->base.base.id,
15364                                       encoder->base.name);
15365                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15366                         if (encoder->post_disable)
15367                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15368                 }
15369                 encoder->base.crtc = NULL;
15370
15371                 /* Inconsistent output/port/pipe state happens presumably due to
15372                  * a bug in one of the get_hw_state functions. Or someplace else
15373                  * in our code, like the register restore mess on resume. Clamp
15374                  * things to off as a safer default. */
15375
15376                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15377                 connector->base.encoder = NULL;
15378         }
15379         /* Enabled encoders without active connectors will be fixed in
15380          * the crtc fixup. */
15381 }
15382
15383 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15384 {
15385         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15386
15387         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15388                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15389                 i915_disable_vga(dev_priv);
15390         }
15391 }
15392
15393 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15394 {
15395         /* This function can be called both from intel_modeset_setup_hw_state or
15396          * at a very early point in our resume sequence, where the power well
15397          * structures are not yet restored. Since this function is at a very
15398          * paranoid "someone might have enabled VGA while we were not looking"
15399          * level, just check if the power well is enabled instead of trying to
15400          * follow the "don't touch the power well if we don't need it" policy
15401          * the rest of the driver uses. */
15402         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15403                 return;
15404
15405         i915_redisable_vga_power_on(dev_priv);
15406
15407         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15408 }
15409
15410 static bool primary_get_hw_state(struct intel_plane *plane)
15411 {
15412         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15413
15414         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15415 }
15416
15417 /* FIXME read out full plane state for all planes */
15418 static void readout_plane_state(struct intel_crtc *crtc)
15419 {
15420         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15421         bool visible;
15422
15423         visible = crtc->active && primary_get_hw_state(primary);
15424
15425         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15426                                 to_intel_plane_state(primary->base.state),
15427                                 visible);
15428 }
15429
15430 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15431 {
15432         struct drm_i915_private *dev_priv = to_i915(dev);
15433         enum pipe pipe;
15434         struct intel_crtc *crtc;
15435         struct intel_encoder *encoder;
15436         struct intel_connector *connector;
15437         struct drm_connector_list_iter conn_iter;
15438         int i;
15439
15440         dev_priv->active_crtcs = 0;
15441
15442         for_each_intel_crtc(dev, crtc) {
15443                 struct intel_crtc_state *crtc_state =
15444                         to_intel_crtc_state(crtc->base.state);
15445
15446                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15447                 memset(crtc_state, 0, sizeof(*crtc_state));
15448                 crtc_state->base.crtc = &crtc->base;
15449
15450                 crtc_state->base.active = crtc_state->base.enable =
15451                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15452
15453                 crtc->base.enabled = crtc_state->base.enable;
15454                 crtc->active = crtc_state->base.active;
15455
15456                 if (crtc_state->base.active)
15457                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15458
15459                 readout_plane_state(crtc);
15460
15461                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15462                               crtc->base.base.id, crtc->base.name,
15463                               enableddisabled(crtc_state->base.active));
15464         }
15465
15466         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15467                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15468
15469                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15470                                                   &pll->state.hw_state);
15471                 pll->state.crtc_mask = 0;
15472                 for_each_intel_crtc(dev, crtc) {
15473                         struct intel_crtc_state *crtc_state =
15474                                 to_intel_crtc_state(crtc->base.state);
15475
15476                         if (crtc_state->base.active &&
15477                             crtc_state->shared_dpll == pll)
15478                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15479                 }
15480                 pll->active_mask = pll->state.crtc_mask;
15481
15482                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15483                               pll->name, pll->state.crtc_mask, pll->on);
15484         }
15485
15486         for_each_intel_encoder(dev, encoder) {
15487                 pipe = 0;
15488
15489                 if (encoder->get_hw_state(encoder, &pipe)) {
15490                         struct intel_crtc_state *crtc_state;
15491
15492                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15493                         crtc_state = to_intel_crtc_state(crtc->base.state);
15494
15495                         encoder->base.crtc = &crtc->base;
15496                         crtc_state->output_types |= 1 << encoder->type;
15497                         encoder->get_config(encoder, crtc_state);
15498                 } else {
15499                         encoder->base.crtc = NULL;
15500                 }
15501
15502                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15503                               encoder->base.base.id, encoder->base.name,
15504                               enableddisabled(encoder->base.crtc),
15505                               pipe_name(pipe));
15506         }
15507
15508         drm_connector_list_iter_begin(dev, &conn_iter);
15509         for_each_intel_connector_iter(connector, &conn_iter) {
15510                 if (connector->get_hw_state(connector)) {
15511                         connector->base.dpms = DRM_MODE_DPMS_ON;
15512
15513                         encoder = connector->encoder;
15514                         connector->base.encoder = &encoder->base;
15515
15516                         if (encoder->base.crtc &&
15517                             encoder->base.crtc->state->active) {
15518                                 /*
15519                                  * This has to be done during hardware readout
15520                                  * because anything calling .crtc_disable may
15521                                  * rely on the connector_mask being accurate.
15522                                  */
15523                                 encoder->base.crtc->state->connector_mask |=
15524                                         1 << drm_connector_index(&connector->base);
15525                                 encoder->base.crtc->state->encoder_mask |=
15526                                         1 << drm_encoder_index(&encoder->base);
15527                         }
15528
15529                 } else {
15530                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15531                         connector->base.encoder = NULL;
15532                 }
15533                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15534                               connector->base.base.id, connector->base.name,
15535                               enableddisabled(connector->base.encoder));
15536         }
15537         drm_connector_list_iter_end(&conn_iter);
15538
15539         for_each_intel_crtc(dev, crtc) {
15540                 struct intel_crtc_state *crtc_state =
15541                         to_intel_crtc_state(crtc->base.state);
15542                 int pixclk = 0;
15543
15544                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15545                 if (crtc_state->base.active) {
15546                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15547                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15548                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15549
15550                         /*
15551                          * The initial mode needs to be set in order to keep
15552                          * the atomic core happy. It wants a valid mode if the
15553                          * crtc's enabled, so we do the above call.
15554                          *
15555                          * But we don't set all the derived state fully, hence
15556                          * set a flag to indicate that a full recalculation is
15557                          * needed on the next commit.
15558                          */
15559                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15560
15561                         intel_crtc_compute_pixel_rate(crtc_state);
15562
15563                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15564                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15565                                 pixclk = crtc_state->pixel_rate;
15566                         else
15567                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15568
15569                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15570                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15571                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15572
15573                         drm_calc_timestamping_constants(&crtc->base,
15574                                                         &crtc_state->base.adjusted_mode);
15575                         update_scanline_offset(crtc);
15576                 }
15577
15578                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15579
15580                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15581         }
15582 }
15583
15584 static void
15585 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15586 {
15587         struct intel_encoder *encoder;
15588
15589         for_each_intel_encoder(&dev_priv->drm, encoder) {
15590                 u64 get_domains;
15591                 enum intel_display_power_domain domain;
15592
15593                 if (!encoder->get_power_domains)
15594                         continue;
15595
15596                 get_domains = encoder->get_power_domains(encoder);
15597                 for_each_power_domain(domain, get_domains)
15598                         intel_display_power_get(dev_priv, domain);
15599         }
15600 }
15601
15602 /* Scan out the current hw modeset state,
15603  * and sanitizes it to the current state
15604  */
15605 static void
15606 intel_modeset_setup_hw_state(struct drm_device *dev)
15607 {
15608         struct drm_i915_private *dev_priv = to_i915(dev);
15609         enum pipe pipe;
15610         struct intel_crtc *crtc;
15611         struct intel_encoder *encoder;
15612         int i;
15613
15614         intel_modeset_readout_hw_state(dev);
15615
15616         /* HW state is read out, now we need to sanitize this mess. */
15617         get_encoder_power_domains(dev_priv);
15618
15619         for_each_intel_encoder(dev, encoder) {
15620                 intel_sanitize_encoder(encoder);
15621         }
15622
15623         for_each_pipe(dev_priv, pipe) {
15624                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15625
15626                 intel_sanitize_crtc(crtc);
15627                 intel_dump_pipe_config(crtc, crtc->config,
15628                                        "[setup_hw_state]");
15629         }
15630
15631         intel_modeset_update_connector_atomic_state(dev);
15632
15633         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15634                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15635
15636                 if (!pll->on || pll->active_mask)
15637                         continue;
15638
15639                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15640
15641                 pll->funcs.disable(dev_priv, pll);
15642                 pll->on = false;
15643         }
15644
15645         if (IS_G4X(dev_priv)) {
15646                 g4x_wm_get_hw_state(dev);
15647                 g4x_wm_sanitize(dev_priv);
15648         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15649                 vlv_wm_get_hw_state(dev);
15650                 vlv_wm_sanitize(dev_priv);
15651         } else if (IS_GEN9(dev_priv)) {
15652                 skl_wm_get_hw_state(dev);
15653         } else if (HAS_PCH_SPLIT(dev_priv)) {
15654                 ilk_wm_get_hw_state(dev);
15655         }
15656
15657         for_each_intel_crtc(dev, crtc) {
15658                 u64 put_domains;
15659
15660                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15661                 if (WARN_ON(put_domains))
15662                         modeset_put_power_domains(dev_priv, put_domains);
15663         }
15664         intel_display_set_init_power(dev_priv, false);
15665
15666         intel_power_domains_verify_state(dev_priv);
15667
15668         intel_fbc_init_pipe_state(dev_priv);
15669 }
15670
15671 void intel_display_resume(struct drm_device *dev)
15672 {
15673         struct drm_i915_private *dev_priv = to_i915(dev);
15674         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15675         struct drm_modeset_acquire_ctx ctx;
15676         int ret;
15677
15678         dev_priv->modeset_restore_state = NULL;
15679         if (state)
15680                 state->acquire_ctx = &ctx;
15681
15682         drm_modeset_acquire_init(&ctx, 0);
15683
15684         while (1) {
15685                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15686                 if (ret != -EDEADLK)
15687                         break;
15688
15689                 drm_modeset_backoff(&ctx);
15690         }
15691
15692         if (!ret)
15693                 ret = __intel_display_resume(dev, state, &ctx);
15694
15695         drm_modeset_drop_locks(&ctx);
15696         drm_modeset_acquire_fini(&ctx);
15697
15698         if (ret)
15699                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15700         if (state)
15701                 drm_atomic_state_put(state);
15702 }
15703
15704 void intel_modeset_gem_init(struct drm_device *dev)
15705 {
15706         struct drm_i915_private *dev_priv = to_i915(dev);
15707
15708         intel_init_gt_powersave(dev_priv);
15709
15710         intel_setup_overlay(dev_priv);
15711 }
15712
15713 int intel_connector_register(struct drm_connector *connector)
15714 {
15715         struct intel_connector *intel_connector = to_intel_connector(connector);
15716         int ret;
15717
15718         ret = intel_backlight_device_register(intel_connector);
15719         if (ret)
15720                 goto err;
15721
15722         return 0;
15723
15724 err:
15725         return ret;
15726 }
15727
15728 void intel_connector_unregister(struct drm_connector *connector)
15729 {
15730         struct intel_connector *intel_connector = to_intel_connector(connector);
15731
15732         intel_backlight_device_unregister(intel_connector);
15733         intel_panel_destroy_backlight(connector);
15734 }
15735
15736 void intel_modeset_cleanup(struct drm_device *dev)
15737 {
15738         struct drm_i915_private *dev_priv = to_i915(dev);
15739
15740         flush_work(&dev_priv->atomic_helper.free_work);
15741         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15742
15743         intel_disable_gt_powersave(dev_priv);
15744
15745         /*
15746          * Interrupts and polling as the first thing to avoid creating havoc.
15747          * Too much stuff here (turning of connectors, ...) would
15748          * experience fancy races otherwise.
15749          */
15750         intel_irq_uninstall(dev_priv);
15751
15752         /*
15753          * Due to the hpd irq storm handling the hotplug work can re-arm the
15754          * poll handlers. Hence disable polling after hpd handling is shut down.
15755          */
15756         drm_kms_helper_poll_fini(dev);
15757
15758         intel_unregister_dsm_handler();
15759
15760         intel_fbc_global_disable(dev_priv);
15761
15762         /* flush any delayed tasks or pending work */
15763         flush_scheduled_work();
15764
15765         drm_mode_config_cleanup(dev);
15766
15767         intel_cleanup_overlay(dev_priv);
15768
15769         intel_cleanup_gt_powersave(dev_priv);
15770
15771         intel_teardown_gmbus(dev_priv);
15772 }
15773
15774 void intel_connector_attach_encoder(struct intel_connector *connector,
15775                                     struct intel_encoder *encoder)
15776 {
15777         connector->encoder = encoder;
15778         drm_mode_connector_attach_encoder(&connector->base,
15779                                           &encoder->base);
15780 }
15781
15782 /*
15783  * set vga decode state - true == enable VGA decode
15784  */
15785 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15786 {
15787         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15788         u16 gmch_ctrl;
15789
15790         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15791                 DRM_ERROR("failed to read control word\n");
15792                 return -EIO;
15793         }
15794
15795         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15796                 return 0;
15797
15798         if (state)
15799                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15800         else
15801                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15802
15803         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15804                 DRM_ERROR("failed to write control word\n");
15805                 return -EIO;
15806         }
15807
15808         return 0;
15809 }
15810
15811 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15812
15813 struct intel_display_error_state {
15814
15815         u32 power_well_driver;
15816
15817         int num_transcoders;
15818
15819         struct intel_cursor_error_state {
15820                 u32 control;
15821                 u32 position;
15822                 u32 base;
15823                 u32 size;
15824         } cursor[I915_MAX_PIPES];
15825
15826         struct intel_pipe_error_state {
15827                 bool power_domain_on;
15828                 u32 source;
15829                 u32 stat;
15830         } pipe[I915_MAX_PIPES];
15831
15832         struct intel_plane_error_state {
15833                 u32 control;
15834                 u32 stride;
15835                 u32 size;
15836                 u32 pos;
15837                 u32 addr;
15838                 u32 surface;
15839                 u32 tile_offset;
15840         } plane[I915_MAX_PIPES];
15841
15842         struct intel_transcoder_error_state {
15843                 bool power_domain_on;
15844                 enum transcoder cpu_transcoder;
15845
15846                 u32 conf;
15847
15848                 u32 htotal;
15849                 u32 hblank;
15850                 u32 hsync;
15851                 u32 vtotal;
15852                 u32 vblank;
15853                 u32 vsync;
15854         } transcoder[4];
15855 };
15856
15857 struct intel_display_error_state *
15858 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15859 {
15860         struct intel_display_error_state *error;
15861         int transcoders[] = {
15862                 TRANSCODER_A,
15863                 TRANSCODER_B,
15864                 TRANSCODER_C,
15865                 TRANSCODER_EDP,
15866         };
15867         int i;
15868
15869         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15870                 return NULL;
15871
15872         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15873         if (error == NULL)
15874                 return NULL;
15875
15876         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15877                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15878
15879         for_each_pipe(dev_priv, i) {
15880                 error->pipe[i].power_domain_on =
15881                         __intel_display_power_is_enabled(dev_priv,
15882                                                          POWER_DOMAIN_PIPE(i));
15883                 if (!error->pipe[i].power_domain_on)
15884                         continue;
15885
15886                 error->cursor[i].control = I915_READ(CURCNTR(i));
15887                 error->cursor[i].position = I915_READ(CURPOS(i));
15888                 error->cursor[i].base = I915_READ(CURBASE(i));
15889
15890                 error->plane[i].control = I915_READ(DSPCNTR(i));
15891                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15892                 if (INTEL_GEN(dev_priv) <= 3) {
15893                         error->plane[i].size = I915_READ(DSPSIZE(i));
15894                         error->plane[i].pos = I915_READ(DSPPOS(i));
15895                 }
15896                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15897                         error->plane[i].addr = I915_READ(DSPADDR(i));
15898                 if (INTEL_GEN(dev_priv) >= 4) {
15899                         error->plane[i].surface = I915_READ(DSPSURF(i));
15900                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15901                 }
15902
15903                 error->pipe[i].source = I915_READ(PIPESRC(i));
15904
15905                 if (HAS_GMCH_DISPLAY(dev_priv))
15906                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15907         }
15908
15909         /* Note: this does not include DSI transcoders. */
15910         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15911         if (HAS_DDI(dev_priv))
15912                 error->num_transcoders++; /* Account for eDP. */
15913
15914         for (i = 0; i < error->num_transcoders; i++) {
15915                 enum transcoder cpu_transcoder = transcoders[i];
15916
15917                 error->transcoder[i].power_domain_on =
15918                         __intel_display_power_is_enabled(dev_priv,
15919                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15920                 if (!error->transcoder[i].power_domain_on)
15921                         continue;
15922
15923                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15924
15925                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15926                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15927                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15928                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15929                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15930                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15931                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15932         }
15933
15934         return error;
15935 }
15936
15937 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15938
15939 void
15940 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15941                                 struct intel_display_error_state *error)
15942 {
15943         struct drm_i915_private *dev_priv = m->i915;
15944         int i;
15945
15946         if (!error)
15947                 return;
15948
15949         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15950         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15951                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15952                            error->power_well_driver);
15953         for_each_pipe(dev_priv, i) {
15954                 err_printf(m, "Pipe [%d]:\n", i);
15955                 err_printf(m, "  Power: %s\n",
15956                            onoff(error->pipe[i].power_domain_on));
15957                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15958                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15959
15960                 err_printf(m, "Plane [%d]:\n", i);
15961                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15962                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15963                 if (INTEL_GEN(dev_priv) <= 3) {
15964                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15965                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15966                 }
15967                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15968                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15969                 if (INTEL_GEN(dev_priv) >= 4) {
15970                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15971                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15972                 }
15973
15974                 err_printf(m, "Cursor [%d]:\n", i);
15975                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15976                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15977                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15978         }
15979
15980         for (i = 0; i < error->num_transcoders; i++) {
15981                 err_printf(m, "CPU transcoder: %s\n",
15982                            transcoder_name(error->transcoder[i].cpu_transcoder));
15983                 err_printf(m, "  Power: %s\n",
15984                            onoff(error->transcoder[i].power_domain_on));
15985                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15986                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15987                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15988                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15989                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15990                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15991                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15992         }
15993 }
15994
15995 #endif