drivers/gpu/drm/arm/malidp_crtc.c

   1 /*
   2  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   3  * Author: Liviu Dudau <[email protected]>
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * ARM Mali DP500/DP550/DP650 driver (crtc operations)
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <video/videomode.h>
  21
  22 #include "malidp_drv.h"
  23 #include "malidp_hw.h"
  24
  25 static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc,
  26                                                    const struct drm_display_mode *mode)
  27 {
  28         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  29         struct malidp_hw_device *hwdev = malidp->dev;
  30
  31         /*
  32          * check that the hardware can drive the required clock rate,
  33          * but skip the check if the clock is meant to be disabled (req_rate = 0)
  34          */
  35         long rate, req_rate = mode->crtc_clock * 1000;
  36
  37         if (req_rate) {
  38                 rate = clk_round_rate(hwdev->pxlclk, req_rate);
  39                 if (rate != req_rate) {
  40                         DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
  41                                          req_rate);
  42                         return MODE_NOCLOCK;
  43                 }
  44         }
  45
  46         return MODE_OK;
  47 }
  48
  49 static void malidp_crtc_enable(struct drm_crtc *crtc)
  50 {
  51         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  52         struct malidp_hw_device *hwdev = malidp->dev;
  53         struct videomode vm;
  54         int err = pm_runtime_get_sync(crtc->dev->dev);
  55
  56         if (err < 0) {
  57                 DRM_DEBUG_DRIVER("Failed to enable runtime power management: %d\n", err);
  58                 return;
  59         }
  60
  61         drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm);
  62         clk_prepare_enable(hwdev->pxlclk);
  63
  64         /* We rely on firmware to set mclk to a sensible level. */
  65         clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
  66
  67         hwdev->modeset(hwdev, &vm);
  68         hwdev->leave_config_mode(hwdev);
  69         drm_crtc_vblank_on(crtc);
  70 }
  71
  72 static void malidp_crtc_disable(struct drm_crtc *crtc)
  73 {
  74         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  75         struct malidp_hw_device *hwdev = malidp->dev;
  76         int err;
  77
  78         drm_crtc_vblank_off(crtc);
  79         hwdev->enter_config_mode(hwdev);
  80         clk_disable_unprepare(hwdev->pxlclk);
  81
  82         err = pm_runtime_put(crtc->dev->dev);
  83         if (err < 0) {
  84                 DRM_DEBUG_DRIVER("Failed to disable runtime power management: %d\n", err);
  85         }
  86 }
  87
  88 static const struct gamma_curve_segment {
  89         u16 start;
  90         u16 end;
  91 } segments[MALIDP_COEFFTAB_NUM_COEFFS] = {
  92         /* sector 0 */
  93         {    0,    0 }, {    1,    1 }, {    2,    2 }, {    3,    3 },
  94         {    4,    4 }, {    5,    5 }, {    6,    6 }, {    7,    7 },
  95         {    8,    8 }, {    9,    9 }, {   10,   10 }, {   11,   11 },
  96         {   12,   12 }, {   13,   13 }, {   14,   14 }, {   15,   15 },
  97         /* sector 1 */
  98         {   16,   19 }, {   20,   23 }, {   24,   27 }, {   28,   31 },
  99         /* sector 2 */
 100         {   32,   39 }, {   40,   47 }, {   48,   55 }, {   56,   63 },
 101         /* sector 3 */
 102         {   64,   79 }, {   80,   95 }, {   96,  111 }, {  112,  127 },
 103         /* sector 4 */
 104         {  128,  159 }, {  160,  191 }, {  192,  223 }, {  224,  255 },
 105         /* sector 5 */
 106         {  256,  319 }, {  320,  383 }, {  384,  447 }, {  448,  511 },
 107         /* sector 6 */
 108         {  512,  639 }, {  640,  767 }, {  768,  895 }, {  896, 1023 },
 109         { 1024, 1151 }, { 1152, 1279 }, { 1280, 1407 }, { 1408, 1535 },
 110         { 1536, 1663 }, { 1664, 1791 }, { 1792, 1919 }, { 1920, 2047 },
 111         { 2048, 2175 }, { 2176, 2303 }, { 2304, 2431 }, { 2432, 2559 },
 112         { 2560, 2687 }, { 2688, 2815 }, { 2816, 2943 }, { 2944, 3071 },
 113         { 3072, 3199 }, { 3200, 3327 }, { 3328, 3455 }, { 3456, 3583 },
 114         { 3584, 3711 }, { 3712, 3839 }, { 3840, 3967 }, { 3968, 4095 },
 115 };
 116
 117 #define DE_COEFTAB_DATA(a, b) ((((a) & 0xfff) << 16) | (((b) & 0xfff)))
 118
 119 static void malidp_generate_gamma_table(struct drm_property_blob *lut_blob,
 120                                         u32 coeffs[MALIDP_COEFFTAB_NUM_COEFFS])
 121 {
 122         struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data;
 123         int i;
 124
 125         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) {
 126                 u32 a, b, delta_in, out_start, out_end;
 127
 128                 delta_in = segments[i].end - segments[i].start;
 129                 /* DP has 12-bit internal precision for its LUTs. */
 130                 out_start = drm_color_lut_extract(lut[segments[i].start].green,
 131                                                   12);
 132                 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12);
 133                 a = (delta_in == 0) ? 0 : ((out_end - out_start) * 256) / delta_in;
 134                 b = out_start;
 135                 coeffs[i] = DE_COEFTAB_DATA(a, b);
 136         }
 137 }
 138
 139 /*
 140  * Check if there is a new gamma LUT and if it is of an acceptable size. Also,
 141  * reject any LUTs that use distinct red, green, and blue curves.
 142  */
 143 static int malidp_crtc_atomic_check_gamma(struct drm_crtc *crtc,
 144                                           struct drm_crtc_state *state)
 145 {
 146         struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
 147         struct drm_color_lut *lut;
 148         size_t lut_size;
 149         int i;
 150
 151         if (!state->color_mgmt_changed || !state->gamma_lut)
 152                 return 0;
 153
 154         if (crtc->state->gamma_lut &&
 155             (crtc->state->gamma_lut->base.id == state->gamma_lut->base.id))
 156                 return 0;
 157
 158         if (state->gamma_lut->length % sizeof(struct drm_color_lut))
 159                 return -EINVAL;
 160
 161         lut_size = state->gamma_lut->length / sizeof(struct drm_color_lut);
 162         if (lut_size != MALIDP_GAMMA_LUT_SIZE)
 163                 return -EINVAL;
 164
 165         lut = (struct drm_color_lut *)state->gamma_lut->data;
 166         for (i = 0; i < lut_size; ++i)
 167                 if (!((lut[i].red == lut[i].green) &&
 168                       (lut[i].red == lut[i].blue)))
 169                         return -EINVAL;
 170
 171         if (!state->mode_changed) {
 172                 int ret;
 173
 174                 state->mode_changed = true;
 175                 /*
 176                  * Kerneldoc for drm_atomic_helper_check_modeset mandates that
 177                  * it be invoked when the driver sets ->mode_changed. Since
 178                  * changing the gamma LUT doesn't depend on any external
 179                  * resources, it is safe to call it only once.
 180                  */
 181                 ret = drm_atomic_helper_check_modeset(crtc->dev, state->state);
 182                 if (ret)
 183                         return ret;
 184         }
 185
 186         malidp_generate_gamma_table(state->gamma_lut, mc->gamma_coeffs);
 187         return 0;
 188 }
 189
 190 /*
 191  * Check if there is a new CTM and if it contains valid input. Valid here means
 192  * that the number is inside the representable range for a Q3.12 number,
 193  * excluding truncating the fractional part of the input data.
 194  *
 195  * The COLORADJ registers can be changed atomically.
 196  */
 197 static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc,
 198                                         struct drm_crtc_state *state)
 199 {
 200         struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
 201         struct drm_color_ctm *ctm;
 202         int i;
 203
 204         if (!state->color_mgmt_changed)
 205                 return 0;
 206
 207         if (!state->ctm)
 208                 return 0;
 209
 210         if (crtc->state->ctm && (crtc->state->ctm->base.id ==
 211                                  state->ctm->base.id))
 212                 return 0;
 213
 214         /*
 215          * The size of the ctm is checked in
 216          * drm_atomic_replace_property_blob_from_id.
 217          */
 218         ctm = (struct drm_color_ctm *)state->ctm->data;
 219         for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) {
 220                 /* Convert from S31.32 to Q3.12. */
 221                 s64 val = ctm->matrix[i];
 222                 u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) &
 223                           GENMASK_ULL(14, 0);
 224
 225                 /*
 226                  * Convert to 2s complement and check the destination's top bit
 227                  * for overflow. NB: Can't check before converting or it'd
 228                  * incorrectly reject the case:
 229                  * sign == 1
 230                  * mag == 0x2000
 231                  */
 232                 if (val & BIT_ULL(63))
 233                         mag = ~mag + 1;
 234                 if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14)))
 235                         return -EINVAL;
 236                 mc->coloradj_coeffs[i] = mag;
 237         }
 238
 239         return 0;
 240 }
 241
 242 static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
 243                                             struct drm_crtc_state *state)
 244 {
 245         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 246         struct malidp_hw_device *hwdev = malidp->dev;
 247         struct malidp_crtc_state *cs = to_malidp_crtc_state(state);
 248         struct malidp_se_config *s = &cs->scaler_config;
 249         struct drm_plane *plane;
 250         struct videomode vm;
 251         const struct drm_plane_state *pstate;
 252         u32 h_upscale_factor = 0; /* U16.16 */
 253         u32 v_upscale_factor = 0; /* U16.16 */
 254         u8 scaling = cs->scaled_planes_mask;
 255         int ret;
 256
 257         if (!scaling) {
 258                 s->scale_enable = false;
 259                 goto mclk_calc;
 260         }
 261
 262         /* The scaling engine can only handle one plane at a time. */
 263         if (scaling & (scaling - 1))
 264                 return -EINVAL;
 265
 266         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 267                 struct malidp_plane *mp = to_malidp_plane(plane);
 268                 u32 phase;
 269
 270                 if (!(mp->layer->id & scaling))
 271                         continue;
 272
 273                 /*
 274                  * Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h]
 275                  * to get the U16.16 result.
 276                  */
 277                 h_upscale_factor = div_u64((u64)pstate->crtc_w << 32,
 278                                            pstate->src_w);
 279                 v_upscale_factor = div_u64((u64)pstate->crtc_h << 32,
 280                                            pstate->src_h);
 281
 282                 s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||
 283                                       (v_upscale_factor >> 16) >= 2);
 284
 285                 s->input_w = pstate->src_w >> 16;
 286                 s->input_h = pstate->src_h >> 16;
 287                 s->output_w = pstate->crtc_w;
 288                 s->output_h = pstate->crtc_h;
 289
 290 #define SE_N_PHASE 4
 291 #define SE_SHIFT_N_PHASE 12
 292                 /* Calculate initial_phase and delta_phase for horizontal. */
 293                 phase = s->input_w;
 294                 s->h_init_phase =
 295                                 ((phase << SE_N_PHASE) / s->output_w + 1) / 2;
 296
 297                 phase = s->input_w;
 298                 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
 299                 s->h_delta_phase = phase / s->output_w;
 300
 301                 /* Same for vertical. */
 302                 phase = s->input_h;
 303                 s->v_init_phase =
 304                                 ((phase << SE_N_PHASE) / s->output_h + 1) / 2;
 305
 306                 phase = s->input_h;
 307                 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
 308                 s->v_delta_phase = phase / s->output_h;
 309 #undef SE_N_PHASE
 310 #undef SE_SHIFT_N_PHASE
 311                 s->plane_src_id = mp->layer->id;
 312         }
 313
 314         s->scale_enable = true;
 315         s->hcoeff = malidp_se_select_coeffs(h_upscale_factor);
 316         s->vcoeff = malidp_se_select_coeffs(v_upscale_factor);
 317
 318 mclk_calc:
 319         drm_display_mode_to_videomode(&state->adjusted_mode, &vm);
 320         ret = hwdev->se_calc_mclk(hwdev, s, &vm);
 321         if (ret < 0)
 322                 return -EINVAL;
 323         return 0;
 324 }
 325
 326 static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
 327                                     struct drm_crtc_state *state)
 328 {
 329         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 330         struct malidp_hw_device *hwdev = malidp->dev;
 331         struct drm_plane *plane;
 332         const struct drm_plane_state *pstate;
 333         u32 rot_mem_free, rot_mem_usable;
 334         int rotated_planes = 0;
 335         int ret;
 336
 337         /*
 338          * check if there is enough rotation memory available for planes
 339          * that need 90° and 270° rotation. Each plane has set its required
 340          * memory size in the ->plane_check() callback, here we only make
 341          * sure that the sums are less that the total usable memory.
 342          *
 343          * The rotation memory allocation algorithm (for each plane):
 344          *  a. If no more rotated planes exist, all remaining rotate
 345          *     memory in the bank is available for use by the plane.
 346          *  b. If other rotated planes exist, and plane's layer ID is
 347          *     DE_VIDEO1, it can use all the memory from first bank if
 348          *     secondary rotation memory bank is available, otherwise it can
 349          *     use up to half the bank's memory.
 350          *  c. If other rotated planes exist, and plane's layer ID is not
 351          *     DE_VIDEO1, it can use half of the available memory
 352          *
 353          * Note: this algorithm assumes that the order in which the planes are
 354          * checked always has DE_VIDEO1 plane first in the list if it is
 355          * rotated. Because that is how we create the planes in the first
 356          * place, under current DRM version things work, but if ever the order
 357          * in which drm_atomic_crtc_state_for_each_plane() iterates over planes
 358          * changes, we need to pre-sort the planes before validation.
 359          */
 360
 361         /* first count the number of rotated planes */
 362         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 363                 if (pstate->rotation & MALIDP_ROTATED_MASK)
 364                         rotated_planes++;
 365         }
 366
 367         rot_mem_free = hwdev->rotation_memory[0];
 368         /*
 369          * if we have more than 1 plane using rotation memory, use the second
 370          * block of rotation memory as well
 371          */
 372         if (rotated_planes > 1)
 373                 rot_mem_free += hwdev->rotation_memory[1];
 374
 375         /* now validate the rotation memory requirements */
 376         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 377                 struct malidp_plane *mp = to_malidp_plane(plane);
 378                 struct malidp_plane_state *ms = to_malidp_plane_state(pstate);
 379
 380                 if (pstate->rotation & MALIDP_ROTATED_MASK) {
 381                         /* process current plane */
 382                         rotated_planes--;
 383
 384                         if (!rotated_planes) {
 385                                 /* no more rotated planes, we can use what's left */
 386                                 rot_mem_usable = rot_mem_free;
 387                         } else {
 388                                 if ((mp->layer->id != DE_VIDEO1) ||
 389                                     (hwdev->rotation_memory[1] == 0))
 390                                         rot_mem_usable = rot_mem_free / 2;
 391                                 else
 392                                         rot_mem_usable = hwdev->rotation_memory[0];
 393                         }
 394
 395                         rot_mem_free -= rot_mem_usable;
 396
 397                         if (ms->rotmem_size > rot_mem_usable)
 398                                 return -EINVAL;
 399                 }
 400         }
 401
 402         ret = malidp_crtc_atomic_check_gamma(crtc, state);
 403         ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state);
 404         ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state);
 405
 406         return ret;
 407 }
 408
 409 static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
 410         .mode_valid = malidp_crtc_mode_valid,
 411         .enable = malidp_crtc_enable,
 412         .disable = malidp_crtc_disable,
 413         .atomic_check = malidp_crtc_atomic_check,
 414 };
 415
 416 static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc *crtc)
 417 {
 418         struct malidp_crtc_state *state, *old_state;
 419
 420         if (WARN_ON(!crtc->state))
 421                 return NULL;
 422
 423         old_state = to_malidp_crtc_state(crtc->state);
 424         state = kmalloc(sizeof(*state), GFP_KERNEL);
 425         if (!state)
 426                 return NULL;
 427
 428         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 429         memcpy(state->gamma_coeffs, old_state->gamma_coeffs,
 430                sizeof(state->gamma_coeffs));
 431         memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs,
 432                sizeof(state->coloradj_coeffs));
 433         memcpy(&state->scaler_config, &old_state->scaler_config,
 434                sizeof(state->scaler_config));
 435         state->scaled_planes_mask = 0;
 436
 437         return &state->base;
 438 }
 439
 440 static void malidp_crtc_reset(struct drm_crtc *crtc)
 441 {
 442         struct malidp_crtc_state *state = NULL;
 443
 444         if (crtc->state) {
 445                 state = to_malidp_crtc_state(crtc->state);
 446                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 447         }
 448
 449         kfree(state);
 450         state = kzalloc(sizeof(*state), GFP_KERNEL);
 451         if (state) {
 452                 crtc->state = &state->base;
 453                 crtc->state->crtc = crtc;
 454         }
 455 }
 456
 457 static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
 458                                       struct drm_crtc_state *state)
 459 {
 460         struct malidp_crtc_state *mali_state = NULL;
 461
 462         if (state) {
 463                 mali_state = to_malidp_crtc_state(state);
 464                 __drm_atomic_helper_crtc_destroy_state(state);
 465         }
 466
 467         kfree(mali_state);
 468 }
 469
 470 static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
 471 {
 472         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 473         struct malidp_hw_device *hwdev = malidp->dev;
 474
 475         malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
 476                              hwdev->map.de_irq_map.vsync_irq);
 477         return 0;
 478 }
 479
 480 static void malidp_crtc_disable_vblank(struct drm_crtc *crtc)
 481 {
 482         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 483         struct malidp_hw_device *hwdev = malidp->dev;
 484
 485         malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
 486                               hwdev->map.de_irq_map.vsync_irq);
 487 }
 488
 489 static const struct drm_crtc_funcs malidp_crtc_funcs = {
 490         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 491         .destroy = drm_crtc_cleanup,
 492         .set_config = drm_atomic_helper_set_config,
 493         .page_flip = drm_atomic_helper_page_flip,
 494         .reset = malidp_crtc_reset,
 495         .atomic_duplicate_state = malidp_crtc_duplicate_state,
 496         .atomic_destroy_state = malidp_crtc_destroy_state,
 497         .enable_vblank = malidp_crtc_enable_vblank,
 498         .disable_vblank = malidp_crtc_disable_vblank,
 499 };
 500
 501 int malidp_crtc_init(struct drm_device *drm)
 502 {
 503         struct malidp_drm *malidp = drm->dev_private;
 504         struct drm_plane *primary = NULL, *plane;
 505         int ret;
 506
 507         ret = malidp_de_planes_init(drm);
 508         if (ret < 0) {
 509                 DRM_ERROR("Failed to initialise planes\n");
 510                 return ret;
 511         }
 512
 513         drm_for_each_plane(plane, drm) {
 514                 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 515                         primary = plane;
 516                         break;
 517                 }
 518         }
 519
 520         if (!primary) {
 521                 DRM_ERROR("no primary plane found\n");
 522                 ret = -EINVAL;
 523                 goto crtc_cleanup_planes;
 524         }
 525
 526         ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
 527                                         &malidp_crtc_funcs, NULL);
 528         if (ret)
 529                 goto crtc_cleanup_planes;
 530
 531         drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
 532         drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
 533         /* No inverse-gamma: it is per-plane. */
 534         drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE);
 535
 536         malidp_se_set_enh_coeffs(malidp->dev);
 537
 538         return 0;
 539
 540 crtc_cleanup_planes:
 541         malidp_de_planes_destroy(drm);
 542
 543         return ret;
 544 }