1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
4 #include <linux/device.h>
5 #include <linux/dma-mapping.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/reset.h>
10 #include <linux/sched/signal.h>
11 #include <linux/uaccess.h>
13 #include <drm/drm_syncobj.h>
14 #include <uapi/drm/v3d_drm.h>
18 #include "v3d_trace.h"
21 v3d_init_core(struct v3d_dev *v3d, int core)
23 /* Set OVRTMUOUT, which means that the texture sampler uniform
24 * configuration's tmu output type field is used, instead of
25 * using the hardware default behavior based on the texture
26 * type. If you want the default behavior, you can still put
27 * "2" in the indirect texture state's output_type field.
30 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
32 /* Whenever we flush the L2T cache, we always want to flush
35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0);
36 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0);
39 /* Sets invariant state for the HW. */
41 v3d_init_hw_state(struct v3d_dev *v3d)
43 v3d_init_core(v3d, 0);
47 v3d_idle_axi(struct v3d_dev *v3d, int core)
49 V3D_CORE_WRITE(core, V3D_GMP_CFG, V3D_GMP_CFG_STOP_REQ);
51 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) &
52 (V3D_GMP_STATUS_RD_COUNT_MASK |
53 V3D_GMP_STATUS_WR_COUNT_MASK |
54 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) {
55 DRM_ERROR("Failed to wait for safe GMP shutdown\n");
60 v3d_idle_gca(struct v3d_dev *v3d)
65 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN);
67 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) &
68 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) ==
69 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) {
70 DRM_ERROR("Failed to wait for safe GCA shutdown\n");
75 v3d_reset_by_bridge(struct v3d_dev *v3d)
77 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION);
79 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) {
80 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0,
81 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT);
82 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0);
84 /* GFXH-1383: The SW_INIT may cause a stray write to address 0
85 * of the unit, so reset it to its power-on value here.
87 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK);
89 WARN_ON_ONCE(V3D_GET_FIELD(version,
90 V3D_TOP_GR_BRIDGE_MAJOR) != 7);
91 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1,
92 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT);
93 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0);
98 v3d_reset_v3d(struct v3d_dev *v3d)
101 reset_control_reset(v3d->reset);
103 v3d_reset_by_bridge(v3d);
105 v3d_init_hw_state(v3d);
109 v3d_reset(struct v3d_dev *v3d)
111 struct drm_device *dev = &v3d->drm;
113 DRM_DEV_ERROR(dev->dev, "Resetting GPU for hang.\n");
114 DRM_DEV_ERROR(dev->dev, "V3D_ERR_STAT: 0x%08x\n",
115 V3D_CORE_READ(0, V3D_ERR_STAT));
116 trace_v3d_reset_begin(dev);
118 /* XXX: only needed for safe powerdown, not reset. */
120 v3d_idle_axi(v3d, 0);
125 v3d_mmu_set_page_table(v3d);
128 v3d_perfmon_stop(v3d, v3d->active_perfmon, false);
130 trace_v3d_reset_end(dev);
134 v3d_flush_l3(struct v3d_dev *v3d)
137 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL);
139 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
140 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH);
143 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
144 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH);
149 /* Invalidates the (read-only) L2C cache. This was the L2 cache for
150 * uniforms and instructions on V3D 3.2.
153 v3d_invalidate_l2c(struct v3d_dev *v3d, int core)
158 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL,
163 /* Invalidates texture L2 cachelines */
165 v3d_flush_l2t(struct v3d_dev *v3d, int core)
167 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't
168 * need to wait for completion before dispatching the job --
169 * L2T accesses will be stalled until the flush has completed.
170 * However, we do need to make sure we don't try to trigger a
171 * new flush while the L2_CLEAN queue is trying to
172 * synchronously clean after a job.
174 mutex_lock(&v3d->cache_clean_lock);
175 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
176 V3D_L2TCACTL_L2TFLS |
177 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM));
178 mutex_unlock(&v3d->cache_clean_lock);
181 /* Cleans texture L1 and L2 cachelines (writing back dirty data).
183 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has
184 * executed, we need to make sure that the clean is done before
185 * signaling job completion. So, we synchronously wait before
186 * returning, and we make sure that L2 invalidates don't happen in the
187 * meantime to confuse our are-we-done checks.
190 v3d_clean_caches(struct v3d_dev *v3d)
192 struct drm_device *dev = &v3d->drm;
195 trace_v3d_cache_clean_begin(dev);
197 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
198 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
199 V3D_L2TCACTL_TMUWCF), 100)) {
200 DRM_ERROR("Timeout waiting for TMU write combiner flush\n");
203 mutex_lock(&v3d->cache_clean_lock);
204 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
205 V3D_L2TCACTL_L2TFLS |
206 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM));
208 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
209 V3D_L2TCACTL_L2TFLS), 100)) {
210 DRM_ERROR("Timeout waiting for L2T clean\n");
213 mutex_unlock(&v3d->cache_clean_lock);
215 trace_v3d_cache_clean_end(dev);
218 /* Invalidates the slice caches. These are read-only caches. */
220 v3d_invalidate_slices(struct v3d_dev *v3d, int core)
222 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL,
223 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) |
224 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) |
225 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
226 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC));
230 v3d_invalidate_caches(struct v3d_dev *v3d)
232 /* Invalidate the caches from the outside in. That way if
233 * another CL's concurrent use of nearby memory were to pull
234 * an invalidated cacheline back in, we wouldn't leave stale
235 * data in the inner cache.
238 v3d_invalidate_l2c(v3d, 0);
239 v3d_flush_l2t(v3d, 0);
240 v3d_invalidate_slices(v3d, 0);
243 /* Takes the reservation lock on all the BOs being referenced, so that
244 * at queue submit time we can update the reservations.
246 * We don't lock the RCL the tile alloc/state BOs, or overflow memory
247 * (all of which are on exec->unref_list). They're entirely private
248 * to v3d, so we don't attach dma-buf fences to them.
251 v3d_lock_bo_reservations(struct v3d_job *job,
252 struct ww_acquire_ctx *acquire_ctx)
256 ret = drm_gem_lock_reservations(job->bo, job->bo_count, acquire_ctx);
260 for (i = 0; i < job->bo_count; i++) {
261 ret = dma_resv_reserve_fences(job->bo[i]->resv, 1);
265 ret = drm_sched_job_add_implicit_dependencies(&job->base,
274 drm_gem_unlock_reservations(job->bo, job->bo_count, acquire_ctx);
279 * v3d_lookup_bos() - Sets up job->bo[] with the GEM objects
280 * referenced by the job.
282 * @file_priv: DRM file for this fd
283 * @job: V3D job being set up
284 * @bo_handles: GEM handles
285 * @bo_count: Number of GEM handles passed in
287 * The command validator needs to reference BOs by their index within
288 * the submitted job's BO list. This does the validation of the job's
289 * BO list and reference counting for the lifetime of the job.
291 * Note that this function doesn't need to unreference the BOs on
292 * failure, because that will happen at v3d_exec_cleanup() time.
295 v3d_lookup_bos(struct drm_device *dev,
296 struct drm_file *file_priv,
305 job->bo_count = bo_count;
307 if (!job->bo_count) {
308 /* See comment on bo_index for why we have to check
311 DRM_DEBUG("Rendering requires BOs\n");
315 job->bo = kvmalloc_array(job->bo_count,
316 sizeof(struct drm_gem_cma_object *),
317 GFP_KERNEL | __GFP_ZERO);
319 DRM_DEBUG("Failed to allocate validated BO pointers\n");
323 handles = kvmalloc_array(job->bo_count, sizeof(u32), GFP_KERNEL);
326 DRM_DEBUG("Failed to allocate incoming GEM handles\n");
330 if (copy_from_user(handles,
331 (void __user *)(uintptr_t)bo_handles,
332 job->bo_count * sizeof(u32))) {
334 DRM_DEBUG("Failed to copy in GEM handles\n");
338 spin_lock(&file_priv->table_lock);
339 for (i = 0; i < job->bo_count; i++) {
340 struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
343 DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
346 spin_unlock(&file_priv->table_lock);
349 drm_gem_object_get(bo);
352 spin_unlock(&file_priv->table_lock);
360 v3d_job_free(struct kref *ref)
362 struct v3d_job *job = container_of(ref, struct v3d_job, refcount);
365 for (i = 0; i < job->bo_count; i++) {
367 drm_gem_object_put(job->bo[i]);
371 dma_fence_put(job->irq_fence);
372 dma_fence_put(job->done_fence);
375 v3d_perfmon_put(job->perfmon);
381 v3d_render_job_free(struct kref *ref)
383 struct v3d_render_job *job = container_of(ref, struct v3d_render_job,
385 struct v3d_bo *bo, *save;
387 list_for_each_entry_safe(bo, save, &job->unref_list, unref_head) {
388 drm_gem_object_put(&bo->base.base);
394 void v3d_job_cleanup(struct v3d_job *job)
399 drm_sched_job_cleanup(&job->base);
403 void v3d_job_put(struct v3d_job *job)
405 kref_put(&job->refcount, job->free);
409 v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
410 struct drm_file *file_priv)
413 struct drm_v3d_wait_bo *args = data;
414 ktime_t start = ktime_get();
416 unsigned long timeout_jiffies =
417 nsecs_to_jiffies_timeout(args->timeout_ns);
422 ret = drm_gem_dma_resv_wait(file_priv, args->handle,
423 true, timeout_jiffies);
425 /* Decrement the user's timeout, in case we got interrupted
426 * such that the ioctl will be restarted.
428 delta_ns = ktime_to_ns(ktime_sub(ktime_get(), start));
429 if (delta_ns < args->timeout_ns)
430 args->timeout_ns -= delta_ns;
432 args->timeout_ns = 0;
434 /* Asked to wait beyond the jiffie/scheduler precision? */
435 if (ret == -ETIME && args->timeout_ns)
442 v3d_job_add_deps(struct drm_file *file_priv, struct v3d_job *job,
443 u32 in_sync, u32 point)
445 struct dma_fence *in_fence = NULL;
448 ret = drm_syncobj_find_fence(file_priv, in_sync, point, 0, &in_fence);
452 return drm_sched_job_add_dependency(&job->base, in_fence);
456 v3d_job_init(struct v3d_dev *v3d, struct drm_file *file_priv,
457 void **container, size_t size, void (*free)(struct kref *ref),
458 u32 in_sync, struct v3d_submit_ext *se, enum v3d_queue queue)
460 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
462 bool has_multisync = se && (se->flags & DRM_V3D_EXT_ID_MULTI_SYNC);
465 *container = kcalloc(1, size, GFP_KERNEL);
467 DRM_ERROR("Cannot allocate memory for v3d job.");
475 ret = drm_sched_job_init(&job->base, &v3d_priv->sched_entity[queue],
481 if (se->in_sync_count && se->wait_stage == queue) {
482 struct drm_v3d_sem __user *handle = u64_to_user_ptr(se->in_syncs);
484 for (i = 0; i < se->in_sync_count; i++) {
485 struct drm_v3d_sem in;
487 if (copy_from_user(&in, handle++, sizeof(in))) {
489 DRM_DEBUG("Failed to copy wait dep handle.\n");
492 ret = v3d_job_add_deps(file_priv, job, in.handle, 0);
498 ret = v3d_job_add_deps(file_priv, job, in_sync, 0);
503 kref_init(&job->refcount);
508 drm_sched_job_cleanup(&job->base);
517 v3d_push_job(struct v3d_job *job)
519 drm_sched_job_arm(&job->base);
521 job->done_fence = dma_fence_get(&job->base.s_fence->finished);
523 /* put by scheduler job completion */
524 kref_get(&job->refcount);
526 drm_sched_entity_push_job(&job->base);
530 v3d_attach_fences_and_unlock_reservation(struct drm_file *file_priv,
532 struct ww_acquire_ctx *acquire_ctx,
534 struct v3d_submit_ext *se,
535 struct dma_fence *done_fence)
537 struct drm_syncobj *sync_out;
538 bool has_multisync = se && (se->flags & DRM_V3D_EXT_ID_MULTI_SYNC);
541 for (i = 0; i < job->bo_count; i++) {
542 /* XXX: Use shared fences for read-only objects. */
543 dma_resv_add_fence(job->bo[i]->resv, job->done_fence,
544 DMA_RESV_USAGE_WRITE);
547 drm_gem_unlock_reservations(job->bo, job->bo_count, acquire_ctx);
549 /* Update the return sync object for the job */
550 /* If it only supports a single signal semaphore*/
551 if (!has_multisync) {
552 sync_out = drm_syncobj_find(file_priv, out_sync);
554 drm_syncobj_replace_fence(sync_out, done_fence);
555 drm_syncobj_put(sync_out);
560 /* If multiple semaphores extension is supported */
561 if (se->out_sync_count) {
562 for (i = 0; i < se->out_sync_count; i++) {
563 drm_syncobj_replace_fence(se->out_syncs[i].syncobj,
565 drm_syncobj_put(se->out_syncs[i].syncobj);
567 kvfree(se->out_syncs);
572 v3d_put_multisync_post_deps(struct v3d_submit_ext *se)
576 if (!(se && se->out_sync_count))
579 for (i = 0; i < se->out_sync_count; i++)
580 drm_syncobj_put(se->out_syncs[i].syncobj);
581 kvfree(se->out_syncs);
585 v3d_get_multisync_post_deps(struct drm_file *file_priv,
586 struct v3d_submit_ext *se,
587 u32 count, u64 handles)
589 struct drm_v3d_sem __user *post_deps;
595 se->out_syncs = (struct v3d_submit_outsync *)
596 kvmalloc_array(count,
597 sizeof(struct v3d_submit_outsync),
602 post_deps = u64_to_user_ptr(handles);
604 for (i = 0; i < count; i++) {
605 struct drm_v3d_sem out;
607 if (copy_from_user(&out, post_deps++, sizeof(out))) {
609 DRM_DEBUG("Failed to copy post dep handles\n");
613 se->out_syncs[i].syncobj = drm_syncobj_find(file_priv,
615 if (!se->out_syncs[i].syncobj) {
620 se->out_sync_count = count;
625 for (i--; i >= 0; i--)
626 drm_syncobj_put(se->out_syncs[i].syncobj);
627 kvfree(se->out_syncs);
632 /* Get data for multiple binary semaphores synchronization. Parse syncobj
633 * to be signaled when job completes (out_sync).
636 v3d_get_multisync_submit_deps(struct drm_file *file_priv,
637 struct drm_v3d_extension __user *ext,
640 struct drm_v3d_multi_sync multisync;
641 struct v3d_submit_ext *se = data;
644 if (copy_from_user(&multisync, ext, sizeof(multisync)))
650 ret = v3d_get_multisync_post_deps(file_priv, data, multisync.out_sync_count,
651 multisync.out_syncs);
655 se->in_sync_count = multisync.in_sync_count;
656 se->in_syncs = multisync.in_syncs;
657 se->flags |= DRM_V3D_EXT_ID_MULTI_SYNC;
658 se->wait_stage = multisync.wait_stage;
663 /* Whenever userspace sets ioctl extensions, v3d_get_extensions parses data
664 * according to the extension id (name).
667 v3d_get_extensions(struct drm_file *file_priv,
671 struct drm_v3d_extension __user *user_ext;
674 user_ext = u64_to_user_ptr(ext_handles);
676 struct drm_v3d_extension ext;
678 if (copy_from_user(&ext, user_ext, sizeof(ext))) {
679 DRM_DEBUG("Failed to copy submit extension\n");
684 case DRM_V3D_EXT_ID_MULTI_SYNC:
685 ret = v3d_get_multisync_submit_deps(file_priv, user_ext, data);
690 DRM_DEBUG_DRIVER("Unknown extension id: %d\n", ext.id);
694 user_ext = u64_to_user_ptr(ext.next);
701 * v3d_submit_cl_ioctl() - Submits a job (frame) to the V3D.
703 * @data: ioctl argument
704 * @file_priv: DRM file for this fd
706 * This is the main entrypoint for userspace to submit a 3D frame to
707 * the GPU. Userspace provides the binner command list (if
708 * applicable), and the kernel sets up the render command list to draw
709 * to the framebuffer described in the ioctl, using the command lists
710 * that the 3D engine's binner will produce.
713 v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
714 struct drm_file *file_priv)
716 struct v3d_dev *v3d = to_v3d_dev(dev);
717 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
718 struct drm_v3d_submit_cl *args = data;
719 struct v3d_submit_ext se = {0};
720 struct v3d_bin_job *bin = NULL;
721 struct v3d_render_job *render = NULL;
722 struct v3d_job *clean_job = NULL;
723 struct v3d_job *last_job;
724 struct ww_acquire_ctx acquire_ctx;
727 trace_v3d_submit_cl_ioctl(&v3d->drm, args->rcl_start, args->rcl_end);
733 args->flags & ~(DRM_V3D_SUBMIT_CL_FLUSH_CACHE |
734 DRM_V3D_SUBMIT_EXTENSION)) {
735 DRM_INFO("invalid flags: %d\n", args->flags);
739 if (args->flags & DRM_V3D_SUBMIT_EXTENSION) {
740 ret = v3d_get_extensions(file_priv, args->extensions, &se);
742 DRM_DEBUG("Failed to get extensions.\n");
747 ret = v3d_job_init(v3d, file_priv, (void *)&render, sizeof(*render),
748 v3d_render_job_free, args->in_sync_rcl, &se, V3D_RENDER);
752 render->start = args->rcl_start;
753 render->end = args->rcl_end;
754 INIT_LIST_HEAD(&render->unref_list);
756 if (args->bcl_start != args->bcl_end) {
757 ret = v3d_job_init(v3d, file_priv, (void *)&bin, sizeof(*bin),
758 v3d_job_free, args->in_sync_bcl, &se, V3D_BIN);
762 bin->start = args->bcl_start;
763 bin->end = args->bcl_end;
764 bin->qma = args->qma;
765 bin->qms = args->qms;
766 bin->qts = args->qts;
767 bin->render = render;
770 if (args->flags & DRM_V3D_SUBMIT_CL_FLUSH_CACHE) {
771 ret = v3d_job_init(v3d, file_priv, (void *)&clean_job, sizeof(*clean_job),
772 v3d_job_free, 0, NULL, V3D_CACHE_CLEAN);
776 last_job = clean_job;
778 last_job = &render->base;
781 ret = v3d_lookup_bos(dev, file_priv, last_job,
782 args->bo_handles, args->bo_handle_count);
786 ret = v3d_lock_bo_reservations(last_job, &acquire_ctx);
790 if (args->perfmon_id) {
791 render->base.perfmon = v3d_perfmon_find(v3d_priv,
794 if (!render->base.perfmon) {
800 mutex_lock(&v3d->sched_lock);
802 bin->base.perfmon = render->base.perfmon;
803 v3d_perfmon_get(bin->base.perfmon);
804 v3d_push_job(&bin->base);
806 ret = drm_sched_job_add_dependency(&render->base.base,
807 dma_fence_get(bin->base.done_fence));
812 v3d_push_job(&render->base);
815 struct dma_fence *render_fence =
816 dma_fence_get(render->base.done_fence);
817 ret = drm_sched_job_add_dependency(&clean_job->base,
821 clean_job->perfmon = render->base.perfmon;
822 v3d_perfmon_get(clean_job->perfmon);
823 v3d_push_job(clean_job);
826 mutex_unlock(&v3d->sched_lock);
828 v3d_attach_fences_and_unlock_reservation(file_priv,
833 last_job->done_fence);
836 v3d_job_put(&bin->base);
837 v3d_job_put(&render->base);
839 v3d_job_put(clean_job);
844 mutex_unlock(&v3d->sched_lock);
846 drm_gem_unlock_reservations(last_job->bo,
847 last_job->bo_count, &acquire_ctx);
849 v3d_job_cleanup((void *)bin);
850 v3d_job_cleanup((void *)render);
851 v3d_job_cleanup(clean_job);
852 v3d_put_multisync_post_deps(&se);
858 * v3d_submit_tfu_ioctl() - Submits a TFU (texture formatting) job to the V3D.
860 * @data: ioctl argument
861 * @file_priv: DRM file for this fd
863 * Userspace provides the register setup for the TFU, which we don't
864 * need to validate since the TFU is behind the MMU.
867 v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
868 struct drm_file *file_priv)
870 struct v3d_dev *v3d = to_v3d_dev(dev);
871 struct drm_v3d_submit_tfu *args = data;
872 struct v3d_submit_ext se = {0};
873 struct v3d_tfu_job *job = NULL;
874 struct ww_acquire_ctx acquire_ctx;
877 trace_v3d_submit_tfu_ioctl(&v3d->drm, args->iia);
879 if (args->flags && !(args->flags & DRM_V3D_SUBMIT_EXTENSION)) {
880 DRM_DEBUG("invalid flags: %d\n", args->flags);
884 if (args->flags & DRM_V3D_SUBMIT_EXTENSION) {
885 ret = v3d_get_extensions(file_priv, args->extensions, &se);
887 DRM_DEBUG("Failed to get extensions.\n");
892 ret = v3d_job_init(v3d, file_priv, (void *)&job, sizeof(*job),
893 v3d_job_free, args->in_sync, &se, V3D_TFU);
897 job->base.bo = kcalloc(ARRAY_SIZE(args->bo_handles),
898 sizeof(*job->base.bo), GFP_KERNEL);
906 spin_lock(&file_priv->table_lock);
907 for (job->base.bo_count = 0;
908 job->base.bo_count < ARRAY_SIZE(args->bo_handles);
909 job->base.bo_count++) {
910 struct drm_gem_object *bo;
912 if (!args->bo_handles[job->base.bo_count])
915 bo = idr_find(&file_priv->object_idr,
916 args->bo_handles[job->base.bo_count]);
918 DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
920 args->bo_handles[job->base.bo_count]);
922 spin_unlock(&file_priv->table_lock);
925 drm_gem_object_get(bo);
926 job->base.bo[job->base.bo_count] = bo;
928 spin_unlock(&file_priv->table_lock);
930 ret = v3d_lock_bo_reservations(&job->base, &acquire_ctx);
934 mutex_lock(&v3d->sched_lock);
935 v3d_push_job(&job->base);
936 mutex_unlock(&v3d->sched_lock);
938 v3d_attach_fences_and_unlock_reservation(file_priv,
939 &job->base, &acquire_ctx,
942 job->base.done_fence);
944 v3d_job_put(&job->base);
949 v3d_job_cleanup((void *)job);
950 v3d_put_multisync_post_deps(&se);
956 * v3d_submit_csd_ioctl() - Submits a CSD (texture formatting) job to the V3D.
958 * @data: ioctl argument
959 * @file_priv: DRM file for this fd
961 * Userspace provides the register setup for the CSD, which we don't
962 * need to validate since the CSD is behind the MMU.
965 v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
966 struct drm_file *file_priv)
968 struct v3d_dev *v3d = to_v3d_dev(dev);
969 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
970 struct drm_v3d_submit_csd *args = data;
971 struct v3d_submit_ext se = {0};
972 struct v3d_csd_job *job = NULL;
973 struct v3d_job *clean_job = NULL;
974 struct ww_acquire_ctx acquire_ctx;
977 trace_v3d_submit_csd_ioctl(&v3d->drm, args->cfg[5], args->cfg[6]);
982 if (!v3d_has_csd(v3d)) {
983 DRM_DEBUG("Attempting CSD submit on non-CSD hardware\n");
987 if (args->flags && !(args->flags & DRM_V3D_SUBMIT_EXTENSION)) {
988 DRM_INFO("invalid flags: %d\n", args->flags);
992 if (args->flags & DRM_V3D_SUBMIT_EXTENSION) {
993 ret = v3d_get_extensions(file_priv, args->extensions, &se);
995 DRM_DEBUG("Failed to get extensions.\n");
1000 ret = v3d_job_init(v3d, file_priv, (void *)&job, sizeof(*job),
1001 v3d_job_free, args->in_sync, &se, V3D_CSD);
1005 ret = v3d_job_init(v3d, file_priv, (void *)&clean_job, sizeof(*clean_job),
1006 v3d_job_free, 0, NULL, V3D_CACHE_CLEAN);
1012 ret = v3d_lookup_bos(dev, file_priv, clean_job,
1013 args->bo_handles, args->bo_handle_count);
1017 ret = v3d_lock_bo_reservations(clean_job, &acquire_ctx);
1021 if (args->perfmon_id) {
1022 job->base.perfmon = v3d_perfmon_find(v3d_priv,
1024 if (!job->base.perfmon) {
1030 mutex_lock(&v3d->sched_lock);
1031 v3d_push_job(&job->base);
1033 ret = drm_sched_job_add_dependency(&clean_job->base,
1034 dma_fence_get(job->base.done_fence));
1036 goto fail_unreserve;
1038 v3d_push_job(clean_job);
1039 mutex_unlock(&v3d->sched_lock);
1041 v3d_attach_fences_and_unlock_reservation(file_priv,
1046 clean_job->done_fence);
1048 v3d_job_put(&job->base);
1049 v3d_job_put(clean_job);
1054 mutex_unlock(&v3d->sched_lock);
1056 drm_gem_unlock_reservations(clean_job->bo, clean_job->bo_count,
1059 v3d_job_cleanup((void *)job);
1060 v3d_job_cleanup(clean_job);
1061 v3d_put_multisync_post_deps(&se);
1067 v3d_gem_init(struct drm_device *dev)
1069 struct v3d_dev *v3d = to_v3d_dev(dev);
1070 u32 pt_size = 4096 * 1024;
1073 for (i = 0; i < V3D_MAX_QUEUES; i++)
1074 v3d->queue[i].fence_context = dma_fence_context_alloc(1);
1076 spin_lock_init(&v3d->mm_lock);
1077 spin_lock_init(&v3d->job_lock);
1078 mutex_init(&v3d->bo_lock);
1079 mutex_init(&v3d->reset_lock);
1080 mutex_init(&v3d->sched_lock);
1081 mutex_init(&v3d->cache_clean_lock);
1083 /* Note: We don't allocate address 0. Various bits of HW
1084 * treat 0 as special, such as the occlusion query counters
1085 * where 0 means "disabled".
1087 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1);
1089 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size,
1091 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
1093 drm_mm_takedown(&v3d->mm);
1094 dev_err(v3d->drm.dev,
1095 "Failed to allocate page tables. Please ensure you have CMA enabled.\n");
1099 v3d_init_hw_state(v3d);
1100 v3d_mmu_set_page_table(v3d);
1102 ret = v3d_sched_init(v3d);
1104 drm_mm_takedown(&v3d->mm);
1105 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt,
1113 v3d_gem_destroy(struct drm_device *dev)
1115 struct v3d_dev *v3d = to_v3d_dev(dev);
1117 v3d_sched_fini(v3d);
1119 /* Waiting for jobs to finish would need to be done before
1120 * unregistering V3D.
1122 WARN_ON(v3d->bin_job);
1123 WARN_ON(v3d->render_job);
1125 drm_mm_takedown(&v3d->mm);
1127 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt,