arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <[email protected]>
  12  *   Yaniv Kamay  <[email protected]>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP    128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 130 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 131 module_param(ple_gap, int, S_IRUGO);
 132
 133 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 134 module_param(ple_window, int, S_IRUGO);
 135
 136 extern const ulong vmx_return;
 137
 138 #define NR_AUTOLOAD_MSRS 8
 139 #define VMCS02_POOL_SIZE 1
 140
 141 struct vmcs {
 142         u32 revision_id;
 143         u32 abort;
 144         char data[0];
 145 };
 146
 147 /*
 148  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 149  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 150  * loaded on this CPU (so we can clear them if the CPU goes down).
 151  */
 152 struct loaded_vmcs {
 153         struct vmcs *vmcs;
 154         int cpu;
 155         int launched;
 156         struct list_head loaded_vmcss_on_cpu_link;
 157 };
 158
 159 struct shared_msr_entry {
 160         unsigned index;
 161         u64 data;
 162         u64 mask;
 163 };
 164
 165 /*
 166  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 167  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 168  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 169  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 170  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 171  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 172  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 173  * underlying hardware which will be used to run L2.
 174  * This structure is packed to ensure that its layout is identical across
 175  * machines (necessary for live migration).
 176  * If there are changes in this struct, VMCS12_REVISION must be changed.
 177  */
 178 typedef u64 natural_width;
 179 struct __packed vmcs12 {
 180         /* According to the Intel spec, a VMCS region must start with the
 181          * following two fields. Then follow implementation-specific data.
 182          */
 183         u32 revision_id;
 184         u32 abort;
 185
 186         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 187         u32 padding[7]; /* room for future expansion */
 188
 189         u64 io_bitmap_a;
 190         u64 io_bitmap_b;
 191         u64 msr_bitmap;
 192         u64 vm_exit_msr_store_addr;
 193         u64 vm_exit_msr_load_addr;
 194         u64 vm_entry_msr_load_addr;
 195         u64 tsc_offset;
 196         u64 virtual_apic_page_addr;
 197         u64 apic_access_addr;
 198         u64 ept_pointer;
 199         u64 guest_physical_address;
 200         u64 vmcs_link_pointer;
 201         u64 guest_ia32_debugctl;
 202         u64 guest_ia32_pat;
 203         u64 guest_ia32_efer;
 204         u64 guest_ia32_perf_global_ctrl;
 205         u64 guest_pdptr0;
 206         u64 guest_pdptr1;
 207         u64 guest_pdptr2;
 208         u64 guest_pdptr3;
 209         u64 guest_bndcfgs;
 210         u64 host_ia32_pat;
 211         u64 host_ia32_efer;
 212         u64 host_ia32_perf_global_ctrl;
 213         u64 padding64[8]; /* room for future expansion */
 214         /*
 215          * To allow migration of L1 (complete with its L2 guests) between
 216          * machines of different natural widths (32 or 64 bit), we cannot have
 217          * unsigned long fields with no explict size. We use u64 (aliased
 218          * natural_width) instead. Luckily, x86 is little-endian.
 219          */
 220         natural_width cr0_guest_host_mask;
 221         natural_width cr4_guest_host_mask;
 222         natural_width cr0_read_shadow;
 223         natural_width cr4_read_shadow;
 224         natural_width cr3_target_value0;
 225         natural_width cr3_target_value1;
 226         natural_width cr3_target_value2;
 227         natural_width cr3_target_value3;
 228         natural_width exit_qualification;
 229         natural_width guest_linear_address;
 230         natural_width guest_cr0;
 231         natural_width guest_cr3;
 232         natural_width guest_cr4;
 233         natural_width guest_es_base;
 234         natural_width guest_cs_base;
 235         natural_width guest_ss_base;
 236         natural_width guest_ds_base;
 237         natural_width guest_fs_base;
 238         natural_width guest_gs_base;
 239         natural_width guest_ldtr_base;
 240         natural_width guest_tr_base;
 241         natural_width guest_gdtr_base;
 242         natural_width guest_idtr_base;
 243         natural_width guest_dr7;
 244         natural_width guest_rsp;
 245         natural_width guest_rip;
 246         natural_width guest_rflags;
 247         natural_width guest_pending_dbg_exceptions;
 248         natural_width guest_sysenter_esp;
 249         natural_width guest_sysenter_eip;
 250         natural_width host_cr0;
 251         natural_width host_cr3;
 252         natural_width host_cr4;
 253         natural_width host_fs_base;
 254         natural_width host_gs_base;
 255         natural_width host_tr_base;
 256         natural_width host_gdtr_base;
 257         natural_width host_idtr_base;
 258         natural_width host_ia32_sysenter_esp;
 259         natural_width host_ia32_sysenter_eip;
 260         natural_width host_rsp;
 261         natural_width host_rip;
 262         natural_width paddingl[8]; /* room for future expansion */
 263         u32 pin_based_vm_exec_control;
 264         u32 cpu_based_vm_exec_control;
 265         u32 exception_bitmap;
 266         u32 page_fault_error_code_mask;
 267         u32 page_fault_error_code_match;
 268         u32 cr3_target_count;
 269         u32 vm_exit_controls;
 270         u32 vm_exit_msr_store_count;
 271         u32 vm_exit_msr_load_count;
 272         u32 vm_entry_controls;
 273         u32 vm_entry_msr_load_count;
 274         u32 vm_entry_intr_info_field;
 275         u32 vm_entry_exception_error_code;
 276         u32 vm_entry_instruction_len;
 277         u32 tpr_threshold;
 278         u32 secondary_vm_exec_control;
 279         u32 vm_instruction_error;
 280         u32 vm_exit_reason;
 281         u32 vm_exit_intr_info;
 282         u32 vm_exit_intr_error_code;
 283         u32 idt_vectoring_info_field;
 284         u32 idt_vectoring_error_code;
 285         u32 vm_exit_instruction_len;
 286         u32 vmx_instruction_info;
 287         u32 guest_es_limit;
 288         u32 guest_cs_limit;
 289         u32 guest_ss_limit;
 290         u32 guest_ds_limit;
 291         u32 guest_fs_limit;
 292         u32 guest_gs_limit;
 293         u32 guest_ldtr_limit;
 294         u32 guest_tr_limit;
 295         u32 guest_gdtr_limit;
 296         u32 guest_idtr_limit;
 297         u32 guest_es_ar_bytes;
 298         u32 guest_cs_ar_bytes;
 299         u32 guest_ss_ar_bytes;
 300         u32 guest_ds_ar_bytes;
 301         u32 guest_fs_ar_bytes;
 302         u32 guest_gs_ar_bytes;
 303         u32 guest_ldtr_ar_bytes;
 304         u32 guest_tr_ar_bytes;
 305         u32 guest_interruptibility_info;
 306         u32 guest_activity_state;
 307         u32 guest_sysenter_cs;
 308         u32 host_ia32_sysenter_cs;
 309         u32 vmx_preemption_timer_value;
 310         u32 padding32[7]; /* room for future expansion */
 311         u16 virtual_processor_id;
 312         u16 guest_es_selector;
 313         u16 guest_cs_selector;
 314         u16 guest_ss_selector;
 315         u16 guest_ds_selector;
 316         u16 guest_fs_selector;
 317         u16 guest_gs_selector;
 318         u16 guest_ldtr_selector;
 319         u16 guest_tr_selector;
 320         u16 host_es_selector;
 321         u16 host_cs_selector;
 322         u16 host_ss_selector;
 323         u16 host_ds_selector;
 324         u16 host_fs_selector;
 325         u16 host_gs_selector;
 326         u16 host_tr_selector;
 327 };
 328
 329 /*
 330  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 331  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 332  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 333  */
 334 #define VMCS12_REVISION 0x11e57ed0
 335
 336 /*
 337  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 338  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 339  * current implementation, 4K are reserved to avoid future complications.
 340  */
 341 #define VMCS12_SIZE 0x1000
 342
 343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 344 struct vmcs02_list {
 345         struct list_head list;
 346         gpa_t vmptr;
 347         struct loaded_vmcs vmcs02;
 348 };
 349
 350 /*
 351  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 352  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 353  */
 354 struct nested_vmx {
 355         /* Has the level1 guest done vmxon? */
 356         bool vmxon;
 357         gpa_t vmxon_ptr;
 358
 359         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 360         gpa_t current_vmptr;
 361         /* The host-usable pointer to the above */
 362         struct page *current_vmcs12_page;
 363         struct vmcs12 *current_vmcs12;
 364         struct vmcs *current_shadow_vmcs;
 365         /*
 366          * Indicates if the shadow vmcs must be updated with the
 367          * data hold by vmcs12
 368          */
 369         bool sync_shadow_vmcs;
 370
 371         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 372         struct list_head vmcs02_pool;
 373         int vmcs02_num;
 374         u64 vmcs01_tsc_offset;
 375         /* L2 must run next, and mustn't decide to exit to L1. */
 376         bool nested_run_pending;
 377         /*
 378          * Guest pages referred to in vmcs02 with host-physical pointers, so
 379          * we must keep them pinned while L2 runs.
 380          */
 381         struct page *apic_access_page;
 382         u64 msr_ia32_feature_control;
 383
 384         struct hrtimer preemption_timer;
 385         bool preemption_timer_expired;
 386 };
 387
 388 #define POSTED_INTR_ON  0
 389 /* Posted-Interrupt Descriptor */
 390 struct pi_desc {
 391         u32 pir[8];     /* Posted interrupt requested */
 392         u32 control;    /* bit 0 of control is outstanding notification bit */
 393         u32 rsvd[7];
 394 } __aligned(64);
 395
 396 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 397 {
 398         return test_and_set_bit(POSTED_INTR_ON,
 399                         (unsigned long *)&pi_desc->control);
 400 }
 401
 402 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 403 {
 404         return test_and_clear_bit(POSTED_INTR_ON,
 405                         (unsigned long *)&pi_desc->control);
 406 }
 407
 408 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 409 {
 410         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 411 }
 412
 413 struct vcpu_vmx {
 414         struct kvm_vcpu       vcpu;
 415         unsigned long         host_rsp;
 416         u8                    fail;
 417         bool                  nmi_known_unmasked;
 418         u32                   exit_intr_info;
 419         u32                   idt_vectoring_info;
 420         ulong                 rflags;
 421         struct shared_msr_entry *guest_msrs;
 422         int                   nmsrs;
 423         int                   save_nmsrs;
 424         unsigned long         host_idt_base;
 425 #ifdef CONFIG_X86_64
 426         u64                   msr_host_kernel_gs_base;
 427         u64                   msr_guest_kernel_gs_base;
 428 #endif
 429         u32 vm_entry_controls_shadow;
 430         u32 vm_exit_controls_shadow;
 431         /*
 432          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 433          * non-nested (L1) guest, it always points to vmcs01. For a nested
 434          * guest (L2), it points to a different VMCS.
 435          */
 436         struct loaded_vmcs    vmcs01;
 437         struct loaded_vmcs   *loaded_vmcs;
 438         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 439         struct msr_autoload {
 440                 unsigned nr;
 441                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 442                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 443         } msr_autoload;
 444         struct {
 445                 int           loaded;
 446                 u16           fs_sel, gs_sel, ldt_sel;
 447 #ifdef CONFIG_X86_64
 448                 u16           ds_sel, es_sel;
 449 #endif
 450                 int           gs_ldt_reload_needed;
 451                 int           fs_reload_needed;
 452                 u64           msr_host_bndcfgs;
 453         } host_state;
 454         struct {
 455                 int vm86_active;
 456                 ulong save_rflags;
 457                 struct kvm_segment segs[8];
 458         } rmode;
 459         struct {
 460                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 461                 struct kvm_save_segment {
 462                         u16 selector;
 463                         unsigned long base;
 464                         u32 limit;
 465                         u32 ar;
 466                 } seg[8];
 467         } segment_cache;
 468         int vpid;
 469         bool emulation_required;
 470
 471         /* Support for vnmi-less CPUs */
 472         int soft_vnmi_blocked;
 473         ktime_t entry_time;
 474         s64 vnmi_blocked_time;
 475         u32 exit_reason;
 476
 477         bool rdtscp_enabled;
 478
 479         /* Posted interrupt descriptor */
 480         struct pi_desc pi_desc;
 481
 482         /* Support for a guest hypervisor (nested VMX) */
 483         struct nested_vmx nested;
 484 };
 485
 486 enum segment_cache_field {
 487         SEG_FIELD_SEL = 0,
 488         SEG_FIELD_BASE = 1,
 489         SEG_FIELD_LIMIT = 2,
 490         SEG_FIELD_AR = 3,
 491
 492         SEG_FIELD_NR = 4
 493 };
 494
 495 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 496 {
 497         return container_of(vcpu, struct vcpu_vmx, vcpu);
 498 }
 499
 500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 501 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 502 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 503                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 504
 505
 506 static const unsigned long shadow_read_only_fields[] = {
 507         /*
 508          * We do NOT shadow fields that are modified when L0
 509          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 510          * VMXON...) executed by L1.
 511          * For example, VM_INSTRUCTION_ERROR is read
 512          * by L1 if a vmx instruction fails (part of the error path).
 513          * Note the code assumes this logic. If for some reason
 514          * we start shadowing these fields then we need to
 515          * force a shadow sync when L0 emulates vmx instructions
 516          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 517          * by nested_vmx_failValid)
 518          */
 519         VM_EXIT_REASON,
 520         VM_EXIT_INTR_INFO,
 521         VM_EXIT_INSTRUCTION_LEN,
 522         IDT_VECTORING_INFO_FIELD,
 523         IDT_VECTORING_ERROR_CODE,
 524         VM_EXIT_INTR_ERROR_CODE,
 525         EXIT_QUALIFICATION,
 526         GUEST_LINEAR_ADDRESS,
 527         GUEST_PHYSICAL_ADDRESS
 528 };
 529 static const int max_shadow_read_only_fields =
 530         ARRAY_SIZE(shadow_read_only_fields);
 531
 532 static const unsigned long shadow_read_write_fields[] = {
 533         GUEST_RIP,
 534         GUEST_RSP,
 535         GUEST_CR0,
 536         GUEST_CR3,
 537         GUEST_CR4,
 538         GUEST_INTERRUPTIBILITY_INFO,
 539         GUEST_RFLAGS,
 540         GUEST_CS_SELECTOR,
 541         GUEST_CS_AR_BYTES,
 542         GUEST_CS_LIMIT,
 543         GUEST_CS_BASE,
 544         GUEST_ES_BASE,
 545         GUEST_BNDCFGS,
 546         CR0_GUEST_HOST_MASK,
 547         CR0_READ_SHADOW,
 548         CR4_READ_SHADOW,
 549         TSC_OFFSET,
 550         EXCEPTION_BITMAP,
 551         CPU_BASED_VM_EXEC_CONTROL,
 552         VM_ENTRY_EXCEPTION_ERROR_CODE,
 553         VM_ENTRY_INTR_INFO_FIELD,
 554         VM_ENTRY_INSTRUCTION_LEN,
 555         VM_ENTRY_EXCEPTION_ERROR_CODE,
 556         HOST_FS_BASE,
 557         HOST_GS_BASE,
 558         HOST_FS_SELECTOR,
 559         HOST_GS_SELECTOR
 560 };
 561 static const int max_shadow_read_write_fields =
 562         ARRAY_SIZE(shadow_read_write_fields);
 563
 564 static const unsigned short vmcs_field_to_offset_table[] = {
 565         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 566         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 567         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 568         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 569         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 570         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 571         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 572         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 573         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 574         FIELD(HOST_ES_SELECTOR, host_es_selector),
 575         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 576         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 577         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 578         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 579         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 580         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 581         FIELD64(IO_BITMAP_A, io_bitmap_a),
 582         FIELD64(IO_BITMAP_B, io_bitmap_b),
 583         FIELD64(MSR_BITMAP, msr_bitmap),
 584         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 585         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 586         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 587         FIELD64(TSC_OFFSET, tsc_offset),
 588         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 589         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 590         FIELD64(EPT_POINTER, ept_pointer),
 591         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 592         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 593         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 594         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 595         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 596         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 597         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 598         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 599         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 600         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 601         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 602         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 603         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 604         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 605         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 606         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 607         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 608         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 609         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 610         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 611         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 612         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 613         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 614         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 615         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 616         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 617         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 618         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 619         FIELD(TPR_THRESHOLD, tpr_threshold),
 620         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 621         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 622         FIELD(VM_EXIT_REASON, vm_exit_reason),
 623         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 624         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 625         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 626         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 627         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 628         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 629         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 630         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 631         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 632         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 633         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 634         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 635         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 636         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 637         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 638         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 639         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 640         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 641         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 642         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 643         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 644         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 645         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 646         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 647         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 648         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 649         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 650         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 651         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 652         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 653         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 654         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 655         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 656         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 657         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 658         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 659         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 660         FIELD(EXIT_QUALIFICATION, exit_qualification),
 661         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 662         FIELD(GUEST_CR0, guest_cr0),
 663         FIELD(GUEST_CR3, guest_cr3),
 664         FIELD(GUEST_CR4, guest_cr4),
 665         FIELD(GUEST_ES_BASE, guest_es_base),
 666         FIELD(GUEST_CS_BASE, guest_cs_base),
 667         FIELD(GUEST_SS_BASE, guest_ss_base),
 668         FIELD(GUEST_DS_BASE, guest_ds_base),
 669         FIELD(GUEST_FS_BASE, guest_fs_base),
 670         FIELD(GUEST_GS_BASE, guest_gs_base),
 671         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 672         FIELD(GUEST_TR_BASE, guest_tr_base),
 673         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 674         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 675         FIELD(GUEST_DR7, guest_dr7),
 676         FIELD(GUEST_RSP, guest_rsp),
 677         FIELD(GUEST_RIP, guest_rip),
 678         FIELD(GUEST_RFLAGS, guest_rflags),
 679         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 680         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 681         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 682         FIELD(HOST_CR0, host_cr0),
 683         FIELD(HOST_CR3, host_cr3),
 684         FIELD(HOST_CR4, host_cr4),
 685         FIELD(HOST_FS_BASE, host_fs_base),
 686         FIELD(HOST_GS_BASE, host_gs_base),
 687         FIELD(HOST_TR_BASE, host_tr_base),
 688         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 689         FIELD(HOST_IDTR_BASE, host_idtr_base),
 690         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 691         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 692         FIELD(HOST_RSP, host_rsp),
 693         FIELD(HOST_RIP, host_rip),
 694 };
 695 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 696
 697 static inline short vmcs_field_to_offset(unsigned long field)
 698 {
 699         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 700                 return -1;
 701         return vmcs_field_to_offset_table[field];
 702 }
 703
 704 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 705 {
 706         return to_vmx(vcpu)->nested.current_vmcs12;
 707 }
 708
 709 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 710 {
 711         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 712         if (is_error_page(page))
 713                 return NULL;
 714
 715         return page;
 716 }
 717
 718 static void nested_release_page(struct page *page)
 719 {
 720         kvm_release_page_dirty(page);
 721 }
 722
 723 static void nested_release_page_clean(struct page *page)
 724 {
 725         kvm_release_page_clean(page);
 726 }
 727
 728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 729 static u64 construct_eptp(unsigned long root_hpa);
 730 static void kvm_cpu_vmxon(u64 addr);
 731 static void kvm_cpu_vmxoff(void);
 732 static bool vmx_mpx_supported(void);
 733 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 734 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 735                             struct kvm_segment *var, int seg);
 736 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 737                             struct kvm_segment *var, int seg);
 738 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 739 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 740 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 741 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 742 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 743 static bool vmx_mpx_supported(void);
 744
 745 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 746 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 747 /*
 748  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 749  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 750  */
 751 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 752 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 753
 754 static unsigned long *vmx_io_bitmap_a;
 755 static unsigned long *vmx_io_bitmap_b;
 756 static unsigned long *vmx_msr_bitmap_legacy;
 757 static unsigned long *vmx_msr_bitmap_longmode;
 758 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 759 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 760 static unsigned long *vmx_vmread_bitmap;
 761 static unsigned long *vmx_vmwrite_bitmap;
 762
 763 static bool cpu_has_load_ia32_efer;
 764 static bool cpu_has_load_perf_global_ctrl;
 765
 766 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 767 static DEFINE_SPINLOCK(vmx_vpid_lock);
 768
 769 static struct vmcs_config {
 770         int size;
 771         int order;
 772         u32 revision_id;
 773         u32 pin_based_exec_ctrl;
 774         u32 cpu_based_exec_ctrl;
 775         u32 cpu_based_2nd_exec_ctrl;
 776         u32 vmexit_ctrl;
 777         u32 vmentry_ctrl;
 778 } vmcs_config;
 779
 780 static struct vmx_capability {
 781         u32 ept;
 782         u32 vpid;
 783 } vmx_capability;
 784
 785 #define VMX_SEGMENT_FIELD(seg)                                  \
 786         [VCPU_SREG_##seg] = {                                   \
 787                 .selector = GUEST_##seg##_SELECTOR,             \
 788                 .base = GUEST_##seg##_BASE,                     \
 789                 .limit = GUEST_##seg##_LIMIT,                   \
 790                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 791         }
 792
 793 static const struct kvm_vmx_segment_field {
 794         unsigned selector;
 795         unsigned base;
 796         unsigned limit;
 797         unsigned ar_bytes;
 798 } kvm_vmx_segment_fields[] = {
 799         VMX_SEGMENT_FIELD(CS),
 800         VMX_SEGMENT_FIELD(DS),
 801         VMX_SEGMENT_FIELD(ES),
 802         VMX_SEGMENT_FIELD(FS),
 803         VMX_SEGMENT_FIELD(GS),
 804         VMX_SEGMENT_FIELD(SS),
 805         VMX_SEGMENT_FIELD(TR),
 806         VMX_SEGMENT_FIELD(LDTR),
 807 };
 808
 809 static u64 host_efer;
 810
 811 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 812
 813 /*
 814  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 815  * away by decrementing the array size.
 816  */
 817 static const u32 vmx_msr_index[] = {
 818 #ifdef CONFIG_X86_64
 819         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 820 #endif
 821         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 822 };
 823 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 824
 825 static inline bool is_page_fault(u32 intr_info)
 826 {
 827         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 828                              INTR_INFO_VALID_MASK)) ==
 829                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 830 }
 831
 832 static inline bool is_no_device(u32 intr_info)
 833 {
 834         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 835                              INTR_INFO_VALID_MASK)) ==
 836                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 837 }
 838
 839 static inline bool is_invalid_opcode(u32 intr_info)
 840 {
 841         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 842                              INTR_INFO_VALID_MASK)) ==
 843                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 844 }
 845
 846 static inline bool is_external_interrupt(u32 intr_info)
 847 {
 848         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 849                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 850 }
 851
 852 static inline bool is_machine_check(u32 intr_info)
 853 {
 854         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 855                              INTR_INFO_VALID_MASK)) ==
 856                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 857 }
 858
 859 static inline bool cpu_has_vmx_msr_bitmap(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 862 }
 863
 864 static inline bool cpu_has_vmx_tpr_shadow(void)
 865 {
 866         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 867 }
 868
 869 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 870 {
 871         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 872 }
 873
 874 static inline bool cpu_has_secondary_exec_ctrls(void)
 875 {
 876         return vmcs_config.cpu_based_exec_ctrl &
 877                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 878 }
 879
 880 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 881 {
 882         return vmcs_config.cpu_based_2nd_exec_ctrl &
 883                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 884 }
 885
 886 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 887 {
 888         return vmcs_config.cpu_based_2nd_exec_ctrl &
 889                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 890 }
 891
 892 static inline bool cpu_has_vmx_apic_register_virt(void)
 893 {
 894         return vmcs_config.cpu_based_2nd_exec_ctrl &
 895                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 896 }
 897
 898 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 899 {
 900         return vmcs_config.cpu_based_2nd_exec_ctrl &
 901                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 902 }
 903
 904 static inline bool cpu_has_vmx_posted_intr(void)
 905 {
 906         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 907 }
 908
 909 static inline bool cpu_has_vmx_apicv(void)
 910 {
 911         return cpu_has_vmx_apic_register_virt() &&
 912                 cpu_has_vmx_virtual_intr_delivery() &&
 913                 cpu_has_vmx_posted_intr();
 914 }
 915
 916 static inline bool cpu_has_vmx_flexpriority(void)
 917 {
 918         return cpu_has_vmx_tpr_shadow() &&
 919                 cpu_has_vmx_virtualize_apic_accesses();
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_execute_only(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 928 {
 929         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_eptp_writeback(void)
 933 {
 934         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_2m_page(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_ept_1g_page(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_ept_4levels(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_ept_ad_bits(void)
 953 {
 954         return vmx_capability.ept & VMX_EPT_AD_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invept_context(void)
 958 {
 959         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_invept_global(void)
 963 {
 964         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 965 }
 966
 967 static inline bool cpu_has_vmx_invvpid_single(void)
 968 {
 969         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 970 }
 971
 972 static inline bool cpu_has_vmx_invvpid_global(void)
 973 {
 974         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 975 }
 976
 977 static inline bool cpu_has_vmx_ept(void)
 978 {
 979         return vmcs_config.cpu_based_2nd_exec_ctrl &
 980                 SECONDARY_EXEC_ENABLE_EPT;
 981 }
 982
 983 static inline bool cpu_has_vmx_unrestricted_guest(void)
 984 {
 985         return vmcs_config.cpu_based_2nd_exec_ctrl &
 986                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 987 }
 988
 989 static inline bool cpu_has_vmx_ple(void)
 990 {
 991         return vmcs_config.cpu_based_2nd_exec_ctrl &
 992                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 993 }
 994
 995 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 996 {
 997         return flexpriority_enabled && irqchip_in_kernel(kvm);
 998 }
 999
1000 static inline bool cpu_has_vmx_vpid(void)
1001 {
1002         return vmcs_config.cpu_based_2nd_exec_ctrl &
1003                 SECONDARY_EXEC_ENABLE_VPID;
1004 }
1005
1006 static inline bool cpu_has_vmx_rdtscp(void)
1007 {
1008         return vmcs_config.cpu_based_2nd_exec_ctrl &
1009                 SECONDARY_EXEC_RDTSCP;
1010 }
1011
1012 static inline bool cpu_has_vmx_invpcid(void)
1013 {
1014         return vmcs_config.cpu_based_2nd_exec_ctrl &
1015                 SECONDARY_EXEC_ENABLE_INVPCID;
1016 }
1017
1018 static inline bool cpu_has_virtual_nmis(void)
1019 {
1020         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021 }
1022
1023 static inline bool cpu_has_vmx_wbinvd_exit(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_WBINVD_EXITING;
1027 }
1028
1029 static inline bool cpu_has_vmx_shadow_vmcs(void)
1030 {
1031         u64 vmx_msr;
1032         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033         /* check if the cpu supports writing r/o exit information fields */
1034         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035                 return false;
1036
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_SHADOW_VMCS;
1039 }
1040
1041 static inline bool report_flexpriority(void)
1042 {
1043         return flexpriority_enabled;
1044 }
1045
1046 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047 {
1048         return vmcs12->cpu_based_vm_exec_control & bit;
1049 }
1050
1051 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052 {
1053         return (vmcs12->cpu_based_vm_exec_control &
1054                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055                 (vmcs12->secondary_vm_exec_control & bit);
1056 }
1057
1058 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1059 {
1060         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061 }
1062
1063 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064 {
1065         return vmcs12->pin_based_vm_exec_control &
1066                 PIN_BASED_VMX_PREEMPTION_TIMER;
1067 }
1068
1069 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070 {
1071         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072 }
1073
1074 static inline bool is_exception(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081                               u32 exit_intr_info,
1082                               unsigned long exit_qualification);
1083 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084                         struct vmcs12 *vmcs12,
1085                         u32 reason, unsigned long qualification);
1086
1087 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1088 {
1089         int i;
1090
1091         for (i = 0; i < vmx->nmsrs; ++i)
1092                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1093                         return i;
1094         return -1;
1095 }
1096
1097 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098 {
1099     struct {
1100         u64 vpid : 16;
1101         u64 rsvd : 48;
1102         u64 gva;
1103     } operand = { vpid, 0, gva };
1104
1105     asm volatile (__ex(ASM_VMX_INVVPID)
1106                   /* CF==1 or ZF==1 --> rc = -1 */
1107                   "; ja 1f ; ud2 ; 1:"
1108                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1109 }
1110
1111 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112 {
1113         struct {
1114                 u64 eptp, gpa;
1115         } operand = {eptp, gpa};
1116
1117         asm volatile (__ex(ASM_VMX_INVEPT)
1118                         /* CF==1 or ZF==1 --> rc = -1 */
1119                         "; ja 1f ; ud2 ; 1:\n"
1120                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1121 }
1122
1123 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1124 {
1125         int i;
1126
1127         i = __find_msr_index(vmx, msr);
1128         if (i >= 0)
1129                 return &vmx->guest_msrs[i];
1130         return NULL;
1131 }
1132
1133 static void vmcs_clear(struct vmcs *vmcs)
1134 {
1135         u64 phys_addr = __pa(vmcs);
1136         u8 error;
1137
1138         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1139                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1140                       : "cc", "memory");
1141         if (error)
1142                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143                        vmcs, phys_addr);
1144 }
1145
1146 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147 {
1148         vmcs_clear(loaded_vmcs->vmcs);
1149         loaded_vmcs->cpu = -1;
1150         loaded_vmcs->launched = 0;
1151 }
1152
1153 static void vmcs_load(struct vmcs *vmcs)
1154 {
1155         u64 phys_addr = __pa(vmcs);
1156         u8 error;
1157
1158         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1159                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1160                         : "cc", "memory");
1161         if (error)
1162                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1163                        vmcs, phys_addr);
1164 }
1165
1166 #ifdef CONFIG_KEXEC
1167 /*
1168  * This bitmap is used to indicate whether the vmclear
1169  * operation is enabled on all cpus. All disabled by
1170  * default.
1171  */
1172 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174 static inline void crash_enable_local_vmclear(int cpu)
1175 {
1176         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177 }
1178
1179 static inline void crash_disable_local_vmclear(int cpu)
1180 {
1181         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182 }
1183
1184 static inline int crash_local_vmclear_enabled(int cpu)
1185 {
1186         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187 }
1188
1189 static void crash_vmclear_local_loaded_vmcss(void)
1190 {
1191         int cpu = raw_smp_processor_id();
1192         struct loaded_vmcs *v;
1193
1194         if (!crash_local_vmclear_enabled(cpu))
1195                 return;
1196
1197         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198                             loaded_vmcss_on_cpu_link)
1199                 vmcs_clear(v->vmcs);
1200 }
1201 #else
1202 static inline void crash_enable_local_vmclear(int cpu) { }
1203 static inline void crash_disable_local_vmclear(int cpu) { }
1204 #endif /* CONFIG_KEXEC */
1205
1206 static void __loaded_vmcs_clear(void *arg)
1207 {
1208         struct loaded_vmcs *loaded_vmcs = arg;
1209         int cpu = raw_smp_processor_id();
1210
1211         if (loaded_vmcs->cpu != cpu)
1212                 return; /* vcpu migration can race with cpu offline */
1213         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1214                 per_cpu(current_vmcs, cpu) = NULL;
1215         crash_disable_local_vmclear(cpu);
1216         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1217
1218         /*
1219          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220          * is before setting loaded_vmcs->vcpu to -1 which is done in
1221          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222          * then adds the vmcs into percpu list before it is deleted.
1223          */
1224         smp_wmb();
1225
1226         loaded_vmcs_init(loaded_vmcs);
1227         crash_enable_local_vmclear(cpu);
1228 }
1229
1230 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1231 {
1232         int cpu = loaded_vmcs->cpu;
1233
1234         if (cpu != -1)
1235                 smp_call_function_single(cpu,
1236                          __loaded_vmcs_clear, loaded_vmcs, 1);
1237 }
1238
1239 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1240 {
1241         if (vmx->vpid == 0)
1242                 return;
1243
1244         if (cpu_has_vmx_invvpid_single())
1245                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1246 }
1247
1248 static inline void vpid_sync_vcpu_global(void)
1249 {
1250         if (cpu_has_vmx_invvpid_global())
1251                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252 }
1253
1254 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255 {
1256         if (cpu_has_vmx_invvpid_single())
1257                 vpid_sync_vcpu_single(vmx);
1258         else
1259                 vpid_sync_vcpu_global();
1260 }
1261
1262 static inline void ept_sync_global(void)
1263 {
1264         if (cpu_has_vmx_invept_global())
1265                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266 }
1267
1268 static inline void ept_sync_context(u64 eptp)
1269 {
1270         if (enable_ept) {
1271                 if (cpu_has_vmx_invept_context())
1272                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273                 else
1274                         ept_sync_global();
1275         }
1276 }
1277
1278 static __always_inline unsigned long vmcs_readl(unsigned long field)
1279 {
1280         unsigned long value;
1281
1282         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283                       : "=a"(value) : "d"(field) : "cc");
1284         return value;
1285 }
1286
1287 static __always_inline u16 vmcs_read16(unsigned long field)
1288 {
1289         return vmcs_readl(field);
1290 }
1291
1292 static __always_inline u32 vmcs_read32(unsigned long field)
1293 {
1294         return vmcs_readl(field);
1295 }
1296
1297 static __always_inline u64 vmcs_read64(unsigned long field)
1298 {
1299 #ifdef CONFIG_X86_64
1300         return vmcs_readl(field);
1301 #else
1302         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303 #endif
1304 }
1305
1306 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307 {
1308         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310         dump_stack();
1311 }
1312
1313 static void vmcs_writel(unsigned long field, unsigned long value)
1314 {
1315         u8 error;
1316
1317         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1318                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1319         if (unlikely(error))
1320                 vmwrite_error(field, value);
1321 }
1322
1323 static void vmcs_write16(unsigned long field, u16 value)
1324 {
1325         vmcs_writel(field, value);
1326 }
1327
1328 static void vmcs_write32(unsigned long field, u32 value)
1329 {
1330         vmcs_writel(field, value);
1331 }
1332
1333 static void vmcs_write64(unsigned long field, u64 value)
1334 {
1335         vmcs_writel(field, value);
1336 #ifndef CONFIG_X86_64
1337         asm volatile ("");
1338         vmcs_writel(field+1, value >> 32);
1339 #endif
1340 }
1341
1342 static void vmcs_clear_bits(unsigned long field, u32 mask)
1343 {
1344         vmcs_writel(field, vmcs_readl(field) & ~mask);
1345 }
1346
1347 static void vmcs_set_bits(unsigned long field, u32 mask)
1348 {
1349         vmcs_writel(field, vmcs_readl(field) | mask);
1350 }
1351
1352 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353 {
1354         vmcs_write32(VM_ENTRY_CONTROLS, val);
1355         vmx->vm_entry_controls_shadow = val;
1356 }
1357
1358 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359 {
1360         if (vmx->vm_entry_controls_shadow != val)
1361                 vm_entry_controls_init(vmx, val);
1362 }
1363
1364 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365 {
1366         return vmx->vm_entry_controls_shadow;
1367 }
1368
1369
1370 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371 {
1372         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373 }
1374
1375 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376 {
1377         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378 }
1379
1380 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381 {
1382         vmcs_write32(VM_EXIT_CONTROLS, val);
1383         vmx->vm_exit_controls_shadow = val;
1384 }
1385
1386 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387 {
1388         if (vmx->vm_exit_controls_shadow != val)
1389                 vm_exit_controls_init(vmx, val);
1390 }
1391
1392 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393 {
1394         return vmx->vm_exit_controls_shadow;
1395 }
1396
1397
1398 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399 {
1400         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401 }
1402
1403 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404 {
1405         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406 }
1407
1408 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409 {
1410         vmx->segment_cache.bitmask = 0;
1411 }
1412
1413 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414                                        unsigned field)
1415 {
1416         bool ret;
1417         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421                 vmx->segment_cache.bitmask = 0;
1422         }
1423         ret = vmx->segment_cache.bitmask & mask;
1424         vmx->segment_cache.bitmask |= mask;
1425         return ret;
1426 }
1427
1428 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429 {
1430         u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434         return *p;
1435 }
1436
1437 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438 {
1439         ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443         return *p;
1444 }
1445
1446 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447 {
1448         u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452         return *p;
1453 }
1454
1455 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456 {
1457         u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461         return *p;
1462 }
1463
1464 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465 {
1466         u32 eb;
1467
1468         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470         if ((vcpu->guest_debug &
1471              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473                 eb |= 1u << BP_VECTOR;
1474         if (to_vmx(vcpu)->rmode.vm86_active)
1475                 eb = ~0;
1476         if (enable_ept)
1477                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1478         if (vcpu->fpu_active)
1479                 eb &= ~(1u << NM_VECTOR);
1480
1481         /* When we are running a nested L2 guest and L1 specified for it a
1482          * certain exception bitmap, we must trap the same exceptions and pass
1483          * them to L1. When running L2, we will only handle the exceptions
1484          * specified above if L1 did not want them.
1485          */
1486         if (is_guest_mode(vcpu))
1487                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
1489         vmcs_write32(EXCEPTION_BITMAP, eb);
1490 }
1491
1492 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493                 unsigned long entry, unsigned long exit)
1494 {
1495         vm_entry_controls_clearbit(vmx, entry);
1496         vm_exit_controls_clearbit(vmx, exit);
1497 }
1498
1499 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500 {
1501         unsigned i;
1502         struct msr_autoload *m = &vmx->msr_autoload;
1503
1504         switch (msr) {
1505         case MSR_EFER:
1506                 if (cpu_has_load_ia32_efer) {
1507                         clear_atomic_switch_msr_special(vmx,
1508                                         VM_ENTRY_LOAD_IA32_EFER,
1509                                         VM_EXIT_LOAD_IA32_EFER);
1510                         return;
1511                 }
1512                 break;
1513         case MSR_CORE_PERF_GLOBAL_CTRL:
1514                 if (cpu_has_load_perf_global_ctrl) {
1515                         clear_atomic_switch_msr_special(vmx,
1516                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518                         return;
1519                 }
1520                 break;
1521         }
1522
1523         for (i = 0; i < m->nr; ++i)
1524                 if (m->guest[i].index == msr)
1525                         break;
1526
1527         if (i == m->nr)
1528                 return;
1529         --m->nr;
1530         m->guest[i] = m->guest[m->nr];
1531         m->host[i] = m->host[m->nr];
1532         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534 }
1535
1536 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537                 unsigned long entry, unsigned long exit,
1538                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539                 u64 guest_val, u64 host_val)
1540 {
1541         vmcs_write64(guest_val_vmcs, guest_val);
1542         vmcs_write64(host_val_vmcs, host_val);
1543         vm_entry_controls_setbit(vmx, entry);
1544         vm_exit_controls_setbit(vmx, exit);
1545 }
1546
1547 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548                                   u64 guest_val, u64 host_val)
1549 {
1550         unsigned i;
1551         struct msr_autoload *m = &vmx->msr_autoload;
1552
1553         switch (msr) {
1554         case MSR_EFER:
1555                 if (cpu_has_load_ia32_efer) {
1556                         add_atomic_switch_msr_special(vmx,
1557                                         VM_ENTRY_LOAD_IA32_EFER,
1558                                         VM_EXIT_LOAD_IA32_EFER,
1559                                         GUEST_IA32_EFER,
1560                                         HOST_IA32_EFER,
1561                                         guest_val, host_val);
1562                         return;
1563                 }
1564                 break;
1565         case MSR_CORE_PERF_GLOBAL_CTRL:
1566                 if (cpu_has_load_perf_global_ctrl) {
1567                         add_atomic_switch_msr_special(vmx,
1568                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1571                                         HOST_IA32_PERF_GLOBAL_CTRL,
1572                                         guest_val, host_val);
1573                         return;
1574                 }
1575                 break;
1576         }
1577
1578         for (i = 0; i < m->nr; ++i)
1579                 if (m->guest[i].index == msr)
1580                         break;
1581
1582         if (i == NR_AUTOLOAD_MSRS) {
1583                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1584                                 "Can't add msr %x\n", msr);
1585                 return;
1586         } else if (i == m->nr) {
1587                 ++m->nr;
1588                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590         }
1591
1592         m->guest[i].index = msr;
1593         m->guest[i].value = guest_val;
1594         m->host[i].index = msr;
1595         m->host[i].value = host_val;
1596 }
1597
1598 static void reload_tss(void)
1599 {
1600         /*
1601          * VT restores TR but not its size.  Useless.
1602          */
1603         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1604         struct desc_struct *descs;
1605
1606         descs = (void *)gdt->address;
1607         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608         load_TR_desc();
1609 }
1610
1611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1612 {
1613         u64 guest_efer;
1614         u64 ignore_bits;
1615
1616         guest_efer = vmx->vcpu.arch.efer;
1617
1618         /*
1619          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1620          * outside long mode
1621          */
1622         ignore_bits = EFER_NX | EFER_SCE;
1623 #ifdef CONFIG_X86_64
1624         ignore_bits |= EFER_LMA | EFER_LME;
1625         /* SCE is meaningful only in long mode on Intel */
1626         if (guest_efer & EFER_LMA)
1627                 ignore_bits &= ~(u64)EFER_SCE;
1628 #endif
1629         guest_efer &= ~ignore_bits;
1630         guest_efer |= host_efer & ignore_bits;
1631         vmx->guest_msrs[efer_offset].data = guest_efer;
1632         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1633
1634         clear_atomic_switch_msr(vmx, MSR_EFER);
1635         /* On ept, can't emulate nx, and must switch nx atomically */
1636         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637                 guest_efer = vmx->vcpu.arch.efer;
1638                 if (!(guest_efer & EFER_LMA))
1639                         guest_efer &= ~EFER_LME;
1640                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641                 return false;
1642         }
1643
1644         return true;
1645 }
1646
1647 static unsigned long segment_base(u16 selector)
1648 {
1649         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1650         struct desc_struct *d;
1651         unsigned long table_base;
1652         unsigned long v;
1653
1654         if (!(selector & ~3))
1655                 return 0;
1656
1657         table_base = gdt->address;
1658
1659         if (selector & 4) {           /* from ldt */
1660                 u16 ldt_selector = kvm_read_ldt();
1661
1662                 if (!(ldt_selector & ~3))
1663                         return 0;
1664
1665                 table_base = segment_base(ldt_selector);
1666         }
1667         d = (struct desc_struct *)(table_base + (selector & ~7));
1668         v = get_desc_base(d);
1669 #ifdef CONFIG_X86_64
1670        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672 #endif
1673         return v;
1674 }
1675
1676 static inline unsigned long kvm_read_tr_base(void)
1677 {
1678         u16 tr;
1679         asm("str %0" : "=g"(tr));
1680         return segment_base(tr);
1681 }
1682
1683 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1684 {
1685         struct vcpu_vmx *vmx = to_vmx(vcpu);
1686         int i;
1687
1688         if (vmx->host_state.loaded)
1689                 return;
1690
1691         vmx->host_state.loaded = 1;
1692         /*
1693          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1694          * allow segment selectors with cpl > 0 or ti == 1.
1695          */
1696         vmx->host_state.ldt_sel = kvm_read_ldt();
1697         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1698         savesegment(fs, vmx->host_state.fs_sel);
1699         if (!(vmx->host_state.fs_sel & 7)) {
1700                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1701                 vmx->host_state.fs_reload_needed = 0;
1702         } else {
1703                 vmcs_write16(HOST_FS_SELECTOR, 0);
1704                 vmx->host_state.fs_reload_needed = 1;
1705         }
1706         savesegment(gs, vmx->host_state.gs_sel);
1707         if (!(vmx->host_state.gs_sel & 7))
1708                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1709         else {
1710                 vmcs_write16(HOST_GS_SELECTOR, 0);
1711                 vmx->host_state.gs_ldt_reload_needed = 1;
1712         }
1713
1714 #ifdef CONFIG_X86_64
1715         savesegment(ds, vmx->host_state.ds_sel);
1716         savesegment(es, vmx->host_state.es_sel);
1717 #endif
1718
1719 #ifdef CONFIG_X86_64
1720         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722 #else
1723         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1725 #endif
1726
1727 #ifdef CONFIG_X86_64
1728         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729         if (is_long_mode(&vmx->vcpu))
1730                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1731 #endif
1732         if (boot_cpu_has(X86_FEATURE_MPX))
1733                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1734         for (i = 0; i < vmx->save_nmsrs; ++i)
1735                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1736                                    vmx->guest_msrs[i].data,
1737                                    vmx->guest_msrs[i].mask);
1738 }
1739
1740 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1741 {
1742         if (!vmx->host_state.loaded)
1743                 return;
1744
1745         ++vmx->vcpu.stat.host_state_reload;
1746         vmx->host_state.loaded = 0;
1747 #ifdef CONFIG_X86_64
1748         if (is_long_mode(&vmx->vcpu))
1749                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750 #endif
1751         if (vmx->host_state.gs_ldt_reload_needed) {
1752                 kvm_load_ldt(vmx->host_state.ldt_sel);
1753 #ifdef CONFIG_X86_64
1754                 load_gs_index(vmx->host_state.gs_sel);
1755 #else
1756                 loadsegment(gs, vmx->host_state.gs_sel);
1757 #endif
1758         }
1759         if (vmx->host_state.fs_reload_needed)
1760                 loadsegment(fs, vmx->host_state.fs_sel);
1761 #ifdef CONFIG_X86_64
1762         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763                 loadsegment(ds, vmx->host_state.ds_sel);
1764                 loadsegment(es, vmx->host_state.es_sel);
1765         }
1766 #endif
1767         reload_tss();
1768 #ifdef CONFIG_X86_64
1769         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1770 #endif
1771         if (vmx->host_state.msr_host_bndcfgs)
1772                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1773         /*
1774          * If the FPU is not active (through the host task or
1775          * the guest vcpu), then restore the cr0.TS bit.
1776          */
1777         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778                 stts();
1779         load_gdt(&__get_cpu_var(host_gdt));
1780 }
1781
1782 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783 {
1784         preempt_disable();
1785         __vmx_load_host_state(vmx);
1786         preempt_enable();
1787 }
1788
1789 /*
1790  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791  * vcpu mutex is already taken.
1792  */
1793 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1794 {
1795         struct vcpu_vmx *vmx = to_vmx(vcpu);
1796         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1797
1798         if (!vmm_exclusive)
1799                 kvm_cpu_vmxon(phys_addr);
1800         else if (vmx->loaded_vmcs->cpu != cpu)
1801                 loaded_vmcs_clear(vmx->loaded_vmcs);
1802
1803         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805                 vmcs_load(vmx->loaded_vmcs->vmcs);
1806         }
1807
1808         if (vmx->loaded_vmcs->cpu != cpu) {
1809                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1810                 unsigned long sysenter_esp;
1811
1812                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1813                 local_irq_disable();
1814                 crash_disable_local_vmclear(cpu);
1815
1816                 /*
1817                  * Read loaded_vmcs->cpu should be before fetching
1818                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819                  * See the comments in __loaded_vmcs_clear().
1820                  */
1821                 smp_rmb();
1822
1823                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1825                 crash_enable_local_vmclear(cpu);
1826                 local_irq_enable();
1827
1828                 /*
1829                  * Linux uses per-cpu TSS and GDT, so set these when switching
1830                  * processors.
1831                  */
1832                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1833                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1834
1835                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1837                 vmx->loaded_vmcs->cpu = cpu;
1838         }
1839 }
1840
1841 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842 {
1843         __vmx_load_host_state(to_vmx(vcpu));
1844         if (!vmm_exclusive) {
1845                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846                 vcpu->cpu = -1;
1847                 kvm_cpu_vmxoff();
1848         }
1849 }
1850
1851 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852 {
1853         ulong cr0;
1854
1855         if (vcpu->fpu_active)
1856                 return;
1857         vcpu->fpu_active = 1;
1858         cr0 = vmcs_readl(GUEST_CR0);
1859         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861         vmcs_writel(GUEST_CR0, cr0);
1862         update_exception_bitmap(vcpu);
1863         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1864         if (is_guest_mode(vcpu))
1865                 vcpu->arch.cr0_guest_owned_bits &=
1866                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1867         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1868 }
1869
1870 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
1872 /*
1873  * Return the cr0 value that a nested guest would read. This is a combination
1874  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875  * its hypervisor (cr0_read_shadow).
1876  */
1877 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878 {
1879         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881 }
1882 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883 {
1884         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886 }
1887
1888 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889 {
1890         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891          * set this *before* calling this function.
1892          */
1893         vmx_decache_cr0_guest_bits(vcpu);
1894         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1895         update_exception_bitmap(vcpu);
1896         vcpu->arch.cr0_guest_owned_bits = 0;
1897         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1898         if (is_guest_mode(vcpu)) {
1899                 /*
1900                  * L1's specified read shadow might not contain the TS bit,
1901                  * so now that we turned on shadowing of this bit, we need to
1902                  * set this bit of the shadow. Like in nested_vmx_run we need
1903                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904                  * up-to-date here because we just decached cr0.TS (and we'll
1905                  * only update vmcs12->guest_cr0 on nested exit).
1906                  */
1907                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909                         (vcpu->arch.cr0 & X86_CR0_TS);
1910                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911         } else
1912                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1913 }
1914
1915 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916 {
1917         unsigned long rflags, save_rflags;
1918
1919         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921                 rflags = vmcs_readl(GUEST_RFLAGS);
1922                 if (to_vmx(vcpu)->rmode.vm86_active) {
1923                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926                 }
1927                 to_vmx(vcpu)->rflags = rflags;
1928         }
1929         return to_vmx(vcpu)->rflags;
1930 }
1931
1932 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933 {
1934         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935         to_vmx(vcpu)->rflags = rflags;
1936         if (to_vmx(vcpu)->rmode.vm86_active) {
1937                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1938                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1939         }
1940         vmcs_writel(GUEST_RFLAGS, rflags);
1941 }
1942
1943 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944 {
1945         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946         int ret = 0;
1947
1948         if (interruptibility & GUEST_INTR_STATE_STI)
1949                 ret |= KVM_X86_SHADOW_INT_STI;
1950         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1951                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1952
1953         return ret & mask;
1954 }
1955
1956 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957 {
1958         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959         u32 interruptibility = interruptibility_old;
1960
1961         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
1963         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1964                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1965         else if (mask & KVM_X86_SHADOW_INT_STI)
1966                 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968         if ((interruptibility != interruptibility_old))
1969                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970 }
1971
1972 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973 {
1974         unsigned long rip;
1975
1976         rip = kvm_rip_read(vcpu);
1977         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1978         kvm_rip_write(vcpu, rip);
1979
1980         /* skipping an emulated instruction also counts */
1981         vmx_set_interrupt_shadow(vcpu, 0);
1982 }
1983
1984 /*
1985  * KVM wants to inject page-faults which it got to the guest. This function
1986  * checks whether in a nested guest, we need to inject them to L1 or L2.
1987  */
1988 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1989 {
1990         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
1992         if (!(vmcs12->exception_bitmap & (1u << nr)))
1993                 return 0;
1994
1995         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996                           vmcs_read32(VM_EXIT_INTR_INFO),
1997                           vmcs_readl(EXIT_QUALIFICATION));
1998         return 1;
1999 }
2000
2001 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2002                                 bool has_error_code, u32 error_code,
2003                                 bool reinject)
2004 {
2005         struct vcpu_vmx *vmx = to_vmx(vcpu);
2006         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2007
2008         if (!reinject && is_guest_mode(vcpu) &&
2009             nested_vmx_check_exception(vcpu, nr))
2010                 return;
2011
2012         if (has_error_code) {
2013                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2014                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015         }
2016
2017         if (vmx->rmode.vm86_active) {
2018                 int inc_eip = 0;
2019                 if (kvm_exception_is_soft(nr))
2020                         inc_eip = vcpu->arch.event_exit_inst_len;
2021                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2022                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2023                 return;
2024         }
2025
2026         if (kvm_exception_is_soft(nr)) {
2027                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028                              vmx->vcpu.arch.event_exit_inst_len);
2029                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030         } else
2031                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2034 }
2035
2036 static bool vmx_rdtscp_supported(void)
2037 {
2038         return cpu_has_vmx_rdtscp();
2039 }
2040
2041 static bool vmx_invpcid_supported(void)
2042 {
2043         return cpu_has_vmx_invpcid() && enable_ept;
2044 }
2045
2046 /*
2047  * Swap MSR entry in host/guest MSR entry array.
2048  */
2049 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2050 {
2051         struct shared_msr_entry tmp;
2052
2053         tmp = vmx->guest_msrs[to];
2054         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055         vmx->guest_msrs[from] = tmp;
2056 }
2057
2058 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059 {
2060         unsigned long *msr_bitmap;
2061
2062         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063                 if (is_long_mode(vcpu))
2064                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065                 else
2066                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067         } else {
2068                 if (is_long_mode(vcpu))
2069                         msr_bitmap = vmx_msr_bitmap_longmode;
2070                 else
2071                         msr_bitmap = vmx_msr_bitmap_legacy;
2072         }
2073
2074         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075 }
2076
2077 /*
2078  * Set up the vmcs to automatically save and restore system
2079  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2080  * mode, as fiddling with msrs is very expensive.
2081  */
2082 static void setup_msrs(struct vcpu_vmx *vmx)
2083 {
2084         int save_nmsrs, index;
2085
2086         save_nmsrs = 0;
2087 #ifdef CONFIG_X86_64
2088         if (is_long_mode(&vmx->vcpu)) {
2089                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2090                 if (index >= 0)
2091                         move_msr_up(vmx, index, save_nmsrs++);
2092                 index = __find_msr_index(vmx, MSR_LSTAR);
2093                 if (index >= 0)
2094                         move_msr_up(vmx, index, save_nmsrs++);
2095                 index = __find_msr_index(vmx, MSR_CSTAR);
2096                 if (index >= 0)
2097                         move_msr_up(vmx, index, save_nmsrs++);
2098                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099                 if (index >= 0 && vmx->rdtscp_enabled)
2100                         move_msr_up(vmx, index, save_nmsrs++);
2101                 /*
2102                  * MSR_STAR is only needed on long mode guests, and only
2103                  * if efer.sce is enabled.
2104                  */
2105                 index = __find_msr_index(vmx, MSR_STAR);
2106                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2107                         move_msr_up(vmx, index, save_nmsrs++);
2108         }
2109 #endif
2110         index = __find_msr_index(vmx, MSR_EFER);
2111         if (index >= 0 && update_transition_efer(vmx, index))
2112                 move_msr_up(vmx, index, save_nmsrs++);
2113
2114         vmx->save_nmsrs = save_nmsrs;
2115
2116         if (cpu_has_vmx_msr_bitmap())
2117                 vmx_set_msr_bitmap(&vmx->vcpu);
2118 }
2119
2120 /*
2121  * reads and returns guest's timestamp counter "register"
2122  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2123  */
2124 static u64 guest_read_tsc(void)
2125 {
2126         u64 host_tsc, tsc_offset;
2127
2128         rdtscll(host_tsc);
2129         tsc_offset = vmcs_read64(TSC_OFFSET);
2130         return host_tsc + tsc_offset;
2131 }
2132
2133 /*
2134  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135  * counter, even if a nested guest (L2) is currently running.
2136  */
2137 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2138 {
2139         u64 tsc_offset;
2140
2141         tsc_offset = is_guest_mode(vcpu) ?
2142                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143                 vmcs_read64(TSC_OFFSET);
2144         return host_tsc + tsc_offset;
2145 }
2146
2147 /*
2148  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2149  * software catchup for faster rates on slower CPUs.
2150  */
2151 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2152 {
2153         if (!scale)
2154                 return;
2155
2156         if (user_tsc_khz > tsc_khz) {
2157                 vcpu->arch.tsc_catchup = 1;
2158                 vcpu->arch.tsc_always_catchup = 1;
2159         } else
2160                 WARN(1, "user requested TSC rate below hardware speed\n");
2161 }
2162
2163 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164 {
2165         return vmcs_read64(TSC_OFFSET);
2166 }
2167
2168 /*
2169  * writes 'offset' into guest's timestamp counter offset register
2170  */
2171 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2172 {
2173         if (is_guest_mode(vcpu)) {
2174                 /*
2175                  * We're here if L1 chose not to trap WRMSR to TSC. According
2176                  * to the spec, this should set L1's TSC; The offset that L1
2177                  * set for L2 remains unchanged, and still needs to be added
2178                  * to the newly set TSC to get L2's TSC.
2179                  */
2180                 struct vmcs12 *vmcs12;
2181                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182                 /* recalculate vmcs02.TSC_OFFSET: */
2183                 vmcs12 = get_vmcs12(vcpu);
2184                 vmcs_write64(TSC_OFFSET, offset +
2185                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186                          vmcs12->tsc_offset : 0));
2187         } else {
2188                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189                                            vmcs_read64(TSC_OFFSET), offset);
2190                 vmcs_write64(TSC_OFFSET, offset);
2191         }
2192 }
2193
2194 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2195 {
2196         u64 offset = vmcs_read64(TSC_OFFSET);
2197
2198         vmcs_write64(TSC_OFFSET, offset + adjustment);
2199         if (is_guest_mode(vcpu)) {
2200                 /* Even when running L2, the adjustment needs to apply to L1 */
2201                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2202         } else
2203                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204                                            offset + adjustment);
2205 }
2206
2207 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208 {
2209         return target_tsc - native_read_tsc();
2210 }
2211
2212 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213 {
2214         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216 }
2217
2218 /*
2219  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221  * all guests if the "nested" module option is off, and can also be disabled
2222  * for a single guest by disabling its VMX cpuid bit.
2223  */
2224 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225 {
2226         return nested && guest_cpuid_has_vmx(vcpu);
2227 }
2228
2229 /*
2230  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231  * returned for the various VMX controls MSRs when nested VMX is enabled.
2232  * The same values should also be used to verify that vmcs12 control fields are
2233  * valid during nested entry from L1 to L2.
2234  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236  * bit in the high half is on if the corresponding bit in the control field
2237  * may be on. See also vmx_control_verify().
2238  * TODO: allow these variables to be modified (downgraded) by module options
2239  * or other means.
2240  */
2241 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2246 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2247 static u32 nested_vmx_ept_caps;
2248 static __init void nested_vmx_setup_ctls_msrs(void)
2249 {
2250         /*
2251          * Note that as a general rule, the high half of the MSRs (bits in
2252          * the control fields which may be 1) should be initialized by the
2253          * intersection of the underlying hardware's MSR (i.e., features which
2254          * can be supported) and the list of features we want to expose -
2255          * because they are known to be properly supported in our code.
2256          * Also, usually, the low half of the MSRs (bits which must be 1) can
2257          * be set to 0, meaning that L1 may turn off any of these bits. The
2258          * reason is that if one of these bits is necessary, it will appear
2259          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260          * fields of vmcs01 and vmcs02, will turn these bits off - and
2261          * nested_vmx_exit_handled() will not pass related exits to L1.
2262          * These rules have exceptions below.
2263          */
2264
2265         /* pin-based controls */
2266         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2268         /*
2269          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271          */
2272         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2274                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2276                 PIN_BASED_VMX_PREEMPTION_TIMER;
2277
2278         /*
2279          * Exit controls
2280          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2281          * 17 must be 1.
2282          */
2283         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2285         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2286
2287         nested_vmx_exit_ctls_high &=
2288 #ifdef CONFIG_X86_64
2289                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2290 #endif
2291                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2294                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2295
2296         if (vmx_mpx_supported())
2297                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2298
2299         /* entry controls */
2300         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2301                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2302         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2303         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2304         nested_vmx_entry_ctls_high &=
2305 #ifdef CONFIG_X86_64
2306                 VM_ENTRY_IA32E_MODE |
2307 #endif
2308                 VM_ENTRY_LOAD_IA32_PAT;
2309         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2310                                        VM_ENTRY_LOAD_IA32_EFER);
2311         if (vmx_mpx_supported())
2312                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2313
2314         /* cpu-based controls */
2315         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2316                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2317         nested_vmx_procbased_ctls_low = 0;
2318         nested_vmx_procbased_ctls_high &=
2319                 CPU_BASED_VIRTUAL_INTR_PENDING |
2320                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2321                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2322                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2323                 CPU_BASED_CR3_STORE_EXITING |
2324 #ifdef CONFIG_X86_64
2325                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2326 #endif
2327                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2328                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2329                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2330                 CPU_BASED_PAUSE_EXITING |
2331                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2332         /*
2333          * We can allow some features even when not supported by the
2334          * hardware. For example, L1 can specify an MSR bitmap - and we
2335          * can use it to avoid exits to L1 - even when L0 runs L2
2336          * without MSR bitmaps.
2337          */
2338         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2339
2340         /* secondary cpu-based controls */
2341         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2342                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2343         nested_vmx_secondary_ctls_low = 0;
2344         nested_vmx_secondary_ctls_high &=
2345                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2346                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2347                 SECONDARY_EXEC_WBINVD_EXITING;
2348
2349         if (enable_ept) {
2350                 /* nested EPT: emulate EPT also to L1 */
2351                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2352                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2353                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2354                          VMX_EPT_INVEPT_BIT;
2355                 nested_vmx_ept_caps &= vmx_capability.ept;
2356                 /*
2357                  * For nested guests, we don't do anything specific
2358                  * for single context invalidation. Hence, only advertise
2359                  * support for global context invalidation.
2360                  */
2361                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2362         } else
2363                 nested_vmx_ept_caps = 0;
2364
2365         /* miscellaneous data */
2366         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2367         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2368         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2369                 VMX_MISC_ACTIVITY_HLT;
2370         nested_vmx_misc_high = 0;
2371 }
2372
2373 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2374 {
2375         /*
2376          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2377          */
2378         return ((control & high) | low) == control;
2379 }
2380
2381 static inline u64 vmx_control_msr(u32 low, u32 high)
2382 {
2383         return low | ((u64)high << 32);
2384 }
2385
2386 /* Returns 0 on success, non-0 otherwise. */
2387 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2388 {
2389         switch (msr_index) {
2390         case MSR_IA32_VMX_BASIC:
2391                 /*
2392                  * This MSR reports some information about VMX support. We
2393                  * should return information about the VMX we emulate for the
2394                  * guest, and the VMCS structure we give it - not about the
2395                  * VMX support of the underlying hardware.
2396                  */
2397                 *pdata = VMCS12_REVISION |
2398                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2399                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2400                 break;
2401         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2402         case MSR_IA32_VMX_PINBASED_CTLS:
2403                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2404                                         nested_vmx_pinbased_ctls_high);
2405                 break;
2406         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2407         case MSR_IA32_VMX_PROCBASED_CTLS:
2408                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409                                         nested_vmx_procbased_ctls_high);
2410                 break;
2411         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412         case MSR_IA32_VMX_EXIT_CTLS:
2413                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414                                         nested_vmx_exit_ctls_high);
2415                 break;
2416         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417         case MSR_IA32_VMX_ENTRY_CTLS:
2418                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419                                         nested_vmx_entry_ctls_high);
2420                 break;
2421         case MSR_IA32_VMX_MISC:
2422                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423                                          nested_vmx_misc_high);
2424                 break;
2425         /*
2426          * These MSRs specify bits which the guest must keep fixed (on or off)
2427          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428          * We picked the standard core2 setting.
2429          */
2430 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2432         case MSR_IA32_VMX_CR0_FIXED0:
2433                 *pdata = VMXON_CR0_ALWAYSON;
2434                 break;
2435         case MSR_IA32_VMX_CR0_FIXED1:
2436                 *pdata = -1ULL;
2437                 break;
2438         case MSR_IA32_VMX_CR4_FIXED0:
2439                 *pdata = VMXON_CR4_ALWAYSON;
2440                 break;
2441         case MSR_IA32_VMX_CR4_FIXED1:
2442                 *pdata = -1ULL;
2443                 break;
2444         case MSR_IA32_VMX_VMCS_ENUM:
2445                 *pdata = 0x1f;
2446                 break;
2447         case MSR_IA32_VMX_PROCBASED_CTLS2:
2448                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449                                         nested_vmx_secondary_ctls_high);
2450                 break;
2451         case MSR_IA32_VMX_EPT_VPID_CAP:
2452                 /* Currently, no nested vpid support */
2453                 *pdata = nested_vmx_ept_caps;
2454                 break;
2455         default:
2456                 return 1;
2457         }
2458
2459         return 0;
2460 }
2461
2462 /*
2463  * Reads an msr value (of 'msr_index') into 'pdata'.
2464  * Returns 0 on success, non-0 otherwise.
2465  * Assumes vcpu_load() was already called.
2466  */
2467 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2468 {
2469         u64 data;
2470         struct shared_msr_entry *msr;
2471
2472         if (!pdata) {
2473                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2474                 return -EINVAL;
2475         }
2476
2477         switch (msr_index) {
2478 #ifdef CONFIG_X86_64
2479         case MSR_FS_BASE:
2480                 data = vmcs_readl(GUEST_FS_BASE);
2481                 break;
2482         case MSR_GS_BASE:
2483                 data = vmcs_readl(GUEST_GS_BASE);
2484                 break;
2485         case MSR_KERNEL_GS_BASE:
2486                 vmx_load_host_state(to_vmx(vcpu));
2487                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2488                 break;
2489 #endif
2490         case MSR_EFER:
2491                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2492         case MSR_IA32_TSC:
2493                 data = guest_read_tsc();
2494                 break;
2495         case MSR_IA32_SYSENTER_CS:
2496                 data = vmcs_read32(GUEST_SYSENTER_CS);
2497                 break;
2498         case MSR_IA32_SYSENTER_EIP:
2499                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2500                 break;
2501         case MSR_IA32_SYSENTER_ESP:
2502                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2503                 break;
2504         case MSR_IA32_BNDCFGS:
2505                 if (!vmx_mpx_supported())
2506                         return 1;
2507                 data = vmcs_read64(GUEST_BNDCFGS);
2508                 break;
2509         case MSR_IA32_FEATURE_CONTROL:
2510                 if (!nested_vmx_allowed(vcpu))
2511                         return 1;
2512                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2513                 break;
2514         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2515                 if (!nested_vmx_allowed(vcpu))
2516                         return 1;
2517                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2518         case MSR_TSC_AUX:
2519                 if (!to_vmx(vcpu)->rdtscp_enabled)
2520                         return 1;
2521                 /* Otherwise falls through */
2522         default:
2523                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2524                 if (msr) {
2525                         data = msr->data;
2526                         break;
2527                 }
2528                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2529         }
2530
2531         *pdata = data;
2532         return 0;
2533 }
2534
2535 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2536
2537 /*
2538  * Writes msr value into into the appropriate "register".
2539  * Returns 0 on success, non-0 otherwise.
2540  * Assumes vcpu_load() was already called.
2541  */
2542 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2543 {
2544         struct vcpu_vmx *vmx = to_vmx(vcpu);
2545         struct shared_msr_entry *msr;
2546         int ret = 0;
2547         u32 msr_index = msr_info->index;
2548         u64 data = msr_info->data;
2549
2550         switch (msr_index) {
2551         case MSR_EFER:
2552                 ret = kvm_set_msr_common(vcpu, msr_info);
2553                 break;
2554 #ifdef CONFIG_X86_64
2555         case MSR_FS_BASE:
2556                 vmx_segment_cache_clear(vmx);
2557                 vmcs_writel(GUEST_FS_BASE, data);
2558                 break;
2559         case MSR_GS_BASE:
2560                 vmx_segment_cache_clear(vmx);
2561                 vmcs_writel(GUEST_GS_BASE, data);
2562                 break;
2563         case MSR_KERNEL_GS_BASE:
2564                 vmx_load_host_state(vmx);
2565                 vmx->msr_guest_kernel_gs_base = data;
2566                 break;
2567 #endif
2568         case MSR_IA32_SYSENTER_CS:
2569                 vmcs_write32(GUEST_SYSENTER_CS, data);
2570                 break;
2571         case MSR_IA32_SYSENTER_EIP:
2572                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2573                 break;
2574         case MSR_IA32_SYSENTER_ESP:
2575                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2576                 break;
2577         case MSR_IA32_BNDCFGS:
2578                 if (!vmx_mpx_supported())
2579                         return 1;
2580                 vmcs_write64(GUEST_BNDCFGS, data);
2581                 break;
2582         case MSR_IA32_TSC:
2583                 kvm_write_tsc(vcpu, msr_info);
2584                 break;
2585         case MSR_IA32_CR_PAT:
2586                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2587                         vmcs_write64(GUEST_IA32_PAT, data);
2588                         vcpu->arch.pat = data;
2589                         break;
2590                 }
2591                 ret = kvm_set_msr_common(vcpu, msr_info);
2592                 break;
2593         case MSR_IA32_TSC_ADJUST:
2594                 ret = kvm_set_msr_common(vcpu, msr_info);
2595                 break;
2596         case MSR_IA32_FEATURE_CONTROL:
2597                 if (!nested_vmx_allowed(vcpu) ||
2598                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2599                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2600                         return 1;
2601                 vmx->nested.msr_ia32_feature_control = data;
2602                 if (msr_info->host_initiated && data == 0)
2603                         vmx_leave_nested(vcpu);
2604                 break;
2605         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2606                 return 1; /* they are read-only */
2607         case MSR_TSC_AUX:
2608                 if (!vmx->rdtscp_enabled)
2609                         return 1;
2610                 /* Check reserved bit, higher 32 bits should be zero */
2611                 if ((data >> 32) != 0)
2612                         return 1;
2613                 /* Otherwise falls through */
2614         default:
2615                 msr = find_msr_entry(vmx, msr_index);
2616                 if (msr) {
2617                         msr->data = data;
2618                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2619                                 preempt_disable();
2620                                 kvm_set_shared_msr(msr->index, msr->data,
2621                                                    msr->mask);
2622                                 preempt_enable();
2623                         }
2624                         break;
2625                 }
2626                 ret = kvm_set_msr_common(vcpu, msr_info);
2627         }
2628
2629         return ret;
2630 }
2631
2632 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2633 {
2634         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2635         switch (reg) {
2636         case VCPU_REGS_RSP:
2637                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2638                 break;
2639         case VCPU_REGS_RIP:
2640                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2641                 break;
2642         case VCPU_EXREG_PDPTR:
2643                 if (enable_ept)
2644                         ept_save_pdptrs(vcpu);
2645                 break;
2646         default:
2647                 break;
2648         }
2649 }
2650
2651 static __init int cpu_has_kvm_support(void)
2652 {
2653         return cpu_has_vmx();
2654 }
2655
2656 static __init int vmx_disabled_by_bios(void)
2657 {
2658         u64 msr;
2659
2660         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2661         if (msr & FEATURE_CONTROL_LOCKED) {
2662                 /* launched w/ TXT and VMX disabled */
2663                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2664                         && tboot_enabled())
2665                         return 1;
2666                 /* launched w/o TXT and VMX only enabled w/ TXT */
2667                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2668                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2669                         && !tboot_enabled()) {
2670                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2671                                 "activate TXT before enabling KVM\n");
2672                         return 1;
2673                 }
2674                 /* launched w/o TXT and VMX disabled */
2675                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2676                         && !tboot_enabled())
2677                         return 1;
2678         }
2679
2680         return 0;
2681 }
2682
2683 static void kvm_cpu_vmxon(u64 addr)
2684 {
2685         asm volatile (ASM_VMX_VMXON_RAX
2686                         : : "a"(&addr), "m"(addr)
2687                         : "memory", "cc");
2688 }
2689
2690 static int hardware_enable(void *garbage)
2691 {
2692         int cpu = raw_smp_processor_id();
2693         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2694         u64 old, test_bits;
2695
2696         if (read_cr4() & X86_CR4_VMXE)
2697                 return -EBUSY;
2698
2699         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2700
2701         /*
2702          * Now we can enable the vmclear operation in kdump
2703          * since the loaded_vmcss_on_cpu list on this cpu
2704          * has been initialized.
2705          *
2706          * Though the cpu is not in VMX operation now, there
2707          * is no problem to enable the vmclear operation
2708          * for the loaded_vmcss_on_cpu list is empty!
2709          */
2710         crash_enable_local_vmclear(cpu);
2711
2712         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2713
2714         test_bits = FEATURE_CONTROL_LOCKED;
2715         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2716         if (tboot_enabled())
2717                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2718
2719         if ((old & test_bits) != test_bits) {
2720                 /* enable and lock */
2721                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2722         }
2723         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2724
2725         if (vmm_exclusive) {
2726                 kvm_cpu_vmxon(phys_addr);
2727                 ept_sync_global();
2728         }
2729
2730         native_store_gdt(&__get_cpu_var(host_gdt));
2731
2732         return 0;
2733 }
2734
2735 static void vmclear_local_loaded_vmcss(void)
2736 {
2737         int cpu = raw_smp_processor_id();
2738         struct loaded_vmcs *v, *n;
2739
2740         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2741                                  loaded_vmcss_on_cpu_link)
2742                 __loaded_vmcs_clear(v);
2743 }
2744
2745
2746 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2747  * tricks.
2748  */
2749 static void kvm_cpu_vmxoff(void)
2750 {
2751         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2752 }
2753
2754 static void hardware_disable(void *garbage)
2755 {
2756         if (vmm_exclusive) {
2757                 vmclear_local_loaded_vmcss();
2758                 kvm_cpu_vmxoff();
2759         }
2760         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2761 }
2762
2763 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2764                                       u32 msr, u32 *result)
2765 {
2766         u32 vmx_msr_low, vmx_msr_high;
2767         u32 ctl = ctl_min | ctl_opt;
2768
2769         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2770
2771         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2772         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2773
2774         /* Ensure minimum (required) set of control bits are supported. */
2775         if (ctl_min & ~ctl)
2776                 return -EIO;
2777
2778         *result = ctl;
2779         return 0;
2780 }
2781
2782 static __init bool allow_1_setting(u32 msr, u32 ctl)
2783 {
2784         u32 vmx_msr_low, vmx_msr_high;
2785
2786         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2787         return vmx_msr_high & ctl;
2788 }
2789
2790 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2791 {
2792         u32 vmx_msr_low, vmx_msr_high;
2793         u32 min, opt, min2, opt2;
2794         u32 _pin_based_exec_control = 0;
2795         u32 _cpu_based_exec_control = 0;
2796         u32 _cpu_based_2nd_exec_control = 0;
2797         u32 _vmexit_control = 0;
2798         u32 _vmentry_control = 0;
2799
2800         min = CPU_BASED_HLT_EXITING |
2801 #ifdef CONFIG_X86_64
2802               CPU_BASED_CR8_LOAD_EXITING |
2803               CPU_BASED_CR8_STORE_EXITING |
2804 #endif
2805               CPU_BASED_CR3_LOAD_EXITING |
2806               CPU_BASED_CR3_STORE_EXITING |
2807               CPU_BASED_USE_IO_BITMAPS |
2808               CPU_BASED_MOV_DR_EXITING |
2809               CPU_BASED_USE_TSC_OFFSETING |
2810               CPU_BASED_MWAIT_EXITING |
2811               CPU_BASED_MONITOR_EXITING |
2812               CPU_BASED_INVLPG_EXITING |
2813               CPU_BASED_RDPMC_EXITING;
2814
2815         opt = CPU_BASED_TPR_SHADOW |
2816               CPU_BASED_USE_MSR_BITMAPS |
2817               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2818         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2819                                 &_cpu_based_exec_control) < 0)
2820                 return -EIO;
2821 #ifdef CONFIG_X86_64
2822         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2824                                            ~CPU_BASED_CR8_STORE_EXITING;
2825 #endif
2826         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2827                 min2 = 0;
2828                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2829                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2830                         SECONDARY_EXEC_WBINVD_EXITING |
2831                         SECONDARY_EXEC_ENABLE_VPID |
2832                         SECONDARY_EXEC_ENABLE_EPT |
2833                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2834                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2835                         SECONDARY_EXEC_RDTSCP |
2836                         SECONDARY_EXEC_ENABLE_INVPCID |
2837                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2838                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2839                         SECONDARY_EXEC_SHADOW_VMCS;
2840                 if (adjust_vmx_controls(min2, opt2,
2841                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2842                                         &_cpu_based_2nd_exec_control) < 0)
2843                         return -EIO;
2844         }
2845 #ifndef CONFIG_X86_64
2846         if (!(_cpu_based_2nd_exec_control &
2847                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2848                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2849 #endif
2850
2851         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2852                 _cpu_based_2nd_exec_control &= ~(
2853                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2854                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2855                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2856
2857         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2858                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2859                    enabled */
2860                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2861                                              CPU_BASED_CR3_STORE_EXITING |
2862                                              CPU_BASED_INVLPG_EXITING);
2863                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2864                       vmx_capability.ept, vmx_capability.vpid);
2865         }
2866
2867         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2868 #ifdef CONFIG_X86_64
2869         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2870 #endif
2871         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2872                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2873         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2874                                 &_vmexit_control) < 0)
2875                 return -EIO;
2876
2877         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2878         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2879         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2880                                 &_pin_based_exec_control) < 0)
2881                 return -EIO;
2882
2883         if (!(_cpu_based_2nd_exec_control &
2884                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2885                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2886                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2887
2888         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2889         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2890         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2891                                 &_vmentry_control) < 0)
2892                 return -EIO;
2893
2894         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2895
2896         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2898                 return -EIO;
2899
2900 #ifdef CONFIG_X86_64
2901         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902         if (vmx_msr_high & (1u<<16))
2903                 return -EIO;
2904 #endif
2905
2906         /* Require Write-Back (WB) memory type for VMCS accesses. */
2907         if (((vmx_msr_high >> 18) & 15) != 6)
2908                 return -EIO;
2909
2910         vmcs_conf->size = vmx_msr_high & 0x1fff;
2911         vmcs_conf->order = get_order(vmcs_config.size);
2912         vmcs_conf->revision_id = vmx_msr_low;
2913
2914         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2915         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2916         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2917         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2918         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2919
2920         cpu_has_load_ia32_efer =
2921                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2922                                 VM_ENTRY_LOAD_IA32_EFER)
2923                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2924                                    VM_EXIT_LOAD_IA32_EFER);
2925
2926         cpu_has_load_perf_global_ctrl =
2927                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2928                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2929                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2930                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2931
2932         /*
2933          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934          * but due to arrata below it can't be used. Workaround is to use
2935          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2936          *
2937          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2938          *
2939          * AAK155             (model 26)
2940          * AAP115             (model 30)
2941          * AAT100             (model 37)
2942          * BC86,AAY89,BD102   (model 44)
2943          * BA97               (model 46)
2944          *
2945          */
2946         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2947                 switch (boot_cpu_data.x86_model) {
2948                 case 26:
2949                 case 30:
2950                 case 37:
2951                 case 44:
2952                 case 46:
2953                         cpu_has_load_perf_global_ctrl = false;
2954                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955                                         "does not work properly. Using workaround\n");
2956                         break;
2957                 default:
2958                         break;
2959                 }
2960         }
2961
2962         return 0;
2963 }
2964
2965 static struct vmcs *alloc_vmcs_cpu(int cpu)
2966 {
2967         int node = cpu_to_node(cpu);
2968         struct page *pages;
2969         struct vmcs *vmcs;
2970
2971         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2972         if (!pages)
2973                 return NULL;
2974         vmcs = page_address(pages);
2975         memset(vmcs, 0, vmcs_config.size);
2976         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2977         return vmcs;
2978 }
2979
2980 static struct vmcs *alloc_vmcs(void)
2981 {
2982         return alloc_vmcs_cpu(raw_smp_processor_id());
2983 }
2984
2985 static void free_vmcs(struct vmcs *vmcs)
2986 {
2987         free_pages((unsigned long)vmcs, vmcs_config.order);
2988 }
2989
2990 /*
2991  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2992  */
2993 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2994 {
2995         if (!loaded_vmcs->vmcs)
2996                 return;
2997         loaded_vmcs_clear(loaded_vmcs);
2998         free_vmcs(loaded_vmcs->vmcs);
2999         loaded_vmcs->vmcs = NULL;
3000 }
3001
3002 static void free_kvm_area(void)
3003 {
3004         int cpu;
3005
3006         for_each_possible_cpu(cpu) {
3007                 free_vmcs(per_cpu(vmxarea, cpu));
3008                 per_cpu(vmxarea, cpu) = NULL;
3009         }
3010 }
3011
3012 static __init int alloc_kvm_area(void)
3013 {
3014         int cpu;
3015
3016         for_each_possible_cpu(cpu) {
3017                 struct vmcs *vmcs;
3018
3019                 vmcs = alloc_vmcs_cpu(cpu);
3020                 if (!vmcs) {
3021                         free_kvm_area();
3022                         return -ENOMEM;
3023                 }
3024
3025                 per_cpu(vmxarea, cpu) = vmcs;
3026         }
3027         return 0;
3028 }
3029
3030 static __init int hardware_setup(void)
3031 {
3032         if (setup_vmcs_config(&vmcs_config) < 0)
3033                 return -EIO;
3034
3035         if (boot_cpu_has(X86_FEATURE_NX))
3036                 kvm_enable_efer_bits(EFER_NX);
3037
3038         if (!cpu_has_vmx_vpid())
3039                 enable_vpid = 0;
3040         if (!cpu_has_vmx_shadow_vmcs())
3041                 enable_shadow_vmcs = 0;
3042
3043         if (!cpu_has_vmx_ept() ||
3044             !cpu_has_vmx_ept_4levels()) {
3045                 enable_ept = 0;
3046                 enable_unrestricted_guest = 0;
3047                 enable_ept_ad_bits = 0;
3048         }
3049
3050         if (!cpu_has_vmx_ept_ad_bits())
3051                 enable_ept_ad_bits = 0;
3052
3053         if (!cpu_has_vmx_unrestricted_guest())
3054                 enable_unrestricted_guest = 0;
3055
3056         if (!cpu_has_vmx_flexpriority())
3057                 flexpriority_enabled = 0;
3058
3059         if (!cpu_has_vmx_tpr_shadow())
3060                 kvm_x86_ops->update_cr8_intercept = NULL;
3061
3062         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3063                 kvm_disable_largepages();
3064
3065         if (!cpu_has_vmx_ple())
3066                 ple_gap = 0;
3067
3068         if (!cpu_has_vmx_apicv())
3069                 enable_apicv = 0;
3070
3071         if (enable_apicv)
3072                 kvm_x86_ops->update_cr8_intercept = NULL;
3073         else {
3074                 kvm_x86_ops->hwapic_irr_update = NULL;
3075                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3076                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3077         }
3078
3079         if (nested)
3080                 nested_vmx_setup_ctls_msrs();
3081
3082         return alloc_kvm_area();
3083 }
3084
3085 static __exit void hardware_unsetup(void)
3086 {
3087         free_kvm_area();
3088 }
3089
3090 static bool emulation_required(struct kvm_vcpu *vcpu)
3091 {
3092         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3093 }
3094
3095 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3096                 struct kvm_segment *save)
3097 {
3098         if (!emulate_invalid_guest_state) {
3099                 /*
3100                  * CS and SS RPL should be equal during guest entry according
3101                  * to VMX spec, but in reality it is not always so. Since vcpu
3102                  * is in the middle of the transition from real mode to
3103                  * protected mode it is safe to assume that RPL 0 is a good
3104                  * default value.
3105                  */
3106                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3107                         save->selector &= ~SELECTOR_RPL_MASK;
3108                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3109                 save->s = 1;
3110         }
3111         vmx_set_segment(vcpu, save, seg);
3112 }
3113
3114 static void enter_pmode(struct kvm_vcpu *vcpu)
3115 {
3116         unsigned long flags;
3117         struct vcpu_vmx *vmx = to_vmx(vcpu);
3118
3119         /*
3120          * Update real mode segment cache. It may be not up-to-date if sement
3121          * register was written while vcpu was in a guest mode.
3122          */
3123         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3124         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3127         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3128         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3129
3130         vmx->rmode.vm86_active = 0;
3131
3132         vmx_segment_cache_clear(vmx);
3133
3134         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3135
3136         flags = vmcs_readl(GUEST_RFLAGS);
3137         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3138         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3139         vmcs_writel(GUEST_RFLAGS, flags);
3140
3141         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3142                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3143
3144         update_exception_bitmap(vcpu);
3145
3146         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3147         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3148         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3149         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3150         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3151         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3152 }
3153
3154 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3155 {
3156         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3157         struct kvm_segment var = *save;
3158
3159         var.dpl = 0x3;
3160         if (seg == VCPU_SREG_CS)
3161                 var.type = 0x3;
3162
3163         if (!emulate_invalid_guest_state) {
3164                 var.selector = var.base >> 4;
3165                 var.base = var.base & 0xffff0;
3166                 var.limit = 0xffff;
3167                 var.g = 0;
3168                 var.db = 0;
3169                 var.present = 1;
3170                 var.s = 1;
3171                 var.l = 0;
3172                 var.unusable = 0;
3173                 var.type = 0x3;
3174                 var.avl = 0;
3175                 if (save->base & 0xf)
3176                         printk_once(KERN_WARNING "kvm: segment base is not "
3177                                         "paragraph aligned when entering "
3178                                         "protected mode (seg=%d)", seg);
3179         }
3180
3181         vmcs_write16(sf->selector, var.selector);
3182         vmcs_write32(sf->base, var.base);
3183         vmcs_write32(sf->limit, var.limit);
3184         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3185 }
3186
3187 static void enter_rmode(struct kvm_vcpu *vcpu)
3188 {
3189         unsigned long flags;
3190         struct vcpu_vmx *vmx = to_vmx(vcpu);
3191
3192         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3193         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3194         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3195         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3196         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3197         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3198         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3199
3200         vmx->rmode.vm86_active = 1;
3201
3202         /*
3203          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3204          * vcpu. Warn the user that an update is overdue.
3205          */
3206         if (!vcpu->kvm->arch.tss_addr)
3207                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3208                              "called before entering vcpu\n");
3209
3210         vmx_segment_cache_clear(vmx);
3211
3212         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3213         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3214         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3215
3216         flags = vmcs_readl(GUEST_RFLAGS);
3217         vmx->rmode.save_rflags = flags;
3218
3219         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3220
3221         vmcs_writel(GUEST_RFLAGS, flags);
3222         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3223         update_exception_bitmap(vcpu);
3224
3225         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3226         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3227         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3228         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3229         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3230         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3231
3232         kvm_mmu_reset_context(vcpu);
3233 }
3234
3235 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3236 {
3237         struct vcpu_vmx *vmx = to_vmx(vcpu);
3238         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3239
3240         if (!msr)
3241                 return;
3242
3243         /*
3244          * Force kernel_gs_base reloading before EFER changes, as control
3245          * of this msr depends on is_long_mode().
3246          */
3247         vmx_load_host_state(to_vmx(vcpu));
3248         vcpu->arch.efer = efer;
3249         if (efer & EFER_LMA) {
3250                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3251                 msr->data = efer;
3252         } else {
3253                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3254
3255                 msr->data = efer & ~EFER_LME;
3256         }
3257         setup_msrs(vmx);
3258 }
3259
3260 #ifdef CONFIG_X86_64
3261
3262 static void enter_lmode(struct kvm_vcpu *vcpu)
3263 {
3264         u32 guest_tr_ar;
3265
3266         vmx_segment_cache_clear(to_vmx(vcpu));
3267
3268         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3269         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3270                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3271                                      __func__);
3272                 vmcs_write32(GUEST_TR_AR_BYTES,
3273                              (guest_tr_ar & ~AR_TYPE_MASK)
3274                              | AR_TYPE_BUSY_64_TSS);
3275         }
3276         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3277 }
3278
3279 static void exit_lmode(struct kvm_vcpu *vcpu)
3280 {
3281         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3282         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3283 }
3284
3285 #endif
3286
3287 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3288 {
3289         vpid_sync_context(to_vmx(vcpu));
3290         if (enable_ept) {
3291                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3292                         return;
3293                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3294         }
3295 }
3296
3297 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3298 {
3299         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3300
3301         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3302         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3303 }
3304
3305 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3306 {
3307         if (enable_ept && is_paging(vcpu))
3308                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3309         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3310 }
3311
3312 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3313 {
3314         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3315
3316         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3317         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3318 }
3319
3320 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3321 {
3322         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3323
3324         if (!test_bit(VCPU_EXREG_PDPTR,
3325                       (unsigned long *)&vcpu->arch.regs_dirty))
3326                 return;
3327
3328         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3329                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3330                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3331                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3332                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3333         }
3334 }
3335
3336 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3337 {
3338         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3339
3340         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3341                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3342                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3343                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3344                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3345         }
3346
3347         __set_bit(VCPU_EXREG_PDPTR,
3348                   (unsigned long *)&vcpu->arch.regs_avail);
3349         __set_bit(VCPU_EXREG_PDPTR,
3350                   (unsigned long *)&vcpu->arch.regs_dirty);
3351 }
3352
3353 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3354
3355 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3356                                         unsigned long cr0,
3357                                         struct kvm_vcpu *vcpu)
3358 {
3359         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3360                 vmx_decache_cr3(vcpu);
3361         if (!(cr0 & X86_CR0_PG)) {
3362                 /* From paging/starting to nonpaging */
3363                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3364                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3365                              (CPU_BASED_CR3_LOAD_EXITING |
3366                               CPU_BASED_CR3_STORE_EXITING));
3367                 vcpu->arch.cr0 = cr0;
3368                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3369         } else if (!is_paging(vcpu)) {
3370                 /* From nonpaging to paging */
3371                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3372                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3373                              ~(CPU_BASED_CR3_LOAD_EXITING |
3374                                CPU_BASED_CR3_STORE_EXITING));
3375                 vcpu->arch.cr0 = cr0;
3376                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3377         }
3378
3379         if (!(cr0 & X86_CR0_WP))
3380                 *hw_cr0 &= ~X86_CR0_WP;
3381 }
3382
3383 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3384 {
3385         struct vcpu_vmx *vmx = to_vmx(vcpu);
3386         unsigned long hw_cr0;
3387
3388         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3389         if (enable_unrestricted_guest)
3390                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3391         else {
3392                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3393
3394                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3395                         enter_pmode(vcpu);
3396
3397                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3398                         enter_rmode(vcpu);
3399         }
3400
3401 #ifdef CONFIG_X86_64
3402         if (vcpu->arch.efer & EFER_LME) {
3403                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3404                         enter_lmode(vcpu);
3405                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3406                         exit_lmode(vcpu);
3407         }
3408 #endif
3409
3410         if (enable_ept)
3411                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3412
3413         if (!vcpu->fpu_active)
3414                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3415
3416         vmcs_writel(CR0_READ_SHADOW, cr0);
3417         vmcs_writel(GUEST_CR0, hw_cr0);
3418         vcpu->arch.cr0 = cr0;
3419
3420         /* depends on vcpu->arch.cr0 to be set to a new value */
3421         vmx->emulation_required = emulation_required(vcpu);
3422 }
3423
3424 static u64 construct_eptp(unsigned long root_hpa)
3425 {
3426         u64 eptp;
3427
3428         /* TODO write the value reading from MSR */
3429         eptp = VMX_EPT_DEFAULT_MT |
3430                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3431         if (enable_ept_ad_bits)
3432                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3433         eptp |= (root_hpa & PAGE_MASK);
3434
3435         return eptp;
3436 }
3437
3438 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3439 {
3440         unsigned long guest_cr3;
3441         u64 eptp;
3442
3443         guest_cr3 = cr3;
3444         if (enable_ept) {
3445                 eptp = construct_eptp(cr3);
3446                 vmcs_write64(EPT_POINTER, eptp);
3447                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3448                         guest_cr3 = kvm_read_cr3(vcpu);
3449                 else
3450                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3451                 ept_load_pdptrs(vcpu);
3452         }
3453
3454         vmx_flush_tlb(vcpu);
3455         vmcs_writel(GUEST_CR3, guest_cr3);
3456 }
3457
3458 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3459 {
3460         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3461                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3462
3463         if (cr4 & X86_CR4_VMXE) {
3464                 /*
3465                  * To use VMXON (and later other VMX instructions), a guest
3466                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3467                  * So basically the check on whether to allow nested VMX
3468                  * is here.
3469                  */
3470                 if (!nested_vmx_allowed(vcpu))
3471                         return 1;
3472         }
3473         if (to_vmx(vcpu)->nested.vmxon &&
3474             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3475                 return 1;
3476
3477         vcpu->arch.cr4 = cr4;
3478         if (enable_ept) {
3479                 if (!is_paging(vcpu)) {
3480                         hw_cr4 &= ~X86_CR4_PAE;
3481                         hw_cr4 |= X86_CR4_PSE;
3482                         /*
3483                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3484                          * in hardware. However KVM always uses paging mode to
3485                          * emulate guest non-paging mode with TDP.
3486                          * To emulate this behavior, SMEP/SMAP needs to be
3487                          * manually disabled when guest switches to non-paging
3488                          * mode.
3489                          */
3490                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3491                 } else if (!(cr4 & X86_CR4_PAE)) {
3492                         hw_cr4 &= ~X86_CR4_PAE;
3493                 }
3494         }
3495
3496         vmcs_writel(CR4_READ_SHADOW, cr4);
3497         vmcs_writel(GUEST_CR4, hw_cr4);
3498         return 0;
3499 }
3500
3501 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3502                             struct kvm_segment *var, int seg)
3503 {
3504         struct vcpu_vmx *vmx = to_vmx(vcpu);
3505         u32 ar;
3506
3507         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3508                 *var = vmx->rmode.segs[seg];
3509                 if (seg == VCPU_SREG_TR
3510                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3511                         return;
3512                 var->base = vmx_read_guest_seg_base(vmx, seg);
3513                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3514                 return;
3515         }
3516         var->base = vmx_read_guest_seg_base(vmx, seg);
3517         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3518         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3519         ar = vmx_read_guest_seg_ar(vmx, seg);
3520         var->unusable = (ar >> 16) & 1;
3521         var->type = ar & 15;
3522         var->s = (ar >> 4) & 1;
3523         var->dpl = (ar >> 5) & 3;
3524         /*
3525          * Some userspaces do not preserve unusable property. Since usable
3526          * segment has to be present according to VMX spec we can use present
3527          * property to amend userspace bug by making unusable segment always
3528          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3529          * segment as unusable.
3530          */
3531         var->present = !var->unusable;
3532         var->avl = (ar >> 12) & 1;
3533         var->l = (ar >> 13) & 1;
3534         var->db = (ar >> 14) & 1;
3535         var->g = (ar >> 15) & 1;
3536 }
3537
3538 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3539 {
3540         struct kvm_segment s;
3541
3542         if (to_vmx(vcpu)->rmode.vm86_active) {
3543                 vmx_get_segment(vcpu, &s, seg);
3544                 return s.base;
3545         }
3546         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3547 }
3548
3549 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3550 {
3551         struct vcpu_vmx *vmx = to_vmx(vcpu);
3552
3553         if (unlikely(vmx->rmode.vm86_active))
3554                 return 0;
3555         else {
3556                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3557                 return AR_DPL(ar);
3558         }
3559 }
3560
3561 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3562 {
3563         u32 ar;
3564
3565         if (var->unusable || !var->present)
3566                 ar = 1 << 16;
3567         else {
3568                 ar = var->type & 15;
3569                 ar |= (var->s & 1) << 4;
3570                 ar |= (var->dpl & 3) << 5;
3571                 ar |= (var->present & 1) << 7;
3572                 ar |= (var->avl & 1) << 12;
3573                 ar |= (var->l & 1) << 13;
3574                 ar |= (var->db & 1) << 14;
3575                 ar |= (var->g & 1) << 15;
3576         }
3577
3578         return ar;
3579 }
3580
3581 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3582                             struct kvm_segment *var, int seg)
3583 {
3584         struct vcpu_vmx *vmx = to_vmx(vcpu);
3585         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3586
3587         vmx_segment_cache_clear(vmx);
3588
3589         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3590                 vmx->rmode.segs[seg] = *var;
3591                 if (seg == VCPU_SREG_TR)
3592                         vmcs_write16(sf->selector, var->selector);
3593                 else if (var->s)
3594                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3595                 goto out;
3596         }
3597
3598         vmcs_writel(sf->base, var->base);
3599         vmcs_write32(sf->limit, var->limit);
3600         vmcs_write16(sf->selector, var->selector);
3601
3602         /*
3603          *   Fix the "Accessed" bit in AR field of segment registers for older
3604          * qemu binaries.
3605          *   IA32 arch specifies that at the time of processor reset the
3606          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3607          * is setting it to 0 in the userland code. This causes invalid guest
3608          * state vmexit when "unrestricted guest" mode is turned on.
3609          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3610          * tree. Newer qemu binaries with that qemu fix would not need this
3611          * kvm hack.
3612          */
3613         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3614                 var->type |= 0x1; /* Accessed */
3615
3616         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3617
3618 out:
3619         vmx->emulation_required |= emulation_required(vcpu);
3620 }
3621
3622 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3623 {
3624         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3625
3626         *db = (ar >> 14) & 1;
3627         *l = (ar >> 13) & 1;
3628 }
3629
3630 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3631 {
3632         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3633         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3634 }
3635
3636 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3637 {
3638         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3639         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3640 }
3641
3642 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3643 {
3644         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3645         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3646 }
3647
3648 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3649 {
3650         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3651         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3652 }
3653
3654 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3655 {
3656         struct kvm_segment var;
3657         u32 ar;
3658
3659         vmx_get_segment(vcpu, &var, seg);
3660         var.dpl = 0x3;
3661         if (seg == VCPU_SREG_CS)
3662                 var.type = 0x3;
3663         ar = vmx_segment_access_rights(&var);
3664
3665         if (var.base != (var.selector << 4))
3666                 return false;
3667         if (var.limit != 0xffff)
3668                 return false;
3669         if (ar != 0xf3)
3670                 return false;
3671
3672         return true;
3673 }
3674
3675 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3676 {
3677         struct kvm_segment cs;
3678         unsigned int cs_rpl;
3679
3680         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3681         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3682
3683         if (cs.unusable)
3684                 return false;
3685         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3686                 return false;
3687         if (!cs.s)
3688                 return false;
3689         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3690                 if (cs.dpl > cs_rpl)
3691                         return false;
3692         } else {
3693                 if (cs.dpl != cs_rpl)
3694                         return false;
3695         }
3696         if (!cs.present)
3697                 return false;
3698
3699         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3700         return true;
3701 }
3702
3703 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3704 {
3705         struct kvm_segment ss;
3706         unsigned int ss_rpl;
3707
3708         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3709         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3710
3711         if (ss.unusable)
3712                 return true;
3713         if (ss.type != 3 && ss.type != 7)
3714                 return false;
3715         if (!ss.s)
3716                 return false;
3717         if (ss.dpl != ss_rpl) /* DPL != RPL */
3718                 return false;
3719         if (!ss.present)
3720                 return false;
3721
3722         return true;
3723 }
3724
3725 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3726 {
3727         struct kvm_segment var;
3728         unsigned int rpl;
3729
3730         vmx_get_segment(vcpu, &var, seg);
3731         rpl = var.selector & SELECTOR_RPL_MASK;
3732
3733         if (var.unusable)
3734                 return true;
3735         if (!var.s)
3736                 return false;
3737         if (!var.present)
3738                 return false;
3739         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3740                 if (var.dpl < rpl) /* DPL < RPL */
3741                         return false;
3742         }
3743
3744         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3745          * rights flags
3746          */
3747         return true;
3748 }
3749
3750 static bool tr_valid(struct kvm_vcpu *vcpu)
3751 {
3752         struct kvm_segment tr;
3753
3754         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3755
3756         if (tr.unusable)
3757                 return false;
3758         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3759                 return false;
3760         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3761                 return false;
3762         if (!tr.present)
3763                 return false;
3764
3765         return true;
3766 }
3767
3768 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3769 {
3770         struct kvm_segment ldtr;
3771
3772         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3773
3774         if (ldtr.unusable)
3775                 return true;
3776         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3777                 return false;
3778         if (ldtr.type != 2)
3779                 return false;
3780         if (!ldtr.present)
3781                 return false;
3782
3783         return true;
3784 }
3785
3786 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3787 {
3788         struct kvm_segment cs, ss;
3789
3790         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3791         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3792
3793         return ((cs.selector & SELECTOR_RPL_MASK) ==
3794                  (ss.selector & SELECTOR_RPL_MASK));
3795 }
3796
3797 /*
3798  * Check if guest state is valid. Returns true if valid, false if
3799  * not.
3800  * We assume that registers are always usable
3801  */
3802 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3803 {
3804         if (enable_unrestricted_guest)
3805                 return true;
3806
3807         /* real mode guest state checks */
3808         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3809                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3810                         return false;
3811                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3812                         return false;
3813                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3814                         return false;
3815                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3816                         return false;
3817                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3818                         return false;
3819                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3820                         return false;
3821         } else {
3822         /* protected mode guest state checks */
3823                 if (!cs_ss_rpl_check(vcpu))
3824                         return false;
3825                 if (!code_segment_valid(vcpu))
3826                         return false;
3827                 if (!stack_segment_valid(vcpu))
3828                         return false;
3829                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3830                         return false;
3831                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3832                         return false;
3833                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3834                         return false;
3835                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3836                         return false;
3837                 if (!tr_valid(vcpu))
3838                         return false;
3839                 if (!ldtr_valid(vcpu))
3840                         return false;
3841         }
3842         /* TODO:
3843          * - Add checks on RIP
3844          * - Add checks on RFLAGS
3845          */
3846
3847         return true;
3848 }
3849
3850 static int init_rmode_tss(struct kvm *kvm)
3851 {
3852         gfn_t fn;
3853         u16 data = 0;
3854         int r, idx, ret = 0;
3855
3856         idx = srcu_read_lock(&kvm->srcu);
3857         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3858         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3859         if (r < 0)
3860                 goto out;
3861         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3862         r = kvm_write_guest_page(kvm, fn++, &data,
3863                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3864         if (r < 0)
3865                 goto out;
3866         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3867         if (r < 0)
3868                 goto out;
3869         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3870         if (r < 0)
3871                 goto out;
3872         data = ~0;
3873         r = kvm_write_guest_page(kvm, fn, &data,
3874                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3875                                  sizeof(u8));
3876         if (r < 0)
3877                 goto out;
3878
3879         ret = 1;
3880 out:
3881         srcu_read_unlock(&kvm->srcu, idx);
3882         return ret;
3883 }
3884
3885 static int init_rmode_identity_map(struct kvm *kvm)
3886 {
3887         int i, idx, r, ret;
3888         pfn_t identity_map_pfn;
3889         u32 tmp;
3890
3891         if (!enable_ept)
3892                 return 1;
3893         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3894                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3895                         "haven't been allocated!\n");
3896                 return 0;
3897         }
3898         if (likely(kvm->arch.ept_identity_pagetable_done))
3899                 return 1;
3900         ret = 0;
3901         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3902         idx = srcu_read_lock(&kvm->srcu);
3903         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3904         if (r < 0)
3905                 goto out;
3906         /* Set up identity-mapping pagetable for EPT in real mode */
3907         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3908                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3909                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3910                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3911                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3912                 if (r < 0)
3913                         goto out;
3914         }
3915         kvm->arch.ept_identity_pagetable_done = true;
3916         ret = 1;
3917 out:
3918         srcu_read_unlock(&kvm->srcu, idx);
3919         return ret;
3920 }
3921
3922 static void seg_setup(int seg)
3923 {
3924         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3925         unsigned int ar;
3926
3927         vmcs_write16(sf->selector, 0);
3928         vmcs_writel(sf->base, 0);
3929         vmcs_write32(sf->limit, 0xffff);
3930         ar = 0x93;
3931         if (seg == VCPU_SREG_CS)
3932                 ar |= 0x08; /* code segment */
3933
3934         vmcs_write32(sf->ar_bytes, ar);
3935 }
3936
3937 static int alloc_apic_access_page(struct kvm *kvm)
3938 {
3939         struct page *page;
3940         struct kvm_userspace_memory_region kvm_userspace_mem;
3941         int r = 0;
3942
3943         mutex_lock(&kvm->slots_lock);
3944         if (kvm->arch.apic_access_page)
3945                 goto out;
3946         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3947         kvm_userspace_mem.flags = 0;
3948         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3949         kvm_userspace_mem.memory_size = PAGE_SIZE;
3950         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3951         if (r)
3952                 goto out;
3953
3954         page = gfn_to_page(kvm, 0xfee00);
3955         if (is_error_page(page)) {
3956                 r = -EFAULT;
3957                 goto out;
3958         }
3959
3960         kvm->arch.apic_access_page = page;
3961 out:
3962         mutex_unlock(&kvm->slots_lock);
3963         return r;
3964 }
3965
3966 static int alloc_identity_pagetable(struct kvm *kvm)
3967 {
3968         struct page *page;
3969         struct kvm_userspace_memory_region kvm_userspace_mem;
3970         int r = 0;
3971
3972         mutex_lock(&kvm->slots_lock);
3973         if (kvm->arch.ept_identity_pagetable)
3974                 goto out;
3975         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3976         kvm_userspace_mem.flags = 0;
3977         kvm_userspace_mem.guest_phys_addr =
3978                 kvm->arch.ept_identity_map_addr;
3979         kvm_userspace_mem.memory_size = PAGE_SIZE;
3980         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3981         if (r)
3982                 goto out;
3983
3984         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3985         if (is_error_page(page)) {
3986                 r = -EFAULT;
3987                 goto out;
3988         }
3989
3990         kvm->arch.ept_identity_pagetable = page;
3991 out:
3992         mutex_unlock(&kvm->slots_lock);
3993         return r;
3994 }
3995
3996 static void allocate_vpid(struct vcpu_vmx *vmx)
3997 {
3998         int vpid;
3999
4000         vmx->vpid = 0;
4001         if (!enable_vpid)
4002                 return;
4003         spin_lock(&vmx_vpid_lock);
4004         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4005         if (vpid < VMX_NR_VPIDS) {
4006                 vmx->vpid = vpid;
4007                 __set_bit(vpid, vmx_vpid_bitmap);
4008         }
4009         spin_unlock(&vmx_vpid_lock);
4010 }
4011
4012 static void free_vpid(struct vcpu_vmx *vmx)
4013 {
4014         if (!enable_vpid)
4015                 return;
4016         spin_lock(&vmx_vpid_lock);
4017         if (vmx->vpid != 0)
4018                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4019         spin_unlock(&vmx_vpid_lock);
4020 }
4021
4022 #define MSR_TYPE_R      1
4023 #define MSR_TYPE_W      2
4024 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4025                                                 u32 msr, int type)
4026 {
4027         int f = sizeof(unsigned long);
4028
4029         if (!cpu_has_vmx_msr_bitmap())
4030                 return;
4031
4032         /*
4033          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4034          * have the write-low and read-high bitmap offsets the wrong way round.
4035          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4036          */
4037         if (msr <= 0x1fff) {
4038                 if (type & MSR_TYPE_R)
4039                         /* read-low */
4040                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4041
4042                 if (type & MSR_TYPE_W)
4043                         /* write-low */
4044                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4045
4046         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4047                 msr &= 0x1fff;
4048                 if (type & MSR_TYPE_R)
4049                         /* read-high */
4050                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4051
4052                 if (type & MSR_TYPE_W)
4053                         /* write-high */
4054                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4055
4056         }
4057 }
4058
4059 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4060                                                 u32 msr, int type)
4061 {
4062         int f = sizeof(unsigned long);
4063
4064         if (!cpu_has_vmx_msr_bitmap())
4065                 return;
4066
4067         /*
4068          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4069          * have the write-low and read-high bitmap offsets the wrong way round.
4070          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4071          */
4072         if (msr <= 0x1fff) {
4073                 if (type & MSR_TYPE_R)
4074                         /* read-low */
4075                         __set_bit(msr, msr_bitmap + 0x000 / f);
4076
4077                 if (type & MSR_TYPE_W)
4078                         /* write-low */
4079                         __set_bit(msr, msr_bitmap + 0x800 / f);
4080
4081         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4082                 msr &= 0x1fff;
4083                 if (type & MSR_TYPE_R)
4084                         /* read-high */
4085                         __set_bit(msr, msr_bitmap + 0x400 / f);
4086
4087                 if (type & MSR_TYPE_W)
4088                         /* write-high */
4089                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4090
4091         }
4092 }
4093
4094 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4095 {
4096         if (!longmode_only)
4097                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4098                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4099         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4100                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4101 }
4102
4103 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4104 {
4105         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4106                         msr, MSR_TYPE_R);
4107         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4108                         msr, MSR_TYPE_R);
4109 }
4110
4111 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4112 {
4113         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4114                         msr, MSR_TYPE_R);
4115         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4116                         msr, MSR_TYPE_R);
4117 }
4118
4119 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4120 {
4121         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4122                         msr, MSR_TYPE_W);
4123         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4124                         msr, MSR_TYPE_W);
4125 }
4126
4127 static int vmx_vm_has_apicv(struct kvm *kvm)
4128 {
4129         return enable_apicv && irqchip_in_kernel(kvm);
4130 }
4131
4132 /*
4133  * Send interrupt to vcpu via posted interrupt way.
4134  * 1. If target vcpu is running(non-root mode), send posted interrupt
4135  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4136  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4137  * interrupt from PIR in next vmentry.
4138  */
4139 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4140 {
4141         struct vcpu_vmx *vmx = to_vmx(vcpu);
4142         int r;
4143
4144         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4145                 return;
4146
4147         r = pi_test_and_set_on(&vmx->pi_desc);
4148         kvm_make_request(KVM_REQ_EVENT, vcpu);
4149 #ifdef CONFIG_SMP
4150         if (!r && (vcpu->mode == IN_GUEST_MODE))
4151                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4152                                 POSTED_INTR_VECTOR);
4153         else
4154 #endif
4155                 kvm_vcpu_kick(vcpu);
4156 }
4157
4158 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4159 {
4160         struct vcpu_vmx *vmx = to_vmx(vcpu);
4161
4162         if (!pi_test_and_clear_on(&vmx->pi_desc))
4163                 return;
4164
4165         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4166 }
4167
4168 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4169 {
4170         return;
4171 }
4172
4173 /*
4174  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4175  * will not change in the lifetime of the guest.
4176  * Note that host-state that does change is set elsewhere. E.g., host-state
4177  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4178  */
4179 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4180 {
4181         u32 low32, high32;
4182         unsigned long tmpl;
4183         struct desc_ptr dt;
4184
4185         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4186         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4187         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4188
4189         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4190 #ifdef CONFIG_X86_64
4191         /*
4192          * Load null selectors, so we can avoid reloading them in
4193          * __vmx_load_host_state(), in case userspace uses the null selectors
4194          * too (the expected case).
4195          */
4196         vmcs_write16(HOST_DS_SELECTOR, 0);
4197         vmcs_write16(HOST_ES_SELECTOR, 0);
4198 #else
4199         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4200         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4201 #endif
4202         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4203         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4204
4205         native_store_idt(&dt);
4206         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4207         vmx->host_idt_base = dt.address;
4208
4209         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4210
4211         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4212         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4213         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4214         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4215
4216         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4217                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4218                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4219         }
4220 }
4221
4222 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4223 {
4224         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4225         if (enable_ept)
4226                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4227         if (is_guest_mode(&vmx->vcpu))
4228                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4229                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4230         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4231 }
4232
4233 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4234 {
4235         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4236
4237         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4238                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4239         return pin_based_exec_ctrl;
4240 }
4241
4242 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4243 {
4244         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4245
4246         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4247                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4248
4249         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4250                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4251 #ifdef CONFIG_X86_64
4252                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4253                                 CPU_BASED_CR8_LOAD_EXITING;
4254 #endif
4255         }
4256         if (!enable_ept)
4257                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4258                                 CPU_BASED_CR3_LOAD_EXITING  |
4259                                 CPU_BASED_INVLPG_EXITING;
4260         return exec_control;
4261 }
4262
4263 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4264 {
4265         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4266         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4267                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4268         if (vmx->vpid == 0)
4269                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4270         if (!enable_ept) {
4271                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4272                 enable_unrestricted_guest = 0;
4273                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4274                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4275         }
4276         if (!enable_unrestricted_guest)
4277                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4278         if (!ple_gap)
4279                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4280         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4281                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4282                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4283         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4284         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4285            (handle_vmptrld).
4286            We can NOT enable shadow_vmcs here because we don't have yet
4287            a current VMCS12
4288         */
4289         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4290         return exec_control;
4291 }
4292
4293 static void ept_set_mmio_spte_mask(void)
4294 {
4295         /*
4296          * EPT Misconfigurations can be generated if the value of bits 2:0
4297          * of an EPT paging-structure entry is 110b (write/execute).
4298          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4299          * spte.
4300          */
4301         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4302 }
4303
4304 /*
4305  * Sets up the vmcs for emulated real mode.
4306  */
4307 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4308 {
4309 #ifdef CONFIG_X86_64
4310         unsigned long a;
4311 #endif
4312         int i;
4313
4314         /* I/O */
4315         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4316         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4317
4318         if (enable_shadow_vmcs) {
4319                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4320                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4321         }
4322         if (cpu_has_vmx_msr_bitmap())
4323                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4324
4325         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4326
4327         /* Control */
4328         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4329
4330         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4331
4332         if (cpu_has_secondary_exec_ctrls()) {
4333                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4334                                 vmx_secondary_exec_control(vmx));
4335         }
4336
4337         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4338                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4339                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4340                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4341                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4342
4343                 vmcs_write16(GUEST_INTR_STATUS, 0);
4344
4345                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4346                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4347         }
4348
4349         if (ple_gap) {
4350                 vmcs_write32(PLE_GAP, ple_gap);
4351                 vmcs_write32(PLE_WINDOW, ple_window);
4352         }
4353
4354         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4355         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4356         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4357
4358         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4359         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4360         vmx_set_constant_host_state(vmx);
4361 #ifdef CONFIG_X86_64
4362         rdmsrl(MSR_FS_BASE, a);
4363         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4364         rdmsrl(MSR_GS_BASE, a);
4365         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4366 #else
4367         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4368         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4369 #endif
4370
4371         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4372         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4373         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4374         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4375         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4376
4377         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4378                 u32 msr_low, msr_high;
4379                 u64 host_pat;
4380                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4381                 host_pat = msr_low | ((u64) msr_high << 32);
4382                 /* Write the default value follow host pat */
4383                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4384                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4385                 vmx->vcpu.arch.pat = host_pat;
4386         }
4387
4388         for (i = 0; i < NR_VMX_MSR; ++i) {
4389                 u32 index = vmx_msr_index[i];
4390                 u32 data_low, data_high;
4391                 int j = vmx->nmsrs;
4392
4393                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4394                         continue;
4395                 if (wrmsr_safe(index, data_low, data_high) < 0)
4396                         continue;
4397                 vmx->guest_msrs[j].index = i;
4398                 vmx->guest_msrs[j].data = 0;
4399                 vmx->guest_msrs[j].mask = -1ull;
4400                 ++vmx->nmsrs;
4401         }
4402
4403
4404         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4405
4406         /* 22.2.1, 20.8.1 */
4407         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4408
4409         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4410         set_cr4_guest_host_mask(vmx);
4411
4412         return 0;
4413 }
4414
4415 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4416 {
4417         struct vcpu_vmx *vmx = to_vmx(vcpu);
4418         struct msr_data apic_base_msr;
4419
4420         vmx->rmode.vm86_active = 0;
4421
4422         vmx->soft_vnmi_blocked = 0;
4423
4424         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4425         kvm_set_cr8(&vmx->vcpu, 0);
4426         apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4427         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4428                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4429         apic_base_msr.host_initiated = true;
4430         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4431
4432         vmx_segment_cache_clear(vmx);
4433
4434         seg_setup(VCPU_SREG_CS);
4435         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4436         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4437
4438         seg_setup(VCPU_SREG_DS);
4439         seg_setup(VCPU_SREG_ES);
4440         seg_setup(VCPU_SREG_FS);
4441         seg_setup(VCPU_SREG_GS);
4442         seg_setup(VCPU_SREG_SS);
4443
4444         vmcs_write16(GUEST_TR_SELECTOR, 0);
4445         vmcs_writel(GUEST_TR_BASE, 0);
4446         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4447         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4448
4449         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4450         vmcs_writel(GUEST_LDTR_BASE, 0);
4451         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4452         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4453
4454         vmcs_write32(GUEST_SYSENTER_CS, 0);
4455         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4456         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4457
4458         vmcs_writel(GUEST_RFLAGS, 0x02);
4459         kvm_rip_write(vcpu, 0xfff0);
4460
4461         vmcs_writel(GUEST_GDTR_BASE, 0);
4462         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4463
4464         vmcs_writel(GUEST_IDTR_BASE, 0);
4465         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4466
4467         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4468         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4469         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4470
4471         /* Special registers */
4472         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4473
4474         setup_msrs(vmx);
4475
4476         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4477
4478         if (cpu_has_vmx_tpr_shadow()) {
4479                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4480                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4481                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4482                                      __pa(vmx->vcpu.arch.apic->regs));
4483                 vmcs_write32(TPR_THRESHOLD, 0);
4484         }
4485
4486         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4487                 vmcs_write64(APIC_ACCESS_ADDR,
4488                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4489
4490         if (vmx_vm_has_apicv(vcpu->kvm))
4491                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4492
4493         if (vmx->vpid != 0)
4494                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4495
4496         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4497         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4498         vmx_set_cr4(&vmx->vcpu, 0);
4499         vmx_set_efer(&vmx->vcpu, 0);
4500         vmx_fpu_activate(&vmx->vcpu);
4501         update_exception_bitmap(&vmx->vcpu);
4502
4503         vpid_sync_context(vmx);
4504 }
4505
4506 /*
4507  * In nested virtualization, check if L1 asked to exit on external interrupts.
4508  * For most existing hypervisors, this will always return true.
4509  */
4510 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4511 {
4512         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4513                 PIN_BASED_EXT_INTR_MASK;
4514 }
4515
4516 /*
4517  * In nested virtualization, check if L1 has set
4518  * VM_EXIT_ACK_INTR_ON_EXIT
4519  */
4520 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4521 {
4522         return get_vmcs12(vcpu)->vm_exit_controls &
4523                 VM_EXIT_ACK_INTR_ON_EXIT;
4524 }
4525
4526 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4527 {
4528         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4529                 PIN_BASED_NMI_EXITING;
4530 }
4531
4532 static void enable_irq_window(struct kvm_vcpu *vcpu)
4533 {
4534         u32 cpu_based_vm_exec_control;
4535
4536         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4537         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4538         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4539 }
4540
4541 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4542 {
4543         u32 cpu_based_vm_exec_control;
4544
4545         if (!cpu_has_virtual_nmis() ||
4546             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4547                 enable_irq_window(vcpu);
4548                 return;
4549         }
4550
4551         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4552         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4553         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4554 }
4555
4556 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4557 {
4558         struct vcpu_vmx *vmx = to_vmx(vcpu);
4559         uint32_t intr;
4560         int irq = vcpu->arch.interrupt.nr;
4561
4562         trace_kvm_inj_virq(irq);
4563
4564         ++vcpu->stat.irq_injections;
4565         if (vmx->rmode.vm86_active) {
4566                 int inc_eip = 0;
4567                 if (vcpu->arch.interrupt.soft)
4568                         inc_eip = vcpu->arch.event_exit_inst_len;
4569                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4570                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4571                 return;
4572         }
4573         intr = irq | INTR_INFO_VALID_MASK;
4574         if (vcpu->arch.interrupt.soft) {
4575                 intr |= INTR_TYPE_SOFT_INTR;
4576                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4577                              vmx->vcpu.arch.event_exit_inst_len);
4578         } else
4579                 intr |= INTR_TYPE_EXT_INTR;
4580         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4581 }
4582
4583 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4584 {
4585         struct vcpu_vmx *vmx = to_vmx(vcpu);
4586
4587         if (is_guest_mode(vcpu))
4588                 return;
4589
4590         if (!cpu_has_virtual_nmis()) {
4591                 /*
4592                  * Tracking the NMI-blocked state in software is built upon
4593                  * finding the next open IRQ window. This, in turn, depends on
4594                  * well-behaving guests: They have to keep IRQs disabled at
4595                  * least as long as the NMI handler runs. Otherwise we may
4596                  * cause NMI nesting, maybe breaking the guest. But as this is
4597                  * highly unlikely, we can live with the residual risk.
4598                  */
4599                 vmx->soft_vnmi_blocked = 1;
4600                 vmx->vnmi_blocked_time = 0;
4601         }
4602
4603         ++vcpu->stat.nmi_injections;
4604         vmx->nmi_known_unmasked = false;
4605         if (vmx->rmode.vm86_active) {
4606                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4607                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4608                 return;
4609         }
4610         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4611                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4612 }
4613
4614 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4615 {
4616         if (!cpu_has_virtual_nmis())
4617                 return to_vmx(vcpu)->soft_vnmi_blocked;
4618         if (to_vmx(vcpu)->nmi_known_unmasked)
4619                 return false;
4620         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4621 }
4622
4623 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4624 {
4625         struct vcpu_vmx *vmx = to_vmx(vcpu);
4626
4627         if (!cpu_has_virtual_nmis()) {
4628                 if (vmx->soft_vnmi_blocked != masked) {
4629                         vmx->soft_vnmi_blocked = masked;
4630                         vmx->vnmi_blocked_time = 0;
4631                 }
4632         } else {
4633                 vmx->nmi_known_unmasked = !masked;
4634                 if (masked)
4635                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4636                                       GUEST_INTR_STATE_NMI);
4637                 else
4638                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4639                                         GUEST_INTR_STATE_NMI);
4640         }
4641 }
4642
4643 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4644 {
4645         if (to_vmx(vcpu)->nested.nested_run_pending)
4646                 return 0;
4647
4648         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4649                 return 0;
4650
4651         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4652                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4653                    | GUEST_INTR_STATE_NMI));
4654 }
4655
4656 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4657 {
4658         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4659                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4660                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4661                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4662 }
4663
4664 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4665 {
4666         int ret;
4667         struct kvm_userspace_memory_region tss_mem = {
4668                 .slot = TSS_PRIVATE_MEMSLOT,
4669                 .guest_phys_addr = addr,
4670                 .memory_size = PAGE_SIZE * 3,
4671                 .flags = 0,
4672         };
4673
4674         ret = kvm_set_memory_region(kvm, &tss_mem);
4675         if (ret)
4676                 return ret;
4677         kvm->arch.tss_addr = addr;
4678         if (!init_rmode_tss(kvm))
4679                 return  -ENOMEM;
4680
4681         return 0;
4682 }
4683
4684 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4685 {
4686         switch (vec) {
4687         case BP_VECTOR:
4688                 /*
4689                  * Update instruction length as we may reinject the exception
4690                  * from user space while in guest debugging mode.
4691                  */
4692                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4693                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4694                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4695                         return false;
4696                 /* fall through */
4697         case DB_VECTOR:
4698                 if (vcpu->guest_debug &
4699                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4700                         return false;
4701                 /* fall through */
4702         case DE_VECTOR:
4703         case OF_VECTOR:
4704         case BR_VECTOR:
4705         case UD_VECTOR:
4706         case DF_VECTOR:
4707         case SS_VECTOR:
4708         case GP_VECTOR:
4709         case MF_VECTOR:
4710                 return true;
4711         break;
4712         }
4713         return false;
4714 }
4715
4716 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4717                                   int vec, u32 err_code)
4718 {
4719         /*
4720          * Instruction with address size override prefix opcode 0x67
4721          * Cause the #SS fault with 0 error code in VM86 mode.
4722          */
4723         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4724                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4725                         if (vcpu->arch.halt_request) {
4726                                 vcpu->arch.halt_request = 0;
4727                                 return kvm_emulate_halt(vcpu);
4728                         }
4729                         return 1;
4730                 }
4731                 return 0;
4732         }
4733
4734         /*
4735          * Forward all other exceptions that are valid in real mode.
4736          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4737          *        the required debugging infrastructure rework.
4738          */
4739         kvm_queue_exception(vcpu, vec);
4740         return 1;
4741 }
4742
4743 /*
4744  * Trigger machine check on the host. We assume all the MSRs are already set up
4745  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4746  * We pass a fake environment to the machine check handler because we want
4747  * the guest to be always treated like user space, no matter what context
4748  * it used internally.
4749  */
4750 static void kvm_machine_check(void)
4751 {
4752 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4753         struct pt_regs regs = {
4754                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4755                 .flags = X86_EFLAGS_IF,
4756         };
4757
4758         do_machine_check(&regs, 0);
4759 #endif
4760 }
4761
4762 static int handle_machine_check(struct kvm_vcpu *vcpu)
4763 {
4764         /* already handled by vcpu_run */
4765         return 1;
4766 }
4767
4768 static int handle_exception(struct kvm_vcpu *vcpu)
4769 {
4770         struct vcpu_vmx *vmx = to_vmx(vcpu);
4771         struct kvm_run *kvm_run = vcpu->run;
4772         u32 intr_info, ex_no, error_code;
4773         unsigned long cr2, rip, dr6;
4774         u32 vect_info;
4775         enum emulation_result er;
4776
4777         vect_info = vmx->idt_vectoring_info;
4778         intr_info = vmx->exit_intr_info;
4779
4780         if (is_machine_check(intr_info))
4781                 return handle_machine_check(vcpu);
4782
4783         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4784                 return 1;  /* already handled by vmx_vcpu_run() */
4785
4786         if (is_no_device(intr_info)) {
4787                 vmx_fpu_activate(vcpu);
4788                 return 1;
4789         }
4790
4791         if (is_invalid_opcode(intr_info)) {
4792                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4793                 if (er != EMULATE_DONE)
4794                         kvm_queue_exception(vcpu, UD_VECTOR);
4795                 return 1;
4796         }
4797
4798         error_code = 0;
4799         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4800                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4801
4802         /*
4803          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4804          * MMIO, it is better to report an internal error.
4805          * See the comments in vmx_handle_exit.
4806          */
4807         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4808             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4809                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4810                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4811                 vcpu->run->internal.ndata = 2;
4812                 vcpu->run->internal.data[0] = vect_info;
4813                 vcpu->run->internal.data[1] = intr_info;
4814                 return 0;
4815         }
4816
4817         if (is_page_fault(intr_info)) {
4818                 /* EPT won't cause page fault directly */
4819                 BUG_ON(enable_ept);
4820                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4821                 trace_kvm_page_fault(cr2, error_code);
4822
4823                 if (kvm_event_needs_reinjection(vcpu))
4824                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4825                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4826         }
4827
4828         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4829
4830         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4831                 return handle_rmode_exception(vcpu, ex_no, error_code);
4832
4833         switch (ex_no) {
4834         case DB_VECTOR:
4835                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4836                 if (!(vcpu->guest_debug &
4837                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4838                         vcpu->arch.dr6 &= ~15;
4839                         vcpu->arch.dr6 |= dr6;
4840                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4841                                 skip_emulated_instruction(vcpu);
4842
4843                         kvm_queue_exception(vcpu, DB_VECTOR);
4844                         return 1;
4845                 }
4846                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4847                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4848                 /* fall through */
4849         case BP_VECTOR:
4850                 /*
4851                  * Update instruction length as we may reinject #BP from
4852                  * user space while in guest debugging mode. Reading it for
4853                  * #DB as well causes no harm, it is not used in that case.
4854                  */
4855                 vmx->vcpu.arch.event_exit_inst_len =
4856                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4857                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4858                 rip = kvm_rip_read(vcpu);
4859                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4860                 kvm_run->debug.arch.exception = ex_no;
4861                 break;
4862         default:
4863                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4864                 kvm_run->ex.exception = ex_no;
4865                 kvm_run->ex.error_code = error_code;
4866                 break;
4867         }
4868         return 0;
4869 }
4870
4871 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4872 {
4873         ++vcpu->stat.irq_exits;
4874         return 1;
4875 }
4876
4877 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4878 {
4879         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4880         return 0;
4881 }
4882
4883 static int handle_io(struct kvm_vcpu *vcpu)
4884 {
4885         unsigned long exit_qualification;
4886         int size, in, string;
4887         unsigned port;
4888
4889         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4890         string = (exit_qualification & 16) != 0;
4891         in = (exit_qualification & 8) != 0;
4892
4893         ++vcpu->stat.io_exits;
4894
4895         if (string || in)
4896                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4897
4898         port = exit_qualification >> 16;
4899         size = (exit_qualification & 7) + 1;
4900         skip_emulated_instruction(vcpu);
4901
4902         return kvm_fast_pio_out(vcpu, size, port);
4903 }
4904
4905 static void
4906 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4907 {
4908         /*
4909          * Patch in the VMCALL instruction:
4910          */
4911         hypercall[0] = 0x0f;
4912         hypercall[1] = 0x01;
4913         hypercall[2] = 0xc1;
4914 }
4915
4916 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4917 {
4918         unsigned long always_on = VMXON_CR0_ALWAYSON;
4919
4920         if (nested_vmx_secondary_ctls_high &
4921                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4922             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4923                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4924         return (val & always_on) == always_on;
4925 }
4926
4927 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4928 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4929 {
4930         if (is_guest_mode(vcpu)) {
4931                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4932                 unsigned long orig_val = val;
4933
4934                 /*
4935                  * We get here when L2 changed cr0 in a way that did not change
4936                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4937                  * but did change L0 shadowed bits. So we first calculate the
4938                  * effective cr0 value that L1 would like to write into the
4939                  * hardware. It consists of the L2-owned bits from the new
4940                  * value combined with the L1-owned bits from L1's guest_cr0.
4941                  */
4942                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4943                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4944
4945                 if (!nested_cr0_valid(vmcs12, val))
4946                         return 1;
4947
4948                 if (kvm_set_cr0(vcpu, val))
4949                         return 1;
4950                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4951                 return 0;
4952         } else {
4953                 if (to_vmx(vcpu)->nested.vmxon &&
4954                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4955                         return 1;
4956                 return kvm_set_cr0(vcpu, val);
4957         }
4958 }
4959
4960 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4961 {
4962         if (is_guest_mode(vcpu)) {
4963                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4964                 unsigned long orig_val = val;
4965
4966                 /* analogously to handle_set_cr0 */
4967                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4968                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4969                 if (kvm_set_cr4(vcpu, val))
4970                         return 1;
4971                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4972                 return 0;
4973         } else
4974                 return kvm_set_cr4(vcpu, val);
4975 }
4976
4977 /* called to set cr0 as approriate for clts instruction exit. */
4978 static void handle_clts(struct kvm_vcpu *vcpu)
4979 {
4980         if (is_guest_mode(vcpu)) {
4981                 /*
4982                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4983                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4984                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4985                  */
4986                 vmcs_writel(CR0_READ_SHADOW,
4987                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4988                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4989         } else
4990                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4991 }
4992
4993 static int handle_cr(struct kvm_vcpu *vcpu)
4994 {
4995         unsigned long exit_qualification, val;
4996         int cr;
4997         int reg;
4998         int err;
4999
5000         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5001         cr = exit_qualification & 15;
5002         reg = (exit_qualification >> 8) & 15;
5003         switch ((exit_qualification >> 4) & 3) {
5004         case 0: /* mov to cr */
5005                 val = kvm_register_read(vcpu, reg);
5006                 trace_kvm_cr_write(cr, val);
5007                 switch (cr) {
5008                 case 0:
5009                         err = handle_set_cr0(vcpu, val);
5010                         kvm_complete_insn_gp(vcpu, err);
5011                         return 1;
5012                 case 3:
5013                         err = kvm_set_cr3(vcpu, val);
5014                         kvm_complete_insn_gp(vcpu, err);
5015                         return 1;
5016                 case 4:
5017                         err = handle_set_cr4(vcpu, val);
5018                         kvm_complete_insn_gp(vcpu, err);
5019                         return 1;
5020                 case 8: {
5021                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5022                                 u8 cr8 = kvm_register_read(vcpu, reg);
5023                                 err = kvm_set_cr8(vcpu, cr8);
5024                                 kvm_complete_insn_gp(vcpu, err);
5025                                 if (irqchip_in_kernel(vcpu->kvm))
5026                                         return 1;
5027                                 if (cr8_prev <= cr8)
5028                                         return 1;
5029                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5030                                 return 0;
5031                         }
5032                 }
5033                 break;
5034         case 2: /* clts */
5035                 handle_clts(vcpu);
5036                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5037                 skip_emulated_instruction(vcpu);
5038                 vmx_fpu_activate(vcpu);
5039                 return 1;
5040         case 1: /*mov from cr*/
5041                 switch (cr) {
5042                 case 3:
5043                         val = kvm_read_cr3(vcpu);
5044                         kvm_register_write(vcpu, reg, val);
5045                         trace_kvm_cr_read(cr, val);
5046                         skip_emulated_instruction(vcpu);
5047                         return 1;
5048                 case 8:
5049                         val = kvm_get_cr8(vcpu);
5050                         kvm_register_write(vcpu, reg, val);
5051                         trace_kvm_cr_read(cr, val);
5052                         skip_emulated_instruction(vcpu);
5053                         return 1;
5054                 }
5055                 break;
5056         case 3: /* lmsw */
5057                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5058                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5059                 kvm_lmsw(vcpu, val);
5060
5061                 skip_emulated_instruction(vcpu);
5062                 return 1;
5063         default:
5064                 break;
5065         }
5066         vcpu->run->exit_reason = 0;
5067         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5068                (int)(exit_qualification >> 4) & 3, cr);
5069         return 0;
5070 }
5071
5072 static int handle_dr(struct kvm_vcpu *vcpu)
5073 {
5074         unsigned long exit_qualification;
5075         int dr, reg;
5076
5077         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5078         if (!kvm_require_cpl(vcpu, 0))
5079                 return 1;
5080         dr = vmcs_readl(GUEST_DR7);
5081         if (dr & DR7_GD) {
5082                 /*
5083                  * As the vm-exit takes precedence over the debug trap, we
5084                  * need to emulate the latter, either for the host or the
5085                  * guest debugging itself.
5086                  */
5087                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5088                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5089                         vcpu->run->debug.arch.dr7 = dr;
5090                         vcpu->run->debug.arch.pc =
5091                                 vmcs_readl(GUEST_CS_BASE) +
5092                                 vmcs_readl(GUEST_RIP);
5093                         vcpu->run->debug.arch.exception = DB_VECTOR;
5094                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5095                         return 0;
5096                 } else {
5097                         vcpu->arch.dr7 &= ~DR7_GD;
5098                         vcpu->arch.dr6 |= DR6_BD;
5099                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5100                         kvm_queue_exception(vcpu, DB_VECTOR);
5101                         return 1;
5102                 }
5103         }
5104
5105         if (vcpu->guest_debug == 0) {
5106                 u32 cpu_based_vm_exec_control;
5107
5108                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5109                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5110                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5111
5112                 /*
5113                  * No more DR vmexits; force a reload of the debug registers
5114                  * and reenter on this instruction.  The next vmexit will
5115                  * retrieve the full state of the debug registers.
5116                  */
5117                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5118                 return 1;
5119         }
5120
5121         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5122         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5123         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5124         if (exit_qualification & TYPE_MOV_FROM_DR) {
5125                 unsigned long val;
5126
5127                 if (kvm_get_dr(vcpu, dr, &val))
5128                         return 1;
5129                 kvm_register_write(vcpu, reg, val);
5130         } else
5131                 if (kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg)))
5132                         return 1;
5133
5134         skip_emulated_instruction(vcpu);
5135         return 1;
5136 }
5137
5138 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5139 {
5140         return vcpu->arch.dr6;
5141 }
5142
5143 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5144 {
5145 }
5146
5147 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5148 {
5149         u32 cpu_based_vm_exec_control;
5150
5151         get_debugreg(vcpu->arch.db[0], 0);
5152         get_debugreg(vcpu->arch.db[1], 1);
5153         get_debugreg(vcpu->arch.db[2], 2);
5154         get_debugreg(vcpu->arch.db[3], 3);
5155         get_debugreg(vcpu->arch.dr6, 6);
5156         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5157
5158         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5159
5160         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5161         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5162         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5163 }
5164
5165 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5166 {
5167         vmcs_writel(GUEST_DR7, val);
5168 }
5169
5170 static int handle_cpuid(struct kvm_vcpu *vcpu)
5171 {
5172         kvm_emulate_cpuid(vcpu);
5173         return 1;
5174 }
5175
5176 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5177 {
5178         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5179         u64 data;
5180
5181         if (vmx_get_msr(vcpu, ecx, &data)) {
5182                 trace_kvm_msr_read_ex(ecx);
5183                 kvm_inject_gp(vcpu, 0);
5184                 return 1;
5185         }
5186
5187         trace_kvm_msr_read(ecx, data);
5188
5189         /* FIXME: handling of bits 32:63 of rax, rdx */
5190         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5191         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5192         skip_emulated_instruction(vcpu);
5193         return 1;
5194 }
5195
5196 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5197 {
5198         struct msr_data msr;
5199         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5200         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5201                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5202
5203         msr.data = data;
5204         msr.index = ecx;
5205         msr.host_initiated = false;
5206         if (vmx_set_msr(vcpu, &msr) != 0) {
5207                 trace_kvm_msr_write_ex(ecx, data);
5208                 kvm_inject_gp(vcpu, 0);
5209                 return 1;
5210         }
5211
5212         trace_kvm_msr_write(ecx, data);
5213         skip_emulated_instruction(vcpu);
5214         return 1;
5215 }
5216
5217 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5218 {
5219         kvm_make_request(KVM_REQ_EVENT, vcpu);
5220         return 1;
5221 }
5222
5223 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5224 {
5225         u32 cpu_based_vm_exec_control;
5226
5227         /* clear pending irq */
5228         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5229         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5230         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5231
5232         kvm_make_request(KVM_REQ_EVENT, vcpu);
5233
5234         ++vcpu->stat.irq_window_exits;
5235
5236         /*
5237          * If the user space waits to inject interrupts, exit as soon as
5238          * possible
5239          */
5240         if (!irqchip_in_kernel(vcpu->kvm) &&
5241             vcpu->run->request_interrupt_window &&
5242             !kvm_cpu_has_interrupt(vcpu)) {
5243                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5244                 return 0;
5245         }
5246         return 1;
5247 }
5248
5249 static int handle_halt(struct kvm_vcpu *vcpu)
5250 {
5251         skip_emulated_instruction(vcpu);
5252         return kvm_emulate_halt(vcpu);
5253 }
5254
5255 static int handle_vmcall(struct kvm_vcpu *vcpu)
5256 {
5257         skip_emulated_instruction(vcpu);
5258         kvm_emulate_hypercall(vcpu);
5259         return 1;
5260 }
5261
5262 static int handle_invd(struct kvm_vcpu *vcpu)
5263 {
5264         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5265 }
5266
5267 static int handle_invlpg(struct kvm_vcpu *vcpu)
5268 {
5269         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5270
5271         kvm_mmu_invlpg(vcpu, exit_qualification);
5272         skip_emulated_instruction(vcpu);
5273         return 1;
5274 }
5275
5276 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5277 {
5278         int err;
5279
5280         err = kvm_rdpmc(vcpu);
5281         kvm_complete_insn_gp(vcpu, err);
5282
5283         return 1;
5284 }
5285
5286 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5287 {
5288         skip_emulated_instruction(vcpu);
5289         kvm_emulate_wbinvd(vcpu);
5290         return 1;
5291 }
5292
5293 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5294 {
5295         u64 new_bv = kvm_read_edx_eax(vcpu);
5296         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5297
5298         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5299                 skip_emulated_instruction(vcpu);
5300         return 1;
5301 }
5302
5303 static int handle_apic_access(struct kvm_vcpu *vcpu)
5304 {
5305         if (likely(fasteoi)) {
5306                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5307                 int access_type, offset;
5308
5309                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5310                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5311                 /*
5312                  * Sane guest uses MOV to write EOI, with written value
5313                  * not cared. So make a short-circuit here by avoiding
5314                  * heavy instruction emulation.
5315                  */
5316                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5317                     (offset == APIC_EOI)) {
5318                         kvm_lapic_set_eoi(vcpu);
5319                         skip_emulated_instruction(vcpu);
5320                         return 1;
5321                 }
5322         }
5323         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5324 }
5325
5326 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5327 {
5328         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5329         int vector = exit_qualification & 0xff;
5330
5331         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5332         kvm_apic_set_eoi_accelerated(vcpu, vector);
5333         return 1;
5334 }
5335
5336 static int handle_apic_write(struct kvm_vcpu *vcpu)
5337 {
5338         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5339         u32 offset = exit_qualification & 0xfff;
5340
5341         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5342         kvm_apic_write_nodecode(vcpu, offset);
5343         return 1;
5344 }
5345
5346 static int handle_task_switch(struct kvm_vcpu *vcpu)
5347 {
5348         struct vcpu_vmx *vmx = to_vmx(vcpu);
5349         unsigned long exit_qualification;
5350         bool has_error_code = false;
5351         u32 error_code = 0;
5352         u16 tss_selector;
5353         int reason, type, idt_v, idt_index;
5354
5355         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5356         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5357         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5358
5359         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5360
5361         reason = (u32)exit_qualification >> 30;
5362         if (reason == TASK_SWITCH_GATE && idt_v) {
5363                 switch (type) {
5364                 case INTR_TYPE_NMI_INTR:
5365                         vcpu->arch.nmi_injected = false;
5366                         vmx_set_nmi_mask(vcpu, true);
5367                         break;
5368                 case INTR_TYPE_EXT_INTR:
5369                 case INTR_TYPE_SOFT_INTR:
5370                         kvm_clear_interrupt_queue(vcpu);
5371                         break;
5372                 case INTR_TYPE_HARD_EXCEPTION:
5373                         if (vmx->idt_vectoring_info &
5374                             VECTORING_INFO_DELIVER_CODE_MASK) {
5375                                 has_error_code = true;
5376                                 error_code =
5377                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5378                         }
5379                         /* fall through */
5380                 case INTR_TYPE_SOFT_EXCEPTION:
5381                         kvm_clear_exception_queue(vcpu);
5382                         break;
5383                 default:
5384                         break;
5385                 }
5386         }
5387         tss_selector = exit_qualification;
5388
5389         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5390                        type != INTR_TYPE_EXT_INTR &&
5391                        type != INTR_TYPE_NMI_INTR))
5392                 skip_emulated_instruction(vcpu);
5393
5394         if (kvm_task_switch(vcpu, tss_selector,
5395                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5396                             has_error_code, error_code) == EMULATE_FAIL) {
5397                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5398                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5399                 vcpu->run->internal.ndata = 0;
5400                 return 0;
5401         }
5402
5403         /* clear all local breakpoint enable flags */
5404         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5405
5406         /*
5407          * TODO: What about debug traps on tss switch?
5408          *       Are we supposed to inject them and update dr6?
5409          */
5410
5411         return 1;
5412 }
5413
5414 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5415 {
5416         unsigned long exit_qualification;
5417         gpa_t gpa;
5418         u32 error_code;
5419         int gla_validity;
5420
5421         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5422
5423         gla_validity = (exit_qualification >> 7) & 0x3;
5424         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5425                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5426                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5427                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5428                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5429                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5430                         (long unsigned int)exit_qualification);
5431                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5432                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5433                 return 0;
5434         }
5435
5436         /*
5437          * EPT violation happened while executing iret from NMI,
5438          * "blocked by NMI" bit has to be set before next VM entry.
5439          * There are errata that may cause this bit to not be set:
5440          * AAK134, BY25.
5441          */
5442         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5443                         cpu_has_virtual_nmis() &&
5444                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5445                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5446
5447         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5448         trace_kvm_page_fault(gpa, exit_qualification);
5449
5450         /* It is a write fault? */
5451         error_code = exit_qualification & (1U << 1);
5452         /* It is a fetch fault? */
5453         error_code |= (exit_qualification & (1U << 2)) << 2;
5454         /* ept page table is present? */
5455         error_code |= (exit_qualification >> 3) & 0x1;
5456
5457         vcpu->arch.exit_qualification = exit_qualification;
5458
5459         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5460 }
5461
5462 static u64 ept_rsvd_mask(u64 spte, int level)
5463 {
5464         int i;
5465         u64 mask = 0;
5466
5467         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5468                 mask |= (1ULL << i);
5469
5470         if (level > 2)
5471                 /* bits 7:3 reserved */
5472                 mask |= 0xf8;
5473         else if (level == 2) {
5474                 if (spte & (1ULL << 7))
5475                         /* 2MB ref, bits 20:12 reserved */
5476                         mask |= 0x1ff000;
5477                 else
5478                         /* bits 6:3 reserved */
5479                         mask |= 0x78;
5480         }
5481
5482         return mask;
5483 }
5484
5485 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5486                                        int level)
5487 {
5488         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5489
5490         /* 010b (write-only) */
5491         WARN_ON((spte & 0x7) == 0x2);
5492
5493         /* 110b (write/execute) */
5494         WARN_ON((spte & 0x7) == 0x6);
5495
5496         /* 100b (execute-only) and value not supported by logical processor */
5497         if (!cpu_has_vmx_ept_execute_only())
5498                 WARN_ON((spte & 0x7) == 0x4);
5499
5500         /* not 000b */
5501         if ((spte & 0x7)) {
5502                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5503
5504                 if (rsvd_bits != 0) {
5505                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5506                                          __func__, rsvd_bits);
5507                         WARN_ON(1);
5508                 }
5509
5510                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5511                         u64 ept_mem_type = (spte & 0x38) >> 3;
5512
5513                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5514                             ept_mem_type == 7) {
5515                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5516                                                 __func__, ept_mem_type);
5517                                 WARN_ON(1);
5518                         }
5519                 }
5520         }
5521 }
5522
5523 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5524 {
5525         u64 sptes[4];
5526         int nr_sptes, i, ret;
5527         gpa_t gpa;
5528
5529         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5530         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5531                 skip_emulated_instruction(vcpu);
5532                 return 1;
5533         }
5534
5535         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5536         if (likely(ret == RET_MMIO_PF_EMULATE))
5537                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5538                                               EMULATE_DONE;
5539
5540         if (unlikely(ret == RET_MMIO_PF_INVALID))
5541                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5542
5543         if (unlikely(ret == RET_MMIO_PF_RETRY))
5544                 return 1;
5545
5546         /* It is the real ept misconfig */
5547         printk(KERN_ERR "EPT: Misconfiguration.\n");
5548         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5549
5550         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5551
5552         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5553                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5554
5555         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5556         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5557
5558         return 0;
5559 }
5560
5561 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5562 {
5563         u32 cpu_based_vm_exec_control;
5564
5565         /* clear pending NMI */
5566         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5567         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5568         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5569         ++vcpu->stat.nmi_window_exits;
5570         kvm_make_request(KVM_REQ_EVENT, vcpu);
5571
5572         return 1;
5573 }
5574
5575 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5576 {
5577         struct vcpu_vmx *vmx = to_vmx(vcpu);
5578         enum emulation_result err = EMULATE_DONE;
5579         int ret = 1;
5580         u32 cpu_exec_ctrl;
5581         bool intr_window_requested;
5582         unsigned count = 130;
5583
5584         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5585         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5586
5587         while (!guest_state_valid(vcpu) && count-- != 0) {
5588                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5589                         return handle_interrupt_window(&vmx->vcpu);
5590
5591                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5592                         return 1;
5593
5594                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5595
5596                 if (err == EMULATE_USER_EXIT) {
5597                         ++vcpu->stat.mmio_exits;
5598                         ret = 0;
5599                         goto out;
5600                 }
5601
5602                 if (err != EMULATE_DONE) {
5603                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5604                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5605                         vcpu->run->internal.ndata = 0;
5606                         return 0;
5607                 }
5608
5609                 if (vcpu->arch.halt_request) {
5610                         vcpu->arch.halt_request = 0;
5611                         ret = kvm_emulate_halt(vcpu);
5612                         goto out;
5613                 }
5614
5615                 if (signal_pending(current))
5616                         goto out;
5617                 if (need_resched())
5618                         schedule();
5619         }
5620
5621         vmx->emulation_required = emulation_required(vcpu);
5622 out:
5623         return ret;
5624 }
5625
5626 /*
5627  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5628  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5629  */
5630 static int handle_pause(struct kvm_vcpu *vcpu)
5631 {
5632         skip_emulated_instruction(vcpu);
5633         kvm_vcpu_on_spin(vcpu);
5634
5635         return 1;
5636 }
5637
5638 static int handle_nop(struct kvm_vcpu *vcpu)
5639 {
5640         skip_emulated_instruction(vcpu);
5641         return 1;
5642 }
5643
5644 static int handle_mwait(struct kvm_vcpu *vcpu)
5645 {
5646         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5647         return handle_nop(vcpu);
5648 }
5649
5650 static int handle_monitor(struct kvm_vcpu *vcpu)
5651 {
5652         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5653         return handle_nop(vcpu);
5654 }
5655
5656 /*
5657  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5658  * We could reuse a single VMCS for all the L2 guests, but we also want the
5659  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5660  * allows keeping them loaded on the processor, and in the future will allow
5661  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5662  * every entry if they never change.
5663  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5664  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5665  *
5666  * The following functions allocate and free a vmcs02 in this pool.
5667  */
5668
5669 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5670 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5671 {
5672         struct vmcs02_list *item;
5673         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5674                 if (item->vmptr == vmx->nested.current_vmptr) {
5675                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5676                         return &item->vmcs02;
5677                 }
5678
5679         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5680                 /* Recycle the least recently used VMCS. */
5681                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5682                         struct vmcs02_list, list);
5683                 item->vmptr = vmx->nested.current_vmptr;
5684                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5685                 return &item->vmcs02;
5686         }
5687
5688         /* Create a new VMCS */
5689         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5690         if (!item)
5691                 return NULL;
5692         item->vmcs02.vmcs = alloc_vmcs();
5693         if (!item->vmcs02.vmcs) {
5694                 kfree(item);
5695                 return NULL;
5696         }
5697         loaded_vmcs_init(&item->vmcs02);
5698         item->vmptr = vmx->nested.current_vmptr;
5699         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5700         vmx->nested.vmcs02_num++;
5701         return &item->vmcs02;
5702 }
5703
5704 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5705 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5706 {
5707         struct vmcs02_list *item;
5708         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5709                 if (item->vmptr == vmptr) {
5710                         free_loaded_vmcs(&item->vmcs02);
5711                         list_del(&item->list);
5712                         kfree(item);
5713                         vmx->nested.vmcs02_num--;
5714                         return;
5715                 }
5716 }
5717
5718 /*
5719  * Free all VMCSs saved for this vcpu, except the one pointed by
5720  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5721  * currently used, if running L2), and vmcs01 when running L2.
5722  */
5723 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5724 {
5725         struct vmcs02_list *item, *n;
5726         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5727                 if (vmx->loaded_vmcs != &item->vmcs02)
5728                         free_loaded_vmcs(&item->vmcs02);
5729                 list_del(&item->list);
5730                 kfree(item);
5731         }
5732         vmx->nested.vmcs02_num = 0;
5733
5734         if (vmx->loaded_vmcs != &vmx->vmcs01)
5735                 free_loaded_vmcs(&vmx->vmcs01);
5736 }
5737
5738 /*
5739  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5740  * set the success or error code of an emulated VMX instruction, as specified
5741  * by Vol 2B, VMX Instruction Reference, "Conventions".
5742  */
5743 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5744 {
5745         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5746                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5747                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5748 }
5749
5750 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5751 {
5752         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5753                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5754                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5755                         | X86_EFLAGS_CF);
5756 }
5757
5758 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5759                                         u32 vm_instruction_error)
5760 {
5761         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5762                 /*
5763                  * failValid writes the error number to the current VMCS, which
5764                  * can't be done there isn't a current VMCS.
5765                  */
5766                 nested_vmx_failInvalid(vcpu);
5767                 return;
5768         }
5769         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5770                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5771                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5772                         | X86_EFLAGS_ZF);
5773         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5774         /*
5775          * We don't need to force a shadow sync because
5776          * VM_INSTRUCTION_ERROR is not shadowed
5777          */
5778 }
5779
5780 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5781 {
5782         struct vcpu_vmx *vmx =
5783                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5784
5785         vmx->nested.preemption_timer_expired = true;
5786         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5787         kvm_vcpu_kick(&vmx->vcpu);
5788
5789         return HRTIMER_NORESTART;
5790 }
5791
5792 /*
5793  * Decode the memory-address operand of a vmx instruction, as recorded on an
5794  * exit caused by such an instruction (run by a guest hypervisor).
5795  * On success, returns 0. When the operand is invalid, returns 1 and throws
5796  * #UD or #GP.
5797  */
5798 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5799                                  unsigned long exit_qualification,
5800                                  u32 vmx_instruction_info, gva_t *ret)
5801 {
5802         /*
5803          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5804          * Execution", on an exit, vmx_instruction_info holds most of the
5805          * addressing components of the operand. Only the displacement part
5806          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5807          * For how an actual address is calculated from all these components,
5808          * refer to Vol. 1, "Operand Addressing".
5809          */
5810         int  scaling = vmx_instruction_info & 3;
5811         int  addr_size = (vmx_instruction_info >> 7) & 7;
5812         bool is_reg = vmx_instruction_info & (1u << 10);
5813         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5814         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5815         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5816         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5817         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5818
5819         if (is_reg) {
5820                 kvm_queue_exception(vcpu, UD_VECTOR);
5821                 return 1;
5822         }
5823
5824         /* Addr = segment_base + offset */
5825         /* offset = base + [index * scale] + displacement */
5826         *ret = vmx_get_segment_base(vcpu, seg_reg);
5827         if (base_is_valid)
5828                 *ret += kvm_register_read(vcpu, base_reg);
5829         if (index_is_valid)
5830                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5831         *ret += exit_qualification; /* holds the displacement */
5832
5833         if (addr_size == 1) /* 32 bit */
5834                 *ret &= 0xffffffff;
5835
5836         /*
5837          * TODO: throw #GP (and return 1) in various cases that the VM*
5838          * instructions require it - e.g., offset beyond segment limit,
5839          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5840          * address, and so on. Currently these are not checked.
5841          */
5842         return 0;
5843 }
5844
5845 /*
5846  * This function performs the various checks including
5847  * - if it's 4KB aligned
5848  * - No bits beyond the physical address width are set
5849  * - Returns 0 on success or else 1
5850  * (Intel SDM Section 30.3)
5851  */
5852 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
5853                                   gpa_t *vmpointer)
5854 {
5855         gva_t gva;
5856         gpa_t vmptr;
5857         struct x86_exception e;
5858         struct page *page;
5859         struct vcpu_vmx *vmx = to_vmx(vcpu);
5860         int maxphyaddr = cpuid_maxphyaddr(vcpu);
5861
5862         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5863                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5864                 return 1;
5865
5866         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5867                                 sizeof(vmptr), &e)) {
5868                 kvm_inject_page_fault(vcpu, &e);
5869                 return 1;
5870         }
5871
5872         switch (exit_reason) {
5873         case EXIT_REASON_VMON:
5874                 /*
5875                  * SDM 3: 24.11.5
5876                  * The first 4 bytes of VMXON region contain the supported
5877                  * VMCS revision identifier
5878                  *
5879                  * Note - IA32_VMX_BASIC[48] will never be 1
5880                  * for the nested case;
5881                  * which replaces physical address width with 32
5882                  *
5883                  */
5884                 if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) {
5885                         nested_vmx_failInvalid(vcpu);
5886                         skip_emulated_instruction(vcpu);
5887                         return 1;
5888                 }
5889
5890                 page = nested_get_page(vcpu, vmptr);
5891                 if (page == NULL ||
5892                     *(u32 *)kmap(page) != VMCS12_REVISION) {
5893                         nested_vmx_failInvalid(vcpu);
5894                         kunmap(page);
5895                         skip_emulated_instruction(vcpu);
5896                         return 1;
5897                 }
5898                 kunmap(page);
5899                 vmx->nested.vmxon_ptr = vmptr;
5900                 break;
5901         case EXIT_REASON_VMCLEAR:
5902                 if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) {
5903                         nested_vmx_failValid(vcpu,
5904                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
5905                         skip_emulated_instruction(vcpu);
5906                         return 1;
5907                 }
5908
5909                 if (vmptr == vmx->nested.vmxon_ptr) {
5910                         nested_vmx_failValid(vcpu,
5911                                              VMXERR_VMCLEAR_VMXON_POINTER);
5912                         skip_emulated_instruction(vcpu);
5913                         return 1;
5914                 }
5915                 break;
5916         case EXIT_REASON_VMPTRLD:
5917                 if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) {
5918                         nested_vmx_failValid(vcpu,
5919                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
5920                         skip_emulated_instruction(vcpu);
5921                         return 1;
5922                 }
5923
5924                 if (vmptr == vmx->nested.vmxon_ptr) {
5925                         nested_vmx_failValid(vcpu,
5926                                              VMXERR_VMCLEAR_VMXON_POINTER);
5927                         skip_emulated_instruction(vcpu);
5928                         return 1;
5929                 }
5930                 break;
5931         default:
5932                 return 1; /* shouldn't happen */
5933         }
5934
5935         if (vmpointer)
5936                 *vmpointer = vmptr;
5937         return 0;
5938 }
5939
5940 /*
5941  * Emulate the VMXON instruction.
5942  * Currently, we just remember that VMX is active, and do not save or even
5943  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5944  * do not currently need to store anything in that guest-allocated memory
5945  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5946  * argument is different from the VMXON pointer (which the spec says they do).
5947  */
5948 static int handle_vmon(struct kvm_vcpu *vcpu)
5949 {
5950         struct kvm_segment cs;
5951         struct vcpu_vmx *vmx = to_vmx(vcpu);
5952         struct vmcs *shadow_vmcs;
5953         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5954                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5955
5956         /* The Intel VMX Instruction Reference lists a bunch of bits that
5957          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5958          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5959          * Otherwise, we should fail with #UD. We test these now:
5960          */
5961         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5962             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5963             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5964                 kvm_queue_exception(vcpu, UD_VECTOR);
5965                 return 1;
5966         }
5967
5968         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5969         if (is_long_mode(vcpu) && !cs.l) {
5970                 kvm_queue_exception(vcpu, UD_VECTOR);
5971                 return 1;
5972         }
5973
5974         if (vmx_get_cpl(vcpu)) {
5975                 kvm_inject_gp(vcpu, 0);
5976                 return 1;
5977         }
5978
5979         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
5980                 return 1;
5981
5982         if (vmx->nested.vmxon) {
5983                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5984                 skip_emulated_instruction(vcpu);
5985                 return 1;
5986         }
5987
5988         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5989                         != VMXON_NEEDED_FEATURES) {
5990                 kvm_inject_gp(vcpu, 0);
5991                 return 1;
5992         }
5993
5994         if (enable_shadow_vmcs) {
5995                 shadow_vmcs = alloc_vmcs();
5996                 if (!shadow_vmcs)
5997                         return -ENOMEM;
5998                 /* mark vmcs as shadow */
5999                 shadow_vmcs->revision_id |= (1u << 31);
6000                 /* init shadow vmcs */
6001                 vmcs_clear(shadow_vmcs);
6002                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6003         }
6004
6005         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6006         vmx->nested.vmcs02_num = 0;
6007
6008         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6009                      HRTIMER_MODE_REL);
6010         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6011
6012         vmx->nested.vmxon = true;
6013
6014         skip_emulated_instruction(vcpu);
6015         nested_vmx_succeed(vcpu);
6016         return 1;
6017 }
6018
6019 /*
6020  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6021  * for running VMX instructions (except VMXON, whose prerequisites are
6022  * slightly different). It also specifies what exception to inject otherwise.
6023  */
6024 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6025 {
6026         struct kvm_segment cs;
6027         struct vcpu_vmx *vmx = to_vmx(vcpu);
6028
6029         if (!vmx->nested.vmxon) {
6030                 kvm_queue_exception(vcpu, UD_VECTOR);
6031                 return 0;
6032         }
6033
6034         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6035         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6036             (is_long_mode(vcpu) && !cs.l)) {
6037                 kvm_queue_exception(vcpu, UD_VECTOR);
6038                 return 0;
6039         }
6040
6041         if (vmx_get_cpl(vcpu)) {
6042                 kvm_inject_gp(vcpu, 0);
6043                 return 0;
6044         }
6045
6046         return 1;
6047 }
6048
6049 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6050 {
6051         u32 exec_control;
6052         if (enable_shadow_vmcs) {
6053                 if (vmx->nested.current_vmcs12 != NULL) {
6054                         /* copy to memory all shadowed fields in case
6055                            they were modified */
6056                         copy_shadow_to_vmcs12(vmx);
6057                         vmx->nested.sync_shadow_vmcs = false;
6058                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6059                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6060                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6061                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6062                 }
6063         }
6064         kunmap(vmx->nested.current_vmcs12_page);
6065         nested_release_page(vmx->nested.current_vmcs12_page);
6066 }
6067
6068 /*
6069  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6070  * just stops using VMX.
6071  */
6072 static void free_nested(struct vcpu_vmx *vmx)
6073 {
6074         if (!vmx->nested.vmxon)
6075                 return;
6076         vmx->nested.vmxon = false;
6077         if (vmx->nested.current_vmptr != -1ull) {
6078                 nested_release_vmcs12(vmx);
6079                 vmx->nested.current_vmptr = -1ull;
6080                 vmx->nested.current_vmcs12 = NULL;
6081         }
6082         if (enable_shadow_vmcs)
6083                 free_vmcs(vmx->nested.current_shadow_vmcs);
6084         /* Unpin physical memory we referred to in current vmcs02 */
6085         if (vmx->nested.apic_access_page) {
6086                 nested_release_page(vmx->nested.apic_access_page);
6087                 vmx->nested.apic_access_page = 0;
6088         }
6089
6090         nested_free_all_saved_vmcss(vmx);
6091 }
6092
6093 /* Emulate the VMXOFF instruction */
6094 static int handle_vmoff(struct kvm_vcpu *vcpu)
6095 {
6096         if (!nested_vmx_check_permission(vcpu))
6097                 return 1;
6098         free_nested(to_vmx(vcpu));
6099         skip_emulated_instruction(vcpu);
6100         nested_vmx_succeed(vcpu);
6101         return 1;
6102 }
6103
6104 /* Emulate the VMCLEAR instruction */
6105 static int handle_vmclear(struct kvm_vcpu *vcpu)
6106 {
6107         struct vcpu_vmx *vmx = to_vmx(vcpu);
6108         gpa_t vmptr;
6109         struct vmcs12 *vmcs12;
6110         struct page *page;
6111
6112         if (!nested_vmx_check_permission(vcpu))
6113                 return 1;
6114
6115         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6116                 return 1;
6117
6118         if (vmptr == vmx->nested.current_vmptr) {
6119                 nested_release_vmcs12(vmx);
6120                 vmx->nested.current_vmptr = -1ull;
6121                 vmx->nested.current_vmcs12 = NULL;
6122         }
6123
6124         page = nested_get_page(vcpu, vmptr);
6125         if (page == NULL) {
6126                 /*
6127                  * For accurate processor emulation, VMCLEAR beyond available
6128                  * physical memory should do nothing at all. However, it is
6129                  * possible that a nested vmx bug, not a guest hypervisor bug,
6130                  * resulted in this case, so let's shut down before doing any
6131                  * more damage:
6132                  */
6133                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6134                 return 1;
6135         }
6136         vmcs12 = kmap(page);
6137         vmcs12->launch_state = 0;
6138         kunmap(page);
6139         nested_release_page(page);
6140
6141         nested_free_vmcs02(vmx, vmptr);
6142
6143         skip_emulated_instruction(vcpu);
6144         nested_vmx_succeed(vcpu);
6145         return 1;
6146 }
6147
6148 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6149
6150 /* Emulate the VMLAUNCH instruction */
6151 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6152 {
6153         return nested_vmx_run(vcpu, true);
6154 }
6155
6156 /* Emulate the VMRESUME instruction */
6157 static int handle_vmresume(struct kvm_vcpu *vcpu)
6158 {
6159
6160         return nested_vmx_run(vcpu, false);
6161 }
6162
6163 enum vmcs_field_type {
6164         VMCS_FIELD_TYPE_U16 = 0,
6165         VMCS_FIELD_TYPE_U64 = 1,
6166         VMCS_FIELD_TYPE_U32 = 2,
6167         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6168 };
6169
6170 static inline int vmcs_field_type(unsigned long field)
6171 {
6172         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6173                 return VMCS_FIELD_TYPE_U32;
6174         return (field >> 13) & 0x3 ;
6175 }
6176
6177 static inline int vmcs_field_readonly(unsigned long field)
6178 {
6179         return (((field >> 10) & 0x3) == 1);
6180 }
6181
6182 /*
6183  * Read a vmcs12 field. Since these can have varying lengths and we return
6184  * one type, we chose the biggest type (u64) and zero-extend the return value
6185  * to that size. Note that the caller, handle_vmread, might need to use only
6186  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6187  * 64-bit fields are to be returned).
6188  */
6189 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6190                                         unsigned long field, u64 *ret)
6191 {
6192         short offset = vmcs_field_to_offset(field);
6193         char *p;
6194
6195         if (offset < 0)
6196                 return 0;
6197
6198         p = ((char *)(get_vmcs12(vcpu))) + offset;
6199
6200         switch (vmcs_field_type(field)) {
6201         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6202                 *ret = *((natural_width *)p);
6203                 return 1;
6204         case VMCS_FIELD_TYPE_U16:
6205                 *ret = *((u16 *)p);
6206                 return 1;
6207         case VMCS_FIELD_TYPE_U32:
6208                 *ret = *((u32 *)p);
6209                 return 1;
6210         case VMCS_FIELD_TYPE_U64:
6211                 *ret = *((u64 *)p);
6212                 return 1;
6213         default:
6214                 return 0; /* can never happen. */
6215         }
6216 }
6217
6218
6219 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6220                                     unsigned long field, u64 field_value){
6221         short offset = vmcs_field_to_offset(field);
6222         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6223         if (offset < 0)
6224                 return false;
6225
6226         switch (vmcs_field_type(field)) {
6227         case VMCS_FIELD_TYPE_U16:
6228                 *(u16 *)p = field_value;
6229                 return true;
6230         case VMCS_FIELD_TYPE_U32:
6231                 *(u32 *)p = field_value;
6232                 return true;
6233         case VMCS_FIELD_TYPE_U64:
6234                 *(u64 *)p = field_value;
6235                 return true;
6236         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6237                 *(natural_width *)p = field_value;
6238                 return true;
6239         default:
6240                 return false; /* can never happen. */
6241         }
6242
6243 }
6244
6245 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6246 {
6247         int i;
6248         unsigned long field;
6249         u64 field_value;
6250         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6251         const unsigned long *fields = shadow_read_write_fields;
6252         const int num_fields = max_shadow_read_write_fields;
6253
6254         vmcs_load(shadow_vmcs);
6255
6256         for (i = 0; i < num_fields; i++) {
6257                 field = fields[i];
6258                 switch (vmcs_field_type(field)) {
6259                 case VMCS_FIELD_TYPE_U16:
6260                         field_value = vmcs_read16(field);
6261                         break;
6262                 case VMCS_FIELD_TYPE_U32:
6263                         field_value = vmcs_read32(field);
6264                         break;
6265                 case VMCS_FIELD_TYPE_U64:
6266                         field_value = vmcs_read64(field);
6267                         break;
6268                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6269                         field_value = vmcs_readl(field);
6270                         break;
6271                 }
6272                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6273         }
6274
6275         vmcs_clear(shadow_vmcs);
6276         vmcs_load(vmx->loaded_vmcs->vmcs);
6277 }
6278
6279 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6280 {
6281         const unsigned long *fields[] = {
6282                 shadow_read_write_fields,
6283                 shadow_read_only_fields
6284         };
6285         const int max_fields[] = {
6286                 max_shadow_read_write_fields,
6287                 max_shadow_read_only_fields
6288         };
6289         int i, q;
6290         unsigned long field;
6291         u64 field_value = 0;
6292         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6293
6294         vmcs_load(shadow_vmcs);
6295
6296         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6297                 for (i = 0; i < max_fields[q]; i++) {
6298                         field = fields[q][i];
6299                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6300
6301                         switch (vmcs_field_type(field)) {
6302                         case VMCS_FIELD_TYPE_U16:
6303                                 vmcs_write16(field, (u16)field_value);
6304                                 break;
6305                         case VMCS_FIELD_TYPE_U32:
6306                                 vmcs_write32(field, (u32)field_value);
6307                                 break;
6308                         case VMCS_FIELD_TYPE_U64:
6309                                 vmcs_write64(field, (u64)field_value);
6310                                 break;
6311                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6312                                 vmcs_writel(field, (long)field_value);
6313                                 break;
6314                         }
6315                 }
6316         }
6317
6318         vmcs_clear(shadow_vmcs);
6319         vmcs_load(vmx->loaded_vmcs->vmcs);
6320 }
6321
6322 /*
6323  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6324  * used before) all generate the same failure when it is missing.
6325  */
6326 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6327 {
6328         struct vcpu_vmx *vmx = to_vmx(vcpu);
6329         if (vmx->nested.current_vmptr == -1ull) {
6330                 nested_vmx_failInvalid(vcpu);
6331                 skip_emulated_instruction(vcpu);
6332                 return 0;
6333         }
6334         return 1;
6335 }
6336
6337 static int handle_vmread(struct kvm_vcpu *vcpu)
6338 {
6339         unsigned long field;
6340         u64 field_value;
6341         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6342         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6343         gva_t gva = 0;
6344
6345         if (!nested_vmx_check_permission(vcpu) ||
6346             !nested_vmx_check_vmcs12(vcpu))
6347                 return 1;
6348
6349         /* Decode instruction info and find the field to read */
6350         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6351         /* Read the field, zero-extended to a u64 field_value */
6352         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6353                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6354                 skip_emulated_instruction(vcpu);
6355                 return 1;
6356         }
6357         /*
6358          * Now copy part of this value to register or memory, as requested.
6359          * Note that the number of bits actually copied is 32 or 64 depending
6360          * on the guest's mode (32 or 64 bit), not on the given field's length.
6361          */
6362         if (vmx_instruction_info & (1u << 10)) {
6363                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6364                         field_value);
6365         } else {
6366                 if (get_vmx_mem_address(vcpu, exit_qualification,
6367                                 vmx_instruction_info, &gva))
6368                         return 1;
6369                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6370                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6371                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6372         }
6373
6374         nested_vmx_succeed(vcpu);
6375         skip_emulated_instruction(vcpu);
6376         return 1;
6377 }
6378
6379
6380 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6381 {
6382         unsigned long field;
6383         gva_t gva;
6384         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6385         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6386         /* The value to write might be 32 or 64 bits, depending on L1's long
6387          * mode, and eventually we need to write that into a field of several
6388          * possible lengths. The code below first zero-extends the value to 64
6389          * bit (field_value), and then copies only the approriate number of
6390          * bits into the vmcs12 field.
6391          */
6392         u64 field_value = 0;
6393         struct x86_exception e;
6394
6395         if (!nested_vmx_check_permission(vcpu) ||
6396             !nested_vmx_check_vmcs12(vcpu))
6397                 return 1;
6398
6399         if (vmx_instruction_info & (1u << 10))
6400                 field_value = kvm_register_read(vcpu,
6401                         (((vmx_instruction_info) >> 3) & 0xf));
6402         else {
6403                 if (get_vmx_mem_address(vcpu, exit_qualification,
6404                                 vmx_instruction_info, &gva))
6405                         return 1;
6406                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6407                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6408                         kvm_inject_page_fault(vcpu, &e);
6409                         return 1;
6410                 }
6411         }
6412
6413
6414         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6415         if (vmcs_field_readonly(field)) {
6416                 nested_vmx_failValid(vcpu,
6417                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6418                 skip_emulated_instruction(vcpu);
6419                 return 1;
6420         }
6421
6422         if (!vmcs12_write_any(vcpu, field, field_value)) {
6423                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6424                 skip_emulated_instruction(vcpu);
6425                 return 1;
6426         }
6427
6428         nested_vmx_succeed(vcpu);
6429         skip_emulated_instruction(vcpu);
6430         return 1;
6431 }
6432
6433 /* Emulate the VMPTRLD instruction */
6434 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6435 {
6436         struct vcpu_vmx *vmx = to_vmx(vcpu);
6437         gpa_t vmptr;
6438         u32 exec_control;
6439
6440         if (!nested_vmx_check_permission(vcpu))
6441                 return 1;
6442
6443         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
6444                 return 1;
6445
6446         if (vmx->nested.current_vmptr != vmptr) {
6447                 struct vmcs12 *new_vmcs12;
6448                 struct page *page;
6449                 page = nested_get_page(vcpu, vmptr);
6450                 if (page == NULL) {
6451                         nested_vmx_failInvalid(vcpu);
6452                         skip_emulated_instruction(vcpu);
6453                         return 1;
6454                 }
6455                 new_vmcs12 = kmap(page);
6456                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6457                         kunmap(page);
6458                         nested_release_page_clean(page);
6459                         nested_vmx_failValid(vcpu,
6460                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6461                         skip_emulated_instruction(vcpu);
6462                         return 1;
6463                 }
6464                 if (vmx->nested.current_vmptr != -1ull)
6465                         nested_release_vmcs12(vmx);
6466
6467                 vmx->nested.current_vmptr = vmptr;
6468                 vmx->nested.current_vmcs12 = new_vmcs12;
6469                 vmx->nested.current_vmcs12_page = page;
6470                 if (enable_shadow_vmcs) {
6471                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6472                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6473                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6474                         vmcs_write64(VMCS_LINK_POINTER,
6475                                      __pa(vmx->nested.current_shadow_vmcs));
6476                         vmx->nested.sync_shadow_vmcs = true;
6477                 }
6478         }
6479
6480         nested_vmx_succeed(vcpu);
6481         skip_emulated_instruction(vcpu);
6482         return 1;
6483 }
6484
6485 /* Emulate the VMPTRST instruction */
6486 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6487 {
6488         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6489         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6490         gva_t vmcs_gva;
6491         struct x86_exception e;
6492
6493         if (!nested_vmx_check_permission(vcpu))
6494                 return 1;
6495
6496         if (get_vmx_mem_address(vcpu, exit_qualification,
6497                         vmx_instruction_info, &vmcs_gva))
6498                 return 1;
6499         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6500         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6501                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6502                                  sizeof(u64), &e)) {
6503                 kvm_inject_page_fault(vcpu, &e);
6504                 return 1;
6505         }
6506         nested_vmx_succeed(vcpu);
6507         skip_emulated_instruction(vcpu);
6508         return 1;
6509 }
6510
6511 /* Emulate the INVEPT instruction */
6512 static int handle_invept(struct kvm_vcpu *vcpu)
6513 {
6514         u32 vmx_instruction_info, types;
6515         unsigned long type;
6516         gva_t gva;
6517         struct x86_exception e;
6518         struct {
6519                 u64 eptp, gpa;
6520         } operand;
6521
6522         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6523             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6524                 kvm_queue_exception(vcpu, UD_VECTOR);
6525                 return 1;
6526         }
6527
6528         if (!nested_vmx_check_permission(vcpu))
6529                 return 1;
6530
6531         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6532                 kvm_queue_exception(vcpu, UD_VECTOR);
6533                 return 1;
6534         }
6535
6536         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6537         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6538
6539         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6540
6541         if (!(types & (1UL << type))) {
6542                 nested_vmx_failValid(vcpu,
6543                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6544                 return 1;
6545         }
6546
6547         /* According to the Intel VMX instruction reference, the memory
6548          * operand is read even if it isn't needed (e.g., for type==global)
6549          */
6550         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6551                         vmx_instruction_info, &gva))
6552                 return 1;
6553         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6554                                 sizeof(operand), &e)) {
6555                 kvm_inject_page_fault(vcpu, &e);
6556                 return 1;
6557         }
6558
6559         switch (type) {
6560         case VMX_EPT_EXTENT_GLOBAL:
6561                 kvm_mmu_sync_roots(vcpu);
6562                 kvm_mmu_flush_tlb(vcpu);
6563                 nested_vmx_succeed(vcpu);
6564                 break;
6565         default:
6566                 /* Trap single context invalidation invept calls */
6567                 BUG_ON(1);
6568                 break;
6569         }
6570
6571         skip_emulated_instruction(vcpu);
6572         return 1;
6573 }
6574
6575 /*
6576  * The exit handlers return 1 if the exit was handled fully and guest execution
6577  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6578  * to be done to userspace and return 0.
6579  */
6580 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6581         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6582         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6583         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6584         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6585         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6586         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6587         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6588         [EXIT_REASON_CPUID]                   = handle_cpuid,
6589         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6590         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6591         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6592         [EXIT_REASON_HLT]                     = handle_halt,
6593         [EXIT_REASON_INVD]                    = handle_invd,
6594         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6595         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6596         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6597         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6598         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6599         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6600         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6601         [EXIT_REASON_VMREAD]                  = handle_vmread,
6602         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6603         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6604         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6605         [EXIT_REASON_VMON]                    = handle_vmon,
6606         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6607         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6608         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6609         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6610         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6611         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6612         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6613         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6614         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6615         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6616         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6617         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
6618         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
6619         [EXIT_REASON_INVEPT]                  = handle_invept,
6620 };
6621
6622 static const int kvm_vmx_max_exit_handlers =
6623         ARRAY_SIZE(kvm_vmx_exit_handlers);
6624
6625 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6626                                        struct vmcs12 *vmcs12)
6627 {
6628         unsigned long exit_qualification;
6629         gpa_t bitmap, last_bitmap;
6630         unsigned int port;
6631         int size;
6632         u8 b;
6633
6634         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6635                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6636
6637         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6638
6639         port = exit_qualification >> 16;
6640         size = (exit_qualification & 7) + 1;
6641
6642         last_bitmap = (gpa_t)-1;
6643         b = -1;
6644
6645         while (size > 0) {
6646                 if (port < 0x8000)
6647                         bitmap = vmcs12->io_bitmap_a;
6648                 else if (port < 0x10000)
6649                         bitmap = vmcs12->io_bitmap_b;
6650                 else
6651                         return 1;
6652                 bitmap += (port & 0x7fff) / 8;
6653
6654                 if (last_bitmap != bitmap)
6655                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6656                                 return 1;
6657                 if (b & (1 << (port & 7)))
6658                         return 1;
6659
6660                 port++;
6661                 size--;
6662                 last_bitmap = bitmap;
6663         }
6664
6665         return 0;
6666 }
6667
6668 /*
6669  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6670  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6671  * disinterest in the current event (read or write a specific MSR) by using an
6672  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6673  */
6674 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6675         struct vmcs12 *vmcs12, u32 exit_reason)
6676 {
6677         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6678         gpa_t bitmap;
6679
6680         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6681                 return 1;
6682
6683         /*
6684          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6685          * for the four combinations of read/write and low/high MSR numbers.
6686          * First we need to figure out which of the four to use:
6687          */
6688         bitmap = vmcs12->msr_bitmap;
6689         if (exit_reason == EXIT_REASON_MSR_WRITE)
6690                 bitmap += 2048;
6691         if (msr_index >= 0xc0000000) {
6692                 msr_index -= 0xc0000000;
6693                 bitmap += 1024;
6694         }
6695
6696         /* Then read the msr_index'th bit from this bitmap: */
6697         if (msr_index < 1024*8) {
6698                 unsigned char b;
6699                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6700                         return 1;
6701                 return 1 & (b >> (msr_index & 7));
6702         } else
6703                 return 1; /* let L1 handle the wrong parameter */
6704 }
6705
6706 /*
6707  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6708  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6709  * intercept (via guest_host_mask etc.) the current event.
6710  */
6711 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6712         struct vmcs12 *vmcs12)
6713 {
6714         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6715         int cr = exit_qualification & 15;
6716         int reg = (exit_qualification >> 8) & 15;
6717         unsigned long val = kvm_register_read(vcpu, reg);
6718
6719         switch ((exit_qualification >> 4) & 3) {
6720         case 0: /* mov to cr */
6721                 switch (cr) {
6722                 case 0:
6723                         if (vmcs12->cr0_guest_host_mask &
6724                             (val ^ vmcs12->cr0_read_shadow))
6725                                 return 1;
6726                         break;
6727                 case 3:
6728                         if ((vmcs12->cr3_target_count >= 1 &&
6729                                         vmcs12->cr3_target_value0 == val) ||
6730                                 (vmcs12->cr3_target_count >= 2 &&
6731                                         vmcs12->cr3_target_value1 == val) ||
6732                                 (vmcs12->cr3_target_count >= 3 &&
6733                                         vmcs12->cr3_target_value2 == val) ||
6734                                 (vmcs12->cr3_target_count >= 4 &&
6735                                         vmcs12->cr3_target_value3 == val))
6736                                 return 0;
6737                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6738                                 return 1;
6739                         break;
6740                 case 4:
6741                         if (vmcs12->cr4_guest_host_mask &
6742                             (vmcs12->cr4_read_shadow ^ val))
6743                                 return 1;
6744                         break;
6745                 case 8:
6746                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6747                                 return 1;
6748                         break;
6749                 }
6750                 break;
6751         case 2: /* clts */
6752                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6753                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6754                         return 1;
6755                 break;
6756         case 1: /* mov from cr */
6757                 switch (cr) {
6758                 case 3:
6759                         if (vmcs12->cpu_based_vm_exec_control &
6760                             CPU_BASED_CR3_STORE_EXITING)
6761                                 return 1;
6762                         break;
6763                 case 8:
6764                         if (vmcs12->cpu_based_vm_exec_control &
6765                             CPU_BASED_CR8_STORE_EXITING)
6766                                 return 1;
6767                         break;
6768                 }
6769                 break;
6770         case 3: /* lmsw */
6771                 /*
6772                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6773                  * cr0. Other attempted changes are ignored, with no exit.
6774                  */
6775                 if (vmcs12->cr0_guest_host_mask & 0xe &
6776                     (val ^ vmcs12->cr0_read_shadow))
6777                         return 1;
6778                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6779                     !(vmcs12->cr0_read_shadow & 0x1) &&
6780                     (val & 0x1))
6781                         return 1;
6782                 break;
6783         }
6784         return 0;
6785 }
6786
6787 /*
6788  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6789  * should handle it ourselves in L0 (and then continue L2). Only call this
6790  * when in is_guest_mode (L2).
6791  */
6792 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6793 {
6794         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6795         struct vcpu_vmx *vmx = to_vmx(vcpu);
6796         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6797         u32 exit_reason = vmx->exit_reason;
6798
6799         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6800                                 vmcs_readl(EXIT_QUALIFICATION),
6801                                 vmx->idt_vectoring_info,
6802                                 intr_info,
6803                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6804                                 KVM_ISA_VMX);
6805
6806         if (vmx->nested.nested_run_pending)
6807                 return 0;
6808
6809         if (unlikely(vmx->fail)) {
6810                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6811                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6812                 return 1;
6813         }
6814
6815         switch (exit_reason) {
6816         case EXIT_REASON_EXCEPTION_NMI:
6817                 if (!is_exception(intr_info))
6818                         return 0;
6819                 else if (is_page_fault(intr_info))
6820                         return enable_ept;
6821                 else if (is_no_device(intr_info) &&
6822                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6823                         return 0;
6824                 return vmcs12->exception_bitmap &
6825                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6826         case EXIT_REASON_EXTERNAL_INTERRUPT:
6827                 return 0;
6828         case EXIT_REASON_TRIPLE_FAULT:
6829                 return 1;
6830         case EXIT_REASON_PENDING_INTERRUPT:
6831                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6832         case EXIT_REASON_NMI_WINDOW:
6833                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6834         case EXIT_REASON_TASK_SWITCH:
6835                 return 1;
6836         case EXIT_REASON_CPUID:
6837                 return 1;
6838         case EXIT_REASON_HLT:
6839                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6840         case EXIT_REASON_INVD:
6841                 return 1;
6842         case EXIT_REASON_INVLPG:
6843                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6844         case EXIT_REASON_RDPMC:
6845                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6846         case EXIT_REASON_RDTSC:
6847                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6848         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6849         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6850         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6851         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6852         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6853         case EXIT_REASON_INVEPT:
6854                 /*
6855                  * VMX instructions trap unconditionally. This allows L1 to
6856                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6857                  */
6858                 return 1;
6859         case EXIT_REASON_CR_ACCESS:
6860                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6861         case EXIT_REASON_DR_ACCESS:
6862                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6863         case EXIT_REASON_IO_INSTRUCTION:
6864                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6865         case EXIT_REASON_MSR_READ:
6866         case EXIT_REASON_MSR_WRITE:
6867                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6868         case EXIT_REASON_INVALID_STATE:
6869                 return 1;
6870         case EXIT_REASON_MWAIT_INSTRUCTION:
6871                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6872         case EXIT_REASON_MONITOR_INSTRUCTION:
6873                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6874         case EXIT_REASON_PAUSE_INSTRUCTION:
6875                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6876                         nested_cpu_has2(vmcs12,
6877                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6878         case EXIT_REASON_MCE_DURING_VMENTRY:
6879                 return 0;
6880         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6881                 return 1;
6882         case EXIT_REASON_APIC_ACCESS:
6883                 return nested_cpu_has2(vmcs12,
6884                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6885         case EXIT_REASON_EPT_VIOLATION:
6886                 /*
6887                  * L0 always deals with the EPT violation. If nested EPT is
6888                  * used, and the nested mmu code discovers that the address is
6889                  * missing in the guest EPT table (EPT12), the EPT violation
6890                  * will be injected with nested_ept_inject_page_fault()
6891                  */
6892                 return 0;
6893         case EXIT_REASON_EPT_MISCONFIG:
6894                 /*
6895                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6896                  * table (shadow on EPT) or a merged EPT table that L0 built
6897                  * (EPT on EPT). So any problems with the structure of the
6898                  * table is L0's fault.
6899                  */
6900                 return 0;
6901         case EXIT_REASON_WBINVD:
6902                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6903         case EXIT_REASON_XSETBV:
6904                 return 1;
6905         default:
6906                 return 1;
6907         }
6908 }
6909
6910 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6911 {
6912         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6913         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6914 }
6915
6916 /*
6917  * The guest has exited.  See if we can fix it or if we need userspace
6918  * assistance.
6919  */
6920 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6921 {
6922         struct vcpu_vmx *vmx = to_vmx(vcpu);
6923         u32 exit_reason = vmx->exit_reason;
6924         u32 vectoring_info = vmx->idt_vectoring_info;
6925
6926         /* If guest state is invalid, start emulating */
6927         if (vmx->emulation_required)
6928                 return handle_invalid_guest_state(vcpu);
6929
6930         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6931                 nested_vmx_vmexit(vcpu, exit_reason,
6932                                   vmcs_read32(VM_EXIT_INTR_INFO),
6933                                   vmcs_readl(EXIT_QUALIFICATION));
6934                 return 1;
6935         }
6936
6937         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6938                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6939                 vcpu->run->fail_entry.hardware_entry_failure_reason
6940                         = exit_reason;
6941                 return 0;
6942         }
6943
6944         if (unlikely(vmx->fail)) {
6945                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6946                 vcpu->run->fail_entry.hardware_entry_failure_reason
6947                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6948                 return 0;
6949         }
6950
6951         /*
6952          * Note:
6953          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6954          * delivery event since it indicates guest is accessing MMIO.
6955          * The vm-exit can be triggered again after return to guest that
6956          * will cause infinite loop.
6957          */
6958         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6959                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6960                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6961                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6962                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6963                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6964                 vcpu->run->internal.ndata = 2;
6965                 vcpu->run->internal.data[0] = vectoring_info;
6966                 vcpu->run->internal.data[1] = exit_reason;
6967                 return 0;
6968         }
6969
6970         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6971             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6972                                         get_vmcs12(vcpu))))) {
6973                 if (vmx_interrupt_allowed(vcpu)) {
6974                         vmx->soft_vnmi_blocked = 0;
6975                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6976                            vcpu->arch.nmi_pending) {
6977                         /*
6978                          * This CPU don't support us in finding the end of an
6979                          * NMI-blocked window if the guest runs with IRQs
6980                          * disabled. So we pull the trigger after 1 s of
6981                          * futile waiting, but inform the user about this.
6982                          */
6983                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6984                                "state on VCPU %d after 1 s timeout\n",
6985                                __func__, vcpu->vcpu_id);
6986                         vmx->soft_vnmi_blocked = 0;
6987                 }
6988         }
6989
6990         if (exit_reason < kvm_vmx_max_exit_handlers
6991             && kvm_vmx_exit_handlers[exit_reason])
6992                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6993         else {
6994                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6995                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6996         }
6997         return 0;
6998 }
6999
7000 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7001 {
7002         if (irr == -1 || tpr < irr) {
7003                 vmcs_write32(TPR_THRESHOLD, 0);
7004                 return;
7005         }
7006
7007         vmcs_write32(TPR_THRESHOLD, irr);
7008 }
7009
7010 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7011 {
7012         u32 sec_exec_control;
7013
7014         /*
7015          * There is not point to enable virtualize x2apic without enable
7016          * apicv
7017          */
7018         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7019                                 !vmx_vm_has_apicv(vcpu->kvm))
7020                 return;
7021
7022         if (!vm_need_tpr_shadow(vcpu->kvm))
7023                 return;
7024
7025         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7026
7027         if (set) {
7028                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7029                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7030         } else {
7031                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7032                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7033         }
7034         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7035
7036         vmx_set_msr_bitmap(vcpu);
7037 }
7038
7039 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7040 {
7041         u16 status;
7042         u8 old;
7043
7044         if (!vmx_vm_has_apicv(kvm))
7045                 return;
7046
7047         if (isr == -1)
7048                 isr = 0;
7049
7050         status = vmcs_read16(GUEST_INTR_STATUS);
7051         old = status >> 8;
7052         if (isr != old) {
7053                 status &= 0xff;
7054                 status |= isr << 8;
7055                 vmcs_write16(GUEST_INTR_STATUS, status);
7056         }
7057 }
7058
7059 static void vmx_set_rvi(int vector)
7060 {
7061         u16 status;
7062         u8 old;
7063
7064         status = vmcs_read16(GUEST_INTR_STATUS);
7065         old = (u8)status & 0xff;
7066         if ((u8)vector != old) {
7067                 status &= ~0xff;
7068                 status |= (u8)vector;
7069                 vmcs_write16(GUEST_INTR_STATUS, status);
7070         }
7071 }
7072
7073 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7074 {
7075         if (max_irr == -1)
7076                 return;
7077
7078         vmx_set_rvi(max_irr);
7079 }
7080
7081 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7082 {
7083         if (!vmx_vm_has_apicv(vcpu->kvm))
7084                 return;
7085
7086         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7087         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7088         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7089         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7090 }
7091
7092 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7093 {
7094         u32 exit_intr_info;
7095
7096         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7097               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7098                 return;
7099
7100         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7101         exit_intr_info = vmx->exit_intr_info;
7102
7103         /* Handle machine checks before interrupts are enabled */
7104         if (is_machine_check(exit_intr_info))
7105                 kvm_machine_check();
7106
7107         /* We need to handle NMIs before interrupts are enabled */
7108         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7109             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7110                 kvm_before_handle_nmi(&vmx->vcpu);
7111                 asm("int $2");
7112                 kvm_after_handle_nmi(&vmx->vcpu);
7113         }
7114 }
7115
7116 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7117 {
7118         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7119
7120         /*
7121          * If external interrupt exists, IF bit is set in rflags/eflags on the
7122          * interrupt stack frame, and interrupt will be enabled on a return
7123          * from interrupt handler.
7124          */
7125         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7126                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7127                 unsigned int vector;
7128                 unsigned long entry;
7129                 gate_desc *desc;
7130                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7131 #ifdef CONFIG_X86_64
7132                 unsigned long tmp;
7133 #endif
7134
7135                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7136                 desc = (gate_desc *)vmx->host_idt_base + vector;
7137                 entry = gate_offset(*desc);
7138                 asm volatile(
7139 #ifdef CONFIG_X86_64
7140                         "mov %%" _ASM_SP ", %[sp]\n\t"
7141                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7142                         "push $%c[ss]\n\t"
7143                         "push %[sp]\n\t"
7144 #endif
7145                         "pushf\n\t"
7146                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7147                         __ASM_SIZE(push) " $%c[cs]\n\t"
7148                         "call *%[entry]\n\t"
7149                         :
7150 #ifdef CONFIG_X86_64
7151                         [sp]"=&r"(tmp)
7152 #endif
7153                         :
7154                         [entry]"r"(entry),
7155                         [ss]"i"(__KERNEL_DS),
7156                         [cs]"i"(__KERNEL_CS)
7157                         );
7158         } else
7159                 local_irq_enable();
7160 }
7161
7162 static bool vmx_mpx_supported(void)
7163 {
7164         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7165                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7166 }
7167
7168 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7169 {
7170         u32 exit_intr_info;
7171         bool unblock_nmi;
7172         u8 vector;
7173         bool idtv_info_valid;
7174
7175         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7176
7177         if (cpu_has_virtual_nmis()) {
7178                 if (vmx->nmi_known_unmasked)
7179                         return;
7180                 /*
7181                  * Can't use vmx->exit_intr_info since we're not sure what
7182                  * the exit reason is.
7183                  */
7184                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7185                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7186                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7187                 /*
7188                  * SDM 3: 27.7.1.2 (September 2008)
7189                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7190                  * a guest IRET fault.
7191                  * SDM 3: 23.2.2 (September 2008)
7192                  * Bit 12 is undefined in any of the following cases:
7193                  *  If the VM exit sets the valid bit in the IDT-vectoring
7194                  *   information field.
7195                  *  If the VM exit is due to a double fault.
7196                  */
7197                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7198                     vector != DF_VECTOR && !idtv_info_valid)
7199                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7200                                       GUEST_INTR_STATE_NMI);
7201                 else
7202                         vmx->nmi_known_unmasked =
7203                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7204                                   & GUEST_INTR_STATE_NMI);
7205         } else if (unlikely(vmx->soft_vnmi_blocked))
7206                 vmx->vnmi_blocked_time +=
7207                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7208 }
7209
7210 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7211                                       u32 idt_vectoring_info,
7212                                       int instr_len_field,
7213                                       int error_code_field)
7214 {
7215         u8 vector;
7216         int type;
7217         bool idtv_info_valid;
7218
7219         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7220
7221         vcpu->arch.nmi_injected = false;
7222         kvm_clear_exception_queue(vcpu);
7223         kvm_clear_interrupt_queue(vcpu);
7224
7225         if (!idtv_info_valid)
7226                 return;
7227
7228         kvm_make_request(KVM_REQ_EVENT, vcpu);
7229
7230         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7231         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7232
7233         switch (type) {
7234         case INTR_TYPE_NMI_INTR:
7235                 vcpu->arch.nmi_injected = true;
7236                 /*
7237                  * SDM 3: 27.7.1.2 (September 2008)
7238                  * Clear bit "block by NMI" before VM entry if a NMI
7239                  * delivery faulted.
7240                  */
7241                 vmx_set_nmi_mask(vcpu, false);
7242                 break;
7243         case INTR_TYPE_SOFT_EXCEPTION:
7244                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7245                 /* fall through */
7246         case INTR_TYPE_HARD_EXCEPTION:
7247                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7248                         u32 err = vmcs_read32(error_code_field);
7249                         kvm_requeue_exception_e(vcpu, vector, err);
7250                 } else
7251                         kvm_requeue_exception(vcpu, vector);
7252                 break;
7253         case INTR_TYPE_SOFT_INTR:
7254                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7255                 /* fall through */
7256         case INTR_TYPE_EXT_INTR:
7257                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7258                 break;
7259         default:
7260                 break;
7261         }
7262 }
7263
7264 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7265 {
7266         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7267                                   VM_EXIT_INSTRUCTION_LEN,
7268                                   IDT_VECTORING_ERROR_CODE);
7269 }
7270
7271 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7272 {
7273         __vmx_complete_interrupts(vcpu,
7274                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7275                                   VM_ENTRY_INSTRUCTION_LEN,
7276                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7277
7278         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7279 }
7280
7281 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7282 {
7283         int i, nr_msrs;
7284         struct perf_guest_switch_msr *msrs;
7285
7286         msrs = perf_guest_get_msrs(&nr_msrs);
7287
7288         if (!msrs)
7289                 return;
7290
7291         for (i = 0; i < nr_msrs; i++)
7292                 if (msrs[i].host == msrs[i].guest)
7293                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7294                 else
7295                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7296                                         msrs[i].host);
7297 }
7298
7299 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7300 {
7301         struct vcpu_vmx *vmx = to_vmx(vcpu);
7302         unsigned long debugctlmsr;
7303
7304         /* Record the guest's net vcpu time for enforced NMI injections. */
7305         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7306                 vmx->entry_time = ktime_get();
7307
7308         /* Don't enter VMX if guest state is invalid, let the exit handler
7309            start emulation until we arrive back to a valid state */
7310         if (vmx->emulation_required)
7311                 return;
7312
7313         if (vmx->nested.sync_shadow_vmcs) {
7314                 copy_vmcs12_to_shadow(vmx);
7315                 vmx->nested.sync_shadow_vmcs = false;
7316         }
7317
7318         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7319                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7320         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7321                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7322
7323         /* When single-stepping over STI and MOV SS, we must clear the
7324          * corresponding interruptibility bits in the guest state. Otherwise
7325          * vmentry fails as it then expects bit 14 (BS) in pending debug
7326          * exceptions being set, but that's not correct for the guest debugging
7327          * case. */
7328         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7329                 vmx_set_interrupt_shadow(vcpu, 0);
7330
7331         atomic_switch_perf_msrs(vmx);
7332         debugctlmsr = get_debugctlmsr();
7333
7334         vmx->__launched = vmx->loaded_vmcs->launched;
7335         asm(
7336                 /* Store host registers */
7337                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7338                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7339                 "push %%" _ASM_CX " \n\t"
7340                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7341                 "je 1f \n\t"
7342                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7343                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7344                 "1: \n\t"
7345                 /* Reload cr2 if changed */
7346                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7347                 "mov %%cr2, %%" _ASM_DX " \n\t"
7348                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7349                 "je 2f \n\t"
7350                 "mov %%" _ASM_AX", %%cr2 \n\t"
7351                 "2: \n\t"
7352                 /* Check if vmlaunch of vmresume is needed */
7353                 "cmpl $0, %c[launched](%0) \n\t"
7354                 /* Load guest registers.  Don't clobber flags. */
7355                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7356                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7357                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7358                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7359                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7360                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7361 #ifdef CONFIG_X86_64
7362                 "mov %c[r8](%0),  %%r8  \n\t"
7363                 "mov %c[r9](%0),  %%r9  \n\t"
7364                 "mov %c[r10](%0), %%r10 \n\t"
7365                 "mov %c[r11](%0), %%r11 \n\t"
7366                 "mov %c[r12](%0), %%r12 \n\t"
7367                 "mov %c[r13](%0), %%r13 \n\t"
7368                 "mov %c[r14](%0), %%r14 \n\t"
7369                 "mov %c[r15](%0), %%r15 \n\t"
7370 #endif
7371                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7372
7373                 /* Enter guest mode */
7374                 "jne 1f \n\t"
7375                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7376                 "jmp 2f \n\t"
7377                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7378                 "2: "
7379                 /* Save guest registers, load host registers, keep flags */
7380                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7381                 "pop %0 \n\t"
7382                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7383                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7384                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7385                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7386                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7387                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7388                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7389 #ifdef CONFIG_X86_64
7390                 "mov %%r8,  %c[r8](%0) \n\t"
7391                 "mov %%r9,  %c[r9](%0) \n\t"
7392                 "mov %%r10, %c[r10](%0) \n\t"
7393                 "mov %%r11, %c[r11](%0) \n\t"
7394                 "mov %%r12, %c[r12](%0) \n\t"
7395                 "mov %%r13, %c[r13](%0) \n\t"
7396                 "mov %%r14, %c[r14](%0) \n\t"
7397                 "mov %%r15, %c[r15](%0) \n\t"
7398 #endif
7399                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7400                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7401
7402                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7403                 "setbe %c[fail](%0) \n\t"
7404                 ".pushsection .rodata \n\t"
7405                 ".global vmx_return \n\t"
7406                 "vmx_return: " _ASM_PTR " 2b \n\t"
7407                 ".popsection"
7408               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7409                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7410                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7411                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7412                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7413                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7414                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7415                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7416                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7417                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7418                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7419 #ifdef CONFIG_X86_64
7420                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7421                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7422                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7423                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7424                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7425                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7426                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7427                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7428 #endif
7429                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7430                 [wordsize]"i"(sizeof(ulong))
7431               : "cc", "memory"
7432 #ifdef CONFIG_X86_64
7433                 , "rax", "rbx", "rdi", "rsi"
7434                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7435 #else
7436                 , "eax", "ebx", "edi", "esi"
7437 #endif
7438               );
7439
7440         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7441         if (debugctlmsr)
7442                 update_debugctlmsr(debugctlmsr);
7443
7444 #ifndef CONFIG_X86_64
7445         /*
7446          * The sysexit path does not restore ds/es, so we must set them to
7447          * a reasonable value ourselves.
7448          *
7449          * We can't defer this to vmx_load_host_state() since that function
7450          * may be executed in interrupt context, which saves and restore segments
7451          * around it, nullifying its effect.
7452          */
7453         loadsegment(ds, __USER_DS);
7454         loadsegment(es, __USER_DS);
7455 #endif
7456
7457         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7458                                   | (1 << VCPU_EXREG_RFLAGS)
7459                                   | (1 << VCPU_EXREG_PDPTR)
7460                                   | (1 << VCPU_EXREG_SEGMENTS)
7461                                   | (1 << VCPU_EXREG_CR3));
7462         vcpu->arch.regs_dirty = 0;
7463
7464         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7465
7466         vmx->loaded_vmcs->launched = 1;
7467
7468         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7469         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7470
7471         /*
7472          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7473          * we did not inject a still-pending event to L1 now because of
7474          * nested_run_pending, we need to re-enable this bit.
7475          */
7476         if (vmx->nested.nested_run_pending)
7477                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7478
7479         vmx->nested.nested_run_pending = 0;
7480
7481         vmx_complete_atomic_exit(vmx);
7482         vmx_recover_nmi_blocking(vmx);
7483         vmx_complete_interrupts(vmx);
7484 }
7485
7486 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7487 {
7488         struct vcpu_vmx *vmx = to_vmx(vcpu);
7489
7490         free_vpid(vmx);
7491         free_loaded_vmcs(vmx->loaded_vmcs);
7492         free_nested(vmx);
7493         kfree(vmx->guest_msrs);
7494         kvm_vcpu_uninit(vcpu);
7495         kmem_cache_free(kvm_vcpu_cache, vmx);
7496 }
7497
7498 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7499 {
7500         int err;
7501         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7502         int cpu;
7503
7504         if (!vmx)
7505                 return ERR_PTR(-ENOMEM);
7506
7507         allocate_vpid(vmx);
7508
7509         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7510         if (err)
7511                 goto free_vcpu;
7512
7513         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7514         err = -ENOMEM;
7515         if (!vmx->guest_msrs) {
7516                 goto uninit_vcpu;
7517         }
7518
7519         vmx->loaded_vmcs = &vmx->vmcs01;
7520         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7521         if (!vmx->loaded_vmcs->vmcs)
7522                 goto free_msrs;
7523         if (!vmm_exclusive)
7524                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7525         loaded_vmcs_init(vmx->loaded_vmcs);
7526         if (!vmm_exclusive)
7527                 kvm_cpu_vmxoff();
7528
7529         cpu = get_cpu();
7530         vmx_vcpu_load(&vmx->vcpu, cpu);
7531         vmx->vcpu.cpu = cpu;
7532         err = vmx_vcpu_setup(vmx);
7533         vmx_vcpu_put(&vmx->vcpu);
7534         put_cpu();
7535         if (err)
7536                 goto free_vmcs;
7537         if (vm_need_virtualize_apic_accesses(kvm)) {
7538                 err = alloc_apic_access_page(kvm);
7539                 if (err)
7540                         goto free_vmcs;
7541         }
7542
7543         if (enable_ept) {
7544                 if (!kvm->arch.ept_identity_map_addr)
7545                         kvm->arch.ept_identity_map_addr =
7546                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7547                 err = -ENOMEM;
7548                 if (alloc_identity_pagetable(kvm) != 0)
7549                         goto free_vmcs;
7550                 if (!init_rmode_identity_map(kvm))
7551                         goto free_vmcs;
7552         }
7553
7554         vmx->nested.current_vmptr = -1ull;
7555         vmx->nested.current_vmcs12 = NULL;
7556
7557         return &vmx->vcpu;
7558
7559 free_vmcs:
7560         free_loaded_vmcs(vmx->loaded_vmcs);
7561 free_msrs:
7562         kfree(vmx->guest_msrs);
7563 uninit_vcpu:
7564         kvm_vcpu_uninit(&vmx->vcpu);
7565 free_vcpu:
7566         free_vpid(vmx);
7567         kmem_cache_free(kvm_vcpu_cache, vmx);
7568         return ERR_PTR(err);
7569 }
7570
7571 static void __init vmx_check_processor_compat(void *rtn)
7572 {
7573         struct vmcs_config vmcs_conf;
7574
7575         *(int *)rtn = 0;
7576         if (setup_vmcs_config(&vmcs_conf) < 0)
7577                 *(int *)rtn = -EIO;
7578         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7579                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7580                                 smp_processor_id());
7581                 *(int *)rtn = -EIO;
7582         }
7583 }
7584
7585 static int get_ept_level(void)
7586 {
7587         return VMX_EPT_DEFAULT_GAW + 1;
7588 }
7589
7590 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7591 {
7592         u64 ret;
7593
7594         /* For VT-d and EPT combination
7595          * 1. MMIO: always map as UC
7596          * 2. EPT with VT-d:
7597          *   a. VT-d without snooping control feature: can't guarantee the
7598          *      result, try to trust guest.
7599          *   b. VT-d with snooping control feature: snooping control feature of
7600          *      VT-d engine can guarantee the cache correctness. Just set it
7601          *      to WB to keep consistent with host. So the same as item 3.
7602          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7603          *    consistent with host MTRR
7604          */
7605         if (is_mmio)
7606                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7607         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7608                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7609                       VMX_EPT_MT_EPTE_SHIFT;
7610         else
7611                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7612                         | VMX_EPT_IPAT_BIT;
7613
7614         return ret;
7615 }
7616
7617 static int vmx_get_lpage_level(void)
7618 {
7619         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7620                 return PT_DIRECTORY_LEVEL;
7621         else
7622                 /* For shadow and EPT supported 1GB page */
7623                 return PT_PDPE_LEVEL;
7624 }
7625
7626 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7627 {
7628         struct kvm_cpuid_entry2 *best;
7629         struct vcpu_vmx *vmx = to_vmx(vcpu);
7630         u32 exec_control;
7631
7632         vmx->rdtscp_enabled = false;
7633         if (vmx_rdtscp_supported()) {
7634                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7635                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7636                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7637                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7638                                 vmx->rdtscp_enabled = true;
7639                         else {
7640                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7641                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7642                                                 exec_control);
7643                         }
7644                 }
7645         }
7646
7647         /* Exposing INVPCID only when PCID is exposed */
7648         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7649         if (vmx_invpcid_supported() &&
7650             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7651             guest_cpuid_has_pcid(vcpu)) {
7652                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7653                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7654                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7655                              exec_control);
7656         } else {
7657                 if (cpu_has_secondary_exec_ctrls()) {
7658                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7659                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7660                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7661                                      exec_control);
7662                 }
7663                 if (best)
7664                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7665         }
7666 }
7667
7668 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7669 {
7670         if (func == 1 && nested)
7671                 entry->ecx |= bit(X86_FEATURE_VMX);
7672 }
7673
7674 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7675                 struct x86_exception *fault)
7676 {
7677         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7678         u32 exit_reason;
7679
7680         if (fault->error_code & PFERR_RSVD_MASK)
7681                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7682         else
7683                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7684         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7685         vmcs12->guest_physical_address = fault->address;
7686 }
7687
7688 /* Callbacks for nested_ept_init_mmu_context: */
7689
7690 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7691 {
7692         /* return the page table to be shadowed - in our case, EPT12 */
7693         return get_vmcs12(vcpu)->ept_pointer;
7694 }
7695
7696 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7697 {
7698         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7699                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7700
7701         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7702         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7703         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7704
7705         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7706 }
7707
7708 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7709 {
7710         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7711 }
7712
7713 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7714                 struct x86_exception *fault)
7715 {
7716         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7717
7718         WARN_ON(!is_guest_mode(vcpu));
7719
7720         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7721         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7722                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7723                                   vmcs_read32(VM_EXIT_INTR_INFO),
7724                                   vmcs_readl(EXIT_QUALIFICATION));
7725         else
7726                 kvm_inject_page_fault(vcpu, fault);
7727 }
7728
7729 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7730 {
7731         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7732         struct vcpu_vmx *vmx = to_vmx(vcpu);
7733
7734         if (vcpu->arch.virtual_tsc_khz == 0)
7735                 return;
7736
7737         /* Make sure short timeouts reliably trigger an immediate vmexit.
7738          * hrtimer_start does not guarantee this. */
7739         if (preemption_timeout <= 1) {
7740                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7741                 return;
7742         }
7743
7744         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7745         preemption_timeout *= 1000000;
7746         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7747         hrtimer_start(&vmx->nested.preemption_timer,
7748                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7749 }
7750
7751 /*
7752  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7753  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7754  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7755  * guest in a way that will both be appropriate to L1's requests, and our
7756  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7757  * function also has additional necessary side-effects, like setting various
7758  * vcpu->arch fields.
7759  */
7760 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7761 {
7762         struct vcpu_vmx *vmx = to_vmx(vcpu);
7763         u32 exec_control;
7764
7765         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7766         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7767         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7768         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7769         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7770         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7771         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7772         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7773         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7774         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7775         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7776         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7777         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7778         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7779         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7780         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7781         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7782         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7783         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7784         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7785         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7786         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7787         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7788         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7789         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7790         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7791         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7792         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7793         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7794         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7795         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7796         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7797         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7798         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7799         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7800         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7801
7802         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7803         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7804                 vmcs12->vm_entry_intr_info_field);
7805         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7806                 vmcs12->vm_entry_exception_error_code);
7807         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7808                 vmcs12->vm_entry_instruction_len);
7809         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7810                 vmcs12->guest_interruptibility_info);
7811         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7812         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7813         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7814         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7815                 vmcs12->guest_pending_dbg_exceptions);
7816         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7817         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7818
7819         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7820
7821         exec_control = vmcs12->pin_based_vm_exec_control;
7822         exec_control |= vmcs_config.pin_based_exec_ctrl;
7823         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7824         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
7825
7826         vmx->nested.preemption_timer_expired = false;
7827         if (nested_cpu_has_preemption_timer(vmcs12))
7828                 vmx_start_preemption_timer(vcpu);
7829
7830         /*
7831          * Whether page-faults are trapped is determined by a combination of
7832          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7833          * If enable_ept, L0 doesn't care about page faults and we should
7834          * set all of these to L1's desires. However, if !enable_ept, L0 does
7835          * care about (at least some) page faults, and because it is not easy
7836          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7837          * to exit on each and every L2 page fault. This is done by setting
7838          * MASK=MATCH=0 and (see below) EB.PF=1.
7839          * Note that below we don't need special code to set EB.PF beyond the
7840          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7841          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7842          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7843          *
7844          * A problem with this approach (when !enable_ept) is that L1 may be
7845          * injected with more page faults than it asked for. This could have
7846          * caused problems, but in practice existing hypervisors don't care.
7847          * To fix this, we will need to emulate the PFEC checking (on the L1
7848          * page tables), using walk_addr(), when injecting PFs to L1.
7849          */
7850         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7851                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7852         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7853                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7854
7855         if (cpu_has_secondary_exec_ctrls()) {
7856                 exec_control = vmx_secondary_exec_control(vmx);
7857                 if (!vmx->rdtscp_enabled)
7858                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7859                 /* Take the following fields only from vmcs12 */
7860                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7861                 if (nested_cpu_has(vmcs12,
7862                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7863                         exec_control |= vmcs12->secondary_vm_exec_control;
7864
7865                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7866                         /*
7867                          * Translate L1 physical address to host physical
7868                          * address for vmcs02. Keep the page pinned, so this
7869                          * physical address remains valid. We keep a reference
7870                          * to it so we can release it later.
7871                          */
7872                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7873                                 nested_release_page(vmx->nested.apic_access_page);
7874                         vmx->nested.apic_access_page =
7875                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7876                         /*
7877                          * If translation failed, no matter: This feature asks
7878                          * to exit when accessing the given address, and if it
7879                          * can never be accessed, this feature won't do
7880                          * anything anyway.
7881                          */
7882                         if (!vmx->nested.apic_access_page)
7883                                 exec_control &=
7884                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7885                         else
7886                                 vmcs_write64(APIC_ACCESS_ADDR,
7887                                   page_to_phys(vmx->nested.apic_access_page));
7888                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7889                         exec_control |=
7890                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7891                         vmcs_write64(APIC_ACCESS_ADDR,
7892                                 page_to_phys(vcpu->kvm->arch.apic_access_page));
7893                 }
7894
7895                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7896         }
7897
7898
7899         /*
7900          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7901          * Some constant fields are set here by vmx_set_constant_host_state().
7902          * Other fields are different per CPU, and will be set later when
7903          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7904          */
7905         vmx_set_constant_host_state(vmx);
7906
7907         /*
7908          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7909          * entry, but only if the current (host) sp changed from the value
7910          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7911          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7912          * here we just force the write to happen on entry.
7913          */
7914         vmx->host_rsp = 0;
7915
7916         exec_control = vmx_exec_control(vmx); /* L0's desires */
7917         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7918         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7919         exec_control &= ~CPU_BASED_TPR_SHADOW;
7920         exec_control |= vmcs12->cpu_based_vm_exec_control;
7921         /*
7922          * Merging of IO and MSR bitmaps not currently supported.
7923          * Rather, exit every time.
7924          */
7925         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7926         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7927         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7928
7929         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7930
7931         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7932          * bitwise-or of what L1 wants to trap for L2, and what we want to
7933          * trap. Note that CR0.TS also needs updating - we do this later.
7934          */
7935         update_exception_bitmap(vcpu);
7936         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7937         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7938
7939         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7940          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7941          * bits are further modified by vmx_set_efer() below.
7942          */
7943         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7944
7945         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7946          * emulated by vmx_set_efer(), below.
7947          */
7948         vm_entry_controls_init(vmx,
7949                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7950                         ~VM_ENTRY_IA32E_MODE) |
7951                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7952
7953         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7954                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7955                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7956         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7957                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7958
7959
7960         set_cr4_guest_host_mask(vmx);
7961
7962         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7963                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7964
7965         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7966                 vmcs_write64(TSC_OFFSET,
7967                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7968         else
7969                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7970
7971         if (enable_vpid) {
7972                 /*
7973                  * Trivially support vpid by letting L2s share their parent
7974                  * L1's vpid. TODO: move to a more elaborate solution, giving
7975                  * each L2 its own vpid and exposing the vpid feature to L1.
7976                  */
7977                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7978                 vmx_flush_tlb(vcpu);
7979         }
7980
7981         if (nested_cpu_has_ept(vmcs12)) {
7982                 kvm_mmu_unload(vcpu);
7983                 nested_ept_init_mmu_context(vcpu);
7984         }
7985
7986         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7987                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7988         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7989                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7990         else
7991                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7992         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7993         vmx_set_efer(vcpu, vcpu->arch.efer);
7994
7995         /*
7996          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7997          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7998          * The CR0_READ_SHADOW is what L2 should have expected to read given
7999          * the specifications by L1; It's not enough to take
8000          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8001          * have more bits than L1 expected.
8002          */
8003         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8004         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8005
8006         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8007         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8008
8009         /* shadow page tables on either EPT or shadow page tables */
8010         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8011         kvm_mmu_reset_context(vcpu);
8012
8013         if (!enable_ept)
8014                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8015
8016         /*
8017          * L1 may access the L2's PDPTR, so save them to construct vmcs12
8018          */
8019         if (enable_ept) {
8020                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8021                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8022                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8023                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8024         }
8025
8026         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8027         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8028 }
8029
8030 /*
8031  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8032  * for running an L2 nested guest.
8033  */
8034 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8035 {
8036         struct vmcs12 *vmcs12;
8037         struct vcpu_vmx *vmx = to_vmx(vcpu);
8038         int cpu;
8039         struct loaded_vmcs *vmcs02;
8040         bool ia32e;
8041
8042         if (!nested_vmx_check_permission(vcpu) ||
8043             !nested_vmx_check_vmcs12(vcpu))
8044                 return 1;
8045
8046         skip_emulated_instruction(vcpu);
8047         vmcs12 = get_vmcs12(vcpu);
8048
8049         if (enable_shadow_vmcs)
8050                 copy_shadow_to_vmcs12(vmx);
8051
8052         /*
8053          * The nested entry process starts with enforcing various prerequisites
8054          * on vmcs12 as required by the Intel SDM, and act appropriately when
8055          * they fail: As the SDM explains, some conditions should cause the
8056          * instruction to fail, while others will cause the instruction to seem
8057          * to succeed, but return an EXIT_REASON_INVALID_STATE.
8058          * To speed up the normal (success) code path, we should avoid checking
8059          * for misconfigurations which will anyway be caught by the processor
8060          * when using the merged vmcs02.
8061          */
8062         if (vmcs12->launch_state == launch) {
8063                 nested_vmx_failValid(vcpu,
8064                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8065                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8066                 return 1;
8067         }
8068
8069         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8070             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8071                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8072                 return 1;
8073         }
8074
8075         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8076                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
8077                 /*TODO: Also verify bits beyond physical address width are 0*/
8078                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8079                 return 1;
8080         }
8081
8082         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8083                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8084                 /*TODO: Also verify bits beyond physical address width are 0*/
8085                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8086                 return 1;
8087         }
8088
8089         if (vmcs12->vm_entry_msr_load_count > 0 ||
8090             vmcs12->vm_exit_msr_load_count > 0 ||
8091             vmcs12->vm_exit_msr_store_count > 0) {
8092                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8093                                     __func__);
8094                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8095                 return 1;
8096         }
8097
8098         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8099               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8100             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8101               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8102             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8103               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8104             !vmx_control_verify(vmcs12->vm_exit_controls,
8105               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8106             !vmx_control_verify(vmcs12->vm_entry_controls,
8107               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8108         {
8109                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8110                 return 1;
8111         }
8112
8113         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8114             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8115                 nested_vmx_failValid(vcpu,
8116                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8117                 return 1;
8118         }
8119
8120         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8121             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8122                 nested_vmx_entry_failure(vcpu, vmcs12,
8123                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8124                 return 1;
8125         }
8126         if (vmcs12->vmcs_link_pointer != -1ull) {
8127                 nested_vmx_entry_failure(vcpu, vmcs12,
8128                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8129                 return 1;
8130         }
8131
8132         /*
8133          * If the load IA32_EFER VM-entry control is 1, the following checks
8134          * are performed on the field for the IA32_EFER MSR:
8135          * - Bits reserved in the IA32_EFER MSR must be 0.
8136          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8137          *   the IA-32e mode guest VM-exit control. It must also be identical
8138          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8139          *   CR0.PG) is 1.
8140          */
8141         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8142                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8143                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8144                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8145                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8146                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8147                         nested_vmx_entry_failure(vcpu, vmcs12,
8148                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8149                         return 1;
8150                 }
8151         }
8152
8153         /*
8154          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8155          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8156          * the values of the LMA and LME bits in the field must each be that of
8157          * the host address-space size VM-exit control.
8158          */
8159         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8160                 ia32e = (vmcs12->vm_exit_controls &
8161                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8162                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8163                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8164                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8165                         nested_vmx_entry_failure(vcpu, vmcs12,
8166                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8167                         return 1;
8168                 }
8169         }
8170
8171         /*
8172          * We're finally done with prerequisite checking, and can start with
8173          * the nested entry.
8174          */
8175
8176         vmcs02 = nested_get_current_vmcs02(vmx);
8177         if (!vmcs02)
8178                 return -ENOMEM;
8179
8180         enter_guest_mode(vcpu);
8181
8182         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8183
8184         cpu = get_cpu();
8185         vmx->loaded_vmcs = vmcs02;
8186         vmx_vcpu_put(vcpu);
8187         vmx_vcpu_load(vcpu, cpu);
8188         vcpu->cpu = cpu;
8189         put_cpu();
8190
8191         vmx_segment_cache_clear(vmx);
8192
8193         vmcs12->launch_state = 1;
8194
8195         prepare_vmcs02(vcpu, vmcs12);
8196
8197         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8198                 return kvm_emulate_halt(vcpu);
8199
8200         vmx->nested.nested_run_pending = 1;
8201
8202         /*
8203          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8204          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8205          * returned as far as L1 is concerned. It will only return (and set
8206          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8207          */
8208         return 1;
8209 }
8210
8211 /*
8212  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8213  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8214  * This function returns the new value we should put in vmcs12.guest_cr0.
8215  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8216  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8217  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8218  *     didn't trap the bit, because if L1 did, so would L0).
8219  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8220  *     been modified by L2, and L1 knows it. So just leave the old value of
8221  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8222  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8223  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8224  *     changed these bits, and therefore they need to be updated, but L0
8225  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8226  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8227  */
8228 static inline unsigned long
8229 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8230 {
8231         return
8232         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8233         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8234         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8235                         vcpu->arch.cr0_guest_owned_bits));
8236 }
8237
8238 static inline unsigned long
8239 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8240 {
8241         return
8242         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8243         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8244         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8245                         vcpu->arch.cr4_guest_owned_bits));
8246 }
8247
8248 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8249                                        struct vmcs12 *vmcs12)
8250 {
8251         u32 idt_vectoring;
8252         unsigned int nr;
8253
8254         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8255                 nr = vcpu->arch.exception.nr;
8256                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8257
8258                 if (kvm_exception_is_soft(nr)) {
8259                         vmcs12->vm_exit_instruction_len =
8260                                 vcpu->arch.event_exit_inst_len;
8261                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8262                 } else
8263                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8264
8265                 if (vcpu->arch.exception.has_error_code) {
8266                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8267                         vmcs12->idt_vectoring_error_code =
8268                                 vcpu->arch.exception.error_code;
8269                 }
8270
8271                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8272         } else if (vcpu->arch.nmi_injected) {
8273                 vmcs12->idt_vectoring_info_field =
8274                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8275         } else if (vcpu->arch.interrupt.pending) {
8276                 nr = vcpu->arch.interrupt.nr;
8277                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8278
8279                 if (vcpu->arch.interrupt.soft) {
8280                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8281                         vmcs12->vm_entry_instruction_len =
8282                                 vcpu->arch.event_exit_inst_len;
8283                 } else
8284                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8285
8286                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8287         }
8288 }
8289
8290 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8291 {
8292         struct vcpu_vmx *vmx = to_vmx(vcpu);
8293
8294         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8295             vmx->nested.preemption_timer_expired) {
8296                 if (vmx->nested.nested_run_pending)
8297                         return -EBUSY;
8298                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8299                 return 0;
8300         }
8301
8302         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8303                 if (vmx->nested.nested_run_pending ||
8304                     vcpu->arch.interrupt.pending)
8305                         return -EBUSY;
8306                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8307                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8308                                   INTR_INFO_VALID_MASK, 0);
8309                 /*
8310                  * The NMI-triggered VM exit counts as injection:
8311                  * clear this one and block further NMIs.
8312                  */
8313                 vcpu->arch.nmi_pending = 0;
8314                 vmx_set_nmi_mask(vcpu, true);
8315                 return 0;
8316         }
8317
8318         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8319             nested_exit_on_intr(vcpu)) {
8320                 if (vmx->nested.nested_run_pending)
8321                         return -EBUSY;
8322                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8323         }
8324
8325         return 0;
8326 }
8327
8328 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8329 {
8330         ktime_t remaining =
8331                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8332         u64 value;
8333
8334         if (ktime_to_ns(remaining) <= 0)
8335                 return 0;
8336
8337         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8338         do_div(value, 1000000);
8339         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8340 }
8341
8342 /*
8343  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8344  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8345  * and this function updates it to reflect the changes to the guest state while
8346  * L2 was running (and perhaps made some exits which were handled directly by L0
8347  * without going back to L1), and to reflect the exit reason.
8348  * Note that we do not have to copy here all VMCS fields, just those that
8349  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8350  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8351  * which already writes to vmcs12 directly.
8352  */
8353 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8354                            u32 exit_reason, u32 exit_intr_info,
8355                            unsigned long exit_qualification)
8356 {
8357         /* update guest state fields: */
8358         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8359         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8360
8361         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8362         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8363         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8364         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8365
8366         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8367         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8368         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8369         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8370         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8371         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8372         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8373         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8374         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8375         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8376         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8377         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8378         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8379         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8380         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8381         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8382         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8383         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8384         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8385         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8386         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8387         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8388         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8389         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8390         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8391         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8392         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8393         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8394         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8395         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8396         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8397         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8398         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8399         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8400         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8401         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8402
8403         vmcs12->guest_interruptibility_info =
8404                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8405         vmcs12->guest_pending_dbg_exceptions =
8406                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8407         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8408                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8409         else
8410                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8411
8412         if (nested_cpu_has_preemption_timer(vmcs12)) {
8413                 if (vmcs12->vm_exit_controls &
8414                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8415                         vmcs12->vmx_preemption_timer_value =
8416                                 vmx_get_preemption_timer_value(vcpu);
8417                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8418         }
8419
8420         /*
8421          * In some cases (usually, nested EPT), L2 is allowed to change its
8422          * own CR3 without exiting. If it has changed it, we must keep it.
8423          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8424          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8425          *
8426          * Additionally, restore L2's PDPTR to vmcs12.
8427          */
8428         if (enable_ept) {
8429                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8430                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8431                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8432                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8433                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8434         }
8435
8436         vmcs12->vm_entry_controls =
8437                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8438                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8439
8440         /* TODO: These cannot have changed unless we have MSR bitmaps and
8441          * the relevant bit asks not to trap the change */
8442         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8443         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8444                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8445         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8446                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8447         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8448         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8449         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8450         if (vmx_mpx_supported())
8451                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8452
8453         /* update exit information fields: */
8454
8455         vmcs12->vm_exit_reason = exit_reason;
8456         vmcs12->exit_qualification = exit_qualification;
8457
8458         vmcs12->vm_exit_intr_info = exit_intr_info;
8459         if ((vmcs12->vm_exit_intr_info &
8460              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8461             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8462                 vmcs12->vm_exit_intr_error_code =
8463                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8464         vmcs12->idt_vectoring_info_field = 0;
8465         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8466         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8467
8468         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8469                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8470                  * instead of reading the real value. */
8471                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8472
8473                 /*
8474                  * Transfer the event that L0 or L1 may wanted to inject into
8475                  * L2 to IDT_VECTORING_INFO_FIELD.
8476                  */
8477                 vmcs12_save_pending_event(vcpu, vmcs12);
8478         }
8479
8480         /*
8481          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8482          * preserved above and would only end up incorrectly in L1.
8483          */
8484         vcpu->arch.nmi_injected = false;
8485         kvm_clear_exception_queue(vcpu);
8486         kvm_clear_interrupt_queue(vcpu);
8487 }
8488
8489 /*
8490  * A part of what we need to when the nested L2 guest exits and we want to
8491  * run its L1 parent, is to reset L1's guest state to the host state specified
8492  * in vmcs12.
8493  * This function is to be called not only on normal nested exit, but also on
8494  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8495  * Failures During or After Loading Guest State").
8496  * This function should be called when the active VMCS is L1's (vmcs01).
8497  */
8498 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8499                                    struct vmcs12 *vmcs12)
8500 {
8501         struct kvm_segment seg;
8502
8503         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8504                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8505         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8506                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8507         else
8508                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8509         vmx_set_efer(vcpu, vcpu->arch.efer);
8510
8511         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8512         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8513         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8514         /*
8515          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8516          * actually changed, because it depends on the current state of
8517          * fpu_active (which may have changed).
8518          * Note that vmx_set_cr0 refers to efer set above.
8519          */
8520         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8521         /*
8522          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8523          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8524          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8525          */
8526         update_exception_bitmap(vcpu);
8527         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8528         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8529
8530         /*
8531          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8532          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8533          */
8534         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8535         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8536
8537         nested_ept_uninit_mmu_context(vcpu);
8538
8539         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8540         kvm_mmu_reset_context(vcpu);
8541
8542         if (!enable_ept)
8543                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8544
8545         if (enable_vpid) {
8546                 /*
8547                  * Trivially support vpid by letting L2s share their parent
8548                  * L1's vpid. TODO: move to a more elaborate solution, giving
8549                  * each L2 its own vpid and exposing the vpid feature to L1.
8550                  */
8551                 vmx_flush_tlb(vcpu);
8552         }
8553
8554
8555         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8556         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8557         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8558         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8559         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8560
8561         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
8562         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8563                 vmcs_write64(GUEST_BNDCFGS, 0);
8564
8565         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8566                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8567                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8568         }
8569         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8570                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8571                         vmcs12->host_ia32_perf_global_ctrl);
8572
8573         /* Set L1 segment info according to Intel SDM
8574             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8575         seg = (struct kvm_segment) {
8576                 .base = 0,
8577                 .limit = 0xFFFFFFFF,
8578                 .selector = vmcs12->host_cs_selector,
8579                 .type = 11,
8580                 .present = 1,
8581                 .s = 1,
8582                 .g = 1
8583         };
8584         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8585                 seg.l = 1;
8586         else
8587                 seg.db = 1;
8588         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8589         seg = (struct kvm_segment) {
8590                 .base = 0,
8591                 .limit = 0xFFFFFFFF,
8592                 .type = 3,
8593                 .present = 1,
8594                 .s = 1,
8595                 .db = 1,
8596                 .g = 1
8597         };
8598         seg.selector = vmcs12->host_ds_selector;
8599         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8600         seg.selector = vmcs12->host_es_selector;
8601         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8602         seg.selector = vmcs12->host_ss_selector;
8603         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8604         seg.selector = vmcs12->host_fs_selector;
8605         seg.base = vmcs12->host_fs_base;
8606         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8607         seg.selector = vmcs12->host_gs_selector;
8608         seg.base = vmcs12->host_gs_base;
8609         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8610         seg = (struct kvm_segment) {
8611                 .base = vmcs12->host_tr_base,
8612                 .limit = 0x67,
8613                 .selector = vmcs12->host_tr_selector,
8614                 .type = 11,
8615                 .present = 1
8616         };
8617         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8618
8619         kvm_set_dr(vcpu, 7, 0x400);
8620         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8621 }
8622
8623 /*
8624  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8625  * and modify vmcs12 to make it see what it would expect to see there if
8626  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8627  */
8628 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8629                               u32 exit_intr_info,
8630                               unsigned long exit_qualification)
8631 {
8632         struct vcpu_vmx *vmx = to_vmx(vcpu);
8633         int cpu;
8634         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8635
8636         /* trying to cancel vmlaunch/vmresume is a bug */
8637         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8638
8639         leave_guest_mode(vcpu);
8640         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8641                        exit_qualification);
8642
8643         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8644             && nested_exit_intr_ack_set(vcpu)) {
8645                 int irq = kvm_cpu_get_interrupt(vcpu);
8646                 WARN_ON(irq < 0);
8647                 vmcs12->vm_exit_intr_info = irq |
8648                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8649         }
8650
8651         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8652                                        vmcs12->exit_qualification,
8653                                        vmcs12->idt_vectoring_info_field,
8654                                        vmcs12->vm_exit_intr_info,
8655                                        vmcs12->vm_exit_intr_error_code,
8656                                        KVM_ISA_VMX);
8657
8658         cpu = get_cpu();
8659         vmx->loaded_vmcs = &vmx->vmcs01;
8660         vmx_vcpu_put(vcpu);
8661         vmx_vcpu_load(vcpu, cpu);
8662         vcpu->cpu = cpu;
8663         put_cpu();
8664
8665         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8666         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8667         vmx_segment_cache_clear(vmx);
8668
8669         /* if no vmcs02 cache requested, remove the one we used */
8670         if (VMCS02_POOL_SIZE == 0)
8671                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8672
8673         load_vmcs12_host_state(vcpu, vmcs12);
8674
8675         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8676         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8677
8678         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8679         vmx->host_rsp = 0;
8680
8681         /* Unpin physical memory we referred to in vmcs02 */
8682         if (vmx->nested.apic_access_page) {
8683                 nested_release_page(vmx->nested.apic_access_page);
8684                 vmx->nested.apic_access_page = 0;
8685         }
8686
8687         /*
8688          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8689          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8690          * success or failure flag accordingly.
8691          */
8692         if (unlikely(vmx->fail)) {
8693                 vmx->fail = 0;
8694                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8695         } else
8696                 nested_vmx_succeed(vcpu);
8697         if (enable_shadow_vmcs)
8698                 vmx->nested.sync_shadow_vmcs = true;
8699
8700         /* in case we halted in L2 */
8701         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8702 }
8703
8704 /*
8705  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8706  */
8707 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8708 {
8709         if (is_guest_mode(vcpu))
8710                 nested_vmx_vmexit(vcpu, -1, 0, 0);
8711         free_nested(to_vmx(vcpu));
8712 }
8713
8714 /*
8715  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8716  * 23.7 "VM-entry failures during or after loading guest state" (this also
8717  * lists the acceptable exit-reason and exit-qualification parameters).
8718  * It should only be called before L2 actually succeeded to run, and when
8719  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8720  */
8721 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8722                         struct vmcs12 *vmcs12,
8723                         u32 reason, unsigned long qualification)
8724 {
8725         load_vmcs12_host_state(vcpu, vmcs12);
8726         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8727         vmcs12->exit_qualification = qualification;
8728         nested_vmx_succeed(vcpu);
8729         if (enable_shadow_vmcs)
8730                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8731 }
8732
8733 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8734                                struct x86_instruction_info *info,
8735                                enum x86_intercept_stage stage)
8736 {
8737         return X86EMUL_CONTINUE;
8738 }
8739
8740 static struct kvm_x86_ops vmx_x86_ops = {
8741         .cpu_has_kvm_support = cpu_has_kvm_support,
8742         .disabled_by_bios = vmx_disabled_by_bios,
8743         .hardware_setup = hardware_setup,
8744         .hardware_unsetup = hardware_unsetup,
8745         .check_processor_compatibility = vmx_check_processor_compat,
8746         .hardware_enable = hardware_enable,
8747         .hardware_disable = hardware_disable,
8748         .cpu_has_accelerated_tpr = report_flexpriority,
8749
8750         .vcpu_create = vmx_create_vcpu,
8751         .vcpu_free = vmx_free_vcpu,
8752         .vcpu_reset = vmx_vcpu_reset,
8753
8754         .prepare_guest_switch = vmx_save_host_state,
8755         .vcpu_load = vmx_vcpu_load,
8756         .vcpu_put = vmx_vcpu_put,
8757
8758         .update_db_bp_intercept = update_exception_bitmap,
8759         .get_msr = vmx_get_msr,
8760         .set_msr = vmx_set_msr,
8761         .get_segment_base = vmx_get_segment_base,
8762         .get_segment = vmx_get_segment,
8763         .set_segment = vmx_set_segment,
8764         .get_cpl = vmx_get_cpl,
8765         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8766         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8767         .decache_cr3 = vmx_decache_cr3,
8768         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8769         .set_cr0 = vmx_set_cr0,
8770         .set_cr3 = vmx_set_cr3,
8771         .set_cr4 = vmx_set_cr4,
8772         .set_efer = vmx_set_efer,
8773         .get_idt = vmx_get_idt,
8774         .set_idt = vmx_set_idt,
8775         .get_gdt = vmx_get_gdt,
8776         .set_gdt = vmx_set_gdt,
8777         .get_dr6 = vmx_get_dr6,
8778         .set_dr6 = vmx_set_dr6,
8779         .set_dr7 = vmx_set_dr7,
8780         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8781         .cache_reg = vmx_cache_reg,
8782         .get_rflags = vmx_get_rflags,
8783         .set_rflags = vmx_set_rflags,
8784         .fpu_activate = vmx_fpu_activate,
8785         .fpu_deactivate = vmx_fpu_deactivate,
8786
8787         .tlb_flush = vmx_flush_tlb,
8788
8789         .run = vmx_vcpu_run,
8790         .handle_exit = vmx_handle_exit,
8791         .skip_emulated_instruction = skip_emulated_instruction,
8792         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8793         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8794         .patch_hypercall = vmx_patch_hypercall,
8795         .set_irq = vmx_inject_irq,
8796         .set_nmi = vmx_inject_nmi,
8797         .queue_exception = vmx_queue_exception,
8798         .cancel_injection = vmx_cancel_injection,
8799         .interrupt_allowed = vmx_interrupt_allowed,
8800         .nmi_allowed = vmx_nmi_allowed,
8801         .get_nmi_mask = vmx_get_nmi_mask,
8802         .set_nmi_mask = vmx_set_nmi_mask,
8803         .enable_nmi_window = enable_nmi_window,
8804         .enable_irq_window = enable_irq_window,
8805         .update_cr8_intercept = update_cr8_intercept,
8806         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8807         .vm_has_apicv = vmx_vm_has_apicv,
8808         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8809         .hwapic_irr_update = vmx_hwapic_irr_update,
8810         .hwapic_isr_update = vmx_hwapic_isr_update,
8811         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8812         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8813
8814         .set_tss_addr = vmx_set_tss_addr,
8815         .get_tdp_level = get_ept_level,
8816         .get_mt_mask = vmx_get_mt_mask,
8817
8818         .get_exit_info = vmx_get_exit_info,
8819
8820         .get_lpage_level = vmx_get_lpage_level,
8821
8822         .cpuid_update = vmx_cpuid_update,
8823
8824         .rdtscp_supported = vmx_rdtscp_supported,
8825         .invpcid_supported = vmx_invpcid_supported,
8826
8827         .set_supported_cpuid = vmx_set_supported_cpuid,
8828
8829         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8830
8831         .set_tsc_khz = vmx_set_tsc_khz,
8832         .read_tsc_offset = vmx_read_tsc_offset,
8833         .write_tsc_offset = vmx_write_tsc_offset,
8834         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8835         .compute_tsc_offset = vmx_compute_tsc_offset,
8836         .read_l1_tsc = vmx_read_l1_tsc,
8837
8838         .set_tdp_cr3 = vmx_set_cr3,
8839
8840         .check_intercept = vmx_check_intercept,
8841         .handle_external_intr = vmx_handle_external_intr,
8842         .mpx_supported = vmx_mpx_supported,
8843
8844         .check_nested_events = vmx_check_nested_events,
8845 };
8846
8847 static int __init vmx_init(void)
8848 {
8849         int r, i, msr;
8850
8851         rdmsrl_safe(MSR_EFER, &host_efer);
8852
8853         for (i = 0; i < NR_VMX_MSR; ++i)
8854                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8855
8856         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8857         if (!vmx_io_bitmap_a)
8858                 return -ENOMEM;
8859
8860         r = -ENOMEM;
8861
8862         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8863         if (!vmx_io_bitmap_b)
8864                 goto out;
8865
8866         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8867         if (!vmx_msr_bitmap_legacy)
8868                 goto out1;
8869
8870         vmx_msr_bitmap_legacy_x2apic =
8871                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8872         if (!vmx_msr_bitmap_legacy_x2apic)
8873                 goto out2;
8874
8875         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8876         if (!vmx_msr_bitmap_longmode)
8877                 goto out3;
8878
8879         vmx_msr_bitmap_longmode_x2apic =
8880                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8881         if (!vmx_msr_bitmap_longmode_x2apic)
8882                 goto out4;
8883         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8884         if (!vmx_vmread_bitmap)
8885                 goto out5;
8886
8887         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8888         if (!vmx_vmwrite_bitmap)
8889                 goto out6;
8890
8891         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8892         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8893         /* shadowed read/write fields */
8894         for (i = 0; i < max_shadow_read_write_fields; i++) {
8895                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8896                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8897         }
8898         /* shadowed read only fields */
8899         for (i = 0; i < max_shadow_read_only_fields; i++)
8900                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8901
8902         /*
8903          * Allow direct access to the PC debug port (it is often used for I/O
8904          * delays, but the vmexits simply slow things down).
8905          */
8906         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8907         clear_bit(0x80, vmx_io_bitmap_a);
8908
8909         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8910
8911         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8912         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8913
8914         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8915
8916         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8917                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8918         if (r)
8919                 goto out7;
8920
8921 #ifdef CONFIG_KEXEC
8922         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8923                            crash_vmclear_local_loaded_vmcss);
8924 #endif
8925
8926         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8927         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8928         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8929         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8930         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8931         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8932         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8933
8934         memcpy(vmx_msr_bitmap_legacy_x2apic,
8935                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8936         memcpy(vmx_msr_bitmap_longmode_x2apic,
8937                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8938
8939         if (enable_apicv) {
8940                 for (msr = 0x800; msr <= 0x8ff; msr++)
8941                         vmx_disable_intercept_msr_read_x2apic(msr);
8942
8943                 /* According SDM, in x2apic mode, the whole id reg is used.
8944                  * But in KVM, it only use the highest eight bits. Need to
8945                  * intercept it */
8946                 vmx_enable_intercept_msr_read_x2apic(0x802);
8947                 /* TMCCT */
8948                 vmx_enable_intercept_msr_read_x2apic(0x839);
8949                 /* TPR */
8950                 vmx_disable_intercept_msr_write_x2apic(0x808);
8951                 /* EOI */
8952                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8953                 /* SELF-IPI */
8954                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8955         }
8956
8957         if (enable_ept) {
8958                 kvm_mmu_set_mask_ptes(0ull,
8959                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8960                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8961                         0ull, VMX_EPT_EXECUTABLE_MASK);
8962                 ept_set_mmio_spte_mask();
8963                 kvm_enable_tdp();
8964         } else
8965                 kvm_disable_tdp();
8966
8967         return 0;
8968
8969 out7:
8970         free_page((unsigned long)vmx_vmwrite_bitmap);
8971 out6:
8972         free_page((unsigned long)vmx_vmread_bitmap);
8973 out5:
8974         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8975 out4:
8976         free_page((unsigned long)vmx_msr_bitmap_longmode);
8977 out3:
8978         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8979 out2:
8980         free_page((unsigned long)vmx_msr_bitmap_legacy);
8981 out1:
8982         free_page((unsigned long)vmx_io_bitmap_b);
8983 out:
8984         free_page((unsigned long)vmx_io_bitmap_a);
8985         return r;
8986 }
8987
8988 static void __exit vmx_exit(void)
8989 {
8990         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8991         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8992         free_page((unsigned long)vmx_msr_bitmap_legacy);
8993         free_page((unsigned long)vmx_msr_bitmap_longmode);
8994         free_page((unsigned long)vmx_io_bitmap_b);
8995         free_page((unsigned long)vmx_io_bitmap_a);
8996         free_page((unsigned long)vmx_vmwrite_bitmap);
8997         free_page((unsigned long)vmx_vmread_bitmap);
8998
8999 #ifdef CONFIG_KEXEC
9000         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
9001         synchronize_rcu();
9002 #endif
9003
9004         kvm_exit();
9005 }
9006
9007 module_init(vmx_init)
9008 module_exit(vmx_exit)