1 // SPDX-License-Identifier: GPL-2.0
2 /* smp.c: Sparc SMP support.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/threads.h>
14 #include <linux/smp.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
21 #include <linux/seq_file.h>
22 #include <linux/cache.h>
23 #include <linux/delay.h>
24 #include <linux/profile.h>
25 #include <linux/cpu.h>
27 #include <asm/ptrace.h>
28 #include <linux/atomic.h>
32 #include <asm/pgalloc.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/cacheflush.h>
36 #include <asm/tlbflush.h>
37 #include <asm/cpudata.h>
38 #include <asm/timer.h>
44 volatile unsigned long cpu_callin_map[NR_CPUS] = {0,};
46 cpumask_t smp_commenced_mask = CPU_MASK_NONE;
48 const struct sparc32_ipi_ops *sparc32_ipi_ops;
50 /* The only guaranteed locking primitive available on all Sparc
51 * processors is 'ldstub [%reg + immediate], %dest_reg' which atomically
52 * places the current byte at the effective address into dest_reg and
53 * places 0xff there afterwards. Pretty lame locking primitive
54 * compared to the Alpha and the Intel no? Most Sparcs have 'swap'
55 * instruction which is much better...
58 void smp_store_cpu_info(int id)
63 cpu_data(id).udelay_val = loops_per_jiffy;
65 cpu_find_by_mid(id, &cpu_node);
66 cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
67 "clock-frequency", 0);
68 cpu_data(id).prom_node = cpu_node;
69 mid = cpu_get_hwmid(cpu_node);
72 printk(KERN_NOTICE "No MID found for CPU%d at node 0x%08x", id, cpu_node);
75 cpu_data(id).mid = mid;
78 void __init smp_cpus_done(unsigned int max_cpus)
80 unsigned long bogosum = 0;
83 for_each_online_cpu(cpu) {
85 bogosum += cpu_data(cpu).udelay_val;
88 printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
89 num, bogosum/(500000/HZ),
90 (bogosum/(5000/HZ))%100);
92 switch(sparc_cpu_model) {
111 printk("UNKNOWN!\n");
119 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
120 panic("SMP bolixed\n");
123 struct linux_prom_registers smp_penguin_ctable = { 0 };
125 void smp_send_reschedule(int cpu)
128 * CPU model dependent way of implementing IPI generation targeting
129 * a single CPU. The trap handler needs only to do trap entry/return
132 sparc32_ipi_ops->resched(cpu);
135 void smp_send_stop(void)
139 void arch_send_call_function_single_ipi(int cpu)
141 /* trigger one IPI single call on one CPU */
142 sparc32_ipi_ops->single(cpu);
145 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
149 /* trigger IPI mask call on each CPU */
150 for_each_cpu(cpu, mask)
151 sparc32_ipi_ops->mask_one(cpu);
154 void smp_resched_interrupt(void)
158 local_cpu_data().irq_resched_count++;
160 /* re-schedule routine called by interrupt return code. */
163 void smp_call_function_single_interrupt(void)
166 generic_smp_call_function_single_interrupt();
167 local_cpu_data().irq_call_count++;
171 void smp_call_function_interrupt(void)
174 generic_smp_call_function_interrupt();
175 local_cpu_data().irq_call_count++;
179 int setup_profiling_timer(unsigned int multiplier)
184 void __init smp_prepare_cpus(unsigned int max_cpus)
188 printk("Entering SMP Mode...\n");
191 for (i = 0; !cpu_find_by_instance(i, NULL, &cpuid); i++) {
192 if (cpuid >= NR_CPUS)
195 /* i = number of cpus */
196 if (extra && max_cpus > i - extra)
197 printk("Warning: NR_CPUS is too low to start all cpus\n");
199 smp_store_cpu_info(boot_cpu_id);
201 switch(sparc_cpu_model) {
220 printk("UNKNOWN!\n");
226 /* Set this up early so that things like the scheduler can init
227 * properly. We use the same cpu mask for both the present and
230 void __init smp_setup_cpu_possible_map(void)
235 while (!cpu_find_by_instance(instance, NULL, &mid)) {
237 set_cpu_possible(mid, true);
238 set_cpu_present(mid, true);
244 void __init smp_prepare_boot_cpu(void)
246 int cpuid = hard_smp_processor_id();
248 if (cpuid >= NR_CPUS) {
249 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
253 printk("boot cpu id != 0, this could work but is untested\n");
255 current_thread_info()->cpu = cpuid;
256 set_cpu_online(cpuid, true);
257 set_cpu_possible(cpuid, true);
260 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
264 switch(sparc_cpu_model) {
266 ret = smp4m_boot_one_cpu(cpu, tidle);
269 ret = smp4d_boot_one_cpu(cpu, tidle);
272 ret = leon_boot_one_cpu(cpu, tidle);
283 printk("UNKNOWN!\n");
289 cpumask_set_cpu(cpu, &smp_commenced_mask);
290 while (!cpu_online(cpu))
296 static void arch_cpu_pre_starting(void *arg)
298 local_ops->cache_all();
299 local_ops->tlb_all();
301 switch(sparc_cpu_model) {
303 sun4m_cpu_pre_starting(arg);
306 sun4d_cpu_pre_starting(arg);
309 leon_cpu_pre_starting(arg);
316 static void arch_cpu_pre_online(void *arg)
318 unsigned int cpuid = hard_smp_processor_id();
320 register_percpu_ce(cpuid);
323 smp_store_cpu_info(cpuid);
325 local_ops->cache_all();
326 local_ops->tlb_all();
328 switch(sparc_cpu_model) {
330 sun4m_cpu_pre_online(arg);
333 sun4d_cpu_pre_online(arg);
336 leon_cpu_pre_online(arg);
343 static void sparc_start_secondary(void *arg)
348 * SMP booting is extremely fragile in some architectures. So run
349 * the cpu initialization code first before anything else.
351 arch_cpu_pre_starting(arg);
354 cpu = smp_processor_id();
356 notify_cpu_starting(cpu);
357 arch_cpu_pre_online(arg);
359 /* Set the CPU in the cpu_online_mask */
360 set_cpu_online(cpu, true);
362 /* Enable local interrupts now */
366 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
368 /* We should never reach here! */
372 void smp_callin(void)
374 sparc_start_secondary(NULL);
377 void smp_bogo(struct seq_file *m)
381 for_each_online_cpu(i) {
383 "Cpu%dBogo\t: %lu.%02lu\n",
385 cpu_data(i).udelay_val/(500000/HZ),
386 (cpu_data(i).udelay_val/(5000/HZ))%100);
390 void smp_info(struct seq_file *m)
394 seq_printf(m, "State:\n");
395 for_each_online_cpu(i)
396 seq_printf(m, "CPU%d\t\t: online\n", i);