drivers/gpu/drm/panfrost/panfrost_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright 2018 Marty E. Plummer <[email protected]> */
   3 /* Copyright 2019 Linaro, Ltd., Rob Herring <[email protected]> */
   4 /* Copyright 2019 Collabora ltd. */
   5 #include <linux/bitfield.h>
   6 #include <linux/bitmap.h>
   7 #include <linux/delay.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/platform_device.h>
  13
  14 #include "panfrost_device.h"
  15 #include "panfrost_features.h"
  16 #include "panfrost_issues.h"
  17 #include "panfrost_gpu.h"
  18 #include "panfrost_regs.h"
  19
  20 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
  21 #define gpu_read(dev, reg) readl(dev->iomem + reg)
  22
  23 static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data)
  24 {
  25         struct panfrost_device *pfdev = data;
  26         u32 state = gpu_read(pfdev, GPU_INT_STAT);
  27         u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS);
  28
  29         if (!state)
  30                 return IRQ_NONE;
  31
  32         if (state & GPU_IRQ_MASK_ERROR) {
  33                 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32;
  34                 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO);
  35
  36                 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
  37                          fault_status & 0xFF, panfrost_exception_name(pfdev, fault_status),
  38                          address);
  39
  40                 if (state & GPU_IRQ_MULTIPLE_FAULT)
  41                         dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n");
  42
  43                 gpu_write(pfdev, GPU_INT_MASK, 0);
  44         }
  45
  46         gpu_write(pfdev, GPU_INT_CLEAR, state);
  47
  48         return IRQ_HANDLED;
  49 }
  50
  51 int panfrost_gpu_soft_reset(struct panfrost_device *pfdev)
  52 {
  53         int ret;
  54         u32 val;
  55
  56         gpu_write(pfdev, GPU_INT_MASK, 0);
  57         gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
  58         gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET);
  59
  60         ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,
  61                 val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000);
  62
  63         if (ret) {
  64                 dev_err(pfdev->dev, "gpu soft reset timed out\n");
  65                 return ret;
  66         }
  67
  68         gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL);
  69         gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL);
  70
  71         return 0;
  72 }
  73
  74 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
  75 {
  76         u32 quirks = 0;
  77
  78         if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) ||
  79             panfrost_has_hw_issue(pfdev, HW_ISSUE_11035))
  80                 quirks |= SC_LS_PAUSEBUFFER_DISABLE;
  81
  82         if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327))
  83                 quirks |= SC_SDC_DISABLE_OQ_DISCARD;
  84
  85         if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797))
  86                 quirks |= SC_ENABLE_TEXGRD_FLAGS;
  87
  88         if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) {
  89                 if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */
  90                         quirks |= SC_LS_ATTR_CHECK_DISABLE;
  91                 else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */
  92                         quirks |= SC_LS_ALLOW_ATTR_TYPES;
  93         }
  94
  95         if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
  96                 quirks |= SC_TLS_HASH_ENABLE;
  97
  98         if (quirks)
  99                 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks);
 100
 101
 102         quirks = gpu_read(pfdev, GPU_TILER_CONFIG);
 103
 104         /* Set tiler clock gate override if required */
 105         if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953))
 106                 quirks |= TC_CLOCK_GATE_OVERRIDE;
 107
 108         gpu_write(pfdev, GPU_TILER_CONFIG, quirks);
 109
 110
 111         quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG);
 112
 113         /* Limit read & write ID width for AXI */
 114         if (panfrost_has_hw_feature(pfdev, HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG))
 115                 quirks &= ~(L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS |
 116                             L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES);
 117         else
 118                 quirks &= ~(L2_MMU_CONFIG_LIMIT_EXTERNAL_READS |
 119                             L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES);
 120
 121         gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks);
 122
 123         quirks = 0;
 124         if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) &&
 125             pfdev->features.revision >= 0x2000)
 126                 quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;
 127         else if (panfrost_model_eq(pfdev, 0x6000) &&
 128                  pfdev->features.coherency_features == COHERENCY_ACE)
 129                 quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) <<
 130                            JM_FORCE_COHERENCY_FEATURES_SHIFT;
 131
 132         if (quirks)
 133                 gpu_write(pfdev, GPU_JM_CONFIG, quirks);
 134 }
 135
 136 #define MAX_HW_REVS 6
 137
 138 struct panfrost_model {
 139         const char *name;
 140         u32 id;
 141         u32 id_mask;
 142         u64 features;
 143         u64 issues;
 144         struct {
 145                 u32 revision;
 146                 u64 issues;
 147         } revs[MAX_HW_REVS];
 148 };
 149
 150 #define GPU_MODEL(_name, _id, ...) \
 151 {\
 152         .name = __stringify(_name),                             \
 153         .id = _id,                                              \
 154         .features = hw_features_##_name,                        \
 155         .issues = hw_issues_##_name,                            \
 156         .revs = { __VA_ARGS__ },                                \
 157 }
 158
 159 #define GPU_REV_EXT(name, _rev, _p, _s, stat) \
 160 {\
 161         .revision = (_rev) << 12 | (_p) << 4 | (_s),            \
 162         .issues = hw_issues_##name##_r##_rev##p##_p##stat,      \
 163 }
 164 #define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, )
 165
 166 static const struct panfrost_model gpu_models[] = {
 167         /* T60x has an oddball version */
 168         GPU_MODEL(t600, 0x600,
 169                 GPU_REV_EXT(t600, 0, 0, 1, _15dev0)),
 170         GPU_MODEL(t620, 0x620,
 171                 GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)),
 172         GPU_MODEL(t720, 0x720),
 173         GPU_MODEL(t760, 0x750,
 174                 GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1),
 175                 GPU_REV_EXT(t760, 0, 1, 0, _50rel0),
 176                 GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)),
 177         GPU_MODEL(t820, 0x820),
 178         GPU_MODEL(t830, 0x830),
 179         GPU_MODEL(t860, 0x860),
 180         GPU_MODEL(t880, 0x880),
 181
 182         GPU_MODEL(g71, 0x6000,
 183                 GPU_REV_EXT(g71, 0, 0, 1, _05dev0)),
 184         GPU_MODEL(g72, 0x6001),
 185         GPU_MODEL(g51, 0x7000),
 186         GPU_MODEL(g76, 0x7001),
 187         GPU_MODEL(g52, 0x7002),
 188         GPU_MODEL(g31, 0x7003,
 189                 GPU_REV(g31, 1, 0)),
 190 };
 191
 192 static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
 193 {
 194         u32 gpu_id, num_js, major, minor, status, rev;
 195         const char *name = "unknown";
 196         u64 hw_feat = 0;
 197         u64 hw_issues = hw_issues_all;
 198         const struct panfrost_model *model;
 199         int i;
 200
 201         pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
 202         pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES);
 203         pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES);
 204         pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES);
 205         pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES);
 206         pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES);
 207         pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
 208         for (i = 0; i < 4; i++)
 209                 pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));
 210
 211         pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT);
 212
 213         pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT);
 214         num_js = hweight32(pfdev->features.js_present);
 215         for (i = 0; i < num_js; i++)
 216                 pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i));
 217
 218         pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO);
 219         pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32;
 220
 221         pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO);
 222         pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32;
 223
 224         pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO);
 225         pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32;
 226         pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present);
 227
 228         pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO);
 229         pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32;
 230
 231         gpu_id = gpu_read(pfdev, GPU_ID);
 232         pfdev->features.revision = gpu_id & 0xffff;
 233         pfdev->features.id = gpu_id >> 16;
 234
 235         /* The T60x has an oddball ID value. Fix it up to the standard Midgard
 236          * format so we (and userspace) don't have to special case it.
 237          */
 238         if (pfdev->features.id == 0x6956)
 239                 pfdev->features.id = 0x0600;
 240
 241         major = (pfdev->features.revision >> 12) & 0xf;
 242         minor = (pfdev->features.revision >> 4) & 0xff;
 243         status = pfdev->features.revision & 0xf;
 244         rev = pfdev->features.revision;
 245
 246         gpu_id = pfdev->features.id;
 247
 248         for (model = gpu_models; model->name; model++) {
 249                 int best = -1;
 250
 251                 if (!panfrost_model_eq(pfdev, model->id))
 252                         continue;
 253
 254                 name = model->name;
 255                 hw_feat = model->features;
 256                 hw_issues |= model->issues;
 257                 for (i = 0; i < MAX_HW_REVS; i++) {
 258                         if (model->revs[i].revision == rev) {
 259                                 best = i;
 260                                 break;
 261                         } else if (model->revs[i].revision == (rev & ~0xf))
 262                                 best = i;
 263                 }
 264
 265                 if (best >= 0)
 266                         hw_issues |= model->revs[best].issues;
 267
 268                 break;
 269         }
 270
 271         bitmap_from_u64(pfdev->features.hw_features, hw_feat);
 272         bitmap_from_u64(pfdev->features.hw_issues, hw_issues);
 273
 274         dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
 275                  name, gpu_id, major, minor, status);
 276         dev_info(pfdev->dev, "features: %64pb, issues: %64pb",
 277                  pfdev->features.hw_features,
 278                  pfdev->features.hw_issues);
 279
 280         dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x",
 281                  pfdev->features.l2_features,
 282                  pfdev->features.core_features,
 283                  pfdev->features.tiler_features,
 284                  pfdev->features.mem_features,
 285                  pfdev->features.mmu_features,
 286                  pfdev->features.as_present,
 287                  pfdev->features.js_present);
 288
 289         dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx",
 290                  pfdev->features.shader_present, pfdev->features.l2_present);
 291 }
 292
 293 void panfrost_gpu_power_on(struct panfrost_device *pfdev)
 294 {
 295         int ret;
 296         u32 val;
 297
 298         /* Just turn on everything for now */
 299         gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present);
 300         ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
 301                 val, val == pfdev->features.l2_present, 100, 1000);
 302
 303         gpu_write(pfdev, STACK_PWRON_LO, pfdev->features.stack_present);
 304         ret |= readl_relaxed_poll_timeout(pfdev->iomem + STACK_READY_LO,
 305                 val, val == pfdev->features.stack_present, 100, 1000);
 306
 307         gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present);
 308         ret |= readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
 309                 val, val == pfdev->features.shader_present, 100, 1000);
 310
 311         gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
 312         ret |= readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
 313                 val, val == pfdev->features.tiler_present, 100, 1000);
 314
 315         if (ret)
 316                 dev_err(pfdev->dev, "error powering up gpu");
 317 }
 318
 319 void panfrost_gpu_power_off(struct panfrost_device *pfdev)
 320 {
 321         gpu_write(pfdev, TILER_PWROFF_LO, 0);
 322         gpu_write(pfdev, SHADER_PWROFF_LO, 0);
 323         gpu_write(pfdev, STACK_PWROFF_LO, 0);
 324         gpu_write(pfdev, L2_PWROFF_LO, 0);
 325 }
 326
 327 int panfrost_gpu_init(struct panfrost_device *pfdev)
 328 {
 329         int err, irq;
 330
 331         err = panfrost_gpu_soft_reset(pfdev);
 332         if (err)
 333                 return err;
 334
 335         panfrost_gpu_init_features(pfdev);
 336
 337         dma_set_mask_and_coherent(pfdev->dev,
 338                 DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features)));
 339
 340         irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu");
 341         if (irq <= 0)
 342                 return -ENODEV;
 343
 344         err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler,
 345                                IRQF_SHARED, "gpu", pfdev);
 346         if (err) {
 347                 dev_err(pfdev->dev, "failed to request gpu irq");
 348                 return err;
 349         }
 350
 351         panfrost_gpu_init_quirks(pfdev);
 352         panfrost_gpu_power_on(pfdev);
 353
 354         return 0;
 355 }
 356
 357 void panfrost_gpu_fini(struct panfrost_device *pfdev)
 358 {
 359         panfrost_gpu_power_off(pfdev);
 360 }
 361
 362 u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev)
 363 {
 364         if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION))
 365                 return gpu_read(pfdev, GPU_LATEST_FLUSH_ID);
 366         return 0;
 367 }