drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "amdgpu_rlc.h"
  29 #include "amdgpu_ras.h"
  30
  31 /* delay 0.1 second to enable gfx off feature */
  32 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  33
  34 /*
  35  * GPU GFX IP block helpers function.
  36  */
  37
  38 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  39                                 int pipe, int queue)
  40 {
  41         int bit = 0;
  42
  43         bit += mec * adev->gfx.mec.num_pipe_per_mec
  44                 * adev->gfx.mec.num_queue_per_pipe;
  45         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  46         bit += queue;
  47
  48         return bit;
  49 }
  50
  51 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  52                                  int *mec, int *pipe, int *queue)
  53 {
  54         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  55         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  56                 % adev->gfx.mec.num_pipe_per_mec;
  57         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  58                / adev->gfx.mec.num_pipe_per_mec;
  59
  60 }
  61
  62 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  63                                      int mec, int pipe, int queue)
  64 {
  65         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  66                         adev->gfx.mec.queue_bitmap);
  67 }
  68
  69 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  70                                int me, int pipe, int queue)
  71 {
  72         int bit = 0;
  73
  74         bit += me * adev->gfx.me.num_pipe_per_me
  75                 * adev->gfx.me.num_queue_per_pipe;
  76         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  77         bit += queue;
  78
  79         return bit;
  80 }
  81
  82 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  83                                 int *me, int *pipe, int *queue)
  84 {
  85         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  86         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  87                 % adev->gfx.me.num_pipe_per_me;
  88         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  89                 / adev->gfx.me.num_pipe_per_me;
  90 }
  91
  92 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  93                                     int me, int pipe, int queue)
  94 {
  95         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
  96                         adev->gfx.me.queue_bitmap);
  97 }
  98
  99 /**
 100  * amdgpu_gfx_scratch_get - Allocate a scratch register
 101  *
 102  * @adev: amdgpu_device pointer
 103  * @reg: scratch register mmio offset
 104  *
 105  * Allocate a CP scratch register for use by the driver (all asics).
 106  * Returns 0 on success or -EINVAL on failure.
 107  */
 108 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
 109 {
 110         int i;
 111
 112         i = ffs(adev->gfx.scratch.free_mask);
 113         if (i != 0 && i <= adev->gfx.scratch.num_reg) {
 114                 i--;
 115                 adev->gfx.scratch.free_mask &= ~(1u << i);
 116                 *reg = adev->gfx.scratch.reg_base + i;
 117                 return 0;
 118         }
 119         return -EINVAL;
 120 }
 121
 122 /**
 123  * amdgpu_gfx_scratch_free - Free a scratch register
 124  *
 125  * @adev: amdgpu_device pointer
 126  * @reg: scratch register mmio offset
 127  *
 128  * Free a CP scratch register allocated for use by the driver (all asics)
 129  */
 130 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
 131 {
 132         adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
 133 }
 134
 135 /**
 136  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 137  *
 138  * @mask: array in which the per-shader array disable masks will be stored
 139  * @max_se: number of SEs
 140  * @max_sh: number of SHs
 141  *
 142  * The bitmask of CUs to be disabled in the shader array determined by se and
 143  * sh is stored in mask[se * max_sh + sh].
 144  */
 145 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 146 {
 147         unsigned se, sh, cu;
 148         const char *p;
 149
 150         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 151
 152         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 153                 return;
 154
 155         p = amdgpu_disable_cu;
 156         for (;;) {
 157                 char *next;
 158                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 159                 if (ret < 3) {
 160                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 161                         return;
 162                 }
 163
 164                 if (se < max_se && sh < max_sh && cu < 16) {
 165                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 166                         mask[se * max_sh + sh] |= 1u << cu;
 167                 } else {
 168                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 169                                   se, sh, cu);
 170                 }
 171
 172                 next = strchr(p, ',');
 173                 if (!next)
 174                         break;
 175                 p = next + 1;
 176         }
 177 }
 178
 179 static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
 180 {
 181         if (amdgpu_compute_multipipe != -1) {
 182                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 183                          amdgpu_compute_multipipe);
 184                 return amdgpu_compute_multipipe == 1;
 185         }
 186
 187         /* FIXME: spreading the queues across pipes causes perf regressions
 188          * on POLARIS11 compute workloads */
 189         if (adev->asic_type == CHIP_POLARIS11)
 190                 return false;
 191
 192         return adev->gfx.mec.num_mec > 1;
 193 }
 194
 195 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 196                                                int queue)
 197 {
 198         /* Policy: make queue 0 of each pipe as high priority compute queue */
 199         return (queue == 0);
 200
 201 }
 202
 203 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 204 {
 205         int i, queue, pipe;
 206         bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
 207         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 208                                      adev->gfx.mec.num_queue_per_pipe,
 209                                      adev->gfx.num_compute_rings);
 210
 211         if (multipipe_policy) {
 212                 /* policy: make queues evenly cross all pipes on MEC1 only */
 213                 for (i = 0; i < max_queues_per_mec; i++) {
 214                         pipe = i % adev->gfx.mec.num_pipe_per_mec;
 215                         queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 216                                 adev->gfx.mec.num_queue_per_pipe;
 217
 218                         set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 219                                         adev->gfx.mec.queue_bitmap);
 220                 }
 221         } else {
 222                 /* policy: amdgpu owns all queues in the given pipe */
 223                 for (i = 0; i < max_queues_per_mec; ++i)
 224                         set_bit(i, adev->gfx.mec.queue_bitmap);
 225         }
 226
 227         dev_dbg(adev->dev, "mec queue bitmap weight=%d\n", bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 228 }
 229
 230 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 231 {
 232         int i, queue, me;
 233
 234         for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
 235                 queue = i % adev->gfx.me.num_queue_per_pipe;
 236                 me = (i / adev->gfx.me.num_queue_per_pipe)
 237                       / adev->gfx.me.num_pipe_per_me;
 238
 239                 if (me >= adev->gfx.me.num_me)
 240                         break;
 241                 /* policy: amdgpu owns the first queue per pipe at this stage
 242                  * will extend to mulitple queues per pipe later */
 243                 if (me == 0 && queue < 1)
 244                         set_bit(i, adev->gfx.me.queue_bitmap);
 245         }
 246
 247         /* update the number of active graphics rings */
 248         adev->gfx.num_gfx_rings =
 249                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 250 }
 251
 252 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 253                                   struct amdgpu_ring *ring)
 254 {
 255         int queue_bit;
 256         int mec, pipe, queue;
 257
 258         queue_bit = adev->gfx.mec.num_mec
 259                     * adev->gfx.mec.num_pipe_per_mec
 260                     * adev->gfx.mec.num_queue_per_pipe;
 261
 262         while (queue_bit-- >= 0) {
 263                 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
 264                         continue;
 265
 266                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 267
 268                 /*
 269                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 270                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 271                  * only can be issued on queue 0.
 272                  */
 273                 if ((mec == 1 && pipe > 1) || queue != 0)
 274                         continue;
 275
 276                 ring->me = mec + 1;
 277                 ring->pipe = pipe;
 278                 ring->queue = queue;
 279
 280                 return 0;
 281         }
 282
 283         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 284         return -EINVAL;
 285 }
 286
 287 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 288                              struct amdgpu_ring *ring,
 289                              struct amdgpu_irq_src *irq)
 290 {
 291         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 292         int r = 0;
 293
 294         spin_lock_init(&kiq->ring_lock);
 295
 296         ring->adev = NULL;
 297         ring->ring_obj = NULL;
 298         ring->use_doorbell = true;
 299         ring->doorbell_index = adev->doorbell_index.kiq;
 300
 301         r = amdgpu_gfx_kiq_acquire(adev, ring);
 302         if (r)
 303                 return r;
 304
 305         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 306         ring->no_scheduler = true;
 307         sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 308         r = amdgpu_ring_init(adev, ring, 1024,
 309                              irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 310                              AMDGPU_RING_PRIO_DEFAULT);
 311         if (r)
 312                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 313
 314         return r;
 315 }
 316
 317 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 318 {
 319         amdgpu_ring_fini(ring);
 320 }
 321
 322 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
 323 {
 324         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 325
 326         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 327 }
 328
 329 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 330                         unsigned hpd_size)
 331 {
 332         int r;
 333         u32 *hpd;
 334         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 335
 336         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 337                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 338                                     &kiq->eop_gpu_addr, (void **)&hpd);
 339         if (r) {
 340                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 341                 return r;
 342         }
 343
 344         memset(hpd, 0, hpd_size);
 345
 346         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 347         if (unlikely(r != 0))
 348                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 349         amdgpu_bo_kunmap(kiq->eop_obj);
 350         amdgpu_bo_unreserve(kiq->eop_obj);
 351
 352         return 0;
 353 }
 354
 355 /* create MQD for each compute/gfx queue */
 356 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 357                            unsigned mqd_size)
 358 {
 359         struct amdgpu_ring *ring = NULL;
 360         int r, i;
 361
 362         /* create MQD for KIQ */
 363         ring = &adev->gfx.kiq.ring;
 364         if (!ring->mqd_obj) {
 365                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 366                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 367                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 368                  * KIQ MQD no matter SRIOV or Bare-metal
 369                  */
 370                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 371                                             AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
 372                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 373                 if (r) {
 374                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 375                         return r;
 376                 }
 377
 378                 /* prepare MQD backup */
 379                 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
 380                 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
 381                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 382         }
 383
 384         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 385                 /* create MQD for each KGQ */
 386                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 387                         ring = &adev->gfx.gfx_ring[i];
 388                         if (!ring->mqd_obj) {
 389                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 390                                                             AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 391                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 392                                 if (r) {
 393                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 394                                         return r;
 395                                 }
 396
 397                                 /* prepare MQD backup */
 398                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 399                                 if (!adev->gfx.me.mqd_backup[i])
 400                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 401                         }
 402                 }
 403         }
 404
 405         /* create MQD for each KCQ */
 406         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 407                 ring = &adev->gfx.compute_ring[i];
 408                 if (!ring->mqd_obj) {
 409                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 410                                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 411                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 412                         if (r) {
 413                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 414                                 return r;
 415                         }
 416
 417                         /* prepare MQD backup */
 418                         adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 419                         if (!adev->gfx.mec.mqd_backup[i])
 420                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 421                 }
 422         }
 423
 424         return 0;
 425 }
 426
 427 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
 428 {
 429         struct amdgpu_ring *ring = NULL;
 430         int i;
 431
 432         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 433                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 434                         ring = &adev->gfx.gfx_ring[i];
 435                         kfree(adev->gfx.me.mqd_backup[i]);
 436                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 437                                               &ring->mqd_gpu_addr,
 438                                               &ring->mqd_ptr);
 439                 }
 440         }
 441
 442         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 443                 ring = &adev->gfx.compute_ring[i];
 444                 kfree(adev->gfx.mec.mqd_backup[i]);
 445                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 446                                       &ring->mqd_gpu_addr,
 447                                       &ring->mqd_ptr);
 448         }
 449
 450         ring = &adev->gfx.kiq.ring;
 451         kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
 452         amdgpu_bo_free_kernel(&ring->mqd_obj,
 453                               &ring->mqd_gpu_addr,
 454                               &ring->mqd_ptr);
 455 }
 456
 457 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
 458 {
 459         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 460         struct amdgpu_ring *kiq_ring = &kiq->ring;
 461         int i;
 462
 463         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 464                 return -EINVAL;
 465
 466         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 467                                         adev->gfx.num_compute_rings))
 468                 return -ENOMEM;
 469
 470         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 471                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
 472                                            RESET_QUEUES, 0, 0);
 473
 474         return amdgpu_ring_test_helper(kiq_ring);
 475 }
 476
 477 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 478                                         int queue_bit)
 479 {
 480         int mec, pipe, queue;
 481         int set_resource_bit = 0;
 482
 483         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 484
 485         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 486
 487         return set_resource_bit;
 488 }
 489
 490 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
 491 {
 492         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 493         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
 494         uint64_t queue_mask = 0;
 495         int r, i;
 496
 497         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 498                 return -EINVAL;
 499
 500         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 501                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
 502                         continue;
 503
 504                 /* This situation may be hit in the future if a new HW
 505                  * generation exposes more than 64 queues. If so, the
 506                  * definition of queue_mask needs updating */
 507                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 508                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 509                         break;
 510                 }
 511
 512                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 513         }
 514
 515         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 516                                                         kiq_ring->queue);
 517
 518         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 519                                         adev->gfx.num_compute_rings +
 520                                         kiq->pmf->set_resources_size);
 521         if (r) {
 522                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 523                 return r;
 524         }
 525
 526         kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 527         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 528                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]);
 529
 530         r = amdgpu_ring_test_helper(kiq_ring);
 531         if (r)
 532                 DRM_ERROR("KCQ enable failed\n");
 533
 534         return r;
 535 }
 536
 537 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 538  *
 539  * @adev: amdgpu_device pointer
 540  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 541  *
 542  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 543  * 2. other client can send request to disable gfx off feature, the request should be honored.
 544  * 3. other client can cancel their request of disable gfx off feature
 545  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 546  */
 547
 548 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 549 {
 550         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 551                 return;
 552
 553         mutex_lock(&adev->gfx.gfx_off_mutex);
 554
 555         if (!enable)
 556                 adev->gfx.gfx_off_req_count++;
 557         else if (adev->gfx.gfx_off_req_count > 0)
 558                 adev->gfx.gfx_off_req_count--;
 559
 560         if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
 561                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);
 562         } else if (!enable && adev->gfx.gfx_off_state) {
 563                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 564                         adev->gfx.gfx_off_state = false;
 565
 566                         if (adev->gfx.funcs->init_spm_golden) {
 567                                 dev_dbg(adev->dev, "GFXOFF is disabled, re-init SPM golden settings\n");
 568                                 amdgpu_gfx_init_spm_golden(adev);
 569                         }
 570                 }
 571         }
 572
 573         mutex_unlock(&adev->gfx.gfx_off_mutex);
 574 }
 575
 576 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 577 {
 578
 579         int r = 0;
 580
 581         mutex_lock(&adev->gfx.gfx_off_mutex);
 582
 583         r = smu_get_status_gfxoff(adev, value);
 584
 585         mutex_unlock(&adev->gfx.gfx_off_mutex);
 586
 587         return r;
 588 }
 589
 590 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
 591 {
 592         int r;
 593         struct ras_fs_if fs_info = {
 594                 .sysfs_name = "gfx_err_count",
 595         };
 596         struct ras_ih_if ih_info = {
 597                 .cb = amdgpu_gfx_process_ras_data_cb,
 598         };
 599
 600         if (!adev->gfx.ras_if) {
 601                 adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
 602                 if (!adev->gfx.ras_if)
 603                         return -ENOMEM;
 604                 adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
 605                 adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 606                 adev->gfx.ras_if->sub_block_index = 0;
 607                 strcpy(adev->gfx.ras_if->name, "gfx");
 608         }
 609         fs_info.head = ih_info.head = *adev->gfx.ras_if;
 610
 611         r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
 612                                  &fs_info, &ih_info);
 613         if (r)
 614                 goto free;
 615
 616         if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
 617                 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 618                 if (r)
 619                         goto late_fini;
 620         } else {
 621                 /* free gfx ras_if if ras is not supported */
 622                 r = 0;
 623                 goto free;
 624         }
 625
 626         return 0;
 627 late_fini:
 628         amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
 629 free:
 630         kfree(adev->gfx.ras_if);
 631         adev->gfx.ras_if = NULL;
 632         return r;
 633 }
 634
 635 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
 636 {
 637         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
 638                         adev->gfx.ras_if) {
 639                 struct ras_common_if *ras_if = adev->gfx.ras_if;
 640                 struct ras_ih_if ih_info = {
 641                         .head = *ras_if,
 642                         .cb = amdgpu_gfx_process_ras_data_cb,
 643                 };
 644
 645                 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
 646                 kfree(ras_if);
 647         }
 648 }
 649
 650 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 651                 void *err_data,
 652                 struct amdgpu_iv_entry *entry)
 653 {
 654         /* TODO ue will trigger an interrupt.
 655          *
 656          * When “Full RAS” is enabled, the per-IP interrupt sources should
 657          * be disabled and the driver should only look for the aggregated
 658          * interrupt via sync flood
 659          */
 660         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 661                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 662                 if (adev->gfx.funcs->query_ras_error_count)
 663                         adev->gfx.funcs->query_ras_error_count(adev, err_data);
 664                 amdgpu_ras_reset_gpu(adev);
 665         }
 666         return AMDGPU_RAS_SUCCESS;
 667 }
 668
 669 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 670                                   struct amdgpu_irq_src *source,
 671                                   struct amdgpu_iv_entry *entry)
 672 {
 673         struct ras_common_if *ras_if = adev->gfx.ras_if;
 674         struct ras_dispatch_if ih_data = {
 675                 .entry = entry,
 676         };
 677
 678         if (!ras_if)
 679                 return 0;
 680
 681         ih_data.head = *ras_if;
 682
 683         DRM_ERROR("CP ECC ERROR IRQ\n");
 684         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 685         return 0;
 686 }
 687
 688 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 689 {
 690         signed long r, cnt = 0;
 691         unsigned long flags;
 692         uint32_t seq, reg_val_offs = 0, value = 0;
 693         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 694         struct amdgpu_ring *ring = &kiq->ring;
 695
 696         if (adev->in_pci_err_recovery)
 697                 return 0;
 698
 699         BUG_ON(!ring->funcs->emit_rreg);
 700
 701         spin_lock_irqsave(&kiq->ring_lock, flags);
 702         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 703                 pr_err("critical bug! too many kiq readers\n");
 704                 goto failed_unlock;
 705         }
 706         amdgpu_ring_alloc(ring, 32);
 707         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 708         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 709         if (r)
 710                 goto failed_undo;
 711
 712         amdgpu_ring_commit(ring);
 713         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 714
 715         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 716
 717         /* don't wait anymore for gpu reset case because this way may
 718          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 719          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 720          * never return if we keep waiting in virt_kiq_rreg, which cause
 721          * gpu_recover() hang there.
 722          *
 723          * also don't wait anymore for IRQ context
 724          * */
 725         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 726                 goto failed_kiq_read;
 727
 728         might_sleep();
 729         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 730                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 731                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 732         }
 733
 734         if (cnt > MAX_KIQ_REG_TRY)
 735                 goto failed_kiq_read;
 736
 737         mb();
 738         value = adev->wb.wb[reg_val_offs];
 739         amdgpu_device_wb_free(adev, reg_val_offs);
 740         return value;
 741
 742 failed_undo:
 743         amdgpu_ring_undo(ring);
 744 failed_unlock:
 745         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 746 failed_kiq_read:
 747         if (reg_val_offs)
 748                 amdgpu_device_wb_free(adev, reg_val_offs);
 749         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 750         return ~0;
 751 }
 752
 753 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 754 {
 755         signed long r, cnt = 0;
 756         unsigned long flags;
 757         uint32_t seq;
 758         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 759         struct amdgpu_ring *ring = &kiq->ring;
 760
 761         BUG_ON(!ring->funcs->emit_wreg);
 762
 763         if (adev->in_pci_err_recovery)
 764                 return;
 765
 766         spin_lock_irqsave(&kiq->ring_lock, flags);
 767         amdgpu_ring_alloc(ring, 32);
 768         amdgpu_ring_emit_wreg(ring, reg, v);
 769         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 770         if (r)
 771                 goto failed_undo;
 772
 773         amdgpu_ring_commit(ring);
 774         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 775
 776         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 777
 778         /* don't wait anymore for gpu reset case because this way may
 779          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 780          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 781          * never return if we keep waiting in virt_kiq_rreg, which cause
 782          * gpu_recover() hang there.
 783          *
 784          * also don't wait anymore for IRQ context
 785          * */
 786         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 787                 goto failed_kiq_write;
 788
 789         might_sleep();
 790         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 791
 792                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 793                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 794         }
 795
 796         if (cnt > MAX_KIQ_REG_TRY)
 797                 goto failed_kiq_write;
 798
 799         return;
 800
 801 failed_undo:
 802         amdgpu_ring_undo(ring);
 803         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 804 failed_kiq_write:
 805         dev_err(adev->dev, "failed to write reg:%x\n", reg);
 806 }