drivers/gpu/drm/sun4i/sun4i_backend.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_fb_cma_helper.h>
  18 #include <drm/drm_gem_cma_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_probe_helper.h>
  21
  22 #include <linux/component.h>
  23 #include <linux/list.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_graph.h>
  26 #include <linux/reset.h>
  27
  28 #include "sun4i_backend.h"
  29 #include "sun4i_drv.h"
  30 #include "sun4i_frontend.h"
  31 #include "sun4i_layer.h"
  32 #include "sunxi_engine.h"
  33
  34 struct sun4i_backend_quirks {
  35         /* backend <-> TCON muxing selection done in backend */
  36         bool needs_output_muxing;
  37
  38         /* alpha at the lowest z position is not always supported */
  39         bool supports_lowest_plane_alpha;
  40 };
  41
  42 static const u32 sunxi_rgb2yuv_coef[12] = {
  43         0x00000107, 0x00000204, 0x00000064, 0x00000108,
  44         0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  45         0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  46 };
  47
  48 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
  49 {
  50         int i;
  51
  52         DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
  53
  54         /* Set color correction */
  55         regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
  56                      SUN4I_BACKEND_OCCTL_ENABLE);
  57
  58         for (i = 0; i < 12; i++)
  59                 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
  60                              sunxi_rgb2yuv_coef[i]);
  61 }
  62
  63 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
  64 {
  65         DRM_DEBUG_DRIVER("Disabling color correction\n");
  66
  67         /* Disable color correction */
  68         regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
  69                            SUN4I_BACKEND_OCCTL_ENABLE, 0);
  70 }
  71
  72 static void sun4i_backend_commit(struct sunxi_engine *engine)
  73 {
  74         DRM_DEBUG_DRIVER("Committing changes\n");
  75
  76         regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
  77                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
  78                      SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
  79 }
  80
  81 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
  82                                 int layer, bool enable)
  83 {
  84         u32 val;
  85
  86         DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
  87                          layer);
  88
  89         if (enable)
  90                 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
  91         else
  92                 val = 0;
  93
  94         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
  95                            SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
  96 }
  97
  98 static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode)
  99 {
 100         switch (format) {
 101         case DRM_FORMAT_ARGB8888:
 102                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
 103                 break;
 104
 105         case DRM_FORMAT_ARGB4444:
 106                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
 107                 break;
 108
 109         case DRM_FORMAT_ARGB1555:
 110                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
 111                 break;
 112
 113         case DRM_FORMAT_RGBA5551:
 114                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
 115                 break;
 116
 117         case DRM_FORMAT_RGBA4444:
 118                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
 119                 break;
 120
 121         case DRM_FORMAT_XRGB8888:
 122                 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
 123                 break;
 124
 125         case DRM_FORMAT_RGB888:
 126                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
 127                 break;
 128
 129         case DRM_FORMAT_RGB565:
 130                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
 131                 break;
 132
 133         default:
 134                 return -EINVAL;
 135         }
 136
 137         return 0;
 138 }
 139
 140 static const uint32_t sun4i_backend_formats[] = {
 141         DRM_FORMAT_ARGB1555,
 142         DRM_FORMAT_ARGB4444,
 143         DRM_FORMAT_ARGB8888,
 144         DRM_FORMAT_RGB565,
 145         DRM_FORMAT_RGB888,
 146         DRM_FORMAT_RGBA4444,
 147         DRM_FORMAT_RGBA5551,
 148         DRM_FORMAT_UYVY,
 149         DRM_FORMAT_VYUY,
 150         DRM_FORMAT_XRGB8888,
 151         DRM_FORMAT_YUYV,
 152         DRM_FORMAT_YVYU,
 153 };
 154
 155 bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier)
 156 {
 157         unsigned int i;
 158
 159         if (modifier != DRM_FORMAT_MOD_LINEAR)
 160                 return false;
 161
 162         for (i = 0; i < ARRAY_SIZE(sun4i_backend_formats); i++)
 163                 if (sun4i_backend_formats[i] == fmt)
 164                         return true;
 165
 166         return false;
 167 }
 168
 169 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
 170                                      int layer, struct drm_plane *plane)
 171 {
 172         struct drm_plane_state *state = plane->state;
 173
 174         DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
 175
 176         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 177                 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
 178                                  state->crtc_w, state->crtc_h);
 179                 regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG,
 180                              SUN4I_BACKEND_DISSIZE(state->crtc_w,
 181                                                    state->crtc_h));
 182         }
 183
 184         /* Set height and width */
 185         DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
 186                          state->crtc_w, state->crtc_h);
 187         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
 188                      SUN4I_BACKEND_LAYSIZE(state->crtc_w,
 189                                            state->crtc_h));
 190
 191         /* Set base coordinates */
 192         DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
 193                          state->crtc_x, state->crtc_y);
 194         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
 195                      SUN4I_BACKEND_LAYCOOR(state->crtc_x,
 196                                            state->crtc_y));
 197
 198         return 0;
 199 }
 200
 201 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
 202                                            int layer, struct drm_plane *plane)
 203 {
 204         struct drm_plane_state *state = plane->state;
 205         struct drm_framebuffer *fb = state->fb;
 206         const struct drm_format_info *format = fb->format;
 207         const uint32_t fmt = format->format;
 208         u32 val = SUN4I_BACKEND_IYUVCTL_EN;
 209         int i;
 210
 211         for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
 212                 regmap_write(backend->engine.regs,
 213                              SUN4I_BACKEND_YGCOEF_REG(i),
 214                              sunxi_bt601_yuv2rgb_coef[i]);
 215
 216         /*
 217          * We should do that only for a single plane, but the
 218          * framebuffer's atomic_check has our back on this.
 219          */
 220         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 221                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN,
 222                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN);
 223
 224         /* TODO: Add support for the multi-planar YUV formats */
 225         if (drm_format_info_is_yuv_packed(format) &&
 226             drm_format_info_is_yuv_sampling_422(format))
 227                 val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422;
 228         else
 229                 DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt);
 230
 231         /*
 232          * Allwinner seems to list the pixel sequence from right to left, while
 233          * DRM lists it from left to right.
 234          */
 235         switch (fmt) {
 236         case DRM_FORMAT_YUYV:
 237                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY;
 238                 break;
 239         case DRM_FORMAT_YVYU:
 240                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY;
 241                 break;
 242         case DRM_FORMAT_UYVY:
 243                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU;
 244                 break;
 245         case DRM_FORMAT_VYUY:
 246                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV;
 247                 break;
 248         default:
 249                 DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n",
 250                                  fmt);
 251         }
 252
 253         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
 254
 255         return 0;
 256 }
 257
 258 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
 259                                        int layer, struct drm_plane *plane)
 260 {
 261         struct drm_plane_state *state = plane->state;
 262         struct drm_framebuffer *fb = state->fb;
 263         bool interlaced = false;
 264         u32 val;
 265         int ret;
 266
 267         /* Clear the YUV mode */
 268         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 269                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
 270
 271         if (plane->state->crtc)
 272                 interlaced = plane->state->crtc->state->adjusted_mode.flags
 273                         & DRM_MODE_FLAG_INTERLACE;
 274
 275         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 276                            SUN4I_BACKEND_MODCTL_ITLMOD_EN,
 277                            interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
 278
 279         DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
 280                          interlaced ? "on" : "off");
 281
 282         val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8);
 283         if (state->alpha != DRM_BLEND_ALPHA_OPAQUE)
 284                 val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN;
 285         regmap_update_bits(backend->engine.regs,
 286                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 287                            SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK |
 288                            SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN,
 289                            val);
 290
 291         if (fb->format->is_yuv)
 292                 return sun4i_backend_update_yuv_format(backend, layer, plane);
 293
 294         ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val);
 295         if (ret) {
 296                 DRM_DEBUG_DRIVER("Invalid format\n");
 297                 return ret;
 298         }
 299
 300         regmap_update_bits(backend->engine.regs,
 301                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 302                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 303
 304         return 0;
 305 }
 306
 307 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
 308                                         int layer, uint32_t fmt)
 309 {
 310         u32 val;
 311         int ret;
 312
 313         ret = sun4i_backend_drm_format_to_layer(fmt, &val);
 314         if (ret) {
 315                 DRM_DEBUG_DRIVER("Invalid format\n");
 316                 return ret;
 317         }
 318
 319         regmap_update_bits(backend->engine.regs,
 320                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 321                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN,
 322                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN);
 323
 324         regmap_update_bits(backend->engine.regs,
 325                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 326                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 327
 328         return 0;
 329 }
 330
 331 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
 332                                            struct drm_framebuffer *fb,
 333                                            dma_addr_t paddr)
 334 {
 335         /* TODO: Add support for the multi-planar YUV formats */
 336         DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr);
 337         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
 338
 339         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 340         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
 341                      fb->pitches[0] * 8);
 342
 343         return 0;
 344 }
 345
 346 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 347                                       int layer, struct drm_plane *plane)
 348 {
 349         struct drm_plane_state *state = plane->state;
 350         struct drm_framebuffer *fb = state->fb;
 351         u32 lo_paddr, hi_paddr;
 352         dma_addr_t paddr;
 353
 354         /* Set the line width */
 355         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 356         regmap_write(backend->engine.regs,
 357                      SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
 358                      fb->pitches[0] * 8);
 359
 360         /* Get the start of the displayed memory */
 361         paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
 362         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 363
 364         /*
 365          * backend DMA accesses DRAM directly, bypassing the system
 366          * bus. As such, the address range is different and the buffer
 367          * address needs to be corrected.
 368          */
 369         paddr -= PHYS_OFFSET;
 370
 371         if (fb->format->is_yuv)
 372                 return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
 373
 374         /* Write the 32 lower bits of the address (in bits) */
 375         lo_paddr = paddr << 3;
 376         DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
 377         regmap_write(backend->engine.regs,
 378                      SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
 379                      lo_paddr);
 380
 381         /* And the upper bits */
 382         hi_paddr = paddr >> 29;
 383         DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
 384         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
 385                            SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
 386                            SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
 387
 388         return 0;
 389 }
 390
 391 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
 392                                     struct drm_plane *plane)
 393 {
 394         struct drm_plane_state *state = plane->state;
 395         struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state);
 396         unsigned int priority = state->normalized_zpos;
 397         unsigned int pipe = p_state->pipe;
 398
 399         DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n",
 400                          layer, priority, pipe);
 401         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 402                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK |
 403                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK,
 404                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) |
 405                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority));
 406
 407         return 0;
 408 }
 409
 410 void sun4i_backend_cleanup_layer(struct sun4i_backend *backend,
 411                                  int layer)
 412 {
 413         regmap_update_bits(backend->engine.regs,
 414                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 415                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN |
 416                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
 417 }
 418
 419 static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state)
 420 {
 421         u16 src_h = state->src_h >> 16;
 422         u16 src_w = state->src_w >> 16;
 423
 424         DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n",
 425                          src_w, src_h, state->crtc_w, state->crtc_h);
 426
 427         if ((state->crtc_h != src_h) || (state->crtc_w != src_w))
 428                 return true;
 429
 430         return false;
 431 }
 432
 433 static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state)
 434 {
 435         struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane);
 436         struct sun4i_backend *backend = layer->backend;
 437         uint32_t format = state->fb->format->format;
 438         uint64_t modifier = state->fb->modifier;
 439
 440         if (IS_ERR(backend->frontend))
 441                 return false;
 442
 443         if (!sun4i_frontend_format_is_supported(format, modifier))
 444                 return false;
 445
 446         if (!sun4i_backend_format_is_supported(format, modifier))
 447                 return true;
 448
 449         /*
 450          * TODO: The backend alone allows 2x and 4x integer scaling, including
 451          * support for an alpha component (which the frontend doesn't support).
 452          * Use the backend directly instead of the frontend in this case, with
 453          * another test to return false.
 454          */
 455
 456         if (sun4i_backend_plane_uses_scaler(state))
 457                 return true;
 458
 459         /*
 460          * Here the format is supported by both the frontend and the backend
 461          * and no frontend scaling is required, so use the backend directly.
 462          */
 463         return false;
 464 }
 465
 466 static bool sun4i_backend_plane_is_supported(struct drm_plane_state *state,
 467                                              bool *uses_frontend)
 468 {
 469         if (sun4i_backend_plane_uses_frontend(state)) {
 470                 *uses_frontend = true;
 471                 return true;
 472         }
 473
 474         *uses_frontend = false;
 475
 476         /* Scaling is not supported without the frontend. */
 477         if (sun4i_backend_plane_uses_scaler(state))
 478                 return false;
 479
 480         return true;
 481 }
 482
 483 static void sun4i_backend_atomic_begin(struct sunxi_engine *engine,
 484                                        struct drm_crtc_state *old_state)
 485 {
 486         u32 val;
 487
 488         WARN_ON(regmap_read_poll_timeout(engine->regs,
 489                                          SUN4I_BACKEND_REGBUFFCTL_REG,
 490                                          val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL),
 491                                          100, 50000));
 492 }
 493
 494 static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
 495                                       struct drm_crtc_state *crtc_state)
 496 {
 497         struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 };
 498         struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
 499         struct drm_atomic_state *state = crtc_state->state;
 500         struct drm_device *drm = state->dev;
 501         struct drm_plane *plane;
 502         unsigned int num_planes = 0;
 503         unsigned int num_alpha_planes = 0;
 504         unsigned int num_frontend_planes = 0;
 505         unsigned int num_alpha_planes_max = 1;
 506         unsigned int num_yuv_planes = 0;
 507         unsigned int current_pipe = 0;
 508         unsigned int i;
 509
 510         DRM_DEBUG_DRIVER("Starting checking our planes\n");
 511
 512         if (!crtc_state->planes_changed)
 513                 return 0;
 514
 515         drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) {
 516                 struct drm_plane_state *plane_state =
 517                         drm_atomic_get_plane_state(state, plane);
 518                 struct sun4i_layer_state *layer_state =
 519                         state_to_sun4i_layer_state(plane_state);
 520                 struct drm_framebuffer *fb = plane_state->fb;
 521                 struct drm_format_name_buf format_name;
 522
 523                 if (!sun4i_backend_plane_is_supported(plane_state,
 524                                                       &layer_state->uses_frontend))
 525                         return -EINVAL;
 526
 527                 if (layer_state->uses_frontend) {
 528                         DRM_DEBUG_DRIVER("Using the frontend for plane %d\n",
 529                                          plane->index);
 530                         num_frontend_planes++;
 531                 } else {
 532                         if (fb->format->is_yuv) {
 533                                 DRM_DEBUG_DRIVER("Plane FB format is YUV\n");
 534                                 num_yuv_planes++;
 535                         }
 536                 }
 537
 538                 DRM_DEBUG_DRIVER("Plane FB format is %s\n",
 539                                  drm_get_format_name(fb->format->format,
 540                                                      &format_name));
 541                 if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
 542                         num_alpha_planes++;
 543
 544                 DRM_DEBUG_DRIVER("Plane zpos is %d\n",
 545                                  plane_state->normalized_zpos);
 546
 547                 /* Sort our planes by Zpos */
 548                 plane_states[plane_state->normalized_zpos] = plane_state;
 549
 550                 num_planes++;
 551         }
 552
 553         /* All our planes were disabled, bail out */
 554         if (!num_planes)
 555                 return 0;
 556
 557         /*
 558          * The hardware is a bit unusual here.
 559          *
 560          * Even though it supports 4 layers, it does the composition
 561          * in two separate steps.
 562          *
 563          * The first one is assigning a layer to one of its two
 564          * pipes. If more that 1 layer is assigned to the same pipe,
 565          * and if pixels overlaps, the pipe will take the pixel from
 566          * the layer with the highest priority.
 567          *
 568          * The second step is the actual alpha blending, that takes
 569          * the two pipes as input, and uses the potential alpha
 570          * component to do the transparency between the two.
 571          *
 572          * This two-step scenario makes us unable to guarantee a
 573          * robust alpha blending between the 4 layers in all
 574          * situations, since this means that we need to have one layer
 575          * with alpha at the lowest position of our two pipes.
 576          *
 577          * However, we cannot even do that on every platform, since
 578          * the hardware has a bug where the lowest plane of the lowest
 579          * pipe (pipe 0, priority 0), if it has any alpha, will
 580          * discard the pixel data entirely and just display the pixels
 581          * in the background color (black by default).
 582          *
 583          * This means that on the affected platforms, we effectively
 584          * have only three valid configurations with alpha, all of
 585          * them with the alpha being on pipe1 with the lowest
 586          * position, which can be 1, 2 or 3 depending on the number of
 587          * planes and their zpos.
 588          */
 589
 590         /* For platforms that are not affected by the issue described above. */
 591         if (backend->quirks->supports_lowest_plane_alpha)
 592                 num_alpha_planes_max++;
 593
 594         if (num_alpha_planes > num_alpha_planes_max) {
 595                 DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n");
 596                 return -EINVAL;
 597         }
 598
 599         /* We can't have an alpha plane at the lowest position */
 600         if (!backend->quirks->supports_lowest_plane_alpha &&
 601             (plane_states[0]->fb->format->has_alpha ||
 602             (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE)))
 603                 return -EINVAL;
 604
 605         for (i = 1; i < num_planes; i++) {
 606                 struct drm_plane_state *p_state = plane_states[i];
 607                 struct drm_framebuffer *fb = p_state->fb;
 608                 struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state);
 609
 610                 /*
 611                  * The only alpha position is the lowest plane of the
 612                  * second pipe.
 613                  */
 614                 if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
 615                         current_pipe++;
 616
 617                 s_state->pipe = current_pipe;
 618         }
 619
 620         /* We can only have a single YUV plane at a time */
 621         if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) {
 622                 DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n");
 623                 return -EINVAL;
 624         }
 625
 626         if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) {
 627                 DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n");
 628                 return -EINVAL;
 629         }
 630
 631         DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n",
 632                          num_planes, num_alpha_planes, num_frontend_planes,
 633                          num_yuv_planes);
 634
 635         return 0;
 636 }
 637
 638 static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine)
 639 {
 640         struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
 641         struct sun4i_frontend *frontend = backend->frontend;
 642
 643         if (!frontend)
 644                 return;
 645
 646         /*
 647          * In a teardown scenario with the frontend involved, we have
 648          * to keep the frontend enabled until the next vblank, and
 649          * only then disable it.
 650          *
 651          * This is due to the fact that the backend will not take into
 652          * account the new configuration (with the plane that used to
 653          * be fed by the frontend now disabled) until we write to the
 654          * commit bit and the hardware fetches the new configuration
 655          * during the next vblank.
 656          *
 657          * So we keep the frontend around in order to prevent any
 658          * visual artifacts.
 659          */
 660         spin_lock(&backend->frontend_lock);
 661         if (backend->frontend_teardown) {
 662                 sun4i_frontend_exit(frontend);
 663                 backend->frontend_teardown = false;
 664         }
 665         spin_unlock(&backend->frontend_lock);
 666 };
 667
 668 static int sun4i_backend_init_sat(struct device *dev) {
 669         struct sun4i_backend *backend = dev_get_drvdata(dev);
 670         int ret;
 671
 672         backend->sat_reset = devm_reset_control_get(dev, "sat");
 673         if (IS_ERR(backend->sat_reset)) {
 674                 dev_err(dev, "Couldn't get the SAT reset line\n");
 675                 return PTR_ERR(backend->sat_reset);
 676         }
 677
 678         ret = reset_control_deassert(backend->sat_reset);
 679         if (ret) {
 680                 dev_err(dev, "Couldn't deassert the SAT reset line\n");
 681                 return ret;
 682         }
 683
 684         backend->sat_clk = devm_clk_get(dev, "sat");
 685         if (IS_ERR(backend->sat_clk)) {
 686                 dev_err(dev, "Couldn't get our SAT clock\n");
 687                 ret = PTR_ERR(backend->sat_clk);
 688                 goto err_assert_reset;
 689         }
 690
 691         ret = clk_prepare_enable(backend->sat_clk);
 692         if (ret) {
 693                 dev_err(dev, "Couldn't enable the SAT clock\n");
 694                 return ret;
 695         }
 696
 697         return 0;
 698
 699 err_assert_reset:
 700         reset_control_assert(backend->sat_reset);
 701         return ret;
 702 }
 703
 704 static int sun4i_backend_free_sat(struct device *dev) {
 705         struct sun4i_backend *backend = dev_get_drvdata(dev);
 706
 707         clk_disable_unprepare(backend->sat_clk);
 708         reset_control_assert(backend->sat_reset);
 709
 710         return 0;
 711 }
 712
 713 /*
 714  * The display backend can take video output from the display frontend, or
 715  * the display enhancement unit on the A80, as input for one it its layers.
 716  * This relationship within the display pipeline is encoded in the device
 717  * tree with of_graph, and we use it here to figure out which backend, if
 718  * there are 2 or more, we are currently probing. The number would be in
 719  * the "reg" property of the upstream output port endpoint.
 720  */
 721 static int sun4i_backend_of_get_id(struct device_node *node)
 722 {
 723         struct device_node *port, *ep;
 724         int ret = -EINVAL;
 725
 726         /* input is port 0 */
 727         port = of_graph_get_port_by_id(node, 0);
 728         if (!port)
 729                 return -EINVAL;
 730
 731         /* try finding an upstream endpoint */
 732         for_each_available_child_of_node(port, ep) {
 733                 struct device_node *remote;
 734                 u32 reg;
 735
 736                 remote = of_graph_get_remote_endpoint(ep);
 737                 if (!remote)
 738                         continue;
 739
 740                 ret = of_property_read_u32(remote, "reg", &reg);
 741                 if (ret)
 742                         continue;
 743
 744                 ret = reg;
 745         }
 746
 747         of_node_put(port);
 748
 749         return ret;
 750 }
 751
 752 /* TODO: This needs to take multiple pipelines into account */
 753 static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv,
 754                                                           struct device_node *node)
 755 {
 756         struct device_node *port, *ep, *remote;
 757         struct sun4i_frontend *frontend;
 758
 759         port = of_graph_get_port_by_id(node, 0);
 760         if (!port)
 761                 return ERR_PTR(-EINVAL);
 762
 763         for_each_available_child_of_node(port, ep) {
 764                 remote = of_graph_get_remote_port_parent(ep);
 765                 if (!remote)
 766                         continue;
 767                 of_node_put(remote);
 768
 769                 /* does this node match any registered engines? */
 770                 list_for_each_entry(frontend, &drv->frontend_list, list) {
 771                         if (remote == frontend->node) {
 772                                 of_node_put(port);
 773                                 of_node_put(ep);
 774                                 return frontend;
 775                         }
 776                 }
 777         }
 778         of_node_put(port);
 779         return ERR_PTR(-EINVAL);
 780 }
 781
 782 static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
 783         .atomic_begin                   = sun4i_backend_atomic_begin,
 784         .atomic_check                   = sun4i_backend_atomic_check,
 785         .commit                         = sun4i_backend_commit,
 786         .layers_init                    = sun4i_layers_init,
 787         .apply_color_correction         = sun4i_backend_apply_color_correction,
 788         .disable_color_correction       = sun4i_backend_disable_color_correction,
 789         .vblank_quirk                   = sun4i_backend_vblank_quirk,
 790 };
 791
 792 static struct regmap_config sun4i_backend_regmap_config = {
 793         .reg_bits       = 32,
 794         .val_bits       = 32,
 795         .reg_stride     = 4,
 796         .max_register   = 0x5800,
 797 };
 798
 799 static int sun4i_backend_bind(struct device *dev, struct device *master,
 800                               void *data)
 801 {
 802         struct platform_device *pdev = to_platform_device(dev);
 803         struct drm_device *drm = data;
 804         struct sun4i_drv *drv = drm->dev_private;
 805         struct sun4i_backend *backend;
 806         const struct sun4i_backend_quirks *quirks;
 807         struct resource *res;
 808         void __iomem *regs;
 809         int i, ret;
 810
 811         backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
 812         if (!backend)
 813                 return -ENOMEM;
 814         dev_set_drvdata(dev, backend);
 815         spin_lock_init(&backend->frontend_lock);
 816
 817         backend->engine.node = dev->of_node;
 818         backend->engine.ops = &sun4i_backend_engine_ops;
 819         backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
 820         if (backend->engine.id < 0)
 821                 return backend->engine.id;
 822
 823         backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
 824         if (IS_ERR(backend->frontend))
 825                 dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n");
 826
 827         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 828         regs = devm_ioremap_resource(dev, res);
 829         if (IS_ERR(regs))
 830                 return PTR_ERR(regs);
 831
 832         backend->reset = devm_reset_control_get(dev, NULL);
 833         if (IS_ERR(backend->reset)) {
 834                 dev_err(dev, "Couldn't get our reset line\n");
 835                 return PTR_ERR(backend->reset);
 836         }
 837
 838         ret = reset_control_deassert(backend->reset);
 839         if (ret) {
 840                 dev_err(dev, "Couldn't deassert our reset line\n");
 841                 return ret;
 842         }
 843
 844         backend->bus_clk = devm_clk_get(dev, "ahb");
 845         if (IS_ERR(backend->bus_clk)) {
 846                 dev_err(dev, "Couldn't get the backend bus clock\n");
 847                 ret = PTR_ERR(backend->bus_clk);
 848                 goto err_assert_reset;
 849         }
 850         clk_prepare_enable(backend->bus_clk);
 851
 852         backend->mod_clk = devm_clk_get(dev, "mod");
 853         if (IS_ERR(backend->mod_clk)) {
 854                 dev_err(dev, "Couldn't get the backend module clock\n");
 855                 ret = PTR_ERR(backend->mod_clk);
 856                 goto err_disable_bus_clk;
 857         }
 858         clk_prepare_enable(backend->mod_clk);
 859
 860         backend->ram_clk = devm_clk_get(dev, "ram");
 861         if (IS_ERR(backend->ram_clk)) {
 862                 dev_err(dev, "Couldn't get the backend RAM clock\n");
 863                 ret = PTR_ERR(backend->ram_clk);
 864                 goto err_disable_mod_clk;
 865         }
 866         clk_prepare_enable(backend->ram_clk);
 867
 868         if (of_device_is_compatible(dev->of_node,
 869                                     "allwinner,sun8i-a33-display-backend")) {
 870                 ret = sun4i_backend_init_sat(dev);
 871                 if (ret) {
 872                         dev_err(dev, "Couldn't init SAT resources\n");
 873                         goto err_disable_ram_clk;
 874                 }
 875         }
 876
 877         backend->engine.regs = devm_regmap_init_mmio(dev, regs,
 878                                                      &sun4i_backend_regmap_config);
 879         if (IS_ERR(backend->engine.regs)) {
 880                 dev_err(dev, "Couldn't create the backend regmap\n");
 881                 return PTR_ERR(backend->engine.regs);
 882         }
 883
 884         list_add_tail(&backend->engine.list, &drv->engine_list);
 885
 886         /*
 887          * Many of the backend's layer configuration registers have
 888          * undefined default values. This poses a risk as we use
 889          * regmap_update_bits in some places, and don't overwrite
 890          * the whole register.
 891          *
 892          * Clear the registers here to have something predictable.
 893          */
 894         for (i = 0x800; i < 0x1000; i += 4)
 895                 regmap_write(backend->engine.regs, i, 0);
 896
 897         /* Disable registers autoloading */
 898         regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 899                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
 900
 901         /* Enable the backend */
 902         regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 903                      SUN4I_BACKEND_MODCTL_DEBE_EN |
 904                      SUN4I_BACKEND_MODCTL_START_CTL);
 905
 906         /* Set output selection if needed */
 907         quirks = of_device_get_match_data(dev);
 908         if (quirks->needs_output_muxing) {
 909                 /*
 910                  * We assume there is no dynamic muxing of backends
 911                  * and TCONs, so we select the backend with same ID.
 912                  *
 913                  * While dynamic selection might be interesting, since
 914                  * the CRTC is tied to the TCON, while the layers are
 915                  * tied to the backends, this means, we will need to
 916                  * switch between groups of layers. There might not be
 917                  * a way to represent this constraint in DRM.
 918                  */
 919                 regmap_update_bits(backend->engine.regs,
 920                                    SUN4I_BACKEND_MODCTL_REG,
 921                                    SUN4I_BACKEND_MODCTL_OUT_SEL,
 922                                    (backend->engine.id
 923                                     ? SUN4I_BACKEND_MODCTL_OUT_LCD1
 924                                     : SUN4I_BACKEND_MODCTL_OUT_LCD0));
 925         }
 926
 927         backend->quirks = quirks;
 928
 929         return 0;
 930
 931 err_disable_ram_clk:
 932         clk_disable_unprepare(backend->ram_clk);
 933 err_disable_mod_clk:
 934         clk_disable_unprepare(backend->mod_clk);
 935 err_disable_bus_clk:
 936         clk_disable_unprepare(backend->bus_clk);
 937 err_assert_reset:
 938         reset_control_assert(backend->reset);
 939         return ret;
 940 }
 941
 942 static void sun4i_backend_unbind(struct device *dev, struct device *master,
 943                                  void *data)
 944 {
 945         struct sun4i_backend *backend = dev_get_drvdata(dev);
 946
 947         list_del(&backend->engine.list);
 948
 949         if (of_device_is_compatible(dev->of_node,
 950                                     "allwinner,sun8i-a33-display-backend"))
 951                 sun4i_backend_free_sat(dev);
 952
 953         clk_disable_unprepare(backend->ram_clk);
 954         clk_disable_unprepare(backend->mod_clk);
 955         clk_disable_unprepare(backend->bus_clk);
 956         reset_control_assert(backend->reset);
 957 }
 958
 959 static const struct component_ops sun4i_backend_ops = {
 960         .bind   = sun4i_backend_bind,
 961         .unbind = sun4i_backend_unbind,
 962 };
 963
 964 static int sun4i_backend_probe(struct platform_device *pdev)
 965 {
 966         return component_add(&pdev->dev, &sun4i_backend_ops);
 967 }
 968
 969 static int sun4i_backend_remove(struct platform_device *pdev)
 970 {
 971         component_del(&pdev->dev, &sun4i_backend_ops);
 972
 973         return 0;
 974 }
 975
 976 static const struct sun4i_backend_quirks sun4i_backend_quirks = {
 977         .needs_output_muxing = true,
 978 };
 979
 980 static const struct sun4i_backend_quirks sun5i_backend_quirks = {
 981 };
 982
 983 static const struct sun4i_backend_quirks sun6i_backend_quirks = {
 984 };
 985
 986 static const struct sun4i_backend_quirks sun7i_backend_quirks = {
 987         .needs_output_muxing = true,
 988         .supports_lowest_plane_alpha = true,
 989 };
 990
 991 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = {
 992         .supports_lowest_plane_alpha = true,
 993 };
 994
 995 static const struct sun4i_backend_quirks sun9i_backend_quirks = {
 996 };
 997
 998 static const struct of_device_id sun4i_backend_of_table[] = {
 999         {
1000                 .compatible = "allwinner,sun4i-a10-display-backend",
1001                 .data = &sun4i_backend_quirks,
1002         },
1003         {
1004                 .compatible = "allwinner,sun5i-a13-display-backend",
1005                 .data = &sun5i_backend_quirks,
1006         },
1007         {
1008                 .compatible = "allwinner,sun6i-a31-display-backend",
1009                 .data = &sun6i_backend_quirks,
1010         },
1011         {
1012                 .compatible = "allwinner,sun7i-a20-display-backend",
1013                 .data = &sun7i_backend_quirks,
1014         },
1015         {
1016                 .compatible = "allwinner,sun8i-a23-display-backend",
1017                 .data = &sun8i_a33_backend_quirks,
1018         },
1019         {
1020                 .compatible = "allwinner,sun8i-a33-display-backend",
1021                 .data = &sun8i_a33_backend_quirks,
1022         },
1023         {
1024                 .compatible = "allwinner,sun9i-a80-display-backend",
1025                 .data = &sun9i_backend_quirks,
1026         },
1027         { }
1028 };
1029 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
1030
1031 static struct platform_driver sun4i_backend_platform_driver = {
1032         .probe          = sun4i_backend_probe,
1033         .remove         = sun4i_backend_remove,
1034         .driver         = {
1035                 .name           = "sun4i-backend",
1036                 .of_match_table = sun4i_backend_of_table,
1037         },
1038 };
1039 module_platform_driver(sun4i_backend_platform_driver);
1040
1041 MODULE_AUTHOR("Maxime Ripard <[email protected]>");
1042 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
1043 MODULE_LICENSE("GPL");