drivers/perf/arm_pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 #undef DEBUG
   3
   4 /*
   5  * ARM performance counter support.
   6  *
   7  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   8  * Copyright (C) 2010 ARM Ltd., Will Deacon <[email protected]>
   9  *
  10  * This code is based on the sparc64 perf event code, which is in turn based
  11  * on the x86 code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/bitmap.h>
  16 #include <linux/cpumask.h>
  17 #include <linux/cpu_pm.h>
  18 #include <linux/export.h>
  19 #include <linux/kernel.h>
  20 #include <linux/perf/arm_pmu.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched/clock.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/irq.h>
  25 #include <linux/irqdesc.h>
  26
  27 #include <asm/irq_regs.h>
  28
  29 static int armpmu_count_irq_users(const int irq);
  30
  31 struct pmu_irq_ops {
  32         void (*enable_pmuirq)(unsigned int irq);
  33         void (*disable_pmuirq)(unsigned int irq);
  34         void (*free_pmuirq)(unsigned int irq, int cpu, void __percpu *devid);
  35 };
  36
  37 static void armpmu_free_pmuirq(unsigned int irq, int cpu, void __percpu *devid)
  38 {
  39         free_irq(irq, per_cpu_ptr(devid, cpu));
  40 }
  41
  42 static const struct pmu_irq_ops pmuirq_ops = {
  43         .enable_pmuirq = enable_irq,
  44         .disable_pmuirq = disable_irq_nosync,
  45         .free_pmuirq = armpmu_free_pmuirq
  46 };
  47
  48 static void armpmu_free_pmunmi(unsigned int irq, int cpu, void __percpu *devid)
  49 {
  50         free_nmi(irq, per_cpu_ptr(devid, cpu));
  51 }
  52
  53 static const struct pmu_irq_ops pmunmi_ops = {
  54         .enable_pmuirq = enable_nmi,
  55         .disable_pmuirq = disable_nmi_nosync,
  56         .free_pmuirq = armpmu_free_pmunmi
  57 };
  58
  59 static void armpmu_enable_percpu_pmuirq(unsigned int irq)
  60 {
  61         enable_percpu_irq(irq, IRQ_TYPE_NONE);
  62 }
  63
  64 static void armpmu_free_percpu_pmuirq(unsigned int irq, int cpu,
  65                                    void __percpu *devid)
  66 {
  67         if (armpmu_count_irq_users(irq) == 1)
  68                 free_percpu_irq(irq, devid);
  69 }
  70
  71 static const struct pmu_irq_ops percpu_pmuirq_ops = {
  72         .enable_pmuirq = armpmu_enable_percpu_pmuirq,
  73         .disable_pmuirq = disable_percpu_irq,
  74         .free_pmuirq = armpmu_free_percpu_pmuirq
  75 };
  76
  77 static void armpmu_enable_percpu_pmunmi(unsigned int irq)
  78 {
  79         if (!prepare_percpu_nmi(irq))
  80                 enable_percpu_nmi(irq, IRQ_TYPE_NONE);
  81 }
  82
  83 static void armpmu_disable_percpu_pmunmi(unsigned int irq)
  84 {
  85         disable_percpu_nmi(irq);
  86         teardown_percpu_nmi(irq);
  87 }
  88
  89 static void armpmu_free_percpu_pmunmi(unsigned int irq, int cpu,
  90                                       void __percpu *devid)
  91 {
  92         if (armpmu_count_irq_users(irq) == 1)
  93                 free_percpu_nmi(irq, devid);
  94 }
  95
  96 static const struct pmu_irq_ops percpu_pmunmi_ops = {
  97         .enable_pmuirq = armpmu_enable_percpu_pmunmi,
  98         .disable_pmuirq = armpmu_disable_percpu_pmunmi,
  99         .free_pmuirq = armpmu_free_percpu_pmunmi
 100 };
 101
 102 static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
 103 static DEFINE_PER_CPU(int, cpu_irq);
 104 static DEFINE_PER_CPU(const struct pmu_irq_ops *, cpu_irq_ops);
 105
 106 static bool has_nmi;
 107
 108 static inline u64 arm_pmu_event_max_period(struct perf_event *event)
 109 {
 110         if (event->hw.flags & ARMPMU_EVT_64BIT)
 111                 return GENMASK_ULL(63, 0);
 112         else if (event->hw.flags & ARMPMU_EVT_47BIT)
 113                 return GENMASK_ULL(46, 0);
 114         else
 115                 return GENMASK_ULL(31, 0);
 116 }
 117
 118 static int
 119 armpmu_map_cache_event(const unsigned (*cache_map)
 120                                       [PERF_COUNT_HW_CACHE_MAX]
 121                                       [PERF_COUNT_HW_CACHE_OP_MAX]
 122                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
 123                        u64 config)
 124 {
 125         unsigned int cache_type, cache_op, cache_result, ret;
 126
 127         cache_type = (config >>  0) & 0xff;
 128         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 129                 return -EINVAL;
 130
 131         cache_op = (config >>  8) & 0xff;
 132         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 133                 return -EINVAL;
 134
 135         cache_result = (config >> 16) & 0xff;
 136         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 137                 return -EINVAL;
 138
 139         if (!cache_map)
 140                 return -ENOENT;
 141
 142         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
 143
 144         if (ret == CACHE_OP_UNSUPPORTED)
 145                 return -ENOENT;
 146
 147         return ret;
 148 }
 149
 150 static int
 151 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 152 {
 153         int mapping;
 154
 155         if (config >= PERF_COUNT_HW_MAX)
 156                 return -EINVAL;
 157
 158         if (!event_map)
 159                 return -ENOENT;
 160
 161         mapping = (*event_map)[config];
 162         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
 163 }
 164
 165 static int
 166 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
 167 {
 168         return (int)(config & raw_event_mask);
 169 }
 170
 171 int
 172 armpmu_map_event(struct perf_event *event,
 173                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 174                  const unsigned (*cache_map)
 175                                 [PERF_COUNT_HW_CACHE_MAX]
 176                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 177                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
 178                  u32 raw_event_mask)
 179 {
 180         u64 config = event->attr.config;
 181         int type = event->attr.type;
 182
 183         if (type == event->pmu->type)
 184                 return armpmu_map_raw_event(raw_event_mask, config);
 185
 186         switch (type) {
 187         case PERF_TYPE_HARDWARE:
 188                 return armpmu_map_hw_event(event_map, config);
 189         case PERF_TYPE_HW_CACHE:
 190                 return armpmu_map_cache_event(cache_map, config);
 191         case PERF_TYPE_RAW:
 192                 return armpmu_map_raw_event(raw_event_mask, config);
 193         }
 194
 195         return -ENOENT;
 196 }
 197
 198 int armpmu_event_set_period(struct perf_event *event)
 199 {
 200         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 201         struct hw_perf_event *hwc = &event->hw;
 202         s64 left = local64_read(&hwc->period_left);
 203         s64 period = hwc->sample_period;
 204         u64 max_period;
 205         int ret = 0;
 206
 207         max_period = arm_pmu_event_max_period(event);
 208         if (unlikely(left <= -period)) {
 209                 left = period;
 210                 local64_set(&hwc->period_left, left);
 211                 hwc->last_period = period;
 212                 ret = 1;
 213         }
 214
 215         if (unlikely(left <= 0)) {
 216                 left += period;
 217                 local64_set(&hwc->period_left, left);
 218                 hwc->last_period = period;
 219                 ret = 1;
 220         }
 221
 222         /*
 223          * Limit the maximum period to prevent the counter value
 224          * from overtaking the one we are about to program. In
 225          * effect we are reducing max_period to account for
 226          * interrupt latency (and we are being very conservative).
 227          */
 228         if (left > (max_period >> 1))
 229                 left = (max_period >> 1);
 230
 231         local64_set(&hwc->prev_count, (u64)-left);
 232
 233         armpmu->write_counter(event, (u64)(-left) & max_period);
 234
 235         perf_event_update_userpage(event);
 236
 237         return ret;
 238 }
 239
 240 u64 armpmu_event_update(struct perf_event *event)
 241 {
 242         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 243         struct hw_perf_event *hwc = &event->hw;
 244         u64 delta, prev_raw_count, new_raw_count;
 245         u64 max_period = arm_pmu_event_max_period(event);
 246
 247 again:
 248         prev_raw_count = local64_read(&hwc->prev_count);
 249         new_raw_count = armpmu->read_counter(event);
 250
 251         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 252                              new_raw_count) != prev_raw_count)
 253                 goto again;
 254
 255         delta = (new_raw_count - prev_raw_count) & max_period;
 256
 257         local64_add(delta, &event->count);
 258         local64_sub(delta, &hwc->period_left);
 259
 260         return new_raw_count;
 261 }
 262
 263 static void
 264 armpmu_read(struct perf_event *event)
 265 {
 266         armpmu_event_update(event);
 267 }
 268
 269 static void
 270 armpmu_stop(struct perf_event *event, int flags)
 271 {
 272         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 273         struct hw_perf_event *hwc = &event->hw;
 274
 275         /*
 276          * ARM pmu always has to update the counter, so ignore
 277          * PERF_EF_UPDATE, see comments in armpmu_start().
 278          */
 279         if (!(hwc->state & PERF_HES_STOPPED)) {
 280                 armpmu->disable(event);
 281                 armpmu_event_update(event);
 282                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 283         }
 284 }
 285
 286 static void armpmu_start(struct perf_event *event, int flags)
 287 {
 288         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 289         struct hw_perf_event *hwc = &event->hw;
 290
 291         /*
 292          * ARM pmu always has to reprogram the period, so ignore
 293          * PERF_EF_RELOAD, see the comment below.
 294          */
 295         if (flags & PERF_EF_RELOAD)
 296                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 297
 298         hwc->state = 0;
 299         /*
 300          * Set the period again. Some counters can't be stopped, so when we
 301          * were stopped we simply disabled the IRQ source and the counter
 302          * may have been left counting. If we don't do this step then we may
 303          * get an interrupt too soon or *way* too late if the overflow has
 304          * happened since disabling.
 305          */
 306         armpmu_event_set_period(event);
 307         armpmu->enable(event);
 308 }
 309
 310 static void
 311 armpmu_del(struct perf_event *event, int flags)
 312 {
 313         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 314         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 315         struct hw_perf_event *hwc = &event->hw;
 316         int idx = hwc->idx;
 317
 318         armpmu_stop(event, PERF_EF_UPDATE);
 319         hw_events->events[idx] = NULL;
 320         armpmu->clear_event_idx(hw_events, event);
 321         perf_event_update_userpage(event);
 322         /* Clear the allocated counter */
 323         hwc->idx = -1;
 324 }
 325
 326 static int
 327 armpmu_add(struct perf_event *event, int flags)
 328 {
 329         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 330         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 331         struct hw_perf_event *hwc = &event->hw;
 332         int idx;
 333
 334         /* An event following a process won't be stopped earlier */
 335         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 336                 return -ENOENT;
 337
 338         /* If we don't have a space for the counter then finish early. */
 339         idx = armpmu->get_event_idx(hw_events, event);
 340         if (idx < 0)
 341                 return idx;
 342
 343         /*
 344          * If there is an event in the counter we are going to use then make
 345          * sure it is disabled.
 346          */
 347         event->hw.idx = idx;
 348         armpmu->disable(event);
 349         hw_events->events[idx] = event;
 350
 351         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 352         if (flags & PERF_EF_START)
 353                 armpmu_start(event, PERF_EF_RELOAD);
 354
 355         /* Propagate our changes to the userspace mapping. */
 356         perf_event_update_userpage(event);
 357
 358         return 0;
 359 }
 360
 361 static int
 362 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
 363                                struct perf_event *event)
 364 {
 365         struct arm_pmu *armpmu;
 366
 367         if (is_software_event(event))
 368                 return 1;
 369
 370         /*
 371          * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
 372          * core perf code won't check that the pmu->ctx == leader->ctx
 373          * until after pmu->event_init(event).
 374          */
 375         if (event->pmu != pmu)
 376                 return 0;
 377
 378         if (event->state < PERF_EVENT_STATE_OFF)
 379                 return 1;
 380
 381         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 382                 return 1;
 383
 384         armpmu = to_arm_pmu(event->pmu);
 385         return armpmu->get_event_idx(hw_events, event) >= 0;
 386 }
 387
 388 static int
 389 validate_group(struct perf_event *event)
 390 {
 391         struct perf_event *sibling, *leader = event->group_leader;
 392         struct pmu_hw_events fake_pmu;
 393
 394         /*
 395          * Initialise the fake PMU. We only need to populate the
 396          * used_mask for the purposes of validation.
 397          */
 398         memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
 399
 400         if (!validate_event(event->pmu, &fake_pmu, leader))
 401                 return -EINVAL;
 402
 403         if (event == leader)
 404                 return 0;
 405
 406         for_each_sibling_event(sibling, leader) {
 407                 if (!validate_event(event->pmu, &fake_pmu, sibling))
 408                         return -EINVAL;
 409         }
 410
 411         if (!validate_event(event->pmu, &fake_pmu, event))
 412                 return -EINVAL;
 413
 414         return 0;
 415 }
 416
 417 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 418 {
 419         struct arm_pmu *armpmu;
 420         int ret;
 421         u64 start_clock, finish_clock;
 422
 423         /*
 424          * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
 425          * the handlers expect a struct arm_pmu*. The percpu_irq framework will
 426          * do any necessary shifting, we just need to perform the first
 427          * dereference.
 428          */
 429         armpmu = *(void **)dev;
 430         if (WARN_ON_ONCE(!armpmu))
 431                 return IRQ_NONE;
 432
 433         start_clock = sched_clock();
 434         ret = armpmu->handle_irq(armpmu);
 435         finish_clock = sched_clock();
 436
 437         perf_sample_event_took(finish_clock - start_clock);
 438         return ret;
 439 }
 440
 441 static int
 442 __hw_perf_event_init(struct perf_event *event)
 443 {
 444         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 445         struct hw_perf_event *hwc = &event->hw;
 446         int mapping;
 447
 448         hwc->flags = 0;
 449         mapping = armpmu->map_event(event);
 450
 451         if (mapping < 0) {
 452                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 453                          event->attr.config);
 454                 return mapping;
 455         }
 456
 457         /*
 458          * We don't assign an index until we actually place the event onto
 459          * hardware. Use -1 to signify that we haven't decided where to put it
 460          * yet. For SMP systems, each core has it's own PMU so we can't do any
 461          * clever allocation or constraints checking at this point.
 462          */
 463         hwc->idx                = -1;
 464         hwc->config_base        = 0;
 465         hwc->config             = 0;
 466         hwc->event_base         = 0;
 467
 468         /*
 469          * Check whether we need to exclude the counter from certain modes.
 470          */
 471         if (armpmu->set_event_filter &&
 472             armpmu->set_event_filter(hwc, &event->attr)) {
 473                 pr_debug("ARM performance counters do not support "
 474                          "mode exclusion\n");
 475                 return -EOPNOTSUPP;
 476         }
 477
 478         /*
 479          * Store the event encoding into the config_base field.
 480          */
 481         hwc->config_base            |= (unsigned long)mapping;
 482
 483         if (!is_sampling_event(event)) {
 484                 /*
 485                  * For non-sampling runs, limit the sample_period to half
 486                  * of the counter width. That way, the new counter value
 487                  * is far less likely to overtake the previous one unless
 488                  * you have some serious IRQ latency issues.
 489                  */
 490                 hwc->sample_period  = arm_pmu_event_max_period(event) >> 1;
 491                 hwc->last_period    = hwc->sample_period;
 492                 local64_set(&hwc->period_left, hwc->sample_period);
 493         }
 494
 495         return validate_group(event);
 496 }
 497
 498 static int armpmu_event_init(struct perf_event *event)
 499 {
 500         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 501
 502         /*
 503          * Reject CPU-affine events for CPUs that are of a different class to
 504          * that which this PMU handles. Process-following events (where
 505          * event->cpu == -1) can be migrated between CPUs, and thus we have to
 506          * reject them later (in armpmu_add) if they're scheduled on a
 507          * different class of CPU.
 508          */
 509         if (event->cpu != -1 &&
 510                 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
 511                 return -ENOENT;
 512
 513         /* does not support taken branch sampling */
 514         if (has_branch_stack(event))
 515                 return -EOPNOTSUPP;
 516
 517         return __hw_perf_event_init(event);
 518 }
 519
 520 static void armpmu_enable(struct pmu *pmu)
 521 {
 522         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 523         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 524         bool enabled = !bitmap_empty(hw_events->used_mask, armpmu->num_events);
 525
 526         /* For task-bound events we may be called on other CPUs */
 527         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 528                 return;
 529
 530         if (enabled)
 531                 armpmu->start(armpmu);
 532 }
 533
 534 static void armpmu_disable(struct pmu *pmu)
 535 {
 536         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 537
 538         /* For task-bound events we may be called on other CPUs */
 539         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 540                 return;
 541
 542         armpmu->stop(armpmu);
 543 }
 544
 545 /*
 546  * In heterogeneous systems, events are specific to a particular
 547  * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
 548  * the same microarchitecture.
 549  */
 550 static bool armpmu_filter(struct pmu *pmu, int cpu)
 551 {
 552         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 553         bool ret;
 554
 555         ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus);
 556         if (ret && armpmu->filter)
 557                 return armpmu->filter(pmu, cpu);
 558
 559         return ret;
 560 }
 561
 562 static ssize_t cpus_show(struct device *dev,
 563                          struct device_attribute *attr, char *buf)
 564 {
 565         struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
 566         return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
 567 }
 568
 569 static DEVICE_ATTR_RO(cpus);
 570
 571 static struct attribute *armpmu_common_attrs[] = {
 572         &dev_attr_cpus.attr,
 573         NULL,
 574 };
 575
 576 static const struct attribute_group armpmu_common_attr_group = {
 577         .attrs = armpmu_common_attrs,
 578 };
 579
 580 static int armpmu_count_irq_users(const int irq)
 581 {
 582         int cpu, count = 0;
 583
 584         for_each_possible_cpu(cpu) {
 585                 if (per_cpu(cpu_irq, cpu) == irq)
 586                         count++;
 587         }
 588
 589         return count;
 590 }
 591
 592 static const struct pmu_irq_ops *armpmu_find_irq_ops(int irq)
 593 {
 594         const struct pmu_irq_ops *ops = NULL;
 595         int cpu;
 596
 597         for_each_possible_cpu(cpu) {
 598                 if (per_cpu(cpu_irq, cpu) != irq)
 599                         continue;
 600
 601                 ops = per_cpu(cpu_irq_ops, cpu);
 602                 if (ops)
 603                         break;
 604         }
 605
 606         return ops;
 607 }
 608
 609 void armpmu_free_irq(int irq, int cpu)
 610 {
 611         if (per_cpu(cpu_irq, cpu) == 0)
 612                 return;
 613         if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
 614                 return;
 615
 616         per_cpu(cpu_irq_ops, cpu)->free_pmuirq(irq, cpu, &cpu_armpmu);
 617
 618         per_cpu(cpu_irq, cpu) = 0;
 619         per_cpu(cpu_irq_ops, cpu) = NULL;
 620 }
 621
 622 int armpmu_request_irq(int irq, int cpu)
 623 {
 624         int err = 0;
 625         const irq_handler_t handler = armpmu_dispatch_irq;
 626         const struct pmu_irq_ops *irq_ops;
 627
 628         if (!irq)
 629                 return 0;
 630
 631         if (!irq_is_percpu_devid(irq)) {
 632                 unsigned long irq_flags;
 633
 634                 err = irq_force_affinity(irq, cpumask_of(cpu));
 635
 636                 if (err && num_possible_cpus() > 1) {
 637                         pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
 638                                 irq, cpu);
 639                         goto err_out;
 640                 }
 641
 642                 irq_flags = IRQF_PERCPU |
 643                             IRQF_NOBALANCING | IRQF_NO_AUTOEN |
 644                             IRQF_NO_THREAD;
 645
 646                 err = request_nmi(irq, handler, irq_flags, "arm-pmu",
 647                                   per_cpu_ptr(&cpu_armpmu, cpu));
 648
 649                 /* If cannot get an NMI, get a normal interrupt */
 650                 if (err) {
 651                         err = request_irq(irq, handler, irq_flags, "arm-pmu",
 652                                           per_cpu_ptr(&cpu_armpmu, cpu));
 653                         irq_ops = &pmuirq_ops;
 654                 } else {
 655                         has_nmi = true;
 656                         irq_ops = &pmunmi_ops;
 657                 }
 658         } else if (armpmu_count_irq_users(irq) == 0) {
 659                 err = request_percpu_nmi(irq, handler, "arm-pmu", &cpu_armpmu);
 660
 661                 /* If cannot get an NMI, get a normal interrupt */
 662                 if (err) {
 663                         err = request_percpu_irq(irq, handler, "arm-pmu",
 664                                                  &cpu_armpmu);
 665                         irq_ops = &percpu_pmuirq_ops;
 666                 } else {
 667                         has_nmi = true;
 668                         irq_ops = &percpu_pmunmi_ops;
 669                 }
 670         } else {
 671                 /* Per cpudevid irq was already requested by another CPU */
 672                 irq_ops = armpmu_find_irq_ops(irq);
 673
 674                 if (WARN_ON(!irq_ops))
 675                         err = -EINVAL;
 676         }
 677
 678         if (err)
 679                 goto err_out;
 680
 681         per_cpu(cpu_irq, cpu) = irq;
 682         per_cpu(cpu_irq_ops, cpu) = irq_ops;
 683         return 0;
 684
 685 err_out:
 686         pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
 687         return err;
 688 }
 689
 690 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
 691 {
 692         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 693         return per_cpu(hw_events->irq, cpu);
 694 }
 695
 696 /*
 697  * PMU hardware loses all context when a CPU goes offline.
 698  * When a CPU is hotplugged back in, since some hardware registers are
 699  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 700  * junk values out of them.
 701  */
 702 static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
 703 {
 704         struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
 705         int irq;
 706
 707         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 708                 return 0;
 709         if (pmu->reset)
 710                 pmu->reset(pmu);
 711
 712         per_cpu(cpu_armpmu, cpu) = pmu;
 713
 714         irq = armpmu_get_cpu_irq(pmu, cpu);
 715         if (irq)
 716                 per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq);
 717
 718         return 0;
 719 }
 720
 721 static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
 722 {
 723         struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
 724         int irq;
 725
 726         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 727                 return 0;
 728
 729         irq = armpmu_get_cpu_irq(pmu, cpu);
 730         if (irq)
 731                 per_cpu(cpu_irq_ops, cpu)->disable_pmuirq(irq);
 732
 733         per_cpu(cpu_armpmu, cpu) = NULL;
 734
 735         return 0;
 736 }
 737
 738 #ifdef CONFIG_CPU_PM
 739 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
 740 {
 741         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 742         struct perf_event *event;
 743         int idx;
 744
 745         for (idx = 0; idx < armpmu->num_events; idx++) {
 746                 event = hw_events->events[idx];
 747                 if (!event)
 748                         continue;
 749
 750                 switch (cmd) {
 751                 case CPU_PM_ENTER:
 752                         /*
 753                          * Stop and update the counter
 754                          */
 755                         armpmu_stop(event, PERF_EF_UPDATE);
 756                         break;
 757                 case CPU_PM_EXIT:
 758                 case CPU_PM_ENTER_FAILED:
 759                          /*
 760                           * Restore and enable the counter.
 761                           * armpmu_start() indirectly calls
 762                           *
 763                           * perf_event_update_userpage()
 764                           *
 765                           * that requires RCU read locking to be functional,
 766                           * wrap the call within RCU_NONIDLE to make the
 767                           * RCU subsystem aware this cpu is not idle from
 768                           * an RCU perspective for the armpmu_start() call
 769                           * duration.
 770                           */
 771                         RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
 772                         break;
 773                 default:
 774                         break;
 775                 }
 776         }
 777 }
 778
 779 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
 780                              void *v)
 781 {
 782         struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
 783         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 784         bool enabled = !bitmap_empty(hw_events->used_mask, armpmu->num_events);
 785
 786         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 787                 return NOTIFY_DONE;
 788
 789         /*
 790          * Always reset the PMU registers on power-up even if
 791          * there are no events running.
 792          */
 793         if (cmd == CPU_PM_EXIT && armpmu->reset)
 794                 armpmu->reset(armpmu);
 795
 796         if (!enabled)
 797                 return NOTIFY_OK;
 798
 799         switch (cmd) {
 800         case CPU_PM_ENTER:
 801                 armpmu->stop(armpmu);
 802                 cpu_pm_pmu_setup(armpmu, cmd);
 803                 break;
 804         case CPU_PM_EXIT:
 805         case CPU_PM_ENTER_FAILED:
 806                 cpu_pm_pmu_setup(armpmu, cmd);
 807                 armpmu->start(armpmu);
 808                 break;
 809         default:
 810                 return NOTIFY_DONE;
 811         }
 812
 813         return NOTIFY_OK;
 814 }
 815
 816 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
 817 {
 818         cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
 819         return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
 820 }
 821
 822 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
 823 {
 824         cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
 825 }
 826 #else
 827 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
 828 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
 829 #endif
 830
 831 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
 832 {
 833         int err;
 834
 835         err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
 836                                        &cpu_pmu->node);
 837         if (err)
 838                 goto out;
 839
 840         err = cpu_pm_pmu_register(cpu_pmu);
 841         if (err)
 842                 goto out_unregister;
 843
 844         return 0;
 845
 846 out_unregister:
 847         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
 848                                             &cpu_pmu->node);
 849 out:
 850         return err;
 851 }
 852
 853 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
 854 {
 855         cpu_pm_pmu_unregister(cpu_pmu);
 856         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
 857                                             &cpu_pmu->node);
 858 }
 859
 860 struct arm_pmu *armpmu_alloc(void)
 861 {
 862         struct arm_pmu *pmu;
 863         int cpu;
 864
 865         pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
 866         if (!pmu)
 867                 goto out;
 868
 869         pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, GFP_KERNEL);
 870         if (!pmu->hw_events) {
 871                 pr_info("failed to allocate per-cpu PMU data.\n");
 872                 goto out_free_pmu;
 873         }
 874
 875         pmu->pmu = (struct pmu) {
 876                 .pmu_enable     = armpmu_enable,
 877                 .pmu_disable    = armpmu_disable,
 878                 .event_init     = armpmu_event_init,
 879                 .add            = armpmu_add,
 880                 .del            = armpmu_del,
 881                 .start          = armpmu_start,
 882                 .stop           = armpmu_stop,
 883                 .read           = armpmu_read,
 884                 .filter         = armpmu_filter,
 885                 .attr_groups    = pmu->attr_groups,
 886                 /*
 887                  * This is a CPU PMU potentially in a heterogeneous
 888                  * configuration (e.g. big.LITTLE). This is not an uncore PMU,
 889                  * and we have taken ctx sharing into account (e.g. with our
 890                  * pmu::filter callback and pmu::event_init group validation).
 891                  */
 892                 .capabilities   = PERF_PMU_CAP_HETEROGENEOUS_CPUS | PERF_PMU_CAP_EXTENDED_REGS,
 893         };
 894
 895         pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
 896                 &armpmu_common_attr_group;
 897
 898         for_each_possible_cpu(cpu) {
 899                 struct pmu_hw_events *events;
 900
 901                 events = per_cpu_ptr(pmu->hw_events, cpu);
 902                 raw_spin_lock_init(&events->pmu_lock);
 903                 events->percpu_pmu = pmu;
 904         }
 905
 906         return pmu;
 907
 908 out_free_pmu:
 909         kfree(pmu);
 910 out:
 911         return NULL;
 912 }
 913
 914 void armpmu_free(struct arm_pmu *pmu)
 915 {
 916         free_percpu(pmu->hw_events);
 917         kfree(pmu);
 918 }
 919
 920 int armpmu_register(struct arm_pmu *pmu)
 921 {
 922         int ret;
 923
 924         ret = cpu_pmu_init(pmu);
 925         if (ret)
 926                 return ret;
 927
 928         if (!pmu->set_event_filter)
 929                 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
 930
 931         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
 932         if (ret)
 933                 goto out_destroy;
 934
 935         pr_info("enabled with %s PMU driver, %d counters available%s\n",
 936                 pmu->name, pmu->num_events,
 937                 has_nmi ? ", using NMIs" : "");
 938
 939         kvm_host_pmu_init(pmu);
 940
 941         return 0;
 942
 943 out_destroy:
 944         cpu_pmu_destroy(pmu);
 945         return ret;
 946 }
 947
 948 static int arm_pmu_hp_init(void)
 949 {
 950         int ret;
 951
 952         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
 953                                       "perf/arm/pmu:starting",
 954                                       arm_perf_starting_cpu,
 955                                       arm_perf_teardown_cpu);
 956         if (ret)
 957                 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
 958                        ret);
 959         return ret;
 960 }
 961 subsys_initcall(arm_pmu_hp_init);