arch/arm64/kernel/perf_event.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARMv8 PMUv3 Performance Events handling code.
   4  *
   5  * Copyright (C) 2012 ARM Limited
   6  * Author: Will Deacon <[email protected]>
   7  *
   8  * This code is based heavily on the ARMv7 perf event code.
   9  */
  10
  11 #include <asm/irq_regs.h>
  12 #include <asm/perf_event.h>
  13 #include <asm/sysreg.h>
  14 #include <asm/virt.h>
  15
  16 #include <clocksource/arm_arch_timer.h>
  17
  18 #include <linux/acpi.h>
  19 #include <linux/clocksource.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/of.h>
  22 #include <linux/perf/arm_pmu.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sched_clock.h>
  25 #include <linux/smp.h>
  26
  27 /* ARMv8 Cortex-A53 specific event types. */
  28 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
  29
  30 /* ARMv8 Cavium ThunderX specific event types. */
  31 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
  32 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
  33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
  34 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
  35 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
  36
  37 /*
  38  * ARMv8 Architectural defined events, not all of these may
  39  * be supported on any given implementation. Unsupported events will
  40  * be disabled at run-time based on the PMCEID registers.
  41  */
  42 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
  43         PERF_MAP_ALL_UNSUPPORTED,
  44         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
  45         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
  46         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  47         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  48         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
  49         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  50         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
  51         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
  52         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
  53 };
  54
  55 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  56                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  58         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  59
  60         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  61         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  62
  63         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
  64         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
  65
  66         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
  67         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
  68
  69         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
  70         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
  71
  72         [C(LL)][C(OP_READ)][C(RESULT_MISS)]     = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
  73         [C(LL)][C(OP_READ)][C(RESULT_ACCESS)]   = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
  74
  75         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
  76         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  77 };
  78
  79 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  80                                               [PERF_COUNT_HW_CACHE_OP_MAX]
  81                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  82         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  83
  84         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
  85
  86         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
  87         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
  88 };
  89
  90 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  91                                               [PERF_COUNT_HW_CACHE_OP_MAX]
  92                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  93         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  94
  95         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  96         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
  97         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  98         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
  99
 100         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 101         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 102
 103         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 104         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 105 };
 106
 107 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 108                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 109                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 110         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 111
 112         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 113         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 114 };
 115
 116 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 117                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 118                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 119         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 120
 121         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 122         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 123         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 124         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 125         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 126         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 127
 128         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 129         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 130
 131         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 132         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 133         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 134         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 135 };
 136
 137 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 138                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 139                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 140         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 141
 142         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 143         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 144         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 145         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 146
 147         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 148         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 149         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 150         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 151
 152         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 153         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 154 };
 155
 156 static ssize_t
 157 armv8pmu_events_sysfs_show(struct device *dev,
 158                            struct device_attribute *attr, char *page)
 159 {
 160         struct perf_pmu_events_attr *pmu_attr;
 161
 162         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 163
 164         return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
 165 }
 166
 167 #define ARMV8_EVENT_ATTR(name, config)                                          \
 168         PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config)
 169
 170 static struct attribute *armv8_pmuv3_event_attrs[] = {
 171         ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
 172         ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
 173         ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
 174         ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
 175         ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
 176         ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
 177         ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
 178         ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
 179         ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
 180         ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
 181         ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
 182         ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
 183         ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
 184         ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
 185         ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
 186         ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
 187         ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
 188         ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
 189         ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
 190         ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
 191         ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
 192         ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
 193         ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
 194         ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
 195         ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
 196         ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
 197         ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
 198         ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
 199         ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
 200         ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
 201         /* Don't expose the chain event in /sys, since it's useless in isolation */
 202         ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
 203         ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
 204         ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
 205         ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
 206         ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
 207         ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
 208         ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
 209         ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
 210         ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
 211         ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
 212         ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
 213         ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
 214         ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
 215         ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
 216         ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
 217         ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
 218         ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
 219         ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
 220         ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
 221         ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
 222         ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
 223         ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
 224         ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
 225         ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
 226         ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
 227         ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
 228         ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
 229         ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
 230         ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
 231         ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
 232         ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
 233         ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
 234         ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
 235         ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
 236         ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
 237         ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
 238         ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
 239         ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
 240         ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
 241         ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
 242         ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
 243         ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
 244         ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
 245         ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP),
 246         ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG),
 247         ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0),
 248         ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1),
 249         ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2),
 250         ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3),
 251         ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4),
 252         ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5),
 253         ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6),
 254         ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7),
 255         ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
 256         ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
 257         ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
 258         ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
 259         ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
 260         ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
 261         NULL,
 262 };
 263
 264 static umode_t
 265 armv8pmu_event_attr_is_visible(struct kobject *kobj,
 266                                struct attribute *attr, int unused)
 267 {
 268         struct device *dev = kobj_to_dev(kobj);
 269         struct pmu *pmu = dev_get_drvdata(dev);
 270         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 271         struct perf_pmu_events_attr *pmu_attr;
 272
 273         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 274
 275         if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 276             test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 277                 return attr->mode;
 278
 279         if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
 280                 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
 281
 282                 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 283                     test_bit(id, cpu_pmu->pmceid_ext_bitmap))
 284                         return attr->mode;
 285         }
 286
 287         return 0;
 288 }
 289
 290 static const struct attribute_group armv8_pmuv3_events_attr_group = {
 291         .name = "events",
 292         .attrs = armv8_pmuv3_event_attrs,
 293         .is_visible = armv8pmu_event_attr_is_visible,
 294 };
 295
 296 PMU_FORMAT_ATTR(event, "config:0-15");
 297 PMU_FORMAT_ATTR(long, "config1:0");
 298 PMU_FORMAT_ATTR(rdpmc, "config1:1");
 299
 300 static int sysctl_perf_user_access __read_mostly;
 301
 302 static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
 303 {
 304         return event->attr.config1 & 0x1;
 305 }
 306
 307 static inline bool armv8pmu_event_want_user_access(struct perf_event *event)
 308 {
 309         return event->attr.config1 & 0x2;
 310 }
 311
 312 static struct attribute *armv8_pmuv3_format_attrs[] = {
 313         &format_attr_event.attr,
 314         &format_attr_long.attr,
 315         &format_attr_rdpmc.attr,
 316         NULL,
 317 };
 318
 319 static const struct attribute_group armv8_pmuv3_format_attr_group = {
 320         .name = "format",
 321         .attrs = armv8_pmuv3_format_attrs,
 322 };
 323
 324 static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
 325                           char *page)
 326 {
 327         struct pmu *pmu = dev_get_drvdata(dev);
 328         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 329         u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
 330
 331         return sysfs_emit(page, "0x%08x\n", slots);
 332 }
 333
 334 static DEVICE_ATTR_RO(slots);
 335
 336 static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr,
 337                               char *page)
 338 {
 339         struct pmu *pmu = dev_get_drvdata(dev);
 340         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 341         u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT)
 342                         & ARMV8_PMU_BUS_SLOTS_MASK;
 343
 344         return sysfs_emit(page, "0x%08x\n", bus_slots);
 345 }
 346
 347 static DEVICE_ATTR_RO(bus_slots);
 348
 349 static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr,
 350                               char *page)
 351 {
 352         struct pmu *pmu = dev_get_drvdata(dev);
 353         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 354         u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT)
 355                         & ARMV8_PMU_BUS_WIDTH_MASK;
 356         u32 val = 0;
 357
 358         /* Encoded as Log2(number of bytes), plus one */
 359         if (bus_width > 2 && bus_width < 13)
 360                 val = 1 << (bus_width - 1);
 361
 362         return sysfs_emit(page, "0x%08x\n", val);
 363 }
 364
 365 static DEVICE_ATTR_RO(bus_width);
 366
 367 static struct attribute *armv8_pmuv3_caps_attrs[] = {
 368         &dev_attr_slots.attr,
 369         &dev_attr_bus_slots.attr,
 370         &dev_attr_bus_width.attr,
 371         NULL,
 372 };
 373
 374 static const struct attribute_group armv8_pmuv3_caps_attr_group = {
 375         .name = "caps",
 376         .attrs = armv8_pmuv3_caps_attrs,
 377 };
 378
 379 /*
 380  * Perf Events' indices
 381  */
 382 #define ARMV8_IDX_CYCLE_COUNTER 0
 383 #define ARMV8_IDX_COUNTER0      1
 384 #define ARMV8_IDX_CYCLE_COUNTER_USER    32
 385
 386 /*
 387  * We unconditionally enable ARMv8.5-PMU long event counter support
 388  * (64-bit events) where supported. Indicate if this arm_pmu has long
 389  * event counter support.
 390  */
 391 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
 392 {
 393         return (cpu_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5);
 394 }
 395
 396 static inline bool armv8pmu_event_has_user_read(struct perf_event *event)
 397 {
 398         return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT;
 399 }
 400
 401 /*
 402  * We must chain two programmable counters for 64 bit events,
 403  * except when we have allocated the 64bit cycle counter (for CPU
 404  * cycles event) or when user space counter access is enabled.
 405  */
 406 static inline bool armv8pmu_event_is_chained(struct perf_event *event)
 407 {
 408         int idx = event->hw.idx;
 409         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 410
 411         return !armv8pmu_event_has_user_read(event) &&
 412                armv8pmu_event_is_64bit(event) &&
 413                !armv8pmu_has_long_event(cpu_pmu) &&
 414                (idx != ARMV8_IDX_CYCLE_COUNTER);
 415 }
 416
 417 /*
 418  * ARMv8 low level PMU access
 419  */
 420
 421 /*
 422  * Perf Event to low level counters mapping
 423  */
 424 #define ARMV8_IDX_TO_COUNTER(x) \
 425         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 426
 427 /*
 428  * This code is really good
 429  */
 430
 431 #define PMEVN_CASE(n, case_macro) \
 432         case n: case_macro(n); break
 433
 434 #define PMEVN_SWITCH(x, case_macro)                             \
 435         do {                                                    \
 436                 switch (x) {                                    \
 437                 PMEVN_CASE(0,  case_macro);                     \
 438                 PMEVN_CASE(1,  case_macro);                     \
 439                 PMEVN_CASE(2,  case_macro);                     \
 440                 PMEVN_CASE(3,  case_macro);                     \
 441                 PMEVN_CASE(4,  case_macro);                     \
 442                 PMEVN_CASE(5,  case_macro);                     \
 443                 PMEVN_CASE(6,  case_macro);                     \
 444                 PMEVN_CASE(7,  case_macro);                     \
 445                 PMEVN_CASE(8,  case_macro);                     \
 446                 PMEVN_CASE(9,  case_macro);                     \
 447                 PMEVN_CASE(10, case_macro);                     \
 448                 PMEVN_CASE(11, case_macro);                     \
 449                 PMEVN_CASE(12, case_macro);                     \
 450                 PMEVN_CASE(13, case_macro);                     \
 451                 PMEVN_CASE(14, case_macro);                     \
 452                 PMEVN_CASE(15, case_macro);                     \
 453                 PMEVN_CASE(16, case_macro);                     \
 454                 PMEVN_CASE(17, case_macro);                     \
 455                 PMEVN_CASE(18, case_macro);                     \
 456                 PMEVN_CASE(19, case_macro);                     \
 457                 PMEVN_CASE(20, case_macro);                     \
 458                 PMEVN_CASE(21, case_macro);                     \
 459                 PMEVN_CASE(22, case_macro);                     \
 460                 PMEVN_CASE(23, case_macro);                     \
 461                 PMEVN_CASE(24, case_macro);                     \
 462                 PMEVN_CASE(25, case_macro);                     \
 463                 PMEVN_CASE(26, case_macro);                     \
 464                 PMEVN_CASE(27, case_macro);                     \
 465                 PMEVN_CASE(28, case_macro);                     \
 466                 PMEVN_CASE(29, case_macro);                     \
 467                 PMEVN_CASE(30, case_macro);                     \
 468                 default: WARN(1, "Invalid PMEV* index\n");      \
 469                 }                                               \
 470         } while (0)
 471
 472 #define RETURN_READ_PMEVCNTRN(n) \
 473         return read_sysreg(pmevcntr##n##_el0)
 474 static unsigned long read_pmevcntrn(int n)
 475 {
 476         PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
 477         return 0;
 478 }
 479
 480 #define WRITE_PMEVCNTRN(n) \
 481         write_sysreg(val, pmevcntr##n##_el0)
 482 static void write_pmevcntrn(int n, unsigned long val)
 483 {
 484         PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
 485 }
 486
 487 #define WRITE_PMEVTYPERN(n) \
 488         write_sysreg(val, pmevtyper##n##_el0)
 489 static void write_pmevtypern(int n, unsigned long val)
 490 {
 491         PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
 492 }
 493
 494 static inline u32 armv8pmu_pmcr_read(void)
 495 {
 496         return read_sysreg(pmcr_el0);
 497 }
 498
 499 static inline void armv8pmu_pmcr_write(u32 val)
 500 {
 501         val &= ARMV8_PMU_PMCR_MASK;
 502         isb();
 503         write_sysreg(val, pmcr_el0);
 504 }
 505
 506 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 507 {
 508         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 509 }
 510
 511 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 512 {
 513         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 514 }
 515
 516 static inline u64 armv8pmu_read_evcntr(int idx)
 517 {
 518         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 519
 520         return read_pmevcntrn(counter);
 521 }
 522
 523 static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
 524 {
 525         int idx = event->hw.idx;
 526         u64 val = armv8pmu_read_evcntr(idx);
 527
 528         if (armv8pmu_event_is_chained(event))
 529                 val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
 530         return val;
 531 }
 532
 533 /*
 534  * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
 535  * is set the event counters also become 64-bit counters. Unless the
 536  * user has requested a long counter (attr.config1) then we want to
 537  * interrupt upon 32-bit overflow - we achieve this by applying a bias.
 538  */
 539 static bool armv8pmu_event_needs_bias(struct perf_event *event)
 540 {
 541         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 542         struct hw_perf_event *hwc = &event->hw;
 543         int idx = hwc->idx;
 544
 545         if (armv8pmu_event_is_64bit(event))
 546                 return false;
 547
 548         if (armv8pmu_has_long_event(cpu_pmu) ||
 549             idx == ARMV8_IDX_CYCLE_COUNTER)
 550                 return true;
 551
 552         return false;
 553 }
 554
 555 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
 556 {
 557         if (armv8pmu_event_needs_bias(event))
 558                 value |= GENMASK(63, 32);
 559
 560         return value;
 561 }
 562
 563 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
 564 {
 565         if (armv8pmu_event_needs_bias(event))
 566                 value &= ~GENMASK(63, 32);
 567
 568         return value;
 569 }
 570
 571 static u64 armv8pmu_read_counter(struct perf_event *event)
 572 {
 573         struct hw_perf_event *hwc = &event->hw;
 574         int idx = hwc->idx;
 575         u64 value;
 576
 577         if (idx == ARMV8_IDX_CYCLE_COUNTER)
 578                 value = read_sysreg(pmccntr_el0);
 579         else
 580                 value = armv8pmu_read_hw_counter(event);
 581
 582         return  armv8pmu_unbias_long_counter(event, value);
 583 }
 584
 585 static inline void armv8pmu_write_evcntr(int idx, u64 value)
 586 {
 587         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 588
 589         write_pmevcntrn(counter, value);
 590 }
 591
 592 static inline void armv8pmu_write_hw_counter(struct perf_event *event,
 593                                              u64 value)
 594 {
 595         int idx = event->hw.idx;
 596
 597         if (armv8pmu_event_is_chained(event)) {
 598                 armv8pmu_write_evcntr(idx, upper_32_bits(value));
 599                 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
 600         } else {
 601                 armv8pmu_write_evcntr(idx, value);
 602         }
 603 }
 604
 605 static void armv8pmu_write_counter(struct perf_event *event, u64 value)
 606 {
 607         struct hw_perf_event *hwc = &event->hw;
 608         int idx = hwc->idx;
 609
 610         value = armv8pmu_bias_long_counter(event, value);
 611
 612         if (idx == ARMV8_IDX_CYCLE_COUNTER)
 613                 write_sysreg(value, pmccntr_el0);
 614         else
 615                 armv8pmu_write_hw_counter(event, value);
 616 }
 617
 618 static inline void armv8pmu_write_evtype(int idx, u32 val)
 619 {
 620         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 621
 622         val &= ARMV8_PMU_EVTYPE_MASK;
 623         write_pmevtypern(counter, val);
 624 }
 625
 626 static inline void armv8pmu_write_event_type(struct perf_event *event)
 627 {
 628         struct hw_perf_event *hwc = &event->hw;
 629         int idx = hwc->idx;
 630
 631         /*
 632          * For chained events, the low counter is programmed to count
 633          * the event of interest and the high counter is programmed
 634          * with CHAIN event code with filters set to count at all ELs.
 635          */
 636         if (armv8pmu_event_is_chained(event)) {
 637                 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
 638                                 ARMV8_PMU_INCLUDE_EL2;
 639
 640                 armv8pmu_write_evtype(idx - 1, hwc->config_base);
 641                 armv8pmu_write_evtype(idx, chain_evt);
 642         } else {
 643                 if (idx == ARMV8_IDX_CYCLE_COUNTER)
 644                         write_sysreg(hwc->config_base, pmccfiltr_el0);
 645                 else
 646                         armv8pmu_write_evtype(idx, hwc->config_base);
 647         }
 648 }
 649
 650 static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
 651 {
 652         int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 653         u32 mask = BIT(counter);
 654
 655         if (armv8pmu_event_is_chained(event))
 656                 mask |= BIT(counter - 1);
 657         return mask;
 658 }
 659
 660 static inline void armv8pmu_enable_counter(u32 mask)
 661 {
 662         /*
 663          * Make sure event configuration register writes are visible before we
 664          * enable the counter.
 665          * */
 666         isb();
 667         write_sysreg(mask, pmcntenset_el0);
 668 }
 669
 670 static inline void armv8pmu_enable_event_counter(struct perf_event *event)
 671 {
 672         struct perf_event_attr *attr = &event->attr;
 673         u32 mask = armv8pmu_event_cnten_mask(event);
 674
 675         kvm_set_pmu_events(mask, attr);
 676
 677         /* We rely on the hypervisor switch code to enable guest counters */
 678         if (!kvm_pmu_counter_deferred(attr))
 679                 armv8pmu_enable_counter(mask);
 680 }
 681
 682 static inline void armv8pmu_disable_counter(u32 mask)
 683 {
 684         write_sysreg(mask, pmcntenclr_el0);
 685         /*
 686          * Make sure the effects of disabling the counter are visible before we
 687          * start configuring the event.
 688          */
 689         isb();
 690 }
 691
 692 static inline void armv8pmu_disable_event_counter(struct perf_event *event)
 693 {
 694         struct perf_event_attr *attr = &event->attr;
 695         u32 mask = armv8pmu_event_cnten_mask(event);
 696
 697         kvm_clr_pmu_events(mask);
 698
 699         /* We rely on the hypervisor switch code to disable guest counters */
 700         if (!kvm_pmu_counter_deferred(attr))
 701                 armv8pmu_disable_counter(mask);
 702 }
 703
 704 static inline void armv8pmu_enable_intens(u32 mask)
 705 {
 706         write_sysreg(mask, pmintenset_el1);
 707 }
 708
 709 static inline void armv8pmu_enable_event_irq(struct perf_event *event)
 710 {
 711         u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 712         armv8pmu_enable_intens(BIT(counter));
 713 }
 714
 715 static inline void armv8pmu_disable_intens(u32 mask)
 716 {
 717         write_sysreg(mask, pmintenclr_el1);
 718         isb();
 719         /* Clear the overflow flag in case an interrupt is pending. */
 720         write_sysreg(mask, pmovsclr_el0);
 721         isb();
 722 }
 723
 724 static inline void armv8pmu_disable_event_irq(struct perf_event *event)
 725 {
 726         u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 727         armv8pmu_disable_intens(BIT(counter));
 728 }
 729
 730 static inline u32 armv8pmu_getreset_flags(void)
 731 {
 732         u32 value;
 733
 734         /* Read */
 735         value = read_sysreg(pmovsclr_el0);
 736
 737         /* Write to clear flags */
 738         value &= ARMV8_PMU_OVSR_MASK;
 739         write_sysreg(value, pmovsclr_el0);
 740
 741         return value;
 742 }
 743
 744 static void armv8pmu_disable_user_access(void)
 745 {
 746         write_sysreg(0, pmuserenr_el0);
 747 }
 748
 749 static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu)
 750 {
 751         int i;
 752         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 753
 754         /* Clear any unused counters to avoid leaking their contents */
 755         for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) {
 756                 if (i == ARMV8_IDX_CYCLE_COUNTER)
 757                         write_sysreg(0, pmccntr_el0);
 758                 else
 759                         armv8pmu_write_evcntr(i, 0);
 760         }
 761
 762         write_sysreg(0, pmuserenr_el0);
 763         write_sysreg(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR, pmuserenr_el0);
 764 }
 765
 766 static void armv8pmu_enable_event(struct perf_event *event)
 767 {
 768         /*
 769          * Enable counter and interrupt, and set the counter to count
 770          * the event that we're interested in.
 771          */
 772
 773         /*
 774          * Disable counter
 775          */
 776         armv8pmu_disable_event_counter(event);
 777
 778         /*
 779          * Set event.
 780          */
 781         armv8pmu_write_event_type(event);
 782
 783         /*
 784          * Enable interrupt for this counter
 785          */
 786         armv8pmu_enable_event_irq(event);
 787
 788         /*
 789          * Enable counter
 790          */
 791         armv8pmu_enable_event_counter(event);
 792 }
 793
 794 static void armv8pmu_disable_event(struct perf_event *event)
 795 {
 796         /*
 797          * Disable counter
 798          */
 799         armv8pmu_disable_event_counter(event);
 800
 801         /*
 802          * Disable interrupt for this counter
 803          */
 804         armv8pmu_disable_event_irq(event);
 805 }
 806
 807 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 808 {
 809         struct perf_event_context *ctx;
 810         int nr_user = 0;
 811
 812         ctx = perf_cpu_task_ctx();
 813         if (ctx)
 814                 nr_user = ctx->nr_user;
 815
 816         if (sysctl_perf_user_access && nr_user)
 817                 armv8pmu_enable_user_access(cpu_pmu);
 818         else
 819                 armv8pmu_disable_user_access();
 820
 821         /* Enable all counters */
 822         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 823 }
 824
 825 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 826 {
 827         /* Disable all counters */
 828         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 829 }
 830
 831 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
 832 {
 833         u32 pmovsr;
 834         struct perf_sample_data data;
 835         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 836         struct pt_regs *regs;
 837         int idx;
 838
 839         /*
 840          * Get and reset the IRQ flags
 841          */
 842         pmovsr = armv8pmu_getreset_flags();
 843
 844         /*
 845          * Did an overflow occur?
 846          */
 847         if (!armv8pmu_has_overflowed(pmovsr))
 848                 return IRQ_NONE;
 849
 850         /*
 851          * Handle the counter(s) overflow(s)
 852          */
 853         regs = get_irq_regs();
 854
 855         /*
 856          * Stop the PMU while processing the counter overflows
 857          * to prevent skews in group events.
 858          */
 859         armv8pmu_stop(cpu_pmu);
 860         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 861                 struct perf_event *event = cpuc->events[idx];
 862                 struct hw_perf_event *hwc;
 863
 864                 /* Ignore if we don't have an event. */
 865                 if (!event)
 866                         continue;
 867
 868                 /*
 869                  * We have a single interrupt for all counters. Check that
 870                  * each counter has overflowed before we process it.
 871                  */
 872                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 873                         continue;
 874
 875                 hwc = &event->hw;
 876                 armpmu_event_update(event);
 877                 perf_sample_data_init(&data, 0, hwc->last_period);
 878                 if (!armpmu_event_set_period(event))
 879                         continue;
 880
 881                 /*
 882                  * Perf event overflow will queue the processing of the event as
 883                  * an irq_work which will be taken care of in the handling of
 884                  * IPI_IRQ_WORK.
 885                  */
 886                 if (perf_event_overflow(event, &data, regs))
 887                         cpu_pmu->disable(event);
 888         }
 889         armv8pmu_start(cpu_pmu);
 890
 891         return IRQ_HANDLED;
 892 }
 893
 894 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
 895                                     struct arm_pmu *cpu_pmu)
 896 {
 897         int idx;
 898
 899         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) {
 900                 if (!test_and_set_bit(idx, cpuc->used_mask))
 901                         return idx;
 902         }
 903         return -EAGAIN;
 904 }
 905
 906 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
 907                                    struct arm_pmu *cpu_pmu)
 908 {
 909         int idx;
 910
 911         /*
 912          * Chaining requires two consecutive event counters, where
 913          * the lower idx must be even.
 914          */
 915         for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
 916                 if (!test_and_set_bit(idx, cpuc->used_mask)) {
 917                         /* Check if the preceding even counter is available */
 918                         if (!test_and_set_bit(idx - 1, cpuc->used_mask))
 919                                 return idx;
 920                         /* Release the Odd counter */
 921                         clear_bit(idx, cpuc->used_mask);
 922                 }
 923         }
 924         return -EAGAIN;
 925 }
 926
 927 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 928                                   struct perf_event *event)
 929 {
 930         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 931         struct hw_perf_event *hwc = &event->hw;
 932         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 933
 934         /* Always prefer to place a cycle counter into the cycle counter. */
 935         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 936                 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 937                         return ARMV8_IDX_CYCLE_COUNTER;
 938                 else if (armv8pmu_event_is_64bit(event) &&
 939                            armv8pmu_event_want_user_access(event) &&
 940                            !armv8pmu_has_long_event(cpu_pmu))
 941                                 return -EAGAIN;
 942         }
 943
 944         /*
 945          * Otherwise use events counters
 946          */
 947         if (armv8pmu_event_is_chained(event))
 948                 return  armv8pmu_get_chain_idx(cpuc, cpu_pmu);
 949         else
 950                 return armv8pmu_get_single_idx(cpuc, cpu_pmu);
 951 }
 952
 953 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
 954                                      struct perf_event *event)
 955 {
 956         int idx = event->hw.idx;
 957
 958         clear_bit(idx, cpuc->used_mask);
 959         if (armv8pmu_event_is_chained(event))
 960                 clear_bit(idx - 1, cpuc->used_mask);
 961 }
 962
 963 static int armv8pmu_user_event_idx(struct perf_event *event)
 964 {
 965         if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event))
 966                 return 0;
 967
 968         /*
 969          * We remap the cycle counter index to 32 to
 970          * match the offset applied to the rest of
 971          * the counter indices.
 972          */
 973         if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
 974                 return ARMV8_IDX_CYCLE_COUNTER_USER;
 975
 976         return event->hw.idx;
 977 }
 978
 979 /*
 980  * Add an event filter to a given event.
 981  */
 982 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 983                                      struct perf_event_attr *attr)
 984 {
 985         unsigned long config_base = 0;
 986
 987         if (attr->exclude_idle)
 988                 return -EPERM;
 989
 990         /*
 991          * If we're running in hyp mode, then we *are* the hypervisor.
 992          * Therefore we ignore exclude_hv in this configuration, since
 993          * there's no hypervisor to sample anyway. This is consistent
 994          * with other architectures (x86 and Power).
 995          */
 996         if (is_kernel_in_hyp_mode()) {
 997                 if (!attr->exclude_kernel && !attr->exclude_host)
 998                         config_base |= ARMV8_PMU_INCLUDE_EL2;
 999                 if (attr->exclude_guest)
1000                         config_base |= ARMV8_PMU_EXCLUDE_EL1;
1001                 if (attr->exclude_host)
1002                         config_base |= ARMV8_PMU_EXCLUDE_EL0;
1003         } else {
1004                 if (!attr->exclude_hv && !attr->exclude_host)
1005                         config_base |= ARMV8_PMU_INCLUDE_EL2;
1006         }
1007
1008         /*
1009          * Filter out !VHE kernels and guest kernels
1010          */
1011         if (attr->exclude_kernel)
1012                 config_base |= ARMV8_PMU_EXCLUDE_EL1;
1013
1014         if (attr->exclude_user)
1015                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
1016
1017         /*
1018          * Install the filter into config_base as this is used to
1019          * construct the event type.
1020          */
1021         event->config_base = config_base;
1022
1023         return 0;
1024 }
1025
1026 static bool armv8pmu_filter(struct pmu *pmu, int cpu)
1027 {
1028         struct arm_pmu *armpmu = to_arm_pmu(pmu);
1029         return !cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus);
1030 }
1031
1032 static void armv8pmu_reset(void *info)
1033 {
1034         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
1035         u32 pmcr;
1036
1037         /* The counter and interrupt enable registers are unknown at reset. */
1038         armv8pmu_disable_counter(U32_MAX);
1039         armv8pmu_disable_intens(U32_MAX);
1040
1041         /* Clear the counters we flip at guest entry/exit */
1042         kvm_clr_pmu_events(U32_MAX);
1043
1044         /*
1045          * Initialize & Reset PMNC. Request overflow interrupt for
1046          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
1047          */
1048         pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
1049
1050         /* Enable long event counter support where available */
1051         if (armv8pmu_has_long_event(cpu_pmu))
1052                 pmcr |= ARMV8_PMU_PMCR_LP;
1053
1054         armv8pmu_pmcr_write(pmcr);
1055 }
1056
1057 static int __armv8_pmuv3_map_event(struct perf_event *event,
1058                                    const unsigned (*extra_event_map)
1059                                                   [PERF_COUNT_HW_MAX],
1060                                    const unsigned (*extra_cache_map)
1061                                                   [PERF_COUNT_HW_CACHE_MAX]
1062                                                   [PERF_COUNT_HW_CACHE_OP_MAX]
1063                                                   [PERF_COUNT_HW_CACHE_RESULT_MAX])
1064 {
1065         int hw_event_id;
1066         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
1067
1068         hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
1069                                        &armv8_pmuv3_perf_cache_map,
1070                                        ARMV8_PMU_EVTYPE_EVENT);
1071
1072         if (armv8pmu_event_is_64bit(event))
1073                 event->hw.flags |= ARMPMU_EVT_64BIT;
1074
1075         /*
1076          * User events must be allocated into a single counter, and so
1077          * must not be chained.
1078          *
1079          * Most 64-bit events require long counter support, but 64-bit
1080          * CPU_CYCLES events can be placed into the dedicated cycle
1081          * counter when this is free.
1082          */
1083         if (armv8pmu_event_want_user_access(event)) {
1084                 if (!(event->attach_state & PERF_ATTACH_TASK))
1085                         return -EINVAL;
1086                 if (armv8pmu_event_is_64bit(event) &&
1087                     (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) &&
1088                     !armv8pmu_has_long_event(armpmu))
1089                         return -EOPNOTSUPP;
1090
1091                 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
1092         }
1093
1094         /* Only expose micro/arch events supported by this PMU */
1095         if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
1096             && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
1097                 return hw_event_id;
1098         }
1099
1100         return armpmu_map_event(event, extra_event_map, extra_cache_map,
1101                                 ARMV8_PMU_EVTYPE_EVENT);
1102 }
1103
1104 static int armv8_pmuv3_map_event(struct perf_event *event)
1105 {
1106         return __armv8_pmuv3_map_event(event, NULL, NULL);
1107 }
1108
1109 static int armv8_a53_map_event(struct perf_event *event)
1110 {
1111         return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
1112 }
1113
1114 static int armv8_a57_map_event(struct perf_event *event)
1115 {
1116         return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
1117 }
1118
1119 static int armv8_a73_map_event(struct perf_event *event)
1120 {
1121         return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
1122 }
1123
1124 static int armv8_thunder_map_event(struct perf_event *event)
1125 {
1126         return __armv8_pmuv3_map_event(event, NULL,
1127                                        &armv8_thunder_perf_cache_map);
1128 }
1129
1130 static int armv8_vulcan_map_event(struct perf_event *event)
1131 {
1132         return __armv8_pmuv3_map_event(event, NULL,
1133                                        &armv8_vulcan_perf_cache_map);
1134 }
1135
1136 struct armv8pmu_probe_info {
1137         struct arm_pmu *pmu;
1138         bool present;
1139 };
1140
1141 static void __armv8pmu_probe_pmu(void *info)
1142 {
1143         struct armv8pmu_probe_info *probe = info;
1144         struct arm_pmu *cpu_pmu = probe->pmu;
1145         u64 dfr0;
1146         u64 pmceid_raw[2];
1147         u32 pmceid[2];
1148         int pmuver;
1149
1150         dfr0 = read_sysreg(id_aa64dfr0_el1);
1151         pmuver = cpuid_feature_extract_unsigned_field(dfr0,
1152                         ID_AA64DFR0_EL1_PMUVer_SHIFT);
1153         if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF ||
1154             pmuver == ID_AA64DFR0_EL1_PMUVer_NI)
1155                 return;
1156
1157         cpu_pmu->pmuver = pmuver;
1158         probe->present = true;
1159
1160         /* Read the nb of CNTx counters supported from PMNC */
1161         cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
1162                 & ARMV8_PMU_PMCR_N_MASK;
1163
1164         /* Add the CPU cycles counter */
1165         cpu_pmu->num_events += 1;
1166
1167         pmceid[0] = pmceid_raw[0] = read_sysreg(pmceid0_el0);
1168         pmceid[1] = pmceid_raw[1] = read_sysreg(pmceid1_el0);
1169
1170         bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1171                              pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1172
1173         pmceid[0] = pmceid_raw[0] >> 32;
1174         pmceid[1] = pmceid_raw[1] >> 32;
1175
1176         bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1177                              pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1178
1179         /* store PMMIR_EL1 register for sysfs */
1180         if (pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4 && (pmceid_raw[1] & BIT(31)))
1181                 cpu_pmu->reg_pmmir = read_cpuid(PMMIR_EL1);
1182         else
1183                 cpu_pmu->reg_pmmir = 0;
1184 }
1185
1186 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1187 {
1188         struct armv8pmu_probe_info probe = {
1189                 .pmu = cpu_pmu,
1190                 .present = false,
1191         };
1192         int ret;
1193
1194         ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1195                                     __armv8pmu_probe_pmu,
1196                                     &probe, 1);
1197         if (ret)
1198                 return ret;
1199
1200         return probe.present ? 0 : -ENODEV;
1201 }
1202
1203 static void armv8pmu_disable_user_access_ipi(void *unused)
1204 {
1205         armv8pmu_disable_user_access();
1206 }
1207
1208 static int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write,
1209                 void *buffer, size_t *lenp, loff_t *ppos)
1210 {
1211         int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
1212         if (ret || !write || sysctl_perf_user_access)
1213                 return ret;
1214
1215         on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1);
1216         return 0;
1217 }
1218
1219 static struct ctl_table armv8_pmu_sysctl_table[] = {
1220         {
1221                 .procname       = "perf_user_access",
1222                 .data           = &sysctl_perf_user_access,
1223                 .maxlen         = sizeof(unsigned int),
1224                 .mode           = 0644,
1225                 .proc_handler   = armv8pmu_proc_user_access_handler,
1226                 .extra1         = SYSCTL_ZERO,
1227                 .extra2         = SYSCTL_ONE,
1228         },
1229         { }
1230 };
1231
1232 static void armv8_pmu_register_sysctl_table(void)
1233 {
1234         static u32 tbl_registered = 0;
1235
1236         if (!cmpxchg_relaxed(&tbl_registered, 0, 1))
1237                 register_sysctl("kernel", armv8_pmu_sysctl_table);
1238 }
1239
1240 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1241                           int (*map_event)(struct perf_event *event),
1242                           const struct attribute_group *events,
1243                           const struct attribute_group *format,
1244                           const struct attribute_group *caps)
1245 {
1246         int ret = armv8pmu_probe_pmu(cpu_pmu);
1247         if (ret)
1248                 return ret;
1249
1250         cpu_pmu->handle_irq             = armv8pmu_handle_irq;
1251         cpu_pmu->enable                 = armv8pmu_enable_event;
1252         cpu_pmu->disable                = armv8pmu_disable_event;
1253         cpu_pmu->read_counter           = armv8pmu_read_counter;
1254         cpu_pmu->write_counter          = armv8pmu_write_counter;
1255         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx;
1256         cpu_pmu->clear_event_idx        = armv8pmu_clear_event_idx;
1257         cpu_pmu->start                  = armv8pmu_start;
1258         cpu_pmu->stop                   = armv8pmu_stop;
1259         cpu_pmu->reset                  = armv8pmu_reset;
1260         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
1261         cpu_pmu->filter                 = armv8pmu_filter;
1262
1263         cpu_pmu->pmu.event_idx          = armv8pmu_user_event_idx;
1264
1265         cpu_pmu->name                   = name;
1266         cpu_pmu->map_event              = map_event;
1267         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
1268                         events : &armv8_pmuv3_events_attr_group;
1269         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
1270                         format : &armv8_pmuv3_format_attr_group;
1271         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
1272                         caps : &armv8_pmuv3_caps_attr_group;
1273
1274         armv8_pmu_register_sysctl_table();
1275         return 0;
1276 }
1277
1278 static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
1279                                    int (*map_event)(struct perf_event *event))
1280 {
1281         return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
1282 }
1283
1284 #define PMUV3_INIT_SIMPLE(name)                                         \
1285 static int name##_pmu_init(struct arm_pmu *cpu_pmu)                     \
1286 {                                                                       \
1287         return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\
1288 }
1289
1290 PMUV3_INIT_SIMPLE(armv8_pmuv3)
1291
1292 PMUV3_INIT_SIMPLE(armv8_cortex_a34)
1293 PMUV3_INIT_SIMPLE(armv8_cortex_a55)
1294 PMUV3_INIT_SIMPLE(armv8_cortex_a65)
1295 PMUV3_INIT_SIMPLE(armv8_cortex_a75)
1296 PMUV3_INIT_SIMPLE(armv8_cortex_a76)
1297 PMUV3_INIT_SIMPLE(armv8_cortex_a77)
1298 PMUV3_INIT_SIMPLE(armv8_cortex_a78)
1299 PMUV3_INIT_SIMPLE(armv9_cortex_a510)
1300 PMUV3_INIT_SIMPLE(armv9_cortex_a710)
1301 PMUV3_INIT_SIMPLE(armv8_cortex_x1)
1302 PMUV3_INIT_SIMPLE(armv9_cortex_x2)
1303 PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
1304 PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
1305 PMUV3_INIT_SIMPLE(armv9_neoverse_n2)
1306 PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
1307
1308 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
1309 PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
1310
1311 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
1312 {
1313         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
1314                                        armv8_a53_map_event);
1315 }
1316
1317 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1318 {
1319         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
1320                                        armv8_a53_map_event);
1321 }
1322
1323 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1324 {
1325         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
1326                                        armv8_a57_map_event);
1327 }
1328
1329 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1330 {
1331         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
1332                                        armv8_a57_map_event);
1333 }
1334
1335 static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1336 {
1337         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
1338                                        armv8_a73_map_event);
1339 }
1340
1341 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1342 {
1343         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
1344                                        armv8_thunder_map_event);
1345 }
1346
1347 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1348 {
1349         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
1350                                        armv8_vulcan_map_event);
1351 }
1352
1353 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1354         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_pmu_init},
1355         {.compatible = "arm,cortex-a34-pmu",    .data = armv8_cortex_a34_pmu_init},
1356         {.compatible = "arm,cortex-a35-pmu",    .data = armv8_a35_pmu_init},
1357         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
1358         {.compatible = "arm,cortex-a55-pmu",    .data = armv8_cortex_a55_pmu_init},
1359         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
1360         {.compatible = "arm,cortex-a65-pmu",    .data = armv8_cortex_a65_pmu_init},
1361         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
1362         {.compatible = "arm,cortex-a73-pmu",    .data = armv8_a73_pmu_init},
1363         {.compatible = "arm,cortex-a75-pmu",    .data = armv8_cortex_a75_pmu_init},
1364         {.compatible = "arm,cortex-a76-pmu",    .data = armv8_cortex_a76_pmu_init},
1365         {.compatible = "arm,cortex-a77-pmu",    .data = armv8_cortex_a77_pmu_init},
1366         {.compatible = "arm,cortex-a78-pmu",    .data = armv8_cortex_a78_pmu_init},
1367         {.compatible = "arm,cortex-a510-pmu",   .data = armv9_cortex_a510_pmu_init},
1368         {.compatible = "arm,cortex-a710-pmu",   .data = armv9_cortex_a710_pmu_init},
1369         {.compatible = "arm,cortex-x1-pmu",     .data = armv8_cortex_x1_pmu_init},
1370         {.compatible = "arm,cortex-x2-pmu",     .data = armv9_cortex_x2_pmu_init},
1371         {.compatible = "arm,neoverse-e1-pmu",   .data = armv8_neoverse_e1_pmu_init},
1372         {.compatible = "arm,neoverse-n1-pmu",   .data = armv8_neoverse_n1_pmu_init},
1373         {.compatible = "arm,neoverse-n2-pmu",   .data = armv9_neoverse_n2_pmu_init},
1374         {.compatible = "arm,neoverse-v1-pmu",   .data = armv8_neoverse_v1_pmu_init},
1375         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
1376         {.compatible = "brcm,vulcan-pmu",       .data = armv8_vulcan_pmu_init},
1377         {.compatible = "nvidia,carmel-pmu",     .data = armv8_nvidia_carmel_pmu_init},
1378         {.compatible = "nvidia,denver-pmu",     .data = armv8_nvidia_denver_pmu_init},
1379         {},
1380 };
1381
1382 static int armv8_pmu_device_probe(struct platform_device *pdev)
1383 {
1384         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1385 }
1386
1387 static struct platform_driver armv8_pmu_driver = {
1388         .driver         = {
1389                 .name   = ARMV8_PMU_PDEV_NAME,
1390                 .of_match_table = armv8_pmu_of_device_ids,
1391                 .suppress_bind_attrs = true,
1392         },
1393         .probe          = armv8_pmu_device_probe,
1394 };
1395
1396 static int __init armv8_pmu_driver_init(void)
1397 {
1398         if (acpi_disabled)
1399                 return platform_driver_register(&armv8_pmu_driver);
1400         else
1401                 return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init);
1402 }
1403 device_initcall(armv8_pmu_driver_init)
1404
1405 void arch_perf_update_userpage(struct perf_event *event,
1406                                struct perf_event_mmap_page *userpg, u64 now)
1407 {
1408         struct clock_read_data *rd;
1409         unsigned int seq;
1410         u64 ns;
1411
1412         userpg->cap_user_time = 0;
1413         userpg->cap_user_time_zero = 0;
1414         userpg->cap_user_time_short = 0;
1415         userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event);
1416
1417         if (userpg->cap_user_rdpmc) {
1418                 if (event->hw.flags & ARMPMU_EVT_64BIT)
1419                         userpg->pmc_width = 64;
1420                 else
1421                         userpg->pmc_width = 32;
1422         }
1423
1424         do {
1425                 rd = sched_clock_read_begin(&seq);
1426
1427                 if (rd->read_sched_clock != arch_timer_read_counter)
1428                         return;
1429
1430                 userpg->time_mult = rd->mult;
1431                 userpg->time_shift = rd->shift;
1432                 userpg->time_zero = rd->epoch_ns;
1433                 userpg->time_cycles = rd->epoch_cyc;
1434                 userpg->time_mask = rd->sched_clock_mask;
1435
1436                 /*
1437                  * Subtract the cycle base, such that software that
1438                  * doesn't know about cap_user_time_short still 'works'
1439                  * assuming no wraps.
1440                  */
1441                 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1442                 userpg->time_zero -= ns;
1443
1444         } while (sched_clock_read_retry(seq));
1445
1446         userpg->time_offset = userpg->time_zero - now;
1447
1448         /*
1449          * time_shift is not expected to be greater than 31 due to
1450          * the original published conversion algorithm shifting a
1451          * 32-bit value (now specifies a 64-bit value) - refer
1452          * perf_event_mmap_page documentation in perf_event.h.
1453          */
1454         if (userpg->time_shift == 32) {
1455                 userpg->time_shift = 31;
1456                 userpg->time_mult >>= 1;
1457         }
1458
1459         /*
1460          * Internal timekeeping for enabled/running/stopped times
1461          * is always computed with the sched_clock.
1462          */
1463         userpg->cap_user_time = 1;
1464         userpg->cap_user_time_zero = 1;
1465         userpg->cap_user_time_short = 1;
1466 }