drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "intel_dsi.h"
  40 #include "i915_trace.h"
  41 #include <drm/drm_atomic.h>
  42 #include <drm/drm_atomic_helper.h>
  43 #include <drm/drm_dp_helper.h>
  44 #include <drm/drm_crtc_helper.h>
  45 #include <drm/drm_plane_helper.h>
  46 #include <drm/drm_rect.h>
  47 #include <linux/dma_remapping.h>
  48 #include <linux/reservation.h>
  49 #include <linux/dma-buf.h>
  50
  51 /* Primary plane formats for gen <= 3 */
  52 static const uint32_t i8xx_primary_formats[] = {
  53         DRM_FORMAT_C8,
  54         DRM_FORMAT_RGB565,
  55         DRM_FORMAT_XRGB1555,
  56         DRM_FORMAT_XRGB8888,
  57 };
  58
  59 /* Primary plane formats for gen >= 4 */
  60 static const uint32_t i965_primary_formats[] = {
  61         DRM_FORMAT_C8,
  62         DRM_FORMAT_RGB565,
  63         DRM_FORMAT_XRGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_XBGR2101010,
  67 };
  68
  69 static const uint32_t skl_primary_formats[] = {
  70         DRM_FORMAT_C8,
  71         DRM_FORMAT_RGB565,
  72         DRM_FORMAT_XRGB8888,
  73         DRM_FORMAT_XBGR8888,
  74         DRM_FORMAT_ARGB8888,
  75         DRM_FORMAT_ABGR8888,
  76         DRM_FORMAT_XRGB2101010,
  77         DRM_FORMAT_XBGR2101010,
  78         DRM_FORMAT_YUYV,
  79         DRM_FORMAT_YVYU,
  80         DRM_FORMAT_UYVY,
  81         DRM_FORMAT_VYUY,
  82 };
  83
  84 /* Cursor formats */
  85 static const uint32_t intel_cursor_formats[] = {
  86         DRM_FORMAT_ARGB8888,
  87 };
  88
  89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  90                                 struct intel_crtc_state *pipe_config);
  91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  92                                    struct intel_crtc_state *pipe_config);
  93
  94 static int intel_framebuffer_init(struct drm_device *dev,
  95                                   struct intel_framebuffer *ifb,
  96                                   struct drm_mode_fb_cmd2 *mode_cmd,
  97                                   struct drm_i915_gem_object *obj);
  98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 102                                          struct intel_link_m_n *m_n,
 103                                          struct intel_link_m_n *m2_n2);
 104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 107 static void vlv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void chv_prepare_pll(struct intel_crtc *crtc,
 110                             const struct intel_crtc_state *pipe_config);
 111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 114         struct intel_crtc_state *crtc_state);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 /* returns HPLL frequency in kHz */
 137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 138 {
 139         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 140
 141         /* Obtain SKU information */
 142         mutex_lock(&dev_priv->sb_lock);
 143         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 144                 CCK_FUSE_HPLL_FREQ_MASK;
 145         mutex_unlock(&dev_priv->sb_lock);
 146
 147         return vco_freq[hpll_freq] * 1000;
 148 }
 149
 150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 151                       const char *name, u32 reg, int ref_freq)
 152 {
 153         u32 val;
 154         int divider;
 155
 156         mutex_lock(&dev_priv->sb_lock);
 157         val = vlv_cck_read(dev_priv, reg);
 158         mutex_unlock(&dev_priv->sb_lock);
 159
 160         divider = val & CCK_FREQUENCY_VALUES;
 161
 162         WARN((val & CCK_FREQUENCY_STATUS) !=
 163              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 164              "%s change in progress\n", name);
 165
 166         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 167 }
 168
 169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 170                                   const char *name, u32 reg)
 171 {
 172         if (dev_priv->hpll_freq == 0)
 173                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 174
 175         return vlv_get_cck_clock(dev_priv, name, reg,
 176                                  dev_priv->hpll_freq);
 177 }
 178
 179 static int
 180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 181 {
 182         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 183 }
 184
 185 static int
 186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 187 {
 188         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 189                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 190 }
 191
 192 static int
 193 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 194 {
 195         uint32_t clkcfg;
 196
 197         /* hrawclock is 1/4 the FSB frequency */
 198         clkcfg = I915_READ(CLKCFG);
 199         switch (clkcfg & CLKCFG_FSB_MASK) {
 200         case CLKCFG_FSB_400:
 201                 return 100000;
 202         case CLKCFG_FSB_533:
 203                 return 133333;
 204         case CLKCFG_FSB_667:
 205                 return 166667;
 206         case CLKCFG_FSB_800:
 207                 return 200000;
 208         case CLKCFG_FSB_1067:
 209                 return 266667;
 210         case CLKCFG_FSB_1333:
 211                 return 333333;
 212         /* these two are just a guess; one of them might be right */
 213         case CLKCFG_FSB_1600:
 214         case CLKCFG_FSB_1600_ALT:
 215                 return 400000;
 216         default:
 217                 return 133333;
 218         }
 219 }
 220
 221 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
 222 {
 223         if (HAS_PCH_SPLIT(dev_priv))
 224                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 225         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 226                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 227         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 228                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 229         else
 230                 return; /* no rawclk on other platforms, or no need to know it */
 231
 232         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 233 }
 234
 235 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 236 {
 237         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 238                 return;
 239
 240         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 241                                                       CCK_CZ_CLOCK_CONTROL);
 242
 243         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 244 }
 245
 246 static inline u32 /* units of 100MHz */
 247 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 248                     const struct intel_crtc_state *pipe_config)
 249 {
 250         if (HAS_DDI(dev_priv))
 251                 return pipe_config->port_clock; /* SPLL */
 252         else if (IS_GEN5(dev_priv))
 253                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 254         else
 255                 return 270000;
 256 }
 257
 258 static const intel_limit_t intel_limits_i8xx_dac = {
 259         .dot = { .min = 25000, .max = 350000 },
 260         .vco = { .min = 908000, .max = 1512000 },
 261         .n = { .min = 2, .max = 16 },
 262         .m = { .min = 96, .max = 140 },
 263         .m1 = { .min = 18, .max = 26 },
 264         .m2 = { .min = 6, .max = 16 },
 265         .p = { .min = 4, .max = 128 },
 266         .p1 = { .min = 2, .max = 33 },
 267         .p2 = { .dot_limit = 165000,
 268                 .p2_slow = 4, .p2_fast = 2 },
 269 };
 270
 271 static const intel_limit_t intel_limits_i8xx_dvo = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 908000, .max = 1512000 },
 274         .n = { .min = 2, .max = 16 },
 275         .m = { .min = 96, .max = 140 },
 276         .m1 = { .min = 18, .max = 26 },
 277         .m2 = { .min = 6, .max = 16 },
 278         .p = { .min = 4, .max = 128 },
 279         .p1 = { .min = 2, .max = 33 },
 280         .p2 = { .dot_limit = 165000,
 281                 .p2_slow = 4, .p2_fast = 4 },
 282 };
 283
 284 static const intel_limit_t intel_limits_i8xx_lvds = {
 285         .dot = { .min = 25000, .max = 350000 },
 286         .vco = { .min = 908000, .max = 1512000 },
 287         .n = { .min = 2, .max = 16 },
 288         .m = { .min = 96, .max = 140 },
 289         .m1 = { .min = 18, .max = 26 },
 290         .m2 = { .min = 6, .max = 16 },
 291         .p = { .min = 4, .max = 128 },
 292         .p1 = { .min = 1, .max = 6 },
 293         .p2 = { .dot_limit = 165000,
 294                 .p2_slow = 14, .p2_fast = 7 },
 295 };
 296
 297 static const intel_limit_t intel_limits_i9xx_sdvo = {
 298         .dot = { .min = 20000, .max = 400000 },
 299         .vco = { .min = 1400000, .max = 2800000 },
 300         .n = { .min = 1, .max = 6 },
 301         .m = { .min = 70, .max = 120 },
 302         .m1 = { .min = 8, .max = 18 },
 303         .m2 = { .min = 3, .max = 7 },
 304         .p = { .min = 5, .max = 80 },
 305         .p1 = { .min = 1, .max = 8 },
 306         .p2 = { .dot_limit = 200000,
 307                 .p2_slow = 10, .p2_fast = 5 },
 308 };
 309
 310 static const intel_limit_t intel_limits_i9xx_lvds = {
 311         .dot = { .min = 20000, .max = 400000 },
 312         .vco = { .min = 1400000, .max = 2800000 },
 313         .n = { .min = 1, .max = 6 },
 314         .m = { .min = 70, .max = 120 },
 315         .m1 = { .min = 8, .max = 18 },
 316         .m2 = { .min = 3, .max = 7 },
 317         .p = { .min = 7, .max = 98 },
 318         .p1 = { .min = 1, .max = 8 },
 319         .p2 = { .dot_limit = 112000,
 320                 .p2_slow = 14, .p2_fast = 7 },
 321 };
 322
 323
 324 static const intel_limit_t intel_limits_g4x_sdvo = {
 325         .dot = { .min = 25000, .max = 270000 },
 326         .vco = { .min = 1750000, .max = 3500000},
 327         .n = { .min = 1, .max = 4 },
 328         .m = { .min = 104, .max = 138 },
 329         .m1 = { .min = 17, .max = 23 },
 330         .m2 = { .min = 5, .max = 11 },
 331         .p = { .min = 10, .max = 30 },
 332         .p1 = { .min = 1, .max = 3},
 333         .p2 = { .dot_limit = 270000,
 334                 .p2_slow = 10,
 335                 .p2_fast = 10
 336         },
 337 };
 338
 339 static const intel_limit_t intel_limits_g4x_hdmi = {
 340         .dot = { .min = 22000, .max = 400000 },
 341         .vco = { .min = 1750000, .max = 3500000},
 342         .n = { .min = 1, .max = 4 },
 343         .m = { .min = 104, .max = 138 },
 344         .m1 = { .min = 16, .max = 23 },
 345         .m2 = { .min = 5, .max = 11 },
 346         .p = { .min = 5, .max = 80 },
 347         .p1 = { .min = 1, .max = 8},
 348         .p2 = { .dot_limit = 165000,
 349                 .p2_slow = 10, .p2_fast = 5 },
 350 };
 351
 352 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 353         .dot = { .min = 20000, .max = 115000 },
 354         .vco = { .min = 1750000, .max = 3500000 },
 355         .n = { .min = 1, .max = 3 },
 356         .m = { .min = 104, .max = 138 },
 357         .m1 = { .min = 17, .max = 23 },
 358         .m2 = { .min = 5, .max = 11 },
 359         .p = { .min = 28, .max = 112 },
 360         .p1 = { .min = 2, .max = 8 },
 361         .p2 = { .dot_limit = 0,
 362                 .p2_slow = 14, .p2_fast = 14
 363         },
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 367         .dot = { .min = 80000, .max = 224000 },
 368         .vco = { .min = 1750000, .max = 3500000 },
 369         .n = { .min = 1, .max = 3 },
 370         .m = { .min = 104, .max = 138 },
 371         .m1 = { .min = 17, .max = 23 },
 372         .m2 = { .min = 5, .max = 11 },
 373         .p = { .min = 14, .max = 42 },
 374         .p1 = { .min = 2, .max = 6 },
 375         .p2 = { .dot_limit = 0,
 376                 .p2_slow = 7, .p2_fast = 7
 377         },
 378 };
 379
 380 static const intel_limit_t intel_limits_pineview_sdvo = {
 381         .dot = { .min = 20000, .max = 400000},
 382         .vco = { .min = 1700000, .max = 3500000 },
 383         /* Pineview's Ncounter is a ring counter */
 384         .n = { .min = 3, .max = 6 },
 385         .m = { .min = 2, .max = 256 },
 386         /* Pineview only has one combined m divider, which we treat as m2. */
 387         .m1 = { .min = 0, .max = 0 },
 388         .m2 = { .min = 0, .max = 254 },
 389         .p = { .min = 5, .max = 80 },
 390         .p1 = { .min = 1, .max = 8 },
 391         .p2 = { .dot_limit = 200000,
 392                 .p2_slow = 10, .p2_fast = 5 },
 393 };
 394
 395 static const intel_limit_t intel_limits_pineview_lvds = {
 396         .dot = { .min = 20000, .max = 400000 },
 397         .vco = { .min = 1700000, .max = 3500000 },
 398         .n = { .min = 3, .max = 6 },
 399         .m = { .min = 2, .max = 256 },
 400         .m1 = { .min = 0, .max = 0 },
 401         .m2 = { .min = 0, .max = 254 },
 402         .p = { .min = 7, .max = 112 },
 403         .p1 = { .min = 1, .max = 8 },
 404         .p2 = { .dot_limit = 112000,
 405                 .p2_slow = 14, .p2_fast = 14 },
 406 };
 407
 408 /* Ironlake / Sandybridge
 409  *
 410  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 411  * the range value for them is (actual_value - 2).
 412  */
 413 static const intel_limit_t intel_limits_ironlake_dac = {
 414         .dot = { .min = 25000, .max = 350000 },
 415         .vco = { .min = 1760000, .max = 3510000 },
 416         .n = { .min = 1, .max = 5 },
 417         .m = { .min = 79, .max = 127 },
 418         .m1 = { .min = 12, .max = 22 },
 419         .m2 = { .min = 5, .max = 9 },
 420         .p = { .min = 5, .max = 80 },
 421         .p1 = { .min = 1, .max = 8 },
 422         .p2 = { .dot_limit = 225000,
 423                 .p2_slow = 10, .p2_fast = 5 },
 424 };
 425
 426 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 427         .dot = { .min = 25000, .max = 350000 },
 428         .vco = { .min = 1760000, .max = 3510000 },
 429         .n = { .min = 1, .max = 3 },
 430         .m = { .min = 79, .max = 118 },
 431         .m1 = { .min = 12, .max = 22 },
 432         .m2 = { .min = 5, .max = 9 },
 433         .p = { .min = 28, .max = 112 },
 434         .p1 = { .min = 2, .max = 8 },
 435         .p2 = { .dot_limit = 225000,
 436                 .p2_slow = 14, .p2_fast = 14 },
 437 };
 438
 439 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 440         .dot = { .min = 25000, .max = 350000 },
 441         .vco = { .min = 1760000, .max = 3510000 },
 442         .n = { .min = 1, .max = 3 },
 443         .m = { .min = 79, .max = 127 },
 444         .m1 = { .min = 12, .max = 22 },
 445         .m2 = { .min = 5, .max = 9 },
 446         .p = { .min = 14, .max = 56 },
 447         .p1 = { .min = 2, .max = 8 },
 448         .p2 = { .dot_limit = 225000,
 449                 .p2_slow = 7, .p2_fast = 7 },
 450 };
 451
 452 /* LVDS 100mhz refclk limits. */
 453 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 454         .dot = { .min = 25000, .max = 350000 },
 455         .vco = { .min = 1760000, .max = 3510000 },
 456         .n = { .min = 1, .max = 2 },
 457         .m = { .min = 79, .max = 126 },
 458         .m1 = { .min = 12, .max = 22 },
 459         .m2 = { .min = 5, .max = 9 },
 460         .p = { .min = 28, .max = 112 },
 461         .p1 = { .min = 2, .max = 8 },
 462         .p2 = { .dot_limit = 225000,
 463                 .p2_slow = 14, .p2_fast = 14 },
 464 };
 465
 466 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 467         .dot = { .min = 25000, .max = 350000 },
 468         .vco = { .min = 1760000, .max = 3510000 },
 469         .n = { .min = 1, .max = 3 },
 470         .m = { .min = 79, .max = 126 },
 471         .m1 = { .min = 12, .max = 22 },
 472         .m2 = { .min = 5, .max = 9 },
 473         .p = { .min = 14, .max = 42 },
 474         .p1 = { .min = 2, .max = 6 },
 475         .p2 = { .dot_limit = 225000,
 476                 .p2_slow = 7, .p2_fast = 7 },
 477 };
 478
 479 static const intel_limit_t intel_limits_vlv = {
 480          /*
 481           * These are the data rate limits (measured in fast clocks)
 482           * since those are the strictest limits we have. The fast
 483           * clock and actual rate limits are more relaxed, so checking
 484           * them would make no difference.
 485           */
 486         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 487         .vco = { .min = 4000000, .max = 6000000 },
 488         .n = { .min = 1, .max = 7 },
 489         .m1 = { .min = 2, .max = 3 },
 490         .m2 = { .min = 11, .max = 156 },
 491         .p1 = { .min = 2, .max = 3 },
 492         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 493 };
 494
 495 static const intel_limit_t intel_limits_chv = {
 496         /*
 497          * These are the data rate limits (measured in fast clocks)
 498          * since those are the strictest limits we have.  The fast
 499          * clock and actual rate limits are more relaxed, so checking
 500          * them would make no difference.
 501          */
 502         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 503         .vco = { .min = 4800000, .max = 6480000 },
 504         .n = { .min = 1, .max = 1 },
 505         .m1 = { .min = 2, .max = 2 },
 506         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 507         .p1 = { .min = 2, .max = 4 },
 508         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 509 };
 510
 511 static const intel_limit_t intel_limits_bxt = {
 512         /* FIXME: find real dot limits */
 513         .dot = { .min = 0, .max = INT_MAX },
 514         .vco = { .min = 4800000, .max = 6700000 },
 515         .n = { .min = 1, .max = 1 },
 516         .m1 = { .min = 2, .max = 2 },
 517         /* FIXME: find real m2 limits */
 518         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 519         .p1 = { .min = 2, .max = 4 },
 520         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 521 };
 522
 523 static bool
 524 needs_modeset(struct drm_crtc_state *state)
 525 {
 526         return drm_atomic_crtc_needs_modeset(state);
 527 }
 528
 529 /**
 530  * Returns whether any output on the specified pipe is of the specified type
 531  */
 532 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 533 {
 534         struct drm_device *dev = crtc->base.dev;
 535         struct intel_encoder *encoder;
 536
 537         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 538                 if (encoder->type == type)
 539                         return true;
 540
 541         return false;
 542 }
 543
 544 /**
 545  * Returns whether any output on the specified pipe will have the specified
 546  * type after a staged modeset is complete, i.e., the same as
 547  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 548  * encoder->crtc.
 549  */
 550 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 551                                       int type)
 552 {
 553         struct drm_atomic_state *state = crtc_state->base.state;
 554         struct drm_connector *connector;
 555         struct drm_connector_state *connector_state;
 556         struct intel_encoder *encoder;
 557         int i, num_connectors = 0;
 558
 559         for_each_connector_in_state(state, connector, connector_state, i) {
 560                 if (connector_state->crtc != crtc_state->base.crtc)
 561                         continue;
 562
 563                 num_connectors++;
 564
 565                 encoder = to_intel_encoder(connector_state->best_encoder);
 566                 if (encoder->type == type)
 567                         return true;
 568         }
 569
 570         WARN_ON(num_connectors == 0);
 571
 572         return false;
 573 }
 574
 575 /*
 576  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 577  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 578  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 579  * The helpers' return value is the rate of the clock that is fed to the
 580  * display engine's pipe which can be the above fast dot clock rate or a
 581  * divided-down version of it.
 582  */
 583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 584 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 591         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 592
 593         return clock->dot;
 594 }
 595
 596 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 597 {
 598         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 599 }
 600
 601 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 602 {
 603         clock->m = i9xx_dpll_compute_m(clock);
 604         clock->p = clock->p1 * clock->p2;
 605         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 606                 return 0;
 607         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 608         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 609
 610         return clock->dot;
 611 }
 612
 613 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 614 {
 615         clock->m = clock->m1 * clock->m2;
 616         clock->p = clock->p1 * clock->p2;
 617         if (WARN_ON(clock->n == 0 || clock->p == 0))
 618                 return 0;
 619         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 620         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 621
 622         return clock->dot / 5;
 623 }
 624
 625 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 626 {
 627         clock->m = clock->m1 * clock->m2;
 628         clock->p = clock->p1 * clock->p2;
 629         if (WARN_ON(clock->n == 0 || clock->p == 0))
 630                 return 0;
 631         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 632                         clock->n << 22);
 633         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 634
 635         return clock->dot / 5;
 636 }
 637
 638 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 639 /**
 640  * Returns whether the given set of divisors are valid for a given refclk with
 641  * the given connectors.
 642  */
 643
 644 static bool intel_PLL_is_valid(struct drm_device *dev,
 645                                const intel_limit_t *limit,
 646                                const intel_clock_t *clock)
 647 {
 648         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 649                 INTELPllInvalid("n out of range\n");
 650         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 651                 INTELPllInvalid("p1 out of range\n");
 652         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 653                 INTELPllInvalid("m2 out of range\n");
 654         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 655                 INTELPllInvalid("m1 out of range\n");
 656
 657         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 658             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 659                 if (clock->m1 <= clock->m2)
 660                         INTELPllInvalid("m1 <= m2\n");
 661
 662         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 663                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 664                         INTELPllInvalid("p out of range\n");
 665                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 666                         INTELPllInvalid("m out of range\n");
 667         }
 668
 669         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 670                 INTELPllInvalid("vco out of range\n");
 671         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 672          * connector, etc., rather than just a single range.
 673          */
 674         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 675                 INTELPllInvalid("dot out of range\n");
 676
 677         return true;
 678 }
 679
 680 static int
 681 i9xx_select_p2_div(const intel_limit_t *limit,
 682                    const struct intel_crtc_state *crtc_state,
 683                    int target)
 684 {
 685         struct drm_device *dev = crtc_state->base.crtc->dev;
 686
 687         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 688                 /*
 689                  * For LVDS just rely on its current settings for dual-channel.
 690                  * We haven't figured out how to reliably set up different
 691                  * single/dual channel state, if we even can.
 692                  */
 693                 if (intel_is_dual_link_lvds(dev))
 694                         return limit->p2.p2_fast;
 695                 else
 696                         return limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         return limit->p2.p2_slow;
 700                 else
 701                         return limit->p2.p2_fast;
 702         }
 703 }
 704
 705 /*
 706  * Returns a set of divisors for the desired target clock with the given
 707  * refclk, or FALSE.  The returned values represent the clock equation:
 708  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 709  *
 710  * Target and reference clocks are specified in kHz.
 711  *
 712  * If match_clock is provided, then best_clock P divider must match the P
 713  * divider from @match_clock used for LVDS downclocking.
 714  */
 715 static bool
 716 i9xx_find_best_dpll(const intel_limit_t *limit,
 717                     struct intel_crtc_state *crtc_state,
 718                     int target, int refclk, intel_clock_t *match_clock,
 719                     intel_clock_t *best_clock)
 720 {
 721         struct drm_device *dev = crtc_state->base.crtc->dev;
 722         intel_clock_t clock;
 723         int err = target;
 724
 725         memset(best_clock, 0, sizeof(*best_clock));
 726
 727         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 728
 729         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 730              clock.m1++) {
 731                 for (clock.m2 = limit->m2.min;
 732                      clock.m2 <= limit->m2.max; clock.m2++) {
 733                         if (clock.m2 >= clock.m1)
 734                                 break;
 735                         for (clock.n = limit->n.min;
 736                              clock.n <= limit->n.max; clock.n++) {
 737                                 for (clock.p1 = limit->p1.min;
 738                                         clock.p1 <= limit->p1.max; clock.p1++) {
 739                                         int this_err;
 740
 741                                         i9xx_calc_dpll_params(refclk, &clock);
 742                                         if (!intel_PLL_is_valid(dev, limit,
 743                                                                 &clock))
 744                                                 continue;
 745                                         if (match_clock &&
 746                                             clock.p != match_clock->p)
 747                                                 continue;
 748
 749                                         this_err = abs(clock.dot - target);
 750                                         if (this_err < err) {
 751                                                 *best_clock = clock;
 752                                                 err = this_err;
 753                                         }
 754                                 }
 755                         }
 756                 }
 757         }
 758
 759         return (err != target);
 760 }
 761
 762 /*
 763  * Returns a set of divisors for the desired target clock with the given
 764  * refclk, or FALSE.  The returned values represent the clock equation:
 765  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 766  *
 767  * Target and reference clocks are specified in kHz.
 768  *
 769  * If match_clock is provided, then best_clock P divider must match the P
 770  * divider from @match_clock used for LVDS downclocking.
 771  */
 772 static bool
 773 pnv_find_best_dpll(const intel_limit_t *limit,
 774                    struct intel_crtc_state *crtc_state,
 775                    int target, int refclk, intel_clock_t *match_clock,
 776                    intel_clock_t *best_clock)
 777 {
 778         struct drm_device *dev = crtc_state->base.crtc->dev;
 779         intel_clock_t clock;
 780         int err = target;
 781
 782         memset(best_clock, 0, sizeof(*best_clock));
 783
 784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 785
 786         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 787              clock.m1++) {
 788                 for (clock.m2 = limit->m2.min;
 789                      clock.m2 <= limit->m2.max; clock.m2++) {
 790                         for (clock.n = limit->n.min;
 791                              clock.n <= limit->n.max; clock.n++) {
 792                                 for (clock.p1 = limit->p1.min;
 793                                         clock.p1 <= limit->p1.max; clock.p1++) {
 794                                         int this_err;
 795
 796                                         pnv_calc_dpll_params(refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err) {
 806                                                 *best_clock = clock;
 807                                                 err = this_err;
 808                                         }
 809                                 }
 810                         }
 811                 }
 812         }
 813
 814         return (err != target);
 815 }
 816
 817 /*
 818  * Returns a set of divisors for the desired target clock with the given
 819  * refclk, or FALSE.  The returned values represent the clock equation:
 820  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 821  *
 822  * Target and reference clocks are specified in kHz.
 823  *
 824  * If match_clock is provided, then best_clock P divider must match the P
 825  * divider from @match_clock used for LVDS downclocking.
 826  */
 827 static bool
 828 g4x_find_best_dpll(const intel_limit_t *limit,
 829                    struct intel_crtc_state *crtc_state,
 830                    int target, int refclk, intel_clock_t *match_clock,
 831                    intel_clock_t *best_clock)
 832 {
 833         struct drm_device *dev = crtc_state->base.crtc->dev;
 834         intel_clock_t clock;
 835         int max_n;
 836         bool found = false;
 837         /* approximately equals target * 0.00585 */
 838         int err_most = (target >> 8) + (target >> 9);
 839
 840         memset(best_clock, 0, sizeof(*best_clock));
 841
 842         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 843
 844         max_n = limit->n.max;
 845         /* based on hardware requirement, prefer smaller n to precision */
 846         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 847                 /* based on hardware requirement, prefere larger m1,m2 */
 848                 for (clock.m1 = limit->m1.max;
 849                      clock.m1 >= limit->m1.min; clock.m1--) {
 850                         for (clock.m2 = limit->m2.max;
 851                              clock.m2 >= limit->m2.min; clock.m2--) {
 852                                 for (clock.p1 = limit->p1.max;
 853                                      clock.p1 >= limit->p1.min; clock.p1--) {
 854                                         int this_err;
 855
 856                                         i9xx_calc_dpll_params(refclk, &clock);
 857                                         if (!intel_PLL_is_valid(dev, limit,
 858                                                                 &clock))
 859                                                 continue;
 860
 861                                         this_err = abs(clock.dot - target);
 862                                         if (this_err < err_most) {
 863                                                 *best_clock = clock;
 864                                                 err_most = this_err;
 865                                                 max_n = clock.n;
 866                                                 found = true;
 867                                         }
 868                                 }
 869                         }
 870                 }
 871         }
 872         return found;
 873 }
 874
 875 /*
 876  * Check if the calculated PLL configuration is more optimal compared to the
 877  * best configuration and error found so far. Return the calculated error.
 878  */
 879 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 880                                const intel_clock_t *calculated_clock,
 881                                const intel_clock_t *best_clock,
 882                                unsigned int best_error_ppm,
 883                                unsigned int *error_ppm)
 884 {
 885         /*
 886          * For CHV ignore the error and consider only the P value.
 887          * Prefer a bigger P value based on HW requirements.
 888          */
 889         if (IS_CHERRYVIEW(dev)) {
 890                 *error_ppm = 0;
 891
 892                 return calculated_clock->p > best_clock->p;
 893         }
 894
 895         if (WARN_ON_ONCE(!target_freq))
 896                 return false;
 897
 898         *error_ppm = div_u64(1000000ULL *
 899                                 abs(target_freq - calculated_clock->dot),
 900                              target_freq);
 901         /*
 902          * Prefer a better P value over a better (smaller) error if the error
 903          * is small. Ensure this preference for future configurations too by
 904          * setting the error to 0.
 905          */
 906         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 907                 *error_ppm = 0;
 908
 909                 return true;
 910         }
 911
 912         return *error_ppm + 10 < best_error_ppm;
 913 }
 914
 915 /*
 916  * Returns a set of divisors for the desired target clock with the given
 917  * refclk, or FALSE.  The returned values represent the clock equation:
 918  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 919  */
 920 static bool
 921 vlv_find_best_dpll(const intel_limit_t *limit,
 922                    struct intel_crtc_state *crtc_state,
 923                    int target, int refclk, intel_clock_t *match_clock,
 924                    intel_clock_t *best_clock)
 925 {
 926         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 927         struct drm_device *dev = crtc->base.dev;
 928         intel_clock_t clock;
 929         unsigned int bestppm = 1000000;
 930         /* min update 19.2 MHz */
 931         int max_n = min(limit->n.max, refclk / 19200);
 932         bool found = false;
 933
 934         target *= 5; /* fast clock */
 935
 936         memset(best_clock, 0, sizeof(*best_clock));
 937
 938         /* based on hardware requirement, prefer smaller n to precision */
 939         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 940                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 941                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 942                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 943                                 clock.p = clock.p1 * clock.p2;
 944                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 945                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 946                                         unsigned int ppm;
 947
 948                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 949                                                                      refclk * clock.m1);
 950
 951                                         vlv_calc_dpll_params(refclk, &clock);
 952
 953                                         if (!intel_PLL_is_valid(dev, limit,
 954                                                                 &clock))
 955                                                 continue;
 956
 957                                         if (!vlv_PLL_is_optimal(dev, target,
 958                                                                 &clock,
 959                                                                 best_clock,
 960                                                                 bestppm, &ppm))
 961                                                 continue;
 962
 963                                         *best_clock = clock;
 964                                         bestppm = ppm;
 965                                         found = true;
 966                                 }
 967                         }
 968                 }
 969         }
 970
 971         return found;
 972 }
 973
 974 /*
 975  * Returns a set of divisors for the desired target clock with the given
 976  * refclk, or FALSE.  The returned values represent the clock equation:
 977  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 978  */
 979 static bool
 980 chv_find_best_dpll(const intel_limit_t *limit,
 981                    struct intel_crtc_state *crtc_state,
 982                    int target, int refclk, intel_clock_t *match_clock,
 983                    intel_clock_t *best_clock)
 984 {
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 986         struct drm_device *dev = crtc->base.dev;
 987         unsigned int best_error_ppm;
 988         intel_clock_t clock;
 989         uint64_t m2;
 990         int found = false;
 991
 992         memset(best_clock, 0, sizeof(*best_clock));
 993         best_error_ppm = 1000000;
 994
 995         /*
 996          * Based on hardware doc, the n always set to 1, and m1 always
 997          * set to 2.  If requires to support 200Mhz refclk, we need to
 998          * revisit this because n may not 1 anymore.
 999          */
1000         clock.n = 1, clock.m1 = 2;
1001         target *= 5;    /* fast clock */
1002
1003         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004                 for (clock.p2 = limit->p2.p2_fast;
1005                                 clock.p2 >= limit->p2.p2_slow;
1006                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007                         unsigned int error_ppm;
1008
1009                         clock.p = clock.p1 * clock.p2;
1010
1011                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1012                                         clock.n) << 22, refclk * clock.m1);
1013
1014                         if (m2 > INT_MAX/clock.m1)
1015                                 continue;
1016
1017                         clock.m2 = m2;
1018
1019                         chv_calc_dpll_params(refclk, &clock);
1020
1021                         if (!intel_PLL_is_valid(dev, limit, &clock))
1022                                 continue;
1023
1024                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025                                                 best_error_ppm, &error_ppm))
1026                                 continue;
1027
1028                         *best_clock = clock;
1029                         best_error_ppm = error_ppm;
1030                         found = true;
1031                 }
1032         }
1033
1034         return found;
1035 }
1036
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1038                         intel_clock_t *best_clock)
1039 {
1040         int refclk = 100000;
1041         const intel_limit_t *limit = &intel_limits_bxt;
1042
1043         return chv_find_best_dpll(limit, crtc_state,
1044                                   target_clock, refclk, NULL, best_clock);
1045 }
1046
1047 bool intel_crtc_active(struct drm_crtc *crtc)
1048 {
1049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1050
1051         /* Be paranoid as we can arrive here with only partial
1052          * state retrieved from the hardware during setup.
1053          *
1054          * We can ditch the adjusted_mode.crtc_clock check as soon
1055          * as Haswell has gained clock readout/fastboot support.
1056          *
1057          * We can ditch the crtc->primary->fb check as soon as we can
1058          * properly reconstruct framebuffers.
1059          *
1060          * FIXME: The intel_crtc->active here should be switched to
1061          * crtc->state->active once we have proper CRTC states wired up
1062          * for atomic.
1063          */
1064         return intel_crtc->active && crtc->primary->state->fb &&
1065                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1066 }
1067
1068 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1069                                              enum pipe pipe)
1070 {
1071         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073
1074         return intel_crtc->config->cpu_transcoder;
1075 }
1076
1077 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1078 {
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         i915_reg_t reg = PIPEDSL(pipe);
1081         u32 line1, line2;
1082         u32 line_mask;
1083
1084         if (IS_GEN2(dev))
1085                 line_mask = DSL_LINEMASK_GEN2;
1086         else
1087                 line_mask = DSL_LINEMASK_GEN3;
1088
1089         line1 = I915_READ(reg) & line_mask;
1090         msleep(5);
1091         line2 = I915_READ(reg) & line_mask;
1092
1093         return line1 == line2;
1094 }
1095
1096 /*
1097  * intel_wait_for_pipe_off - wait for pipe to turn off
1098  * @crtc: crtc whose pipe to wait for
1099  *
1100  * After disabling a pipe, we can't wait for vblank in the usual way,
1101  * spinning on the vblank interrupt status bit, since we won't actually
1102  * see an interrupt when the pipe is disabled.
1103  *
1104  * On Gen4 and above:
1105  *   wait for the pipe register state bit to turn off
1106  *
1107  * Otherwise:
1108  *   wait for the display line value to settle (it usually
1109  *   ends up stopping at the start of the next frame).
1110  *
1111  */
1112 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1113 {
1114         struct drm_device *dev = crtc->base.dev;
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1117         enum pipe pipe = crtc->pipe;
1118
1119         if (INTEL_INFO(dev)->gen >= 4) {
1120                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1121
1122                 /* Wait for the Pipe State to go off */
1123                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1124                              100))
1125                         WARN(1, "pipe_off wait timed out\n");
1126         } else {
1127                 /* Wait for the display line to settle */
1128                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1129                         WARN(1, "pipe_off wait timed out\n");
1130         }
1131 }
1132
1133 /* Only for pre-ILK configs */
1134 void assert_pll(struct drm_i915_private *dev_priv,
1135                 enum pipe pipe, bool state)
1136 {
1137         u32 val;
1138         bool cur_state;
1139
1140         val = I915_READ(DPLL(pipe));
1141         cur_state = !!(val & DPLL_VCO_ENABLE);
1142         I915_STATE_WARN(cur_state != state,
1143              "PLL state assertion failure (expected %s, current %s)\n",
1144                         onoff(state), onoff(cur_state));
1145 }
1146
1147 /* XXX: the dsi pll is shared between MIPI DSI ports */
1148 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1149 {
1150         u32 val;
1151         bool cur_state;
1152
1153         mutex_lock(&dev_priv->sb_lock);
1154         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1155         mutex_unlock(&dev_priv->sb_lock);
1156
1157         cur_state = val & DSI_PLL_VCO_EN;
1158         I915_STATE_WARN(cur_state != state,
1159              "DSI PLL state assertion failure (expected %s, current %s)\n",
1160                         onoff(state), onoff(cur_state));
1161 }
1162
1163 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1164                           enum pipe pipe, bool state)
1165 {
1166         bool cur_state;
1167         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1168                                                                       pipe);
1169
1170         if (HAS_DDI(dev_priv)) {
1171                 /* DDI does not have a specific FDI_TX register */
1172                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1173                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1174         } else {
1175                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1176                 cur_state = !!(val & FDI_TX_ENABLE);
1177         }
1178         I915_STATE_WARN(cur_state != state,
1179              "FDI TX state assertion failure (expected %s, current %s)\n",
1180                         onoff(state), onoff(cur_state));
1181 }
1182 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1183 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1184
1185 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         u32 val;
1189         bool cur_state;
1190
1191         val = I915_READ(FDI_RX_CTL(pipe));
1192         cur_state = !!(val & FDI_RX_ENABLE);
1193         I915_STATE_WARN(cur_state != state,
1194              "FDI RX state assertion failure (expected %s, current %s)\n",
1195                         onoff(state), onoff(cur_state));
1196 }
1197 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201                                       enum pipe pipe)
1202 {
1203         u32 val;
1204
1205         /* ILK FDI PLL is always enabled */
1206         if (INTEL_INFO(dev_priv)->gen == 5)
1207                 return;
1208
1209         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1210         if (HAS_DDI(dev_priv))
1211                 return;
1212
1213         val = I915_READ(FDI_TX_CTL(pipe));
1214         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218                        enum pipe pipe, bool state)
1219 {
1220         u32 val;
1221         bool cur_state;
1222
1223         val = I915_READ(FDI_RX_CTL(pipe));
1224         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1225         I915_STATE_WARN(cur_state != state,
1226              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1227                         onoff(state), onoff(cur_state));
1228 }
1229
1230 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1231                            enum pipe pipe)
1232 {
1233         struct drm_device *dev = dev_priv->dev;
1234         i915_reg_t pp_reg;
1235         u32 val;
1236         enum pipe panel_pipe = PIPE_A;
1237         bool locked = true;
1238
1239         if (WARN_ON(HAS_DDI(dev)))
1240                 return;
1241
1242         if (HAS_PCH_SPLIT(dev)) {
1243                 u32 port_sel;
1244
1245                 pp_reg = PCH_PP_CONTROL;
1246                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1247
1248                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1249                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1250                         panel_pipe = PIPE_B;
1251                 /* XXX: else fix for eDP */
1252         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1253                 /* presumably write lock depends on pipe, not port select */
1254                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1255                 panel_pipe = pipe;
1256         } else {
1257                 pp_reg = PP_CONTROL;
1258                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1259                         panel_pipe = PIPE_B;
1260         }
1261
1262         val = I915_READ(pp_reg);
1263         if (!(val & PANEL_POWER_ON) ||
1264             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1265                 locked = false;
1266
1267         I915_STATE_WARN(panel_pipe == pipe && locked,
1268              "panel assertion failure, pipe %c regs locked\n",
1269              pipe_name(pipe));
1270 }
1271
1272 static void assert_cursor(struct drm_i915_private *dev_priv,
1273                           enum pipe pipe, bool state)
1274 {
1275         struct drm_device *dev = dev_priv->dev;
1276         bool cur_state;
1277
1278         if (IS_845G(dev) || IS_I865G(dev))
1279                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1280         else
1281                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1282
1283         I915_STATE_WARN(cur_state != state,
1284              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1285                         pipe_name(pipe), onoff(state), onoff(cur_state));
1286 }
1287 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1288 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1289
1290 void assert_pipe(struct drm_i915_private *dev_priv,
1291                  enum pipe pipe, bool state)
1292 {
1293         bool cur_state;
1294         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1295                                                                       pipe);
1296         enum intel_display_power_domain power_domain;
1297
1298         /* if we need the pipe quirk it must be always on */
1299         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1300             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1301                 state = true;
1302
1303         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1304         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1305                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1306                 cur_state = !!(val & PIPECONF_ENABLE);
1307
1308                 intel_display_power_put(dev_priv, power_domain);
1309         } else {
1310                 cur_state = false;
1311         }
1312
1313         I915_STATE_WARN(cur_state != state,
1314              "pipe %c assertion failure (expected %s, current %s)\n",
1315                         pipe_name(pipe), onoff(state), onoff(cur_state));
1316 }
1317
1318 static void assert_plane(struct drm_i915_private *dev_priv,
1319                          enum plane plane, bool state)
1320 {
1321         u32 val;
1322         bool cur_state;
1323
1324         val = I915_READ(DSPCNTR(plane));
1325         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1326         I915_STATE_WARN(cur_state != state,
1327              "plane %c assertion failure (expected %s, current %s)\n",
1328                         plane_name(plane), onoff(state), onoff(cur_state));
1329 }
1330
1331 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1332 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1333
1334 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1335                                    enum pipe pipe)
1336 {
1337         struct drm_device *dev = dev_priv->dev;
1338         int i;
1339
1340         /* Primary planes are fixed to pipes on gen4+ */
1341         if (INTEL_INFO(dev)->gen >= 4) {
1342                 u32 val = I915_READ(DSPCNTR(pipe));
1343                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1344                      "plane %c assertion failure, should be disabled but not\n",
1345                      plane_name(pipe));
1346                 return;
1347         }
1348
1349         /* Need to check both planes against the pipe */
1350         for_each_pipe(dev_priv, i) {
1351                 u32 val = I915_READ(DSPCNTR(i));
1352                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1353                         DISPPLANE_SEL_PIPE_SHIFT;
1354                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1355                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1356                      plane_name(i), pipe_name(pipe));
1357         }
1358 }
1359
1360 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1361                                     enum pipe pipe)
1362 {
1363         struct drm_device *dev = dev_priv->dev;
1364         int sprite;
1365
1366         if (INTEL_INFO(dev)->gen >= 9) {
1367                 for_each_sprite(dev_priv, pipe, sprite) {
1368                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1369                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1370                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1371                              sprite, pipe_name(pipe));
1372                 }
1373         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1374                 for_each_sprite(dev_priv, pipe, sprite) {
1375                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1376                         I915_STATE_WARN(val & SP_ENABLE,
1377                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1378                              sprite_name(pipe, sprite), pipe_name(pipe));
1379                 }
1380         } else if (INTEL_INFO(dev)->gen >= 7) {
1381                 u32 val = I915_READ(SPRCTL(pipe));
1382                 I915_STATE_WARN(val & SPRITE_ENABLE,
1383                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1384                      plane_name(pipe), pipe_name(pipe));
1385         } else if (INTEL_INFO(dev)->gen >= 5) {
1386                 u32 val = I915_READ(DVSCNTR(pipe));
1387                 I915_STATE_WARN(val & DVS_ENABLE,
1388                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389                      plane_name(pipe), pipe_name(pipe));
1390         }
1391 }
1392
1393 static void assert_vblank_disabled(struct drm_crtc *crtc)
1394 {
1395         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1396                 drm_crtc_vblank_put(crtc);
1397 }
1398
1399 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1400                                     enum pipe pipe)
1401 {
1402         u32 val;
1403         bool enabled;
1404
1405         val = I915_READ(PCH_TRANSCONF(pipe));
1406         enabled = !!(val & TRANS_ENABLE);
1407         I915_STATE_WARN(enabled,
1408              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1409              pipe_name(pipe));
1410 }
1411
1412 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1413                             enum pipe pipe, u32 port_sel, u32 val)
1414 {
1415         if ((val & DP_PORT_EN) == 0)
1416                 return false;
1417
1418         if (HAS_PCH_CPT(dev_priv)) {
1419                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1420                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421                         return false;
1422         } else if (IS_CHERRYVIEW(dev_priv)) {
1423                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424                         return false;
1425         } else {
1426                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427                         return false;
1428         }
1429         return true;
1430 }
1431
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433                               enum pipe pipe, u32 val)
1434 {
1435         if ((val & SDVO_ENABLE) == 0)
1436                 return false;
1437
1438         if (HAS_PCH_CPT(dev_priv)) {
1439                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440                         return false;
1441         } else if (IS_CHERRYVIEW(dev_priv)) {
1442                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443                         return false;
1444         } else {
1445                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446                         return false;
1447         }
1448         return true;
1449 }
1450
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452                               enum pipe pipe, u32 val)
1453 {
1454         if ((val & LVDS_PORT_EN) == 0)
1455                 return false;
1456
1457         if (HAS_PCH_CPT(dev_priv)) {
1458                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459                         return false;
1460         } else {
1461                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462                         return false;
1463         }
1464         return true;
1465 }
1466
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468                               enum pipe pipe, u32 val)
1469 {
1470         if ((val & ADPA_DAC_ENABLE) == 0)
1471                 return false;
1472         if (HAS_PCH_CPT(dev_priv)) {
1473                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474                         return false;
1475         } else {
1476                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477                         return false;
1478         }
1479         return true;
1480 }
1481
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483                                    enum pipe pipe, i915_reg_t reg,
1484                                    u32 port_sel)
1485 {
1486         u32 val = I915_READ(reg);
1487         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1488              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1489              i915_mmio_reg_offset(reg), pipe_name(pipe));
1490
1491         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1492              && (val & DP_PIPEB_SELECT),
1493              "IBX PCH dp port still using transcoder B\n");
1494 }
1495
1496 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1497                                      enum pipe pipe, i915_reg_t reg)
1498 {
1499         u32 val = I915_READ(reg);
1500         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1501              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1502              i915_mmio_reg_offset(reg), pipe_name(pipe));
1503
1504         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1505              && (val & SDVO_PIPE_B_SELECT),
1506              "IBX PCH hdmi port still using transcoder B\n");
1507 }
1508
1509 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1510                                       enum pipe pipe)
1511 {
1512         u32 val;
1513
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517
1518         val = I915_READ(PCH_ADPA);
1519         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520              "PCH VGA enabled on transcoder %c, should be disabled\n",
1521              pipe_name(pipe));
1522
1523         val = I915_READ(PCH_LVDS);
1524         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1525              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1526              pipe_name(pipe));
1527
1528         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1529         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1530         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc,
1534                            const struct intel_crtc_state *pipe_config)
1535 {
1536         struct drm_device *dev = crtc->base.dev;
1537         struct drm_i915_private *dev_priv = dev->dev_private;
1538         enum pipe pipe = crtc->pipe;
1539         i915_reg_t reg = DPLL(pipe);
1540         u32 dpll = pipe_config->dpll_hw_state.dpll;
1541
1542         assert_pipe_disabled(dev_priv, pipe);
1543
1544         /* PLL is protected by panel, make sure we can write it */
1545         assert_panel_unlocked(dev_priv, pipe);
1546
1547         I915_WRITE(reg, dpll);
1548         POSTING_READ(reg);
1549         udelay(150);
1550
1551         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1553
1554         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1555         POSTING_READ(DPLL_MD(pipe));
1556 }
1557
1558 static void chv_enable_pll(struct intel_crtc *crtc,
1559                            const struct intel_crtc_state *pipe_config)
1560 {
1561         struct drm_device *dev = crtc->base.dev;
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         enum pipe pipe = crtc->pipe;
1564         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1565         u32 tmp;
1566
1567         assert_pipe_disabled(dev_priv, pipe);
1568
1569         /* PLL is protected by panel, make sure we can write it */
1570         assert_panel_unlocked(dev_priv, pipe);
1571
1572         mutex_lock(&dev_priv->sb_lock);
1573
1574         /* Enable back the 10bit clock to display controller */
1575         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1576         tmp |= DPIO_DCLKP_EN;
1577         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1578
1579         mutex_unlock(&dev_priv->sb_lock);
1580
1581         /*
1582          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1583          */
1584         udelay(1);
1585
1586         /* Enable PLL */
1587         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1588
1589         /* Check PLL is locked */
1590         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1591                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1592
1593         if (pipe != PIPE_A) {
1594                 /*
1595                  * WaPixelRepeatModeFixForC0:chv
1596                  *
1597                  * DPLLCMD is AWOL. Use chicken bits to propagate
1598                  * the value from DPLLBMD to either pipe B or C.
1599                  */
1600                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1601                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1602                 I915_WRITE(CBR4_VLV, 0);
1603                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1604
1605                 /*
1606                  * DPLLB VGA mode also seems to cause problems.
1607                  * We should always have it disabled.
1608                  */
1609                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1610         } else {
1611                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1612                 POSTING_READ(DPLL_MD(pipe));
1613         }
1614 }
1615
1616 static int intel_num_dvo_pipes(struct drm_device *dev)
1617 {
1618         struct intel_crtc *crtc;
1619         int count = 0;
1620
1621         for_each_intel_crtc(dev, crtc)
1622                 count += crtc->base.state->active &&
1623                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1624
1625         return count;
1626 }
1627
1628 static void i9xx_enable_pll(struct intel_crtc *crtc)
1629 {
1630         struct drm_device *dev = crtc->base.dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         i915_reg_t reg = DPLL(crtc->pipe);
1633         u32 dpll = crtc->config->dpll_hw_state.dpll;
1634
1635         assert_pipe_disabled(dev_priv, crtc->pipe);
1636
1637         /* PLL is protected by panel, make sure we can write it */
1638         if (IS_MOBILE(dev) && !IS_I830(dev))
1639                 assert_panel_unlocked(dev_priv, crtc->pipe);
1640
1641         /* Enable DVO 2x clock on both PLLs if necessary */
1642         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1643                 /*
1644                  * It appears to be important that we don't enable this
1645                  * for the current pipe before otherwise configuring the
1646                  * PLL. No idea how this should be handled if multiple
1647                  * DVO outputs are enabled simultaneosly.
1648                  */
1649                 dpll |= DPLL_DVO_2X_MODE;
1650                 I915_WRITE(DPLL(!crtc->pipe),
1651                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1652         }
1653
1654         /*
1655          * Apparently we need to have VGA mode enabled prior to changing
1656          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1657          * dividers, even though the register value does change.
1658          */
1659         I915_WRITE(reg, 0);
1660
1661         I915_WRITE(reg, dpll);
1662
1663         /* Wait for the clocks to stabilize. */
1664         POSTING_READ(reg);
1665         udelay(150);
1666
1667         if (INTEL_INFO(dev)->gen >= 4) {
1668                 I915_WRITE(DPLL_MD(crtc->pipe),
1669                            crtc->config->dpll_hw_state.dpll_md);
1670         } else {
1671                 /* The pixel multiplier can only be updated once the
1672                  * DPLL is enabled and the clocks are stable.
1673                  *
1674                  * So write it again.
1675                  */
1676                 I915_WRITE(reg, dpll);
1677         }
1678
1679         /* We do this three times for luck */
1680         I915_WRITE(reg, dpll);
1681         POSTING_READ(reg);
1682         udelay(150); /* wait for warmup */
1683         I915_WRITE(reg, dpll);
1684         POSTING_READ(reg);
1685         udelay(150); /* wait for warmup */
1686         I915_WRITE(reg, dpll);
1687         POSTING_READ(reg);
1688         udelay(150); /* wait for warmup */
1689 }
1690
1691 /**
1692  * i9xx_disable_pll - disable a PLL
1693  * @dev_priv: i915 private structure
1694  * @pipe: pipe PLL to disable
1695  *
1696  * Disable the PLL for @pipe, making sure the pipe is off first.
1697  *
1698  * Note!  This is for pre-ILK only.
1699  */
1700 static void i9xx_disable_pll(struct intel_crtc *crtc)
1701 {
1702         struct drm_device *dev = crtc->base.dev;
1703         struct drm_i915_private *dev_priv = dev->dev_private;
1704         enum pipe pipe = crtc->pipe;
1705
1706         /* Disable DVO 2x clock on both PLLs if necessary */
1707         if (IS_I830(dev) &&
1708             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1709             !intel_num_dvo_pipes(dev)) {
1710                 I915_WRITE(DPLL(PIPE_B),
1711                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1712                 I915_WRITE(DPLL(PIPE_A),
1713                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1714         }
1715
1716         /* Don't disable pipe or pipe PLLs if needed */
1717         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1718             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1719                 return;
1720
1721         /* Make sure the pipe isn't still relying on us */
1722         assert_pipe_disabled(dev_priv, pipe);
1723
1724         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         u32 val;
1731
1732         /* Make sure the pipe isn't still relying on us */
1733         assert_pipe_disabled(dev_priv, pipe);
1734
1735         val = DPLL_INTEGRATED_REF_CLK_VLV |
1736                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737         if (pipe != PIPE_A)
1738                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739
1740         I915_WRITE(DPLL(pipe), val);
1741         POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1747         u32 val;
1748
1749         /* Make sure the pipe isn't still relying on us */
1750         assert_pipe_disabled(dev_priv, pipe);
1751
1752         val = DPLL_SSC_REF_CLK_CHV |
1753                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1754         if (pipe != PIPE_A)
1755                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1756
1757         I915_WRITE(DPLL(pipe), val);
1758         POSTING_READ(DPLL(pipe));
1759
1760         mutex_lock(&dev_priv->sb_lock);
1761
1762         /* Disable 10bit clock to display controller */
1763         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1764         val &= ~DPIO_DCLKP_EN;
1765         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1766
1767         mutex_unlock(&dev_priv->sb_lock);
1768 }
1769
1770 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1771                          struct intel_digital_port *dport,
1772                          unsigned int expected_mask)
1773 {
1774         u32 port_mask;
1775         i915_reg_t dpll_reg;
1776
1777         switch (dport->port) {
1778         case PORT_B:
1779                 port_mask = DPLL_PORTB_READY_MASK;
1780                 dpll_reg = DPLL(0);
1781                 break;
1782         case PORT_C:
1783                 port_mask = DPLL_PORTC_READY_MASK;
1784                 dpll_reg = DPLL(0);
1785                 expected_mask <<= 4;
1786                 break;
1787         case PORT_D:
1788                 port_mask = DPLL_PORTD_READY_MASK;
1789                 dpll_reg = DPIO_PHY_STATUS;
1790                 break;
1791         default:
1792                 BUG();
1793         }
1794
1795         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1796                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1797                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1798 }
1799
1800 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1801                                            enum pipe pipe)
1802 {
1803         struct drm_device *dev = dev_priv->dev;
1804         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806         i915_reg_t reg;
1807         uint32_t val, pipeconf_val;
1808
1809         /* Make sure PCH DPLL is enabled */
1810         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1811
1812         /* FDI must be feeding us bits for PCH ports */
1813         assert_fdi_tx_enabled(dev_priv, pipe);
1814         assert_fdi_rx_enabled(dev_priv, pipe);
1815
1816         if (HAS_PCH_CPT(dev)) {
1817                 /* Workaround: Set the timing override bit before enabling the
1818                  * pch transcoder. */
1819                 reg = TRANS_CHICKEN2(pipe);
1820                 val = I915_READ(reg);
1821                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1822                 I915_WRITE(reg, val);
1823         }
1824
1825         reg = PCH_TRANSCONF(pipe);
1826         val = I915_READ(reg);
1827         pipeconf_val = I915_READ(PIPECONF(pipe));
1828
1829         if (HAS_PCH_IBX(dev_priv)) {
1830                 /*
1831                  * Make the BPC in transcoder be consistent with
1832                  * that in pipeconf reg. For HDMI we must use 8bpc
1833                  * here for both 8bpc and 12bpc.
1834                  */
1835                 val &= ~PIPECONF_BPC_MASK;
1836                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1837                         val |= PIPECONF_8BPC;
1838                 else
1839                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1840         }
1841
1842         val &= ~TRANS_INTERLACE_MASK;
1843         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1844                 if (HAS_PCH_IBX(dev_priv) &&
1845                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1846                         val |= TRANS_LEGACY_INTERLACED_ILK;
1847                 else
1848                         val |= TRANS_INTERLACED;
1849         else
1850                 val |= TRANS_PROGRESSIVE;
1851
1852         I915_WRITE(reg, val | TRANS_ENABLE);
1853         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1854                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1855 }
1856
1857 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1858                                       enum transcoder cpu_transcoder)
1859 {
1860         u32 val, pipeconf_val;
1861
1862         /* FDI must be feeding us bits for PCH ports */
1863         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1864         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1865
1866         /* Workaround: set timing override bit. */
1867         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1868         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1869         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1870
1871         val = TRANS_ENABLE;
1872         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1873
1874         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1875             PIPECONF_INTERLACED_ILK)
1876                 val |= TRANS_INTERLACED;
1877         else
1878                 val |= TRANS_PROGRESSIVE;
1879
1880         I915_WRITE(LPT_TRANSCONF, val);
1881         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1882                 DRM_ERROR("Failed to enable PCH transcoder\n");
1883 }
1884
1885 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1886                                             enum pipe pipe)
1887 {
1888         struct drm_device *dev = dev_priv->dev;
1889         i915_reg_t reg;
1890         uint32_t val;
1891
1892         /* FDI relies on the transcoder */
1893         assert_fdi_tx_disabled(dev_priv, pipe);
1894         assert_fdi_rx_disabled(dev_priv, pipe);
1895
1896         /* Ports must be off as well */
1897         assert_pch_ports_disabled(dev_priv, pipe);
1898
1899         reg = PCH_TRANSCONF(pipe);
1900         val = I915_READ(reg);
1901         val &= ~TRANS_ENABLE;
1902         I915_WRITE(reg, val);
1903         /* wait for PCH transcoder off, transcoder state */
1904         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1905                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1906
1907         if (HAS_PCH_CPT(dev)) {
1908                 /* Workaround: Clear the timing override chicken bit again. */
1909                 reg = TRANS_CHICKEN2(pipe);
1910                 val = I915_READ(reg);
1911                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1912                 I915_WRITE(reg, val);
1913         }
1914 }
1915
1916 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1917 {
1918         u32 val;
1919
1920         val = I915_READ(LPT_TRANSCONF);
1921         val &= ~TRANS_ENABLE;
1922         I915_WRITE(LPT_TRANSCONF, val);
1923         /* wait for PCH transcoder off, transcoder state */
1924         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1925                 DRM_ERROR("Failed to disable PCH transcoder\n");
1926
1927         /* Workaround: clear timing override bit. */
1928         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1929         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1930         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1931 }
1932
1933 /**
1934  * intel_enable_pipe - enable a pipe, asserting requirements
1935  * @crtc: crtc responsible for the pipe
1936  *
1937  * Enable @crtc's pipe, making sure that various hardware specific requirements
1938  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1939  */
1940 static void intel_enable_pipe(struct intel_crtc *crtc)
1941 {
1942         struct drm_device *dev = crtc->base.dev;
1943         struct drm_i915_private *dev_priv = dev->dev_private;
1944         enum pipe pipe = crtc->pipe;
1945         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1946         enum pipe pch_transcoder;
1947         i915_reg_t reg;
1948         u32 val;
1949
1950         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1951
1952         assert_planes_disabled(dev_priv, pipe);
1953         assert_cursor_disabled(dev_priv, pipe);
1954         assert_sprites_disabled(dev_priv, pipe);
1955
1956         if (HAS_PCH_LPT(dev_priv))
1957                 pch_transcoder = TRANSCODER_A;
1958         else
1959                 pch_transcoder = pipe;
1960
1961         /*
1962          * A pipe without a PLL won't actually be able to drive bits from
1963          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1964          * need the check.
1965          */
1966         if (HAS_GMCH_DISPLAY(dev_priv))
1967                 if (crtc->config->has_dsi_encoder)
1968                         assert_dsi_pll_enabled(dev_priv);
1969                 else
1970                         assert_pll_enabled(dev_priv, pipe);
1971         else {
1972                 if (crtc->config->has_pch_encoder) {
1973                         /* if driving the PCH, we need FDI enabled */
1974                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1975                         assert_fdi_tx_pll_enabled(dev_priv,
1976                                                   (enum pipe) cpu_transcoder);
1977                 }
1978                 /* FIXME: assert CPU port conditions for SNB+ */
1979         }
1980
1981         reg = PIPECONF(cpu_transcoder);
1982         val = I915_READ(reg);
1983         if (val & PIPECONF_ENABLE) {
1984                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1985                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1986                 return;
1987         }
1988
1989         I915_WRITE(reg, val | PIPECONF_ENABLE);
1990         POSTING_READ(reg);
1991
1992         /*
1993          * Until the pipe starts DSL will read as 0, which would cause
1994          * an apparent vblank timestamp jump, which messes up also the
1995          * frame count when it's derived from the timestamps. So let's
1996          * wait for the pipe to start properly before we call
1997          * drm_crtc_vblank_on()
1998          */
1999         if (dev->max_vblank_count == 0 &&
2000             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2001                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2002 }
2003
2004 /**
2005  * intel_disable_pipe - disable a pipe, asserting requirements
2006  * @crtc: crtc whose pipes is to be disabled
2007  *
2008  * Disable the pipe of @crtc, making sure that various hardware
2009  * specific requirements are met, if applicable, e.g. plane
2010  * disabled, panel fitter off, etc.
2011  *
2012  * Will wait until the pipe has shut down before returning.
2013  */
2014 static void intel_disable_pipe(struct intel_crtc *crtc)
2015 {
2016         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2017         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2018         enum pipe pipe = crtc->pipe;
2019         i915_reg_t reg;
2020         u32 val;
2021
2022         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2023
2024         /*
2025          * Make sure planes won't keep trying to pump pixels to us,
2026          * or we might hang the display.
2027          */
2028         assert_planes_disabled(dev_priv, pipe);
2029         assert_cursor_disabled(dev_priv, pipe);
2030         assert_sprites_disabled(dev_priv, pipe);
2031
2032         reg = PIPECONF(cpu_transcoder);
2033         val = I915_READ(reg);
2034         if ((val & PIPECONF_ENABLE) == 0)
2035                 return;
2036
2037         /*
2038          * Double wide has implications for planes
2039          * so best keep it disabled when not needed.
2040          */
2041         if (crtc->config->double_wide)
2042                 val &= ~PIPECONF_DOUBLE_WIDE;
2043
2044         /* Don't disable pipe or pipe PLLs if needed */
2045         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2046             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2047                 val &= ~PIPECONF_ENABLE;
2048
2049         I915_WRITE(reg, val);
2050         if ((val & PIPECONF_ENABLE) == 0)
2051                 intel_wait_for_pipe_off(crtc);
2052 }
2053
2054 static bool need_vtd_wa(struct drm_device *dev)
2055 {
2056 #ifdef CONFIG_INTEL_IOMMU
2057         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2058                 return true;
2059 #endif
2060         return false;
2061 }
2062
2063 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2064 {
2065         return IS_GEN2(dev_priv) ? 2048 : 4096;
2066 }
2067
2068 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2069                                            uint64_t fb_modifier, unsigned int cpp)
2070 {
2071         switch (fb_modifier) {
2072         case DRM_FORMAT_MOD_NONE:
2073                 return cpp;
2074         case I915_FORMAT_MOD_X_TILED:
2075                 if (IS_GEN2(dev_priv))
2076                         return 128;
2077                 else
2078                         return 512;
2079         case I915_FORMAT_MOD_Y_TILED:
2080                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2081                         return 128;
2082                 else
2083                         return 512;
2084         case I915_FORMAT_MOD_Yf_TILED:
2085                 switch (cpp) {
2086                 case 1:
2087                         return 64;
2088                 case 2:
2089                 case 4:
2090                         return 128;
2091                 case 8:
2092                 case 16:
2093                         return 256;
2094                 default:
2095                         MISSING_CASE(cpp);
2096                         return cpp;
2097                 }
2098                 break;
2099         default:
2100                 MISSING_CASE(fb_modifier);
2101                 return cpp;
2102         }
2103 }
2104
2105 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2106                                uint64_t fb_modifier, unsigned int cpp)
2107 {
2108         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2109                 return 1;
2110         else
2111                 return intel_tile_size(dev_priv) /
2112                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2113 }
2114
2115 /* Return the tile dimensions in pixel units */
2116 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2117                             unsigned int *tile_width,
2118                             unsigned int *tile_height,
2119                             uint64_t fb_modifier,
2120                             unsigned int cpp)
2121 {
2122         unsigned int tile_width_bytes =
2123                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2124
2125         *tile_width = tile_width_bytes / cpp;
2126         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2127 }
2128
2129 unsigned int
2130 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2131                       uint32_t pixel_format, uint64_t fb_modifier)
2132 {
2133         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2134         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2135
2136         return ALIGN(height, tile_height);
2137 }
2138
2139 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2140 {
2141         unsigned int size = 0;
2142         int i;
2143
2144         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2145                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2146
2147         return size;
2148 }
2149
2150 static void
2151 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2152                         const struct drm_framebuffer *fb,
2153                         unsigned int rotation)
2154 {
2155         if (intel_rotation_90_or_270(rotation)) {
2156                 *view = i915_ggtt_view_rotated;
2157                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2158         } else {
2159                 *view = i915_ggtt_view_normal;
2160         }
2161 }
2162
2163 static void
2164 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2165                    struct drm_framebuffer *fb)
2166 {
2167         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2168         unsigned int tile_size, tile_width, tile_height, cpp;
2169
2170         tile_size = intel_tile_size(dev_priv);
2171
2172         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2173         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2174                         fb->modifier[0], cpp);
2175
2176         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2177         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2178
2179         if (info->pixel_format == DRM_FORMAT_NV12) {
2180                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2181                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2182                                 fb->modifier[1], cpp);
2183
2184                 info->uv_offset = fb->offsets[1];
2185                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2186                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2187         }
2188 }
2189
2190 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2191 {
2192         if (INTEL_INFO(dev_priv)->gen >= 9)
2193                 return 256 * 1024;
2194         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2195                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2196                 return 128 * 1024;
2197         else if (INTEL_INFO(dev_priv)->gen >= 4)
2198                 return 4 * 1024;
2199         else
2200                 return 0;
2201 }
2202
2203 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2204                                          uint64_t fb_modifier)
2205 {
2206         switch (fb_modifier) {
2207         case DRM_FORMAT_MOD_NONE:
2208                 return intel_linear_alignment(dev_priv);
2209         case I915_FORMAT_MOD_X_TILED:
2210                 if (INTEL_INFO(dev_priv)->gen >= 9)
2211                         return 256 * 1024;
2212                 return 0;
2213         case I915_FORMAT_MOD_Y_TILED:
2214         case I915_FORMAT_MOD_Yf_TILED:
2215                 return 1 * 1024 * 1024;
2216         default:
2217                 MISSING_CASE(fb_modifier);
2218                 return 0;
2219         }
2220 }
2221
2222 int
2223 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2224                            unsigned int rotation)
2225 {
2226         struct drm_device *dev = fb->dev;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2229         struct i915_ggtt_view view;
2230         u32 alignment;
2231         int ret;
2232
2233         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2234
2235         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2236
2237         intel_fill_fb_ggtt_view(&view, fb, rotation);
2238
2239         /* Note that the w/a also requires 64 PTE of padding following the
2240          * bo. We currently fill all unused PTE with the shadow page and so
2241          * we should always have valid PTE following the scanout preventing
2242          * the VT-d warning.
2243          */
2244         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2245                 alignment = 256 * 1024;
2246
2247         /*
2248          * Global gtt pte registers are special registers which actually forward
2249          * writes to a chunk of system memory. Which means that there is no risk
2250          * that the register values disappear as soon as we call
2251          * intel_runtime_pm_put(), so it is correct to wrap only the
2252          * pin/unpin/fence and not more.
2253          */
2254         intel_runtime_pm_get(dev_priv);
2255
2256         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2257                                                    &view);
2258         if (ret)
2259                 goto err_pm;
2260
2261         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262          * fence, whereas 965+ only requires a fence if using
2263          * framebuffer compression.  For simplicity, we always install
2264          * a fence as the cost is not that onerous.
2265          */
2266         if (view.type == I915_GGTT_VIEW_NORMAL) {
2267                 ret = i915_gem_object_get_fence(obj);
2268                 if (ret == -EDEADLK) {
2269                         /*
2270                          * -EDEADLK means there are no free fences
2271                          * no pending flips.
2272                          *
2273                          * This is propagated to atomic, but it uses
2274                          * -EDEADLK to force a locking recovery, so
2275                          * change the returned error to -EBUSY.
2276                          */
2277                         ret = -EBUSY;
2278                         goto err_unpin;
2279                 } else if (ret)
2280                         goto err_unpin;
2281
2282                 i915_gem_object_pin_fence(obj);
2283         }
2284
2285         intel_runtime_pm_put(dev_priv);
2286         return 0;
2287
2288 err_unpin:
2289         i915_gem_object_unpin_from_display_plane(obj, &view);
2290 err_pm:
2291         intel_runtime_pm_put(dev_priv);
2292         return ret;
2293 }
2294
2295 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2296 {
2297         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2298         struct i915_ggtt_view view;
2299
2300         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2301
2302         intel_fill_fb_ggtt_view(&view, fb, rotation);
2303
2304         if (view.type == I915_GGTT_VIEW_NORMAL)
2305                 i915_gem_object_unpin_fence(obj);
2306
2307         i915_gem_object_unpin_from_display_plane(obj, &view);
2308 }
2309
2310 /*
2311  * Adjust the tile offset by moving the difference into
2312  * the x/y offsets.
2313  *
2314  * Input tile dimensions and pitch must already be
2315  * rotated to match x and y, and in pixel units.
2316  */
2317 static u32 intel_adjust_tile_offset(int *x, int *y,
2318                                     unsigned int tile_width,
2319                                     unsigned int tile_height,
2320                                     unsigned int tile_size,
2321                                     unsigned int pitch_tiles,
2322                                     u32 old_offset,
2323                                     u32 new_offset)
2324 {
2325         unsigned int tiles;
2326
2327         WARN_ON(old_offset & (tile_size - 1));
2328         WARN_ON(new_offset & (tile_size - 1));
2329         WARN_ON(new_offset > old_offset);
2330
2331         tiles = (old_offset - new_offset) / tile_size;
2332
2333         *y += tiles / pitch_tiles * tile_height;
2334         *x += tiles % pitch_tiles * tile_width;
2335
2336         return new_offset;
2337 }
2338
2339 /*
2340  * Computes the linear offset to the base tile and adjusts
2341  * x, y. bytes per pixel is assumed to be a power-of-two.
2342  *
2343  * In the 90/270 rotated case, x and y are assumed
2344  * to be already rotated to match the rotated GTT view, and
2345  * pitch is the tile_height aligned framebuffer height.
2346  */
2347 u32 intel_compute_tile_offset(int *x, int *y,
2348                               const struct drm_framebuffer *fb, int plane,
2349                               unsigned int pitch,
2350                               unsigned int rotation)
2351 {
2352         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2353         uint64_t fb_modifier = fb->modifier[plane];
2354         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2355         u32 offset, offset_aligned, alignment;
2356
2357         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2358         if (alignment)
2359                 alignment--;
2360
2361         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2362                 unsigned int tile_size, tile_width, tile_height;
2363                 unsigned int tile_rows, tiles, pitch_tiles;
2364
2365                 tile_size = intel_tile_size(dev_priv);
2366                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2367                                 fb_modifier, cpp);
2368
2369                 if (intel_rotation_90_or_270(rotation)) {
2370                         pitch_tiles = pitch / tile_height;
2371                         swap(tile_width, tile_height);
2372                 } else {
2373                         pitch_tiles = pitch / (tile_width * cpp);
2374                 }
2375
2376                 tile_rows = *y / tile_height;
2377                 *y %= tile_height;
2378
2379                 tiles = *x / tile_width;
2380                 *x %= tile_width;
2381
2382                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2383                 offset_aligned = offset & ~alignment;
2384
2385                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2386                                          tile_size, pitch_tiles,
2387                                          offset, offset_aligned);
2388         } else {
2389                 offset = *y * pitch + *x * cpp;
2390                 offset_aligned = offset & ~alignment;
2391
2392                 *y = (offset & alignment) / pitch;
2393                 *x = ((offset & alignment) - *y * pitch) / cpp;
2394         }
2395
2396         return offset_aligned;
2397 }
2398
2399 static int i9xx_format_to_fourcc(int format)
2400 {
2401         switch (format) {
2402         case DISPPLANE_8BPP:
2403                 return DRM_FORMAT_C8;
2404         case DISPPLANE_BGRX555:
2405                 return DRM_FORMAT_XRGB1555;
2406         case DISPPLANE_BGRX565:
2407                 return DRM_FORMAT_RGB565;
2408         default:
2409         case DISPPLANE_BGRX888:
2410                 return DRM_FORMAT_XRGB8888;
2411         case DISPPLANE_RGBX888:
2412                 return DRM_FORMAT_XBGR8888;
2413         case DISPPLANE_BGRX101010:
2414                 return DRM_FORMAT_XRGB2101010;
2415         case DISPPLANE_RGBX101010:
2416                 return DRM_FORMAT_XBGR2101010;
2417         }
2418 }
2419
2420 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2421 {
2422         switch (format) {
2423         case PLANE_CTL_FORMAT_RGB_565:
2424                 return DRM_FORMAT_RGB565;
2425         default:
2426         case PLANE_CTL_FORMAT_XRGB_8888:
2427                 if (rgb_order) {
2428                         if (alpha)
2429                                 return DRM_FORMAT_ABGR8888;
2430                         else
2431                                 return DRM_FORMAT_XBGR8888;
2432                 } else {
2433                         if (alpha)
2434                                 return DRM_FORMAT_ARGB8888;
2435                         else
2436                                 return DRM_FORMAT_XRGB8888;
2437                 }
2438         case PLANE_CTL_FORMAT_XRGB_2101010:
2439                 if (rgb_order)
2440                         return DRM_FORMAT_XBGR2101010;
2441                 else
2442                         return DRM_FORMAT_XRGB2101010;
2443         }
2444 }
2445
2446 static bool
2447 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2448                               struct intel_initial_plane_config *plane_config)
2449 {
2450         struct drm_device *dev = crtc->base.dev;
2451         struct drm_i915_private *dev_priv = to_i915(dev);
2452         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2453         struct drm_i915_gem_object *obj = NULL;
2454         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2455         struct drm_framebuffer *fb = &plane_config->fb->base;
2456         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2457         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2458                                     PAGE_SIZE);
2459
2460         size_aligned -= base_aligned;
2461
2462         if (plane_config->size == 0)
2463                 return false;
2464
2465         /* If the FB is too big, just don't use it since fbdev is not very
2466          * important and we should probably use that space with FBC or other
2467          * features. */
2468         if (size_aligned * 2 > ggtt->stolen_usable_size)
2469                 return false;
2470
2471         mutex_lock(&dev->struct_mutex);
2472
2473         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2474                                                              base_aligned,
2475                                                              base_aligned,
2476                                                              size_aligned);
2477         if (!obj) {
2478                 mutex_unlock(&dev->struct_mutex);
2479                 return false;
2480         }
2481
2482         obj->tiling_mode = plane_config->tiling;
2483         if (obj->tiling_mode == I915_TILING_X)
2484                 obj->stride = fb->pitches[0];
2485
2486         mode_cmd.pixel_format = fb->pixel_format;
2487         mode_cmd.width = fb->width;
2488         mode_cmd.height = fb->height;
2489         mode_cmd.pitches[0] = fb->pitches[0];
2490         mode_cmd.modifier[0] = fb->modifier[0];
2491         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2492
2493         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2494                                    &mode_cmd, obj)) {
2495                 DRM_DEBUG_KMS("intel fb init failed\n");
2496                 goto out_unref_obj;
2497         }
2498
2499         mutex_unlock(&dev->struct_mutex);
2500
2501         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2502         return true;
2503
2504 out_unref_obj:
2505         drm_gem_object_unreference(&obj->base);
2506         mutex_unlock(&dev->struct_mutex);
2507         return false;
2508 }
2509
2510 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2511 static void
2512 update_state_fb(struct drm_plane *plane)
2513 {
2514         if (plane->fb == plane->state->fb)
2515                 return;
2516
2517         if (plane->state->fb)
2518                 drm_framebuffer_unreference(plane->state->fb);
2519         plane->state->fb = plane->fb;
2520         if (plane->state->fb)
2521                 drm_framebuffer_reference(plane->state->fb);
2522 }
2523
2524 static void
2525 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2526                              struct intel_initial_plane_config *plane_config)
2527 {
2528         struct drm_device *dev = intel_crtc->base.dev;
2529         struct drm_i915_private *dev_priv = dev->dev_private;
2530         struct drm_crtc *c;
2531         struct intel_crtc *i;
2532         struct drm_i915_gem_object *obj;
2533         struct drm_plane *primary = intel_crtc->base.primary;
2534         struct drm_plane_state *plane_state = primary->state;
2535         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2536         struct intel_plane *intel_plane = to_intel_plane(primary);
2537         struct intel_plane_state *intel_state =
2538                 to_intel_plane_state(plane_state);
2539         struct drm_framebuffer *fb;
2540
2541         if (!plane_config->fb)
2542                 return;
2543
2544         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2545                 fb = &plane_config->fb->base;
2546                 goto valid_fb;
2547         }
2548
2549         kfree(plane_config->fb);
2550
2551         /*
2552          * Failed to alloc the obj, check to see if we should share
2553          * an fb with another CRTC instead
2554          */
2555         for_each_crtc(dev, c) {
2556                 i = to_intel_crtc(c);
2557
2558                 if (c == &intel_crtc->base)
2559                         continue;
2560
2561                 if (!i->active)
2562                         continue;
2563
2564                 fb = c->primary->fb;
2565                 if (!fb)
2566                         continue;
2567
2568                 obj = intel_fb_obj(fb);
2569                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2570                         drm_framebuffer_reference(fb);
2571                         goto valid_fb;
2572                 }
2573         }
2574
2575         /*
2576          * We've failed to reconstruct the BIOS FB.  Current display state
2577          * indicates that the primary plane is visible, but has a NULL FB,
2578          * which will lead to problems later if we don't fix it up.  The
2579          * simplest solution is to just disable the primary plane now and
2580          * pretend the BIOS never had it enabled.
2581          */
2582         to_intel_plane_state(plane_state)->visible = false;
2583         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2584         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2585         intel_plane->disable_plane(primary, &intel_crtc->base);
2586
2587         return;
2588
2589 valid_fb:
2590         plane_state->src_x = 0;
2591         plane_state->src_y = 0;
2592         plane_state->src_w = fb->width << 16;
2593         plane_state->src_h = fb->height << 16;
2594
2595         plane_state->crtc_x = 0;
2596         plane_state->crtc_y = 0;
2597         plane_state->crtc_w = fb->width;
2598         plane_state->crtc_h = fb->height;
2599
2600         intel_state->src.x1 = plane_state->src_x;
2601         intel_state->src.y1 = plane_state->src_y;
2602         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2603         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2604         intel_state->dst.x1 = plane_state->crtc_x;
2605         intel_state->dst.y1 = plane_state->crtc_y;
2606         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2607         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2608
2609         obj = intel_fb_obj(fb);
2610         if (obj->tiling_mode != I915_TILING_NONE)
2611                 dev_priv->preserve_bios_swizzle = true;
2612
2613         drm_framebuffer_reference(fb);
2614         primary->fb = primary->state->fb = fb;
2615         primary->crtc = primary->state->crtc = &intel_crtc->base;
2616         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2617         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2618 }
2619
2620 static void i9xx_update_primary_plane(struct drm_plane *primary,
2621                                       const struct intel_crtc_state *crtc_state,
2622                                       const struct intel_plane_state *plane_state)
2623 {
2624         struct drm_device *dev = primary->dev;
2625         struct drm_i915_private *dev_priv = dev->dev_private;
2626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2627         struct drm_framebuffer *fb = plane_state->base.fb;
2628         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2629         int plane = intel_crtc->plane;
2630         u32 linear_offset;
2631         u32 dspcntr;
2632         i915_reg_t reg = DSPCNTR(plane);
2633         unsigned int rotation = plane_state->base.rotation;
2634         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2635         int x = plane_state->src.x1 >> 16;
2636         int y = plane_state->src.y1 >> 16;
2637
2638         dspcntr = DISPPLANE_GAMMA_ENABLE;
2639
2640         dspcntr |= DISPLAY_PLANE_ENABLE;
2641
2642         if (INTEL_INFO(dev)->gen < 4) {
2643                 if (intel_crtc->pipe == PIPE_B)
2644                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2645
2646                 /* pipesrc and dspsize control the size that is scaled from,
2647                  * which should always be the user's requested size.
2648                  */
2649                 I915_WRITE(DSPSIZE(plane),
2650                            ((crtc_state->pipe_src_h - 1) << 16) |
2651                            (crtc_state->pipe_src_w - 1));
2652                 I915_WRITE(DSPPOS(plane), 0);
2653         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2654                 I915_WRITE(PRIMSIZE(plane),
2655                            ((crtc_state->pipe_src_h - 1) << 16) |
2656                            (crtc_state->pipe_src_w - 1));
2657                 I915_WRITE(PRIMPOS(plane), 0);
2658                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2659         }
2660
2661         switch (fb->pixel_format) {
2662         case DRM_FORMAT_C8:
2663                 dspcntr |= DISPPLANE_8BPP;
2664                 break;
2665         case DRM_FORMAT_XRGB1555:
2666                 dspcntr |= DISPPLANE_BGRX555;
2667                 break;
2668         case DRM_FORMAT_RGB565:
2669                 dspcntr |= DISPPLANE_BGRX565;
2670                 break;
2671         case DRM_FORMAT_XRGB8888:
2672                 dspcntr |= DISPPLANE_BGRX888;
2673                 break;
2674         case DRM_FORMAT_XBGR8888:
2675                 dspcntr |= DISPPLANE_RGBX888;
2676                 break;
2677         case DRM_FORMAT_XRGB2101010:
2678                 dspcntr |= DISPPLANE_BGRX101010;
2679                 break;
2680         case DRM_FORMAT_XBGR2101010:
2681                 dspcntr |= DISPPLANE_RGBX101010;
2682                 break;
2683         default:
2684                 BUG();
2685         }
2686
2687         if (INTEL_INFO(dev)->gen >= 4 &&
2688             obj->tiling_mode != I915_TILING_NONE)
2689                 dspcntr |= DISPPLANE_TILED;
2690
2691         if (IS_G4X(dev))
2692                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2693
2694         linear_offset = y * fb->pitches[0] + x * cpp;
2695
2696         if (INTEL_INFO(dev)->gen >= 4) {
2697                 intel_crtc->dspaddr_offset =
2698                         intel_compute_tile_offset(&x, &y, fb, 0,
2699                                                   fb->pitches[0], rotation);
2700                 linear_offset -= intel_crtc->dspaddr_offset;
2701         } else {
2702                 intel_crtc->dspaddr_offset = linear_offset;
2703         }
2704
2705         if (rotation == BIT(DRM_ROTATE_180)) {
2706                 dspcntr |= DISPPLANE_ROTATE_180;
2707
2708                 x += (crtc_state->pipe_src_w - 1);
2709                 y += (crtc_state->pipe_src_h - 1);
2710
2711                 /* Finding the last pixel of the last line of the display
2712                 data and adding to linear_offset*/
2713                 linear_offset +=
2714                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2715                         (crtc_state->pipe_src_w - 1) * cpp;
2716         }
2717
2718         intel_crtc->adjusted_x = x;
2719         intel_crtc->adjusted_y = y;
2720
2721         I915_WRITE(reg, dspcntr);
2722
2723         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2724         if (INTEL_INFO(dev)->gen >= 4) {
2725                 I915_WRITE(DSPSURF(plane),
2726                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2727                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2728                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2729         } else
2730                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2731         POSTING_READ(reg);
2732 }
2733
2734 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2735                                        struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740         int plane = intel_crtc->plane;
2741
2742         I915_WRITE(DSPCNTR(plane), 0);
2743         if (INTEL_INFO(dev_priv)->gen >= 4)
2744                 I915_WRITE(DSPSURF(plane), 0);
2745         else
2746                 I915_WRITE(DSPADDR(plane), 0);
2747         POSTING_READ(DSPCNTR(plane));
2748 }
2749
2750 static void ironlake_update_primary_plane(struct drm_plane *primary,
2751                                           const struct intel_crtc_state *crtc_state,
2752                                           const struct intel_plane_state *plane_state)
2753 {
2754         struct drm_device *dev = primary->dev;
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2757         struct drm_framebuffer *fb = plane_state->base.fb;
2758         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2759         int plane = intel_crtc->plane;
2760         u32 linear_offset;
2761         u32 dspcntr;
2762         i915_reg_t reg = DSPCNTR(plane);
2763         unsigned int rotation = plane_state->base.rotation;
2764         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2765         int x = plane_state->src.x1 >> 16;
2766         int y = plane_state->src.y1 >> 16;
2767
2768         dspcntr = DISPPLANE_GAMMA_ENABLE;
2769         dspcntr |= DISPLAY_PLANE_ENABLE;
2770
2771         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2772                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2773
2774         switch (fb->pixel_format) {
2775         case DRM_FORMAT_C8:
2776                 dspcntr |= DISPPLANE_8BPP;
2777                 break;
2778         case DRM_FORMAT_RGB565:
2779                 dspcntr |= DISPPLANE_BGRX565;
2780                 break;
2781         case DRM_FORMAT_XRGB8888:
2782                 dspcntr |= DISPPLANE_BGRX888;
2783                 break;
2784         case DRM_FORMAT_XBGR8888:
2785                 dspcntr |= DISPPLANE_RGBX888;
2786                 break;
2787         case DRM_FORMAT_XRGB2101010:
2788                 dspcntr |= DISPPLANE_BGRX101010;
2789                 break;
2790         case DRM_FORMAT_XBGR2101010:
2791                 dspcntr |= DISPPLANE_RGBX101010;
2792                 break;
2793         default:
2794                 BUG();
2795         }
2796
2797         if (obj->tiling_mode != I915_TILING_NONE)
2798                 dspcntr |= DISPPLANE_TILED;
2799
2800         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2801                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2802
2803         linear_offset = y * fb->pitches[0] + x * cpp;
2804         intel_crtc->dspaddr_offset =
2805                 intel_compute_tile_offset(&x, &y, fb, 0,
2806                                           fb->pitches[0], rotation);
2807         linear_offset -= intel_crtc->dspaddr_offset;
2808         if (rotation == BIT(DRM_ROTATE_180)) {
2809                 dspcntr |= DISPPLANE_ROTATE_180;
2810
2811                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2812                         x += (crtc_state->pipe_src_w - 1);
2813                         y += (crtc_state->pipe_src_h - 1);
2814
2815                         /* Finding the last pixel of the last line of the display
2816                         data and adding to linear_offset*/
2817                         linear_offset +=
2818                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2819                                 (crtc_state->pipe_src_w - 1) * cpp;
2820                 }
2821         }
2822
2823         intel_crtc->adjusted_x = x;
2824         intel_crtc->adjusted_y = y;
2825
2826         I915_WRITE(reg, dspcntr);
2827
2828         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2829         I915_WRITE(DSPSURF(plane),
2830                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2831         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2832                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2833         } else {
2834                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2835                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2836         }
2837         POSTING_READ(reg);
2838 }
2839
2840 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2841                               uint64_t fb_modifier, uint32_t pixel_format)
2842 {
2843         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2844                 return 64;
2845         } else {
2846                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2847
2848                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2849         }
2850 }
2851
2852 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2853                            struct drm_i915_gem_object *obj,
2854                            unsigned int plane)
2855 {
2856         struct i915_ggtt_view view;
2857         struct i915_vma *vma;
2858         u64 offset;
2859
2860         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2861                                 intel_plane->base.state->rotation);
2862
2863         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2864         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2865                 view.type))
2866                 return -1;
2867
2868         offset = vma->node.start;
2869
2870         if (plane == 1) {
2871                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2872                           PAGE_SIZE;
2873         }
2874
2875         WARN_ON(upper_32_bits(offset));
2876
2877         return lower_32_bits(offset);
2878 }
2879
2880 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2881 {
2882         struct drm_device *dev = intel_crtc->base.dev;
2883         struct drm_i915_private *dev_priv = dev->dev_private;
2884
2885         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2886         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2887         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2888 }
2889
2890 /*
2891  * This function detaches (aka. unbinds) unused scalers in hardware
2892  */
2893 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2894 {
2895         struct intel_crtc_scaler_state *scaler_state;
2896         int i;
2897
2898         scaler_state = &intel_crtc->config->scaler_state;
2899
2900         /* loop through and disable scalers that aren't in use */
2901         for (i = 0; i < intel_crtc->num_scalers; i++) {
2902                 if (!scaler_state->scalers[i].in_use)
2903                         skl_detach_scaler(intel_crtc, i);
2904         }
2905 }
2906
2907 u32 skl_plane_ctl_format(uint32_t pixel_format)
2908 {
2909         switch (pixel_format) {
2910         case DRM_FORMAT_C8:
2911                 return PLANE_CTL_FORMAT_INDEXED;
2912         case DRM_FORMAT_RGB565:
2913                 return PLANE_CTL_FORMAT_RGB_565;
2914         case DRM_FORMAT_XBGR8888:
2915                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2916         case DRM_FORMAT_XRGB8888:
2917                 return PLANE_CTL_FORMAT_XRGB_8888;
2918         /*
2919          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2920          * to be already pre-multiplied. We need to add a knob (or a different
2921          * DRM_FORMAT) for user-space to configure that.
2922          */
2923         case DRM_FORMAT_ABGR8888:
2924                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2925                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2926         case DRM_FORMAT_ARGB8888:
2927                 return PLANE_CTL_FORMAT_XRGB_8888 |
2928                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2929         case DRM_FORMAT_XRGB2101010:
2930                 return PLANE_CTL_FORMAT_XRGB_2101010;
2931         case DRM_FORMAT_XBGR2101010:
2932                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2933         case DRM_FORMAT_YUYV:
2934                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2935         case DRM_FORMAT_YVYU:
2936                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2937         case DRM_FORMAT_UYVY:
2938                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2939         case DRM_FORMAT_VYUY:
2940                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2941         default:
2942                 MISSING_CASE(pixel_format);
2943         }
2944
2945         return 0;
2946 }
2947
2948 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2949 {
2950         switch (fb_modifier) {
2951         case DRM_FORMAT_MOD_NONE:
2952                 break;
2953         case I915_FORMAT_MOD_X_TILED:
2954                 return PLANE_CTL_TILED_X;
2955         case I915_FORMAT_MOD_Y_TILED:
2956                 return PLANE_CTL_TILED_Y;
2957         case I915_FORMAT_MOD_Yf_TILED:
2958                 return PLANE_CTL_TILED_YF;
2959         default:
2960                 MISSING_CASE(fb_modifier);
2961         }
2962
2963         return 0;
2964 }
2965
2966 u32 skl_plane_ctl_rotation(unsigned int rotation)
2967 {
2968         switch (rotation) {
2969         case BIT(DRM_ROTATE_0):
2970                 break;
2971         /*
2972          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2973          * while i915 HW rotation is clockwise, thats why this swapping.
2974          */
2975         case BIT(DRM_ROTATE_90):
2976                 return PLANE_CTL_ROTATE_270;
2977         case BIT(DRM_ROTATE_180):
2978                 return PLANE_CTL_ROTATE_180;
2979         case BIT(DRM_ROTATE_270):
2980                 return PLANE_CTL_ROTATE_90;
2981         default:
2982                 MISSING_CASE(rotation);
2983         }
2984
2985         return 0;
2986 }
2987
2988 static void skylake_update_primary_plane(struct drm_plane *plane,
2989                                          const struct intel_crtc_state *crtc_state,
2990                                          const struct intel_plane_state *plane_state)
2991 {
2992         struct drm_device *dev = plane->dev;
2993         struct drm_i915_private *dev_priv = dev->dev_private;
2994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2995         struct drm_framebuffer *fb = plane_state->base.fb;
2996         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2997         int pipe = intel_crtc->pipe;
2998         u32 plane_ctl, stride_div, stride;
2999         u32 tile_height, plane_offset, plane_size;
3000         unsigned int rotation = plane_state->base.rotation;
3001         int x_offset, y_offset;
3002         u32 surf_addr;
3003         int scaler_id = plane_state->scaler_id;
3004         int src_x = plane_state->src.x1 >> 16;
3005         int src_y = plane_state->src.y1 >> 16;
3006         int src_w = drm_rect_width(&plane_state->src) >> 16;
3007         int src_h = drm_rect_height(&plane_state->src) >> 16;
3008         int dst_x = plane_state->dst.x1;
3009         int dst_y = plane_state->dst.y1;
3010         int dst_w = drm_rect_width(&plane_state->dst);
3011         int dst_h = drm_rect_height(&plane_state->dst);
3012
3013         plane_ctl = PLANE_CTL_ENABLE |
3014                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3015                     PLANE_CTL_PIPE_CSC_ENABLE;
3016
3017         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3018         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3019         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3020         plane_ctl |= skl_plane_ctl_rotation(rotation);
3021
3022         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3023                                                fb->pixel_format);
3024         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3025
3026         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3027
3028         if (intel_rotation_90_or_270(rotation)) {
3029                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3030
3031                 /* stride = Surface height in tiles */
3032                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3033                 stride = DIV_ROUND_UP(fb->height, tile_height);
3034                 x_offset = stride * tile_height - src_y - src_h;
3035                 y_offset = src_x;
3036                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3037         } else {
3038                 stride = fb->pitches[0] / stride_div;
3039                 x_offset = src_x;
3040                 y_offset = src_y;
3041                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3042         }
3043         plane_offset = y_offset << 16 | x_offset;
3044
3045         intel_crtc->adjusted_x = x_offset;
3046         intel_crtc->adjusted_y = y_offset;
3047
3048         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3049         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3050         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3051         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3052
3053         if (scaler_id >= 0) {
3054                 uint32_t ps_ctrl = 0;
3055
3056                 WARN_ON(!dst_w || !dst_h);
3057                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3058                         crtc_state->scaler_state.scalers[scaler_id].mode;
3059                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3060                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3061                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3062                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3063                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3064         } else {
3065                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3066         }
3067
3068         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3069
3070         POSTING_READ(PLANE_SURF(pipe, 0));
3071 }
3072
3073 static void skylake_disable_primary_plane(struct drm_plane *primary,
3074                                           struct drm_crtc *crtc)
3075 {
3076         struct drm_device *dev = crtc->dev;
3077         struct drm_i915_private *dev_priv = dev->dev_private;
3078         int pipe = to_intel_crtc(crtc)->pipe;
3079
3080         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3081         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3082         POSTING_READ(PLANE_SURF(pipe, 0));
3083 }
3084
3085 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3086 static int
3087 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3088                            int x, int y, enum mode_set_atomic state)
3089 {
3090         /* Support for kgdboc is disabled, this needs a major rework. */
3091         DRM_ERROR("legacy panic handler not supported any more.\n");
3092
3093         return -ENODEV;
3094 }
3095
3096 static void intel_complete_page_flips(struct drm_device *dev)
3097 {
3098         struct drm_crtc *crtc;
3099
3100         for_each_crtc(dev, crtc) {
3101                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3102                 enum plane plane = intel_crtc->plane;
3103
3104                 intel_prepare_page_flip(dev, plane);
3105                 intel_finish_page_flip_plane(dev, plane);
3106         }
3107 }
3108
3109 static void intel_update_primary_planes(struct drm_device *dev)
3110 {
3111         struct drm_crtc *crtc;
3112
3113         for_each_crtc(dev, crtc) {
3114                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3115                 struct intel_plane_state *plane_state;
3116
3117                 drm_modeset_lock_crtc(crtc, &plane->base);
3118                 plane_state = to_intel_plane_state(plane->base.state);
3119
3120                 if (plane_state->visible)
3121                         plane->update_plane(&plane->base,
3122                                             to_intel_crtc_state(crtc->state),
3123                                             plane_state);
3124
3125                 drm_modeset_unlock_crtc(crtc);
3126         }
3127 }
3128
3129 void intel_prepare_reset(struct drm_device *dev)
3130 {
3131         /* no reset support for gen2 */
3132         if (IS_GEN2(dev))
3133                 return;
3134
3135         /* reset doesn't touch the display */
3136         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3137                 return;
3138
3139         drm_modeset_lock_all(dev);
3140         /*
3141          * Disabling the crtcs gracefully seems nicer. Also the
3142          * g33 docs say we should at least disable all the planes.
3143          */
3144         intel_display_suspend(dev);
3145 }
3146
3147 void intel_finish_reset(struct drm_device *dev)
3148 {
3149         struct drm_i915_private *dev_priv = to_i915(dev);
3150
3151         /*
3152          * Flips in the rings will be nuked by the reset,
3153          * so complete all pending flips so that user space
3154          * will get its events and not get stuck.
3155          */
3156         intel_complete_page_flips(dev);
3157
3158         /* no reset support for gen2 */
3159         if (IS_GEN2(dev))
3160                 return;
3161
3162         /* reset doesn't touch the display */
3163         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3164                 /*
3165                  * Flips in the rings have been nuked by the reset,
3166                  * so update the base address of all primary
3167                  * planes to the the last fb to make sure we're
3168                  * showing the correct fb after a reset.
3169                  *
3170                  * FIXME: Atomic will make this obsolete since we won't schedule
3171                  * CS-based flips (which might get lost in gpu resets) any more.
3172                  */
3173                 intel_update_primary_planes(dev);
3174                 return;
3175         }
3176
3177         /*
3178          * The display has been reset as well,
3179          * so need a full re-initialization.
3180          */
3181         intel_runtime_pm_disable_interrupts(dev_priv);
3182         intel_runtime_pm_enable_interrupts(dev_priv);
3183
3184         intel_modeset_init_hw(dev);
3185
3186         spin_lock_irq(&dev_priv->irq_lock);
3187         if (dev_priv->display.hpd_irq_setup)
3188                 dev_priv->display.hpd_irq_setup(dev);
3189         spin_unlock_irq(&dev_priv->irq_lock);
3190
3191         intel_display_resume(dev);
3192
3193         intel_hpd_init(dev_priv);
3194
3195         drm_modeset_unlock_all(dev);
3196 }
3197
3198 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3199 {
3200         struct drm_device *dev = crtc->dev;
3201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3202         unsigned reset_counter;
3203         bool pending;
3204
3205         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3206         if (intel_crtc->reset_counter != reset_counter)
3207                 return false;
3208
3209         spin_lock_irq(&dev->event_lock);
3210         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3211         spin_unlock_irq(&dev->event_lock);
3212
3213         return pending;
3214 }
3215
3216 static void intel_update_pipe_config(struct intel_crtc *crtc,
3217                                      struct intel_crtc_state *old_crtc_state)
3218 {
3219         struct drm_device *dev = crtc->base.dev;
3220         struct drm_i915_private *dev_priv = dev->dev_private;
3221         struct intel_crtc_state *pipe_config =
3222                 to_intel_crtc_state(crtc->base.state);
3223
3224         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3225         crtc->base.mode = crtc->base.state->mode;
3226
3227         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3228                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3229                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3230
3231         /*
3232          * Update pipe size and adjust fitter if needed: the reason for this is
3233          * that in compute_mode_changes we check the native mode (not the pfit
3234          * mode) to see if we can flip rather than do a full mode set. In the
3235          * fastboot case, we'll flip, but if we don't update the pipesrc and
3236          * pfit state, we'll end up with a big fb scanned out into the wrong
3237          * sized surface.
3238          */
3239
3240         I915_WRITE(PIPESRC(crtc->pipe),
3241                    ((pipe_config->pipe_src_w - 1) << 16) |
3242                    (pipe_config->pipe_src_h - 1));
3243
3244         /* on skylake this is done by detaching scalers */
3245         if (INTEL_INFO(dev)->gen >= 9) {
3246                 skl_detach_scalers(crtc);
3247
3248                 if (pipe_config->pch_pfit.enabled)
3249                         skylake_pfit_enable(crtc);
3250         } else if (HAS_PCH_SPLIT(dev)) {
3251                 if (pipe_config->pch_pfit.enabled)
3252                         ironlake_pfit_enable(crtc);
3253                 else if (old_crtc_state->pch_pfit.enabled)
3254                         ironlake_pfit_disable(crtc, true);
3255         }
3256 }
3257
3258 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3259 {
3260         struct drm_device *dev = crtc->dev;
3261         struct drm_i915_private *dev_priv = dev->dev_private;
3262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3263         int pipe = intel_crtc->pipe;
3264         i915_reg_t reg;
3265         u32 temp;
3266
3267         /* enable normal train */
3268         reg = FDI_TX_CTL(pipe);
3269         temp = I915_READ(reg);
3270         if (IS_IVYBRIDGE(dev)) {
3271                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3272                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3273         } else {
3274                 temp &= ~FDI_LINK_TRAIN_NONE;
3275                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3276         }
3277         I915_WRITE(reg, temp);
3278
3279         reg = FDI_RX_CTL(pipe);
3280         temp = I915_READ(reg);
3281         if (HAS_PCH_CPT(dev)) {
3282                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3283                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3284         } else {
3285                 temp &= ~FDI_LINK_TRAIN_NONE;
3286                 temp |= FDI_LINK_TRAIN_NONE;
3287         }
3288         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3289
3290         /* wait one idle pattern time */
3291         POSTING_READ(reg);
3292         udelay(1000);
3293
3294         /* IVB wants error correction enabled */
3295         if (IS_IVYBRIDGE(dev))
3296                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3297                            FDI_FE_ERRC_ENABLE);
3298 }
3299
3300 /* The FDI link training functions for ILK/Ibexpeak. */
3301 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306         int pipe = intel_crtc->pipe;
3307         i915_reg_t reg;
3308         u32 temp, tries;
3309
3310         /* FDI needs bits from pipe first */
3311         assert_pipe_enabled(dev_priv, pipe);
3312
3313         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3314            for train result */
3315         reg = FDI_RX_IMR(pipe);
3316         temp = I915_READ(reg);
3317         temp &= ~FDI_RX_SYMBOL_LOCK;
3318         temp &= ~FDI_RX_BIT_LOCK;
3319         I915_WRITE(reg, temp);
3320         I915_READ(reg);
3321         udelay(150);
3322
3323         /* enable CPU FDI TX and PCH FDI RX */
3324         reg = FDI_TX_CTL(pipe);
3325         temp = I915_READ(reg);
3326         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3327         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3328         temp &= ~FDI_LINK_TRAIN_NONE;
3329         temp |= FDI_LINK_TRAIN_PATTERN_1;
3330         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3331
3332         reg = FDI_RX_CTL(pipe);
3333         temp = I915_READ(reg);
3334         temp &= ~FDI_LINK_TRAIN_NONE;
3335         temp |= FDI_LINK_TRAIN_PATTERN_1;
3336         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3337
3338         POSTING_READ(reg);
3339         udelay(150);
3340
3341         /* Ironlake workaround, enable clock pointer after FDI enable*/
3342         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3343         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3344                    FDI_RX_PHASE_SYNC_POINTER_EN);
3345
3346         reg = FDI_RX_IIR(pipe);
3347         for (tries = 0; tries < 5; tries++) {
3348                 temp = I915_READ(reg);
3349                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3350
3351                 if ((temp & FDI_RX_BIT_LOCK)) {
3352                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3353                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3354                         break;
3355                 }
3356         }
3357         if (tries == 5)
3358                 DRM_ERROR("FDI train 1 fail!\n");
3359
3360         /* Train 2 */
3361         reg = FDI_TX_CTL(pipe);
3362         temp = I915_READ(reg);
3363         temp &= ~FDI_LINK_TRAIN_NONE;
3364         temp |= FDI_LINK_TRAIN_PATTERN_2;
3365         I915_WRITE(reg, temp);
3366
3367         reg = FDI_RX_CTL(pipe);
3368         temp = I915_READ(reg);
3369         temp &= ~FDI_LINK_TRAIN_NONE;
3370         temp |= FDI_LINK_TRAIN_PATTERN_2;
3371         I915_WRITE(reg, temp);
3372
3373         POSTING_READ(reg);
3374         udelay(150);
3375
3376         reg = FDI_RX_IIR(pipe);
3377         for (tries = 0; tries < 5; tries++) {
3378                 temp = I915_READ(reg);
3379                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3380
3381                 if (temp & FDI_RX_SYMBOL_LOCK) {
3382                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3383                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3384                         break;
3385                 }
3386         }
3387         if (tries == 5)
3388                 DRM_ERROR("FDI train 2 fail!\n");
3389
3390         DRM_DEBUG_KMS("FDI train done\n");
3391
3392 }
3393
3394 static const int snb_b_fdi_train_param[] = {
3395         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3396         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3397         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3398         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3399 };
3400
3401 /* The FDI link training functions for SNB/Cougarpoint. */
3402 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3403 {
3404         struct drm_device *dev = crtc->dev;
3405         struct drm_i915_private *dev_priv = dev->dev_private;
3406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407         int pipe = intel_crtc->pipe;
3408         i915_reg_t reg;
3409         u32 temp, i, retry;
3410
3411         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3412            for train result */
3413         reg = FDI_RX_IMR(pipe);
3414         temp = I915_READ(reg);
3415         temp &= ~FDI_RX_SYMBOL_LOCK;
3416         temp &= ~FDI_RX_BIT_LOCK;
3417         I915_WRITE(reg, temp);
3418
3419         POSTING_READ(reg);
3420         udelay(150);
3421
3422         /* enable CPU FDI TX and PCH FDI RX */
3423         reg = FDI_TX_CTL(pipe);
3424         temp = I915_READ(reg);
3425         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3426         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3427         temp &= ~FDI_LINK_TRAIN_NONE;
3428         temp |= FDI_LINK_TRAIN_PATTERN_1;
3429         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3430         /* SNB-B */
3431         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3432         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3433
3434         I915_WRITE(FDI_RX_MISC(pipe),
3435                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3436
3437         reg = FDI_RX_CTL(pipe);
3438         temp = I915_READ(reg);
3439         if (HAS_PCH_CPT(dev)) {
3440                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3441                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3442         } else {
3443                 temp &= ~FDI_LINK_TRAIN_NONE;
3444                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3445         }
3446         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3447
3448         POSTING_READ(reg);
3449         udelay(150);
3450
3451         for (i = 0; i < 4; i++) {
3452                 reg = FDI_TX_CTL(pipe);
3453                 temp = I915_READ(reg);
3454                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3455                 temp |= snb_b_fdi_train_param[i];
3456                 I915_WRITE(reg, temp);
3457
3458                 POSTING_READ(reg);
3459                 udelay(500);
3460
3461                 for (retry = 0; retry < 5; retry++) {
3462                         reg = FDI_RX_IIR(pipe);
3463                         temp = I915_READ(reg);
3464                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465                         if (temp & FDI_RX_BIT_LOCK) {
3466                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3467                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3468                                 break;
3469                         }
3470                         udelay(50);
3471                 }
3472                 if (retry < 5)
3473                         break;
3474         }
3475         if (i == 4)
3476                 DRM_ERROR("FDI train 1 fail!\n");
3477
3478         /* Train 2 */
3479         reg = FDI_TX_CTL(pipe);
3480         temp = I915_READ(reg);
3481         temp &= ~FDI_LINK_TRAIN_NONE;
3482         temp |= FDI_LINK_TRAIN_PATTERN_2;
3483         if (IS_GEN6(dev)) {
3484                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3485                 /* SNB-B */
3486                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3487         }
3488         I915_WRITE(reg, temp);
3489
3490         reg = FDI_RX_CTL(pipe);
3491         temp = I915_READ(reg);
3492         if (HAS_PCH_CPT(dev)) {
3493                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3494                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3495         } else {
3496                 temp &= ~FDI_LINK_TRAIN_NONE;
3497                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3498         }
3499         I915_WRITE(reg, temp);
3500
3501         POSTING_READ(reg);
3502         udelay(150);
3503
3504         for (i = 0; i < 4; i++) {
3505                 reg = FDI_TX_CTL(pipe);
3506                 temp = I915_READ(reg);
3507                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3508                 temp |= snb_b_fdi_train_param[i];
3509                 I915_WRITE(reg, temp);
3510
3511                 POSTING_READ(reg);
3512                 udelay(500);
3513
3514                 for (retry = 0; retry < 5; retry++) {
3515                         reg = FDI_RX_IIR(pipe);
3516                         temp = I915_READ(reg);
3517                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3518                         if (temp & FDI_RX_SYMBOL_LOCK) {
3519                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3521                                 break;
3522                         }
3523                         udelay(50);
3524                 }
3525                 if (retry < 5)
3526                         break;
3527         }
3528         if (i == 4)
3529                 DRM_ERROR("FDI train 2 fail!\n");
3530
3531         DRM_DEBUG_KMS("FDI train done.\n");
3532 }
3533
3534 /* Manual link training for Ivy Bridge A0 parts */
3535 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3536 {
3537         struct drm_device *dev = crtc->dev;
3538         struct drm_i915_private *dev_priv = dev->dev_private;
3539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3540         int pipe = intel_crtc->pipe;
3541         i915_reg_t reg;
3542         u32 temp, i, j;
3543
3544         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3545            for train result */
3546         reg = FDI_RX_IMR(pipe);
3547         temp = I915_READ(reg);
3548         temp &= ~FDI_RX_SYMBOL_LOCK;
3549         temp &= ~FDI_RX_BIT_LOCK;
3550         I915_WRITE(reg, temp);
3551
3552         POSTING_READ(reg);
3553         udelay(150);
3554
3555         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3556                       I915_READ(FDI_RX_IIR(pipe)));
3557
3558         /* Try each vswing and preemphasis setting twice before moving on */
3559         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3560                 /* disable first in case we need to retry */
3561                 reg = FDI_TX_CTL(pipe);
3562                 temp = I915_READ(reg);
3563                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3564                 temp &= ~FDI_TX_ENABLE;
3565                 I915_WRITE(reg, temp);
3566
3567                 reg = FDI_RX_CTL(pipe);
3568                 temp = I915_READ(reg);
3569                 temp &= ~FDI_LINK_TRAIN_AUTO;
3570                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571                 temp &= ~FDI_RX_ENABLE;
3572                 I915_WRITE(reg, temp);
3573
3574                 /* enable CPU FDI TX and PCH FDI RX */
3575                 reg = FDI_TX_CTL(pipe);
3576                 temp = I915_READ(reg);
3577                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3578                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3579                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3580                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3581                 temp |= snb_b_fdi_train_param[j/2];
3582                 temp |= FDI_COMPOSITE_SYNC;
3583                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3584
3585                 I915_WRITE(FDI_RX_MISC(pipe),
3586                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3587
3588                 reg = FDI_RX_CTL(pipe);
3589                 temp = I915_READ(reg);
3590                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3591                 temp |= FDI_COMPOSITE_SYNC;
3592                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3593
3594                 POSTING_READ(reg);
3595                 udelay(1); /* should be 0.5us */
3596
3597                 for (i = 0; i < 4; i++) {
3598                         reg = FDI_RX_IIR(pipe);
3599                         temp = I915_READ(reg);
3600                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3601
3602                         if (temp & FDI_RX_BIT_LOCK ||
3603                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3604                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3606                                               i);
3607                                 break;
3608                         }
3609                         udelay(1); /* should be 0.5us */
3610                 }
3611                 if (i == 4) {
3612                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3613                         continue;
3614                 }
3615
3616                 /* Train 2 */
3617                 reg = FDI_TX_CTL(pipe);
3618                 temp = I915_READ(reg);
3619                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3620                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3621                 I915_WRITE(reg, temp);
3622
3623                 reg = FDI_RX_CTL(pipe);
3624                 temp = I915_READ(reg);
3625                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3626                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3627                 I915_WRITE(reg, temp);
3628
3629                 POSTING_READ(reg);
3630                 udelay(2); /* should be 1.5us */
3631
3632                 for (i = 0; i < 4; i++) {
3633                         reg = FDI_RX_IIR(pipe);
3634                         temp = I915_READ(reg);
3635                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3636
3637                         if (temp & FDI_RX_SYMBOL_LOCK ||
3638                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3639                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3640                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3641                                               i);
3642                                 goto train_done;
3643                         }
3644                         udelay(2); /* should be 1.5us */
3645                 }
3646                 if (i == 4)
3647                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3648         }
3649
3650 train_done:
3651         DRM_DEBUG_KMS("FDI train done.\n");
3652 }
3653
3654 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3655 {
3656         struct drm_device *dev = intel_crtc->base.dev;
3657         struct drm_i915_private *dev_priv = dev->dev_private;
3658         int pipe = intel_crtc->pipe;
3659         i915_reg_t reg;
3660         u32 temp;
3661
3662         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3663         reg = FDI_RX_CTL(pipe);
3664         temp = I915_READ(reg);
3665         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3666         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3667         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3668         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3669
3670         POSTING_READ(reg);
3671         udelay(200);
3672
3673         /* Switch from Rawclk to PCDclk */
3674         temp = I915_READ(reg);
3675         I915_WRITE(reg, temp | FDI_PCDCLK);
3676
3677         POSTING_READ(reg);
3678         udelay(200);
3679
3680         /* Enable CPU FDI TX PLL, always on for Ironlake */
3681         reg = FDI_TX_CTL(pipe);
3682         temp = I915_READ(reg);
3683         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3684                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3685
3686                 POSTING_READ(reg);
3687                 udelay(100);
3688         }
3689 }
3690
3691 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3692 {
3693         struct drm_device *dev = intel_crtc->base.dev;
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         int pipe = intel_crtc->pipe;
3696         i915_reg_t reg;
3697         u32 temp;
3698
3699         /* Switch from PCDclk to Rawclk */
3700         reg = FDI_RX_CTL(pipe);
3701         temp = I915_READ(reg);
3702         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3703
3704         /* Disable CPU FDI TX PLL */
3705         reg = FDI_TX_CTL(pipe);
3706         temp = I915_READ(reg);
3707         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3708
3709         POSTING_READ(reg);
3710         udelay(100);
3711
3712         reg = FDI_RX_CTL(pipe);
3713         temp = I915_READ(reg);
3714         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3715
3716         /* Wait for the clocks to turn off. */
3717         POSTING_READ(reg);
3718         udelay(100);
3719 }
3720
3721 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3722 {
3723         struct drm_device *dev = crtc->dev;
3724         struct drm_i915_private *dev_priv = dev->dev_private;
3725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3726         int pipe = intel_crtc->pipe;
3727         i915_reg_t reg;
3728         u32 temp;
3729
3730         /* disable CPU FDI tx and PCH FDI rx */
3731         reg = FDI_TX_CTL(pipe);
3732         temp = I915_READ(reg);
3733         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3734         POSTING_READ(reg);
3735
3736         reg = FDI_RX_CTL(pipe);
3737         temp = I915_READ(reg);
3738         temp &= ~(0x7 << 16);
3739         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3740         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3741
3742         POSTING_READ(reg);
3743         udelay(100);
3744
3745         /* Ironlake workaround, disable clock pointer after downing FDI */
3746         if (HAS_PCH_IBX(dev))
3747                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3748
3749         /* still set train pattern 1 */
3750         reg = FDI_TX_CTL(pipe);
3751         temp = I915_READ(reg);
3752         temp &= ~FDI_LINK_TRAIN_NONE;
3753         temp |= FDI_LINK_TRAIN_PATTERN_1;
3754         I915_WRITE(reg, temp);
3755
3756         reg = FDI_RX_CTL(pipe);
3757         temp = I915_READ(reg);
3758         if (HAS_PCH_CPT(dev)) {
3759                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3760                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3761         } else {
3762                 temp &= ~FDI_LINK_TRAIN_NONE;
3763                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3764         }
3765         /* BPC in FDI rx is consistent with that in PIPECONF */
3766         temp &= ~(0x07 << 16);
3767         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3768         I915_WRITE(reg, temp);
3769
3770         POSTING_READ(reg);
3771         udelay(100);
3772 }
3773
3774 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3775 {
3776         struct intel_crtc *crtc;
3777
3778         /* Note that we don't need to be called with mode_config.lock here
3779          * as our list of CRTC objects is static for the lifetime of the
3780          * device and so cannot disappear as we iterate. Similarly, we can
3781          * happily treat the predicates as racy, atomic checks as userspace
3782          * cannot claim and pin a new fb without at least acquring the
3783          * struct_mutex and so serialising with us.
3784          */
3785         for_each_intel_crtc(dev, crtc) {
3786                 if (atomic_read(&crtc->unpin_work_count) == 0)
3787                         continue;
3788
3789                 if (crtc->unpin_work)
3790                         intel_wait_for_vblank(dev, crtc->pipe);
3791
3792                 return true;
3793         }
3794
3795         return false;
3796 }
3797
3798 static void page_flip_completed(struct intel_crtc *intel_crtc)
3799 {
3800         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3801         struct intel_unpin_work *work = intel_crtc->unpin_work;
3802
3803         /* ensure that the unpin work is consistent wrt ->pending. */
3804         smp_rmb();
3805         intel_crtc->unpin_work = NULL;
3806
3807         if (work->event)
3808                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3809
3810         drm_crtc_vblank_put(&intel_crtc->base);
3811
3812         wake_up_all(&dev_priv->pending_flip_queue);
3813         queue_work(dev_priv->wq, &work->work);
3814
3815         trace_i915_flip_complete(intel_crtc->plane,
3816                                  work->pending_flip_obj);
3817 }
3818
3819 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         long ret;
3824
3825         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3826
3827         ret = wait_event_interruptible_timeout(
3828                                         dev_priv->pending_flip_queue,
3829                                         !intel_crtc_has_pending_flip(crtc),
3830                                         60*HZ);
3831
3832         if (ret < 0)
3833                 return ret;
3834
3835         if (ret == 0) {
3836                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3837
3838                 spin_lock_irq(&dev->event_lock);
3839                 if (intel_crtc->unpin_work) {
3840                         WARN_ONCE(1, "Removing stuck page flip\n");
3841                         page_flip_completed(intel_crtc);
3842                 }
3843                 spin_unlock_irq(&dev->event_lock);
3844         }
3845
3846         return 0;
3847 }
3848
3849 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3850 {
3851         u32 temp;
3852
3853         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3854
3855         mutex_lock(&dev_priv->sb_lock);
3856
3857         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3858         temp |= SBI_SSCCTL_DISABLE;
3859         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3860
3861         mutex_unlock(&dev_priv->sb_lock);
3862 }
3863
3864 /* Program iCLKIP clock to the desired frequency */
3865 static void lpt_program_iclkip(struct drm_crtc *crtc)
3866 {
3867         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3868         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3869         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3870         u32 temp;
3871
3872         lpt_disable_iclkip(dev_priv);
3873
3874         /* The iCLK virtual clock root frequency is in MHz,
3875          * but the adjusted_mode->crtc_clock in in KHz. To get the
3876          * divisors, it is necessary to divide one by another, so we
3877          * convert the virtual clock precision to KHz here for higher
3878          * precision.
3879          */
3880         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3881                 u32 iclk_virtual_root_freq = 172800 * 1000;
3882                 u32 iclk_pi_range = 64;
3883                 u32 desired_divisor;
3884
3885                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3886                                                     clock << auxdiv);
3887                 divsel = (desired_divisor / iclk_pi_range) - 2;
3888                 phaseinc = desired_divisor % iclk_pi_range;
3889
3890                 /*
3891                  * Near 20MHz is a corner case which is
3892                  * out of range for the 7-bit divisor
3893                  */
3894                 if (divsel <= 0x7f)
3895                         break;
3896         }
3897
3898         /* This should not happen with any sane values */
3899         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3900                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3901         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3902                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3903
3904         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3905                         clock,
3906                         auxdiv,
3907                         divsel,
3908                         phasedir,
3909                         phaseinc);
3910
3911         mutex_lock(&dev_priv->sb_lock);
3912
3913         /* Program SSCDIVINTPHASE6 */
3914         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3915         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3916         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3917         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3918         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3919         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3920         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3921         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3922
3923         /* Program SSCAUXDIV */
3924         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3925         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3926         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3927         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3928
3929         /* Enable modulator and associated divider */
3930         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3931         temp &= ~SBI_SSCCTL_DISABLE;
3932         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3933
3934         mutex_unlock(&dev_priv->sb_lock);
3935
3936         /* Wait for initialization time */
3937         udelay(24);
3938
3939         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3940 }
3941
3942 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3943 {
3944         u32 divsel, phaseinc, auxdiv;
3945         u32 iclk_virtual_root_freq = 172800 * 1000;
3946         u32 iclk_pi_range = 64;
3947         u32 desired_divisor;
3948         u32 temp;
3949
3950         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3951                 return 0;
3952
3953         mutex_lock(&dev_priv->sb_lock);
3954
3955         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3956         if (temp & SBI_SSCCTL_DISABLE) {
3957                 mutex_unlock(&dev_priv->sb_lock);
3958                 return 0;
3959         }
3960
3961         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3962         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3963                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3964         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3965                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3966
3967         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3968         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3969                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3970
3971         mutex_unlock(&dev_priv->sb_lock);
3972
3973         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3974
3975         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3976                                  desired_divisor << auxdiv);
3977 }
3978
3979 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3980                                                 enum pipe pch_transcoder)
3981 {
3982         struct drm_device *dev = crtc->base.dev;
3983         struct drm_i915_private *dev_priv = dev->dev_private;
3984         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3985
3986         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3987                    I915_READ(HTOTAL(cpu_transcoder)));
3988         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3989                    I915_READ(HBLANK(cpu_transcoder)));
3990         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3991                    I915_READ(HSYNC(cpu_transcoder)));
3992
3993         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3994                    I915_READ(VTOTAL(cpu_transcoder)));
3995         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3996                    I915_READ(VBLANK(cpu_transcoder)));
3997         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3998                    I915_READ(VSYNC(cpu_transcoder)));
3999         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4000                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4001 }
4002
4003 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4004 {
4005         struct drm_i915_private *dev_priv = dev->dev_private;
4006         uint32_t temp;
4007
4008         temp = I915_READ(SOUTH_CHICKEN1);
4009         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4010                 return;
4011
4012         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4013         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4014
4015         temp &= ~FDI_BC_BIFURCATION_SELECT;
4016         if (enable)
4017                 temp |= FDI_BC_BIFURCATION_SELECT;
4018
4019         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4020         I915_WRITE(SOUTH_CHICKEN1, temp);
4021         POSTING_READ(SOUTH_CHICKEN1);
4022 }
4023
4024 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4025 {
4026         struct drm_device *dev = intel_crtc->base.dev;
4027
4028         switch (intel_crtc->pipe) {
4029         case PIPE_A:
4030                 break;
4031         case PIPE_B:
4032                 if (intel_crtc->config->fdi_lanes > 2)
4033                         cpt_set_fdi_bc_bifurcation(dev, false);
4034                 else
4035                         cpt_set_fdi_bc_bifurcation(dev, true);
4036
4037                 break;
4038         case PIPE_C:
4039                 cpt_set_fdi_bc_bifurcation(dev, true);
4040
4041                 break;
4042         default:
4043                 BUG();
4044         }
4045 }
4046
4047 /* Return which DP Port should be selected for Transcoder DP control */
4048 static enum port
4049 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4050 {
4051         struct drm_device *dev = crtc->dev;
4052         struct intel_encoder *encoder;
4053
4054         for_each_encoder_on_crtc(dev, crtc, encoder) {
4055                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4056                     encoder->type == INTEL_OUTPUT_EDP)
4057                         return enc_to_dig_port(&encoder->base)->port;
4058         }
4059
4060         return -1;
4061 }
4062
4063 /*
4064  * Enable PCH resources required for PCH ports:
4065  *   - PCH PLLs
4066  *   - FDI training & RX/TX
4067  *   - update transcoder timings
4068  *   - DP transcoding bits
4069  *   - transcoder
4070  */
4071 static void ironlake_pch_enable(struct drm_crtc *crtc)
4072 {
4073         struct drm_device *dev = crtc->dev;
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4076         int pipe = intel_crtc->pipe;
4077         u32 temp;
4078
4079         assert_pch_transcoder_disabled(dev_priv, pipe);
4080
4081         if (IS_IVYBRIDGE(dev))
4082                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4083
4084         /* Write the TU size bits before fdi link training, so that error
4085          * detection works. */
4086         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4087                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4088
4089         /* For PCH output, training FDI link */
4090         dev_priv->display.fdi_link_train(crtc);
4091
4092         /* We need to program the right clock selection before writing the pixel
4093          * mutliplier into the DPLL. */
4094         if (HAS_PCH_CPT(dev)) {
4095                 u32 sel;
4096
4097                 temp = I915_READ(PCH_DPLL_SEL);
4098                 temp |= TRANS_DPLL_ENABLE(pipe);
4099                 sel = TRANS_DPLLB_SEL(pipe);
4100                 if (intel_crtc->config->shared_dpll ==
4101                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4102                         temp |= sel;
4103                 else
4104                         temp &= ~sel;
4105                 I915_WRITE(PCH_DPLL_SEL, temp);
4106         }
4107
4108         /* XXX: pch pll's can be enabled any time before we enable the PCH
4109          * transcoder, and we actually should do this to not upset any PCH
4110          * transcoder that already use the clock when we share it.
4111          *
4112          * Note that enable_shared_dpll tries to do the right thing, but
4113          * get_shared_dpll unconditionally resets the pll - we need that to have
4114          * the right LVDS enable sequence. */
4115         intel_enable_shared_dpll(intel_crtc);
4116
4117         /* set transcoder timing, panel must allow it */
4118         assert_panel_unlocked(dev_priv, pipe);
4119         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4120
4121         intel_fdi_normal_train(crtc);
4122
4123         /* For PCH DP, enable TRANS_DP_CTL */
4124         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4125                 const struct drm_display_mode *adjusted_mode =
4126                         &intel_crtc->config->base.adjusted_mode;
4127                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4128                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4129                 temp = I915_READ(reg);
4130                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4131                           TRANS_DP_SYNC_MASK |
4132                           TRANS_DP_BPC_MASK);
4133                 temp |= TRANS_DP_OUTPUT_ENABLE;
4134                 temp |= bpc << 9; /* same format but at 11:9 */
4135
4136                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4137                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4138                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4139                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4140
4141                 switch (intel_trans_dp_port_sel(crtc)) {
4142                 case PORT_B:
4143                         temp |= TRANS_DP_PORT_SEL_B;
4144                         break;
4145                 case PORT_C:
4146                         temp |= TRANS_DP_PORT_SEL_C;
4147                         break;
4148                 case PORT_D:
4149                         temp |= TRANS_DP_PORT_SEL_D;
4150                         break;
4151                 default:
4152                         BUG();
4153                 }
4154
4155                 I915_WRITE(reg, temp);
4156         }
4157
4158         ironlake_enable_pch_transcoder(dev_priv, pipe);
4159 }
4160
4161 static void lpt_pch_enable(struct drm_crtc *crtc)
4162 {
4163         struct drm_device *dev = crtc->dev;
4164         struct drm_i915_private *dev_priv = dev->dev_private;
4165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4166         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4167
4168         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4169
4170         lpt_program_iclkip(crtc);
4171
4172         /* Set transcoder timing. */
4173         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4174
4175         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4176 }
4177
4178 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4179 {
4180         struct drm_i915_private *dev_priv = dev->dev_private;
4181         i915_reg_t dslreg = PIPEDSL(pipe);
4182         u32 temp;
4183
4184         temp = I915_READ(dslreg);
4185         udelay(500);
4186         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4187                 if (wait_for(I915_READ(dslreg) != temp, 5))
4188                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4189         }
4190 }
4191
4192 static int
4193 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4194                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4195                   int src_w, int src_h, int dst_w, int dst_h)
4196 {
4197         struct intel_crtc_scaler_state *scaler_state =
4198                 &crtc_state->scaler_state;
4199         struct intel_crtc *intel_crtc =
4200                 to_intel_crtc(crtc_state->base.crtc);
4201         int need_scaling;
4202
4203         need_scaling = intel_rotation_90_or_270(rotation) ?
4204                 (src_h != dst_w || src_w != dst_h):
4205                 (src_w != dst_w || src_h != dst_h);
4206
4207         /*
4208          * if plane is being disabled or scaler is no more required or force detach
4209          *  - free scaler binded to this plane/crtc
4210          *  - in order to do this, update crtc->scaler_usage
4211          *
4212          * Here scaler state in crtc_state is set free so that
4213          * scaler can be assigned to other user. Actual register
4214          * update to free the scaler is done in plane/panel-fit programming.
4215          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4216          */
4217         if (force_detach || !need_scaling) {
4218                 if (*scaler_id >= 0) {
4219                         scaler_state->scaler_users &= ~(1 << scaler_user);
4220                         scaler_state->scalers[*scaler_id].in_use = 0;
4221
4222                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4223                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4224                                 intel_crtc->pipe, scaler_user, *scaler_id,
4225                                 scaler_state->scaler_users);
4226                         *scaler_id = -1;
4227                 }
4228                 return 0;
4229         }
4230
4231         /* range checks */
4232         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4233                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4234
4235                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4236                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4237                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4238                         "size is out of scaler range\n",
4239                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4240                 return -EINVAL;
4241         }
4242
4243         /* mark this plane as a scaler user in crtc_state */
4244         scaler_state->scaler_users |= (1 << scaler_user);
4245         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4246                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4247                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4248                 scaler_state->scaler_users);
4249
4250         return 0;
4251 }
4252
4253 /**
4254  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4255  *
4256  * @state: crtc's scaler state
4257  *
4258  * Return
4259  *     0 - scaler_usage updated successfully
4260  *    error - requested scaling cannot be supported or other error condition
4261  */
4262 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4263 {
4264         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4265         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4266
4267         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4268                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4269
4270         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4271                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4272                 state->pipe_src_w, state->pipe_src_h,
4273                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4274 }
4275
4276 /**
4277  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4278  *
4279  * @state: crtc's scaler state
4280  * @plane_state: atomic plane state to update
4281  *
4282  * Return
4283  *     0 - scaler_usage updated successfully
4284  *    error - requested scaling cannot be supported or other error condition
4285  */
4286 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4287                                    struct intel_plane_state *plane_state)
4288 {
4289
4290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4291         struct intel_plane *intel_plane =
4292                 to_intel_plane(plane_state->base.plane);
4293         struct drm_framebuffer *fb = plane_state->base.fb;
4294         int ret;
4295
4296         bool force_detach = !fb || !plane_state->visible;
4297
4298         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4299                       intel_plane->base.base.id, intel_crtc->pipe,
4300                       drm_plane_index(&intel_plane->base));
4301
4302         ret = skl_update_scaler(crtc_state, force_detach,
4303                                 drm_plane_index(&intel_plane->base),
4304                                 &plane_state->scaler_id,
4305                                 plane_state->base.rotation,
4306                                 drm_rect_width(&plane_state->src) >> 16,
4307                                 drm_rect_height(&plane_state->src) >> 16,
4308                                 drm_rect_width(&plane_state->dst),
4309                                 drm_rect_height(&plane_state->dst));
4310
4311         if (ret || plane_state->scaler_id < 0)
4312                 return ret;
4313
4314         /* check colorkey */
4315         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4316                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4317                               intel_plane->base.base.id);
4318                 return -EINVAL;
4319         }
4320
4321         /* Check src format */
4322         switch (fb->pixel_format) {
4323         case DRM_FORMAT_RGB565:
4324         case DRM_FORMAT_XBGR8888:
4325         case DRM_FORMAT_XRGB8888:
4326         case DRM_FORMAT_ABGR8888:
4327         case DRM_FORMAT_ARGB8888:
4328         case DRM_FORMAT_XRGB2101010:
4329         case DRM_FORMAT_XBGR2101010:
4330         case DRM_FORMAT_YUYV:
4331         case DRM_FORMAT_YVYU:
4332         case DRM_FORMAT_UYVY:
4333         case DRM_FORMAT_VYUY:
4334                 break;
4335         default:
4336                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4337                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4338                 return -EINVAL;
4339         }
4340
4341         return 0;
4342 }
4343
4344 static void skylake_scaler_disable(struct intel_crtc *crtc)
4345 {
4346         int i;
4347
4348         for (i = 0; i < crtc->num_scalers; i++)
4349                 skl_detach_scaler(crtc, i);
4350 }
4351
4352 static void skylake_pfit_enable(struct intel_crtc *crtc)
4353 {
4354         struct drm_device *dev = crtc->base.dev;
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         int pipe = crtc->pipe;
4357         struct intel_crtc_scaler_state *scaler_state =
4358                 &crtc->config->scaler_state;
4359
4360         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4361
4362         if (crtc->config->pch_pfit.enabled) {
4363                 int id;
4364
4365                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4366                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4367                         return;
4368                 }
4369
4370                 id = scaler_state->scaler_id;
4371                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4372                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4373                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4374                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4375
4376                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4377         }
4378 }
4379
4380 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4381 {
4382         struct drm_device *dev = crtc->base.dev;
4383         struct drm_i915_private *dev_priv = dev->dev_private;
4384         int pipe = crtc->pipe;
4385
4386         if (crtc->config->pch_pfit.enabled) {
4387                 /* Force use of hard-coded filter coefficients
4388                  * as some pre-programmed values are broken,
4389                  * e.g. x201.
4390                  */
4391                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4392                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4393                                                  PF_PIPE_SEL_IVB(pipe));
4394                 else
4395                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4396                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4397                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4398         }
4399 }
4400
4401 void hsw_enable_ips(struct intel_crtc *crtc)
4402 {
4403         struct drm_device *dev = crtc->base.dev;
4404         struct drm_i915_private *dev_priv = dev->dev_private;
4405
4406         if (!crtc->config->ips_enabled)
4407                 return;
4408
4409         /*
4410          * We can only enable IPS after we enable a plane and wait for a vblank
4411          * This function is called from post_plane_update, which is run after
4412          * a vblank wait.
4413          */
4414
4415         assert_plane_enabled(dev_priv, crtc->plane);
4416         if (IS_BROADWELL(dev)) {
4417                 mutex_lock(&dev_priv->rps.hw_lock);
4418                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4419                 mutex_unlock(&dev_priv->rps.hw_lock);
4420                 /* Quoting Art Runyan: "its not safe to expect any particular
4421                  * value in IPS_CTL bit 31 after enabling IPS through the
4422                  * mailbox." Moreover, the mailbox may return a bogus state,
4423                  * so we need to just enable it and continue on.
4424                  */
4425         } else {
4426                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4427                 /* The bit only becomes 1 in the next vblank, so this wait here
4428                  * is essentially intel_wait_for_vblank. If we don't have this
4429                  * and don't wait for vblanks until the end of crtc_enable, then
4430                  * the HW state readout code will complain that the expected
4431                  * IPS_CTL value is not the one we read. */
4432                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4433                         DRM_ERROR("Timed out waiting for IPS enable\n");
4434         }
4435 }
4436
4437 void hsw_disable_ips(struct intel_crtc *crtc)
4438 {
4439         struct drm_device *dev = crtc->base.dev;
4440         struct drm_i915_private *dev_priv = dev->dev_private;
4441
4442         if (!crtc->config->ips_enabled)
4443                 return;
4444
4445         assert_plane_enabled(dev_priv, crtc->plane);
4446         if (IS_BROADWELL(dev)) {
4447                 mutex_lock(&dev_priv->rps.hw_lock);
4448                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4449                 mutex_unlock(&dev_priv->rps.hw_lock);
4450                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4451                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4452                         DRM_ERROR("Timed out waiting for IPS disable\n");
4453         } else {
4454                 I915_WRITE(IPS_CTL, 0);
4455                 POSTING_READ(IPS_CTL);
4456         }
4457
4458         /* We need to wait for a vblank before we can disable the plane. */
4459         intel_wait_for_vblank(dev, crtc->pipe);
4460 }
4461
4462 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4463 {
4464         if (intel_crtc->overlay) {
4465                 struct drm_device *dev = intel_crtc->base.dev;
4466                 struct drm_i915_private *dev_priv = dev->dev_private;
4467
4468                 mutex_lock(&dev->struct_mutex);
4469                 dev_priv->mm.interruptible = false;
4470                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4471                 dev_priv->mm.interruptible = true;
4472                 mutex_unlock(&dev->struct_mutex);
4473         }
4474
4475         /* Let userspace switch the overlay on again. In most cases userspace
4476          * has to recompute where to put it anyway.
4477          */
4478 }
4479
4480 /**
4481  * intel_post_enable_primary - Perform operations after enabling primary plane
4482  * @crtc: the CRTC whose primary plane was just enabled
4483  *
4484  * Performs potentially sleeping operations that must be done after the primary
4485  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4486  * called due to an explicit primary plane update, or due to an implicit
4487  * re-enable that is caused when a sprite plane is updated to no longer
4488  * completely hide the primary plane.
4489  */
4490 static void
4491 intel_post_enable_primary(struct drm_crtc *crtc)
4492 {
4493         struct drm_device *dev = crtc->dev;
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4496         int pipe = intel_crtc->pipe;
4497
4498         /*
4499          * FIXME IPS should be fine as long as one plane is
4500          * enabled, but in practice it seems to have problems
4501          * when going from primary only to sprite only and vice
4502          * versa.
4503          */
4504         hsw_enable_ips(intel_crtc);
4505
4506         /*
4507          * Gen2 reports pipe underruns whenever all planes are disabled.
4508          * So don't enable underrun reporting before at least some planes
4509          * are enabled.
4510          * FIXME: Need to fix the logic to work when we turn off all planes
4511          * but leave the pipe running.
4512          */
4513         if (IS_GEN2(dev))
4514                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4515
4516         /* Underruns don't always raise interrupts, so check manually. */
4517         intel_check_cpu_fifo_underruns(dev_priv);
4518         intel_check_pch_fifo_underruns(dev_priv);
4519 }
4520
4521 /* FIXME move all this to pre_plane_update() with proper state tracking */
4522 static void
4523 intel_pre_disable_primary(struct drm_crtc *crtc)
4524 {
4525         struct drm_device *dev = crtc->dev;
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4528         int pipe = intel_crtc->pipe;
4529
4530         /*
4531          * Gen2 reports pipe underruns whenever all planes are disabled.
4532          * So diasble underrun reporting before all the planes get disabled.
4533          * FIXME: Need to fix the logic to work when we turn off all planes
4534          * but leave the pipe running.
4535          */
4536         if (IS_GEN2(dev))
4537                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4538
4539         /*
4540          * FIXME IPS should be fine as long as one plane is
4541          * enabled, but in practice it seems to have problems
4542          * when going from primary only to sprite only and vice
4543          * versa.
4544          */
4545         hsw_disable_ips(intel_crtc);
4546 }
4547
4548 /* FIXME get rid of this and use pre_plane_update */
4549 static void
4550 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4551 {
4552         struct drm_device *dev = crtc->dev;
4553         struct drm_i915_private *dev_priv = dev->dev_private;
4554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4555         int pipe = intel_crtc->pipe;
4556
4557         intel_pre_disable_primary(crtc);
4558
4559         /*
4560          * Vblank time updates from the shadow to live plane control register
4561          * are blocked if the memory self-refresh mode is active at that
4562          * moment. So to make sure the plane gets truly disabled, disable
4563          * first the self-refresh mode. The self-refresh enable bit in turn
4564          * will be checked/applied by the HW only at the next frame start
4565          * event which is after the vblank start event, so we need to have a
4566          * wait-for-vblank between disabling the plane and the pipe.
4567          */
4568         if (HAS_GMCH_DISPLAY(dev)) {
4569                 intel_set_memory_cxsr(dev_priv, false);
4570                 dev_priv->wm.vlv.cxsr = false;
4571                 intel_wait_for_vblank(dev, pipe);
4572         }
4573 }
4574
4575 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4576 {
4577         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4578         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4579         struct intel_crtc_state *pipe_config =
4580                 to_intel_crtc_state(crtc->base.state);
4581         struct drm_device *dev = crtc->base.dev;
4582         struct drm_plane *primary = crtc->base.primary;
4583         struct drm_plane_state *old_pri_state =
4584                 drm_atomic_get_existing_plane_state(old_state, primary);
4585
4586         intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4587
4588         crtc->wm.cxsr_allowed = true;
4589
4590         if (pipe_config->update_wm_post && pipe_config->base.active)
4591                 intel_update_watermarks(&crtc->base);
4592
4593         if (old_pri_state) {
4594                 struct intel_plane_state *primary_state =
4595                         to_intel_plane_state(primary->state);
4596                 struct intel_plane_state *old_primary_state =
4597                         to_intel_plane_state(old_pri_state);
4598
4599                 intel_fbc_post_update(crtc);
4600
4601                 if (primary_state->visible &&
4602                     (needs_modeset(&pipe_config->base) ||
4603                      !old_primary_state->visible))
4604                         intel_post_enable_primary(&crtc->base);
4605         }
4606 }
4607
4608 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4609 {
4610         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4611         struct drm_device *dev = crtc->base.dev;
4612         struct drm_i915_private *dev_priv = dev->dev_private;
4613         struct intel_crtc_state *pipe_config =
4614                 to_intel_crtc_state(crtc->base.state);
4615         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4616         struct drm_plane *primary = crtc->base.primary;
4617         struct drm_plane_state *old_pri_state =
4618                 drm_atomic_get_existing_plane_state(old_state, primary);
4619         bool modeset = needs_modeset(&pipe_config->base);
4620
4621         if (old_pri_state) {
4622                 struct intel_plane_state *primary_state =
4623                         to_intel_plane_state(primary->state);
4624                 struct intel_plane_state *old_primary_state =
4625                         to_intel_plane_state(old_pri_state);
4626
4627                 intel_fbc_pre_update(crtc);
4628
4629                 if (old_primary_state->visible &&
4630                     (modeset || !primary_state->visible))
4631                         intel_pre_disable_primary(&crtc->base);
4632         }
4633
4634         if (pipe_config->disable_cxsr) {
4635                 crtc->wm.cxsr_allowed = false;
4636
4637                 /*
4638                  * Vblank time updates from the shadow to live plane control register
4639                  * are blocked if the memory self-refresh mode is active at that
4640                  * moment. So to make sure the plane gets truly disabled, disable
4641                  * first the self-refresh mode. The self-refresh enable bit in turn
4642                  * will be checked/applied by the HW only at the next frame start
4643                  * event which is after the vblank start event, so we need to have a
4644                  * wait-for-vblank between disabling the plane and the pipe.
4645                  */
4646                 if (old_crtc_state->base.active) {
4647                         intel_set_memory_cxsr(dev_priv, false);
4648                         dev_priv->wm.vlv.cxsr = false;
4649                         intel_wait_for_vblank(dev, crtc->pipe);
4650                 }
4651         }
4652
4653         /*
4654          * IVB workaround: must disable low power watermarks for at least
4655          * one frame before enabling scaling.  LP watermarks can be re-enabled
4656          * when scaling is disabled.
4657          *
4658          * WaCxSRDisabledForSpriteScaling:ivb
4659          */
4660         if (pipe_config->disable_lp_wm) {
4661                 ilk_disable_lp_wm(dev);
4662                 intel_wait_for_vblank(dev, crtc->pipe);
4663         }
4664
4665         /*
4666          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4667          * watermark programming here.
4668          */
4669         if (needs_modeset(&pipe_config->base))
4670                 return;
4671
4672         /*
4673          * For platforms that support atomic watermarks, program the
4674          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4675          * will be the intermediate values that are safe for both pre- and
4676          * post- vblank; when vblank happens, the 'active' values will be set
4677          * to the final 'target' values and we'll do this again to get the
4678          * optimal watermarks.  For gen9+ platforms, the values we program here
4679          * will be the final target values which will get automatically latched
4680          * at vblank time; no further programming will be necessary.
4681          *
4682          * If a platform hasn't been transitioned to atomic watermarks yet,
4683          * we'll continue to update watermarks the old way, if flags tell
4684          * us to.
4685          */
4686         if (dev_priv->display.initial_watermarks != NULL)
4687                 dev_priv->display.initial_watermarks(pipe_config);
4688         else if (pipe_config->update_wm_pre)
4689                 intel_update_watermarks(&crtc->base);
4690 }
4691
4692 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4693 {
4694         struct drm_device *dev = crtc->dev;
4695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4696         struct drm_plane *p;
4697         int pipe = intel_crtc->pipe;
4698
4699         intel_crtc_dpms_overlay_disable(intel_crtc);
4700
4701         drm_for_each_plane_mask(p, dev, plane_mask)
4702                 to_intel_plane(p)->disable_plane(p, crtc);
4703
4704         /*
4705          * FIXME: Once we grow proper nuclear flip support out of this we need
4706          * to compute the mask of flip planes precisely. For the time being
4707          * consider this a flip to a NULL plane.
4708          */
4709         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4710 }
4711
4712 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4713 {
4714         struct drm_device *dev = crtc->dev;
4715         struct drm_i915_private *dev_priv = dev->dev_private;
4716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4717         struct intel_encoder *encoder;
4718         int pipe = intel_crtc->pipe;
4719         struct intel_crtc_state *pipe_config =
4720                 to_intel_crtc_state(crtc->state);
4721
4722         if (WARN_ON(intel_crtc->active))
4723                 return;
4724
4725         /*
4726          * Sometimes spurious CPU pipe underruns happen during FDI
4727          * training, at least with VGA+HDMI cloning. Suppress them.
4728          *
4729          * On ILK we get an occasional spurious CPU pipe underruns
4730          * between eDP port A enable and vdd enable. Also PCH port
4731          * enable seems to result in the occasional CPU pipe underrun.
4732          *
4733          * Spurious PCH underruns also occur during PCH enabling.
4734          */
4735         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4736                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4737         if (intel_crtc->config->has_pch_encoder)
4738                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4739
4740         if (intel_crtc->config->has_pch_encoder)
4741                 intel_prepare_shared_dpll(intel_crtc);
4742
4743         if (intel_crtc->config->has_dp_encoder)
4744                 intel_dp_set_m_n(intel_crtc, M1_N1);
4745
4746         intel_set_pipe_timings(intel_crtc);
4747         intel_set_pipe_src_size(intel_crtc);
4748
4749         if (intel_crtc->config->has_pch_encoder) {
4750                 intel_cpu_transcoder_set_m_n(intel_crtc,
4751                                      &intel_crtc->config->fdi_m_n, NULL);
4752         }
4753
4754         ironlake_set_pipeconf(crtc);
4755
4756         intel_crtc->active = true;
4757
4758         for_each_encoder_on_crtc(dev, crtc, encoder)
4759                 if (encoder->pre_enable)
4760                         encoder->pre_enable(encoder);
4761
4762         if (intel_crtc->config->has_pch_encoder) {
4763                 /* Note: FDI PLL enabling _must_ be done before we enable the
4764                  * cpu pipes, hence this is separate from all the other fdi/pch
4765                  * enabling. */
4766                 ironlake_fdi_pll_enable(intel_crtc);
4767         } else {
4768                 assert_fdi_tx_disabled(dev_priv, pipe);
4769                 assert_fdi_rx_disabled(dev_priv, pipe);
4770         }
4771
4772         ironlake_pfit_enable(intel_crtc);
4773
4774         /*
4775          * On ILK+ LUT must be loaded before the pipe is running but with
4776          * clocks enabled
4777          */
4778         intel_color_load_luts(&pipe_config->base);
4779
4780         if (dev_priv->display.initial_watermarks != NULL)
4781                 dev_priv->display.initial_watermarks(intel_crtc->config);
4782         intel_enable_pipe(intel_crtc);
4783
4784         if (intel_crtc->config->has_pch_encoder)
4785                 ironlake_pch_enable(crtc);
4786
4787         assert_vblank_disabled(crtc);
4788         drm_crtc_vblank_on(crtc);
4789
4790         for_each_encoder_on_crtc(dev, crtc, encoder)
4791                 encoder->enable(encoder);
4792
4793         if (HAS_PCH_CPT(dev))
4794                 cpt_verify_modeset(dev, intel_crtc->pipe);
4795
4796         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4797         if (intel_crtc->config->has_pch_encoder)
4798                 intel_wait_for_vblank(dev, pipe);
4799         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4800         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4801 }
4802
4803 /* IPS only exists on ULT machines and is tied to pipe A. */
4804 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4805 {
4806         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4807 }
4808
4809 static void haswell_crtc_enable(struct drm_crtc *crtc)
4810 {
4811         struct drm_device *dev = crtc->dev;
4812         struct drm_i915_private *dev_priv = dev->dev_private;
4813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814         struct intel_encoder *encoder;
4815         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4816         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4817         struct intel_crtc_state *pipe_config =
4818                 to_intel_crtc_state(crtc->state);
4819
4820         if (WARN_ON(intel_crtc->active))
4821                 return;
4822
4823         if (intel_crtc->config->has_pch_encoder)
4824                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4825                                                       false);
4826
4827         if (intel_crtc->config->shared_dpll)
4828                 intel_enable_shared_dpll(intel_crtc);
4829
4830         if (intel_crtc->config->has_dp_encoder)
4831                 intel_dp_set_m_n(intel_crtc, M1_N1);
4832
4833         if (!intel_crtc->config->has_dsi_encoder)
4834                 intel_set_pipe_timings(intel_crtc);
4835
4836         intel_set_pipe_src_size(intel_crtc);
4837
4838         if (cpu_transcoder != TRANSCODER_EDP &&
4839             !transcoder_is_dsi(cpu_transcoder)) {
4840                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4841                            intel_crtc->config->pixel_multiplier - 1);
4842         }
4843
4844         if (intel_crtc->config->has_pch_encoder) {
4845                 intel_cpu_transcoder_set_m_n(intel_crtc,
4846                                      &intel_crtc->config->fdi_m_n, NULL);
4847         }
4848
4849         if (!intel_crtc->config->has_dsi_encoder)
4850                 haswell_set_pipeconf(crtc);
4851
4852         haswell_set_pipemisc(crtc);
4853
4854         intel_color_set_csc(&pipe_config->base);
4855
4856         intel_crtc->active = true;
4857
4858         if (intel_crtc->config->has_pch_encoder)
4859                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4860         else
4861                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4862
4863         for_each_encoder_on_crtc(dev, crtc, encoder) {
4864                 if (encoder->pre_enable)
4865                         encoder->pre_enable(encoder);
4866         }
4867
4868         if (intel_crtc->config->has_pch_encoder)
4869                 dev_priv->display.fdi_link_train(crtc);
4870
4871         if (!intel_crtc->config->has_dsi_encoder)
4872                 intel_ddi_enable_pipe_clock(intel_crtc);
4873
4874         if (INTEL_INFO(dev)->gen >= 9)
4875                 skylake_pfit_enable(intel_crtc);
4876         else
4877                 ironlake_pfit_enable(intel_crtc);
4878
4879         /*
4880          * On ILK+ LUT must be loaded before the pipe is running but with
4881          * clocks enabled
4882          */
4883         intel_color_load_luts(&pipe_config->base);
4884
4885         intel_ddi_set_pipe_settings(crtc);
4886         if (!intel_crtc->config->has_dsi_encoder)
4887                 intel_ddi_enable_transcoder_func(crtc);
4888
4889         if (dev_priv->display.initial_watermarks != NULL)
4890                 dev_priv->display.initial_watermarks(pipe_config);
4891         else
4892                 intel_update_watermarks(crtc);
4893
4894         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4895         if (!intel_crtc->config->has_dsi_encoder)
4896                 intel_enable_pipe(intel_crtc);
4897
4898         if (intel_crtc->config->has_pch_encoder)
4899                 lpt_pch_enable(crtc);
4900
4901         if (intel_crtc->config->dp_encoder_is_mst)
4902                 intel_ddi_set_vc_payload_alloc(crtc, true);
4903
4904         assert_vblank_disabled(crtc);
4905         drm_crtc_vblank_on(crtc);
4906
4907         for_each_encoder_on_crtc(dev, crtc, encoder) {
4908                 encoder->enable(encoder);
4909                 intel_opregion_notify_encoder(encoder, true);
4910         }
4911
4912         if (intel_crtc->config->has_pch_encoder) {
4913                 intel_wait_for_vblank(dev, pipe);
4914                 intel_wait_for_vblank(dev, pipe);
4915                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4916                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4917                                                       true);
4918         }
4919
4920         /* If we change the relative order between pipe/planes enabling, we need
4921          * to change the workaround. */
4922         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4923         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4924                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4925                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4926         }
4927 }
4928
4929 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4930 {
4931         struct drm_device *dev = crtc->base.dev;
4932         struct drm_i915_private *dev_priv = dev->dev_private;
4933         int pipe = crtc->pipe;
4934
4935         /* To avoid upsetting the power well on haswell only disable the pfit if
4936          * it's in use. The hw state code will make sure we get this right. */
4937         if (force || crtc->config->pch_pfit.enabled) {
4938                 I915_WRITE(PF_CTL(pipe), 0);
4939                 I915_WRITE(PF_WIN_POS(pipe), 0);
4940                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4941         }
4942 }
4943
4944 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4945 {
4946         struct drm_device *dev = crtc->dev;
4947         struct drm_i915_private *dev_priv = dev->dev_private;
4948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4949         struct intel_encoder *encoder;
4950         int pipe = intel_crtc->pipe;
4951
4952         /*
4953          * Sometimes spurious CPU pipe underruns happen when the
4954          * pipe is already disabled, but FDI RX/TX is still enabled.
4955          * Happens at least with VGA+HDMI cloning. Suppress them.
4956          */
4957         if (intel_crtc->config->has_pch_encoder) {
4958                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4959                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4960         }
4961
4962         for_each_encoder_on_crtc(dev, crtc, encoder)
4963                 encoder->disable(encoder);
4964
4965         drm_crtc_vblank_off(crtc);
4966         assert_vblank_disabled(crtc);
4967
4968         intel_disable_pipe(intel_crtc);
4969
4970         ironlake_pfit_disable(intel_crtc, false);
4971
4972         if (intel_crtc->config->has_pch_encoder)
4973                 ironlake_fdi_disable(crtc);
4974
4975         for_each_encoder_on_crtc(dev, crtc, encoder)
4976                 if (encoder->post_disable)
4977                         encoder->post_disable(encoder);
4978
4979         if (intel_crtc->config->has_pch_encoder) {
4980                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4981
4982                 if (HAS_PCH_CPT(dev)) {
4983                         i915_reg_t reg;
4984                         u32 temp;
4985
4986                         /* disable TRANS_DP_CTL */
4987                         reg = TRANS_DP_CTL(pipe);
4988                         temp = I915_READ(reg);
4989                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4990                                   TRANS_DP_PORT_SEL_MASK);
4991                         temp |= TRANS_DP_PORT_SEL_NONE;
4992                         I915_WRITE(reg, temp);
4993
4994                         /* disable DPLL_SEL */
4995                         temp = I915_READ(PCH_DPLL_SEL);
4996                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4997                         I915_WRITE(PCH_DPLL_SEL, temp);
4998                 }
4999
5000                 ironlake_fdi_pll_disable(intel_crtc);
5001         }
5002
5003         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5004         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5005 }
5006
5007 static void haswell_crtc_disable(struct drm_crtc *crtc)
5008 {
5009         struct drm_device *dev = crtc->dev;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012         struct intel_encoder *encoder;
5013         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5014
5015         if (intel_crtc->config->has_pch_encoder)
5016                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5017                                                       false);
5018
5019         for_each_encoder_on_crtc(dev, crtc, encoder) {
5020                 intel_opregion_notify_encoder(encoder, false);
5021                 encoder->disable(encoder);
5022         }
5023
5024         drm_crtc_vblank_off(crtc);
5025         assert_vblank_disabled(crtc);
5026
5027         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5028         if (!intel_crtc->config->has_dsi_encoder)
5029                 intel_disable_pipe(intel_crtc);
5030
5031         if (intel_crtc->config->dp_encoder_is_mst)
5032                 intel_ddi_set_vc_payload_alloc(crtc, false);
5033
5034         if (!intel_crtc->config->has_dsi_encoder)
5035                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5036
5037         if (INTEL_INFO(dev)->gen >= 9)
5038                 skylake_scaler_disable(intel_crtc);
5039         else
5040                 ironlake_pfit_disable(intel_crtc, false);
5041
5042         if (!intel_crtc->config->has_dsi_encoder)
5043                 intel_ddi_disable_pipe_clock(intel_crtc);
5044
5045         for_each_encoder_on_crtc(dev, crtc, encoder)
5046                 if (encoder->post_disable)
5047                         encoder->post_disable(encoder);
5048
5049         if (intel_crtc->config->has_pch_encoder) {
5050                 lpt_disable_pch_transcoder(dev_priv);
5051                 lpt_disable_iclkip(dev_priv);
5052                 intel_ddi_fdi_disable(crtc);
5053
5054                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5055                                                       true);
5056         }
5057 }
5058
5059 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5060 {
5061         struct drm_device *dev = crtc->base.dev;
5062         struct drm_i915_private *dev_priv = dev->dev_private;
5063         struct intel_crtc_state *pipe_config = crtc->config;
5064
5065         if (!pipe_config->gmch_pfit.control)
5066                 return;
5067
5068         /*
5069          * The panel fitter should only be adjusted whilst the pipe is disabled,
5070          * according to register description and PRM.
5071          */
5072         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5073         assert_pipe_disabled(dev_priv, crtc->pipe);
5074
5075         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5076         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5077
5078         /* Border color in case we don't scale up to the full screen. Black by
5079          * default, change to something else for debugging. */
5080         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5081 }
5082
5083 static enum intel_display_power_domain port_to_power_domain(enum port port)
5084 {
5085         switch (port) {
5086         case PORT_A:
5087                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5088         case PORT_B:
5089                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5090         case PORT_C:
5091                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5092         case PORT_D:
5093                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5094         case PORT_E:
5095                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5096         default:
5097                 MISSING_CASE(port);
5098                 return POWER_DOMAIN_PORT_OTHER;
5099         }
5100 }
5101
5102 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5103 {
5104         switch (port) {
5105         case PORT_A:
5106                 return POWER_DOMAIN_AUX_A;
5107         case PORT_B:
5108                 return POWER_DOMAIN_AUX_B;
5109         case PORT_C:
5110                 return POWER_DOMAIN_AUX_C;
5111         case PORT_D:
5112                 return POWER_DOMAIN_AUX_D;
5113         case PORT_E:
5114                 /* FIXME: Check VBT for actual wiring of PORT E */
5115                 return POWER_DOMAIN_AUX_D;
5116         default:
5117                 MISSING_CASE(port);
5118                 return POWER_DOMAIN_AUX_A;
5119         }
5120 }
5121
5122 enum intel_display_power_domain
5123 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5124 {
5125         struct drm_device *dev = intel_encoder->base.dev;
5126         struct intel_digital_port *intel_dig_port;
5127
5128         switch (intel_encoder->type) {
5129         case INTEL_OUTPUT_UNKNOWN:
5130                 /* Only DDI platforms should ever use this output type */
5131                 WARN_ON_ONCE(!HAS_DDI(dev));
5132         case INTEL_OUTPUT_DISPLAYPORT:
5133         case INTEL_OUTPUT_HDMI:
5134         case INTEL_OUTPUT_EDP:
5135                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5136                 return port_to_power_domain(intel_dig_port->port);
5137         case INTEL_OUTPUT_DP_MST:
5138                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5139                 return port_to_power_domain(intel_dig_port->port);
5140         case INTEL_OUTPUT_ANALOG:
5141                 return POWER_DOMAIN_PORT_CRT;
5142         case INTEL_OUTPUT_DSI:
5143                 return POWER_DOMAIN_PORT_DSI;
5144         default:
5145                 return POWER_DOMAIN_PORT_OTHER;
5146         }
5147 }
5148
5149 enum intel_display_power_domain
5150 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5151 {
5152         struct drm_device *dev = intel_encoder->base.dev;
5153         struct intel_digital_port *intel_dig_port;
5154
5155         switch (intel_encoder->type) {
5156         case INTEL_OUTPUT_UNKNOWN:
5157         case INTEL_OUTPUT_HDMI:
5158                 /*
5159                  * Only DDI platforms should ever use these output types.
5160                  * We can get here after the HDMI detect code has already set
5161                  * the type of the shared encoder. Since we can't be sure
5162                  * what's the status of the given connectors, play safe and
5163                  * run the DP detection too.
5164                  */
5165                 WARN_ON_ONCE(!HAS_DDI(dev));
5166         case INTEL_OUTPUT_DISPLAYPORT:
5167         case INTEL_OUTPUT_EDP:
5168                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5169                 return port_to_aux_power_domain(intel_dig_port->port);
5170         case INTEL_OUTPUT_DP_MST:
5171                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5172                 return port_to_aux_power_domain(intel_dig_port->port);
5173         default:
5174                 MISSING_CASE(intel_encoder->type);
5175                 return POWER_DOMAIN_AUX_A;
5176         }
5177 }
5178
5179 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5180                                             struct intel_crtc_state *crtc_state)
5181 {
5182         struct drm_device *dev = crtc->dev;
5183         struct drm_encoder *encoder;
5184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5185         enum pipe pipe = intel_crtc->pipe;
5186         unsigned long mask;
5187         enum transcoder transcoder = crtc_state->cpu_transcoder;
5188
5189         if (!crtc_state->base.active)
5190                 return 0;
5191
5192         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5193         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5194         if (crtc_state->pch_pfit.enabled ||
5195             crtc_state->pch_pfit.force_thru)
5196                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5197
5198         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5199                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5200
5201                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5202         }
5203
5204         if (crtc_state->shared_dpll)
5205                 mask |= BIT(POWER_DOMAIN_PLLS);
5206
5207         return mask;
5208 }
5209
5210 static unsigned long
5211 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5212                                struct intel_crtc_state *crtc_state)
5213 {
5214         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216         enum intel_display_power_domain domain;
5217         unsigned long domains, new_domains, old_domains;
5218
5219         old_domains = intel_crtc->enabled_power_domains;
5220         intel_crtc->enabled_power_domains = new_domains =
5221                 get_crtc_power_domains(crtc, crtc_state);
5222
5223         domains = new_domains & ~old_domains;
5224
5225         for_each_power_domain(domain, domains)
5226                 intel_display_power_get(dev_priv, domain);
5227
5228         return old_domains & ~new_domains;
5229 }
5230
5231 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5232                                       unsigned long domains)
5233 {
5234         enum intel_display_power_domain domain;
5235
5236         for_each_power_domain(domain, domains)
5237                 intel_display_power_put(dev_priv, domain);
5238 }
5239
5240 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5241 {
5242         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5243
5244         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5245             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5246                 return max_cdclk_freq;
5247         else if (IS_CHERRYVIEW(dev_priv))
5248                 return max_cdclk_freq*95/100;
5249         else if (INTEL_INFO(dev_priv)->gen < 4)
5250                 return 2*max_cdclk_freq*90/100;
5251         else
5252                 return max_cdclk_freq*90/100;
5253 }
5254
5255 static void intel_update_max_cdclk(struct drm_device *dev)
5256 {
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258
5259         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5260                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5261
5262                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5263                         dev_priv->max_cdclk_freq = 675000;
5264                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5265                         dev_priv->max_cdclk_freq = 540000;
5266                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5267                         dev_priv->max_cdclk_freq = 450000;
5268                 else
5269                         dev_priv->max_cdclk_freq = 337500;
5270         } else if (IS_BROXTON(dev)) {
5271                 dev_priv->max_cdclk_freq = 624000;
5272         } else if (IS_BROADWELL(dev))  {
5273                 /*
5274                  * FIXME with extra cooling we can allow
5275                  * 540 MHz for ULX and 675 Mhz for ULT.
5276                  * How can we know if extra cooling is
5277                  * available? PCI ID, VTB, something else?
5278                  */
5279                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5280                         dev_priv->max_cdclk_freq = 450000;
5281                 else if (IS_BDW_ULX(dev))
5282                         dev_priv->max_cdclk_freq = 450000;
5283                 else if (IS_BDW_ULT(dev))
5284                         dev_priv->max_cdclk_freq = 540000;
5285                 else
5286                         dev_priv->max_cdclk_freq = 675000;
5287         } else if (IS_CHERRYVIEW(dev)) {
5288                 dev_priv->max_cdclk_freq = 320000;
5289         } else if (IS_VALLEYVIEW(dev)) {
5290                 dev_priv->max_cdclk_freq = 400000;
5291         } else {
5292                 /* otherwise assume cdclk is fixed */
5293                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5294         }
5295
5296         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5297
5298         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5299                          dev_priv->max_cdclk_freq);
5300
5301         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5302                          dev_priv->max_dotclk_freq);
5303 }
5304
5305 static void intel_update_cdclk(struct drm_device *dev)
5306 {
5307         struct drm_i915_private *dev_priv = dev->dev_private;
5308
5309         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5310         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5311                          dev_priv->cdclk_freq);
5312
5313         /*
5314          * Program the gmbus_freq based on the cdclk frequency.
5315          * BSpec erroneously claims we should aim for 4MHz, but
5316          * in fact 1MHz is the correct frequency.
5317          */
5318         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5319                 /*
5320                  * Program the gmbus_freq based on the cdclk frequency.
5321                  * BSpec erroneously claims we should aim for 4MHz, but
5322                  * in fact 1MHz is the correct frequency.
5323                  */
5324                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5325         }
5326
5327         if (dev_priv->max_cdclk_freq == 0)
5328                 intel_update_max_cdclk(dev);
5329 }
5330
5331 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
5332 {
5333         uint32_t divider;
5334         uint32_t ratio;
5335         uint32_t current_freq;
5336         int ret;
5337
5338         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5339         switch (frequency) {
5340         case 144000:
5341                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5342                 ratio = BXT_DE_PLL_RATIO(60);
5343                 break;
5344         case 288000:
5345                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5346                 ratio = BXT_DE_PLL_RATIO(60);
5347                 break;
5348         case 384000:
5349                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5350                 ratio = BXT_DE_PLL_RATIO(60);
5351                 break;
5352         case 576000:
5353                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5354                 ratio = BXT_DE_PLL_RATIO(60);
5355                 break;
5356         case 624000:
5357                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5358                 ratio = BXT_DE_PLL_RATIO(65);
5359                 break;
5360         case 19200:
5361                 /*
5362                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5363                  * to suppress GCC warning.
5364                  */
5365                 ratio = 0;
5366                 divider = 0;
5367                 break;
5368         default:
5369                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5370
5371                 return;
5372         }
5373
5374         mutex_lock(&dev_priv->rps.hw_lock);
5375         /* Inform power controller of upcoming frequency change */
5376         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5377                                       0x80000000);
5378         mutex_unlock(&dev_priv->rps.hw_lock);
5379
5380         if (ret) {
5381                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5382                           ret, frequency);
5383                 return;
5384         }
5385
5386         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5387         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5388         current_freq = current_freq * 500 + 1000;
5389
5390         /*
5391          * DE PLL has to be disabled when
5392          * - setting to 19.2MHz (bypass, PLL isn't used)
5393          * - before setting to 624MHz (PLL needs toggling)
5394          * - before setting to any frequency from 624MHz (PLL needs toggling)
5395          */
5396         if (frequency == 19200 || frequency == 624000 ||
5397             current_freq == 624000) {
5398                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5399                 /* Timeout 200us */
5400                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5401                              1))
5402                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5403         }
5404
5405         if (frequency != 19200) {
5406                 uint32_t val;
5407
5408                 val = I915_READ(BXT_DE_PLL_CTL);
5409                 val &= ~BXT_DE_PLL_RATIO_MASK;
5410                 val |= ratio;
5411                 I915_WRITE(BXT_DE_PLL_CTL, val);
5412
5413                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5414                 /* Timeout 200us */
5415                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5416                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5417
5418                 val = I915_READ(CDCLK_CTL);
5419                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5420                 val |= divider;
5421                 /*
5422                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5423                  * enable otherwise.
5424                  */
5425                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5426                 if (frequency >= 500000)
5427                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5428
5429                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5430                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5431                 val |= (frequency - 1000) / 500;
5432                 I915_WRITE(CDCLK_CTL, val);
5433         }
5434
5435         mutex_lock(&dev_priv->rps.hw_lock);
5436         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5437                                       DIV_ROUND_UP(frequency, 25000));
5438         mutex_unlock(&dev_priv->rps.hw_lock);
5439
5440         if (ret) {
5441                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5442                           ret, frequency);
5443                 return;
5444         }
5445
5446         intel_update_cdclk(dev_priv->dev);
5447 }
5448
5449 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5450 {
5451         if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5452                 return false;
5453
5454         /* TODO: Check for a valid CDCLK rate */
5455
5456         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5457                 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5458
5459                 return false;
5460         }
5461
5462         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5463                 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5464
5465                 return false;
5466         }
5467
5468         return true;
5469 }
5470
5471 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5472 {
5473         return broxton_cdclk_is_enabled(dev_priv);
5474 }
5475
5476 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5477 {
5478         /* check if cd clock is enabled */
5479         if (broxton_cdclk_is_enabled(dev_priv)) {
5480                 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5481                 return;
5482         }
5483
5484         DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5485
5486         /*
5487          * FIXME:
5488          * - The initial CDCLK needs to be read from VBT.
5489          *   Need to make this change after VBT has changes for BXT.
5490          * - check if setting the max (or any) cdclk freq is really necessary
5491          *   here, it belongs to modeset time
5492          */
5493         broxton_set_cdclk(dev_priv, 624000);
5494
5495         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5496         POSTING_READ(DBUF_CTL);
5497
5498         udelay(10);
5499
5500         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5501                 DRM_ERROR("DBuf power enable timeout!\n");
5502 }
5503
5504 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5505 {
5506         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5507         POSTING_READ(DBUF_CTL);
5508
5509         udelay(10);
5510
5511         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5512                 DRM_ERROR("DBuf power disable timeout!\n");
5513
5514         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5515         broxton_set_cdclk(dev_priv, 19200);
5516 }
5517
5518 static const struct skl_cdclk_entry {
5519         unsigned int freq;
5520         unsigned int vco;
5521 } skl_cdclk_frequencies[] = {
5522         { .freq = 308570, .vco = 8640 },
5523         { .freq = 337500, .vco = 8100 },
5524         { .freq = 432000, .vco = 8640 },
5525         { .freq = 450000, .vco = 8100 },
5526         { .freq = 540000, .vco = 8100 },
5527         { .freq = 617140, .vco = 8640 },
5528         { .freq = 675000, .vco = 8100 },
5529 };
5530
5531 static unsigned int skl_cdclk_decimal(unsigned int freq)
5532 {
5533         return (freq - 1000) / 500;
5534 }
5535
5536 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5537 {
5538         unsigned int i;
5539
5540         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5541                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5542
5543                 if (e->freq == freq)
5544                         return e->vco;
5545         }
5546
5547         return 8100;
5548 }
5549
5550 static void
5551 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5552 {
5553         unsigned int min_freq;
5554         u32 val;
5555
5556         /* select the minimum CDCLK before enabling DPLL 0 */
5557         val = I915_READ(CDCLK_CTL);
5558         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5559         val |= CDCLK_FREQ_337_308;
5560
5561         if (required_vco == 8640)
5562                 min_freq = 308570;
5563         else
5564                 min_freq = 337500;
5565
5566         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5567
5568         I915_WRITE(CDCLK_CTL, val);
5569         POSTING_READ(CDCLK_CTL);
5570
5571         /*
5572          * We always enable DPLL0 with the lowest link rate possible, but still
5573          * taking into account the VCO required to operate the eDP panel at the
5574          * desired frequency. The usual DP link rates operate with a VCO of
5575          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5576          * The modeset code is responsible for the selection of the exact link
5577          * rate later on, with the constraint of choosing a frequency that
5578          * works with required_vco.
5579          */
5580         val = I915_READ(DPLL_CTRL1);
5581
5582         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5583                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5584         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5585         if (required_vco == 8640)
5586                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5587                                             SKL_DPLL0);
5588         else
5589                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5590                                             SKL_DPLL0);
5591
5592         I915_WRITE(DPLL_CTRL1, val);
5593         POSTING_READ(DPLL_CTRL1);
5594
5595         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5596
5597         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5598                 DRM_ERROR("DPLL0 not locked\n");
5599 }
5600
5601 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5602 {
5603         int ret;
5604         u32 val;
5605
5606         /* inform PCU we want to change CDCLK */
5607         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5608         mutex_lock(&dev_priv->rps.hw_lock);
5609         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5610         mutex_unlock(&dev_priv->rps.hw_lock);
5611
5612         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5613 }
5614
5615 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5616 {
5617         unsigned int i;
5618
5619         for (i = 0; i < 15; i++) {
5620                 if (skl_cdclk_pcu_ready(dev_priv))
5621                         return true;
5622                 udelay(10);
5623         }
5624
5625         return false;
5626 }
5627
5628 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5629 {
5630         struct drm_device *dev = dev_priv->dev;
5631         u32 freq_select, pcu_ack;
5632
5633         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5634
5635         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5636                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5637                 return;
5638         }
5639
5640         /* set CDCLK_CTL */
5641         switch(freq) {
5642         case 450000:
5643         case 432000:
5644                 freq_select = CDCLK_FREQ_450_432;
5645                 pcu_ack = 1;
5646                 break;
5647         case 540000:
5648                 freq_select = CDCLK_FREQ_540;
5649                 pcu_ack = 2;
5650                 break;
5651         case 308570:
5652         case 337500:
5653         default:
5654                 freq_select = CDCLK_FREQ_337_308;
5655                 pcu_ack = 0;
5656                 break;
5657         case 617140:
5658         case 675000:
5659                 freq_select = CDCLK_FREQ_675_617;
5660                 pcu_ack = 3;
5661                 break;
5662         }
5663
5664         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5665         POSTING_READ(CDCLK_CTL);
5666
5667         /* inform PCU of the change */
5668         mutex_lock(&dev_priv->rps.hw_lock);
5669         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5670         mutex_unlock(&dev_priv->rps.hw_lock);
5671
5672         intel_update_cdclk(dev);
5673 }
5674
5675 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5676 {
5677         /* disable DBUF power */
5678         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5679         POSTING_READ(DBUF_CTL);
5680
5681         udelay(10);
5682
5683         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5684                 DRM_ERROR("DBuf power disable timeout\n");
5685
5686         /* disable DPLL0 */
5687         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5688         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5689                 DRM_ERROR("Couldn't disable DPLL0\n");
5690 }
5691
5692 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5693 {
5694         unsigned int required_vco;
5695
5696         /* DPLL0 not enabled (happens on early BIOS versions) */
5697         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5698                 /* enable DPLL0 */
5699                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5700                 skl_dpll0_enable(dev_priv, required_vco);
5701         }
5702
5703         /* set CDCLK to the frequency the BIOS chose */
5704         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5705
5706         /* enable DBUF power */
5707         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5708         POSTING_READ(DBUF_CTL);
5709
5710         udelay(10);
5711
5712         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5713                 DRM_ERROR("DBuf power enable timeout\n");
5714 }
5715
5716 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5717 {
5718         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5719         uint32_t cdctl = I915_READ(CDCLK_CTL);
5720         int freq = dev_priv->skl_boot_cdclk;
5721
5722         /*
5723          * check if the pre-os intialized the display
5724          * There is SWF18 scratchpad register defined which is set by the
5725          * pre-os which can be used by the OS drivers to check the status
5726          */
5727         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5728                 goto sanitize;
5729
5730         /* Is PLL enabled and locked ? */
5731         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5732                 goto sanitize;
5733
5734         /* DPLL okay; verify the cdclock
5735          *
5736          * Noticed in some instances that the freq selection is correct but
5737          * decimal part is programmed wrong from BIOS where pre-os does not
5738          * enable display. Verify the same as well.
5739          */
5740         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5741                 /* All well; nothing to sanitize */
5742                 return false;
5743 sanitize:
5744         /*
5745          * As of now initialize with max cdclk till
5746          * we get dynamic cdclk support
5747          * */
5748         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5749         skl_init_cdclk(dev_priv);
5750
5751         /* we did have to sanitize */
5752         return true;
5753 }
5754
5755 /* Adjust CDclk dividers to allow high res or save power if possible */
5756 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5757 {
5758         struct drm_i915_private *dev_priv = dev->dev_private;
5759         u32 val, cmd;
5760
5761         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5762                                         != dev_priv->cdclk_freq);
5763
5764         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5765                 cmd = 2;
5766         else if (cdclk == 266667)
5767                 cmd = 1;
5768         else
5769                 cmd = 0;
5770
5771         mutex_lock(&dev_priv->rps.hw_lock);
5772         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5773         val &= ~DSPFREQGUAR_MASK;
5774         val |= (cmd << DSPFREQGUAR_SHIFT);
5775         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5776         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5777                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5778                      50)) {
5779                 DRM_ERROR("timed out waiting for CDclk change\n");
5780         }
5781         mutex_unlock(&dev_priv->rps.hw_lock);
5782
5783         mutex_lock(&dev_priv->sb_lock);
5784
5785         if (cdclk == 400000) {
5786                 u32 divider;
5787
5788                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5789
5790                 /* adjust cdclk divider */
5791                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5792                 val &= ~CCK_FREQUENCY_VALUES;
5793                 val |= divider;
5794                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5795
5796                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5797                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5798                              50))
5799                         DRM_ERROR("timed out waiting for CDclk change\n");
5800         }
5801
5802         /* adjust self-refresh exit latency value */
5803         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5804         val &= ~0x7f;
5805
5806         /*
5807          * For high bandwidth configs, we set a higher latency in the bunit
5808          * so that the core display fetch happens in time to avoid underruns.
5809          */
5810         if (cdclk == 400000)
5811                 val |= 4500 / 250; /* 4.5 usec */
5812         else
5813                 val |= 3000 / 250; /* 3.0 usec */
5814         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5815
5816         mutex_unlock(&dev_priv->sb_lock);
5817
5818         intel_update_cdclk(dev);
5819 }
5820
5821 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5822 {
5823         struct drm_i915_private *dev_priv = dev->dev_private;
5824         u32 val, cmd;
5825
5826         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5827                                                 != dev_priv->cdclk_freq);
5828
5829         switch (cdclk) {
5830         case 333333:
5831         case 320000:
5832         case 266667:
5833         case 200000:
5834                 break;
5835         default:
5836                 MISSING_CASE(cdclk);
5837                 return;
5838         }
5839
5840         /*
5841          * Specs are full of misinformation, but testing on actual
5842          * hardware has shown that we just need to write the desired
5843          * CCK divider into the Punit register.
5844          */
5845         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5846
5847         mutex_lock(&dev_priv->rps.hw_lock);
5848         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5849         val &= ~DSPFREQGUAR_MASK_CHV;
5850         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5851         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5852         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5853                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5854                      50)) {
5855                 DRM_ERROR("timed out waiting for CDclk change\n");
5856         }
5857         mutex_unlock(&dev_priv->rps.hw_lock);
5858
5859         intel_update_cdclk(dev);
5860 }
5861
5862 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5863                                  int max_pixclk)
5864 {
5865         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5866         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5867
5868         /*
5869          * Really only a few cases to deal with, as only 4 CDclks are supported:
5870          *   200MHz
5871          *   267MHz
5872          *   320/333MHz (depends on HPLL freq)
5873          *   400MHz (VLV only)
5874          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5875          * of the lower bin and adjust if needed.
5876          *
5877          * We seem to get an unstable or solid color picture at 200MHz.
5878          * Not sure what's wrong. For now use 200MHz only when all pipes
5879          * are off.
5880          */
5881         if (!IS_CHERRYVIEW(dev_priv) &&
5882             max_pixclk > freq_320*limit/100)
5883                 return 400000;
5884         else if (max_pixclk > 266667*limit/100)
5885                 return freq_320;
5886         else if (max_pixclk > 0)
5887                 return 266667;
5888         else
5889                 return 200000;
5890 }
5891
5892 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5893                               int max_pixclk)
5894 {
5895         /*
5896          * FIXME:
5897          * - remove the guardband, it's not needed on BXT
5898          * - set 19.2MHz bypass frequency if there are no active pipes
5899          */
5900         if (max_pixclk > 576000*9/10)
5901                 return 624000;
5902         else if (max_pixclk > 384000*9/10)
5903                 return 576000;
5904         else if (max_pixclk > 288000*9/10)
5905                 return 384000;
5906         else if (max_pixclk > 144000*9/10)
5907                 return 288000;
5908         else
5909                 return 144000;
5910 }
5911
5912 /* Compute the max pixel clock for new configuration. */
5913 static int intel_mode_max_pixclk(struct drm_device *dev,
5914                                  struct drm_atomic_state *state)
5915 {
5916         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5917         struct drm_i915_private *dev_priv = dev->dev_private;
5918         struct drm_crtc *crtc;
5919         struct drm_crtc_state *crtc_state;
5920         unsigned max_pixclk = 0, i;
5921         enum pipe pipe;
5922
5923         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5924                sizeof(intel_state->min_pixclk));
5925
5926         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5927                 int pixclk = 0;
5928
5929                 if (crtc_state->enable)
5930                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5931
5932                 intel_state->min_pixclk[i] = pixclk;
5933         }
5934
5935         for_each_pipe(dev_priv, pipe)
5936                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5937
5938         return max_pixclk;
5939 }
5940
5941 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5942 {
5943         struct drm_device *dev = state->dev;
5944         struct drm_i915_private *dev_priv = dev->dev_private;
5945         int max_pixclk = intel_mode_max_pixclk(dev, state);
5946         struct intel_atomic_state *intel_state =
5947                 to_intel_atomic_state(state);
5948
5949         if (max_pixclk < 0)
5950                 return max_pixclk;
5951
5952         intel_state->cdclk = intel_state->dev_cdclk =
5953                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5954
5955         if (!intel_state->active_crtcs)
5956                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5957
5958         return 0;
5959 }
5960
5961 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5962 {
5963         struct drm_device *dev = state->dev;
5964         struct drm_i915_private *dev_priv = dev->dev_private;
5965         int max_pixclk = intel_mode_max_pixclk(dev, state);
5966         struct intel_atomic_state *intel_state =
5967                 to_intel_atomic_state(state);
5968
5969         if (max_pixclk < 0)
5970                 return max_pixclk;
5971
5972         intel_state->cdclk = intel_state->dev_cdclk =
5973                 broxton_calc_cdclk(dev_priv, max_pixclk);
5974
5975         if (!intel_state->active_crtcs)
5976                 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5977
5978         return 0;
5979 }
5980
5981 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5982 {
5983         unsigned int credits, default_credits;
5984
5985         if (IS_CHERRYVIEW(dev_priv))
5986                 default_credits = PFI_CREDIT(12);
5987         else
5988                 default_credits = PFI_CREDIT(8);
5989
5990         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5991                 /* CHV suggested value is 31 or 63 */
5992                 if (IS_CHERRYVIEW(dev_priv))
5993                         credits = PFI_CREDIT_63;
5994                 else
5995                         credits = PFI_CREDIT(15);
5996         } else {
5997                 credits = default_credits;
5998         }
5999
6000         /*
6001          * WA - write default credits before re-programming
6002          * FIXME: should we also set the resend bit here?
6003          */
6004         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6005                    default_credits);
6006
6007         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6008                    credits | PFI_CREDIT_RESEND);
6009
6010         /*
6011          * FIXME is this guaranteed to clear
6012          * immediately or should we poll for it?
6013          */
6014         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6015 }
6016
6017 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6018 {
6019         struct drm_device *dev = old_state->dev;
6020         struct drm_i915_private *dev_priv = dev->dev_private;
6021         struct intel_atomic_state *old_intel_state =
6022                 to_intel_atomic_state(old_state);
6023         unsigned req_cdclk = old_intel_state->dev_cdclk;
6024
6025         /*
6026          * FIXME: We can end up here with all power domains off, yet
6027          * with a CDCLK frequency other than the minimum. To account
6028          * for this take the PIPE-A power domain, which covers the HW
6029          * blocks needed for the following programming. This can be
6030          * removed once it's guaranteed that we get here either with
6031          * the minimum CDCLK set, or the required power domains
6032          * enabled.
6033          */
6034         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6035
6036         if (IS_CHERRYVIEW(dev))
6037                 cherryview_set_cdclk(dev, req_cdclk);
6038         else
6039                 valleyview_set_cdclk(dev, req_cdclk);
6040
6041         vlv_program_pfi_credits(dev_priv);
6042
6043         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6044 }
6045
6046 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6047 {
6048         struct drm_device *dev = crtc->dev;
6049         struct drm_i915_private *dev_priv = to_i915(dev);
6050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6051         struct intel_encoder *encoder;
6052         struct intel_crtc_state *pipe_config =
6053                 to_intel_crtc_state(crtc->state);
6054         int pipe = intel_crtc->pipe;
6055
6056         if (WARN_ON(intel_crtc->active))
6057                 return;
6058
6059         if (intel_crtc->config->has_dp_encoder)
6060                 intel_dp_set_m_n(intel_crtc, M1_N1);
6061
6062         intel_set_pipe_timings(intel_crtc);
6063         intel_set_pipe_src_size(intel_crtc);
6064
6065         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6066                 struct drm_i915_private *dev_priv = dev->dev_private;
6067
6068                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6069                 I915_WRITE(CHV_CANVAS(pipe), 0);
6070         }
6071
6072         i9xx_set_pipeconf(intel_crtc);
6073
6074         intel_crtc->active = true;
6075
6076         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6077
6078         for_each_encoder_on_crtc(dev, crtc, encoder)
6079                 if (encoder->pre_pll_enable)
6080                         encoder->pre_pll_enable(encoder);
6081
6082         if (!intel_crtc->config->has_dsi_encoder) {
6083                 if (IS_CHERRYVIEW(dev)) {
6084                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6085                         chv_enable_pll(intel_crtc, intel_crtc->config);
6086                 } else {
6087                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6088                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6089                 }
6090         }
6091
6092         for_each_encoder_on_crtc(dev, crtc, encoder)
6093                 if (encoder->pre_enable)
6094                         encoder->pre_enable(encoder);
6095
6096         i9xx_pfit_enable(intel_crtc);
6097
6098         intel_color_load_luts(&pipe_config->base);
6099
6100         intel_update_watermarks(crtc);
6101         intel_enable_pipe(intel_crtc);
6102
6103         assert_vblank_disabled(crtc);
6104         drm_crtc_vblank_on(crtc);
6105
6106         for_each_encoder_on_crtc(dev, crtc, encoder)
6107                 encoder->enable(encoder);
6108 }
6109
6110 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6111 {
6112         struct drm_device *dev = crtc->base.dev;
6113         struct drm_i915_private *dev_priv = dev->dev_private;
6114
6115         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6116         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6117 }
6118
6119 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6120 {
6121         struct drm_device *dev = crtc->dev;
6122         struct drm_i915_private *dev_priv = to_i915(dev);
6123         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6124         struct intel_encoder *encoder;
6125         struct intel_crtc_state *pipe_config =
6126                 to_intel_crtc_state(crtc->state);
6127         int pipe = intel_crtc->pipe;
6128
6129         if (WARN_ON(intel_crtc->active))
6130                 return;
6131
6132         i9xx_set_pll_dividers(intel_crtc);
6133
6134         if (intel_crtc->config->has_dp_encoder)
6135                 intel_dp_set_m_n(intel_crtc, M1_N1);
6136
6137         intel_set_pipe_timings(intel_crtc);
6138         intel_set_pipe_src_size(intel_crtc);
6139
6140         i9xx_set_pipeconf(intel_crtc);
6141
6142         intel_crtc->active = true;
6143
6144         if (!IS_GEN2(dev))
6145                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6146
6147         for_each_encoder_on_crtc(dev, crtc, encoder)
6148                 if (encoder->pre_enable)
6149                         encoder->pre_enable(encoder);
6150
6151         i9xx_enable_pll(intel_crtc);
6152
6153         i9xx_pfit_enable(intel_crtc);
6154
6155         intel_color_load_luts(&pipe_config->base);
6156
6157         intel_update_watermarks(crtc);
6158         intel_enable_pipe(intel_crtc);
6159
6160         assert_vblank_disabled(crtc);
6161         drm_crtc_vblank_on(crtc);
6162
6163         for_each_encoder_on_crtc(dev, crtc, encoder)
6164                 encoder->enable(encoder);
6165 }
6166
6167 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6168 {
6169         struct drm_device *dev = crtc->base.dev;
6170         struct drm_i915_private *dev_priv = dev->dev_private;
6171
6172         if (!crtc->config->gmch_pfit.control)
6173                 return;
6174
6175         assert_pipe_disabled(dev_priv, crtc->pipe);
6176
6177         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6178                          I915_READ(PFIT_CONTROL));
6179         I915_WRITE(PFIT_CONTROL, 0);
6180 }
6181
6182 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6183 {
6184         struct drm_device *dev = crtc->dev;
6185         struct drm_i915_private *dev_priv = dev->dev_private;
6186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187         struct intel_encoder *encoder;
6188         int pipe = intel_crtc->pipe;
6189
6190         /*
6191          * On gen2 planes are double buffered but the pipe isn't, so we must
6192          * wait for planes to fully turn off before disabling the pipe.
6193          */
6194         if (IS_GEN2(dev))
6195                 intel_wait_for_vblank(dev, pipe);
6196
6197         for_each_encoder_on_crtc(dev, crtc, encoder)
6198                 encoder->disable(encoder);
6199
6200         drm_crtc_vblank_off(crtc);
6201         assert_vblank_disabled(crtc);
6202
6203         intel_disable_pipe(intel_crtc);
6204
6205         i9xx_pfit_disable(intel_crtc);
6206
6207         for_each_encoder_on_crtc(dev, crtc, encoder)
6208                 if (encoder->post_disable)
6209                         encoder->post_disable(encoder);
6210
6211         if (!intel_crtc->config->has_dsi_encoder) {
6212                 if (IS_CHERRYVIEW(dev))
6213                         chv_disable_pll(dev_priv, pipe);
6214                 else if (IS_VALLEYVIEW(dev))
6215                         vlv_disable_pll(dev_priv, pipe);
6216                 else
6217                         i9xx_disable_pll(intel_crtc);
6218         }
6219
6220         for_each_encoder_on_crtc(dev, crtc, encoder)
6221                 if (encoder->post_pll_disable)
6222                         encoder->post_pll_disable(encoder);
6223
6224         if (!IS_GEN2(dev))
6225                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6226 }
6227
6228 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6229 {
6230         struct intel_encoder *encoder;
6231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6232         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6233         enum intel_display_power_domain domain;
6234         unsigned long domains;
6235
6236         if (!intel_crtc->active)
6237                 return;
6238
6239         if (to_intel_plane_state(crtc->primary->state)->visible) {
6240                 WARN_ON(intel_crtc->unpin_work);
6241
6242                 intel_pre_disable_primary_noatomic(crtc);
6243
6244                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6245                 to_intel_plane_state(crtc->primary->state)->visible = false;
6246         }
6247
6248         dev_priv->display.crtc_disable(crtc);
6249
6250         DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6251                       crtc->base.id);
6252
6253         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6254         crtc->state->active = false;
6255         intel_crtc->active = false;
6256         crtc->enabled = false;
6257         crtc->state->connector_mask = 0;
6258         crtc->state->encoder_mask = 0;
6259
6260         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6261                 encoder->base.crtc = NULL;
6262
6263         intel_fbc_disable(intel_crtc);
6264         intel_update_watermarks(crtc);
6265         intel_disable_shared_dpll(intel_crtc);
6266
6267         domains = intel_crtc->enabled_power_domains;
6268         for_each_power_domain(domain, domains)
6269                 intel_display_power_put(dev_priv, domain);
6270         intel_crtc->enabled_power_domains = 0;
6271
6272         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6273         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6274 }
6275
6276 /*
6277  * turn all crtc's off, but do not adjust state
6278  * This has to be paired with a call to intel_modeset_setup_hw_state.
6279  */
6280 int intel_display_suspend(struct drm_device *dev)
6281 {
6282         struct drm_i915_private *dev_priv = to_i915(dev);
6283         struct drm_atomic_state *state;
6284         int ret;
6285
6286         state = drm_atomic_helper_suspend(dev);
6287         ret = PTR_ERR_OR_ZERO(state);
6288         if (ret)
6289                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6290         else
6291                 dev_priv->modeset_restore_state = state;
6292         return ret;
6293 }
6294
6295 void intel_encoder_destroy(struct drm_encoder *encoder)
6296 {
6297         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6298
6299         drm_encoder_cleanup(encoder);
6300         kfree(intel_encoder);
6301 }
6302
6303 /* Cross check the actual hw state with our own modeset state tracking (and it's
6304  * internal consistency). */
6305 static void intel_connector_verify_state(struct intel_connector *connector)
6306 {
6307         struct drm_crtc *crtc = connector->base.state->crtc;
6308
6309         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6310                       connector->base.base.id,
6311                       connector->base.name);
6312
6313         if (connector->get_hw_state(connector)) {
6314                 struct intel_encoder *encoder = connector->encoder;
6315                 struct drm_connector_state *conn_state = connector->base.state;
6316
6317                 I915_STATE_WARN(!crtc,
6318                          "connector enabled without attached crtc\n");
6319
6320                 if (!crtc)
6321                         return;
6322
6323                 I915_STATE_WARN(!crtc->state->active,
6324                       "connector is active, but attached crtc isn't\n");
6325
6326                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6327                         return;
6328
6329                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6330                         "atomic encoder doesn't match attached encoder\n");
6331
6332                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6333                         "attached encoder crtc differs from connector crtc\n");
6334         } else {
6335                 I915_STATE_WARN(crtc && crtc->state->active,
6336                         "attached crtc is active, but connector isn't\n");
6337                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6338                         "best encoder set without crtc!\n");
6339         }
6340 }
6341
6342 int intel_connector_init(struct intel_connector *connector)
6343 {
6344         drm_atomic_helper_connector_reset(&connector->base);
6345
6346         if (!connector->base.state)
6347                 return -ENOMEM;
6348
6349         return 0;
6350 }
6351
6352 struct intel_connector *intel_connector_alloc(void)
6353 {
6354         struct intel_connector *connector;
6355
6356         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6357         if (!connector)
6358                 return NULL;
6359
6360         if (intel_connector_init(connector) < 0) {
6361                 kfree(connector);
6362                 return NULL;
6363         }
6364
6365         return connector;
6366 }
6367
6368 /* Simple connector->get_hw_state implementation for encoders that support only
6369  * one connector and no cloning and hence the encoder state determines the state
6370  * of the connector. */
6371 bool intel_connector_get_hw_state(struct intel_connector *connector)
6372 {
6373         enum pipe pipe = 0;
6374         struct intel_encoder *encoder = connector->encoder;
6375
6376         return encoder->get_hw_state(encoder, &pipe);
6377 }
6378
6379 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6380 {
6381         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6382                 return crtc_state->fdi_lanes;
6383
6384         return 0;
6385 }
6386
6387 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6388                                      struct intel_crtc_state *pipe_config)
6389 {
6390         struct drm_atomic_state *state = pipe_config->base.state;
6391         struct intel_crtc *other_crtc;
6392         struct intel_crtc_state *other_crtc_state;
6393
6394         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6395                       pipe_name(pipe), pipe_config->fdi_lanes);
6396         if (pipe_config->fdi_lanes > 4) {
6397                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6398                               pipe_name(pipe), pipe_config->fdi_lanes);
6399                 return -EINVAL;
6400         }
6401
6402         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6403                 if (pipe_config->fdi_lanes > 2) {
6404                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6405                                       pipe_config->fdi_lanes);
6406                         return -EINVAL;
6407                 } else {
6408                         return 0;
6409                 }
6410         }
6411
6412         if (INTEL_INFO(dev)->num_pipes == 2)
6413                 return 0;
6414
6415         /* Ivybridge 3 pipe is really complicated */
6416         switch (pipe) {
6417         case PIPE_A:
6418                 return 0;
6419         case PIPE_B:
6420                 if (pipe_config->fdi_lanes <= 2)
6421                         return 0;
6422
6423                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6424                 other_crtc_state =
6425                         intel_atomic_get_crtc_state(state, other_crtc);
6426                 if (IS_ERR(other_crtc_state))
6427                         return PTR_ERR(other_crtc_state);
6428
6429                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6430                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6431                                       pipe_name(pipe), pipe_config->fdi_lanes);
6432                         return -EINVAL;
6433                 }
6434                 return 0;
6435         case PIPE_C:
6436                 if (pipe_config->fdi_lanes > 2) {
6437                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6438                                       pipe_name(pipe), pipe_config->fdi_lanes);
6439                         return -EINVAL;
6440                 }
6441
6442                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6443                 other_crtc_state =
6444                         intel_atomic_get_crtc_state(state, other_crtc);
6445                 if (IS_ERR(other_crtc_state))
6446                         return PTR_ERR(other_crtc_state);
6447
6448                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6449                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6450                         return -EINVAL;
6451                 }
6452                 return 0;
6453         default:
6454                 BUG();
6455         }
6456 }
6457
6458 #define RETRY 1
6459 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6460                                        struct intel_crtc_state *pipe_config)
6461 {
6462         struct drm_device *dev = intel_crtc->base.dev;
6463         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6464         int lane, link_bw, fdi_dotclock, ret;
6465         bool needs_recompute = false;
6466
6467 retry:
6468         /* FDI is a binary signal running at ~2.7GHz, encoding
6469          * each output octet as 10 bits. The actual frequency
6470          * is stored as a divider into a 100MHz clock, and the
6471          * mode pixel clock is stored in units of 1KHz.
6472          * Hence the bw of each lane in terms of the mode signal
6473          * is:
6474          */
6475         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6476
6477         fdi_dotclock = adjusted_mode->crtc_clock;
6478
6479         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6480                                            pipe_config->pipe_bpp);
6481
6482         pipe_config->fdi_lanes = lane;
6483
6484         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6485                                link_bw, &pipe_config->fdi_m_n);
6486
6487         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6488         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6489                 pipe_config->pipe_bpp -= 2*3;
6490                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6491                               pipe_config->pipe_bpp);
6492                 needs_recompute = true;
6493                 pipe_config->bw_constrained = true;
6494
6495                 goto retry;
6496         }
6497
6498         if (needs_recompute)
6499                 return RETRY;
6500
6501         return ret;
6502 }
6503
6504 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6505                                      struct intel_crtc_state *pipe_config)
6506 {
6507         if (pipe_config->pipe_bpp > 24)
6508                 return false;
6509
6510         /* HSW can handle pixel rate up to cdclk? */
6511         if (IS_HASWELL(dev_priv))
6512                 return true;
6513
6514         /*
6515          * We compare against max which means we must take
6516          * the increased cdclk requirement into account when
6517          * calculating the new cdclk.
6518          *
6519          * Should measure whether using a lower cdclk w/o IPS
6520          */
6521         return ilk_pipe_pixel_rate(pipe_config) <=
6522                 dev_priv->max_cdclk_freq * 95 / 100;
6523 }
6524
6525 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6526                                    struct intel_crtc_state *pipe_config)
6527 {
6528         struct drm_device *dev = crtc->base.dev;
6529         struct drm_i915_private *dev_priv = dev->dev_private;
6530
6531         pipe_config->ips_enabled = i915.enable_ips &&
6532                 hsw_crtc_supports_ips(crtc) &&
6533                 pipe_config_supports_ips(dev_priv, pipe_config);
6534 }
6535
6536 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6537 {
6538         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6539
6540         /* GDG double wide on either pipe, otherwise pipe A only */
6541         return INTEL_INFO(dev_priv)->gen < 4 &&
6542                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6543 }
6544
6545 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6546                                      struct intel_crtc_state *pipe_config)
6547 {
6548         struct drm_device *dev = crtc->base.dev;
6549         struct drm_i915_private *dev_priv = dev->dev_private;
6550         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6551
6552         /* FIXME should check pixel clock limits on all platforms */
6553         if (INTEL_INFO(dev)->gen < 4) {
6554                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6555
6556                 /*
6557                  * Enable double wide mode when the dot clock
6558                  * is > 90% of the (display) core speed.
6559                  */
6560                 if (intel_crtc_supports_double_wide(crtc) &&
6561                     adjusted_mode->crtc_clock > clock_limit) {
6562                         clock_limit *= 2;
6563                         pipe_config->double_wide = true;
6564                 }
6565
6566                 if (adjusted_mode->crtc_clock > clock_limit) {
6567                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6568                                       adjusted_mode->crtc_clock, clock_limit,
6569                                       yesno(pipe_config->double_wide));
6570                         return -EINVAL;
6571                 }
6572         }
6573
6574         /*
6575          * Pipe horizontal size must be even in:
6576          * - DVO ganged mode
6577          * - LVDS dual channel mode
6578          * - Double wide pipe
6579          */
6580         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6581              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6582                 pipe_config->pipe_src_w &= ~1;
6583
6584         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6585          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6586          */
6587         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6588                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6589                 return -EINVAL;
6590
6591         if (HAS_IPS(dev))
6592                 hsw_compute_ips_config(crtc, pipe_config);
6593
6594         if (pipe_config->has_pch_encoder)
6595                 return ironlake_fdi_compute_config(crtc, pipe_config);
6596
6597         return 0;
6598 }
6599
6600 static int skylake_get_display_clock_speed(struct drm_device *dev)
6601 {
6602         struct drm_i915_private *dev_priv = to_i915(dev);
6603         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6604         uint32_t cdctl = I915_READ(CDCLK_CTL);
6605         uint32_t linkrate;
6606
6607         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6608                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6609
6610         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6611                 return 540000;
6612
6613         linkrate = (I915_READ(DPLL_CTRL1) &
6614                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6615
6616         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6617             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6618                 /* vco 8640 */
6619                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6620                 case CDCLK_FREQ_450_432:
6621                         return 432000;
6622                 case CDCLK_FREQ_337_308:
6623                         return 308570;
6624                 case CDCLK_FREQ_675_617:
6625                         return 617140;
6626                 default:
6627                         WARN(1, "Unknown cd freq selection\n");
6628                 }
6629         } else {
6630                 /* vco 8100 */
6631                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6632                 case CDCLK_FREQ_450_432:
6633                         return 450000;
6634                 case CDCLK_FREQ_337_308:
6635                         return 337500;
6636                 case CDCLK_FREQ_675_617:
6637                         return 675000;
6638                 default:
6639                         WARN(1, "Unknown cd freq selection\n");
6640                 }
6641         }
6642
6643         /* error case, do as if DPLL0 isn't enabled */
6644         return 24000;
6645 }
6646
6647 static int broxton_get_display_clock_speed(struct drm_device *dev)
6648 {
6649         struct drm_i915_private *dev_priv = to_i915(dev);
6650         uint32_t cdctl = I915_READ(CDCLK_CTL);
6651         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6652         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6653         int cdclk;
6654
6655         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6656                 return 19200;
6657
6658         cdclk = 19200 * pll_ratio / 2;
6659
6660         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6661         case BXT_CDCLK_CD2X_DIV_SEL_1:
6662                 return cdclk;  /* 576MHz or 624MHz */
6663         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6664                 return cdclk * 2 / 3; /* 384MHz */
6665         case BXT_CDCLK_CD2X_DIV_SEL_2:
6666                 return cdclk / 2; /* 288MHz */
6667         case BXT_CDCLK_CD2X_DIV_SEL_4:
6668                 return cdclk / 4; /* 144MHz */
6669         }
6670
6671         /* error case, do as if DE PLL isn't enabled */
6672         return 19200;
6673 }
6674
6675 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6676 {
6677         struct drm_i915_private *dev_priv = dev->dev_private;
6678         uint32_t lcpll = I915_READ(LCPLL_CTL);
6679         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6680
6681         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6682                 return 800000;
6683         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6684                 return 450000;
6685         else if (freq == LCPLL_CLK_FREQ_450)
6686                 return 450000;
6687         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6688                 return 540000;
6689         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6690                 return 337500;
6691         else
6692                 return 675000;
6693 }
6694
6695 static int haswell_get_display_clock_speed(struct drm_device *dev)
6696 {
6697         struct drm_i915_private *dev_priv = dev->dev_private;
6698         uint32_t lcpll = I915_READ(LCPLL_CTL);
6699         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6700
6701         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6702                 return 800000;
6703         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6704                 return 450000;
6705         else if (freq == LCPLL_CLK_FREQ_450)
6706                 return 450000;
6707         else if (IS_HSW_ULT(dev))
6708                 return 337500;
6709         else
6710                 return 540000;
6711 }
6712
6713 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6714 {
6715         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6716                                       CCK_DISPLAY_CLOCK_CONTROL);
6717 }
6718
6719 static int ilk_get_display_clock_speed(struct drm_device *dev)
6720 {
6721         return 450000;
6722 }
6723
6724 static int i945_get_display_clock_speed(struct drm_device *dev)
6725 {
6726         return 400000;
6727 }
6728
6729 static int i915_get_display_clock_speed(struct drm_device *dev)
6730 {
6731         return 333333;
6732 }
6733
6734 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6735 {
6736         return 200000;
6737 }
6738
6739 static int pnv_get_display_clock_speed(struct drm_device *dev)
6740 {
6741         u16 gcfgc = 0;
6742
6743         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6744
6745         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6746         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6747                 return 266667;
6748         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6749                 return 333333;
6750         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6751                 return 444444;
6752         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6753                 return 200000;
6754         default:
6755                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6756         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6757                 return 133333;
6758         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6759                 return 166667;
6760         }
6761 }
6762
6763 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6764 {
6765         u16 gcfgc = 0;
6766
6767         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6768
6769         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6770                 return 133333;
6771         else {
6772                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6773                 case GC_DISPLAY_CLOCK_333_MHZ:
6774                         return 333333;
6775                 default:
6776                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6777                         return 190000;
6778                 }
6779         }
6780 }
6781
6782 static int i865_get_display_clock_speed(struct drm_device *dev)
6783 {
6784         return 266667;
6785 }
6786
6787 static int i85x_get_display_clock_speed(struct drm_device *dev)
6788 {
6789         u16 hpllcc = 0;
6790
6791         /*
6792          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6793          * encoding is different :(
6794          * FIXME is this the right way to detect 852GM/852GMV?
6795          */
6796         if (dev->pdev->revision == 0x1)
6797                 return 133333;
6798
6799         pci_bus_read_config_word(dev->pdev->bus,
6800                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6801
6802         /* Assume that the hardware is in the high speed state.  This
6803          * should be the default.
6804          */
6805         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6806         case GC_CLOCK_133_200:
6807         case GC_CLOCK_133_200_2:
6808         case GC_CLOCK_100_200:
6809                 return 200000;
6810         case GC_CLOCK_166_250:
6811                 return 250000;
6812         case GC_CLOCK_100_133:
6813                 return 133333;
6814         case GC_CLOCK_133_266:
6815         case GC_CLOCK_133_266_2:
6816         case GC_CLOCK_166_266:
6817                 return 266667;
6818         }
6819
6820         /* Shouldn't happen */
6821         return 0;
6822 }
6823
6824 static int i830_get_display_clock_speed(struct drm_device *dev)
6825 {
6826         return 133333;
6827 }
6828
6829 static unsigned int intel_hpll_vco(struct drm_device *dev)
6830 {
6831         struct drm_i915_private *dev_priv = dev->dev_private;
6832         static const unsigned int blb_vco[8] = {
6833                 [0] = 3200000,
6834                 [1] = 4000000,
6835                 [2] = 5333333,
6836                 [3] = 4800000,
6837                 [4] = 6400000,
6838         };
6839         static const unsigned int pnv_vco[8] = {
6840                 [0] = 3200000,
6841                 [1] = 4000000,
6842                 [2] = 5333333,
6843                 [3] = 4800000,
6844                 [4] = 2666667,
6845         };
6846         static const unsigned int cl_vco[8] = {
6847                 [0] = 3200000,
6848                 [1] = 4000000,
6849                 [2] = 5333333,
6850                 [3] = 6400000,
6851                 [4] = 3333333,
6852                 [5] = 3566667,
6853                 [6] = 4266667,
6854         };
6855         static const unsigned int elk_vco[8] = {
6856                 [0] = 3200000,
6857                 [1] = 4000000,
6858                 [2] = 5333333,
6859                 [3] = 4800000,
6860         };
6861         static const unsigned int ctg_vco[8] = {
6862                 [0] = 3200000,
6863                 [1] = 4000000,
6864                 [2] = 5333333,
6865                 [3] = 6400000,
6866                 [4] = 2666667,
6867                 [5] = 4266667,
6868         };
6869         const unsigned int *vco_table;
6870         unsigned int vco;
6871         uint8_t tmp = 0;
6872
6873         /* FIXME other chipsets? */
6874         if (IS_GM45(dev))
6875                 vco_table = ctg_vco;
6876         else if (IS_G4X(dev))
6877                 vco_table = elk_vco;
6878         else if (IS_CRESTLINE(dev))
6879                 vco_table = cl_vco;
6880         else if (IS_PINEVIEW(dev))
6881                 vco_table = pnv_vco;
6882         else if (IS_G33(dev))
6883                 vco_table = blb_vco;
6884         else
6885                 return 0;
6886
6887         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6888
6889         vco = vco_table[tmp & 0x7];
6890         if (vco == 0)
6891                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6892         else
6893                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6894
6895         return vco;
6896 }
6897
6898 static int gm45_get_display_clock_speed(struct drm_device *dev)
6899 {
6900         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6901         uint16_t tmp = 0;
6902
6903         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6904
6905         cdclk_sel = (tmp >> 12) & 0x1;
6906
6907         switch (vco) {
6908         case 2666667:
6909         case 4000000:
6910         case 5333333:
6911                 return cdclk_sel ? 333333 : 222222;
6912         case 3200000:
6913                 return cdclk_sel ? 320000 : 228571;
6914         default:
6915                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6916                 return 222222;
6917         }
6918 }
6919
6920 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6921 {
6922         static const uint8_t div_3200[] = { 16, 10,  8 };
6923         static const uint8_t div_4000[] = { 20, 12, 10 };
6924         static const uint8_t div_5333[] = { 24, 16, 14 };
6925         const uint8_t *div_table;
6926         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6927         uint16_t tmp = 0;
6928
6929         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6930
6931         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6932
6933         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6934                 goto fail;
6935
6936         switch (vco) {
6937         case 3200000:
6938                 div_table = div_3200;
6939                 break;
6940         case 4000000:
6941                 div_table = div_4000;
6942                 break;
6943         case 5333333:
6944                 div_table = div_5333;
6945                 break;
6946         default:
6947                 goto fail;
6948         }
6949
6950         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6951
6952 fail:
6953         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6954         return 200000;
6955 }
6956
6957 static int g33_get_display_clock_speed(struct drm_device *dev)
6958 {
6959         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6960         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6961         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6962         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6963         const uint8_t *div_table;
6964         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6965         uint16_t tmp = 0;
6966
6967         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6968
6969         cdclk_sel = (tmp >> 4) & 0x7;
6970
6971         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6972                 goto fail;
6973
6974         switch (vco) {
6975         case 3200000:
6976                 div_table = div_3200;
6977                 break;
6978         case 4000000:
6979                 div_table = div_4000;
6980                 break;
6981         case 4800000:
6982                 div_table = div_4800;
6983                 break;
6984         case 5333333:
6985                 div_table = div_5333;
6986                 break;
6987         default:
6988                 goto fail;
6989         }
6990
6991         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6992
6993 fail:
6994         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6995         return 190476;
6996 }
6997
6998 static void
6999 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7000 {
7001         while (*num > DATA_LINK_M_N_MASK ||
7002                *den > DATA_LINK_M_N_MASK) {
7003                 *num >>= 1;
7004                 *den >>= 1;
7005         }
7006 }
7007
7008 static void compute_m_n(unsigned int m, unsigned int n,
7009                         uint32_t *ret_m, uint32_t *ret_n)
7010 {
7011         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7012         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7013         intel_reduce_m_n_ratio(ret_m, ret_n);
7014 }
7015
7016 void
7017 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7018                        int pixel_clock, int link_clock,
7019                        struct intel_link_m_n *m_n)
7020 {
7021         m_n->tu = 64;
7022
7023         compute_m_n(bits_per_pixel * pixel_clock,
7024                     link_clock * nlanes * 8,
7025                     &m_n->gmch_m, &m_n->gmch_n);
7026
7027         compute_m_n(pixel_clock, link_clock,
7028                     &m_n->link_m, &m_n->link_n);
7029 }
7030
7031 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7032 {
7033         if (i915.panel_use_ssc >= 0)
7034                 return i915.panel_use_ssc != 0;
7035         return dev_priv->vbt.lvds_use_ssc
7036                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7037 }
7038
7039 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7040 {
7041         return (1 << dpll->n) << 16 | dpll->m2;
7042 }
7043
7044 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7045 {
7046         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7047 }
7048
7049 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7050                                      struct intel_crtc_state *crtc_state,
7051                                      intel_clock_t *reduced_clock)
7052 {
7053         struct drm_device *dev = crtc->base.dev;
7054         u32 fp, fp2 = 0;
7055
7056         if (IS_PINEVIEW(dev)) {
7057                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7058                 if (reduced_clock)
7059                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7060         } else {
7061                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7062                 if (reduced_clock)
7063                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7064         }
7065
7066         crtc_state->dpll_hw_state.fp0 = fp;
7067
7068         crtc->lowfreq_avail = false;
7069         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7070             reduced_clock) {
7071                 crtc_state->dpll_hw_state.fp1 = fp2;
7072                 crtc->lowfreq_avail = true;
7073         } else {
7074                 crtc_state->dpll_hw_state.fp1 = fp;
7075         }
7076 }
7077
7078 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7079                 pipe)
7080 {
7081         u32 reg_val;
7082
7083         /*
7084          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7085          * and set it to a reasonable value instead.
7086          */
7087         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7088         reg_val &= 0xffffff00;
7089         reg_val |= 0x00000030;
7090         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7091
7092         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7093         reg_val &= 0x8cffffff;
7094         reg_val = 0x8c000000;
7095         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7096
7097         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7098         reg_val &= 0xffffff00;
7099         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7100
7101         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7102         reg_val &= 0x00ffffff;
7103         reg_val |= 0xb0000000;
7104         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7105 }
7106
7107 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7108                                          struct intel_link_m_n *m_n)
7109 {
7110         struct drm_device *dev = crtc->base.dev;
7111         struct drm_i915_private *dev_priv = dev->dev_private;
7112         int pipe = crtc->pipe;
7113
7114         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7115         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7116         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7117         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7118 }
7119
7120 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7121                                          struct intel_link_m_n *m_n,
7122                                          struct intel_link_m_n *m2_n2)
7123 {
7124         struct drm_device *dev = crtc->base.dev;
7125         struct drm_i915_private *dev_priv = dev->dev_private;
7126         int pipe = crtc->pipe;
7127         enum transcoder transcoder = crtc->config->cpu_transcoder;
7128
7129         if (INTEL_INFO(dev)->gen >= 5) {
7130                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7131                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7132                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7133                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7134                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7135                  * for gen < 8) and if DRRS is supported (to make sure the
7136                  * registers are not unnecessarily accessed).
7137                  */
7138                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7139                         crtc->config->has_drrs) {
7140                         I915_WRITE(PIPE_DATA_M2(transcoder),
7141                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7142                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7143                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7144                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7145                 }
7146         } else {
7147                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7148                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7149                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7150                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7151         }
7152 }
7153
7154 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7155 {
7156         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7157
7158         if (m_n == M1_N1) {
7159                 dp_m_n = &crtc->config->dp_m_n;
7160                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7161         } else if (m_n == M2_N2) {
7162
7163                 /*
7164                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7165                  * needs to be programmed into M1_N1.
7166                  */
7167                 dp_m_n = &crtc->config->dp_m2_n2;
7168         } else {
7169                 DRM_ERROR("Unsupported divider value\n");
7170                 return;
7171         }
7172
7173         if (crtc->config->has_pch_encoder)
7174                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7175         else
7176                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7177 }
7178
7179 static void vlv_compute_dpll(struct intel_crtc *crtc,
7180                              struct intel_crtc_state *pipe_config)
7181 {
7182         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7183                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7184                 DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
7185         if (crtc->pipe != PIPE_A)
7186                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7187
7188         pipe_config->dpll_hw_state.dpll_md =
7189                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7190 }
7191
7192 static void chv_compute_dpll(struct intel_crtc *crtc,
7193                              struct intel_crtc_state *pipe_config)
7194 {
7195         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7196                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7197                 DPLL_VCO_ENABLE;
7198         if (crtc->pipe != PIPE_A)
7199                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7200
7201         pipe_config->dpll_hw_state.dpll_md =
7202                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7203 }
7204
7205 static void vlv_prepare_pll(struct intel_crtc *crtc,
7206                             const struct intel_crtc_state *pipe_config)
7207 {
7208         struct drm_device *dev = crtc->base.dev;
7209         struct drm_i915_private *dev_priv = dev->dev_private;
7210         int pipe = crtc->pipe;
7211         u32 mdiv;
7212         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7213         u32 coreclk, reg_val;
7214
7215         mutex_lock(&dev_priv->sb_lock);
7216
7217         bestn = pipe_config->dpll.n;
7218         bestm1 = pipe_config->dpll.m1;
7219         bestm2 = pipe_config->dpll.m2;
7220         bestp1 = pipe_config->dpll.p1;
7221         bestp2 = pipe_config->dpll.p2;
7222
7223         /* See eDP HDMI DPIO driver vbios notes doc */
7224
7225         /* PLL B needs special handling */
7226         if (pipe == PIPE_B)
7227                 vlv_pllb_recal_opamp(dev_priv, pipe);
7228
7229         /* Set up Tx target for periodic Rcomp update */
7230         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7231
7232         /* Disable target IRef on PLL */
7233         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7234         reg_val &= 0x00ffffff;
7235         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7236
7237         /* Disable fast lock */
7238         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7239
7240         /* Set idtafcrecal before PLL is enabled */
7241         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7242         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7243         mdiv |= ((bestn << DPIO_N_SHIFT));
7244         mdiv |= (1 << DPIO_K_SHIFT);
7245
7246         /*
7247          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7248          * but we don't support that).
7249          * Note: don't use the DAC post divider as it seems unstable.
7250          */
7251         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7252         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7253
7254         mdiv |= DPIO_ENABLE_CALIBRATION;
7255         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7256
7257         /* Set HBR and RBR LPF coefficients */
7258         if (pipe_config->port_clock == 162000 ||
7259             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7260             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7261                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7262                                  0x009f0003);
7263         else
7264                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7265                                  0x00d0000f);
7266
7267         if (pipe_config->has_dp_encoder) {
7268                 /* Use SSC source */
7269                 if (pipe == PIPE_A)
7270                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7271                                          0x0df40000);
7272                 else
7273                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7274                                          0x0df70000);
7275         } else { /* HDMI or VGA */
7276                 /* Use bend source */
7277                 if (pipe == PIPE_A)
7278                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7279                                          0x0df70000);
7280                 else
7281                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7282                                          0x0df40000);
7283         }
7284
7285         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7286         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7287         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7288             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7289                 coreclk |= 0x01000000;
7290         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7291
7292         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7293         mutex_unlock(&dev_priv->sb_lock);
7294 }
7295
7296 static void chv_prepare_pll(struct intel_crtc *crtc,
7297                             const struct intel_crtc_state *pipe_config)
7298 {
7299         struct drm_device *dev = crtc->base.dev;
7300         struct drm_i915_private *dev_priv = dev->dev_private;
7301         int pipe = crtc->pipe;
7302         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7303         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7304         u32 loopfilter, tribuf_calcntr;
7305         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7306         u32 dpio_val;
7307         int vco;
7308
7309         bestn = pipe_config->dpll.n;
7310         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7311         bestm1 = pipe_config->dpll.m1;
7312         bestm2 = pipe_config->dpll.m2 >> 22;
7313         bestp1 = pipe_config->dpll.p1;
7314         bestp2 = pipe_config->dpll.p2;
7315         vco = pipe_config->dpll.vco;
7316         dpio_val = 0;
7317         loopfilter = 0;
7318
7319         /*
7320          * Enable Refclk and SSC
7321          */
7322         I915_WRITE(dpll_reg,
7323                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7324
7325         mutex_lock(&dev_priv->sb_lock);
7326
7327         /* p1 and p2 divider */
7328         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7329                         5 << DPIO_CHV_S1_DIV_SHIFT |
7330                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7331                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7332                         1 << DPIO_CHV_K_DIV_SHIFT);
7333
7334         /* Feedback post-divider - m2 */
7335         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7336
7337         /* Feedback refclk divider - n and m1 */
7338         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7339                         DPIO_CHV_M1_DIV_BY_2 |
7340                         1 << DPIO_CHV_N_DIV_SHIFT);
7341
7342         /* M2 fraction division */
7343         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7344
7345         /* M2 fraction division enable */
7346         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7347         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7348         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7349         if (bestm2_frac)
7350                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7351         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7352
7353         /* Program digital lock detect threshold */
7354         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7355         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7356                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7357         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7358         if (!bestm2_frac)
7359                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7360         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7361
7362         /* Loop filter */
7363         if (vco == 5400000) {
7364                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7365                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7366                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7367                 tribuf_calcntr = 0x9;
7368         } else if (vco <= 6200000) {
7369                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7370                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7371                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7372                 tribuf_calcntr = 0x9;
7373         } else if (vco <= 6480000) {
7374                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7375                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7376                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7377                 tribuf_calcntr = 0x8;
7378         } else {
7379                 /* Not supported. Apply the same limits as in the max case */
7380                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7381                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7382                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7383                 tribuf_calcntr = 0;
7384         }
7385         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7386
7387         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7388         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7389         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7390         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7391
7392         /* AFC Recal */
7393         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7394                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7395                         DPIO_AFC_RECAL);
7396
7397         mutex_unlock(&dev_priv->sb_lock);
7398 }
7399
7400 /**
7401  * vlv_force_pll_on - forcibly enable just the PLL
7402  * @dev_priv: i915 private structure
7403  * @pipe: pipe PLL to enable
7404  * @dpll: PLL configuration
7405  *
7406  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7407  * in cases where we need the PLL enabled even when @pipe is not going to
7408  * be enabled.
7409  */
7410 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7411                      const struct dpll *dpll)
7412 {
7413         struct intel_crtc *crtc =
7414                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7415         struct intel_crtc_state *pipe_config;
7416
7417         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7418         if (!pipe_config)
7419                 return -ENOMEM;
7420
7421         pipe_config->base.crtc = &crtc->base;
7422         pipe_config->pixel_multiplier = 1;
7423         pipe_config->dpll = *dpll;
7424
7425         if (IS_CHERRYVIEW(dev)) {
7426                 chv_compute_dpll(crtc, pipe_config);
7427                 chv_prepare_pll(crtc, pipe_config);
7428                 chv_enable_pll(crtc, pipe_config);
7429         } else {
7430                 vlv_compute_dpll(crtc, pipe_config);
7431                 vlv_prepare_pll(crtc, pipe_config);
7432                 vlv_enable_pll(crtc, pipe_config);
7433         }
7434
7435         kfree(pipe_config);
7436
7437         return 0;
7438 }
7439
7440 /**
7441  * vlv_force_pll_off - forcibly disable just the PLL
7442  * @dev_priv: i915 private structure
7443  * @pipe: pipe PLL to disable
7444  *
7445  * Disable the PLL for @pipe. To be used in cases where we need
7446  * the PLL enabled even when @pipe is not going to be enabled.
7447  */
7448 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7449 {
7450         if (IS_CHERRYVIEW(dev))
7451                 chv_disable_pll(to_i915(dev), pipe);
7452         else
7453                 vlv_disable_pll(to_i915(dev), pipe);
7454 }
7455
7456 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7457                               struct intel_crtc_state *crtc_state,
7458                               intel_clock_t *reduced_clock)
7459 {
7460         struct drm_device *dev = crtc->base.dev;
7461         struct drm_i915_private *dev_priv = dev->dev_private;
7462         u32 dpll;
7463         bool is_sdvo;
7464         struct dpll *clock = &crtc_state->dpll;
7465
7466         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7467
7468         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7469                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7470
7471         dpll = DPLL_VGA_MODE_DIS;
7472
7473         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7474                 dpll |= DPLLB_MODE_LVDS;
7475         else
7476                 dpll |= DPLLB_MODE_DAC_SERIAL;
7477
7478         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7479                 dpll |= (crtc_state->pixel_multiplier - 1)
7480                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7481         }
7482
7483         if (is_sdvo)
7484                 dpll |= DPLL_SDVO_HIGH_SPEED;
7485
7486         if (crtc_state->has_dp_encoder)
7487                 dpll |= DPLL_SDVO_HIGH_SPEED;
7488
7489         /* compute bitmask from p1 value */
7490         if (IS_PINEVIEW(dev))
7491                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7492         else {
7493                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7494                 if (IS_G4X(dev) && reduced_clock)
7495                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7496         }
7497         switch (clock->p2) {
7498         case 5:
7499                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7500                 break;
7501         case 7:
7502                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7503                 break;
7504         case 10:
7505                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7506                 break;
7507         case 14:
7508                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7509                 break;
7510         }
7511         if (INTEL_INFO(dev)->gen >= 4)
7512                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7513
7514         if (crtc_state->sdvo_tv_clock)
7515                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7516         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7517                  intel_panel_use_ssc(dev_priv))
7518                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7519         else
7520                 dpll |= PLL_REF_INPUT_DREFCLK;
7521
7522         dpll |= DPLL_VCO_ENABLE;
7523         crtc_state->dpll_hw_state.dpll = dpll;
7524
7525         if (INTEL_INFO(dev)->gen >= 4) {
7526                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7527                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7528                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7529         }
7530 }
7531
7532 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7533                               struct intel_crtc_state *crtc_state,
7534                               intel_clock_t *reduced_clock)
7535 {
7536         struct drm_device *dev = crtc->base.dev;
7537         struct drm_i915_private *dev_priv = dev->dev_private;
7538         u32 dpll;
7539         struct dpll *clock = &crtc_state->dpll;
7540
7541         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7542
7543         dpll = DPLL_VGA_MODE_DIS;
7544
7545         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7546                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7547         } else {
7548                 if (clock->p1 == 2)
7549                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7550                 else
7551                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7552                 if (clock->p2 == 4)
7553                         dpll |= PLL_P2_DIVIDE_BY_4;
7554         }
7555
7556         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7557                 dpll |= DPLL_DVO_2X_MODE;
7558
7559         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7560             intel_panel_use_ssc(dev_priv))
7561                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7562         else
7563                 dpll |= PLL_REF_INPUT_DREFCLK;
7564
7565         dpll |= DPLL_VCO_ENABLE;
7566         crtc_state->dpll_hw_state.dpll = dpll;
7567 }
7568
7569 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7570 {
7571         struct drm_device *dev = intel_crtc->base.dev;
7572         struct drm_i915_private *dev_priv = dev->dev_private;
7573         enum pipe pipe = intel_crtc->pipe;
7574         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7575         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7576         uint32_t crtc_vtotal, crtc_vblank_end;
7577         int vsyncshift = 0;
7578
7579         /* We need to be careful not to changed the adjusted mode, for otherwise
7580          * the hw state checker will get angry at the mismatch. */
7581         crtc_vtotal = adjusted_mode->crtc_vtotal;
7582         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7583
7584         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7585                 /* the chip adds 2 halflines automatically */
7586                 crtc_vtotal -= 1;
7587                 crtc_vblank_end -= 1;
7588
7589                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7590                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7591                 else
7592                         vsyncshift = adjusted_mode->crtc_hsync_start -
7593                                 adjusted_mode->crtc_htotal / 2;
7594                 if (vsyncshift < 0)
7595                         vsyncshift += adjusted_mode->crtc_htotal;
7596         }
7597
7598         if (INTEL_INFO(dev)->gen > 3)
7599                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7600
7601         I915_WRITE(HTOTAL(cpu_transcoder),
7602                    (adjusted_mode->crtc_hdisplay - 1) |
7603                    ((adjusted_mode->crtc_htotal - 1) << 16));
7604         I915_WRITE(HBLANK(cpu_transcoder),
7605                    (adjusted_mode->crtc_hblank_start - 1) |
7606                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7607         I915_WRITE(HSYNC(cpu_transcoder),
7608                    (adjusted_mode->crtc_hsync_start - 1) |
7609                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7610
7611         I915_WRITE(VTOTAL(cpu_transcoder),
7612                    (adjusted_mode->crtc_vdisplay - 1) |
7613                    ((crtc_vtotal - 1) << 16));
7614         I915_WRITE(VBLANK(cpu_transcoder),
7615                    (adjusted_mode->crtc_vblank_start - 1) |
7616                    ((crtc_vblank_end - 1) << 16));
7617         I915_WRITE(VSYNC(cpu_transcoder),
7618                    (adjusted_mode->crtc_vsync_start - 1) |
7619                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7620
7621         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7622          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7623          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7624          * bits. */
7625         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7626             (pipe == PIPE_B || pipe == PIPE_C))
7627                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7628
7629 }
7630
7631 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7632 {
7633         struct drm_device *dev = intel_crtc->base.dev;
7634         struct drm_i915_private *dev_priv = dev->dev_private;
7635         enum pipe pipe = intel_crtc->pipe;
7636
7637         /* pipesrc controls the size that is scaled from, which should
7638          * always be the user's requested size.
7639          */
7640         I915_WRITE(PIPESRC(pipe),
7641                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7642                    (intel_crtc->config->pipe_src_h - 1));
7643 }
7644
7645 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7646                                    struct intel_crtc_state *pipe_config)
7647 {
7648         struct drm_device *dev = crtc->base.dev;
7649         struct drm_i915_private *dev_priv = dev->dev_private;
7650         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7651         uint32_t tmp;
7652
7653         tmp = I915_READ(HTOTAL(cpu_transcoder));
7654         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7655         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7656         tmp = I915_READ(HBLANK(cpu_transcoder));
7657         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7658         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7659         tmp = I915_READ(HSYNC(cpu_transcoder));
7660         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7661         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7662
7663         tmp = I915_READ(VTOTAL(cpu_transcoder));
7664         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7665         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7666         tmp = I915_READ(VBLANK(cpu_transcoder));
7667         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7668         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7669         tmp = I915_READ(VSYNC(cpu_transcoder));
7670         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7671         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7672
7673         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7674                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7675                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7676                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7677         }
7678 }
7679
7680 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7681                                     struct intel_crtc_state *pipe_config)
7682 {
7683         struct drm_device *dev = crtc->base.dev;
7684         struct drm_i915_private *dev_priv = dev->dev_private;
7685         u32 tmp;
7686
7687         tmp = I915_READ(PIPESRC(crtc->pipe));
7688         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7689         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7690
7691         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7692         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7693 }
7694
7695 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7696                                  struct intel_crtc_state *pipe_config)
7697 {
7698         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7699         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7700         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7701         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7702
7703         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7704         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7705         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7706         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7707
7708         mode->flags = pipe_config->base.adjusted_mode.flags;
7709         mode->type = DRM_MODE_TYPE_DRIVER;
7710
7711         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7712         mode->flags |= pipe_config->base.adjusted_mode.flags;
7713
7714         mode->hsync = drm_mode_hsync(mode);
7715         mode->vrefresh = drm_mode_vrefresh(mode);
7716         drm_mode_set_name(mode);
7717 }
7718
7719 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7720 {
7721         struct drm_device *dev = intel_crtc->base.dev;
7722         struct drm_i915_private *dev_priv = dev->dev_private;
7723         uint32_t pipeconf;
7724
7725         pipeconf = 0;
7726
7727         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7728             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7729                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7730
7731         if (intel_crtc->config->double_wide)
7732                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7733
7734         /* only g4x and later have fancy bpc/dither controls */
7735         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7736                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7737                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7738                         pipeconf |= PIPECONF_DITHER_EN |
7739                                     PIPECONF_DITHER_TYPE_SP;
7740
7741                 switch (intel_crtc->config->pipe_bpp) {
7742                 case 18:
7743                         pipeconf |= PIPECONF_6BPC;
7744                         break;
7745                 case 24:
7746                         pipeconf |= PIPECONF_8BPC;
7747                         break;
7748                 case 30:
7749                         pipeconf |= PIPECONF_10BPC;
7750                         break;
7751                 default:
7752                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7753                         BUG();
7754                 }
7755         }
7756
7757         if (HAS_PIPE_CXSR(dev)) {
7758                 if (intel_crtc->lowfreq_avail) {
7759                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7760                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7761                 } else {
7762                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7763                 }
7764         }
7765
7766         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7767                 if (INTEL_INFO(dev)->gen < 4 ||
7768                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7769                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7770                 else
7771                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7772         } else
7773                 pipeconf |= PIPECONF_PROGRESSIVE;
7774
7775         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7776              intel_crtc->config->limited_color_range)
7777                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7778
7779         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7780         POSTING_READ(PIPECONF(intel_crtc->pipe));
7781 }
7782
7783 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7784                                    struct intel_crtc_state *crtc_state)
7785 {
7786         struct drm_device *dev = crtc->base.dev;
7787         struct drm_i915_private *dev_priv = dev->dev_private;
7788         const intel_limit_t *limit;
7789         int refclk = 48000;
7790
7791         memset(&crtc_state->dpll_hw_state, 0,
7792                sizeof(crtc_state->dpll_hw_state));
7793
7794         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7795                 if (intel_panel_use_ssc(dev_priv)) {
7796                         refclk = dev_priv->vbt.lvds_ssc_freq;
7797                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7798                 }
7799
7800                 limit = &intel_limits_i8xx_lvds;
7801         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7802                 limit = &intel_limits_i8xx_dvo;
7803         } else {
7804                 limit = &intel_limits_i8xx_dac;
7805         }
7806
7807         if (!crtc_state->clock_set &&
7808             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7809                                  refclk, NULL, &crtc_state->dpll)) {
7810                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7811                 return -EINVAL;
7812         }
7813
7814         i8xx_compute_dpll(crtc, crtc_state, NULL);
7815
7816         return 0;
7817 }
7818
7819 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7820                                   struct intel_crtc_state *crtc_state)
7821 {
7822         struct drm_device *dev = crtc->base.dev;
7823         struct drm_i915_private *dev_priv = dev->dev_private;
7824         const intel_limit_t *limit;
7825         int refclk = 96000;
7826
7827         memset(&crtc_state->dpll_hw_state, 0,
7828                sizeof(crtc_state->dpll_hw_state));
7829
7830         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7831                 if (intel_panel_use_ssc(dev_priv)) {
7832                         refclk = dev_priv->vbt.lvds_ssc_freq;
7833                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7834                 }
7835
7836                 if (intel_is_dual_link_lvds(dev))
7837                         limit = &intel_limits_g4x_dual_channel_lvds;
7838                 else
7839                         limit = &intel_limits_g4x_single_channel_lvds;
7840         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7841                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7842                 limit = &intel_limits_g4x_hdmi;
7843         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7844                 limit = &intel_limits_g4x_sdvo;
7845         } else {
7846                 /* The option is for other outputs */
7847                 limit = &intel_limits_i9xx_sdvo;
7848         }
7849
7850         if (!crtc_state->clock_set &&
7851             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7852                                 refclk, NULL, &crtc_state->dpll)) {
7853                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7854                 return -EINVAL;
7855         }
7856
7857         i9xx_compute_dpll(crtc, crtc_state, NULL);
7858
7859         return 0;
7860 }
7861
7862 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7863                                   struct intel_crtc_state *crtc_state)
7864 {
7865         struct drm_device *dev = crtc->base.dev;
7866         struct drm_i915_private *dev_priv = dev->dev_private;
7867         const intel_limit_t *limit;
7868         int refclk = 96000;
7869
7870         memset(&crtc_state->dpll_hw_state, 0,
7871                sizeof(crtc_state->dpll_hw_state));
7872
7873         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7874                 if (intel_panel_use_ssc(dev_priv)) {
7875                         refclk = dev_priv->vbt.lvds_ssc_freq;
7876                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7877                 }
7878
7879                 limit = &intel_limits_pineview_lvds;
7880         } else {
7881                 limit = &intel_limits_pineview_sdvo;
7882         }
7883
7884         if (!crtc_state->clock_set &&
7885             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7886                                 refclk, NULL, &crtc_state->dpll)) {
7887                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7888                 return -EINVAL;
7889         }
7890
7891         i9xx_compute_dpll(crtc, crtc_state, NULL);
7892
7893         return 0;
7894 }
7895
7896 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7897                                    struct intel_crtc_state *crtc_state)
7898 {
7899         struct drm_device *dev = crtc->base.dev;
7900         struct drm_i915_private *dev_priv = dev->dev_private;
7901         const intel_limit_t *limit;
7902         int refclk = 96000;
7903
7904         memset(&crtc_state->dpll_hw_state, 0,
7905                sizeof(crtc_state->dpll_hw_state));
7906
7907         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7908                 if (intel_panel_use_ssc(dev_priv)) {
7909                         refclk = dev_priv->vbt.lvds_ssc_freq;
7910                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7911                 }
7912
7913                 limit = &intel_limits_i9xx_lvds;
7914         } else {
7915                 limit = &intel_limits_i9xx_sdvo;
7916         }
7917
7918         if (!crtc_state->clock_set &&
7919             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7920                                  refclk, NULL, &crtc_state->dpll)) {
7921                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7922                 return -EINVAL;
7923         }
7924
7925         i9xx_compute_dpll(crtc, crtc_state, NULL);
7926
7927         return 0;
7928 }
7929
7930 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7931                                   struct intel_crtc_state *crtc_state)
7932 {
7933         int refclk = 100000;
7934         const intel_limit_t *limit = &intel_limits_chv;
7935
7936         memset(&crtc_state->dpll_hw_state, 0,
7937                sizeof(crtc_state->dpll_hw_state));
7938
7939         if (crtc_state->has_dsi_encoder)
7940                 return 0;
7941
7942         if (!crtc_state->clock_set &&
7943             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7944                                 refclk, NULL, &crtc_state->dpll)) {
7945                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7946                 return -EINVAL;
7947         }
7948
7949         chv_compute_dpll(crtc, crtc_state);
7950
7951         return 0;
7952 }
7953
7954 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7955                                   struct intel_crtc_state *crtc_state)
7956 {
7957         int refclk = 100000;
7958         const intel_limit_t *limit = &intel_limits_vlv;
7959
7960         memset(&crtc_state->dpll_hw_state, 0,
7961                sizeof(crtc_state->dpll_hw_state));
7962
7963         if (crtc_state->has_dsi_encoder)
7964                 return 0;
7965
7966         if (!crtc_state->clock_set &&
7967             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7968                                 refclk, NULL, &crtc_state->dpll)) {
7969                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7970                 return -EINVAL;
7971         }
7972
7973         vlv_compute_dpll(crtc, crtc_state);
7974
7975         return 0;
7976 }
7977
7978 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7979                                  struct intel_crtc_state *pipe_config)
7980 {
7981         struct drm_device *dev = crtc->base.dev;
7982         struct drm_i915_private *dev_priv = dev->dev_private;
7983         uint32_t tmp;
7984
7985         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7986                 return;
7987
7988         tmp = I915_READ(PFIT_CONTROL);
7989         if (!(tmp & PFIT_ENABLE))
7990                 return;
7991
7992         /* Check whether the pfit is attached to our pipe. */
7993         if (INTEL_INFO(dev)->gen < 4) {
7994                 if (crtc->pipe != PIPE_B)
7995                         return;
7996         } else {
7997                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7998                         return;
7999         }
8000
8001         pipe_config->gmch_pfit.control = tmp;
8002         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8003         if (INTEL_INFO(dev)->gen < 5)
8004                 pipe_config->gmch_pfit.lvds_border_bits =
8005                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8006 }
8007
8008 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8009                                struct intel_crtc_state *pipe_config)
8010 {
8011         struct drm_device *dev = crtc->base.dev;
8012         struct drm_i915_private *dev_priv = dev->dev_private;
8013         int pipe = pipe_config->cpu_transcoder;
8014         intel_clock_t clock;
8015         u32 mdiv;
8016         int refclk = 100000;
8017
8018         /* In case of DSI, DPLL will not be used */
8019         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8020                 return;
8021
8022         mutex_lock(&dev_priv->sb_lock);
8023         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8024         mutex_unlock(&dev_priv->sb_lock);
8025
8026         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8027         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8028         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8029         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8030         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8031
8032         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8033 }
8034
8035 static void
8036 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8037                               struct intel_initial_plane_config *plane_config)
8038 {
8039         struct drm_device *dev = crtc->base.dev;
8040         struct drm_i915_private *dev_priv = dev->dev_private;
8041         u32 val, base, offset;
8042         int pipe = crtc->pipe, plane = crtc->plane;
8043         int fourcc, pixel_format;
8044         unsigned int aligned_height;
8045         struct drm_framebuffer *fb;
8046         struct intel_framebuffer *intel_fb;
8047
8048         val = I915_READ(DSPCNTR(plane));
8049         if (!(val & DISPLAY_PLANE_ENABLE))
8050                 return;
8051
8052         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8053         if (!intel_fb) {
8054                 DRM_DEBUG_KMS("failed to alloc fb\n");
8055                 return;
8056         }
8057
8058         fb = &intel_fb->base;
8059
8060         if (INTEL_INFO(dev)->gen >= 4) {
8061                 if (val & DISPPLANE_TILED) {
8062                         plane_config->tiling = I915_TILING_X;
8063                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8064                 }
8065         }
8066
8067         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8068         fourcc = i9xx_format_to_fourcc(pixel_format);
8069         fb->pixel_format = fourcc;
8070         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8071
8072         if (INTEL_INFO(dev)->gen >= 4) {
8073                 if (plane_config->tiling)
8074                         offset = I915_READ(DSPTILEOFF(plane));
8075                 else
8076                         offset = I915_READ(DSPLINOFF(plane));
8077                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8078         } else {
8079                 base = I915_READ(DSPADDR(plane));
8080         }
8081         plane_config->base = base;
8082
8083         val = I915_READ(PIPESRC(pipe));
8084         fb->width = ((val >> 16) & 0xfff) + 1;
8085         fb->height = ((val >> 0) & 0xfff) + 1;
8086
8087         val = I915_READ(DSPSTRIDE(pipe));
8088         fb->pitches[0] = val & 0xffffffc0;
8089
8090         aligned_height = intel_fb_align_height(dev, fb->height,
8091                                                fb->pixel_format,
8092                                                fb->modifier[0]);
8093
8094         plane_config->size = fb->pitches[0] * aligned_height;
8095
8096         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8097                       pipe_name(pipe), plane, fb->width, fb->height,
8098                       fb->bits_per_pixel, base, fb->pitches[0],
8099                       plane_config->size);
8100
8101         plane_config->fb = intel_fb;
8102 }
8103
8104 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8105                                struct intel_crtc_state *pipe_config)
8106 {
8107         struct drm_device *dev = crtc->base.dev;
8108         struct drm_i915_private *dev_priv = dev->dev_private;
8109         int pipe = pipe_config->cpu_transcoder;
8110         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8111         intel_clock_t clock;
8112         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8113         int refclk = 100000;
8114
8115         /* In case of DSI, DPLL will not be used */
8116         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8117                 return;
8118
8119         mutex_lock(&dev_priv->sb_lock);
8120         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8121         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8122         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8123         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8124         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8125         mutex_unlock(&dev_priv->sb_lock);
8126
8127         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8128         clock.m2 = (pll_dw0 & 0xff) << 22;
8129         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8130                 clock.m2 |= pll_dw2 & 0x3fffff;
8131         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8132         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8133         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8134
8135         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8136 }
8137
8138 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8139                                  struct intel_crtc_state *pipe_config)
8140 {
8141         struct drm_device *dev = crtc->base.dev;
8142         struct drm_i915_private *dev_priv = dev->dev_private;
8143         enum intel_display_power_domain power_domain;
8144         uint32_t tmp;
8145         bool ret;
8146
8147         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8148         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8149                 return false;
8150
8151         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8152         pipe_config->shared_dpll = NULL;
8153
8154         ret = false;
8155
8156         tmp = I915_READ(PIPECONF(crtc->pipe));
8157         if (!(tmp & PIPECONF_ENABLE))
8158                 goto out;
8159
8160         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8161                 switch (tmp & PIPECONF_BPC_MASK) {
8162                 case PIPECONF_6BPC:
8163                         pipe_config->pipe_bpp = 18;
8164                         break;
8165                 case PIPECONF_8BPC:
8166                         pipe_config->pipe_bpp = 24;
8167                         break;
8168                 case PIPECONF_10BPC:
8169                         pipe_config->pipe_bpp = 30;
8170                         break;
8171                 default:
8172                         break;
8173                 }
8174         }
8175
8176         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8177             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8178                 pipe_config->limited_color_range = true;
8179
8180         if (INTEL_INFO(dev)->gen < 4)
8181                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8182
8183         intel_get_pipe_timings(crtc, pipe_config);
8184         intel_get_pipe_src_size(crtc, pipe_config);
8185
8186         i9xx_get_pfit_config(crtc, pipe_config);
8187
8188         if (INTEL_INFO(dev)->gen >= 4) {
8189                 /* No way to read it out on pipes B and C */
8190                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8191                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8192                 else
8193                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8194                 pipe_config->pixel_multiplier =
8195                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8196                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8197                 pipe_config->dpll_hw_state.dpll_md = tmp;
8198         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8199                 tmp = I915_READ(DPLL(crtc->pipe));
8200                 pipe_config->pixel_multiplier =
8201                         ((tmp & SDVO_MULTIPLIER_MASK)
8202                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8203         } else {
8204                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8205                  * port and will be fixed up in the encoder->get_config
8206                  * function. */
8207                 pipe_config->pixel_multiplier = 1;
8208         }
8209         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8210         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8211                 /*
8212                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8213                  * on 830. Filter it out here so that we don't
8214                  * report errors due to that.
8215                  */
8216                 if (IS_I830(dev))
8217                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8218
8219                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8220                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8221         } else {
8222                 /* Mask out read-only status bits. */
8223                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8224                                                      DPLL_PORTC_READY_MASK |
8225                                                      DPLL_PORTB_READY_MASK);
8226         }
8227
8228         if (IS_CHERRYVIEW(dev))
8229                 chv_crtc_clock_get(crtc, pipe_config);
8230         else if (IS_VALLEYVIEW(dev))
8231                 vlv_crtc_clock_get(crtc, pipe_config);
8232         else
8233                 i9xx_crtc_clock_get(crtc, pipe_config);
8234
8235         /*
8236          * Normally the dotclock is filled in by the encoder .get_config()
8237          * but in case the pipe is enabled w/o any ports we need a sane
8238          * default.
8239          */
8240         pipe_config->base.adjusted_mode.crtc_clock =
8241                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8242
8243         ret = true;
8244
8245 out:
8246         intel_display_power_put(dev_priv, power_domain);
8247
8248         return ret;
8249 }
8250
8251 static void ironlake_init_pch_refclk(struct drm_device *dev)
8252 {
8253         struct drm_i915_private *dev_priv = dev->dev_private;
8254         struct intel_encoder *encoder;
8255         u32 val, final;
8256         bool has_lvds = false;
8257         bool has_cpu_edp = false;
8258         bool has_panel = false;
8259         bool has_ck505 = false;
8260         bool can_ssc = false;
8261
8262         /* We need to take the global config into account */
8263         for_each_intel_encoder(dev, encoder) {
8264                 switch (encoder->type) {
8265                 case INTEL_OUTPUT_LVDS:
8266                         has_panel = true;
8267                         has_lvds = true;
8268                         break;
8269                 case INTEL_OUTPUT_EDP:
8270                         has_panel = true;
8271                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8272                                 has_cpu_edp = true;
8273                         break;
8274                 default:
8275                         break;
8276                 }
8277         }
8278
8279         if (HAS_PCH_IBX(dev)) {
8280                 has_ck505 = dev_priv->vbt.display_clock_mode;
8281                 can_ssc = has_ck505;
8282         } else {
8283                 has_ck505 = false;
8284                 can_ssc = true;
8285         }
8286
8287         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8288                       has_panel, has_lvds, has_ck505);
8289
8290         /* Ironlake: try to setup display ref clock before DPLL
8291          * enabling. This is only under driver's control after
8292          * PCH B stepping, previous chipset stepping should be
8293          * ignoring this setting.
8294          */
8295         val = I915_READ(PCH_DREF_CONTROL);
8296
8297         /* As we must carefully and slowly disable/enable each source in turn,
8298          * compute the final state we want first and check if we need to
8299          * make any changes at all.
8300          */
8301         final = val;
8302         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8303         if (has_ck505)
8304                 final |= DREF_NONSPREAD_CK505_ENABLE;
8305         else
8306                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8307
8308         final &= ~DREF_SSC_SOURCE_MASK;
8309         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8310         final &= ~DREF_SSC1_ENABLE;
8311
8312         if (has_panel) {
8313                 final |= DREF_SSC_SOURCE_ENABLE;
8314
8315                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8316                         final |= DREF_SSC1_ENABLE;
8317
8318                 if (has_cpu_edp) {
8319                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8320                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8321                         else
8322                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8323                 } else
8324                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8325         } else {
8326                 final |= DREF_SSC_SOURCE_DISABLE;
8327                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8328         }
8329
8330         if (final == val)
8331                 return;
8332
8333         /* Always enable nonspread source */
8334         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8335
8336         if (has_ck505)
8337                 val |= DREF_NONSPREAD_CK505_ENABLE;
8338         else
8339                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8340
8341         if (has_panel) {
8342                 val &= ~DREF_SSC_SOURCE_MASK;
8343                 val |= DREF_SSC_SOURCE_ENABLE;
8344
8345                 /* SSC must be turned on before enabling the CPU output  */
8346                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8347                         DRM_DEBUG_KMS("Using SSC on panel\n");
8348                         val |= DREF_SSC1_ENABLE;
8349                 } else
8350                         val &= ~DREF_SSC1_ENABLE;
8351
8352                 /* Get SSC going before enabling the outputs */
8353                 I915_WRITE(PCH_DREF_CONTROL, val);
8354                 POSTING_READ(PCH_DREF_CONTROL);
8355                 udelay(200);
8356
8357                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8358
8359                 /* Enable CPU source on CPU attached eDP */
8360                 if (has_cpu_edp) {
8361                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8362                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8363                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8364                         } else
8365                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8366                 } else
8367                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8368
8369                 I915_WRITE(PCH_DREF_CONTROL, val);
8370                 POSTING_READ(PCH_DREF_CONTROL);
8371                 udelay(200);
8372         } else {
8373                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8374
8375                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8376
8377                 /* Turn off CPU output */
8378                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8379
8380                 I915_WRITE(PCH_DREF_CONTROL, val);
8381                 POSTING_READ(PCH_DREF_CONTROL);
8382                 udelay(200);
8383
8384                 /* Turn off the SSC source */
8385                 val &= ~DREF_SSC_SOURCE_MASK;
8386                 val |= DREF_SSC_SOURCE_DISABLE;
8387
8388                 /* Turn off SSC1 */
8389                 val &= ~DREF_SSC1_ENABLE;
8390
8391                 I915_WRITE(PCH_DREF_CONTROL, val);
8392                 POSTING_READ(PCH_DREF_CONTROL);
8393                 udelay(200);
8394         }
8395
8396         BUG_ON(val != final);
8397 }
8398
8399 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8400 {
8401         uint32_t tmp;
8402
8403         tmp = I915_READ(SOUTH_CHICKEN2);
8404         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8405         I915_WRITE(SOUTH_CHICKEN2, tmp);
8406
8407         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8408                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8409                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8410
8411         tmp = I915_READ(SOUTH_CHICKEN2);
8412         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8413         I915_WRITE(SOUTH_CHICKEN2, tmp);
8414
8415         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8416                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8417                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8418 }
8419
8420 /* WaMPhyProgramming:hsw */
8421 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8422 {
8423         uint32_t tmp;
8424
8425         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8426         tmp &= ~(0xFF << 24);
8427         tmp |= (0x12 << 24);
8428         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8429
8430         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8431         tmp |= (1 << 11);
8432         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8433
8434         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8435         tmp |= (1 << 11);
8436         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8437
8438         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8439         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8440         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8441
8442         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8443         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8444         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8445
8446         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8447         tmp &= ~(7 << 13);
8448         tmp |= (5 << 13);
8449         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8450
8451         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8452         tmp &= ~(7 << 13);
8453         tmp |= (5 << 13);
8454         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8455
8456         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8457         tmp &= ~0xFF;
8458         tmp |= 0x1C;
8459         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8460
8461         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8462         tmp &= ~0xFF;
8463         tmp |= 0x1C;
8464         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8465
8466         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8467         tmp &= ~(0xFF << 16);
8468         tmp |= (0x1C << 16);
8469         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8470
8471         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8472         tmp &= ~(0xFF << 16);
8473         tmp |= (0x1C << 16);
8474         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8475
8476         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8477         tmp |= (1 << 27);
8478         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8479
8480         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8481         tmp |= (1 << 27);
8482         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8483
8484         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8485         tmp &= ~(0xF << 28);
8486         tmp |= (4 << 28);
8487         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8488
8489         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8490         tmp &= ~(0xF << 28);
8491         tmp |= (4 << 28);
8492         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8493 }
8494
8495 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8496  * Programming" based on the parameters passed:
8497  * - Sequence to enable CLKOUT_DP
8498  * - Sequence to enable CLKOUT_DP without spread
8499  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8500  */
8501 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8502                                  bool with_fdi)
8503 {
8504         struct drm_i915_private *dev_priv = dev->dev_private;
8505         uint32_t reg, tmp;
8506
8507         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8508                 with_spread = true;
8509         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8510                 with_fdi = false;
8511
8512         mutex_lock(&dev_priv->sb_lock);
8513
8514         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8515         tmp &= ~SBI_SSCCTL_DISABLE;
8516         tmp |= SBI_SSCCTL_PATHALT;
8517         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8518
8519         udelay(24);
8520
8521         if (with_spread) {
8522                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8523                 tmp &= ~SBI_SSCCTL_PATHALT;
8524                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8525
8526                 if (with_fdi) {
8527                         lpt_reset_fdi_mphy(dev_priv);
8528                         lpt_program_fdi_mphy(dev_priv);
8529                 }
8530         }
8531
8532         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8533         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8534         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8535         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8536
8537         mutex_unlock(&dev_priv->sb_lock);
8538 }
8539
8540 /* Sequence to disable CLKOUT_DP */
8541 static void lpt_disable_clkout_dp(struct drm_device *dev)
8542 {
8543         struct drm_i915_private *dev_priv = dev->dev_private;
8544         uint32_t reg, tmp;
8545
8546         mutex_lock(&dev_priv->sb_lock);
8547
8548         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8549         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8550         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8551         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8552
8553         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8554         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8555                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8556                         tmp |= SBI_SSCCTL_PATHALT;
8557                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8558                         udelay(32);
8559                 }
8560                 tmp |= SBI_SSCCTL_DISABLE;
8561                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8562         }
8563
8564         mutex_unlock(&dev_priv->sb_lock);
8565 }
8566
8567 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8568
8569 static const uint16_t sscdivintphase[] = {
8570         [BEND_IDX( 50)] = 0x3B23,
8571         [BEND_IDX( 45)] = 0x3B23,
8572         [BEND_IDX( 40)] = 0x3C23,
8573         [BEND_IDX( 35)] = 0x3C23,
8574         [BEND_IDX( 30)] = 0x3D23,
8575         [BEND_IDX( 25)] = 0x3D23,
8576         [BEND_IDX( 20)] = 0x3E23,
8577         [BEND_IDX( 15)] = 0x3E23,
8578         [BEND_IDX( 10)] = 0x3F23,
8579         [BEND_IDX(  5)] = 0x3F23,
8580         [BEND_IDX(  0)] = 0x0025,
8581         [BEND_IDX( -5)] = 0x0025,
8582         [BEND_IDX(-10)] = 0x0125,
8583         [BEND_IDX(-15)] = 0x0125,
8584         [BEND_IDX(-20)] = 0x0225,
8585         [BEND_IDX(-25)] = 0x0225,
8586         [BEND_IDX(-30)] = 0x0325,
8587         [BEND_IDX(-35)] = 0x0325,
8588         [BEND_IDX(-40)] = 0x0425,
8589         [BEND_IDX(-45)] = 0x0425,
8590         [BEND_IDX(-50)] = 0x0525,
8591 };
8592
8593 /*
8594  * Bend CLKOUT_DP
8595  * steps -50 to 50 inclusive, in steps of 5
8596  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8597  * change in clock period = -(steps / 10) * 5.787 ps
8598  */
8599 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8600 {
8601         uint32_t tmp;
8602         int idx = BEND_IDX(steps);
8603
8604         if (WARN_ON(steps % 5 != 0))
8605                 return;
8606
8607         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8608                 return;
8609
8610         mutex_lock(&dev_priv->sb_lock);
8611
8612         if (steps % 10 != 0)
8613                 tmp = 0xAAAAAAAB;
8614         else
8615                 tmp = 0x00000000;
8616         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8617
8618         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8619         tmp &= 0xffff0000;
8620         tmp |= sscdivintphase[idx];
8621         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8622
8623         mutex_unlock(&dev_priv->sb_lock);
8624 }
8625
8626 #undef BEND_IDX
8627
8628 static void lpt_init_pch_refclk(struct drm_device *dev)
8629 {
8630         struct intel_encoder *encoder;
8631         bool has_vga = false;
8632
8633         for_each_intel_encoder(dev, encoder) {
8634                 switch (encoder->type) {
8635                 case INTEL_OUTPUT_ANALOG:
8636                         has_vga = true;
8637                         break;
8638                 default:
8639                         break;
8640                 }
8641         }
8642
8643         if (has_vga) {
8644                 lpt_bend_clkout_dp(to_i915(dev), 0);
8645                 lpt_enable_clkout_dp(dev, true, true);
8646         } else {
8647                 lpt_disable_clkout_dp(dev);
8648         }
8649 }
8650
8651 /*
8652  * Initialize reference clocks when the driver loads
8653  */
8654 void intel_init_pch_refclk(struct drm_device *dev)
8655 {
8656         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8657                 ironlake_init_pch_refclk(dev);
8658         else if (HAS_PCH_LPT(dev))
8659                 lpt_init_pch_refclk(dev);
8660 }
8661
8662 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8663 {
8664         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666         int pipe = intel_crtc->pipe;
8667         uint32_t val;
8668
8669         val = 0;
8670
8671         switch (intel_crtc->config->pipe_bpp) {
8672         case 18:
8673                 val |= PIPECONF_6BPC;
8674                 break;
8675         case 24:
8676                 val |= PIPECONF_8BPC;
8677                 break;
8678         case 30:
8679                 val |= PIPECONF_10BPC;
8680                 break;
8681         case 36:
8682                 val |= PIPECONF_12BPC;
8683                 break;
8684         default:
8685                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8686                 BUG();
8687         }
8688
8689         if (intel_crtc->config->dither)
8690                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8691
8692         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8693                 val |= PIPECONF_INTERLACED_ILK;
8694         else
8695                 val |= PIPECONF_PROGRESSIVE;
8696
8697         if (intel_crtc->config->limited_color_range)
8698                 val |= PIPECONF_COLOR_RANGE_SELECT;
8699
8700         I915_WRITE(PIPECONF(pipe), val);
8701         POSTING_READ(PIPECONF(pipe));
8702 }
8703
8704 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8705 {
8706         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8707         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8708         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8709         u32 val = 0;
8710
8711         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8712                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8713
8714         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8715                 val |= PIPECONF_INTERLACED_ILK;
8716         else
8717                 val |= PIPECONF_PROGRESSIVE;
8718
8719         I915_WRITE(PIPECONF(cpu_transcoder), val);
8720         POSTING_READ(PIPECONF(cpu_transcoder));
8721 }
8722
8723 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8724 {
8725         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8727
8728         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8729                 u32 val = 0;
8730
8731                 switch (intel_crtc->config->pipe_bpp) {
8732                 case 18:
8733                         val |= PIPEMISC_DITHER_6_BPC;
8734                         break;
8735                 case 24:
8736                         val |= PIPEMISC_DITHER_8_BPC;
8737                         break;
8738                 case 30:
8739                         val |= PIPEMISC_DITHER_10_BPC;
8740                         break;
8741                 case 36:
8742                         val |= PIPEMISC_DITHER_12_BPC;
8743                         break;
8744                 default:
8745                         /* Case prevented by pipe_config_set_bpp. */
8746                         BUG();
8747                 }
8748
8749                 if (intel_crtc->config->dither)
8750                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8751
8752                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8753         }
8754 }
8755
8756 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8757 {
8758         /*
8759          * Account for spread spectrum to avoid
8760          * oversubscribing the link. Max center spread
8761          * is 2.5%; use 5% for safety's sake.
8762          */
8763         u32 bps = target_clock * bpp * 21 / 20;
8764         return DIV_ROUND_UP(bps, link_bw * 8);
8765 }
8766
8767 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8768 {
8769         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8770 }
8771
8772 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8773                                   struct intel_crtc_state *crtc_state,
8774                                   intel_clock_t *reduced_clock)
8775 {
8776         struct drm_crtc *crtc = &intel_crtc->base;
8777         struct drm_device *dev = crtc->dev;
8778         struct drm_i915_private *dev_priv = dev->dev_private;
8779         struct drm_atomic_state *state = crtc_state->base.state;
8780         struct drm_connector *connector;
8781         struct drm_connector_state *connector_state;
8782         struct intel_encoder *encoder;
8783         u32 dpll, fp, fp2;
8784         int factor, i;
8785         bool is_lvds = false, is_sdvo = false;
8786
8787         for_each_connector_in_state(state, connector, connector_state, i) {
8788                 if (connector_state->crtc != crtc_state->base.crtc)
8789                         continue;
8790
8791                 encoder = to_intel_encoder(connector_state->best_encoder);
8792
8793                 switch (encoder->type) {
8794                 case INTEL_OUTPUT_LVDS:
8795                         is_lvds = true;
8796                         break;
8797                 case INTEL_OUTPUT_SDVO:
8798                 case INTEL_OUTPUT_HDMI:
8799                         is_sdvo = true;
8800                         break;
8801                 default:
8802                         break;
8803                 }
8804         }
8805
8806         /* Enable autotuning of the PLL clock (if permissible) */
8807         factor = 21;
8808         if (is_lvds) {
8809                 if ((intel_panel_use_ssc(dev_priv) &&
8810                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8811                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8812                         factor = 25;
8813         } else if (crtc_state->sdvo_tv_clock)
8814                 factor = 20;
8815
8816         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8817
8818         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8819                 fp |= FP_CB_TUNE;
8820
8821         if (reduced_clock) {
8822                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8823
8824                 if (reduced_clock->m < factor * reduced_clock->n)
8825                         fp2 |= FP_CB_TUNE;
8826         } else {
8827                 fp2 = fp;
8828         }
8829
8830         dpll = 0;
8831
8832         if (is_lvds)
8833                 dpll |= DPLLB_MODE_LVDS;
8834         else
8835                 dpll |= DPLLB_MODE_DAC_SERIAL;
8836
8837         dpll |= (crtc_state->pixel_multiplier - 1)
8838                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8839
8840         if (is_sdvo)
8841                 dpll |= DPLL_SDVO_HIGH_SPEED;
8842         if (crtc_state->has_dp_encoder)
8843                 dpll |= DPLL_SDVO_HIGH_SPEED;
8844
8845         /* compute bitmask from p1 value */
8846         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8847         /* also FPA1 */
8848         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8849
8850         switch (crtc_state->dpll.p2) {
8851         case 5:
8852                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8853                 break;
8854         case 7:
8855                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8856                 break;
8857         case 10:
8858                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8859                 break;
8860         case 14:
8861                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8862                 break;
8863         }
8864
8865         if (is_lvds && intel_panel_use_ssc(dev_priv))
8866                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8867         else
8868                 dpll |= PLL_REF_INPUT_DREFCLK;
8869
8870         dpll |= DPLL_VCO_ENABLE;
8871
8872         crtc_state->dpll_hw_state.dpll = dpll;
8873         crtc_state->dpll_hw_state.fp0 = fp;
8874         crtc_state->dpll_hw_state.fp1 = fp2;
8875 }
8876
8877 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8878                                        struct intel_crtc_state *crtc_state)
8879 {
8880         struct drm_device *dev = crtc->base.dev;
8881         struct drm_i915_private *dev_priv = dev->dev_private;
8882         intel_clock_t reduced_clock;
8883         bool has_reduced_clock = false;
8884         struct intel_shared_dpll *pll;
8885         const intel_limit_t *limit;
8886         int refclk = 120000;
8887
8888         memset(&crtc_state->dpll_hw_state, 0,
8889                sizeof(crtc_state->dpll_hw_state));
8890
8891         crtc->lowfreq_avail = false;
8892
8893         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8894         if (!crtc_state->has_pch_encoder)
8895                 return 0;
8896
8897         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8898                 if (intel_panel_use_ssc(dev_priv)) {
8899                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8900                                       dev_priv->vbt.lvds_ssc_freq);
8901                         refclk = dev_priv->vbt.lvds_ssc_freq;
8902                 }
8903
8904                 if (intel_is_dual_link_lvds(dev)) {
8905                         if (refclk == 100000)
8906                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8907                         else
8908                                 limit = &intel_limits_ironlake_dual_lvds;
8909                 } else {
8910                         if (refclk == 100000)
8911                                 limit = &intel_limits_ironlake_single_lvds_100m;
8912                         else
8913                                 limit = &intel_limits_ironlake_single_lvds;
8914                 }
8915         } else {
8916                 limit = &intel_limits_ironlake_dac;
8917         }
8918
8919         if (!crtc_state->clock_set &&
8920             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8921                                 refclk, NULL, &crtc_state->dpll)) {
8922                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8923                 return -EINVAL;
8924         }
8925
8926         ironlake_compute_dpll(crtc, crtc_state,
8927                               has_reduced_clock ? &reduced_clock : NULL);
8928
8929         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8930         if (pll == NULL) {
8931                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8932                                  pipe_name(crtc->pipe));
8933                 return -EINVAL;
8934         }
8935
8936         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8937             has_reduced_clock)
8938                 crtc->lowfreq_avail = true;
8939
8940         return 0;
8941 }
8942
8943 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8944                                          struct intel_link_m_n *m_n)
8945 {
8946         struct drm_device *dev = crtc->base.dev;
8947         struct drm_i915_private *dev_priv = dev->dev_private;
8948         enum pipe pipe = crtc->pipe;
8949
8950         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8951         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8952         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8953                 & ~TU_SIZE_MASK;
8954         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8955         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8956                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8957 }
8958
8959 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8960                                          enum transcoder transcoder,
8961                                          struct intel_link_m_n *m_n,
8962                                          struct intel_link_m_n *m2_n2)
8963 {
8964         struct drm_device *dev = crtc->base.dev;
8965         struct drm_i915_private *dev_priv = dev->dev_private;
8966         enum pipe pipe = crtc->pipe;
8967
8968         if (INTEL_INFO(dev)->gen >= 5) {
8969                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8970                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8971                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8972                         & ~TU_SIZE_MASK;
8973                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8974                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8975                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8976                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8977                  * gen < 8) and if DRRS is supported (to make sure the
8978                  * registers are not unnecessarily read).
8979                  */
8980                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8981                         crtc->config->has_drrs) {
8982                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8983                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8984                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8985                                         & ~TU_SIZE_MASK;
8986                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8987                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8988                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8989                 }
8990         } else {
8991                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8992                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8993                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8994                         & ~TU_SIZE_MASK;
8995                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8996                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8997                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8998         }
8999 }
9000
9001 void intel_dp_get_m_n(struct intel_crtc *crtc,
9002                       struct intel_crtc_state *pipe_config)
9003 {
9004         if (pipe_config->has_pch_encoder)
9005                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9006         else
9007                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9008                                              &pipe_config->dp_m_n,
9009                                              &pipe_config->dp_m2_n2);
9010 }
9011
9012 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9013                                         struct intel_crtc_state *pipe_config)
9014 {
9015         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9016                                      &pipe_config->fdi_m_n, NULL);
9017 }
9018
9019 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9020                                     struct intel_crtc_state *pipe_config)
9021 {
9022         struct drm_device *dev = crtc->base.dev;
9023         struct drm_i915_private *dev_priv = dev->dev_private;
9024         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9025         uint32_t ps_ctrl = 0;
9026         int id = -1;
9027         int i;
9028
9029         /* find scaler attached to this pipe */
9030         for (i = 0; i < crtc->num_scalers; i++) {
9031                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9032                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9033                         id = i;
9034                         pipe_config->pch_pfit.enabled = true;
9035                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9036                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9037                         break;
9038                 }
9039         }
9040
9041         scaler_state->scaler_id = id;
9042         if (id >= 0) {
9043                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9044         } else {
9045                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9046         }
9047 }
9048
9049 static void
9050 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9051                                  struct intel_initial_plane_config *plane_config)
9052 {
9053         struct drm_device *dev = crtc->base.dev;
9054         struct drm_i915_private *dev_priv = dev->dev_private;
9055         u32 val, base, offset, stride_mult, tiling;
9056         int pipe = crtc->pipe;
9057         int fourcc, pixel_format;
9058         unsigned int aligned_height;
9059         struct drm_framebuffer *fb;
9060         struct intel_framebuffer *intel_fb;
9061
9062         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9063         if (!intel_fb) {
9064                 DRM_DEBUG_KMS("failed to alloc fb\n");
9065                 return;
9066         }
9067
9068         fb = &intel_fb->base;
9069
9070         val = I915_READ(PLANE_CTL(pipe, 0));
9071         if (!(val & PLANE_CTL_ENABLE))
9072                 goto error;
9073
9074         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9075         fourcc = skl_format_to_fourcc(pixel_format,
9076                                       val & PLANE_CTL_ORDER_RGBX,
9077                                       val & PLANE_CTL_ALPHA_MASK);
9078         fb->pixel_format = fourcc;
9079         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9080
9081         tiling = val & PLANE_CTL_TILED_MASK;
9082         switch (tiling) {
9083         case PLANE_CTL_TILED_LINEAR:
9084                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9085                 break;
9086         case PLANE_CTL_TILED_X:
9087                 plane_config->tiling = I915_TILING_X;
9088                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9089                 break;
9090         case PLANE_CTL_TILED_Y:
9091                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9092                 break;
9093         case PLANE_CTL_TILED_YF:
9094                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9095                 break;
9096         default:
9097                 MISSING_CASE(tiling);
9098                 goto error;
9099         }
9100
9101         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9102         plane_config->base = base;
9103
9104         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9105
9106         val = I915_READ(PLANE_SIZE(pipe, 0));
9107         fb->height = ((val >> 16) & 0xfff) + 1;
9108         fb->width = ((val >> 0) & 0x1fff) + 1;
9109
9110         val = I915_READ(PLANE_STRIDE(pipe, 0));
9111         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9112                                                 fb->pixel_format);
9113         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9114
9115         aligned_height = intel_fb_align_height(dev, fb->height,
9116                                                fb->pixel_format,
9117                                                fb->modifier[0]);
9118
9119         plane_config->size = fb->pitches[0] * aligned_height;
9120
9121         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9122                       pipe_name(pipe), fb->width, fb->height,
9123                       fb->bits_per_pixel, base, fb->pitches[0],
9124                       plane_config->size);
9125
9126         plane_config->fb = intel_fb;
9127         return;
9128
9129 error:
9130         kfree(fb);
9131 }
9132
9133 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9134                                      struct intel_crtc_state *pipe_config)
9135 {
9136         struct drm_device *dev = crtc->base.dev;
9137         struct drm_i915_private *dev_priv = dev->dev_private;
9138         uint32_t tmp;
9139
9140         tmp = I915_READ(PF_CTL(crtc->pipe));
9141
9142         if (tmp & PF_ENABLE) {
9143                 pipe_config->pch_pfit.enabled = true;
9144                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9145                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9146
9147                 /* We currently do not free assignements of panel fitters on
9148                  * ivb/hsw (since we don't use the higher upscaling modes which
9149                  * differentiates them) so just WARN about this case for now. */
9150                 if (IS_GEN7(dev)) {
9151                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9152                                 PF_PIPE_SEL_IVB(crtc->pipe));
9153                 }
9154         }
9155 }
9156
9157 static void
9158 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9159                                   struct intel_initial_plane_config *plane_config)
9160 {
9161         struct drm_device *dev = crtc->base.dev;
9162         struct drm_i915_private *dev_priv = dev->dev_private;
9163         u32 val, base, offset;
9164         int pipe = crtc->pipe;
9165         int fourcc, pixel_format;
9166         unsigned int aligned_height;
9167         struct drm_framebuffer *fb;
9168         struct intel_framebuffer *intel_fb;
9169
9170         val = I915_READ(DSPCNTR(pipe));
9171         if (!(val & DISPLAY_PLANE_ENABLE))
9172                 return;
9173
9174         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9175         if (!intel_fb) {
9176                 DRM_DEBUG_KMS("failed to alloc fb\n");
9177                 return;
9178         }
9179
9180         fb = &intel_fb->base;
9181
9182         if (INTEL_INFO(dev)->gen >= 4) {
9183                 if (val & DISPPLANE_TILED) {
9184                         plane_config->tiling = I915_TILING_X;
9185                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9186                 }
9187         }
9188
9189         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9190         fourcc = i9xx_format_to_fourcc(pixel_format);
9191         fb->pixel_format = fourcc;
9192         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9193
9194         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9195         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9196                 offset = I915_READ(DSPOFFSET(pipe));
9197         } else {
9198                 if (plane_config->tiling)
9199                         offset = I915_READ(DSPTILEOFF(pipe));
9200                 else
9201                         offset = I915_READ(DSPLINOFF(pipe));
9202         }
9203         plane_config->base = base;
9204
9205         val = I915_READ(PIPESRC(pipe));
9206         fb->width = ((val >> 16) & 0xfff) + 1;
9207         fb->height = ((val >> 0) & 0xfff) + 1;
9208
9209         val = I915_READ(DSPSTRIDE(pipe));
9210         fb->pitches[0] = val & 0xffffffc0;
9211
9212         aligned_height = intel_fb_align_height(dev, fb->height,
9213                                                fb->pixel_format,
9214                                                fb->modifier[0]);
9215
9216         plane_config->size = fb->pitches[0] * aligned_height;
9217
9218         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9219                       pipe_name(pipe), fb->width, fb->height,
9220                       fb->bits_per_pixel, base, fb->pitches[0],
9221                       plane_config->size);
9222
9223         plane_config->fb = intel_fb;
9224 }
9225
9226 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9227                                      struct intel_crtc_state *pipe_config)
9228 {
9229         struct drm_device *dev = crtc->base.dev;
9230         struct drm_i915_private *dev_priv = dev->dev_private;
9231         enum intel_display_power_domain power_domain;
9232         uint32_t tmp;
9233         bool ret;
9234
9235         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9236         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9237                 return false;
9238
9239         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9240         pipe_config->shared_dpll = NULL;
9241
9242         ret = false;
9243         tmp = I915_READ(PIPECONF(crtc->pipe));
9244         if (!(tmp & PIPECONF_ENABLE))
9245                 goto out;
9246
9247         switch (tmp & PIPECONF_BPC_MASK) {
9248         case PIPECONF_6BPC:
9249                 pipe_config->pipe_bpp = 18;
9250                 break;
9251         case PIPECONF_8BPC:
9252                 pipe_config->pipe_bpp = 24;
9253                 break;
9254         case PIPECONF_10BPC:
9255                 pipe_config->pipe_bpp = 30;
9256                 break;
9257         case PIPECONF_12BPC:
9258                 pipe_config->pipe_bpp = 36;
9259                 break;
9260         default:
9261                 break;
9262         }
9263
9264         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9265                 pipe_config->limited_color_range = true;
9266
9267         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9268                 struct intel_shared_dpll *pll;
9269                 enum intel_dpll_id pll_id;
9270
9271                 pipe_config->has_pch_encoder = true;
9272
9273                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9274                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9275                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9276
9277                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9278
9279                 if (HAS_PCH_IBX(dev_priv)) {
9280                         pll_id = (enum intel_dpll_id) crtc->pipe;
9281                 } else {
9282                         tmp = I915_READ(PCH_DPLL_SEL);
9283                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9284                                 pll_id = DPLL_ID_PCH_PLL_B;
9285                         else
9286                                 pll_id= DPLL_ID_PCH_PLL_A;
9287                 }
9288
9289                 pipe_config->shared_dpll =
9290                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9291                 pll = pipe_config->shared_dpll;
9292
9293                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9294                                                  &pipe_config->dpll_hw_state));
9295
9296                 tmp = pipe_config->dpll_hw_state.dpll;
9297                 pipe_config->pixel_multiplier =
9298                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9299                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9300
9301                 ironlake_pch_clock_get(crtc, pipe_config);
9302         } else {
9303                 pipe_config->pixel_multiplier = 1;
9304         }
9305
9306         intel_get_pipe_timings(crtc, pipe_config);
9307         intel_get_pipe_src_size(crtc, pipe_config);
9308
9309         ironlake_get_pfit_config(crtc, pipe_config);
9310
9311         ret = true;
9312
9313 out:
9314         intel_display_power_put(dev_priv, power_domain);
9315
9316         return ret;
9317 }
9318
9319 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9320 {
9321         struct drm_device *dev = dev_priv->dev;
9322         struct intel_crtc *crtc;
9323
9324         for_each_intel_crtc(dev, crtc)
9325                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9326                      pipe_name(crtc->pipe));
9327
9328         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9329         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9330         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9331         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9332         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9333         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9334              "CPU PWM1 enabled\n");
9335         if (IS_HASWELL(dev))
9336                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9337                      "CPU PWM2 enabled\n");
9338         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9339              "PCH PWM1 enabled\n");
9340         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9341              "Utility pin enabled\n");
9342         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9343
9344         /*
9345          * In theory we can still leave IRQs enabled, as long as only the HPD
9346          * interrupts remain enabled. We used to check for that, but since it's
9347          * gen-specific and since we only disable LCPLL after we fully disable
9348          * the interrupts, the check below should be enough.
9349          */
9350         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9351 }
9352
9353 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9354 {
9355         struct drm_device *dev = dev_priv->dev;
9356
9357         if (IS_HASWELL(dev))
9358                 return I915_READ(D_COMP_HSW);
9359         else
9360                 return I915_READ(D_COMP_BDW);
9361 }
9362
9363 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9364 {
9365         struct drm_device *dev = dev_priv->dev;
9366
9367         if (IS_HASWELL(dev)) {
9368                 mutex_lock(&dev_priv->rps.hw_lock);
9369                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9370                                             val))
9371                         DRM_ERROR("Failed to write to D_COMP\n");
9372                 mutex_unlock(&dev_priv->rps.hw_lock);
9373         } else {
9374                 I915_WRITE(D_COMP_BDW, val);
9375                 POSTING_READ(D_COMP_BDW);
9376         }
9377 }
9378
9379 /*
9380  * This function implements pieces of two sequences from BSpec:
9381  * - Sequence for display software to disable LCPLL
9382  * - Sequence for display software to allow package C8+
9383  * The steps implemented here are just the steps that actually touch the LCPLL
9384  * register. Callers should take care of disabling all the display engine
9385  * functions, doing the mode unset, fixing interrupts, etc.
9386  */
9387 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9388                               bool switch_to_fclk, bool allow_power_down)
9389 {
9390         uint32_t val;
9391
9392         assert_can_disable_lcpll(dev_priv);
9393
9394         val = I915_READ(LCPLL_CTL);
9395
9396         if (switch_to_fclk) {
9397                 val |= LCPLL_CD_SOURCE_FCLK;
9398                 I915_WRITE(LCPLL_CTL, val);
9399
9400                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9401                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9402                         DRM_ERROR("Switching to FCLK failed\n");
9403
9404                 val = I915_READ(LCPLL_CTL);
9405         }
9406
9407         val |= LCPLL_PLL_DISABLE;
9408         I915_WRITE(LCPLL_CTL, val);
9409         POSTING_READ(LCPLL_CTL);
9410
9411         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9412                 DRM_ERROR("LCPLL still locked\n");
9413
9414         val = hsw_read_dcomp(dev_priv);
9415         val |= D_COMP_COMP_DISABLE;
9416         hsw_write_dcomp(dev_priv, val);
9417         ndelay(100);
9418
9419         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9420                      1))
9421                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9422
9423         if (allow_power_down) {
9424                 val = I915_READ(LCPLL_CTL);
9425                 val |= LCPLL_POWER_DOWN_ALLOW;
9426                 I915_WRITE(LCPLL_CTL, val);
9427                 POSTING_READ(LCPLL_CTL);
9428         }
9429 }
9430
9431 /*
9432  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9433  * source.
9434  */
9435 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9436 {
9437         uint32_t val;
9438
9439         val = I915_READ(LCPLL_CTL);
9440
9441         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9442                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9443                 return;
9444
9445         /*
9446          * Make sure we're not on PC8 state before disabling PC8, otherwise
9447          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9448          */
9449         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9450
9451         if (val & LCPLL_POWER_DOWN_ALLOW) {
9452                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9453                 I915_WRITE(LCPLL_CTL, val);
9454                 POSTING_READ(LCPLL_CTL);
9455         }
9456
9457         val = hsw_read_dcomp(dev_priv);
9458         val |= D_COMP_COMP_FORCE;
9459         val &= ~D_COMP_COMP_DISABLE;
9460         hsw_write_dcomp(dev_priv, val);
9461
9462         val = I915_READ(LCPLL_CTL);
9463         val &= ~LCPLL_PLL_DISABLE;
9464         I915_WRITE(LCPLL_CTL, val);
9465
9466         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9467                 DRM_ERROR("LCPLL not locked yet\n");
9468
9469         if (val & LCPLL_CD_SOURCE_FCLK) {
9470                 val = I915_READ(LCPLL_CTL);
9471                 val &= ~LCPLL_CD_SOURCE_FCLK;
9472                 I915_WRITE(LCPLL_CTL, val);
9473
9474                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9475                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9476                         DRM_ERROR("Switching back to LCPLL failed\n");
9477         }
9478
9479         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9480         intel_update_cdclk(dev_priv->dev);
9481 }
9482
9483 /*
9484  * Package states C8 and deeper are really deep PC states that can only be
9485  * reached when all the devices on the system allow it, so even if the graphics
9486  * device allows PC8+, it doesn't mean the system will actually get to these
9487  * states. Our driver only allows PC8+ when going into runtime PM.
9488  *
9489  * The requirements for PC8+ are that all the outputs are disabled, the power
9490  * well is disabled and most interrupts are disabled, and these are also
9491  * requirements for runtime PM. When these conditions are met, we manually do
9492  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9493  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9494  * hang the machine.
9495  *
9496  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9497  * the state of some registers, so when we come back from PC8+ we need to
9498  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9499  * need to take care of the registers kept by RC6. Notice that this happens even
9500  * if we don't put the device in PCI D3 state (which is what currently happens
9501  * because of the runtime PM support).
9502  *
9503  * For more, read "Display Sequences for Package C8" on the hardware
9504  * documentation.
9505  */
9506 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9507 {
9508         struct drm_device *dev = dev_priv->dev;
9509         uint32_t val;
9510
9511         DRM_DEBUG_KMS("Enabling package C8+\n");
9512
9513         if (HAS_PCH_LPT_LP(dev)) {
9514                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9515                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9516                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9517         }
9518
9519         lpt_disable_clkout_dp(dev);
9520         hsw_disable_lcpll(dev_priv, true, true);
9521 }
9522
9523 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9524 {
9525         struct drm_device *dev = dev_priv->dev;
9526         uint32_t val;
9527
9528         DRM_DEBUG_KMS("Disabling package C8+\n");
9529
9530         hsw_restore_lcpll(dev_priv);
9531         lpt_init_pch_refclk(dev);
9532
9533         if (HAS_PCH_LPT_LP(dev)) {
9534                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9535                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9536                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9537         }
9538 }
9539
9540 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9541 {
9542         struct drm_device *dev = old_state->dev;
9543         struct intel_atomic_state *old_intel_state =
9544                 to_intel_atomic_state(old_state);
9545         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9546
9547         broxton_set_cdclk(to_i915(dev), req_cdclk);
9548 }
9549
9550 /* compute the max rate for new configuration */
9551 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9552 {
9553         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9554         struct drm_i915_private *dev_priv = state->dev->dev_private;
9555         struct drm_crtc *crtc;
9556         struct drm_crtc_state *cstate;
9557         struct intel_crtc_state *crtc_state;
9558         unsigned max_pixel_rate = 0, i;
9559         enum pipe pipe;
9560
9561         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9562                sizeof(intel_state->min_pixclk));
9563
9564         for_each_crtc_in_state(state, crtc, cstate, i) {
9565                 int pixel_rate;
9566
9567                 crtc_state = to_intel_crtc_state(cstate);
9568                 if (!crtc_state->base.enable) {
9569                         intel_state->min_pixclk[i] = 0;
9570                         continue;
9571                 }
9572
9573                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9574
9575                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9576                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9577                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9578
9579                 intel_state->min_pixclk[i] = pixel_rate;
9580         }
9581
9582         for_each_pipe(dev_priv, pipe)
9583                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9584
9585         return max_pixel_rate;
9586 }
9587
9588 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9589 {
9590         struct drm_i915_private *dev_priv = dev->dev_private;
9591         uint32_t val, data;
9592         int ret;
9593
9594         if (WARN((I915_READ(LCPLL_CTL) &
9595                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9596                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9597                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9598                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9599                  "trying to change cdclk frequency with cdclk not enabled\n"))
9600                 return;
9601
9602         mutex_lock(&dev_priv->rps.hw_lock);
9603         ret = sandybridge_pcode_write(dev_priv,
9604                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9605         mutex_unlock(&dev_priv->rps.hw_lock);
9606         if (ret) {
9607                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9608                 return;
9609         }
9610
9611         val = I915_READ(LCPLL_CTL);
9612         val |= LCPLL_CD_SOURCE_FCLK;
9613         I915_WRITE(LCPLL_CTL, val);
9614
9615         if (wait_for_us(I915_READ(LCPLL_CTL) &
9616                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9617                 DRM_ERROR("Switching to FCLK failed\n");
9618
9619         val = I915_READ(LCPLL_CTL);
9620         val &= ~LCPLL_CLK_FREQ_MASK;
9621
9622         switch (cdclk) {
9623         case 450000:
9624                 val |= LCPLL_CLK_FREQ_450;
9625                 data = 0;
9626                 break;
9627         case 540000:
9628                 val |= LCPLL_CLK_FREQ_54O_BDW;
9629                 data = 1;
9630                 break;
9631         case 337500:
9632                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9633                 data = 2;
9634                 break;
9635         case 675000:
9636                 val |= LCPLL_CLK_FREQ_675_BDW;
9637                 data = 3;
9638                 break;
9639         default:
9640                 WARN(1, "invalid cdclk frequency\n");
9641                 return;
9642         }
9643
9644         I915_WRITE(LCPLL_CTL, val);
9645
9646         val = I915_READ(LCPLL_CTL);
9647         val &= ~LCPLL_CD_SOURCE_FCLK;
9648         I915_WRITE(LCPLL_CTL, val);
9649
9650         if (wait_for_us((I915_READ(LCPLL_CTL) &
9651                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9652                 DRM_ERROR("Switching back to LCPLL failed\n");
9653
9654         mutex_lock(&dev_priv->rps.hw_lock);
9655         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9656         mutex_unlock(&dev_priv->rps.hw_lock);
9657
9658         intel_update_cdclk(dev);
9659
9660         WARN(cdclk != dev_priv->cdclk_freq,
9661              "cdclk requested %d kHz but got %d kHz\n",
9662              cdclk, dev_priv->cdclk_freq);
9663 }
9664
9665 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9666 {
9667         struct drm_i915_private *dev_priv = to_i915(state->dev);
9668         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9669         int max_pixclk = ilk_max_pixel_rate(state);
9670         int cdclk;
9671
9672         /*
9673          * FIXME should also account for plane ratio
9674          * once 64bpp pixel formats are supported.
9675          */
9676         if (max_pixclk > 540000)
9677                 cdclk = 675000;
9678         else if (max_pixclk > 450000)
9679                 cdclk = 540000;
9680         else if (max_pixclk > 337500)
9681                 cdclk = 450000;
9682         else
9683                 cdclk = 337500;
9684
9685         if (cdclk > dev_priv->max_cdclk_freq) {
9686                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9687                               cdclk, dev_priv->max_cdclk_freq);
9688                 return -EINVAL;
9689         }
9690
9691         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9692         if (!intel_state->active_crtcs)
9693                 intel_state->dev_cdclk = 337500;
9694
9695         return 0;
9696 }
9697
9698 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9699 {
9700         struct drm_device *dev = old_state->dev;
9701         struct intel_atomic_state *old_intel_state =
9702                 to_intel_atomic_state(old_state);
9703         unsigned req_cdclk = old_intel_state->dev_cdclk;
9704
9705         broadwell_set_cdclk(dev, req_cdclk);
9706 }
9707
9708 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9709                                       struct intel_crtc_state *crtc_state)
9710 {
9711         struct intel_encoder *intel_encoder =
9712                 intel_ddi_get_crtc_new_encoder(crtc_state);
9713
9714         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9715                 if (!intel_ddi_pll_select(crtc, crtc_state))
9716                         return -EINVAL;
9717         }
9718
9719         crtc->lowfreq_avail = false;
9720
9721         return 0;
9722 }
9723
9724 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9725                                 enum port port,
9726                                 struct intel_crtc_state *pipe_config)
9727 {
9728         enum intel_dpll_id id;
9729
9730         switch (port) {
9731         case PORT_A:
9732                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9733                 id = DPLL_ID_SKL_DPLL0;
9734                 break;
9735         case PORT_B:
9736                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9737                 id = DPLL_ID_SKL_DPLL1;
9738                 break;
9739         case PORT_C:
9740                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9741                 id = DPLL_ID_SKL_DPLL2;
9742                 break;
9743         default:
9744                 DRM_ERROR("Incorrect port type\n");
9745                 return;
9746         }
9747
9748         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9749 }
9750
9751 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9752                                 enum port port,
9753                                 struct intel_crtc_state *pipe_config)
9754 {
9755         enum intel_dpll_id id;
9756         u32 temp;
9757
9758         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9759         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9760
9761         switch (pipe_config->ddi_pll_sel) {
9762         case SKL_DPLL0:
9763                 id = DPLL_ID_SKL_DPLL0;
9764                 break;
9765         case SKL_DPLL1:
9766                 id = DPLL_ID_SKL_DPLL1;
9767                 break;
9768         case SKL_DPLL2:
9769                 id = DPLL_ID_SKL_DPLL2;
9770                 break;
9771         case SKL_DPLL3:
9772                 id = DPLL_ID_SKL_DPLL3;
9773                 break;
9774         default:
9775                 MISSING_CASE(pipe_config->ddi_pll_sel);
9776                 return;
9777         }
9778
9779         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9780 }
9781
9782 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9783                                 enum port port,
9784                                 struct intel_crtc_state *pipe_config)
9785 {
9786         enum intel_dpll_id id;
9787
9788         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9789
9790         switch (pipe_config->ddi_pll_sel) {
9791         case PORT_CLK_SEL_WRPLL1:
9792                 id = DPLL_ID_WRPLL1;
9793                 break;
9794         case PORT_CLK_SEL_WRPLL2:
9795                 id = DPLL_ID_WRPLL2;
9796                 break;
9797         case PORT_CLK_SEL_SPLL:
9798                 id = DPLL_ID_SPLL;
9799                 break;
9800         case PORT_CLK_SEL_LCPLL_810:
9801                 id = DPLL_ID_LCPLL_810;
9802                 break;
9803         case PORT_CLK_SEL_LCPLL_1350:
9804                 id = DPLL_ID_LCPLL_1350;
9805                 break;
9806         case PORT_CLK_SEL_LCPLL_2700:
9807                 id = DPLL_ID_LCPLL_2700;
9808                 break;
9809         default:
9810                 MISSING_CASE(pipe_config->ddi_pll_sel);
9811                 /* fall through */
9812         case PORT_CLK_SEL_NONE:
9813                 return;
9814         }
9815
9816         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9817 }
9818
9819 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9820                                      struct intel_crtc_state *pipe_config,
9821                                      unsigned long *power_domain_mask)
9822 {
9823         struct drm_device *dev = crtc->base.dev;
9824         struct drm_i915_private *dev_priv = dev->dev_private;
9825         enum intel_display_power_domain power_domain;
9826         u32 tmp;
9827
9828         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9829
9830         /*
9831          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9832          * consistency and less surprising code; it's in always on power).
9833          */
9834         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9835         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9836                 enum pipe trans_edp_pipe;
9837                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9838                 default:
9839                         WARN(1, "unknown pipe linked to edp transcoder\n");
9840                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9841                 case TRANS_DDI_EDP_INPUT_A_ON:
9842                         trans_edp_pipe = PIPE_A;
9843                         break;
9844                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9845                         trans_edp_pipe = PIPE_B;
9846                         break;
9847                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9848                         trans_edp_pipe = PIPE_C;
9849                         break;
9850                 }
9851
9852                 if (trans_edp_pipe == crtc->pipe)
9853                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9854         }
9855
9856         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9857         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9858                 return false;
9859         *power_domain_mask |= BIT(power_domain);
9860
9861         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9862
9863         return tmp & PIPECONF_ENABLE;
9864 }
9865
9866 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9867                                          struct intel_crtc_state *pipe_config,
9868                                          unsigned long *power_domain_mask)
9869 {
9870         struct drm_device *dev = crtc->base.dev;
9871         struct drm_i915_private *dev_priv = dev->dev_private;
9872         enum intel_display_power_domain power_domain;
9873         enum port port;
9874         enum transcoder cpu_transcoder;
9875         u32 tmp;
9876
9877         pipe_config->has_dsi_encoder = false;
9878
9879         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9880                 if (port == PORT_A)
9881                         cpu_transcoder = TRANSCODER_DSI_A;
9882                 else
9883                         cpu_transcoder = TRANSCODER_DSI_C;
9884
9885                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9886                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9887                         continue;
9888                 *power_domain_mask |= BIT(power_domain);
9889
9890                 /*
9891                  * The PLL needs to be enabled with a valid divider
9892                  * configuration, otherwise accessing DSI registers will hang
9893                  * the machine. See BSpec North Display Engine
9894                  * registers/MIPI[BXT]. We can break out here early, since we
9895                  * need the same DSI PLL to be enabled for both DSI ports.
9896                  */
9897                 if (!intel_dsi_pll_is_enabled(dev_priv))
9898                         break;
9899
9900                 /* XXX: this works for video mode only */
9901                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9902                 if (!(tmp & DPI_ENABLE))
9903                         continue;
9904
9905                 tmp = I915_READ(MIPI_CTRL(port));
9906                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9907                         continue;
9908
9909                 pipe_config->cpu_transcoder = cpu_transcoder;
9910                 pipe_config->has_dsi_encoder = true;
9911                 break;
9912         }
9913
9914         return pipe_config->has_dsi_encoder;
9915 }
9916
9917 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9918                                        struct intel_crtc_state *pipe_config)
9919 {
9920         struct drm_device *dev = crtc->base.dev;
9921         struct drm_i915_private *dev_priv = dev->dev_private;
9922         struct intel_shared_dpll *pll;
9923         enum port port;
9924         uint32_t tmp;
9925
9926         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9927
9928         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9929
9930         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9931                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9932         else if (IS_BROXTON(dev))
9933                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9934         else
9935                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9936
9937         pll = pipe_config->shared_dpll;
9938         if (pll) {
9939                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9940                                                  &pipe_config->dpll_hw_state));
9941         }
9942
9943         /*
9944          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9945          * DDI E. So just check whether this pipe is wired to DDI E and whether
9946          * the PCH transcoder is on.
9947          */
9948         if (INTEL_INFO(dev)->gen < 9 &&
9949             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9950                 pipe_config->has_pch_encoder = true;
9951
9952                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9953                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9954                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9955
9956                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9957         }
9958 }
9959
9960 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9961                                     struct intel_crtc_state *pipe_config)
9962 {
9963         struct drm_device *dev = crtc->base.dev;
9964         struct drm_i915_private *dev_priv = dev->dev_private;
9965         enum intel_display_power_domain power_domain;
9966         unsigned long power_domain_mask;
9967         bool active;
9968
9969         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9970         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9971                 return false;
9972         power_domain_mask = BIT(power_domain);
9973
9974         pipe_config->shared_dpll = NULL;
9975
9976         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9977
9978         if (IS_BROXTON(dev_priv)) {
9979                 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9980                                              &power_domain_mask);
9981                 WARN_ON(active && pipe_config->has_dsi_encoder);
9982                 if (pipe_config->has_dsi_encoder)
9983                         active = true;
9984         }
9985
9986         if (!active)
9987                 goto out;
9988
9989         if (!pipe_config->has_dsi_encoder) {
9990                 haswell_get_ddi_port_state(crtc, pipe_config);
9991                 intel_get_pipe_timings(crtc, pipe_config);
9992         }
9993
9994         intel_get_pipe_src_size(crtc, pipe_config);
9995
9996         pipe_config->gamma_mode =
9997                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9998
9999         if (INTEL_INFO(dev)->gen >= 9) {
10000                 skl_init_scalers(dev, crtc, pipe_config);
10001         }
10002
10003         if (INTEL_INFO(dev)->gen >= 9) {
10004                 pipe_config->scaler_state.scaler_id = -1;
10005                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10006         }
10007
10008         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10009         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10010                 power_domain_mask |= BIT(power_domain);
10011                 if (INTEL_INFO(dev)->gen >= 9)
10012                         skylake_get_pfit_config(crtc, pipe_config);
10013                 else
10014                         ironlake_get_pfit_config(crtc, pipe_config);
10015         }
10016
10017         if (IS_HASWELL(dev))
10018                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10019                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10020
10021         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10022             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10023                 pipe_config->pixel_multiplier =
10024                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10025         } else {
10026                 pipe_config->pixel_multiplier = 1;
10027         }
10028
10029 out:
10030         for_each_power_domain(power_domain, power_domain_mask)
10031                 intel_display_power_put(dev_priv, power_domain);
10032
10033         return active;
10034 }
10035
10036 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10037                                const struct intel_plane_state *plane_state)
10038 {
10039         struct drm_device *dev = crtc->dev;
10040         struct drm_i915_private *dev_priv = dev->dev_private;
10041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10042         uint32_t cntl = 0, size = 0;
10043
10044         if (plane_state && plane_state->visible) {
10045                 unsigned int width = plane_state->base.crtc_w;
10046                 unsigned int height = plane_state->base.crtc_h;
10047                 unsigned int stride = roundup_pow_of_two(width) * 4;
10048
10049                 switch (stride) {
10050                 default:
10051                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10052                                   width, stride);
10053                         stride = 256;
10054                         /* fallthrough */
10055                 case 256:
10056                 case 512:
10057                 case 1024:
10058                 case 2048:
10059                         break;
10060                 }
10061
10062                 cntl |= CURSOR_ENABLE |
10063                         CURSOR_GAMMA_ENABLE |
10064                         CURSOR_FORMAT_ARGB |
10065                         CURSOR_STRIDE(stride);
10066
10067                 size = (height << 12) | width;
10068         }
10069
10070         if (intel_crtc->cursor_cntl != 0 &&
10071             (intel_crtc->cursor_base != base ||
10072              intel_crtc->cursor_size != size ||
10073              intel_crtc->cursor_cntl != cntl)) {
10074                 /* On these chipsets we can only modify the base/size/stride
10075                  * whilst the cursor is disabled.
10076                  */
10077                 I915_WRITE(CURCNTR(PIPE_A), 0);
10078                 POSTING_READ(CURCNTR(PIPE_A));
10079                 intel_crtc->cursor_cntl = 0;
10080         }
10081
10082         if (intel_crtc->cursor_base != base) {
10083                 I915_WRITE(CURBASE(PIPE_A), base);
10084                 intel_crtc->cursor_base = base;
10085         }
10086
10087         if (intel_crtc->cursor_size != size) {
10088                 I915_WRITE(CURSIZE, size);
10089                 intel_crtc->cursor_size = size;
10090         }
10091
10092         if (intel_crtc->cursor_cntl != cntl) {
10093                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10094                 POSTING_READ(CURCNTR(PIPE_A));
10095                 intel_crtc->cursor_cntl = cntl;
10096         }
10097 }
10098
10099 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10100                                const struct intel_plane_state *plane_state)
10101 {
10102         struct drm_device *dev = crtc->dev;
10103         struct drm_i915_private *dev_priv = dev->dev_private;
10104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10105         int pipe = intel_crtc->pipe;
10106         uint32_t cntl = 0;
10107
10108         if (plane_state && plane_state->visible) {
10109                 cntl = MCURSOR_GAMMA_ENABLE;
10110                 switch (plane_state->base.crtc_w) {
10111                         case 64:
10112                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10113                                 break;
10114                         case 128:
10115                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10116                                 break;
10117                         case 256:
10118                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10119                                 break;
10120                         default:
10121                                 MISSING_CASE(plane_state->base.crtc_w);
10122                                 return;
10123                 }
10124                 cntl |= pipe << 28; /* Connect to correct pipe */
10125
10126                 if (HAS_DDI(dev))
10127                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10128
10129                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10130                         cntl |= CURSOR_ROTATE_180;
10131         }
10132
10133         if (intel_crtc->cursor_cntl != cntl) {
10134                 I915_WRITE(CURCNTR(pipe), cntl);
10135                 POSTING_READ(CURCNTR(pipe));
10136                 intel_crtc->cursor_cntl = cntl;
10137         }
10138
10139         /* and commit changes on next vblank */
10140         I915_WRITE(CURBASE(pipe), base);
10141         POSTING_READ(CURBASE(pipe));
10142
10143         intel_crtc->cursor_base = base;
10144 }
10145
10146 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10147 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10148                                      const struct intel_plane_state *plane_state)
10149 {
10150         struct drm_device *dev = crtc->dev;
10151         struct drm_i915_private *dev_priv = dev->dev_private;
10152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10153         int pipe = intel_crtc->pipe;
10154         u32 base = intel_crtc->cursor_addr;
10155         u32 pos = 0;
10156
10157         if (plane_state) {
10158                 int x = plane_state->base.crtc_x;
10159                 int y = plane_state->base.crtc_y;
10160
10161                 if (x < 0) {
10162                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10163                         x = -x;
10164                 }
10165                 pos |= x << CURSOR_X_SHIFT;
10166
10167                 if (y < 0) {
10168                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10169                         y = -y;
10170                 }
10171                 pos |= y << CURSOR_Y_SHIFT;
10172
10173                 /* ILK+ do this automagically */
10174                 if (HAS_GMCH_DISPLAY(dev) &&
10175                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10176                         base += (plane_state->base.crtc_h *
10177                                  plane_state->base.crtc_w - 1) * 4;
10178                 }
10179         }
10180
10181         I915_WRITE(CURPOS(pipe), pos);
10182
10183         if (IS_845G(dev) || IS_I865G(dev))
10184                 i845_update_cursor(crtc, base, plane_state);
10185         else
10186                 i9xx_update_cursor(crtc, base, plane_state);
10187 }
10188
10189 static bool cursor_size_ok(struct drm_device *dev,
10190                            uint32_t width, uint32_t height)
10191 {
10192         if (width == 0 || height == 0)
10193                 return false;
10194
10195         /*
10196          * 845g/865g are special in that they are only limited by
10197          * the width of their cursors, the height is arbitrary up to
10198          * the precision of the register. Everything else requires
10199          * square cursors, limited to a few power-of-two sizes.
10200          */
10201         if (IS_845G(dev) || IS_I865G(dev)) {
10202                 if ((width & 63) != 0)
10203                         return false;
10204
10205                 if (width > (IS_845G(dev) ? 64 : 512))
10206                         return false;
10207
10208                 if (height > 1023)
10209                         return false;
10210         } else {
10211                 switch (width | height) {
10212                 case 256:
10213                 case 128:
10214                         if (IS_GEN2(dev))
10215                                 return false;
10216                 case 64:
10217                         break;
10218                 default:
10219                         return false;
10220                 }
10221         }
10222
10223         return true;
10224 }
10225
10226 /* VESA 640x480x72Hz mode to set on the pipe */
10227 static struct drm_display_mode load_detect_mode = {
10228         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10229                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10230 };
10231
10232 struct drm_framebuffer *
10233 __intel_framebuffer_create(struct drm_device *dev,
10234                            struct drm_mode_fb_cmd2 *mode_cmd,
10235                            struct drm_i915_gem_object *obj)
10236 {
10237         struct intel_framebuffer *intel_fb;
10238         int ret;
10239
10240         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10241         if (!intel_fb)
10242                 return ERR_PTR(-ENOMEM);
10243
10244         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10245         if (ret)
10246                 goto err;
10247
10248         return &intel_fb->base;
10249
10250 err:
10251         kfree(intel_fb);
10252         return ERR_PTR(ret);
10253 }
10254
10255 static struct drm_framebuffer *
10256 intel_framebuffer_create(struct drm_device *dev,
10257                          struct drm_mode_fb_cmd2 *mode_cmd,
10258                          struct drm_i915_gem_object *obj)
10259 {
10260         struct drm_framebuffer *fb;
10261         int ret;
10262
10263         ret = i915_mutex_lock_interruptible(dev);
10264         if (ret)
10265                 return ERR_PTR(ret);
10266         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10267         mutex_unlock(&dev->struct_mutex);
10268
10269         return fb;
10270 }
10271
10272 static u32
10273 intel_framebuffer_pitch_for_width(int width, int bpp)
10274 {
10275         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10276         return ALIGN(pitch, 64);
10277 }
10278
10279 static u32
10280 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10281 {
10282         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10283         return PAGE_ALIGN(pitch * mode->vdisplay);
10284 }
10285
10286 static struct drm_framebuffer *
10287 intel_framebuffer_create_for_mode(struct drm_device *dev,
10288                                   struct drm_display_mode *mode,
10289                                   int depth, int bpp)
10290 {
10291         struct drm_framebuffer *fb;
10292         struct drm_i915_gem_object *obj;
10293         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10294
10295         obj = i915_gem_alloc_object(dev,
10296                                     intel_framebuffer_size_for_mode(mode, bpp));
10297         if (obj == NULL)
10298                 return ERR_PTR(-ENOMEM);
10299
10300         mode_cmd.width = mode->hdisplay;
10301         mode_cmd.height = mode->vdisplay;
10302         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10303                                                                 bpp);
10304         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10305
10306         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10307         if (IS_ERR(fb))
10308                 drm_gem_object_unreference_unlocked(&obj->base);
10309
10310         return fb;
10311 }
10312
10313 static struct drm_framebuffer *
10314 mode_fits_in_fbdev(struct drm_device *dev,
10315                    struct drm_display_mode *mode)
10316 {
10317 #ifdef CONFIG_DRM_FBDEV_EMULATION
10318         struct drm_i915_private *dev_priv = dev->dev_private;
10319         struct drm_i915_gem_object *obj;
10320         struct drm_framebuffer *fb;
10321
10322         if (!dev_priv->fbdev)
10323                 return NULL;
10324
10325         if (!dev_priv->fbdev->fb)
10326                 return NULL;
10327
10328         obj = dev_priv->fbdev->fb->obj;
10329         BUG_ON(!obj);
10330
10331         fb = &dev_priv->fbdev->fb->base;
10332         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10333                                                                fb->bits_per_pixel))
10334                 return NULL;
10335
10336         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10337                 return NULL;
10338
10339         drm_framebuffer_reference(fb);
10340         return fb;
10341 #else
10342         return NULL;
10343 #endif
10344 }
10345
10346 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10347                                            struct drm_crtc *crtc,
10348                                            struct drm_display_mode *mode,
10349                                            struct drm_framebuffer *fb,
10350                                            int x, int y)
10351 {
10352         struct drm_plane_state *plane_state;
10353         int hdisplay, vdisplay;
10354         int ret;
10355
10356         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10357         if (IS_ERR(plane_state))
10358                 return PTR_ERR(plane_state);
10359
10360         if (mode)
10361                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10362         else
10363                 hdisplay = vdisplay = 0;
10364
10365         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10366         if (ret)
10367                 return ret;
10368         drm_atomic_set_fb_for_plane(plane_state, fb);
10369         plane_state->crtc_x = 0;
10370         plane_state->crtc_y = 0;
10371         plane_state->crtc_w = hdisplay;
10372         plane_state->crtc_h = vdisplay;
10373         plane_state->src_x = x << 16;
10374         plane_state->src_y = y << 16;
10375         plane_state->src_w = hdisplay << 16;
10376         plane_state->src_h = vdisplay << 16;
10377
10378         return 0;
10379 }
10380
10381 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10382                                 struct drm_display_mode *mode,
10383                                 struct intel_load_detect_pipe *old,
10384                                 struct drm_modeset_acquire_ctx *ctx)
10385 {
10386         struct intel_crtc *intel_crtc;
10387         struct intel_encoder *intel_encoder =
10388                 intel_attached_encoder(connector);
10389         struct drm_crtc *possible_crtc;
10390         struct drm_encoder *encoder = &intel_encoder->base;
10391         struct drm_crtc *crtc = NULL;
10392         struct drm_device *dev = encoder->dev;
10393         struct drm_framebuffer *fb;
10394         struct drm_mode_config *config = &dev->mode_config;
10395         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10396         struct drm_connector_state *connector_state;
10397         struct intel_crtc_state *crtc_state;
10398         int ret, i = -1;
10399
10400         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10401                       connector->base.id, connector->name,
10402                       encoder->base.id, encoder->name);
10403
10404         old->restore_state = NULL;
10405
10406 retry:
10407         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10408         if (ret)
10409                 goto fail;
10410
10411         /*
10412          * Algorithm gets a little messy:
10413          *
10414          *   - if the connector already has an assigned crtc, use it (but make
10415          *     sure it's on first)
10416          *
10417          *   - try to find the first unused crtc that can drive this connector,
10418          *     and use that if we find one
10419          */
10420
10421         /* See if we already have a CRTC for this connector */
10422         if (connector->state->crtc) {
10423                 crtc = connector->state->crtc;
10424
10425                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10426                 if (ret)
10427                         goto fail;
10428
10429                 /* Make sure the crtc and connector are running */
10430                 goto found;
10431         }
10432
10433         /* Find an unused one (if possible) */
10434         for_each_crtc(dev, possible_crtc) {
10435                 i++;
10436                 if (!(encoder->possible_crtcs & (1 << i)))
10437                         continue;
10438
10439                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10440                 if (ret)
10441                         goto fail;
10442
10443                 if (possible_crtc->state->enable) {
10444                         drm_modeset_unlock(&possible_crtc->mutex);
10445                         continue;
10446                 }
10447
10448                 crtc = possible_crtc;
10449                 break;
10450         }
10451
10452         /*
10453          * If we didn't find an unused CRTC, don't use any.
10454          */
10455         if (!crtc) {
10456                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10457                 goto fail;
10458         }
10459
10460 found:
10461         intel_crtc = to_intel_crtc(crtc);
10462
10463         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10464         if (ret)
10465                 goto fail;
10466
10467         state = drm_atomic_state_alloc(dev);
10468         restore_state = drm_atomic_state_alloc(dev);
10469         if (!state || !restore_state) {
10470                 ret = -ENOMEM;
10471                 goto fail;
10472         }
10473
10474         state->acquire_ctx = ctx;
10475         restore_state->acquire_ctx = ctx;
10476
10477         connector_state = drm_atomic_get_connector_state(state, connector);
10478         if (IS_ERR(connector_state)) {
10479                 ret = PTR_ERR(connector_state);
10480                 goto fail;
10481         }
10482
10483         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10484         if (ret)
10485                 goto fail;
10486
10487         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10488         if (IS_ERR(crtc_state)) {
10489                 ret = PTR_ERR(crtc_state);
10490                 goto fail;
10491         }
10492
10493         crtc_state->base.active = crtc_state->base.enable = true;
10494
10495         if (!mode)
10496                 mode = &load_detect_mode;
10497
10498         /* We need a framebuffer large enough to accommodate all accesses
10499          * that the plane may generate whilst we perform load detection.
10500          * We can not rely on the fbcon either being present (we get called
10501          * during its initialisation to detect all boot displays, or it may
10502          * not even exist) or that it is large enough to satisfy the
10503          * requested mode.
10504          */
10505         fb = mode_fits_in_fbdev(dev, mode);
10506         if (fb == NULL) {
10507                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10508                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10509         } else
10510                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10511         if (IS_ERR(fb)) {
10512                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10513                 goto fail;
10514         }
10515
10516         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10517         if (ret)
10518                 goto fail;
10519
10520         drm_framebuffer_unreference(fb);
10521
10522         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10523         if (ret)
10524                 goto fail;
10525
10526         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10527         if (!ret)
10528                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10529         if (!ret)
10530                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10531         if (ret) {
10532                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10533                 goto fail;
10534         }
10535
10536         ret = drm_atomic_commit(state);
10537         if (ret) {
10538                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10539                 goto fail;
10540         }
10541
10542         old->restore_state = restore_state;
10543
10544         /* let the connector get through one full cycle before testing */
10545         intel_wait_for_vblank(dev, intel_crtc->pipe);
10546         return true;
10547
10548 fail:
10549         drm_atomic_state_free(state);
10550         drm_atomic_state_free(restore_state);
10551         restore_state = state = NULL;
10552
10553         if (ret == -EDEADLK) {
10554                 drm_modeset_backoff(ctx);
10555                 goto retry;
10556         }
10557
10558         return false;
10559 }
10560
10561 void intel_release_load_detect_pipe(struct drm_connector *connector,
10562                                     struct intel_load_detect_pipe *old,
10563                                     struct drm_modeset_acquire_ctx *ctx)
10564 {
10565         struct intel_encoder *intel_encoder =
10566                 intel_attached_encoder(connector);
10567         struct drm_encoder *encoder = &intel_encoder->base;
10568         struct drm_atomic_state *state = old->restore_state;
10569         int ret;
10570
10571         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10572                       connector->base.id, connector->name,
10573                       encoder->base.id, encoder->name);
10574
10575         if (!state)
10576                 return;
10577
10578         ret = drm_atomic_commit(state);
10579         if (ret) {
10580                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10581                 drm_atomic_state_free(state);
10582         }
10583 }
10584
10585 static int i9xx_pll_refclk(struct drm_device *dev,
10586                            const struct intel_crtc_state *pipe_config)
10587 {
10588         struct drm_i915_private *dev_priv = dev->dev_private;
10589         u32 dpll = pipe_config->dpll_hw_state.dpll;
10590
10591         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10592                 return dev_priv->vbt.lvds_ssc_freq;
10593         else if (HAS_PCH_SPLIT(dev))
10594                 return 120000;
10595         else if (!IS_GEN2(dev))
10596                 return 96000;
10597         else
10598                 return 48000;
10599 }
10600
10601 /* Returns the clock of the currently programmed mode of the given pipe. */
10602 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10603                                 struct intel_crtc_state *pipe_config)
10604 {
10605         struct drm_device *dev = crtc->base.dev;
10606         struct drm_i915_private *dev_priv = dev->dev_private;
10607         int pipe = pipe_config->cpu_transcoder;
10608         u32 dpll = pipe_config->dpll_hw_state.dpll;
10609         u32 fp;
10610         intel_clock_t clock;
10611         int port_clock;
10612         int refclk = i9xx_pll_refclk(dev, pipe_config);
10613
10614         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10615                 fp = pipe_config->dpll_hw_state.fp0;
10616         else
10617                 fp = pipe_config->dpll_hw_state.fp1;
10618
10619         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10620         if (IS_PINEVIEW(dev)) {
10621                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10622                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10623         } else {
10624                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10625                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10626         }
10627
10628         if (!IS_GEN2(dev)) {
10629                 if (IS_PINEVIEW(dev))
10630                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10631                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10632                 else
10633                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10634                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10635
10636                 switch (dpll & DPLL_MODE_MASK) {
10637                 case DPLLB_MODE_DAC_SERIAL:
10638                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10639                                 5 : 10;
10640                         break;
10641                 case DPLLB_MODE_LVDS:
10642                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10643                                 7 : 14;
10644                         break;
10645                 default:
10646                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10647                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10648                         return;
10649                 }
10650
10651                 if (IS_PINEVIEW(dev))
10652                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10653                 else
10654                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10655         } else {
10656                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10657                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10658
10659                 if (is_lvds) {
10660                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10661                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10662
10663                         if (lvds & LVDS_CLKB_POWER_UP)
10664                                 clock.p2 = 7;
10665                         else
10666                                 clock.p2 = 14;
10667                 } else {
10668                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10669                                 clock.p1 = 2;
10670                         else {
10671                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10672                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10673                         }
10674                         if (dpll & PLL_P2_DIVIDE_BY_4)
10675                                 clock.p2 = 4;
10676                         else
10677                                 clock.p2 = 2;
10678                 }
10679
10680                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10681         }
10682
10683         /*
10684          * This value includes pixel_multiplier. We will use
10685          * port_clock to compute adjusted_mode.crtc_clock in the
10686          * encoder's get_config() function.
10687          */
10688         pipe_config->port_clock = port_clock;
10689 }
10690
10691 int intel_dotclock_calculate(int link_freq,
10692                              const struct intel_link_m_n *m_n)
10693 {
10694         /*
10695          * The calculation for the data clock is:
10696          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10697          * But we want to avoid losing precison if possible, so:
10698          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10699          *
10700          * and the link clock is simpler:
10701          * link_clock = (m * link_clock) / n
10702          */
10703
10704         if (!m_n->link_n)
10705                 return 0;
10706
10707         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10708 }
10709
10710 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10711                                    struct intel_crtc_state *pipe_config)
10712 {
10713         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10714
10715         /* read out port_clock from the DPLL */
10716         i9xx_crtc_clock_get(crtc, pipe_config);
10717
10718         /*
10719          * In case there is an active pipe without active ports,
10720          * we may need some idea for the dotclock anyway.
10721          * Calculate one based on the FDI configuration.
10722          */
10723         pipe_config->base.adjusted_mode.crtc_clock =
10724                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10725                                          &pipe_config->fdi_m_n);
10726 }
10727
10728 /** Returns the currently programmed mode of the given pipe. */
10729 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10730                                              struct drm_crtc *crtc)
10731 {
10732         struct drm_i915_private *dev_priv = dev->dev_private;
10733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10734         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10735         struct drm_display_mode *mode;
10736         struct intel_crtc_state *pipe_config;
10737         int htot = I915_READ(HTOTAL(cpu_transcoder));
10738         int hsync = I915_READ(HSYNC(cpu_transcoder));
10739         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10740         int vsync = I915_READ(VSYNC(cpu_transcoder));
10741         enum pipe pipe = intel_crtc->pipe;
10742
10743         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10744         if (!mode)
10745                 return NULL;
10746
10747         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10748         if (!pipe_config) {
10749                 kfree(mode);
10750                 return NULL;
10751         }
10752
10753         /*
10754          * Construct a pipe_config sufficient for getting the clock info
10755          * back out of crtc_clock_get.
10756          *
10757          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10758          * to use a real value here instead.
10759          */
10760         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10761         pipe_config->pixel_multiplier = 1;
10762         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10763         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10764         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10765         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10766
10767         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10768         mode->hdisplay = (htot & 0xffff) + 1;
10769         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10770         mode->hsync_start = (hsync & 0xffff) + 1;
10771         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10772         mode->vdisplay = (vtot & 0xffff) + 1;
10773         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10774         mode->vsync_start = (vsync & 0xffff) + 1;
10775         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10776
10777         drm_mode_set_name(mode);
10778
10779         kfree(pipe_config);
10780
10781         return mode;
10782 }
10783
10784 void intel_mark_busy(struct drm_device *dev)
10785 {
10786         struct drm_i915_private *dev_priv = dev->dev_private;
10787
10788         if (dev_priv->mm.busy)
10789                 return;
10790
10791         intel_runtime_pm_get(dev_priv);
10792         i915_update_gfx_val(dev_priv);
10793         if (INTEL_INFO(dev)->gen >= 6)
10794                 gen6_rps_busy(dev_priv);
10795         dev_priv->mm.busy = true;
10796 }
10797
10798 void intel_mark_idle(struct drm_device *dev)
10799 {
10800         struct drm_i915_private *dev_priv = dev->dev_private;
10801
10802         if (!dev_priv->mm.busy)
10803                 return;
10804
10805         dev_priv->mm.busy = false;
10806
10807         if (INTEL_INFO(dev)->gen >= 6)
10808                 gen6_rps_idle(dev->dev_private);
10809
10810         intel_runtime_pm_put(dev_priv);
10811 }
10812
10813 static void intel_crtc_destroy(struct drm_crtc *crtc)
10814 {
10815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10816         struct drm_device *dev = crtc->dev;
10817         struct intel_unpin_work *work;
10818
10819         spin_lock_irq(&dev->event_lock);
10820         work = intel_crtc->unpin_work;
10821         intel_crtc->unpin_work = NULL;
10822         spin_unlock_irq(&dev->event_lock);
10823
10824         if (work) {
10825                 cancel_work_sync(&work->work);
10826                 kfree(work);
10827         }
10828
10829         drm_crtc_cleanup(crtc);
10830
10831         kfree(intel_crtc);
10832 }
10833
10834 static void intel_unpin_work_fn(struct work_struct *__work)
10835 {
10836         struct intel_unpin_work *work =
10837                 container_of(__work, struct intel_unpin_work, work);
10838         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10839         struct drm_device *dev = crtc->base.dev;
10840         struct drm_plane *primary = crtc->base.primary;
10841
10842         mutex_lock(&dev->struct_mutex);
10843         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10844         drm_gem_object_unreference(&work->pending_flip_obj->base);
10845
10846         if (work->flip_queued_req)
10847                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10848         mutex_unlock(&dev->struct_mutex);
10849
10850         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10851         intel_fbc_post_update(crtc);
10852         drm_framebuffer_unreference(work->old_fb);
10853
10854         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10855         atomic_dec(&crtc->unpin_work_count);
10856
10857         kfree(work);
10858 }
10859
10860 static void do_intel_finish_page_flip(struct drm_device *dev,
10861                                       struct drm_crtc *crtc)
10862 {
10863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10864         struct intel_unpin_work *work;
10865         unsigned long flags;
10866
10867         /* Ignore early vblank irqs */
10868         if (intel_crtc == NULL)
10869                 return;
10870
10871         /*
10872          * This is called both by irq handlers and the reset code (to complete
10873          * lost pageflips) so needs the full irqsave spinlocks.
10874          */
10875         spin_lock_irqsave(&dev->event_lock, flags);
10876         work = intel_crtc->unpin_work;
10877
10878         /* Ensure we don't miss a work->pending update ... */
10879         smp_rmb();
10880
10881         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10882                 spin_unlock_irqrestore(&dev->event_lock, flags);
10883                 return;
10884         }
10885
10886         page_flip_completed(intel_crtc);
10887
10888         spin_unlock_irqrestore(&dev->event_lock, flags);
10889 }
10890
10891 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10892 {
10893         struct drm_i915_private *dev_priv = dev->dev_private;
10894         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10895
10896         do_intel_finish_page_flip(dev, crtc);
10897 }
10898
10899 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10900 {
10901         struct drm_i915_private *dev_priv = dev->dev_private;
10902         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10903
10904         do_intel_finish_page_flip(dev, crtc);
10905 }
10906
10907 /* Is 'a' after or equal to 'b'? */
10908 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10909 {
10910         return !((a - b) & 0x80000000);
10911 }
10912
10913 static bool page_flip_finished(struct intel_crtc *crtc)
10914 {
10915         struct drm_device *dev = crtc->base.dev;
10916         struct drm_i915_private *dev_priv = dev->dev_private;
10917         unsigned reset_counter;
10918
10919         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
10920         if (crtc->reset_counter != reset_counter)
10921                 return true;
10922
10923         /*
10924          * The relevant registers doen't exist on pre-ctg.
10925          * As the flip done interrupt doesn't trigger for mmio
10926          * flips on gmch platforms, a flip count check isn't
10927          * really needed there. But since ctg has the registers,
10928          * include it in the check anyway.
10929          */
10930         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10931                 return true;
10932
10933         /*
10934          * BDW signals flip done immediately if the plane
10935          * is disabled, even if the plane enable is already
10936          * armed to occur at the next vblank :(
10937          */
10938
10939         /*
10940          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10941          * used the same base address. In that case the mmio flip might
10942          * have completed, but the CS hasn't even executed the flip yet.
10943          *
10944          * A flip count check isn't enough as the CS might have updated
10945          * the base address just after start of vblank, but before we
10946          * managed to process the interrupt. This means we'd complete the
10947          * CS flip too soon.
10948          *
10949          * Combining both checks should get us a good enough result. It may
10950          * still happen that the CS flip has been executed, but has not
10951          * yet actually completed. But in case the base address is the same
10952          * anyway, we don't really care.
10953          */
10954         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10955                 crtc->unpin_work->gtt_offset &&
10956                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10957                                     crtc->unpin_work->flip_count);
10958 }
10959
10960 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10961 {
10962         struct drm_i915_private *dev_priv = dev->dev_private;
10963         struct intel_crtc *intel_crtc =
10964                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10965         unsigned long flags;
10966
10967
10968         /*
10969          * This is called both by irq handlers and the reset code (to complete
10970          * lost pageflips) so needs the full irqsave spinlocks.
10971          *
10972          * NB: An MMIO update of the plane base pointer will also
10973          * generate a page-flip completion irq, i.e. every modeset
10974          * is also accompanied by a spurious intel_prepare_page_flip().
10975          */
10976         spin_lock_irqsave(&dev->event_lock, flags);
10977         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10978                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10979         spin_unlock_irqrestore(&dev->event_lock, flags);
10980 }
10981
10982 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10983 {
10984         /* Ensure that the work item is consistent when activating it ... */
10985         smp_wmb();
10986         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10987         /* and that it is marked active as soon as the irq could fire. */
10988         smp_wmb();
10989 }
10990
10991 static int intel_gen2_queue_flip(struct drm_device *dev,
10992                                  struct drm_crtc *crtc,
10993                                  struct drm_framebuffer *fb,
10994                                  struct drm_i915_gem_object *obj,
10995                                  struct drm_i915_gem_request *req,
10996                                  uint32_t flags)
10997 {
10998         struct intel_engine_cs *engine = req->engine;
10999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11000         u32 flip_mask;
11001         int ret;
11002
11003         ret = intel_ring_begin(req, 6);
11004         if (ret)
11005                 return ret;
11006
11007         /* Can't queue multiple flips, so wait for the previous
11008          * one to finish before executing the next.
11009          */
11010         if (intel_crtc->plane)
11011                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11012         else
11013                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11014         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11015         intel_ring_emit(engine, MI_NOOP);
11016         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11017                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11018         intel_ring_emit(engine, fb->pitches[0]);
11019         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11020         intel_ring_emit(engine, 0); /* aux display base address, unused */
11021
11022         intel_mark_page_flip_active(intel_crtc->unpin_work);
11023         return 0;
11024 }
11025
11026 static int intel_gen3_queue_flip(struct drm_device *dev,
11027                                  struct drm_crtc *crtc,
11028                                  struct drm_framebuffer *fb,
11029                                  struct drm_i915_gem_object *obj,
11030                                  struct drm_i915_gem_request *req,
11031                                  uint32_t flags)
11032 {
11033         struct intel_engine_cs *engine = req->engine;
11034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11035         u32 flip_mask;
11036         int ret;
11037
11038         ret = intel_ring_begin(req, 6);
11039         if (ret)
11040                 return ret;
11041
11042         if (intel_crtc->plane)
11043                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11044         else
11045                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11046         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11047         intel_ring_emit(engine, MI_NOOP);
11048         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11049                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11050         intel_ring_emit(engine, fb->pitches[0]);
11051         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11052         intel_ring_emit(engine, MI_NOOP);
11053
11054         intel_mark_page_flip_active(intel_crtc->unpin_work);
11055         return 0;
11056 }
11057
11058 static int intel_gen4_queue_flip(struct drm_device *dev,
11059                                  struct drm_crtc *crtc,
11060                                  struct drm_framebuffer *fb,
11061                                  struct drm_i915_gem_object *obj,
11062                                  struct drm_i915_gem_request *req,
11063                                  uint32_t flags)
11064 {
11065         struct intel_engine_cs *engine = req->engine;
11066         struct drm_i915_private *dev_priv = dev->dev_private;
11067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11068         uint32_t pf, pipesrc;
11069         int ret;
11070
11071         ret = intel_ring_begin(req, 4);
11072         if (ret)
11073                 return ret;
11074
11075         /* i965+ uses the linear or tiled offsets from the
11076          * Display Registers (which do not change across a page-flip)
11077          * so we need only reprogram the base address.
11078          */
11079         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11080                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11081         intel_ring_emit(engine, fb->pitches[0]);
11082         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11083                         obj->tiling_mode);
11084
11085         /* XXX Enabling the panel-fitter across page-flip is so far
11086          * untested on non-native modes, so ignore it for now.
11087          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11088          */
11089         pf = 0;
11090         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11091         intel_ring_emit(engine, pf | pipesrc);
11092
11093         intel_mark_page_flip_active(intel_crtc->unpin_work);
11094         return 0;
11095 }
11096
11097 static int intel_gen6_queue_flip(struct drm_device *dev,
11098                                  struct drm_crtc *crtc,
11099                                  struct drm_framebuffer *fb,
11100                                  struct drm_i915_gem_object *obj,
11101                                  struct drm_i915_gem_request *req,
11102                                  uint32_t flags)
11103 {
11104         struct intel_engine_cs *engine = req->engine;
11105         struct drm_i915_private *dev_priv = dev->dev_private;
11106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11107         uint32_t pf, pipesrc;
11108         int ret;
11109
11110         ret = intel_ring_begin(req, 4);
11111         if (ret)
11112                 return ret;
11113
11114         intel_ring_emit(engine, MI_DISPLAY_FLIP |
11115                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11116         intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11117         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11118
11119         /* Contrary to the suggestions in the documentation,
11120          * "Enable Panel Fitter" does not seem to be required when page
11121          * flipping with a non-native mode, and worse causes a normal
11122          * modeset to fail.
11123          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11124          */
11125         pf = 0;
11126         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11127         intel_ring_emit(engine, pf | pipesrc);
11128
11129         intel_mark_page_flip_active(intel_crtc->unpin_work);
11130         return 0;
11131 }
11132
11133 static int intel_gen7_queue_flip(struct drm_device *dev,
11134                                  struct drm_crtc *crtc,
11135                                  struct drm_framebuffer *fb,
11136                                  struct drm_i915_gem_object *obj,
11137                                  struct drm_i915_gem_request *req,
11138                                  uint32_t flags)
11139 {
11140         struct intel_engine_cs *engine = req->engine;
11141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11142         uint32_t plane_bit = 0;
11143         int len, ret;
11144
11145         switch (intel_crtc->plane) {
11146         case PLANE_A:
11147                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11148                 break;
11149         case PLANE_B:
11150                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11151                 break;
11152         case PLANE_C:
11153                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11154                 break;
11155         default:
11156                 WARN_ONCE(1, "unknown plane in flip command\n");
11157                 return -ENODEV;
11158         }
11159
11160         len = 4;
11161         if (engine->id == RCS) {
11162                 len += 6;
11163                 /*
11164                  * On Gen 8, SRM is now taking an extra dword to accommodate
11165                  * 48bits addresses, and we need a NOOP for the batch size to
11166                  * stay even.
11167                  */
11168                 if (IS_GEN8(dev))
11169                         len += 2;
11170         }
11171
11172         /*
11173          * BSpec MI_DISPLAY_FLIP for IVB:
11174          * "The full packet must be contained within the same cache line."
11175          *
11176          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11177          * cacheline, if we ever start emitting more commands before
11178          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11179          * then do the cacheline alignment, and finally emit the
11180          * MI_DISPLAY_FLIP.
11181          */
11182         ret = intel_ring_cacheline_align(req);
11183         if (ret)
11184                 return ret;
11185
11186         ret = intel_ring_begin(req, len);
11187         if (ret)
11188                 return ret;
11189
11190         /* Unmask the flip-done completion message. Note that the bspec says that
11191          * we should do this for both the BCS and RCS, and that we must not unmask
11192          * more than one flip event at any time (or ensure that one flip message
11193          * can be sent by waiting for flip-done prior to queueing new flips).
11194          * Experimentation says that BCS works despite DERRMR masking all
11195          * flip-done completion events and that unmasking all planes at once
11196          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11197          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11198          */
11199         if (engine->id == RCS) {
11200                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11201                 intel_ring_emit_reg(engine, DERRMR);
11202                 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11203                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11204                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11205                 if (IS_GEN8(dev))
11206                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11207                                               MI_SRM_LRM_GLOBAL_GTT);
11208                 else
11209                         intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11210                                               MI_SRM_LRM_GLOBAL_GTT);
11211                 intel_ring_emit_reg(engine, DERRMR);
11212                 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11213                 if (IS_GEN8(dev)) {
11214                         intel_ring_emit(engine, 0);
11215                         intel_ring_emit(engine, MI_NOOP);
11216                 }
11217         }
11218
11219         intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11220         intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11221         intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11222         intel_ring_emit(engine, (MI_NOOP));
11223
11224         intel_mark_page_flip_active(intel_crtc->unpin_work);
11225         return 0;
11226 }
11227
11228 static bool use_mmio_flip(struct intel_engine_cs *engine,
11229                           struct drm_i915_gem_object *obj)
11230 {
11231         /*
11232          * This is not being used for older platforms, because
11233          * non-availability of flip done interrupt forces us to use
11234          * CS flips. Older platforms derive flip done using some clever
11235          * tricks involving the flip_pending status bits and vblank irqs.
11236          * So using MMIO flips there would disrupt this mechanism.
11237          */
11238
11239         if (engine == NULL)
11240                 return true;
11241
11242         if (INTEL_INFO(engine->dev)->gen < 5)
11243                 return false;
11244
11245         if (i915.use_mmio_flip < 0)
11246                 return false;
11247         else if (i915.use_mmio_flip > 0)
11248                 return true;
11249         else if (i915.enable_execlists)
11250                 return true;
11251         else if (obj->base.dma_buf &&
11252                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11253                                                        false))
11254                 return true;
11255         else
11256                 return engine != i915_gem_request_get_engine(obj->last_write_req);
11257 }
11258
11259 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11260                              unsigned int rotation,
11261                              struct intel_unpin_work *work)
11262 {
11263         struct drm_device *dev = intel_crtc->base.dev;
11264         struct drm_i915_private *dev_priv = dev->dev_private;
11265         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11266         const enum pipe pipe = intel_crtc->pipe;
11267         u32 ctl, stride, tile_height;
11268
11269         ctl = I915_READ(PLANE_CTL(pipe, 0));
11270         ctl &= ~PLANE_CTL_TILED_MASK;
11271         switch (fb->modifier[0]) {
11272         case DRM_FORMAT_MOD_NONE:
11273                 break;
11274         case I915_FORMAT_MOD_X_TILED:
11275                 ctl |= PLANE_CTL_TILED_X;
11276                 break;
11277         case I915_FORMAT_MOD_Y_TILED:
11278                 ctl |= PLANE_CTL_TILED_Y;
11279                 break;
11280         case I915_FORMAT_MOD_Yf_TILED:
11281                 ctl |= PLANE_CTL_TILED_YF;
11282                 break;
11283         default:
11284                 MISSING_CASE(fb->modifier[0]);
11285         }
11286
11287         /*
11288          * The stride is either expressed as a multiple of 64 bytes chunks for
11289          * linear buffers or in number of tiles for tiled buffers.
11290          */
11291         if (intel_rotation_90_or_270(rotation)) {
11292                 /* stride = Surface height in tiles */
11293                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11294                 stride = DIV_ROUND_UP(fb->height, tile_height);
11295         } else {
11296                 stride = fb->pitches[0] /
11297                         intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11298                                                   fb->pixel_format);
11299         }
11300
11301         /*
11302          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11303          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11304          */
11305         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11306         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11307
11308         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11309         POSTING_READ(PLANE_SURF(pipe, 0));
11310 }
11311
11312 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11313                              struct intel_unpin_work *work)
11314 {
11315         struct drm_device *dev = intel_crtc->base.dev;
11316         struct drm_i915_private *dev_priv = dev->dev_private;
11317         struct intel_framebuffer *intel_fb =
11318                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11319         struct drm_i915_gem_object *obj = intel_fb->obj;
11320         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11321         u32 dspcntr;
11322
11323         dspcntr = I915_READ(reg);
11324
11325         if (obj->tiling_mode != I915_TILING_NONE)
11326                 dspcntr |= DISPPLANE_TILED;
11327         else
11328                 dspcntr &= ~DISPPLANE_TILED;
11329
11330         I915_WRITE(reg, dspcntr);
11331
11332         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11333         POSTING_READ(DSPSURF(intel_crtc->plane));
11334 }
11335
11336 /*
11337  * XXX: This is the temporary way to update the plane registers until we get
11338  * around to using the usual plane update functions for MMIO flips
11339  */
11340 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11341 {
11342         struct intel_crtc *crtc = mmio_flip->crtc;
11343         struct intel_unpin_work *work;
11344
11345         spin_lock_irq(&crtc->base.dev->event_lock);
11346         work = crtc->unpin_work;
11347         spin_unlock_irq(&crtc->base.dev->event_lock);
11348         if (work == NULL)
11349                 return;
11350
11351         intel_mark_page_flip_active(work);
11352
11353         intel_pipe_update_start(crtc);
11354
11355         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11356                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11357         else
11358                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11359                 ilk_do_mmio_flip(crtc, work);
11360
11361         intel_pipe_update_end(crtc);
11362 }
11363
11364 static void intel_mmio_flip_work_func(struct work_struct *work)
11365 {
11366         struct intel_mmio_flip *mmio_flip =
11367                 container_of(work, struct intel_mmio_flip, work);
11368         struct intel_framebuffer *intel_fb =
11369                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11370         struct drm_i915_gem_object *obj = intel_fb->obj;
11371
11372         if (mmio_flip->req) {
11373                 WARN_ON(__i915_wait_request(mmio_flip->req,
11374                                             false, NULL,
11375                                             &mmio_flip->i915->rps.mmioflips));
11376                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11377         }
11378
11379         /* For framebuffer backed by dmabuf, wait for fence */
11380         if (obj->base.dma_buf)
11381                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11382                                                             false, false,
11383                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11384
11385         intel_do_mmio_flip(mmio_flip);
11386         kfree(mmio_flip);
11387 }
11388
11389 static int intel_queue_mmio_flip(struct drm_device *dev,
11390                                  struct drm_crtc *crtc,
11391                                  struct drm_i915_gem_object *obj)
11392 {
11393         struct intel_mmio_flip *mmio_flip;
11394
11395         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11396         if (mmio_flip == NULL)
11397                 return -ENOMEM;
11398
11399         mmio_flip->i915 = to_i915(dev);
11400         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11401         mmio_flip->crtc = to_intel_crtc(crtc);
11402         mmio_flip->rotation = crtc->primary->state->rotation;
11403
11404         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11405         schedule_work(&mmio_flip->work);
11406
11407         return 0;
11408 }
11409
11410 static int intel_default_queue_flip(struct drm_device *dev,
11411                                     struct drm_crtc *crtc,
11412                                     struct drm_framebuffer *fb,
11413                                     struct drm_i915_gem_object *obj,
11414                                     struct drm_i915_gem_request *req,
11415                                     uint32_t flags)
11416 {
11417         return -ENODEV;
11418 }
11419
11420 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11421                                          struct drm_crtc *crtc)
11422 {
11423         struct drm_i915_private *dev_priv = dev->dev_private;
11424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11425         struct intel_unpin_work *work = intel_crtc->unpin_work;
11426         u32 addr;
11427
11428         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11429                 return true;
11430
11431         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11432                 return false;
11433
11434         if (!work->enable_stall_check)
11435                 return false;
11436
11437         if (work->flip_ready_vblank == 0) {
11438                 if (work->flip_queued_req &&
11439                     !i915_gem_request_completed(work->flip_queued_req, true))
11440                         return false;
11441
11442                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11443         }
11444
11445         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11446                 return false;
11447
11448         /* Potential stall - if we see that the flip has happened,
11449          * assume a missed interrupt. */
11450         if (INTEL_INFO(dev)->gen >= 4)
11451                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11452         else
11453                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11454
11455         /* There is a potential issue here with a false positive after a flip
11456          * to the same address. We could address this by checking for a
11457          * non-incrementing frame counter.
11458          */
11459         return addr == work->gtt_offset;
11460 }
11461
11462 void intel_check_page_flip(struct drm_device *dev, int pipe)
11463 {
11464         struct drm_i915_private *dev_priv = dev->dev_private;
11465         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11467         struct intel_unpin_work *work;
11468
11469         WARN_ON(!in_interrupt());
11470
11471         if (crtc == NULL)
11472                 return;
11473
11474         spin_lock(&dev->event_lock);
11475         work = intel_crtc->unpin_work;
11476         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11477                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11478                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11479                 page_flip_completed(intel_crtc);
11480                 work = NULL;
11481         }
11482         if (work != NULL &&
11483             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11484                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11485         spin_unlock(&dev->event_lock);
11486 }
11487
11488 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11489                                 struct drm_framebuffer *fb,
11490                                 struct drm_pending_vblank_event *event,
11491                                 uint32_t page_flip_flags)
11492 {
11493         struct drm_device *dev = crtc->dev;
11494         struct drm_i915_private *dev_priv = dev->dev_private;
11495         struct drm_framebuffer *old_fb = crtc->primary->fb;
11496         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11498         struct drm_plane *primary = crtc->primary;
11499         enum pipe pipe = intel_crtc->pipe;
11500         struct intel_unpin_work *work;
11501         struct intel_engine_cs *engine;
11502         bool mmio_flip;
11503         struct drm_i915_gem_request *request = NULL;
11504         int ret;
11505
11506         /*
11507          * drm_mode_page_flip_ioctl() should already catch this, but double
11508          * check to be safe.  In the future we may enable pageflipping from
11509          * a disabled primary plane.
11510          */
11511         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11512                 return -EBUSY;
11513
11514         /* Can't change pixel format via MI display flips. */
11515         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11516                 return -EINVAL;
11517
11518         /*
11519          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11520          * Note that pitch changes could also affect these register.
11521          */
11522         if (INTEL_INFO(dev)->gen > 3 &&
11523             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11524              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11525                 return -EINVAL;
11526
11527         if (i915_terminally_wedged(&dev_priv->gpu_error))
11528                 goto out_hang;
11529
11530         work = kzalloc(sizeof(*work), GFP_KERNEL);
11531         if (work == NULL)
11532                 return -ENOMEM;
11533
11534         work->event = event;
11535         work->crtc = crtc;
11536         work->old_fb = old_fb;
11537         INIT_WORK(&work->work, intel_unpin_work_fn);
11538
11539         ret = drm_crtc_vblank_get(crtc);
11540         if (ret)
11541                 goto free_work;
11542
11543         /* We borrow the event spin lock for protecting unpin_work */
11544         spin_lock_irq(&dev->event_lock);
11545         if (intel_crtc->unpin_work) {
11546                 /* Before declaring the flip queue wedged, check if
11547                  * the hardware completed the operation behind our backs.
11548                  */
11549                 if (__intel_pageflip_stall_check(dev, crtc)) {
11550                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11551                         page_flip_completed(intel_crtc);
11552                 } else {
11553                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11554                         spin_unlock_irq(&dev->event_lock);
11555
11556                         drm_crtc_vblank_put(crtc);
11557                         kfree(work);
11558                         return -EBUSY;
11559                 }
11560         }
11561         intel_crtc->unpin_work = work;
11562         spin_unlock_irq(&dev->event_lock);
11563
11564         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11565                 flush_workqueue(dev_priv->wq);
11566
11567         /* Reference the objects for the scheduled work. */
11568         drm_framebuffer_reference(work->old_fb);
11569         drm_gem_object_reference(&obj->base);
11570
11571         crtc->primary->fb = fb;
11572         update_state_fb(crtc->primary);
11573         intel_fbc_pre_update(intel_crtc);
11574
11575         work->pending_flip_obj = obj;
11576
11577         ret = i915_mutex_lock_interruptible(dev);
11578         if (ret)
11579                 goto cleanup;
11580
11581         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11582         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11583                 ret = -EIO;
11584                 goto cleanup;
11585         }
11586
11587         atomic_inc(&intel_crtc->unpin_work_count);
11588
11589         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11590                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11591
11592         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11593                 engine = &dev_priv->engine[BCS];
11594                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11595                         /* vlv: DISPLAY_FLIP fails to change tiling */
11596                         engine = NULL;
11597         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11598                 engine = &dev_priv->engine[BCS];
11599         } else if (INTEL_INFO(dev)->gen >= 7) {
11600                 engine = i915_gem_request_get_engine(obj->last_write_req);
11601                 if (engine == NULL || engine->id != RCS)
11602                         engine = &dev_priv->engine[BCS];
11603         } else {
11604                 engine = &dev_priv->engine[RCS];
11605         }
11606
11607         mmio_flip = use_mmio_flip(engine, obj);
11608
11609         /* When using CS flips, we want to emit semaphores between rings.
11610          * However, when using mmio flips we will create a task to do the
11611          * synchronisation, so all we want here is to pin the framebuffer
11612          * into the display plane and skip any waits.
11613          */
11614         if (!mmio_flip) {
11615                 ret = i915_gem_object_sync(obj, engine, &request);
11616                 if (ret)
11617                         goto cleanup_pending;
11618         }
11619
11620         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11621         if (ret)
11622                 goto cleanup_pending;
11623
11624         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11625                                                   obj, 0);
11626         work->gtt_offset += intel_crtc->dspaddr_offset;
11627
11628         if (mmio_flip) {
11629                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11630                 if (ret)
11631                         goto cleanup_unpin;
11632
11633                 i915_gem_request_assign(&work->flip_queued_req,
11634                                         obj->last_write_req);
11635         } else {
11636                 if (!request) {
11637                         request = i915_gem_request_alloc(engine, NULL);
11638                         if (IS_ERR(request)) {
11639                                 ret = PTR_ERR(request);
11640                                 goto cleanup_unpin;
11641                         }
11642                 }
11643
11644                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11645                                                    page_flip_flags);
11646                 if (ret)
11647                         goto cleanup_unpin;
11648
11649                 i915_gem_request_assign(&work->flip_queued_req, request);
11650         }
11651
11652         if (request)
11653                 i915_add_request_no_flush(request);
11654
11655         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11656         work->enable_stall_check = true;
11657
11658         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11659                           to_intel_plane(primary)->frontbuffer_bit);
11660         mutex_unlock(&dev->struct_mutex);
11661
11662         intel_frontbuffer_flip_prepare(dev,
11663                                        to_intel_plane(primary)->frontbuffer_bit);
11664
11665         trace_i915_flip_request(intel_crtc->plane, obj);
11666
11667         return 0;
11668
11669 cleanup_unpin:
11670         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11671 cleanup_pending:
11672         if (!IS_ERR_OR_NULL(request))
11673                 i915_add_request_no_flush(request);
11674         atomic_dec(&intel_crtc->unpin_work_count);
11675         mutex_unlock(&dev->struct_mutex);
11676 cleanup:
11677         crtc->primary->fb = old_fb;
11678         update_state_fb(crtc->primary);
11679
11680         drm_gem_object_unreference_unlocked(&obj->base);
11681         drm_framebuffer_unreference(work->old_fb);
11682
11683         spin_lock_irq(&dev->event_lock);
11684         intel_crtc->unpin_work = NULL;
11685         spin_unlock_irq(&dev->event_lock);
11686
11687         drm_crtc_vblank_put(crtc);
11688 free_work:
11689         kfree(work);
11690
11691         if (ret == -EIO) {
11692                 struct drm_atomic_state *state;
11693                 struct drm_plane_state *plane_state;
11694
11695 out_hang:
11696                 state = drm_atomic_state_alloc(dev);
11697                 if (!state)
11698                         return -ENOMEM;
11699                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11700
11701 retry:
11702                 plane_state = drm_atomic_get_plane_state(state, primary);
11703                 ret = PTR_ERR_OR_ZERO(plane_state);
11704                 if (!ret) {
11705                         drm_atomic_set_fb_for_plane(plane_state, fb);
11706
11707                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11708                         if (!ret)
11709                                 ret = drm_atomic_commit(state);
11710                 }
11711
11712                 if (ret == -EDEADLK) {
11713                         drm_modeset_backoff(state->acquire_ctx);
11714                         drm_atomic_state_clear(state);
11715                         goto retry;
11716                 }
11717
11718                 if (ret)
11719                         drm_atomic_state_free(state);
11720
11721                 if (ret == 0 && event) {
11722                         spin_lock_irq(&dev->event_lock);
11723                         drm_crtc_send_vblank_event(crtc, event);
11724                         spin_unlock_irq(&dev->event_lock);
11725                 }
11726         }
11727         return ret;
11728 }
11729
11730
11731 /**
11732  * intel_wm_need_update - Check whether watermarks need updating
11733  * @plane: drm plane
11734  * @state: new plane state
11735  *
11736  * Check current plane state versus the new one to determine whether
11737  * watermarks need to be recalculated.
11738  *
11739  * Returns true or false.
11740  */
11741 static bool intel_wm_need_update(struct drm_plane *plane,
11742                                  struct drm_plane_state *state)
11743 {
11744         struct intel_plane_state *new = to_intel_plane_state(state);
11745         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11746
11747         /* Update watermarks on tiling or size changes. */
11748         if (new->visible != cur->visible)
11749                 return true;
11750
11751         if (!cur->base.fb || !new->base.fb)
11752                 return false;
11753
11754         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11755             cur->base.rotation != new->base.rotation ||
11756             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11757             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11758             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11759             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11760                 return true;
11761
11762         return false;
11763 }
11764
11765 static bool needs_scaling(struct intel_plane_state *state)
11766 {
11767         int src_w = drm_rect_width(&state->src) >> 16;
11768         int src_h = drm_rect_height(&state->src) >> 16;
11769         int dst_w = drm_rect_width(&state->dst);
11770         int dst_h = drm_rect_height(&state->dst);
11771
11772         return (src_w != dst_w || src_h != dst_h);
11773 }
11774
11775 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11776                                     struct drm_plane_state *plane_state)
11777 {
11778         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11779         struct drm_crtc *crtc = crtc_state->crtc;
11780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11781         struct drm_plane *plane = plane_state->plane;
11782         struct drm_device *dev = crtc->dev;
11783         struct drm_i915_private *dev_priv = to_i915(dev);
11784         struct intel_plane_state *old_plane_state =
11785                 to_intel_plane_state(plane->state);
11786         int idx = intel_crtc->base.base.id, ret;
11787         bool mode_changed = needs_modeset(crtc_state);
11788         bool was_crtc_enabled = crtc->state->active;
11789         bool is_crtc_enabled = crtc_state->active;
11790         bool turn_off, turn_on, visible, was_visible;
11791         struct drm_framebuffer *fb = plane_state->fb;
11792
11793         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11794             plane->type != DRM_PLANE_TYPE_CURSOR) {
11795                 ret = skl_update_scaler_plane(
11796                         to_intel_crtc_state(crtc_state),
11797                         to_intel_plane_state(plane_state));
11798                 if (ret)
11799                         return ret;
11800         }
11801
11802         was_visible = old_plane_state->visible;
11803         visible = to_intel_plane_state(plane_state)->visible;
11804
11805         if (!was_crtc_enabled && WARN_ON(was_visible))
11806                 was_visible = false;
11807
11808         /*
11809          * Visibility is calculated as if the crtc was on, but
11810          * after scaler setup everything depends on it being off
11811          * when the crtc isn't active.
11812          */
11813         if (!is_crtc_enabled)
11814                 to_intel_plane_state(plane_state)->visible = visible = false;
11815
11816         if (!was_visible && !visible)
11817                 return 0;
11818
11819         if (fb != old_plane_state->base.fb)
11820                 pipe_config->fb_changed = true;
11821
11822         turn_off = was_visible && (!visible || mode_changed);
11823         turn_on = visible && (!was_visible || mode_changed);
11824
11825         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11826                          plane->base.id, fb ? fb->base.id : -1);
11827
11828         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11829                          plane->base.id, was_visible, visible,
11830                          turn_off, turn_on, mode_changed);
11831
11832         if (turn_on) {
11833                 pipe_config->update_wm_pre = true;
11834
11835                 /* must disable cxsr around plane enable/disable */
11836                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11837                         pipe_config->disable_cxsr = true;
11838         } else if (turn_off) {
11839                 pipe_config->update_wm_post = true;
11840
11841                 /* must disable cxsr around plane enable/disable */
11842                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11843                         pipe_config->disable_cxsr = true;
11844         } else if (intel_wm_need_update(plane, plane_state)) {
11845                 /* FIXME bollocks */
11846                 pipe_config->update_wm_pre = true;
11847                 pipe_config->update_wm_post = true;
11848         }
11849
11850         /* Pre-gen9 platforms need two-step watermark updates */
11851         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11852             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11853                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11854
11855         if (visible || was_visible)
11856                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11857
11858         /*
11859          * WaCxSRDisabledForSpriteScaling:ivb
11860          *
11861          * cstate->update_wm was already set above, so this flag will
11862          * take effect when we commit and program watermarks.
11863          */
11864         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11865             needs_scaling(to_intel_plane_state(plane_state)) &&
11866             !needs_scaling(old_plane_state))
11867                 pipe_config->disable_lp_wm = true;
11868
11869         return 0;
11870 }
11871
11872 static bool encoders_cloneable(const struct intel_encoder *a,
11873                                const struct intel_encoder *b)
11874 {
11875         /* masks could be asymmetric, so check both ways */
11876         return a == b || (a->cloneable & (1 << b->type) &&
11877                           b->cloneable & (1 << a->type));
11878 }
11879
11880 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11881                                          struct intel_crtc *crtc,
11882                                          struct intel_encoder *encoder)
11883 {
11884         struct intel_encoder *source_encoder;
11885         struct drm_connector *connector;
11886         struct drm_connector_state *connector_state;
11887         int i;
11888
11889         for_each_connector_in_state(state, connector, connector_state, i) {
11890                 if (connector_state->crtc != &crtc->base)
11891                         continue;
11892
11893                 source_encoder =
11894                         to_intel_encoder(connector_state->best_encoder);
11895                 if (!encoders_cloneable(encoder, source_encoder))
11896                         return false;
11897         }
11898
11899         return true;
11900 }
11901
11902 static bool check_encoder_cloning(struct drm_atomic_state *state,
11903                                   struct intel_crtc *crtc)
11904 {
11905         struct intel_encoder *encoder;
11906         struct drm_connector *connector;
11907         struct drm_connector_state *connector_state;
11908         int i;
11909
11910         for_each_connector_in_state(state, connector, connector_state, i) {
11911                 if (connector_state->crtc != &crtc->base)
11912                         continue;
11913
11914                 encoder = to_intel_encoder(connector_state->best_encoder);
11915                 if (!check_single_encoder_cloning(state, crtc, encoder))
11916                         return false;
11917         }
11918
11919         return true;
11920 }
11921
11922 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11923                                    struct drm_crtc_state *crtc_state)
11924 {
11925         struct drm_device *dev = crtc->dev;
11926         struct drm_i915_private *dev_priv = dev->dev_private;
11927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11928         struct intel_crtc_state *pipe_config =
11929                 to_intel_crtc_state(crtc_state);
11930         struct drm_atomic_state *state = crtc_state->state;
11931         int ret;
11932         bool mode_changed = needs_modeset(crtc_state);
11933
11934         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11935                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11936                 return -EINVAL;
11937         }
11938
11939         if (mode_changed && !crtc_state->active)
11940                 pipe_config->update_wm_post = true;
11941
11942         if (mode_changed && crtc_state->enable &&
11943             dev_priv->display.crtc_compute_clock &&
11944             !WARN_ON(pipe_config->shared_dpll)) {
11945                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11946                                                            pipe_config);
11947                 if (ret)
11948                         return ret;
11949         }
11950
11951         if (crtc_state->color_mgmt_changed) {
11952                 ret = intel_color_check(crtc, crtc_state);
11953                 if (ret)
11954                         return ret;
11955         }
11956
11957         ret = 0;
11958         if (dev_priv->display.compute_pipe_wm) {
11959                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11960                 if (ret) {
11961                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11962                         return ret;
11963                 }
11964         }
11965
11966         if (dev_priv->display.compute_intermediate_wm &&
11967             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11968                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11969                         return 0;
11970
11971                 /*
11972                  * Calculate 'intermediate' watermarks that satisfy both the
11973                  * old state and the new state.  We can program these
11974                  * immediately.
11975                  */
11976                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11977                                                                 intel_crtc,
11978                                                                 pipe_config);
11979                 if (ret) {
11980                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11981                         return ret;
11982                 }
11983         }
11984
11985         if (INTEL_INFO(dev)->gen >= 9) {
11986                 if (mode_changed)
11987                         ret = skl_update_scaler_crtc(pipe_config);
11988
11989                 if (!ret)
11990                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11991                                                          pipe_config);
11992         }
11993
11994         return ret;
11995 }
11996
11997 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11998         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11999         .atomic_begin = intel_begin_crtc_commit,
12000         .atomic_flush = intel_finish_crtc_commit,
12001         .atomic_check = intel_crtc_atomic_check,
12002 };
12003
12004 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12005 {
12006         struct intel_connector *connector;
12007
12008         for_each_intel_connector(dev, connector) {
12009                 if (connector->base.encoder) {
12010                         connector->base.state->best_encoder =
12011                                 connector->base.encoder;
12012                         connector->base.state->crtc =
12013                                 connector->base.encoder->crtc;
12014                 } else {
12015                         connector->base.state->best_encoder = NULL;
12016                         connector->base.state->crtc = NULL;
12017                 }
12018         }
12019 }
12020
12021 static void
12022 connected_sink_compute_bpp(struct intel_connector *connector,
12023                            struct intel_crtc_state *pipe_config)
12024 {
12025         int bpp = pipe_config->pipe_bpp;
12026
12027         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12028                 connector->base.base.id,
12029                 connector->base.name);
12030
12031         /* Don't use an invalid EDID bpc value */
12032         if (connector->base.display_info.bpc &&
12033             connector->base.display_info.bpc * 3 < bpp) {
12034                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12035                               bpp, connector->base.display_info.bpc*3);
12036                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12037         }
12038
12039         /* Clamp bpp to default limit on screens without EDID 1.4 */
12040         if (connector->base.display_info.bpc == 0) {
12041                 int type = connector->base.connector_type;
12042                 int clamp_bpp = 24;
12043
12044                 /* Fall back to 18 bpp when DP sink capability is unknown. */
12045                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12046                     type == DRM_MODE_CONNECTOR_eDP)
12047                         clamp_bpp = 18;
12048
12049                 if (bpp > clamp_bpp) {
12050                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12051                                       bpp, clamp_bpp);
12052                         pipe_config->pipe_bpp = clamp_bpp;
12053                 }
12054         }
12055 }
12056
12057 static int
12058 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12059                           struct intel_crtc_state *pipe_config)
12060 {
12061         struct drm_device *dev = crtc->base.dev;
12062         struct drm_atomic_state *state;
12063         struct drm_connector *connector;
12064         struct drm_connector_state *connector_state;
12065         int bpp, i;
12066
12067         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12068                 bpp = 10*3;
12069         else if (INTEL_INFO(dev)->gen >= 5)
12070                 bpp = 12*3;
12071         else
12072                 bpp = 8*3;
12073
12074
12075         pipe_config->pipe_bpp = bpp;
12076
12077         state = pipe_config->base.state;
12078
12079         /* Clamp display bpp to EDID value */
12080         for_each_connector_in_state(state, connector, connector_state, i) {
12081                 if (connector_state->crtc != &crtc->base)
12082                         continue;
12083
12084                 connected_sink_compute_bpp(to_intel_connector(connector),
12085                                            pipe_config);
12086         }
12087
12088         return bpp;
12089 }
12090
12091 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12092 {
12093         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12094                         "type: 0x%x flags: 0x%x\n",
12095                 mode->crtc_clock,
12096                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12097                 mode->crtc_hsync_end, mode->crtc_htotal,
12098                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12099                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12100 }
12101
12102 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12103                                    struct intel_crtc_state *pipe_config,
12104                                    const char *context)
12105 {
12106         struct drm_device *dev = crtc->base.dev;
12107         struct drm_plane *plane;
12108         struct intel_plane *intel_plane;
12109         struct intel_plane_state *state;
12110         struct drm_framebuffer *fb;
12111
12112         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12113                       context, pipe_config, pipe_name(crtc->pipe));
12114
12115         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12116         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12117                       pipe_config->pipe_bpp, pipe_config->dither);
12118         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12119                       pipe_config->has_pch_encoder,
12120                       pipe_config->fdi_lanes,
12121                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12122                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12123                       pipe_config->fdi_m_n.tu);
12124         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12125                       pipe_config->has_dp_encoder,
12126                       pipe_config->lane_count,
12127                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12128                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12129                       pipe_config->dp_m_n.tu);
12130
12131         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12132                       pipe_config->has_dp_encoder,
12133                       pipe_config->lane_count,
12134                       pipe_config->dp_m2_n2.gmch_m,
12135                       pipe_config->dp_m2_n2.gmch_n,
12136                       pipe_config->dp_m2_n2.link_m,
12137                       pipe_config->dp_m2_n2.link_n,
12138                       pipe_config->dp_m2_n2.tu);
12139
12140         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12141                       pipe_config->has_audio,
12142                       pipe_config->has_infoframe);
12143
12144         DRM_DEBUG_KMS("requested mode:\n");
12145         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12146         DRM_DEBUG_KMS("adjusted mode:\n");
12147         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12148         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12149         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12150         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12151                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12152         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12153                       crtc->num_scalers,
12154                       pipe_config->scaler_state.scaler_users,
12155                       pipe_config->scaler_state.scaler_id);
12156         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12157                       pipe_config->gmch_pfit.control,
12158                       pipe_config->gmch_pfit.pgm_ratios,
12159                       pipe_config->gmch_pfit.lvds_border_bits);
12160         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12161                       pipe_config->pch_pfit.pos,
12162                       pipe_config->pch_pfit.size,
12163                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12164         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12165         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12166
12167         if (IS_BROXTON(dev)) {
12168                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12169                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12170                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12171                               pipe_config->ddi_pll_sel,
12172                               pipe_config->dpll_hw_state.ebb0,
12173                               pipe_config->dpll_hw_state.ebb4,
12174                               pipe_config->dpll_hw_state.pll0,
12175                               pipe_config->dpll_hw_state.pll1,
12176                               pipe_config->dpll_hw_state.pll2,
12177                               pipe_config->dpll_hw_state.pll3,
12178                               pipe_config->dpll_hw_state.pll6,
12179                               pipe_config->dpll_hw_state.pll8,
12180                               pipe_config->dpll_hw_state.pll9,
12181                               pipe_config->dpll_hw_state.pll10,
12182                               pipe_config->dpll_hw_state.pcsdw12);
12183         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12184                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12185                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12186                               pipe_config->ddi_pll_sel,
12187                               pipe_config->dpll_hw_state.ctrl1,
12188                               pipe_config->dpll_hw_state.cfgcr1,
12189                               pipe_config->dpll_hw_state.cfgcr2);
12190         } else if (HAS_DDI(dev)) {
12191                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12192                               pipe_config->ddi_pll_sel,
12193                               pipe_config->dpll_hw_state.wrpll,
12194                               pipe_config->dpll_hw_state.spll);
12195         } else {
12196                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12197                               "fp0: 0x%x, fp1: 0x%x\n",
12198                               pipe_config->dpll_hw_state.dpll,
12199                               pipe_config->dpll_hw_state.dpll_md,
12200                               pipe_config->dpll_hw_state.fp0,
12201                               pipe_config->dpll_hw_state.fp1);
12202         }
12203
12204         DRM_DEBUG_KMS("planes on this crtc\n");
12205         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12206                 intel_plane = to_intel_plane(plane);
12207                 if (intel_plane->pipe != crtc->pipe)
12208                         continue;
12209
12210                 state = to_intel_plane_state(plane->state);
12211                 fb = state->base.fb;
12212                 if (!fb) {
12213                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12214                                 "disabled, scaler_id = %d\n",
12215                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12216                                 plane->base.id, intel_plane->pipe,
12217                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12218                                 drm_plane_index(plane), state->scaler_id);
12219                         continue;
12220                 }
12221
12222                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12223                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12224                         plane->base.id, intel_plane->pipe,
12225                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12226                         drm_plane_index(plane));
12227                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12228                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12229                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12230                         state->scaler_id,
12231                         state->src.x1 >> 16, state->src.y1 >> 16,
12232                         drm_rect_width(&state->src) >> 16,
12233                         drm_rect_height(&state->src) >> 16,
12234                         state->dst.x1, state->dst.y1,
12235                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12236         }
12237 }
12238
12239 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12240 {
12241         struct drm_device *dev = state->dev;
12242         struct drm_connector *connector;
12243         unsigned int used_ports = 0;
12244
12245         /*
12246          * Walk the connector list instead of the encoder
12247          * list to detect the problem on ddi platforms
12248          * where there's just one encoder per digital port.
12249          */
12250         drm_for_each_connector(connector, dev) {
12251                 struct drm_connector_state *connector_state;
12252                 struct intel_encoder *encoder;
12253
12254                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12255                 if (!connector_state)
12256                         connector_state = connector->state;
12257
12258                 if (!connector_state->best_encoder)
12259                         continue;
12260
12261                 encoder = to_intel_encoder(connector_state->best_encoder);
12262
12263                 WARN_ON(!connector_state->crtc);
12264
12265                 switch (encoder->type) {
12266                         unsigned int port_mask;
12267                 case INTEL_OUTPUT_UNKNOWN:
12268                         if (WARN_ON(!HAS_DDI(dev)))
12269                                 break;
12270                 case INTEL_OUTPUT_DISPLAYPORT:
12271                 case INTEL_OUTPUT_HDMI:
12272                 case INTEL_OUTPUT_EDP:
12273                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12274
12275                         /* the same port mustn't appear more than once */
12276                         if (used_ports & port_mask)
12277                                 return false;
12278
12279                         used_ports |= port_mask;
12280                 default:
12281                         break;
12282                 }
12283         }
12284
12285         return true;
12286 }
12287
12288 static void
12289 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12290 {
12291         struct drm_crtc_state tmp_state;
12292         struct intel_crtc_scaler_state scaler_state;
12293         struct intel_dpll_hw_state dpll_hw_state;
12294         struct intel_shared_dpll *shared_dpll;
12295         uint32_t ddi_pll_sel;
12296         bool force_thru;
12297
12298         /* FIXME: before the switch to atomic started, a new pipe_config was
12299          * kzalloc'd. Code that depends on any field being zero should be
12300          * fixed, so that the crtc_state can be safely duplicated. For now,
12301          * only fields that are know to not cause problems are preserved. */
12302
12303         tmp_state = crtc_state->base;
12304         scaler_state = crtc_state->scaler_state;
12305         shared_dpll = crtc_state->shared_dpll;
12306         dpll_hw_state = crtc_state->dpll_hw_state;
12307         ddi_pll_sel = crtc_state->ddi_pll_sel;
12308         force_thru = crtc_state->pch_pfit.force_thru;
12309
12310         memset(crtc_state, 0, sizeof *crtc_state);
12311
12312         crtc_state->base = tmp_state;
12313         crtc_state->scaler_state = scaler_state;
12314         crtc_state->shared_dpll = shared_dpll;
12315         crtc_state->dpll_hw_state = dpll_hw_state;
12316         crtc_state->ddi_pll_sel = ddi_pll_sel;
12317         crtc_state->pch_pfit.force_thru = force_thru;
12318 }
12319
12320 static int
12321 intel_modeset_pipe_config(struct drm_crtc *crtc,
12322                           struct intel_crtc_state *pipe_config)
12323 {
12324         struct drm_atomic_state *state = pipe_config->base.state;
12325         struct intel_encoder *encoder;
12326         struct drm_connector *connector;
12327         struct drm_connector_state *connector_state;
12328         int base_bpp, ret = -EINVAL;
12329         int i;
12330         bool retry = true;
12331
12332         clear_intel_crtc_state(pipe_config);
12333
12334         pipe_config->cpu_transcoder =
12335                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12336
12337         /*
12338          * Sanitize sync polarity flags based on requested ones. If neither
12339          * positive or negative polarity is requested, treat this as meaning
12340          * negative polarity.
12341          */
12342         if (!(pipe_config->base.adjusted_mode.flags &
12343               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12344                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12345
12346         if (!(pipe_config->base.adjusted_mode.flags &
12347               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12348                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12349
12350         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12351                                              pipe_config);
12352         if (base_bpp < 0)
12353                 goto fail;
12354
12355         /*
12356          * Determine the real pipe dimensions. Note that stereo modes can
12357          * increase the actual pipe size due to the frame doubling and
12358          * insertion of additional space for blanks between the frame. This
12359          * is stored in the crtc timings. We use the requested mode to do this
12360          * computation to clearly distinguish it from the adjusted mode, which
12361          * can be changed by the connectors in the below retry loop.
12362          */
12363         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12364                                &pipe_config->pipe_src_w,
12365                                &pipe_config->pipe_src_h);
12366
12367 encoder_retry:
12368         /* Ensure the port clock defaults are reset when retrying. */
12369         pipe_config->port_clock = 0;
12370         pipe_config->pixel_multiplier = 1;
12371
12372         /* Fill in default crtc timings, allow encoders to overwrite them. */
12373         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12374                               CRTC_STEREO_DOUBLE);
12375
12376         /* Pass our mode to the connectors and the CRTC to give them a chance to
12377          * adjust it according to limitations or connector properties, and also
12378          * a chance to reject the mode entirely.
12379          */
12380         for_each_connector_in_state(state, connector, connector_state, i) {
12381                 if (connector_state->crtc != crtc)
12382                         continue;
12383
12384                 encoder = to_intel_encoder(connector_state->best_encoder);
12385
12386                 if (!(encoder->compute_config(encoder, pipe_config))) {
12387                         DRM_DEBUG_KMS("Encoder config failure\n");
12388                         goto fail;
12389                 }
12390         }
12391
12392         /* Set default port clock if not overwritten by the encoder. Needs to be
12393          * done afterwards in case the encoder adjusts the mode. */
12394         if (!pipe_config->port_clock)
12395                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12396                         * pipe_config->pixel_multiplier;
12397
12398         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12399         if (ret < 0) {
12400                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12401                 goto fail;
12402         }
12403
12404         if (ret == RETRY) {
12405                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12406                         ret = -EINVAL;
12407                         goto fail;
12408                 }
12409
12410                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12411                 retry = false;
12412                 goto encoder_retry;
12413         }
12414
12415         /* Dithering seems to not pass-through bits correctly when it should, so
12416          * only enable it on 6bpc panels. */
12417         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12418         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12419                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12420
12421 fail:
12422         return ret;
12423 }
12424
12425 static void
12426 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12427 {
12428         struct drm_crtc *crtc;
12429         struct drm_crtc_state *crtc_state;
12430         int i;
12431
12432         /* Double check state. */
12433         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12434                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12435
12436                 /* Update hwmode for vblank functions */
12437                 if (crtc->state->active)
12438                         crtc->hwmode = crtc->state->adjusted_mode;
12439                 else
12440                         crtc->hwmode.crtc_clock = 0;
12441
12442                 /*
12443                  * Update legacy state to satisfy fbc code. This can
12444                  * be removed when fbc uses the atomic state.
12445                  */
12446                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12447                         struct drm_plane_state *plane_state = crtc->primary->state;
12448
12449                         crtc->primary->fb = plane_state->fb;
12450                         crtc->x = plane_state->src_x >> 16;
12451                         crtc->y = plane_state->src_y >> 16;
12452                 }
12453         }
12454 }
12455
12456 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12457 {
12458         int diff;
12459
12460         if (clock1 == clock2)
12461                 return true;
12462
12463         if (!clock1 || !clock2)
12464                 return false;
12465
12466         diff = abs(clock1 - clock2);
12467
12468         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12469                 return true;
12470
12471         return false;
12472 }
12473
12474 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12475         list_for_each_entry((intel_crtc), \
12476                             &(dev)->mode_config.crtc_list, \
12477                             base.head) \
12478                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12479
12480 static bool
12481 intel_compare_m_n(unsigned int m, unsigned int n,
12482                   unsigned int m2, unsigned int n2,
12483                   bool exact)
12484 {
12485         if (m == m2 && n == n2)
12486                 return true;
12487
12488         if (exact || !m || !n || !m2 || !n2)
12489                 return false;
12490
12491         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12492
12493         if (n > n2) {
12494                 while (n > n2) {
12495                         m2 <<= 1;
12496                         n2 <<= 1;
12497                 }
12498         } else if (n < n2) {
12499                 while (n < n2) {
12500                         m <<= 1;
12501                         n <<= 1;
12502                 }
12503         }
12504
12505         if (n != n2)
12506                 return false;
12507
12508         return intel_fuzzy_clock_check(m, m2);
12509 }
12510
12511 static bool
12512 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12513                        struct intel_link_m_n *m2_n2,
12514                        bool adjust)
12515 {
12516         if (m_n->tu == m2_n2->tu &&
12517             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12518                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12519             intel_compare_m_n(m_n->link_m, m_n->link_n,
12520                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12521                 if (adjust)
12522                         *m2_n2 = *m_n;
12523
12524                 return true;
12525         }
12526
12527         return false;
12528 }
12529
12530 static bool
12531 intel_pipe_config_compare(struct drm_device *dev,
12532                           struct intel_crtc_state *current_config,
12533                           struct intel_crtc_state *pipe_config,
12534                           bool adjust)
12535 {
12536         bool ret = true;
12537
12538 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12539         do { \
12540                 if (!adjust) \
12541                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12542                 else \
12543                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12544         } while (0)
12545
12546 #define PIPE_CONF_CHECK_X(name) \
12547         if (current_config->name != pipe_config->name) { \
12548                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12549                           "(expected 0x%08x, found 0x%08x)\n", \
12550                           current_config->name, \
12551                           pipe_config->name); \
12552                 ret = false; \
12553         }
12554
12555 #define PIPE_CONF_CHECK_I(name) \
12556         if (current_config->name != pipe_config->name) { \
12557                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12558                           "(expected %i, found %i)\n", \
12559                           current_config->name, \
12560                           pipe_config->name); \
12561                 ret = false; \
12562         }
12563
12564 #define PIPE_CONF_CHECK_P(name) \
12565         if (current_config->name != pipe_config->name) { \
12566                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12567                           "(expected %p, found %p)\n", \
12568                           current_config->name, \
12569                           pipe_config->name); \
12570                 ret = false; \
12571         }
12572
12573 #define PIPE_CONF_CHECK_M_N(name) \
12574         if (!intel_compare_link_m_n(&current_config->name, \
12575                                     &pipe_config->name,\
12576                                     adjust)) { \
12577                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12578                           "(expected tu %i gmch %i/%i link %i/%i, " \
12579                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12580                           current_config->name.tu, \
12581                           current_config->name.gmch_m, \
12582                           current_config->name.gmch_n, \
12583                           current_config->name.link_m, \
12584                           current_config->name.link_n, \
12585                           pipe_config->name.tu, \
12586                           pipe_config->name.gmch_m, \
12587                           pipe_config->name.gmch_n, \
12588                           pipe_config->name.link_m, \
12589                           pipe_config->name.link_n); \
12590                 ret = false; \
12591         }
12592
12593 /* This is required for BDW+ where there is only one set of registers for
12594  * switching between high and low RR.
12595  * This macro can be used whenever a comparison has to be made between one
12596  * hw state and multiple sw state variables.
12597  */
12598 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12599         if (!intel_compare_link_m_n(&current_config->name, \
12600                                     &pipe_config->name, adjust) && \
12601             !intel_compare_link_m_n(&current_config->alt_name, \
12602                                     &pipe_config->name, adjust)) { \
12603                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12604                           "(expected tu %i gmch %i/%i link %i/%i, " \
12605                           "or tu %i gmch %i/%i link %i/%i, " \
12606                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12607                           current_config->name.tu, \
12608                           current_config->name.gmch_m, \
12609                           current_config->name.gmch_n, \
12610                           current_config->name.link_m, \
12611                           current_config->name.link_n, \
12612                           current_config->alt_name.tu, \
12613                           current_config->alt_name.gmch_m, \
12614                           current_config->alt_name.gmch_n, \
12615                           current_config->alt_name.link_m, \
12616                           current_config->alt_name.link_n, \
12617                           pipe_config->name.tu, \
12618                           pipe_config->name.gmch_m, \
12619                           pipe_config->name.gmch_n, \
12620                           pipe_config->name.link_m, \
12621                           pipe_config->name.link_n); \
12622                 ret = false; \
12623         }
12624
12625 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12626         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12627                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12628                           "(expected %i, found %i)\n", \
12629                           current_config->name & (mask), \
12630                           pipe_config->name & (mask)); \
12631                 ret = false; \
12632         }
12633
12634 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12635         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12636                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12637                           "(expected %i, found %i)\n", \
12638                           current_config->name, \
12639                           pipe_config->name); \
12640                 ret = false; \
12641         }
12642
12643 #define PIPE_CONF_QUIRK(quirk)  \
12644         ((current_config->quirks | pipe_config->quirks) & (quirk))
12645
12646         PIPE_CONF_CHECK_I(cpu_transcoder);
12647
12648         PIPE_CONF_CHECK_I(has_pch_encoder);
12649         PIPE_CONF_CHECK_I(fdi_lanes);
12650         PIPE_CONF_CHECK_M_N(fdi_m_n);
12651
12652         PIPE_CONF_CHECK_I(has_dp_encoder);
12653         PIPE_CONF_CHECK_I(lane_count);
12654
12655         if (INTEL_INFO(dev)->gen < 8) {
12656                 PIPE_CONF_CHECK_M_N(dp_m_n);
12657
12658                 if (current_config->has_drrs)
12659                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12660         } else
12661                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12662
12663         PIPE_CONF_CHECK_I(has_dsi_encoder);
12664
12665         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12666         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12667         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12668         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12669         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12670         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12671
12672         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12673         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12674         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12675         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12676         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12677         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12678
12679         PIPE_CONF_CHECK_I(pixel_multiplier);
12680         PIPE_CONF_CHECK_I(has_hdmi_sink);
12681         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12682             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12683                 PIPE_CONF_CHECK_I(limited_color_range);
12684         PIPE_CONF_CHECK_I(has_infoframe);
12685
12686         PIPE_CONF_CHECK_I(has_audio);
12687
12688         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12689                               DRM_MODE_FLAG_INTERLACE);
12690
12691         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12692                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12693                                       DRM_MODE_FLAG_PHSYNC);
12694                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12695                                       DRM_MODE_FLAG_NHSYNC);
12696                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12697                                       DRM_MODE_FLAG_PVSYNC);
12698                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12699                                       DRM_MODE_FLAG_NVSYNC);
12700         }
12701
12702         PIPE_CONF_CHECK_X(gmch_pfit.control);
12703         /* pfit ratios are autocomputed by the hw on gen4+ */
12704         if (INTEL_INFO(dev)->gen < 4)
12705                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12706         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12707
12708         if (!adjust) {
12709                 PIPE_CONF_CHECK_I(pipe_src_w);
12710                 PIPE_CONF_CHECK_I(pipe_src_h);
12711
12712                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12713                 if (current_config->pch_pfit.enabled) {
12714                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12715                         PIPE_CONF_CHECK_X(pch_pfit.size);
12716                 }
12717
12718                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12719         }
12720
12721         /* BDW+ don't expose a synchronous way to read the state */
12722         if (IS_HASWELL(dev))
12723                 PIPE_CONF_CHECK_I(ips_enabled);
12724
12725         PIPE_CONF_CHECK_I(double_wide);
12726
12727         PIPE_CONF_CHECK_X(ddi_pll_sel);
12728
12729         PIPE_CONF_CHECK_P(shared_dpll);
12730         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12731         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12732         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12733         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12734         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12735         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12736         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12737         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12738         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12739
12740         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12741                 PIPE_CONF_CHECK_I(pipe_bpp);
12742
12743         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12744         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12745
12746 #undef PIPE_CONF_CHECK_X
12747 #undef PIPE_CONF_CHECK_I
12748 #undef PIPE_CONF_CHECK_P
12749 #undef PIPE_CONF_CHECK_FLAGS
12750 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12751 #undef PIPE_CONF_QUIRK
12752 #undef INTEL_ERR_OR_DBG_KMS
12753
12754         return ret;
12755 }
12756
12757 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12758                                            const struct intel_crtc_state *pipe_config)
12759 {
12760         if (pipe_config->has_pch_encoder) {
12761                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12762                                                             &pipe_config->fdi_m_n);
12763                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12764
12765                 /*
12766                  * FDI already provided one idea for the dotclock.
12767                  * Yell if the encoder disagrees.
12768                  */
12769                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12770                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12771                      fdi_dotclock, dotclock);
12772         }
12773 }
12774
12775 static void verify_wm_state(struct drm_crtc *crtc,
12776                             struct drm_crtc_state *new_state)
12777 {
12778         struct drm_device *dev = crtc->dev;
12779         struct drm_i915_private *dev_priv = dev->dev_private;
12780         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12781         struct skl_ddb_entry *hw_entry, *sw_entry;
12782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12783         const enum pipe pipe = intel_crtc->pipe;
12784         int plane;
12785
12786         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12787                 return;
12788
12789         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12790         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12791
12792         /* planes */
12793         for_each_plane(dev_priv, pipe, plane) {
12794                 hw_entry = &hw_ddb.plane[pipe][plane];
12795                 sw_entry = &sw_ddb->plane[pipe][plane];
12796
12797                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12798                         continue;
12799
12800                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12801                           "(expected (%u,%u), found (%u,%u))\n",
12802                           pipe_name(pipe), plane + 1,
12803                           sw_entry->start, sw_entry->end,
12804                           hw_entry->start, hw_entry->end);
12805         }
12806
12807         /* cursor */
12808         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12809         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12810
12811         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12812                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12813                           "(expected (%u,%u), found (%u,%u))\n",
12814                           pipe_name(pipe),
12815                           sw_entry->start, sw_entry->end,
12816                           hw_entry->start, hw_entry->end);
12817         }
12818 }
12819
12820 static void
12821 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12822 {
12823         struct drm_connector *connector;
12824
12825         drm_for_each_connector(connector, dev) {
12826                 struct drm_encoder *encoder = connector->encoder;
12827                 struct drm_connector_state *state = connector->state;
12828
12829                 if (state->crtc != crtc)
12830                         continue;
12831
12832                 intel_connector_verify_state(to_intel_connector(connector));
12833
12834                 I915_STATE_WARN(state->best_encoder != encoder,
12835                      "connector's atomic encoder doesn't match legacy encoder\n");
12836         }
12837 }
12838
12839 static void
12840 verify_encoder_state(struct drm_device *dev)
12841 {
12842         struct intel_encoder *encoder;
12843         struct intel_connector *connector;
12844
12845         for_each_intel_encoder(dev, encoder) {
12846                 bool enabled = false;
12847                 enum pipe pipe;
12848
12849                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12850                               encoder->base.base.id,
12851                               encoder->base.name);
12852
12853                 for_each_intel_connector(dev, connector) {
12854                         if (connector->base.state->best_encoder != &encoder->base)
12855                                 continue;
12856                         enabled = true;
12857
12858                         I915_STATE_WARN(connector->base.state->crtc !=
12859                                         encoder->base.crtc,
12860                              "connector's crtc doesn't match encoder crtc\n");
12861                 }
12862
12863                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12864                      "encoder's enabled state mismatch "
12865                      "(expected %i, found %i)\n",
12866                      !!encoder->base.crtc, enabled);
12867
12868                 if (!encoder->base.crtc) {
12869                         bool active;
12870
12871                         active = encoder->get_hw_state(encoder, &pipe);
12872                         I915_STATE_WARN(active,
12873                              "encoder detached but still enabled on pipe %c.\n",
12874                              pipe_name(pipe));
12875                 }
12876         }
12877 }
12878
12879 static void
12880 verify_crtc_state(struct drm_crtc *crtc,
12881                   struct drm_crtc_state *old_crtc_state,
12882                   struct drm_crtc_state *new_crtc_state)
12883 {
12884         struct drm_device *dev = crtc->dev;
12885         struct drm_i915_private *dev_priv = dev->dev_private;
12886         struct intel_encoder *encoder;
12887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12888         struct intel_crtc_state *pipe_config, *sw_config;
12889         struct drm_atomic_state *old_state;
12890         bool active;
12891
12892         old_state = old_crtc_state->state;
12893         __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12894         pipe_config = to_intel_crtc_state(old_crtc_state);
12895         memset(pipe_config, 0, sizeof(*pipe_config));
12896         pipe_config->base.crtc = crtc;
12897         pipe_config->base.state = old_state;
12898
12899         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12900
12901         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12902
12903         /* hw state is inconsistent with the pipe quirk */
12904         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12905             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12906                 active = new_crtc_state->active;
12907
12908         I915_STATE_WARN(new_crtc_state->active != active,
12909              "crtc active state doesn't match with hw state "
12910              "(expected %i, found %i)\n", new_crtc_state->active, active);
12911
12912         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12913              "transitional active state does not match atomic hw state "
12914              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12915
12916         for_each_encoder_on_crtc(dev, crtc, encoder) {
12917                 enum pipe pipe;
12918
12919                 active = encoder->get_hw_state(encoder, &pipe);
12920                 I915_STATE_WARN(active != new_crtc_state->active,
12921                         "[ENCODER:%i] active %i with crtc active %i\n",
12922                         encoder->base.base.id, active, new_crtc_state->active);
12923
12924                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12925                                 "Encoder connected to wrong pipe %c\n",
12926                                 pipe_name(pipe));
12927
12928                 if (active)
12929                         encoder->get_config(encoder, pipe_config);
12930         }
12931
12932         if (!new_crtc_state->active)
12933                 return;
12934
12935         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12936
12937         sw_config = to_intel_crtc_state(crtc->state);
12938         if (!intel_pipe_config_compare(dev, sw_config,
12939                                        pipe_config, false)) {
12940                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12941                 intel_dump_pipe_config(intel_crtc, pipe_config,
12942                                        "[hw state]");
12943                 intel_dump_pipe_config(intel_crtc, sw_config,
12944                                        "[sw state]");
12945         }
12946 }
12947
12948 static void
12949 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12950                          struct intel_shared_dpll *pll,
12951                          struct drm_crtc *crtc,
12952                          struct drm_crtc_state *new_state)
12953 {
12954         struct intel_dpll_hw_state dpll_hw_state;
12955         unsigned crtc_mask;
12956         bool active;
12957
12958         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12959
12960         DRM_DEBUG_KMS("%s\n", pll->name);
12961
12962         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12963
12964         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12965                 I915_STATE_WARN(!pll->on && pll->active_mask,
12966                      "pll in active use but not on in sw tracking\n");
12967                 I915_STATE_WARN(pll->on && !pll->active_mask,
12968                      "pll is on but not used by any active crtc\n");
12969                 I915_STATE_WARN(pll->on != active,
12970                      "pll on state mismatch (expected %i, found %i)\n",
12971                      pll->on, active);
12972         }
12973
12974         if (!crtc) {
12975                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12976                                 "more active pll users than references: %x vs %x\n",
12977                                 pll->active_mask, pll->config.crtc_mask);
12978
12979                 return;
12980         }
12981
12982         crtc_mask = 1 << drm_crtc_index(crtc);
12983
12984         if (new_state->active)
12985                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12986                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12987                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12988         else
12989                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12990                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12991                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12992
12993         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12994                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12995                         crtc_mask, pll->config.crtc_mask);
12996
12997         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12998                                           &dpll_hw_state,
12999                                           sizeof(dpll_hw_state)),
13000                         "pll hw state mismatch\n");
13001 }
13002
13003 static void
13004 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13005                          struct drm_crtc_state *old_crtc_state,
13006                          struct drm_crtc_state *new_crtc_state)
13007 {
13008         struct drm_i915_private *dev_priv = dev->dev_private;
13009         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13010         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13011
13012         if (new_state->shared_dpll)
13013                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13014
13015         if (old_state->shared_dpll &&
13016             old_state->shared_dpll != new_state->shared_dpll) {
13017                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13018                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13019
13020                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13021                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13022                                 pipe_name(drm_crtc_index(crtc)));
13023                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13024                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13025                                 pipe_name(drm_crtc_index(crtc)));
13026         }
13027 }
13028
13029 static void
13030 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13031                          struct drm_crtc_state *old_state,
13032                          struct drm_crtc_state *new_state)
13033 {
13034         if (!needs_modeset(new_state) &&
13035             !to_intel_crtc_state(new_state)->update_pipe)
13036                 return;
13037
13038         verify_wm_state(crtc, new_state);
13039         verify_connector_state(crtc->dev, crtc);
13040         verify_crtc_state(crtc, old_state, new_state);
13041         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13042 }
13043
13044 static void
13045 verify_disabled_dpll_state(struct drm_device *dev)
13046 {
13047         struct drm_i915_private *dev_priv = dev->dev_private;
13048         int i;
13049
13050         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13051                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13052 }
13053
13054 static void
13055 intel_modeset_verify_disabled(struct drm_device *dev)
13056 {
13057         verify_encoder_state(dev);
13058         verify_connector_state(dev, NULL);
13059         verify_disabled_dpll_state(dev);
13060 }
13061
13062 static void update_scanline_offset(struct intel_crtc *crtc)
13063 {
13064         struct drm_device *dev = crtc->base.dev;
13065
13066         /*
13067          * The scanline counter increments at the leading edge of hsync.
13068          *
13069          * On most platforms it starts counting from vtotal-1 on the
13070          * first active line. That means the scanline counter value is
13071          * always one less than what we would expect. Ie. just after
13072          * start of vblank, which also occurs at start of hsync (on the
13073          * last active line), the scanline counter will read vblank_start-1.
13074          *
13075          * On gen2 the scanline counter starts counting from 1 instead
13076          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13077          * to keep the value positive), instead of adding one.
13078          *
13079          * On HSW+ the behaviour of the scanline counter depends on the output
13080          * type. For DP ports it behaves like most other platforms, but on HDMI
13081          * there's an extra 1 line difference. So we need to add two instead of
13082          * one to the value.
13083          */
13084         if (IS_GEN2(dev)) {
13085                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13086                 int vtotal;
13087
13088                 vtotal = adjusted_mode->crtc_vtotal;
13089                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13090                         vtotal /= 2;
13091
13092                 crtc->scanline_offset = vtotal - 1;
13093         } else if (HAS_DDI(dev) &&
13094                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13095                 crtc->scanline_offset = 2;
13096         } else
13097                 crtc->scanline_offset = 1;
13098 }
13099
13100 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13101 {
13102         struct drm_device *dev = state->dev;
13103         struct drm_i915_private *dev_priv = to_i915(dev);
13104         struct intel_shared_dpll_config *shared_dpll = NULL;
13105         struct drm_crtc *crtc;
13106         struct drm_crtc_state *crtc_state;
13107         int i;
13108
13109         if (!dev_priv->display.crtc_compute_clock)
13110                 return;
13111
13112         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13113                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13114                 struct intel_shared_dpll *old_dpll =
13115                         to_intel_crtc_state(crtc->state)->shared_dpll;
13116
13117                 if (!needs_modeset(crtc_state))
13118                         continue;
13119
13120                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13121
13122                 if (!old_dpll)
13123                         continue;
13124
13125                 if (!shared_dpll)
13126                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13127
13128                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13129         }
13130 }
13131
13132 /*
13133  * This implements the workaround described in the "notes" section of the mode
13134  * set sequence documentation. When going from no pipes or single pipe to
13135  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13136  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13137  */
13138 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13139 {
13140         struct drm_crtc_state *crtc_state;
13141         struct intel_crtc *intel_crtc;
13142         struct drm_crtc *crtc;
13143         struct intel_crtc_state *first_crtc_state = NULL;
13144         struct intel_crtc_state *other_crtc_state = NULL;
13145         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13146         int i;
13147
13148         /* look at all crtc's that are going to be enabled in during modeset */
13149         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13150                 intel_crtc = to_intel_crtc(crtc);
13151
13152                 if (!crtc_state->active || !needs_modeset(crtc_state))
13153                         continue;
13154
13155                 if (first_crtc_state) {
13156                         other_crtc_state = to_intel_crtc_state(crtc_state);
13157                         break;
13158                 } else {
13159                         first_crtc_state = to_intel_crtc_state(crtc_state);
13160                         first_pipe = intel_crtc->pipe;
13161                 }
13162         }
13163
13164         /* No workaround needed? */
13165         if (!first_crtc_state)
13166                 return 0;
13167
13168         /* w/a possibly needed, check how many crtc's are already enabled. */
13169         for_each_intel_crtc(state->dev, intel_crtc) {
13170                 struct intel_crtc_state *pipe_config;
13171
13172                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13173                 if (IS_ERR(pipe_config))
13174                         return PTR_ERR(pipe_config);
13175
13176                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13177
13178                 if (!pipe_config->base.active ||
13179                     needs_modeset(&pipe_config->base))
13180                         continue;
13181
13182                 /* 2 or more enabled crtcs means no need for w/a */
13183                 if (enabled_pipe != INVALID_PIPE)
13184                         return 0;
13185
13186                 enabled_pipe = intel_crtc->pipe;
13187         }
13188
13189         if (enabled_pipe != INVALID_PIPE)
13190                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13191         else if (other_crtc_state)
13192                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13193
13194         return 0;
13195 }
13196
13197 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13198 {
13199         struct drm_crtc *crtc;
13200         struct drm_crtc_state *crtc_state;
13201         int ret = 0;
13202
13203         /* add all active pipes to the state */
13204         for_each_crtc(state->dev, crtc) {
13205                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13206                 if (IS_ERR(crtc_state))
13207                         return PTR_ERR(crtc_state);
13208
13209                 if (!crtc_state->active || needs_modeset(crtc_state))
13210                         continue;
13211
13212                 crtc_state->mode_changed = true;
13213
13214                 ret = drm_atomic_add_affected_connectors(state, crtc);
13215                 if (ret)
13216                         break;
13217
13218                 ret = drm_atomic_add_affected_planes(state, crtc);
13219                 if (ret)
13220                         break;
13221         }
13222
13223         return ret;
13224 }
13225
13226 static int intel_modeset_checks(struct drm_atomic_state *state)
13227 {
13228         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13229         struct drm_i915_private *dev_priv = state->dev->dev_private;
13230         struct drm_crtc *crtc;
13231         struct drm_crtc_state *crtc_state;
13232         int ret = 0, i;
13233
13234         if (!check_digital_port_conflicts(state)) {
13235                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13236                 return -EINVAL;
13237         }
13238
13239         intel_state->modeset = true;
13240         intel_state->active_crtcs = dev_priv->active_crtcs;
13241
13242         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13243                 if (crtc_state->active)
13244                         intel_state->active_crtcs |= 1 << i;
13245                 else
13246                         intel_state->active_crtcs &= ~(1 << i);
13247         }
13248
13249         /*
13250          * See if the config requires any additional preparation, e.g.
13251          * to adjust global state with pipes off.  We need to do this
13252          * here so we can get the modeset_pipe updated config for the new
13253          * mode set on this crtc.  For other crtcs we need to use the
13254          * adjusted_mode bits in the crtc directly.
13255          */
13256         if (dev_priv->display.modeset_calc_cdclk) {
13257                 ret = dev_priv->display.modeset_calc_cdclk(state);
13258
13259                 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13260                         ret = intel_modeset_all_pipes(state);
13261
13262                 if (ret < 0)
13263                         return ret;
13264
13265                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13266                               intel_state->cdclk, intel_state->dev_cdclk);
13267         } else
13268                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13269
13270         intel_modeset_clear_plls(state);
13271
13272         if (IS_HASWELL(dev_priv))
13273                 return haswell_mode_set_planes_workaround(state);
13274
13275         return 0;
13276 }
13277
13278 /*
13279  * Handle calculation of various watermark data at the end of the atomic check
13280  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13281  * handlers to ensure that all derived state has been updated.
13282  */
13283 static void calc_watermark_data(struct drm_atomic_state *state)
13284 {
13285         struct drm_device *dev = state->dev;
13286         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13287         struct drm_crtc *crtc;
13288         struct drm_crtc_state *cstate;
13289         struct drm_plane *plane;
13290         struct drm_plane_state *pstate;
13291
13292         /*
13293          * Calculate watermark configuration details now that derived
13294          * plane/crtc state is all properly updated.
13295          */
13296         drm_for_each_crtc(crtc, dev) {
13297                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13298                         crtc->state;
13299
13300                 if (cstate->active)
13301                         intel_state->wm_config.num_pipes_active++;
13302         }
13303         drm_for_each_legacy_plane(plane, dev) {
13304                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13305                         plane->state;
13306
13307                 if (!to_intel_plane_state(pstate)->visible)
13308                         continue;
13309
13310                 intel_state->wm_config.sprites_enabled = true;
13311                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13312                     pstate->crtc_h != pstate->src_h >> 16)
13313                         intel_state->wm_config.sprites_scaled = true;
13314         }
13315 }
13316
13317 /**
13318  * intel_atomic_check - validate state object
13319  * @dev: drm device
13320  * @state: state to validate
13321  */
13322 static int intel_atomic_check(struct drm_device *dev,
13323                               struct drm_atomic_state *state)
13324 {
13325         struct drm_i915_private *dev_priv = to_i915(dev);
13326         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13327         struct drm_crtc *crtc;
13328         struct drm_crtc_state *crtc_state;
13329         int ret, i;
13330         bool any_ms = false;
13331
13332         ret = drm_atomic_helper_check_modeset(dev, state);
13333         if (ret)
13334                 return ret;
13335
13336         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13337                 struct intel_crtc_state *pipe_config =
13338                         to_intel_crtc_state(crtc_state);
13339
13340                 /* Catch I915_MODE_FLAG_INHERITED */
13341                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13342                         crtc_state->mode_changed = true;
13343
13344                 if (!crtc_state->enable) {
13345                         if (needs_modeset(crtc_state))
13346                                 any_ms = true;
13347                         continue;
13348                 }
13349
13350                 if (!needs_modeset(crtc_state))
13351                         continue;
13352
13353                 /* FIXME: For only active_changed we shouldn't need to do any
13354                  * state recomputation at all. */
13355
13356                 ret = drm_atomic_add_affected_connectors(state, crtc);
13357                 if (ret)
13358                         return ret;
13359
13360                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13361                 if (ret)
13362                         return ret;
13363
13364                 if (i915.fastboot &&
13365                     intel_pipe_config_compare(dev,
13366                                         to_intel_crtc_state(crtc->state),
13367                                         pipe_config, true)) {
13368                         crtc_state->mode_changed = false;
13369                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13370                 }
13371
13372                 if (needs_modeset(crtc_state)) {
13373                         any_ms = true;
13374
13375                         ret = drm_atomic_add_affected_planes(state, crtc);
13376                         if (ret)
13377                                 return ret;
13378                 }
13379
13380                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13381                                        needs_modeset(crtc_state) ?
13382                                        "[modeset]" : "[fastset]");
13383         }
13384
13385         if (any_ms) {
13386                 ret = intel_modeset_checks(state);
13387
13388                 if (ret)
13389                         return ret;
13390         } else
13391                 intel_state->cdclk = dev_priv->cdclk_freq;
13392
13393         ret = drm_atomic_helper_check_planes(dev, state);
13394         if (ret)
13395                 return ret;
13396
13397         intel_fbc_choose_crtc(dev_priv, state);
13398         calc_watermark_data(state);
13399
13400         return 0;
13401 }
13402
13403 static int intel_atomic_prepare_commit(struct drm_device *dev,
13404                                        struct drm_atomic_state *state,
13405                                        bool async)
13406 {
13407         struct drm_i915_private *dev_priv = dev->dev_private;
13408         struct drm_plane_state *plane_state;
13409         struct drm_crtc_state *crtc_state;
13410         struct drm_plane *plane;
13411         struct drm_crtc *crtc;
13412         int i, ret;
13413
13414         if (async) {
13415                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13416                 return -EINVAL;
13417         }
13418
13419         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13420                 ret = intel_crtc_wait_for_pending_flips(crtc);
13421                 if (ret)
13422                         return ret;
13423
13424                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13425                         flush_workqueue(dev_priv->wq);
13426         }
13427
13428         ret = mutex_lock_interruptible(&dev->struct_mutex);
13429         if (ret)
13430                 return ret;
13431
13432         ret = drm_atomic_helper_prepare_planes(dev, state);
13433         mutex_unlock(&dev->struct_mutex);
13434
13435         if (!ret && !async) {
13436                 for_each_plane_in_state(state, plane, plane_state, i) {
13437                         struct intel_plane_state *intel_plane_state =
13438                                 to_intel_plane_state(plane_state);
13439
13440                         if (!intel_plane_state->wait_req)
13441                                 continue;
13442
13443                         ret = __i915_wait_request(intel_plane_state->wait_req,
13444                                                   true, NULL, NULL);
13445                         if (ret) {
13446                                 /* Any hang should be swallowed by the wait */
13447                                 WARN_ON(ret == -EIO);
13448                                 mutex_lock(&dev->struct_mutex);
13449                                 drm_atomic_helper_cleanup_planes(dev, state);
13450                                 mutex_unlock(&dev->struct_mutex);
13451                                 break;
13452                         }
13453                 }
13454         }
13455
13456         return ret;
13457 }
13458
13459 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13460                                           struct drm_i915_private *dev_priv,
13461                                           unsigned crtc_mask)
13462 {
13463         unsigned last_vblank_count[I915_MAX_PIPES];
13464         enum pipe pipe;
13465         int ret;
13466
13467         if (!crtc_mask)
13468                 return;
13469
13470         for_each_pipe(dev_priv, pipe) {
13471                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13472
13473                 if (!((1 << pipe) & crtc_mask))
13474                         continue;
13475
13476                 ret = drm_crtc_vblank_get(crtc);
13477                 if (WARN_ON(ret != 0)) {
13478                         crtc_mask &= ~(1 << pipe);
13479                         continue;
13480                 }
13481
13482                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13483         }
13484
13485         for_each_pipe(dev_priv, pipe) {
13486                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13487                 long lret;
13488
13489                 if (!((1 << pipe) & crtc_mask))
13490                         continue;
13491
13492                 lret = wait_event_timeout(dev->vblank[pipe].queue,
13493                                 last_vblank_count[pipe] !=
13494                                         drm_crtc_vblank_count(crtc),
13495                                 msecs_to_jiffies(50));
13496
13497                 WARN_ON(!lret);
13498
13499                 drm_crtc_vblank_put(crtc);
13500         }
13501 }
13502
13503 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13504 {
13505         /* fb updated, need to unpin old fb */
13506         if (crtc_state->fb_changed)
13507                 return true;
13508
13509         /* wm changes, need vblank before final wm's */
13510         if (crtc_state->update_wm_post)
13511                 return true;
13512
13513         /*
13514          * cxsr is re-enabled after vblank.
13515          * This is already handled by crtc_state->update_wm_post,
13516          * but added for clarity.
13517          */
13518         if (crtc_state->disable_cxsr)
13519                 return true;
13520
13521         return false;
13522 }
13523
13524 /**
13525  * intel_atomic_commit - commit validated state object
13526  * @dev: DRM device
13527  * @state: the top-level driver state object
13528  * @async: asynchronous commit
13529  *
13530  * This function commits a top-level state object that has been validated
13531  * with drm_atomic_helper_check().
13532  *
13533  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13534  * we can only handle plane-related operations and do not yet support
13535  * asynchronous commit.
13536  *
13537  * RETURNS
13538  * Zero for success or -errno.
13539  */
13540 static int intel_atomic_commit(struct drm_device *dev,
13541                                struct drm_atomic_state *state,
13542                                bool async)
13543 {
13544         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13545         struct drm_i915_private *dev_priv = dev->dev_private;
13546         struct drm_crtc_state *old_crtc_state;
13547         struct drm_crtc *crtc;
13548         struct intel_crtc_state *intel_cstate;
13549         int ret = 0, i;
13550         bool hw_check = intel_state->modeset;
13551         unsigned long put_domains[I915_MAX_PIPES] = {};
13552         unsigned crtc_vblank_mask = 0;
13553
13554         ret = intel_atomic_prepare_commit(dev, state, async);
13555         if (ret) {
13556                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13557                 return ret;
13558         }
13559
13560         drm_atomic_helper_swap_state(dev, state);
13561         dev_priv->wm.config = intel_state->wm_config;
13562         intel_shared_dpll_commit(state);
13563
13564         if (intel_state->modeset) {
13565                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13566                        sizeof(intel_state->min_pixclk));
13567                 dev_priv->active_crtcs = intel_state->active_crtcs;
13568                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13569
13570                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13571         }
13572
13573         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13574                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13575
13576                 if (needs_modeset(crtc->state) ||
13577                     to_intel_crtc_state(crtc->state)->update_pipe) {
13578                         hw_check = true;
13579
13580                         put_domains[to_intel_crtc(crtc)->pipe] =
13581                                 modeset_get_crtc_power_domains(crtc,
13582                                         to_intel_crtc_state(crtc->state));
13583                 }
13584
13585                 if (!needs_modeset(crtc->state))
13586                         continue;
13587
13588                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13589
13590                 if (old_crtc_state->active) {
13591                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13592                         dev_priv->display.crtc_disable(crtc);
13593                         intel_crtc->active = false;
13594                         intel_fbc_disable(intel_crtc);
13595                         intel_disable_shared_dpll(intel_crtc);
13596
13597                         /*
13598                          * Underruns don't always raise
13599                          * interrupts, so check manually.
13600                          */
13601                         intel_check_cpu_fifo_underruns(dev_priv);
13602                         intel_check_pch_fifo_underruns(dev_priv);
13603
13604                         if (!crtc->state->active)
13605                                 intel_update_watermarks(crtc);
13606                 }
13607         }
13608
13609         /* Only after disabling all output pipelines that will be changed can we
13610          * update the the output configuration. */
13611         intel_modeset_update_crtc_state(state);
13612
13613         if (intel_state->modeset) {
13614                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13615
13616                 if (dev_priv->display.modeset_commit_cdclk &&
13617                     intel_state->dev_cdclk != dev_priv->cdclk_freq)
13618                         dev_priv->display.modeset_commit_cdclk(state);
13619
13620                 intel_modeset_verify_disabled(dev);
13621         }
13622
13623         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13624         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13625                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13626                 bool modeset = needs_modeset(crtc->state);
13627                 struct intel_crtc_state *pipe_config =
13628                         to_intel_crtc_state(crtc->state);
13629                 bool update_pipe = !modeset && pipe_config->update_pipe;
13630
13631                 if (modeset && crtc->state->active) {
13632                         update_scanline_offset(to_intel_crtc(crtc));
13633                         dev_priv->display.crtc_enable(crtc);
13634                 }
13635
13636                 if (!modeset)
13637                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13638
13639                 if (crtc->state->active &&
13640                     drm_atomic_get_existing_plane_state(state, crtc->primary))
13641                         intel_fbc_enable(intel_crtc);
13642
13643                 if (crtc->state->active &&
13644                     (crtc->state->planes_changed || update_pipe))
13645                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13646
13647                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13648                         crtc_vblank_mask |= 1 << i;
13649         }
13650
13651         /* FIXME: add subpixel order */
13652
13653         if (!state->legacy_cursor_update)
13654                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13655
13656         /*
13657          * Now that the vblank has passed, we can go ahead and program the
13658          * optimal watermarks on platforms that need two-step watermark
13659          * programming.
13660          *
13661          * TODO: Move this (and other cleanup) to an async worker eventually.
13662          */
13663         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13664                 intel_cstate = to_intel_crtc_state(crtc->state);
13665
13666                 if (dev_priv->display.optimize_watermarks)
13667                         dev_priv->display.optimize_watermarks(intel_cstate);
13668         }
13669
13670         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13671                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13672
13673                 if (put_domains[i])
13674                         modeset_put_power_domains(dev_priv, put_domains[i]);
13675
13676                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13677         }
13678
13679         if (intel_state->modeset)
13680                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13681
13682         mutex_lock(&dev->struct_mutex);
13683         drm_atomic_helper_cleanup_planes(dev, state);
13684         mutex_unlock(&dev->struct_mutex);
13685
13686         drm_atomic_state_free(state);
13687
13688         /* As one of the primary mmio accessors, KMS has a high likelihood
13689          * of triggering bugs in unclaimed access. After we finish
13690          * modesetting, see if an error has been flagged, and if so
13691          * enable debugging for the next modeset - and hope we catch
13692          * the culprit.
13693          *
13694          * XXX note that we assume display power is on at this point.
13695          * This might hold true now but we need to add pm helper to check
13696          * unclaimed only when the hardware is on, as atomic commits
13697          * can happen also when the device is completely off.
13698          */
13699         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13700
13701         return 0;
13702 }
13703
13704 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13705 {
13706         struct drm_device *dev = crtc->dev;
13707         struct drm_atomic_state *state;
13708         struct drm_crtc_state *crtc_state;
13709         int ret;
13710
13711         state = drm_atomic_state_alloc(dev);
13712         if (!state) {
13713                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13714                               crtc->base.id);
13715                 return;
13716         }
13717
13718         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13719
13720 retry:
13721         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13722         ret = PTR_ERR_OR_ZERO(crtc_state);
13723         if (!ret) {
13724                 if (!crtc_state->active)
13725                         goto out;
13726
13727                 crtc_state->mode_changed = true;
13728                 ret = drm_atomic_commit(state);
13729         }
13730
13731         if (ret == -EDEADLK) {
13732                 drm_atomic_state_clear(state);
13733                 drm_modeset_backoff(state->acquire_ctx);
13734                 goto retry;
13735         }
13736
13737         if (ret)
13738 out:
13739                 drm_atomic_state_free(state);
13740 }
13741
13742 #undef for_each_intel_crtc_masked
13743
13744 static const struct drm_crtc_funcs intel_crtc_funcs = {
13745         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13746         .set_config = drm_atomic_helper_set_config,
13747         .set_property = drm_atomic_helper_crtc_set_property,
13748         .destroy = intel_crtc_destroy,
13749         .page_flip = intel_crtc_page_flip,
13750         .atomic_duplicate_state = intel_crtc_duplicate_state,
13751         .atomic_destroy_state = intel_crtc_destroy_state,
13752 };
13753
13754 /**
13755  * intel_prepare_plane_fb - Prepare fb for usage on plane
13756  * @plane: drm plane to prepare for
13757  * @fb: framebuffer to prepare for presentation
13758  *
13759  * Prepares a framebuffer for usage on a display plane.  Generally this
13760  * involves pinning the underlying object and updating the frontbuffer tracking
13761  * bits.  Some older platforms need special physical address handling for
13762  * cursor planes.
13763  *
13764  * Must be called with struct_mutex held.
13765  *
13766  * Returns 0 on success, negative error code on failure.
13767  */
13768 int
13769 intel_prepare_plane_fb(struct drm_plane *plane,
13770                        const struct drm_plane_state *new_state)
13771 {
13772         struct drm_device *dev = plane->dev;
13773         struct drm_framebuffer *fb = new_state->fb;
13774         struct intel_plane *intel_plane = to_intel_plane(plane);
13775         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13776         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13777         int ret = 0;
13778
13779         if (!obj && !old_obj)
13780                 return 0;
13781
13782         if (old_obj) {
13783                 struct drm_crtc_state *crtc_state =
13784                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13785
13786                 /* Big Hammer, we also need to ensure that any pending
13787                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13788                  * current scanout is retired before unpinning the old
13789                  * framebuffer. Note that we rely on userspace rendering
13790                  * into the buffer attached to the pipe they are waiting
13791                  * on. If not, userspace generates a GPU hang with IPEHR
13792                  * point to the MI_WAIT_FOR_EVENT.
13793                  *
13794                  * This should only fail upon a hung GPU, in which case we
13795                  * can safely continue.
13796                  */
13797                 if (needs_modeset(crtc_state))
13798                         ret = i915_gem_object_wait_rendering(old_obj, true);
13799                 if (ret) {
13800                         /* GPU hangs should have been swallowed by the wait */
13801                         WARN_ON(ret == -EIO);
13802                         return ret;
13803                 }
13804         }
13805
13806         /* For framebuffer backed by dmabuf, wait for fence */
13807         if (obj && obj->base.dma_buf) {
13808                 long lret;
13809
13810                 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13811                                                            false, true,
13812                                                            MAX_SCHEDULE_TIMEOUT);
13813                 if (lret == -ERESTARTSYS)
13814                         return lret;
13815
13816                 WARN(lret < 0, "waiting returns %li\n", lret);
13817         }
13818
13819         if (!obj) {
13820                 ret = 0;
13821         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13822             INTEL_INFO(dev)->cursor_needs_physical) {
13823                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13824                 ret = i915_gem_object_attach_phys(obj, align);
13825                 if (ret)
13826                         DRM_DEBUG_KMS("failed to attach phys object\n");
13827         } else {
13828                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13829         }
13830
13831         if (ret == 0) {
13832                 if (obj) {
13833                         struct intel_plane_state *plane_state =
13834                                 to_intel_plane_state(new_state);
13835
13836                         i915_gem_request_assign(&plane_state->wait_req,
13837                                                 obj->last_write_req);
13838                 }
13839
13840                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13841         }
13842
13843         return ret;
13844 }
13845
13846 /**
13847  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13848  * @plane: drm plane to clean up for
13849  * @fb: old framebuffer that was on plane
13850  *
13851  * Cleans up a framebuffer that has just been removed from a plane.
13852  *
13853  * Must be called with struct_mutex held.
13854  */
13855 void
13856 intel_cleanup_plane_fb(struct drm_plane *plane,
13857                        const struct drm_plane_state *old_state)
13858 {
13859         struct drm_device *dev = plane->dev;
13860         struct intel_plane *intel_plane = to_intel_plane(plane);
13861         struct intel_plane_state *old_intel_state;
13862         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13863         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13864
13865         old_intel_state = to_intel_plane_state(old_state);
13866
13867         if (!obj && !old_obj)
13868                 return;
13869
13870         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13871             !INTEL_INFO(dev)->cursor_needs_physical))
13872                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13873
13874         /* prepare_fb aborted? */
13875         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13876             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13877                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13878
13879         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13880 }
13881
13882 int
13883 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13884 {
13885         int max_scale;
13886         struct drm_device *dev;
13887         struct drm_i915_private *dev_priv;
13888         int crtc_clock, cdclk;
13889
13890         if (!intel_crtc || !crtc_state->base.enable)
13891                 return DRM_PLANE_HELPER_NO_SCALING;
13892
13893         dev = intel_crtc->base.dev;
13894         dev_priv = dev->dev_private;
13895         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13896         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13897
13898         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13899                 return DRM_PLANE_HELPER_NO_SCALING;
13900
13901         /*
13902          * skl max scale is lower of:
13903          *    close to 3 but not 3, -1 is for that purpose
13904          *            or
13905          *    cdclk/crtc_clock
13906          */
13907         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13908
13909         return max_scale;
13910 }
13911
13912 static int
13913 intel_check_primary_plane(struct drm_plane *plane,
13914                           struct intel_crtc_state *crtc_state,
13915                           struct intel_plane_state *state)
13916 {
13917         struct drm_crtc *crtc = state->base.crtc;
13918         struct drm_framebuffer *fb = state->base.fb;
13919         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13920         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13921         bool can_position = false;
13922
13923         if (INTEL_INFO(plane->dev)->gen >= 9) {
13924                 /* use scaler when colorkey is not required */
13925                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13926                         min_scale = 1;
13927                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13928                 }
13929                 can_position = true;
13930         }
13931
13932         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13933                                              &state->dst, &state->clip,
13934                                              min_scale, max_scale,
13935                                              can_position, true,
13936                                              &state->visible);
13937 }
13938
13939 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13940                                     struct drm_crtc_state *old_crtc_state)
13941 {
13942         struct drm_device *dev = crtc->dev;
13943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13944         struct intel_crtc_state *old_intel_state =
13945                 to_intel_crtc_state(old_crtc_state);
13946         bool modeset = needs_modeset(crtc->state);
13947
13948         /* Perform vblank evasion around commit operation */
13949         intel_pipe_update_start(intel_crtc);
13950
13951         if (modeset)
13952                 return;
13953
13954         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13955                 intel_color_set_csc(crtc->state);
13956                 intel_color_load_luts(crtc->state);
13957         }
13958
13959         if (to_intel_crtc_state(crtc->state)->update_pipe)
13960                 intel_update_pipe_config(intel_crtc, old_intel_state);
13961         else if (INTEL_INFO(dev)->gen >= 9)
13962                 skl_detach_scalers(intel_crtc);
13963 }
13964
13965 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13966                                      struct drm_crtc_state *old_crtc_state)
13967 {
13968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13969
13970         intel_pipe_update_end(intel_crtc);
13971 }
13972
13973 /**
13974  * intel_plane_destroy - destroy a plane
13975  * @plane: plane to destroy
13976  *
13977  * Common destruction function for all types of planes (primary, cursor,
13978  * sprite).
13979  */
13980 void intel_plane_destroy(struct drm_plane *plane)
13981 {
13982         struct intel_plane *intel_plane = to_intel_plane(plane);
13983         drm_plane_cleanup(plane);
13984         kfree(intel_plane);
13985 }
13986
13987 const struct drm_plane_funcs intel_plane_funcs = {
13988         .update_plane = drm_atomic_helper_update_plane,
13989         .disable_plane = drm_atomic_helper_disable_plane,
13990         .destroy = intel_plane_destroy,
13991         .set_property = drm_atomic_helper_plane_set_property,
13992         .atomic_get_property = intel_plane_atomic_get_property,
13993         .atomic_set_property = intel_plane_atomic_set_property,
13994         .atomic_duplicate_state = intel_plane_duplicate_state,
13995         .atomic_destroy_state = intel_plane_destroy_state,
13996
13997 };
13998
13999 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14000                                                     int pipe)
14001 {
14002         struct intel_plane *primary = NULL;
14003         struct intel_plane_state *state = NULL;
14004         const uint32_t *intel_primary_formats;
14005         unsigned int num_formats;
14006         int ret;
14007
14008         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14009         if (!primary)
14010                 goto fail;
14011
14012         state = intel_create_plane_state(&primary->base);
14013         if (!state)
14014                 goto fail;
14015         primary->base.state = &state->base;
14016
14017         primary->can_scale = false;
14018         primary->max_downscale = 1;
14019         if (INTEL_INFO(dev)->gen >= 9) {
14020                 primary->can_scale = true;
14021                 state->scaler_id = -1;
14022         }
14023         primary->pipe = pipe;
14024         primary->plane = pipe;
14025         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14026         primary->check_plane = intel_check_primary_plane;
14027         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14028                 primary->plane = !pipe;
14029
14030         if (INTEL_INFO(dev)->gen >= 9) {
14031                 intel_primary_formats = skl_primary_formats;
14032                 num_formats = ARRAY_SIZE(skl_primary_formats);
14033
14034                 primary->update_plane = skylake_update_primary_plane;
14035                 primary->disable_plane = skylake_disable_primary_plane;
14036         } else if (HAS_PCH_SPLIT(dev)) {
14037                 intel_primary_formats = i965_primary_formats;
14038                 num_formats = ARRAY_SIZE(i965_primary_formats);
14039
14040                 primary->update_plane = ironlake_update_primary_plane;
14041                 primary->disable_plane = i9xx_disable_primary_plane;
14042         } else if (INTEL_INFO(dev)->gen >= 4) {
14043                 intel_primary_formats = i965_primary_formats;
14044                 num_formats = ARRAY_SIZE(i965_primary_formats);
14045
14046                 primary->update_plane = i9xx_update_primary_plane;
14047                 primary->disable_plane = i9xx_disable_primary_plane;
14048         } else {
14049                 intel_primary_formats = i8xx_primary_formats;
14050                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14051
14052                 primary->update_plane = i9xx_update_primary_plane;
14053                 primary->disable_plane = i9xx_disable_primary_plane;
14054         }
14055
14056         ret = drm_universal_plane_init(dev, &primary->base, 0,
14057                                        &intel_plane_funcs,
14058                                        intel_primary_formats, num_formats,
14059                                        DRM_PLANE_TYPE_PRIMARY, NULL);
14060         if (ret)
14061                 goto fail;
14062
14063         if (INTEL_INFO(dev)->gen >= 4)
14064                 intel_create_rotation_property(dev, primary);
14065
14066         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14067
14068         return &primary->base;
14069
14070 fail:
14071         kfree(state);
14072         kfree(primary);
14073
14074         return NULL;
14075 }
14076
14077 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14078 {
14079         if (!dev->mode_config.rotation_property) {
14080                 unsigned long flags = BIT(DRM_ROTATE_0) |
14081                         BIT(DRM_ROTATE_180);
14082
14083                 if (INTEL_INFO(dev)->gen >= 9)
14084                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14085
14086                 dev->mode_config.rotation_property =
14087                         drm_mode_create_rotation_property(dev, flags);
14088         }
14089         if (dev->mode_config.rotation_property)
14090                 drm_object_attach_property(&plane->base.base,
14091                                 dev->mode_config.rotation_property,
14092                                 plane->base.state->rotation);
14093 }
14094
14095 static int
14096 intel_check_cursor_plane(struct drm_plane *plane,
14097                          struct intel_crtc_state *crtc_state,
14098                          struct intel_plane_state *state)
14099 {
14100         struct drm_crtc *crtc = crtc_state->base.crtc;
14101         struct drm_framebuffer *fb = state->base.fb;
14102         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14103         enum pipe pipe = to_intel_plane(plane)->pipe;
14104         unsigned stride;
14105         int ret;
14106
14107         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14108                                             &state->dst, &state->clip,
14109                                             DRM_PLANE_HELPER_NO_SCALING,
14110                                             DRM_PLANE_HELPER_NO_SCALING,
14111                                             true, true, &state->visible);
14112         if (ret)
14113                 return ret;
14114
14115         /* if we want to turn off the cursor ignore width and height */
14116         if (!obj)
14117                 return 0;
14118
14119         /* Check for which cursor types we support */
14120         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14121                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14122                           state->base.crtc_w, state->base.crtc_h);
14123                 return -EINVAL;
14124         }
14125
14126         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14127         if (obj->base.size < stride * state->base.crtc_h) {
14128                 DRM_DEBUG_KMS("buffer is too small\n");
14129                 return -ENOMEM;
14130         }
14131
14132         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14133                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14134                 return -EINVAL;
14135         }
14136
14137         /*
14138          * There's something wrong with the cursor on CHV pipe C.
14139          * If it straddles the left edge of the screen then
14140          * moving it away from the edge or disabling it often
14141          * results in a pipe underrun, and often that can lead to
14142          * dead pipe (constant underrun reported, and it scans
14143          * out just a solid color). To recover from that, the
14144          * display power well must be turned off and on again.
14145          * Refuse the put the cursor into that compromised position.
14146          */
14147         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14148             state->visible && state->base.crtc_x < 0) {
14149                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14150                 return -EINVAL;
14151         }
14152
14153         return 0;
14154 }
14155
14156 static void
14157 intel_disable_cursor_plane(struct drm_plane *plane,
14158                            struct drm_crtc *crtc)
14159 {
14160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14161
14162         intel_crtc->cursor_addr = 0;
14163         intel_crtc_update_cursor(crtc, NULL);
14164 }
14165
14166 static void
14167 intel_update_cursor_plane(struct drm_plane *plane,
14168                           const struct intel_crtc_state *crtc_state,
14169                           const struct intel_plane_state *state)
14170 {
14171         struct drm_crtc *crtc = crtc_state->base.crtc;
14172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14173         struct drm_device *dev = plane->dev;
14174         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14175         uint32_t addr;
14176
14177         if (!obj)
14178                 addr = 0;
14179         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14180                 addr = i915_gem_obj_ggtt_offset(obj);
14181         else
14182                 addr = obj->phys_handle->busaddr;
14183
14184         intel_crtc->cursor_addr = addr;
14185         intel_crtc_update_cursor(crtc, state);
14186 }
14187
14188 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14189                                                    int pipe)
14190 {
14191         struct intel_plane *cursor = NULL;
14192         struct intel_plane_state *state = NULL;
14193         int ret;
14194
14195         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14196         if (!cursor)
14197                 goto fail;
14198
14199         state = intel_create_plane_state(&cursor->base);
14200         if (!state)
14201                 goto fail;
14202         cursor->base.state = &state->base;
14203
14204         cursor->can_scale = false;
14205         cursor->max_downscale = 1;
14206         cursor->pipe = pipe;
14207         cursor->plane = pipe;
14208         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14209         cursor->check_plane = intel_check_cursor_plane;
14210         cursor->update_plane = intel_update_cursor_plane;
14211         cursor->disable_plane = intel_disable_cursor_plane;
14212
14213         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14214                                        &intel_plane_funcs,
14215                                        intel_cursor_formats,
14216                                        ARRAY_SIZE(intel_cursor_formats),
14217                                        DRM_PLANE_TYPE_CURSOR, NULL);
14218         if (ret)
14219                 goto fail;
14220
14221         if (INTEL_INFO(dev)->gen >= 4) {
14222                 if (!dev->mode_config.rotation_property)
14223                         dev->mode_config.rotation_property =
14224                                 drm_mode_create_rotation_property(dev,
14225                                                         BIT(DRM_ROTATE_0) |
14226                                                         BIT(DRM_ROTATE_180));
14227                 if (dev->mode_config.rotation_property)
14228                         drm_object_attach_property(&cursor->base.base,
14229                                 dev->mode_config.rotation_property,
14230                                 state->base.rotation);
14231         }
14232
14233         if (INTEL_INFO(dev)->gen >=9)
14234                 state->scaler_id = -1;
14235
14236         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14237
14238         return &cursor->base;
14239
14240 fail:
14241         kfree(state);
14242         kfree(cursor);
14243
14244         return NULL;
14245 }
14246
14247 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14248         struct intel_crtc_state *crtc_state)
14249 {
14250         int i;
14251         struct intel_scaler *intel_scaler;
14252         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14253
14254         for (i = 0; i < intel_crtc->num_scalers; i++) {
14255                 intel_scaler = &scaler_state->scalers[i];
14256                 intel_scaler->in_use = 0;
14257                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14258         }
14259
14260         scaler_state->scaler_id = -1;
14261 }
14262
14263 static void intel_crtc_init(struct drm_device *dev, int pipe)
14264 {
14265         struct drm_i915_private *dev_priv = dev->dev_private;
14266         struct intel_crtc *intel_crtc;
14267         struct intel_crtc_state *crtc_state = NULL;
14268         struct drm_plane *primary = NULL;
14269         struct drm_plane *cursor = NULL;
14270         int ret;
14271
14272         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14273         if (intel_crtc == NULL)
14274                 return;
14275
14276         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14277         if (!crtc_state)
14278                 goto fail;
14279         intel_crtc->config = crtc_state;
14280         intel_crtc->base.state = &crtc_state->base;
14281         crtc_state->base.crtc = &intel_crtc->base;
14282
14283         /* initialize shared scalers */
14284         if (INTEL_INFO(dev)->gen >= 9) {
14285                 if (pipe == PIPE_C)
14286                         intel_crtc->num_scalers = 1;
14287                 else
14288                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14289
14290                 skl_init_scalers(dev, intel_crtc, crtc_state);
14291         }
14292
14293         primary = intel_primary_plane_create(dev, pipe);
14294         if (!primary)
14295                 goto fail;
14296
14297         cursor = intel_cursor_plane_create(dev, pipe);
14298         if (!cursor)
14299                 goto fail;
14300
14301         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14302                                         cursor, &intel_crtc_funcs, NULL);
14303         if (ret)
14304                 goto fail;
14305
14306         /*
14307          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14308          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14309          */
14310         intel_crtc->pipe = pipe;
14311         intel_crtc->plane = pipe;
14312         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14313                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14314                 intel_crtc->plane = !pipe;
14315         }
14316
14317         intel_crtc->cursor_base = ~0;
14318         intel_crtc->cursor_cntl = ~0;
14319         intel_crtc->cursor_size = ~0;
14320
14321         intel_crtc->wm.cxsr_allowed = true;
14322
14323         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14324                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14325         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14326         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14327
14328         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14329
14330         intel_color_init(&intel_crtc->base);
14331
14332         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14333         return;
14334
14335 fail:
14336         if (primary)
14337                 drm_plane_cleanup(primary);
14338         if (cursor)
14339                 drm_plane_cleanup(cursor);
14340         kfree(crtc_state);
14341         kfree(intel_crtc);
14342 }
14343
14344 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14345 {
14346         struct drm_encoder *encoder = connector->base.encoder;
14347         struct drm_device *dev = connector->base.dev;
14348
14349         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14350
14351         if (!encoder || WARN_ON(!encoder->crtc))
14352                 return INVALID_PIPE;
14353
14354         return to_intel_crtc(encoder->crtc)->pipe;
14355 }
14356
14357 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14358                                 struct drm_file *file)
14359 {
14360         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14361         struct drm_crtc *drmmode_crtc;
14362         struct intel_crtc *crtc;
14363
14364         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14365
14366         if (!drmmode_crtc) {
14367                 DRM_ERROR("no such CRTC id\n");
14368                 return -ENOENT;
14369         }
14370
14371         crtc = to_intel_crtc(drmmode_crtc);
14372         pipe_from_crtc_id->pipe = crtc->pipe;
14373
14374         return 0;
14375 }
14376
14377 static int intel_encoder_clones(struct intel_encoder *encoder)
14378 {
14379         struct drm_device *dev = encoder->base.dev;
14380         struct intel_encoder *source_encoder;
14381         int index_mask = 0;
14382         int entry = 0;
14383
14384         for_each_intel_encoder(dev, source_encoder) {
14385                 if (encoders_cloneable(encoder, source_encoder))
14386                         index_mask |= (1 << entry);
14387
14388                 entry++;
14389         }
14390
14391         return index_mask;
14392 }
14393
14394 static bool has_edp_a(struct drm_device *dev)
14395 {
14396         struct drm_i915_private *dev_priv = dev->dev_private;
14397
14398         if (!IS_MOBILE(dev))
14399                 return false;
14400
14401         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14402                 return false;
14403
14404         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14405                 return false;
14406
14407         return true;
14408 }
14409
14410 static bool intel_crt_present(struct drm_device *dev)
14411 {
14412         struct drm_i915_private *dev_priv = dev->dev_private;
14413
14414         if (INTEL_INFO(dev)->gen >= 9)
14415                 return false;
14416
14417         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14418                 return false;
14419
14420         if (IS_CHERRYVIEW(dev))
14421                 return false;
14422
14423         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14424                 return false;
14425
14426         /* DDI E can't be used if DDI A requires 4 lanes */
14427         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14428                 return false;
14429
14430         if (!dev_priv->vbt.int_crt_support)
14431                 return false;
14432
14433         return true;
14434 }
14435
14436 static void intel_setup_outputs(struct drm_device *dev)
14437 {
14438         struct drm_i915_private *dev_priv = dev->dev_private;
14439         struct intel_encoder *encoder;
14440         bool dpd_is_edp = false;
14441
14442         intel_lvds_init(dev);
14443
14444         if (intel_crt_present(dev))
14445                 intel_crt_init(dev);
14446
14447         if (IS_BROXTON(dev)) {
14448                 /*
14449                  * FIXME: Broxton doesn't support port detection via the
14450                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14451                  * detect the ports.
14452                  */
14453                 intel_ddi_init(dev, PORT_A);
14454                 intel_ddi_init(dev, PORT_B);
14455                 intel_ddi_init(dev, PORT_C);
14456
14457                 intel_dsi_init(dev);
14458         } else if (HAS_DDI(dev)) {
14459                 int found;
14460
14461                 /*
14462                  * Haswell uses DDI functions to detect digital outputs.
14463                  * On SKL pre-D0 the strap isn't connected, so we assume
14464                  * it's there.
14465                  */
14466                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14467                 /* WaIgnoreDDIAStrap: skl */
14468                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14469                         intel_ddi_init(dev, PORT_A);
14470
14471                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14472                  * register */
14473                 found = I915_READ(SFUSE_STRAP);
14474
14475                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14476                         intel_ddi_init(dev, PORT_B);
14477                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14478                         intel_ddi_init(dev, PORT_C);
14479                 if (found & SFUSE_STRAP_DDID_DETECTED)
14480                         intel_ddi_init(dev, PORT_D);
14481                 /*
14482                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14483                  */
14484                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14485                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14486                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14487                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14488                         intel_ddi_init(dev, PORT_E);
14489
14490         } else if (HAS_PCH_SPLIT(dev)) {
14491                 int found;
14492                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14493
14494                 if (has_edp_a(dev))
14495                         intel_dp_init(dev, DP_A, PORT_A);
14496
14497                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14498                         /* PCH SDVOB multiplex with HDMIB */
14499                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14500                         if (!found)
14501                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14502                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14503                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14504                 }
14505
14506                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14507                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14508
14509                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14510                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14511
14512                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14513                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14514
14515                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14516                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14517         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14518                 /*
14519                  * The DP_DETECTED bit is the latched state of the DDC
14520                  * SDA pin at boot. However since eDP doesn't require DDC
14521                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14522                  * eDP ports may have been muxed to an alternate function.
14523                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14524                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14525                  * detect eDP ports.
14526                  */
14527                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14528                     !intel_dp_is_edp(dev, PORT_B))
14529                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14530                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14531                     intel_dp_is_edp(dev, PORT_B))
14532                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14533
14534                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14535                     !intel_dp_is_edp(dev, PORT_C))
14536                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14537                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14538                     intel_dp_is_edp(dev, PORT_C))
14539                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14540
14541                 if (IS_CHERRYVIEW(dev)) {
14542                         /* eDP not supported on port D, so don't check VBT */
14543                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14544                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14545                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14546                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14547                 }
14548
14549                 intel_dsi_init(dev);
14550         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14551                 bool found = false;
14552
14553                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14554                         DRM_DEBUG_KMS("probing SDVOB\n");
14555                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14556                         if (!found && IS_G4X(dev)) {
14557                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14558                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14559                         }
14560
14561                         if (!found && IS_G4X(dev))
14562                                 intel_dp_init(dev, DP_B, PORT_B);
14563                 }
14564
14565                 /* Before G4X SDVOC doesn't have its own detect register */
14566
14567                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14568                         DRM_DEBUG_KMS("probing SDVOC\n");
14569                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14570                 }
14571
14572                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14573
14574                         if (IS_G4X(dev)) {
14575                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14576                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14577                         }
14578                         if (IS_G4X(dev))
14579                                 intel_dp_init(dev, DP_C, PORT_C);
14580                 }
14581
14582                 if (IS_G4X(dev) &&
14583                     (I915_READ(DP_D) & DP_DETECTED))
14584                         intel_dp_init(dev, DP_D, PORT_D);
14585         } else if (IS_GEN2(dev))
14586                 intel_dvo_init(dev);
14587
14588         if (SUPPORTS_TV(dev))
14589                 intel_tv_init(dev);
14590
14591         intel_psr_init(dev);
14592
14593         for_each_intel_encoder(dev, encoder) {
14594                 encoder->base.possible_crtcs = encoder->crtc_mask;
14595                 encoder->base.possible_clones =
14596                         intel_encoder_clones(encoder);
14597         }
14598
14599         intel_init_pch_refclk(dev);
14600
14601         drm_helper_move_panel_connectors_to_head(dev);
14602 }
14603
14604 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14605 {
14606         struct drm_device *dev = fb->dev;
14607         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14608
14609         drm_framebuffer_cleanup(fb);
14610         mutex_lock(&dev->struct_mutex);
14611         WARN_ON(!intel_fb->obj->framebuffer_references--);
14612         drm_gem_object_unreference(&intel_fb->obj->base);
14613         mutex_unlock(&dev->struct_mutex);
14614         kfree(intel_fb);
14615 }
14616
14617 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14618                                                 struct drm_file *file,
14619                                                 unsigned int *handle)
14620 {
14621         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14622         struct drm_i915_gem_object *obj = intel_fb->obj;
14623
14624         if (obj->userptr.mm) {
14625                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14626                 return -EINVAL;
14627         }
14628
14629         return drm_gem_handle_create(file, &obj->base, handle);
14630 }
14631
14632 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14633                                         struct drm_file *file,
14634                                         unsigned flags, unsigned color,
14635                                         struct drm_clip_rect *clips,
14636                                         unsigned num_clips)
14637 {
14638         struct drm_device *dev = fb->dev;
14639         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14640         struct drm_i915_gem_object *obj = intel_fb->obj;
14641
14642         mutex_lock(&dev->struct_mutex);
14643         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14644         mutex_unlock(&dev->struct_mutex);
14645
14646         return 0;
14647 }
14648
14649 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14650         .destroy = intel_user_framebuffer_destroy,
14651         .create_handle = intel_user_framebuffer_create_handle,
14652         .dirty = intel_user_framebuffer_dirty,
14653 };
14654
14655 static
14656 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14657                          uint32_t pixel_format)
14658 {
14659         u32 gen = INTEL_INFO(dev)->gen;
14660
14661         if (gen >= 9) {
14662                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14663
14664                 /* "The stride in bytes must not exceed the of the size of 8K
14665                  *  pixels and 32K bytes."
14666                  */
14667                 return min(8192 * cpp, 32768);
14668         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14669                 return 32*1024;
14670         } else if (gen >= 4) {
14671                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14672                         return 16*1024;
14673                 else
14674                         return 32*1024;
14675         } else if (gen >= 3) {
14676                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14677                         return 8*1024;
14678                 else
14679                         return 16*1024;
14680         } else {
14681                 /* XXX DSPC is limited to 4k tiled */
14682                 return 8*1024;
14683         }
14684 }
14685
14686 static int intel_framebuffer_init(struct drm_device *dev,
14687                                   struct intel_framebuffer *intel_fb,
14688                                   struct drm_mode_fb_cmd2 *mode_cmd,
14689                                   struct drm_i915_gem_object *obj)
14690 {
14691         struct drm_i915_private *dev_priv = to_i915(dev);
14692         unsigned int aligned_height;
14693         int ret;
14694         u32 pitch_limit, stride_alignment;
14695
14696         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14697
14698         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14699                 /* Enforce that fb modifier and tiling mode match, but only for
14700                  * X-tiled. This is needed for FBC. */
14701                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14702                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14703                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14704                         return -EINVAL;
14705                 }
14706         } else {
14707                 if (obj->tiling_mode == I915_TILING_X)
14708                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14709                 else if (obj->tiling_mode == I915_TILING_Y) {
14710                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14711                         return -EINVAL;
14712                 }
14713         }
14714
14715         /* Passed in modifier sanity checking. */
14716         switch (mode_cmd->modifier[0]) {
14717         case I915_FORMAT_MOD_Y_TILED:
14718         case I915_FORMAT_MOD_Yf_TILED:
14719                 if (INTEL_INFO(dev)->gen < 9) {
14720                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14721                                   mode_cmd->modifier[0]);
14722                         return -EINVAL;
14723                 }
14724         case DRM_FORMAT_MOD_NONE:
14725         case I915_FORMAT_MOD_X_TILED:
14726                 break;
14727         default:
14728                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14729                           mode_cmd->modifier[0]);
14730                 return -EINVAL;
14731         }
14732
14733         stride_alignment = intel_fb_stride_alignment(dev_priv,
14734                                                      mode_cmd->modifier[0],
14735                                                      mode_cmd->pixel_format);
14736         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14737                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14738                           mode_cmd->pitches[0], stride_alignment);
14739                 return -EINVAL;
14740         }
14741
14742         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14743                                            mode_cmd->pixel_format);
14744         if (mode_cmd->pitches[0] > pitch_limit) {
14745                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14746                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14747                           "tiled" : "linear",
14748                           mode_cmd->pitches[0], pitch_limit);
14749                 return -EINVAL;
14750         }
14751
14752         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14753             mode_cmd->pitches[0] != obj->stride) {
14754                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14755                           mode_cmd->pitches[0], obj->stride);
14756                 return -EINVAL;
14757         }
14758
14759         /* Reject formats not supported by any plane early. */
14760         switch (mode_cmd->pixel_format) {
14761         case DRM_FORMAT_C8:
14762         case DRM_FORMAT_RGB565:
14763         case DRM_FORMAT_XRGB8888:
14764         case DRM_FORMAT_ARGB8888:
14765                 break;
14766         case DRM_FORMAT_XRGB1555:
14767                 if (INTEL_INFO(dev)->gen > 3) {
14768                         DRM_DEBUG("unsupported pixel format: %s\n",
14769                                   drm_get_format_name(mode_cmd->pixel_format));
14770                         return -EINVAL;
14771                 }
14772                 break;
14773         case DRM_FORMAT_ABGR8888:
14774                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14775                     INTEL_INFO(dev)->gen < 9) {
14776                         DRM_DEBUG("unsupported pixel format: %s\n",
14777                                   drm_get_format_name(mode_cmd->pixel_format));
14778                         return -EINVAL;
14779                 }
14780                 break;
14781         case DRM_FORMAT_XBGR8888:
14782         case DRM_FORMAT_XRGB2101010:
14783         case DRM_FORMAT_XBGR2101010:
14784                 if (INTEL_INFO(dev)->gen < 4) {
14785                         DRM_DEBUG("unsupported pixel format: %s\n",
14786                                   drm_get_format_name(mode_cmd->pixel_format));
14787                         return -EINVAL;
14788                 }
14789                 break;
14790         case DRM_FORMAT_ABGR2101010:
14791                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14792                         DRM_DEBUG("unsupported pixel format: %s\n",
14793                                   drm_get_format_name(mode_cmd->pixel_format));
14794                         return -EINVAL;
14795                 }
14796                 break;
14797         case DRM_FORMAT_YUYV:
14798         case DRM_FORMAT_UYVY:
14799         case DRM_FORMAT_YVYU:
14800         case DRM_FORMAT_VYUY:
14801                 if (INTEL_INFO(dev)->gen < 5) {
14802                         DRM_DEBUG("unsupported pixel format: %s\n",
14803                                   drm_get_format_name(mode_cmd->pixel_format));
14804                         return -EINVAL;
14805                 }
14806                 break;
14807         default:
14808                 DRM_DEBUG("unsupported pixel format: %s\n",
14809                           drm_get_format_name(mode_cmd->pixel_format));
14810                 return -EINVAL;
14811         }
14812
14813         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14814         if (mode_cmd->offsets[0] != 0)
14815                 return -EINVAL;
14816
14817         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14818                                                mode_cmd->pixel_format,
14819                                                mode_cmd->modifier[0]);
14820         /* FIXME drm helper for size checks (especially planar formats)? */
14821         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14822                 return -EINVAL;
14823
14824         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14825         intel_fb->obj = obj;
14826
14827         intel_fill_fb_info(dev_priv, &intel_fb->base);
14828
14829         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14830         if (ret) {
14831                 DRM_ERROR("framebuffer init failed %d\n", ret);
14832                 return ret;
14833         }
14834
14835         intel_fb->obj->framebuffer_references++;
14836
14837         return 0;
14838 }
14839
14840 static struct drm_framebuffer *
14841 intel_user_framebuffer_create(struct drm_device *dev,
14842                               struct drm_file *filp,
14843                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14844 {
14845         struct drm_framebuffer *fb;
14846         struct drm_i915_gem_object *obj;
14847         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14848
14849         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14850                                                 mode_cmd.handles[0]));
14851         if (&obj->base == NULL)
14852                 return ERR_PTR(-ENOENT);
14853
14854         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14855         if (IS_ERR(fb))
14856                 drm_gem_object_unreference_unlocked(&obj->base);
14857
14858         return fb;
14859 }
14860
14861 #ifndef CONFIG_DRM_FBDEV_EMULATION
14862 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14863 {
14864 }
14865 #endif
14866
14867 static const struct drm_mode_config_funcs intel_mode_funcs = {
14868         .fb_create = intel_user_framebuffer_create,
14869         .output_poll_changed = intel_fbdev_output_poll_changed,
14870         .atomic_check = intel_atomic_check,
14871         .atomic_commit = intel_atomic_commit,
14872         .atomic_state_alloc = intel_atomic_state_alloc,
14873         .atomic_state_clear = intel_atomic_state_clear,
14874 };
14875
14876 /**
14877  * intel_init_display_hooks - initialize the display modesetting hooks
14878  * @dev_priv: device private
14879  */
14880 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14881 {
14882         if (INTEL_INFO(dev_priv)->gen >= 9) {
14883                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14884                 dev_priv->display.get_initial_plane_config =
14885                         skylake_get_initial_plane_config;
14886                 dev_priv->display.crtc_compute_clock =
14887                         haswell_crtc_compute_clock;
14888                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14889                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14890         } else if (HAS_DDI(dev_priv)) {
14891                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14892                 dev_priv->display.get_initial_plane_config =
14893                         ironlake_get_initial_plane_config;
14894                 dev_priv->display.crtc_compute_clock =
14895                         haswell_crtc_compute_clock;
14896                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14897                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14898         } else if (HAS_PCH_SPLIT(dev_priv)) {
14899                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14900                 dev_priv->display.get_initial_plane_config =
14901                         ironlake_get_initial_plane_config;
14902                 dev_priv->display.crtc_compute_clock =
14903                         ironlake_crtc_compute_clock;
14904                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14905                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14906         } else if (IS_CHERRYVIEW(dev_priv)) {
14907                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14908                 dev_priv->display.get_initial_plane_config =
14909                         i9xx_get_initial_plane_config;
14910                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14911                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14912                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14913         } else if (IS_VALLEYVIEW(dev_priv)) {
14914                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14915                 dev_priv->display.get_initial_plane_config =
14916                         i9xx_get_initial_plane_config;
14917                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14918                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14919                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14920         } else if (IS_G4X(dev_priv)) {
14921                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14922                 dev_priv->display.get_initial_plane_config =
14923                         i9xx_get_initial_plane_config;
14924                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14925                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14926                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14927         } else if (IS_PINEVIEW(dev_priv)) {
14928                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14929                 dev_priv->display.get_initial_plane_config =
14930                         i9xx_get_initial_plane_config;
14931                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14932                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14933                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14934         } else if (!IS_GEN2(dev_priv)) {
14935                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14936                 dev_priv->display.get_initial_plane_config =
14937                         i9xx_get_initial_plane_config;
14938                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14939                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14940                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14941         } else {
14942                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14943                 dev_priv->display.get_initial_plane_config =
14944                         i9xx_get_initial_plane_config;
14945                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14946                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14947                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14948         }
14949
14950         /* Returns the core display clock speed */
14951         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14952                 dev_priv->display.get_display_clock_speed =
14953                         skylake_get_display_clock_speed;
14954         else if (IS_BROXTON(dev_priv))
14955                 dev_priv->display.get_display_clock_speed =
14956                         broxton_get_display_clock_speed;
14957         else if (IS_BROADWELL(dev_priv))
14958                 dev_priv->display.get_display_clock_speed =
14959                         broadwell_get_display_clock_speed;
14960         else if (IS_HASWELL(dev_priv))
14961                 dev_priv->display.get_display_clock_speed =
14962                         haswell_get_display_clock_speed;
14963         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14964                 dev_priv->display.get_display_clock_speed =
14965                         valleyview_get_display_clock_speed;
14966         else if (IS_GEN5(dev_priv))
14967                 dev_priv->display.get_display_clock_speed =
14968                         ilk_get_display_clock_speed;
14969         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14970                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14971                 dev_priv->display.get_display_clock_speed =
14972                         i945_get_display_clock_speed;
14973         else if (IS_GM45(dev_priv))
14974                 dev_priv->display.get_display_clock_speed =
14975                         gm45_get_display_clock_speed;
14976         else if (IS_CRESTLINE(dev_priv))
14977                 dev_priv->display.get_display_clock_speed =
14978                         i965gm_get_display_clock_speed;
14979         else if (IS_PINEVIEW(dev_priv))
14980                 dev_priv->display.get_display_clock_speed =
14981                         pnv_get_display_clock_speed;
14982         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14983                 dev_priv->display.get_display_clock_speed =
14984                         g33_get_display_clock_speed;
14985         else if (IS_I915G(dev_priv))
14986                 dev_priv->display.get_display_clock_speed =
14987                         i915_get_display_clock_speed;
14988         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14989                 dev_priv->display.get_display_clock_speed =
14990                         i9xx_misc_get_display_clock_speed;
14991         else if (IS_I915GM(dev_priv))
14992                 dev_priv->display.get_display_clock_speed =
14993                         i915gm_get_display_clock_speed;
14994         else if (IS_I865G(dev_priv))
14995                 dev_priv->display.get_display_clock_speed =
14996                         i865_get_display_clock_speed;
14997         else if (IS_I85X(dev_priv))
14998                 dev_priv->display.get_display_clock_speed =
14999                         i85x_get_display_clock_speed;
15000         else { /* 830 */
15001                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15002                 dev_priv->display.get_display_clock_speed =
15003                         i830_get_display_clock_speed;
15004         }
15005
15006         if (IS_GEN5(dev_priv)) {
15007                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15008         } else if (IS_GEN6(dev_priv)) {
15009                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15010         } else if (IS_IVYBRIDGE(dev_priv)) {
15011                 /* FIXME: detect B0+ stepping and use auto training */
15012                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15013         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15014                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15015                 if (IS_BROADWELL(dev_priv)) {
15016                         dev_priv->display.modeset_commit_cdclk =
15017                                 broadwell_modeset_commit_cdclk;
15018                         dev_priv->display.modeset_calc_cdclk =
15019                                 broadwell_modeset_calc_cdclk;
15020                 }
15021         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15022                 dev_priv->display.modeset_commit_cdclk =
15023                         valleyview_modeset_commit_cdclk;
15024                 dev_priv->display.modeset_calc_cdclk =
15025                         valleyview_modeset_calc_cdclk;
15026         } else if (IS_BROXTON(dev_priv)) {
15027                 dev_priv->display.modeset_commit_cdclk =
15028                         broxton_modeset_commit_cdclk;
15029                 dev_priv->display.modeset_calc_cdclk =
15030                         broxton_modeset_calc_cdclk;
15031         }
15032
15033         switch (INTEL_INFO(dev_priv)->gen) {
15034         case 2:
15035                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15036                 break;
15037
15038         case 3:
15039                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15040                 break;
15041
15042         case 4:
15043         case 5:
15044                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15045                 break;
15046
15047         case 6:
15048                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15049                 break;
15050         case 7:
15051         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15052                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15053                 break;
15054         case 9:
15055                 /* Drop through - unsupported since execlist only. */
15056         default:
15057                 /* Default just returns -ENODEV to indicate unsupported */
15058                 dev_priv->display.queue_flip = intel_default_queue_flip;
15059         }
15060 }
15061
15062 /*
15063  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15064  * resume, or other times.  This quirk makes sure that's the case for
15065  * affected systems.
15066  */
15067 static void quirk_pipea_force(struct drm_device *dev)
15068 {
15069         struct drm_i915_private *dev_priv = dev->dev_private;
15070
15071         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15072         DRM_INFO("applying pipe a force quirk\n");
15073 }
15074
15075 static void quirk_pipeb_force(struct drm_device *dev)
15076 {
15077         struct drm_i915_private *dev_priv = dev->dev_private;
15078
15079         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15080         DRM_INFO("applying pipe b force quirk\n");
15081 }
15082
15083 /*
15084  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15085  */
15086 static void quirk_ssc_force_disable(struct drm_device *dev)
15087 {
15088         struct drm_i915_private *dev_priv = dev->dev_private;
15089         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15090         DRM_INFO("applying lvds SSC disable quirk\n");
15091 }
15092
15093 /*
15094  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15095  * brightness value
15096  */
15097 static void quirk_invert_brightness(struct drm_device *dev)
15098 {
15099         struct drm_i915_private *dev_priv = dev->dev_private;
15100         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15101         DRM_INFO("applying inverted panel brightness quirk\n");
15102 }
15103
15104 /* Some VBT's incorrectly indicate no backlight is present */
15105 static void quirk_backlight_present(struct drm_device *dev)
15106 {
15107         struct drm_i915_private *dev_priv = dev->dev_private;
15108         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15109         DRM_INFO("applying backlight present quirk\n");
15110 }
15111
15112 struct intel_quirk {
15113         int device;
15114         int subsystem_vendor;
15115         int subsystem_device;
15116         void (*hook)(struct drm_device *dev);
15117 };
15118
15119 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15120 struct intel_dmi_quirk {
15121         void (*hook)(struct drm_device *dev);
15122         const struct dmi_system_id (*dmi_id_list)[];
15123 };
15124
15125 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15126 {
15127         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15128         return 1;
15129 }
15130
15131 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15132         {
15133                 .dmi_id_list = &(const struct dmi_system_id[]) {
15134                         {
15135                                 .callback = intel_dmi_reverse_brightness,
15136                                 .ident = "NCR Corporation",
15137                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15138                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15139                                 },
15140                         },
15141                         { }  /* terminating entry */
15142                 },
15143                 .hook = quirk_invert_brightness,
15144         },
15145 };
15146
15147 static struct intel_quirk intel_quirks[] = {
15148         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15149         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15150
15151         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15152         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15153
15154         /* 830 needs to leave pipe A & dpll A up */
15155         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15156
15157         /* 830 needs to leave pipe B & dpll B up */
15158         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15159
15160         /* Lenovo U160 cannot use SSC on LVDS */
15161         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15162
15163         /* Sony Vaio Y cannot use SSC on LVDS */
15164         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15165
15166         /* Acer Aspire 5734Z must invert backlight brightness */
15167         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15168
15169         /* Acer/eMachines G725 */
15170         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15171
15172         /* Acer/eMachines e725 */
15173         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15174
15175         /* Acer/Packard Bell NCL20 */
15176         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15177
15178         /* Acer Aspire 4736Z */
15179         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15180
15181         /* Acer Aspire 5336 */
15182         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15183
15184         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15185         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15186
15187         /* Acer C720 Chromebook (Core i3 4005U) */
15188         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15189
15190         /* Apple Macbook 2,1 (Core 2 T7400) */
15191         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15192
15193         /* Apple Macbook 4,1 */
15194         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15195
15196         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15197         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15198
15199         /* HP Chromebook 14 (Celeron 2955U) */
15200         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15201
15202         /* Dell Chromebook 11 */
15203         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15204
15205         /* Dell Chromebook 11 (2015 version) */
15206         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15207 };
15208
15209 static void intel_init_quirks(struct drm_device *dev)
15210 {
15211         struct pci_dev *d = dev->pdev;
15212         int i;
15213
15214         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15215                 struct intel_quirk *q = &intel_quirks[i];
15216
15217                 if (d->device == q->device &&
15218                     (d->subsystem_vendor == q->subsystem_vendor ||
15219                      q->subsystem_vendor == PCI_ANY_ID) &&
15220                     (d->subsystem_device == q->subsystem_device ||
15221                      q->subsystem_device == PCI_ANY_ID))
15222                         q->hook(dev);
15223         }
15224         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15225                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15226                         intel_dmi_quirks[i].hook(dev);
15227         }
15228 }
15229
15230 /* Disable the VGA plane that we never use */
15231 static void i915_disable_vga(struct drm_device *dev)
15232 {
15233         struct drm_i915_private *dev_priv = dev->dev_private;
15234         u8 sr1;
15235         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15236
15237         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15238         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15239         outb(SR01, VGA_SR_INDEX);
15240         sr1 = inb(VGA_SR_DATA);
15241         outb(sr1 | 1<<5, VGA_SR_DATA);
15242         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15243         udelay(300);
15244
15245         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15246         POSTING_READ(vga_reg);
15247 }
15248
15249 void intel_modeset_init_hw(struct drm_device *dev)
15250 {
15251         struct drm_i915_private *dev_priv = dev->dev_private;
15252
15253         intel_update_cdclk(dev);
15254
15255         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15256
15257         intel_init_clock_gating(dev);
15258         intel_enable_gt_powersave(dev);
15259 }
15260
15261 /*
15262  * Calculate what we think the watermarks should be for the state we've read
15263  * out of the hardware and then immediately program those watermarks so that
15264  * we ensure the hardware settings match our internal state.
15265  *
15266  * We can calculate what we think WM's should be by creating a duplicate of the
15267  * current state (which was constructed during hardware readout) and running it
15268  * through the atomic check code to calculate new watermark values in the
15269  * state object.
15270  */
15271 static void sanitize_watermarks(struct drm_device *dev)
15272 {
15273         struct drm_i915_private *dev_priv = to_i915(dev);
15274         struct drm_atomic_state *state;
15275         struct drm_crtc *crtc;
15276         struct drm_crtc_state *cstate;
15277         struct drm_modeset_acquire_ctx ctx;
15278         int ret;
15279         int i;
15280
15281         /* Only supported on platforms that use atomic watermark design */
15282         if (!dev_priv->display.optimize_watermarks)
15283                 return;
15284
15285         /*
15286          * We need to hold connection_mutex before calling duplicate_state so
15287          * that the connector loop is protected.
15288          */
15289         drm_modeset_acquire_init(&ctx, 0);
15290 retry:
15291         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15292         if (ret == -EDEADLK) {
15293                 drm_modeset_backoff(&ctx);
15294                 goto retry;
15295         } else if (WARN_ON(ret)) {
15296                 goto fail;
15297         }
15298
15299         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15300         if (WARN_ON(IS_ERR(state)))
15301                 goto fail;
15302
15303         /*
15304          * Hardware readout is the only time we don't want to calculate
15305          * intermediate watermarks (since we don't trust the current
15306          * watermarks).
15307          */
15308         to_intel_atomic_state(state)->skip_intermediate_wm = true;
15309
15310         ret = intel_atomic_check(dev, state);
15311         if (ret) {
15312                 /*
15313                  * If we fail here, it means that the hardware appears to be
15314                  * programmed in a way that shouldn't be possible, given our
15315                  * understanding of watermark requirements.  This might mean a
15316                  * mistake in the hardware readout code or a mistake in the
15317                  * watermark calculations for a given platform.  Raise a WARN
15318                  * so that this is noticeable.
15319                  *
15320                  * If this actually happens, we'll have to just leave the
15321                  * BIOS-programmed watermarks untouched and hope for the best.
15322                  */
15323                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15324                 goto fail;
15325         }
15326
15327         /* Write calculated watermark values back */
15328         to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15329         for_each_crtc_in_state(state, crtc, cstate, i) {
15330                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15331
15332                 cs->wm.need_postvbl_update = true;
15333                 dev_priv->display.optimize_watermarks(cs);
15334         }
15335
15336         drm_atomic_state_free(state);
15337 fail:
15338         drm_modeset_drop_locks(&ctx);
15339         drm_modeset_acquire_fini(&ctx);
15340 }
15341
15342 void intel_modeset_init(struct drm_device *dev)
15343 {
15344         struct drm_i915_private *dev_priv = to_i915(dev);
15345         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15346         int sprite, ret;
15347         enum pipe pipe;
15348         struct intel_crtc *crtc;
15349
15350         drm_mode_config_init(dev);
15351
15352         dev->mode_config.min_width = 0;
15353         dev->mode_config.min_height = 0;
15354
15355         dev->mode_config.preferred_depth = 24;
15356         dev->mode_config.prefer_shadow = 1;
15357
15358         dev->mode_config.allow_fb_modifiers = true;
15359
15360         dev->mode_config.funcs = &intel_mode_funcs;
15361
15362         intel_init_quirks(dev);
15363
15364         intel_init_pm(dev);
15365
15366         if (INTEL_INFO(dev)->num_pipes == 0)
15367                 return;
15368
15369         /*
15370          * There may be no VBT; and if the BIOS enabled SSC we can
15371          * just keep using it to avoid unnecessary flicker.  Whereas if the
15372          * BIOS isn't using it, don't assume it will work even if the VBT
15373          * indicates as much.
15374          */
15375         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15376                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15377                                             DREF_SSC1_ENABLE);
15378
15379                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15380                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15381                                      bios_lvds_use_ssc ? "en" : "dis",
15382                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15383                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15384                 }
15385         }
15386
15387         if (IS_GEN2(dev)) {
15388                 dev->mode_config.max_width = 2048;
15389                 dev->mode_config.max_height = 2048;
15390         } else if (IS_GEN3(dev)) {
15391                 dev->mode_config.max_width = 4096;
15392                 dev->mode_config.max_height = 4096;
15393         } else {
15394                 dev->mode_config.max_width = 8192;
15395                 dev->mode_config.max_height = 8192;
15396         }
15397
15398         if (IS_845G(dev) || IS_I865G(dev)) {
15399                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15400                 dev->mode_config.cursor_height = 1023;
15401         } else if (IS_GEN2(dev)) {
15402                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15403                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15404         } else {
15405                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15406                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15407         }
15408
15409         dev->mode_config.fb_base = ggtt->mappable_base;
15410
15411         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15412                       INTEL_INFO(dev)->num_pipes,
15413                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15414
15415         for_each_pipe(dev_priv, pipe) {
15416                 intel_crtc_init(dev, pipe);
15417                 for_each_sprite(dev_priv, pipe, sprite) {
15418                         ret = intel_plane_init(dev, pipe, sprite);
15419                         if (ret)
15420                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15421                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15422                 }
15423         }
15424
15425         intel_update_czclk(dev_priv);
15426         intel_update_rawclk(dev_priv);
15427         intel_update_cdclk(dev);
15428
15429         intel_shared_dpll_init(dev);
15430
15431         /* Just disable it once at startup */
15432         i915_disable_vga(dev);
15433         intel_setup_outputs(dev);
15434
15435         drm_modeset_lock_all(dev);
15436         intel_modeset_setup_hw_state(dev);
15437         drm_modeset_unlock_all(dev);
15438
15439         for_each_intel_crtc(dev, crtc) {
15440                 struct intel_initial_plane_config plane_config = {};
15441
15442                 if (!crtc->active)
15443                         continue;
15444
15445                 /*
15446                  * Note that reserving the BIOS fb up front prevents us
15447                  * from stuffing other stolen allocations like the ring
15448                  * on top.  This prevents some ugliness at boot time, and
15449                  * can even allow for smooth boot transitions if the BIOS
15450                  * fb is large enough for the active pipe configuration.
15451                  */
15452                 dev_priv->display.get_initial_plane_config(crtc,
15453                                                            &plane_config);
15454
15455                 /*
15456                  * If the fb is shared between multiple heads, we'll
15457                  * just get the first one.
15458                  */
15459                 intel_find_initial_plane_obj(crtc, &plane_config);
15460         }
15461
15462         /*
15463          * Make sure hardware watermarks really match the state we read out.
15464          * Note that we need to do this after reconstructing the BIOS fb's
15465          * since the watermark calculation done here will use pstate->fb.
15466          */
15467         sanitize_watermarks(dev);
15468 }
15469
15470 static void intel_enable_pipe_a(struct drm_device *dev)
15471 {
15472         struct intel_connector *connector;
15473         struct drm_connector *crt = NULL;
15474         struct intel_load_detect_pipe load_detect_temp;
15475         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15476
15477         /* We can't just switch on the pipe A, we need to set things up with a
15478          * proper mode and output configuration. As a gross hack, enable pipe A
15479          * by enabling the load detect pipe once. */
15480         for_each_intel_connector(dev, connector) {
15481                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15482                         crt = &connector->base;
15483                         break;
15484                 }
15485         }
15486
15487         if (!crt)
15488                 return;
15489
15490         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15491                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15492 }
15493
15494 static bool
15495 intel_check_plane_mapping(struct intel_crtc *crtc)
15496 {
15497         struct drm_device *dev = crtc->base.dev;
15498         struct drm_i915_private *dev_priv = dev->dev_private;
15499         u32 val;
15500
15501         if (INTEL_INFO(dev)->num_pipes == 1)
15502                 return true;
15503
15504         val = I915_READ(DSPCNTR(!crtc->plane));
15505
15506         if ((val & DISPLAY_PLANE_ENABLE) &&
15507             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15508                 return false;
15509
15510         return true;
15511 }
15512
15513 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15514 {
15515         struct drm_device *dev = crtc->base.dev;
15516         struct intel_encoder *encoder;
15517
15518         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15519                 return true;
15520
15521         return false;
15522 }
15523
15524 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15525 {
15526         struct drm_device *dev = encoder->base.dev;
15527         struct intel_connector *connector;
15528
15529         for_each_connector_on_encoder(dev, &encoder->base, connector)
15530                 return true;
15531
15532         return false;
15533 }
15534
15535 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15536 {
15537         struct drm_device *dev = crtc->base.dev;
15538         struct drm_i915_private *dev_priv = dev->dev_private;
15539         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15540
15541         /* Clear any frame start delays used for debugging left by the BIOS */
15542         if (!transcoder_is_dsi(cpu_transcoder)) {
15543                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15544
15545                 I915_WRITE(reg,
15546                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15547         }
15548
15549         /* restore vblank interrupts to correct state */
15550         drm_crtc_vblank_reset(&crtc->base);
15551         if (crtc->active) {
15552                 struct intel_plane *plane;
15553
15554                 drm_crtc_vblank_on(&crtc->base);
15555
15556                 /* Disable everything but the primary plane */
15557                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15558                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15559                                 continue;
15560
15561                         plane->disable_plane(&plane->base, &crtc->base);
15562                 }
15563         }
15564
15565         /* We need to sanitize the plane -> pipe mapping first because this will
15566          * disable the crtc (and hence change the state) if it is wrong. Note
15567          * that gen4+ has a fixed plane -> pipe mapping.  */
15568         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15569                 bool plane;
15570
15571                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15572                               crtc->base.base.id);
15573
15574                 /* Pipe has the wrong plane attached and the plane is active.
15575                  * Temporarily change the plane mapping and disable everything
15576                  * ...  */
15577                 plane = crtc->plane;
15578                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15579                 crtc->plane = !plane;
15580                 intel_crtc_disable_noatomic(&crtc->base);
15581                 crtc->plane = plane;
15582         }
15583
15584         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15585             crtc->pipe == PIPE_A && !crtc->active) {
15586                 /* BIOS forgot to enable pipe A, this mostly happens after
15587                  * resume. Force-enable the pipe to fix this, the update_dpms
15588                  * call below we restore the pipe to the right state, but leave
15589                  * the required bits on. */
15590                 intel_enable_pipe_a(dev);
15591         }
15592
15593         /* Adjust the state of the output pipe according to whether we
15594          * have active connectors/encoders. */
15595         if (crtc->active && !intel_crtc_has_encoders(crtc))
15596                 intel_crtc_disable_noatomic(&crtc->base);
15597
15598         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15599                 /*
15600                  * We start out with underrun reporting disabled to avoid races.
15601                  * For correct bookkeeping mark this on active crtcs.
15602                  *
15603                  * Also on gmch platforms we dont have any hardware bits to
15604                  * disable the underrun reporting. Which means we need to start
15605                  * out with underrun reporting disabled also on inactive pipes,
15606                  * since otherwise we'll complain about the garbage we read when
15607                  * e.g. coming up after runtime pm.
15608                  *
15609                  * No protection against concurrent access is required - at
15610                  * worst a fifo underrun happens which also sets this to false.
15611                  */
15612                 crtc->cpu_fifo_underrun_disabled = true;
15613                 crtc->pch_fifo_underrun_disabled = true;
15614         }
15615 }
15616
15617 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15618 {
15619         struct intel_connector *connector;
15620         struct drm_device *dev = encoder->base.dev;
15621
15622         /* We need to check both for a crtc link (meaning that the
15623          * encoder is active and trying to read from a pipe) and the
15624          * pipe itself being active. */
15625         bool has_active_crtc = encoder->base.crtc &&
15626                 to_intel_crtc(encoder->base.crtc)->active;
15627
15628         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15629                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15630                               encoder->base.base.id,
15631                               encoder->base.name);
15632
15633                 /* Connector is active, but has no active pipe. This is
15634                  * fallout from our resume register restoring. Disable
15635                  * the encoder manually again. */
15636                 if (encoder->base.crtc) {
15637                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15638                                       encoder->base.base.id,
15639                                       encoder->base.name);
15640                         encoder->disable(encoder);
15641                         if (encoder->post_disable)
15642                                 encoder->post_disable(encoder);
15643                 }
15644                 encoder->base.crtc = NULL;
15645
15646                 /* Inconsistent output/port/pipe state happens presumably due to
15647                  * a bug in one of the get_hw_state functions. Or someplace else
15648                  * in our code, like the register restore mess on resume. Clamp
15649                  * things to off as a safer default. */
15650                 for_each_intel_connector(dev, connector) {
15651                         if (connector->encoder != encoder)
15652                                 continue;
15653                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15654                         connector->base.encoder = NULL;
15655                 }
15656         }
15657         /* Enabled encoders without active connectors will be fixed in
15658          * the crtc fixup. */
15659 }
15660
15661 void i915_redisable_vga_power_on(struct drm_device *dev)
15662 {
15663         struct drm_i915_private *dev_priv = dev->dev_private;
15664         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15665
15666         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15667                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15668                 i915_disable_vga(dev);
15669         }
15670 }
15671
15672 void i915_redisable_vga(struct drm_device *dev)
15673 {
15674         struct drm_i915_private *dev_priv = dev->dev_private;
15675
15676         /* This function can be called both from intel_modeset_setup_hw_state or
15677          * at a very early point in our resume sequence, where the power well
15678          * structures are not yet restored. Since this function is at a very
15679          * paranoid "someone might have enabled VGA while we were not looking"
15680          * level, just check if the power well is enabled instead of trying to
15681          * follow the "don't touch the power well if we don't need it" policy
15682          * the rest of the driver uses. */
15683         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15684                 return;
15685
15686         i915_redisable_vga_power_on(dev);
15687
15688         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15689 }
15690
15691 static bool primary_get_hw_state(struct intel_plane *plane)
15692 {
15693         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15694
15695         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15696 }
15697
15698 /* FIXME read out full plane state for all planes */
15699 static void readout_plane_state(struct intel_crtc *crtc)
15700 {
15701         struct drm_plane *primary = crtc->base.primary;
15702         struct intel_plane_state *plane_state =
15703                 to_intel_plane_state(primary->state);
15704
15705         plane_state->visible = crtc->active &&
15706                 primary_get_hw_state(to_intel_plane(primary));
15707
15708         if (plane_state->visible)
15709                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15710 }
15711
15712 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15713 {
15714         struct drm_i915_private *dev_priv = dev->dev_private;
15715         enum pipe pipe;
15716         struct intel_crtc *crtc;
15717         struct intel_encoder *encoder;
15718         struct intel_connector *connector;
15719         int i;
15720
15721         dev_priv->active_crtcs = 0;
15722
15723         for_each_intel_crtc(dev, crtc) {
15724                 struct intel_crtc_state *crtc_state = crtc->config;
15725                 int pixclk = 0;
15726
15727                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15728                 memset(crtc_state, 0, sizeof(*crtc_state));
15729                 crtc_state->base.crtc = &crtc->base;
15730
15731                 crtc_state->base.active = crtc_state->base.enable =
15732                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15733
15734                 crtc->base.enabled = crtc_state->base.enable;
15735                 crtc->active = crtc_state->base.active;
15736
15737                 if (crtc_state->base.active) {
15738                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15739
15740                         if (IS_BROADWELL(dev_priv)) {
15741                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15742
15743                                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15744                                 if (crtc_state->ips_enabled)
15745                                         pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15746                         } else if (IS_VALLEYVIEW(dev_priv) ||
15747                                    IS_CHERRYVIEW(dev_priv) ||
15748                                    IS_BROXTON(dev_priv))
15749                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15750                         else
15751                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15752                 }
15753
15754                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15755
15756                 readout_plane_state(crtc);
15757
15758                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15759                               crtc->base.base.id,
15760                               crtc->active ? "enabled" : "disabled");
15761         }
15762
15763         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15764                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15765
15766                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15767                                                   &pll->config.hw_state);
15768                 pll->config.crtc_mask = 0;
15769                 for_each_intel_crtc(dev, crtc) {
15770                         if (crtc->active && crtc->config->shared_dpll == pll)
15771                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15772                 }
15773                 pll->active_mask = pll->config.crtc_mask;
15774
15775                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15776                               pll->name, pll->config.crtc_mask, pll->on);
15777         }
15778
15779         for_each_intel_encoder(dev, encoder) {
15780                 pipe = 0;
15781
15782                 if (encoder->get_hw_state(encoder, &pipe)) {
15783                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15784                         encoder->base.crtc = &crtc->base;
15785                         encoder->get_config(encoder, crtc->config);
15786                 } else {
15787                         encoder->base.crtc = NULL;
15788                 }
15789
15790                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15791                               encoder->base.base.id,
15792                               encoder->base.name,
15793                               encoder->base.crtc ? "enabled" : "disabled",
15794                               pipe_name(pipe));
15795         }
15796
15797         for_each_intel_connector(dev, connector) {
15798                 if (connector->get_hw_state(connector)) {
15799                         connector->base.dpms = DRM_MODE_DPMS_ON;
15800
15801                         encoder = connector->encoder;
15802                         connector->base.encoder = &encoder->base;
15803
15804                         if (encoder->base.crtc &&
15805                             encoder->base.crtc->state->active) {
15806                                 /*
15807                                  * This has to be done during hardware readout
15808                                  * because anything calling .crtc_disable may
15809                                  * rely on the connector_mask being accurate.
15810                                  */
15811                                 encoder->base.crtc->state->connector_mask |=
15812                                         1 << drm_connector_index(&connector->base);
15813                                 encoder->base.crtc->state->encoder_mask |=
15814                                         1 << drm_encoder_index(&encoder->base);
15815                         }
15816
15817                 } else {
15818                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15819                         connector->base.encoder = NULL;
15820                 }
15821                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15822                               connector->base.base.id,
15823                               connector->base.name,
15824                               connector->base.encoder ? "enabled" : "disabled");
15825         }
15826
15827         for_each_intel_crtc(dev, crtc) {
15828                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15829
15830                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15831                 if (crtc->base.state->active) {
15832                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15833                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15834                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15835
15836                         /*
15837                          * The initial mode needs to be set in order to keep
15838                          * the atomic core happy. It wants a valid mode if the
15839                          * crtc's enabled, so we do the above call.
15840                          *
15841                          * At this point some state updated by the connectors
15842                          * in their ->detect() callback has not run yet, so
15843                          * no recalculation can be done yet.
15844                          *
15845                          * Even if we could do a recalculation and modeset
15846                          * right now it would cause a double modeset if
15847                          * fbdev or userspace chooses a different initial mode.
15848                          *
15849                          * If that happens, someone indicated they wanted a
15850                          * mode change, which means it's safe to do a full
15851                          * recalculation.
15852                          */
15853                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15854
15855                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15856                         update_scanline_offset(crtc);
15857                 }
15858
15859                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15860         }
15861 }
15862
15863 /* Scan out the current hw modeset state,
15864  * and sanitizes it to the current state
15865  */
15866 static void
15867 intel_modeset_setup_hw_state(struct drm_device *dev)
15868 {
15869         struct drm_i915_private *dev_priv = dev->dev_private;
15870         enum pipe pipe;
15871         struct intel_crtc *crtc;
15872         struct intel_encoder *encoder;
15873         int i;
15874
15875         intel_modeset_readout_hw_state(dev);
15876
15877         /* HW state is read out, now we need to sanitize this mess. */
15878         for_each_intel_encoder(dev, encoder) {
15879                 intel_sanitize_encoder(encoder);
15880         }
15881
15882         for_each_pipe(dev_priv, pipe) {
15883                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15884                 intel_sanitize_crtc(crtc);
15885                 intel_dump_pipe_config(crtc, crtc->config,
15886                                        "[setup_hw_state]");
15887         }
15888
15889         intel_modeset_update_connector_atomic_state(dev);
15890
15891         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15892                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15893
15894                 if (!pll->on || pll->active_mask)
15895                         continue;
15896
15897                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15898
15899                 pll->funcs.disable(dev_priv, pll);
15900                 pll->on = false;
15901         }
15902
15903         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15904                 vlv_wm_get_hw_state(dev);
15905         else if (IS_GEN9(dev))
15906                 skl_wm_get_hw_state(dev);
15907         else if (HAS_PCH_SPLIT(dev))
15908                 ilk_wm_get_hw_state(dev);
15909
15910         for_each_intel_crtc(dev, crtc) {
15911                 unsigned long put_domains;
15912
15913                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15914                 if (WARN_ON(put_domains))
15915                         modeset_put_power_domains(dev_priv, put_domains);
15916         }
15917         intel_display_set_init_power(dev_priv, false);
15918
15919         intel_fbc_init_pipe_state(dev_priv);
15920 }
15921
15922 void intel_display_resume(struct drm_device *dev)
15923 {
15924         struct drm_i915_private *dev_priv = to_i915(dev);
15925         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15926         struct drm_modeset_acquire_ctx ctx;
15927         int ret;
15928         bool setup = false;
15929
15930         dev_priv->modeset_restore_state = NULL;
15931
15932         /*
15933          * This is a cludge because with real atomic modeset mode_config.mutex
15934          * won't be taken. Unfortunately some probed state like
15935          * audio_codec_enable is still protected by mode_config.mutex, so lock
15936          * it here for now.
15937          */
15938         mutex_lock(&dev->mode_config.mutex);
15939         drm_modeset_acquire_init(&ctx, 0);
15940
15941 retry:
15942         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15943
15944         if (ret == 0 && !setup) {
15945                 setup = true;
15946
15947                 intel_modeset_setup_hw_state(dev);
15948                 i915_redisable_vga(dev);
15949         }
15950
15951         if (ret == 0 && state) {
15952                 struct drm_crtc_state *crtc_state;
15953                 struct drm_crtc *crtc;
15954                 int i;
15955
15956                 state->acquire_ctx = &ctx;
15957
15958                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15959                         /*
15960                          * Force recalculation even if we restore
15961                          * current state. With fast modeset this may not result
15962                          * in a modeset when the state is compatible.
15963                          */
15964                         crtc_state->mode_changed = true;
15965                 }
15966
15967                 ret = drm_atomic_commit(state);
15968         }
15969
15970         if (ret == -EDEADLK) {
15971                 drm_modeset_backoff(&ctx);
15972                 goto retry;
15973         }
15974
15975         drm_modeset_drop_locks(&ctx);
15976         drm_modeset_acquire_fini(&ctx);
15977         mutex_unlock(&dev->mode_config.mutex);
15978
15979         if (ret) {
15980                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15981                 drm_atomic_state_free(state);
15982         }
15983 }
15984
15985 void intel_modeset_gem_init(struct drm_device *dev)
15986 {
15987         struct drm_crtc *c;
15988         struct drm_i915_gem_object *obj;
15989         int ret;
15990
15991         intel_init_gt_powersave(dev);
15992
15993         intel_modeset_init_hw(dev);
15994
15995         intel_setup_overlay(dev);
15996
15997         /*
15998          * Make sure any fbs we allocated at startup are properly
15999          * pinned & fenced.  When we do the allocation it's too early
16000          * for this.
16001          */
16002         for_each_crtc(dev, c) {
16003                 obj = intel_fb_obj(c->primary->fb);
16004                 if (obj == NULL)
16005                         continue;
16006
16007                 mutex_lock(&dev->struct_mutex);
16008                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16009                                                  c->primary->state->rotation);
16010                 mutex_unlock(&dev->struct_mutex);
16011                 if (ret) {
16012                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16013                                   to_intel_crtc(c)->pipe);
16014                         drm_framebuffer_unreference(c->primary->fb);
16015                         c->primary->fb = NULL;
16016                         c->primary->crtc = c->primary->state->crtc = NULL;
16017                         update_state_fb(c->primary);
16018                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16019                 }
16020         }
16021
16022         intel_backlight_register(dev);
16023 }
16024
16025 void intel_connector_unregister(struct intel_connector *intel_connector)
16026 {
16027         struct drm_connector *connector = &intel_connector->base;
16028
16029         intel_panel_destroy_backlight(connector);
16030         drm_connector_unregister(connector);
16031 }
16032
16033 void intel_modeset_cleanup(struct drm_device *dev)
16034 {
16035         struct drm_i915_private *dev_priv = dev->dev_private;
16036         struct intel_connector *connector;
16037
16038         intel_disable_gt_powersave(dev);
16039
16040         intel_backlight_unregister(dev);
16041
16042         /*
16043          * Interrupts and polling as the first thing to avoid creating havoc.
16044          * Too much stuff here (turning of connectors, ...) would
16045          * experience fancy races otherwise.
16046          */
16047         intel_irq_uninstall(dev_priv);
16048
16049         /*
16050          * Due to the hpd irq storm handling the hotplug work can re-arm the
16051          * poll handlers. Hence disable polling after hpd handling is shut down.
16052          */
16053         drm_kms_helper_poll_fini(dev);
16054
16055         intel_unregister_dsm_handler();
16056
16057         intel_fbc_global_disable(dev_priv);
16058
16059         /* flush any delayed tasks or pending work */
16060         flush_scheduled_work();
16061
16062         /* destroy the backlight and sysfs files before encoders/connectors */
16063         for_each_intel_connector(dev, connector)
16064                 connector->unregister(connector);
16065
16066         drm_mode_config_cleanup(dev);
16067
16068         intel_cleanup_overlay(dev);
16069
16070         intel_cleanup_gt_powersave(dev);
16071
16072         intel_teardown_gmbus(dev);
16073 }
16074
16075 /*
16076  * Return which encoder is currently attached for connector.
16077  */
16078 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16079 {
16080         return &intel_attached_encoder(connector)->base;
16081 }
16082
16083 void intel_connector_attach_encoder(struct intel_connector *connector,
16084                                     struct intel_encoder *encoder)
16085 {
16086         connector->encoder = encoder;
16087         drm_mode_connector_attach_encoder(&connector->base,
16088                                           &encoder->base);
16089 }
16090
16091 /*
16092  * set vga decode state - true == enable VGA decode
16093  */
16094 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16095 {
16096         struct drm_i915_private *dev_priv = dev->dev_private;
16097         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16098         u16 gmch_ctrl;
16099
16100         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16101                 DRM_ERROR("failed to read control word\n");
16102                 return -EIO;
16103         }
16104
16105         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16106                 return 0;
16107
16108         if (state)
16109                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16110         else
16111                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16112
16113         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16114                 DRM_ERROR("failed to write control word\n");
16115                 return -EIO;
16116         }
16117
16118         return 0;
16119 }
16120
16121 struct intel_display_error_state {
16122
16123         u32 power_well_driver;
16124
16125         int num_transcoders;
16126
16127         struct intel_cursor_error_state {
16128                 u32 control;
16129                 u32 position;
16130                 u32 base;
16131                 u32 size;
16132         } cursor[I915_MAX_PIPES];
16133
16134         struct intel_pipe_error_state {
16135                 bool power_domain_on;
16136                 u32 source;
16137                 u32 stat;
16138         } pipe[I915_MAX_PIPES];
16139
16140         struct intel_plane_error_state {
16141                 u32 control;
16142                 u32 stride;
16143                 u32 size;
16144                 u32 pos;
16145                 u32 addr;
16146                 u32 surface;
16147                 u32 tile_offset;
16148         } plane[I915_MAX_PIPES];
16149
16150         struct intel_transcoder_error_state {
16151                 bool power_domain_on;
16152                 enum transcoder cpu_transcoder;
16153
16154                 u32 conf;
16155
16156                 u32 htotal;
16157                 u32 hblank;
16158                 u32 hsync;
16159                 u32 vtotal;
16160                 u32 vblank;
16161                 u32 vsync;
16162         } transcoder[4];
16163 };
16164
16165 struct intel_display_error_state *
16166 intel_display_capture_error_state(struct drm_device *dev)
16167 {
16168         struct drm_i915_private *dev_priv = dev->dev_private;
16169         struct intel_display_error_state *error;
16170         int transcoders[] = {
16171                 TRANSCODER_A,
16172                 TRANSCODER_B,
16173                 TRANSCODER_C,
16174                 TRANSCODER_EDP,
16175         };
16176         int i;
16177
16178         if (INTEL_INFO(dev)->num_pipes == 0)
16179                 return NULL;
16180
16181         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16182         if (error == NULL)
16183                 return NULL;
16184
16185         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16186                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16187
16188         for_each_pipe(dev_priv, i) {
16189                 error->pipe[i].power_domain_on =
16190                         __intel_display_power_is_enabled(dev_priv,
16191                                                          POWER_DOMAIN_PIPE(i));
16192                 if (!error->pipe[i].power_domain_on)
16193                         continue;
16194
16195                 error->cursor[i].control = I915_READ(CURCNTR(i));
16196                 error->cursor[i].position = I915_READ(CURPOS(i));
16197                 error->cursor[i].base = I915_READ(CURBASE(i));
16198
16199                 error->plane[i].control = I915_READ(DSPCNTR(i));
16200                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16201                 if (INTEL_INFO(dev)->gen <= 3) {
16202                         error->plane[i].size = I915_READ(DSPSIZE(i));
16203                         error->plane[i].pos = I915_READ(DSPPOS(i));
16204                 }
16205                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16206                         error->plane[i].addr = I915_READ(DSPADDR(i));
16207                 if (INTEL_INFO(dev)->gen >= 4) {
16208                         error->plane[i].surface = I915_READ(DSPSURF(i));
16209                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16210                 }
16211
16212                 error->pipe[i].source = I915_READ(PIPESRC(i));
16213
16214                 if (HAS_GMCH_DISPLAY(dev))
16215                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16216         }
16217
16218         /* Note: this does not include DSI transcoders. */
16219         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16220         if (HAS_DDI(dev_priv))
16221                 error->num_transcoders++; /* Account for eDP. */
16222
16223         for (i = 0; i < error->num_transcoders; i++) {
16224                 enum transcoder cpu_transcoder = transcoders[i];
16225
16226                 error->transcoder[i].power_domain_on =
16227                         __intel_display_power_is_enabled(dev_priv,
16228                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16229                 if (!error->transcoder[i].power_domain_on)
16230                         continue;
16231
16232                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16233
16234                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16235                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16236                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16237                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16238                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16239                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16240                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16241         }
16242
16243         return error;
16244 }
16245
16246 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16247
16248 void
16249 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16250                                 struct drm_device *dev,
16251                                 struct intel_display_error_state *error)
16252 {
16253         struct drm_i915_private *dev_priv = dev->dev_private;
16254         int i;
16255
16256         if (!error)
16257                 return;
16258
16259         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16260         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16261                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16262                            error->power_well_driver);
16263         for_each_pipe(dev_priv, i) {
16264                 err_printf(m, "Pipe [%d]:\n", i);
16265                 err_printf(m, "  Power: %s\n",
16266                            onoff(error->pipe[i].power_domain_on));
16267                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16268                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16269
16270                 err_printf(m, "Plane [%d]:\n", i);
16271                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16272                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16273                 if (INTEL_INFO(dev)->gen <= 3) {
16274                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16275                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16276                 }
16277                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16278                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16279                 if (INTEL_INFO(dev)->gen >= 4) {
16280                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16281                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16282                 }
16283
16284                 err_printf(m, "Cursor [%d]:\n", i);
16285                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16286                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16287                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16288         }
16289
16290         for (i = 0; i < error->num_transcoders; i++) {
16291                 err_printf(m, "CPU transcoder: %s\n",
16292                            transcoder_name(error->transcoder[i].cpu_transcoder));
16293                 err_printf(m, "  Power: %s\n",
16294                            onoff(error->transcoder[i].power_domain_on));
16295                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16296                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16297                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16298                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16299                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16300                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16301                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16302         }
16303 }