drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37
  38 #include "soc15_common.h"
  39 #include "soc15.h"
  40 #include "navi10_sdma_pkt_open.h"
  41 #include "nbio_v2_3.h"
  42 #include "sdma_common.h"
  43 #include "sdma_v5_0.h"
  44
  45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  47
  48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  53
  54 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
  56
  57 #define SDMA1_REG_OFFSET 0x600
  58 #define SDMA0_HYP_DEC_REG_START 0x5880
  59 #define SDMA0_HYP_DEC_REG_END 0x5893
  60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  61
  62 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  64 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  65 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  66
  67 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  92 };
  93
  94 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 115 };
 116
 117 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 120 };
 121
 122 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 125 };
 126
 127 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 134 };
 135
 136 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
 165 };
 166
 167 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 168 {
 169         u32 base;
 170
 171         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 172             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 173                 base = adev->reg_offset[GC_HWIP][0][1];
 174                 if (instance == 1)
 175                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 176         } else {
 177                 base = adev->reg_offset[GC_HWIP][0][0];
 178                 if (instance == 1)
 179                         internal_offset += SDMA1_REG_OFFSET;
 180         }
 181
 182         return base + internal_offset;
 183 }
 184
 185 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 186 {
 187         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
 188         case IP_VERSION(5, 0, 0):
 189                 soc15_program_register_sequence(adev,
 190                                                 golden_settings_sdma_5,
 191                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 192                 soc15_program_register_sequence(adev,
 193                                                 golden_settings_sdma_nv10,
 194                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 195                 break;
 196         case IP_VERSION(5, 0, 2):
 197                 soc15_program_register_sequence(adev,
 198                                                 golden_settings_sdma_5,
 199                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 200                 soc15_program_register_sequence(adev,
 201                                                 golden_settings_sdma_nv14,
 202                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 203                 break;
 204         case IP_VERSION(5, 0, 5):
 205                 if (amdgpu_sriov_vf(adev))
 206                         soc15_program_register_sequence(adev,
 207                                                         golden_settings_sdma_5_sriov,
 208                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 209                 else
 210                         soc15_program_register_sequence(adev,
 211                                                         golden_settings_sdma_5,
 212                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 213                 soc15_program_register_sequence(adev,
 214                                                 golden_settings_sdma_nv12,
 215                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 216                 break;
 217         case IP_VERSION(5, 0, 1):
 218                 soc15_program_register_sequence(adev,
 219                                                 golden_settings_sdma_cyan_skillfish,
 220                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
 221                 break;
 222         default:
 223                 break;
 224         }
 225 }
 226
 227 /**
 228  * sdma_v5_0_init_microcode - load ucode images from disk
 229  *
 230  * @adev: amdgpu_device pointer
 231  *
 232  * Use the firmware interface to load the ucode images into
 233  * the driver (not loaded into hw).
 234  * Returns 0 on success, error on failure.
 235  */
 236
 237 // emulation only, won't work on real chip
 238 // navi10 real chip need to use PSP to load firmware
 239 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 240 {
 241         int ret, i;
 242
 243         for (i = 0; i < adev->sdma.num_instances; i++) {
 244                 ret = amdgpu_sdma_init_microcode(adev, i, false);
 245                 if (ret)
 246                         return ret;
 247         }
 248
 249         return ret;
 250 }
 251
 252 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring,
 253                                               uint64_t addr)
 254 {
 255         unsigned ret;
 256
 257         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 258         amdgpu_ring_write(ring, lower_32_bits(addr));
 259         amdgpu_ring_write(ring, upper_32_bits(addr));
 260         amdgpu_ring_write(ring, 1);
 261         /* this is the offset we need patch later */
 262         ret = ring->wptr & ring->buf_mask;
 263         /* insert dummy here and patch it later */
 264         amdgpu_ring_write(ring, 0);
 265
 266         return ret;
 267 }
 268
 269 /**
 270  * sdma_v5_0_ring_get_rptr - get the current read pointer
 271  *
 272  * @ring: amdgpu ring pointer
 273  *
 274  * Get the current rptr from the hardware (NAVI10+).
 275  */
 276 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 277 {
 278         u64 *rptr;
 279
 280         /* XXX check if swapping is necessary on BE */
 281         rptr = (u64 *)ring->rptr_cpu_addr;
 282
 283         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 284         return ((*rptr) >> 2);
 285 }
 286
 287 /**
 288  * sdma_v5_0_ring_get_wptr - get the current write pointer
 289  *
 290  * @ring: amdgpu ring pointer
 291  *
 292  * Get the current wptr from the hardware (NAVI10+).
 293  */
 294 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 295 {
 296         struct amdgpu_device *adev = ring->adev;
 297         u64 wptr;
 298
 299         if (ring->use_doorbell) {
 300                 /* XXX check if swapping is necessary on BE */
 301                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 302                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 303         } else {
 304                 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 305                 wptr = wptr << 32;
 306                 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 307                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 308         }
 309
 310         return wptr >> 2;
 311 }
 312
 313 /**
 314  * sdma_v5_0_ring_set_wptr - commit the write pointer
 315  *
 316  * @ring: amdgpu ring pointer
 317  *
 318  * Write the wptr back to the hardware (NAVI10+).
 319  */
 320 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 321 {
 322         struct amdgpu_device *adev = ring->adev;
 323         uint32_t *wptr_saved;
 324         uint32_t *is_queue_unmap;
 325         uint64_t aggregated_db_index;
 326         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
 327
 328         DRM_DEBUG("Setting write pointer\n");
 329         if (ring->is_mes_queue) {
 330                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
 331                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
 332                                               sizeof(uint32_t));
 333                 aggregated_db_index =
 334                         amdgpu_mes_get_aggregated_doorbell_index(adev,
 335                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
 336
 337                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 338                              ring->wptr << 2);
 339                 *wptr_saved = ring->wptr << 2;
 340                 if (*is_queue_unmap) {
 341                         WDOORBELL64(aggregated_db_index, ring->wptr << 2);
 342                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 343                                         ring->doorbell_index, ring->wptr << 2);
 344                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 345                 } else {
 346                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 347                                         ring->doorbell_index, ring->wptr << 2);
 348                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 349
 350                         if (*is_queue_unmap)
 351                                 WDOORBELL64(aggregated_db_index,
 352                                             ring->wptr << 2);
 353                 }
 354         } else {
 355                 if (ring->use_doorbell) {
 356                         DRM_DEBUG("Using doorbell -- "
 357                                   "wptr_offs == 0x%08x "
 358                                   "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 359                                   "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 360                                   ring->wptr_offs,
 361                                   lower_32_bits(ring->wptr << 2),
 362                                   upper_32_bits(ring->wptr << 2));
 363                         /* XXX check if swapping is necessary on BE */
 364                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 365                                      ring->wptr << 2);
 366                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 367                                   ring->doorbell_index, ring->wptr << 2);
 368                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 369                 } else {
 370                         DRM_DEBUG("Not using doorbell -- "
 371                                   "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 372                                   "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 373                                   ring->me,
 374                                   lower_32_bits(ring->wptr << 2),
 375                                   ring->me,
 376                                   upper_32_bits(ring->wptr << 2));
 377                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
 378                                              ring->me, mmSDMA0_GFX_RB_WPTR),
 379                                         lower_32_bits(ring->wptr << 2));
 380                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
 381                                              ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 382                                         upper_32_bits(ring->wptr << 2));
 383                 }
 384         }
 385 }
 386
 387 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 388 {
 389         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 390         int i;
 391
 392         for (i = 0; i < count; i++)
 393                 if (sdma && sdma->burst_nop && (i == 0))
 394                         amdgpu_ring_write(ring, ring->funcs->nop |
 395                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 396                 else
 397                         amdgpu_ring_write(ring, ring->funcs->nop);
 398 }
 399
 400 /**
 401  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 402  *
 403  * @ring: amdgpu ring pointer
 404  * @job: job to retrieve vmid from
 405  * @ib: IB object to schedule
 406  * @flags: unused
 407  *
 408  * Schedule an IB in the DMA ring (NAVI10).
 409  */
 410 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 411                                    struct amdgpu_job *job,
 412                                    struct amdgpu_ib *ib,
 413                                    uint32_t flags)
 414 {
 415         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 416         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 417
 418         /* An IB packet must end on a 8 DW boundary--the next dword
 419          * must be on a 8-dword boundary. Our IB packet below is 6
 420          * dwords long, thus add x number of NOPs, such that, in
 421          * modular arithmetic,
 422          * wptr + 6 + x = 8k, k >= 0, which in C is,
 423          * (wptr + 6 + x) % 8 = 0.
 424          * The expression below, is a solution of x.
 425          */
 426         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 427
 428         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 429                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 430         /* base must be 32 byte aligned */
 431         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 432         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 433         amdgpu_ring_write(ring, ib->length_dw);
 434         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 435         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 436 }
 437
 438 /**
 439  * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 440  *
 441  * @ring: amdgpu ring pointer
 442  *
 443  * flush the IB by graphics cache rinse.
 444  */
 445 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 446 {
 447         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 448                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 449                             SDMA_GCR_GLI_INV(1);
 450
 451         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 452         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 453         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 454         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 455                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 456         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 457                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 458         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 459                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 460 }
 461
 462 /**
 463  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 464  *
 465  * @ring: amdgpu ring pointer
 466  *
 467  * Emit an hdp flush packet on the requested DMA ring.
 468  */
 469 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 470 {
 471         struct amdgpu_device *adev = ring->adev;
 472         u32 ref_and_mask = 0;
 473         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 474
 475         if (ring->me == 0)
 476                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 477         else
 478                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 479
 480         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 481                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 482                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 483         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 484         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 485         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 486         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 487         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 488                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 489 }
 490
 491 /**
 492  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 493  *
 494  * @ring: amdgpu ring pointer
 495  * @addr: address
 496  * @seq: sequence number
 497  * @flags: fence related flags
 498  *
 499  * Add a DMA fence packet to the ring to write
 500  * the fence seq number and DMA trap packet to generate
 501  * an interrupt if needed (NAVI10).
 502  */
 503 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 504                                       unsigned flags)
 505 {
 506         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 507         /* write the fence */
 508         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 509                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 510         /* zero in first two bits */
 511         BUG_ON(addr & 0x3);
 512         amdgpu_ring_write(ring, lower_32_bits(addr));
 513         amdgpu_ring_write(ring, upper_32_bits(addr));
 514         amdgpu_ring_write(ring, lower_32_bits(seq));
 515
 516         /* optionally write high bits as well */
 517         if (write64bit) {
 518                 addr += 4;
 519                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 520                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 521                 /* zero in first two bits */
 522                 BUG_ON(addr & 0x3);
 523                 amdgpu_ring_write(ring, lower_32_bits(addr));
 524                 amdgpu_ring_write(ring, upper_32_bits(addr));
 525                 amdgpu_ring_write(ring, upper_32_bits(seq));
 526         }
 527
 528         if (flags & AMDGPU_FENCE_FLAG_INT) {
 529                 uint32_t ctx = ring->is_mes_queue ?
 530                         (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
 531                 /* generate an interrupt */
 532                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 533                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
 534         }
 535 }
 536
 537
 538 /**
 539  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 540  *
 541  * @adev: amdgpu_device pointer
 542  *
 543  * Stop the gfx async dma ring buffers (NAVI10).
 544  */
 545 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 546 {
 547         u32 rb_cntl, ib_cntl;
 548         int i;
 549
 550         for (i = 0; i < adev->sdma.num_instances; i++) {
 551                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 552                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 553                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 554                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 555                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 556                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 557         }
 558 }
 559
 560 /**
 561  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 562  *
 563  * @adev: amdgpu_device pointer
 564  *
 565  * Stop the compute async dma queues (NAVI10).
 566  */
 567 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 568 {
 569         /* XXX todo */
 570 }
 571
 572 /**
 573  * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
 574  *
 575  * @adev: amdgpu_device pointer
 576  * @enable: enable/disable the DMA MEs context switch.
 577  *
 578  * Halt or unhalt the async dma engines context switch (NAVI10).
 579  */
 580 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 581 {
 582         u32 f32_cntl = 0, phase_quantum = 0;
 583         int i;
 584
 585         if (amdgpu_sdma_phase_quantum) {
 586                 unsigned value = amdgpu_sdma_phase_quantum;
 587                 unsigned unit = 0;
 588
 589                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 590                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 591                         value = (value + 1) >> 1;
 592                         unit++;
 593                 }
 594                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 595                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 596                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 597                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 598                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 599                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 600                         WARN_ONCE(1,
 601                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 602                                   value << unit);
 603                 }
 604                 phase_quantum =
 605                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 606                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 607         }
 608
 609         for (i = 0; i < adev->sdma.num_instances; i++) {
 610                 if (!amdgpu_sriov_vf(adev)) {
 611                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 612                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 613                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 614                 }
 615
 616                 if (enable && amdgpu_sdma_phase_quantum) {
 617                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 618                                phase_quantum);
 619                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 620                                phase_quantum);
 621                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 622                                phase_quantum);
 623                 }
 624                 if (!amdgpu_sriov_vf(adev))
 625                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 626         }
 627
 628 }
 629
 630 /**
 631  * sdma_v5_0_enable - stop the async dma engines
 632  *
 633  * @adev: amdgpu_device pointer
 634  * @enable: enable/disable the DMA MEs.
 635  *
 636  * Halt or unhalt the async dma engines (NAVI10).
 637  */
 638 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 639 {
 640         u32 f32_cntl;
 641         int i;
 642
 643         if (!enable) {
 644                 sdma_v5_0_gfx_stop(adev);
 645                 sdma_v5_0_rlc_stop(adev);
 646         }
 647
 648         if (amdgpu_sriov_vf(adev))
 649                 return;
 650
 651         for (i = 0; i < adev->sdma.num_instances; i++) {
 652                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 653                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 654                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 655         }
 656 }
 657
 658 /**
 659  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 660  *
 661  * @adev: amdgpu_device pointer
 662  *
 663  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 664  * Returns 0 for success, error for failure.
 665  */
 666 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 667 {
 668         struct amdgpu_ring *ring;
 669         u32 rb_cntl, ib_cntl;
 670         u32 rb_bufsz;
 671         u32 doorbell;
 672         u32 doorbell_offset;
 673         u32 temp;
 674         u32 wptr_poll_cntl;
 675         u64 wptr_gpu_addr;
 676         int i, r;
 677
 678         for (i = 0; i < adev->sdma.num_instances; i++) {
 679                 ring = &adev->sdma.instance[i].ring;
 680
 681                 if (!amdgpu_sriov_vf(adev))
 682                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 683
 684                 /* Set ring buffer size in dwords */
 685                 rb_bufsz = order_base_2(ring->ring_size / 4);
 686                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 687                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 688 #ifdef __BIG_ENDIAN
 689                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 690                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 691                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 692 #endif
 693                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 694
 695                 /* Initialize the ring buffer's read and write pointers */
 696                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 697                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 698                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 699                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 700
 701                 /* setup the wptr shadow polling */
 702                 wptr_gpu_addr = ring->wptr_gpu_addr;
 703                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 704                        lower_32_bits(wptr_gpu_addr));
 705                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 706                        upper_32_bits(wptr_gpu_addr));
 707                 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 708                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 709                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 710                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 711                                                F32_POLL_ENABLE, 1);
 712                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 713                        wptr_poll_cntl);
 714
 715                 /* set the wb address whether it's enabled or not */
 716                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 717                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 718                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 719                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 720
 721                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 722
 723                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
 724                        ring->gpu_addr >> 8);
 725                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
 726                        ring->gpu_addr >> 40);
 727
 728                 ring->wptr = 0;
 729
 730                 /* before programing wptr to a less value, need set minor_ptr_update first */
 731                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 732
 733                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 734                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
 735                                lower_32_bits(ring->wptr << 2));
 736                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
 737                                upper_32_bits(ring->wptr << 2));
 738                 }
 739
 740                 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 741                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 742                                                 mmSDMA0_GFX_DOORBELL_OFFSET));
 743
 744                 if (ring->use_doorbell) {
 745                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 746                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 747                                         OFFSET, ring->doorbell_index);
 748                 } else {
 749                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 750                 }
 751                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 752                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
 753                        doorbell_offset);
 754
 755                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 756                                                       ring->doorbell_index, 20);
 757
 758                 if (amdgpu_sriov_vf(adev))
 759                         sdma_v5_0_ring_set_wptr(ring);
 760
 761                 /* set minor_ptr_update to 0 after wptr programed */
 762                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 763
 764                 if (!amdgpu_sriov_vf(adev)) {
 765                         /* set utc l1 enable flag always to 1 */
 766                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 767                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 768
 769                         /* enable MCBP */
 770                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 771                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 772
 773                         /* Set up RESP_MODE to non-copy addresses */
 774                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 775                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 776                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 777                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 778
 779                         /* program default cache read and write policy */
 780                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 781                         /* clean read policy and write policy bits */
 782                         temp &= 0xFF0FFF;
 783                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 784                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 785                 }
 786
 787                 if (!amdgpu_sriov_vf(adev)) {
 788                         /* unhalt engine */
 789                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 790                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 791                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 792                 }
 793
 794                 /* enable DMA RB */
 795                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 796                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 797
 798                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 799                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 800 #ifdef __BIG_ENDIAN
 801                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 802 #endif
 803                 /* enable DMA IBs */
 804                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 805
 806                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 807                         sdma_v5_0_ctx_switch_enable(adev, true);
 808                         sdma_v5_0_enable(adev, true);
 809                 }
 810
 811                 r = amdgpu_ring_test_helper(ring);
 812                 if (r)
 813                         return r;
 814         }
 815
 816         return 0;
 817 }
 818
 819 /**
 820  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 821  *
 822  * @adev: amdgpu_device pointer
 823  *
 824  * Set up the compute DMA queues and enable them (NAVI10).
 825  * Returns 0 for success, error for failure.
 826  */
 827 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 828 {
 829         return 0;
 830 }
 831
 832 /**
 833  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 834  *
 835  * @adev: amdgpu_device pointer
 836  *
 837  * Loads the sDMA0/1 ucode.
 838  * Returns 0 for success, -EINVAL if the ucode is not available.
 839  */
 840 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 841 {
 842         const struct sdma_firmware_header_v1_0 *hdr;
 843         const __le32 *fw_data;
 844         u32 fw_size;
 845         int i, j;
 846
 847         /* halt the MEs */
 848         sdma_v5_0_enable(adev, false);
 849
 850         for (i = 0; i < adev->sdma.num_instances; i++) {
 851                 if (!adev->sdma.instance[i].fw)
 852                         return -EINVAL;
 853
 854                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 855                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 856                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 857
 858                 fw_data = (const __le32 *)
 859                         (adev->sdma.instance[i].fw->data +
 860                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 861
 862                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 863
 864                 for (j = 0; j < fw_size; j++) {
 865                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 866                                 msleep(1);
 867                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 868                 }
 869
 870                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 871         }
 872
 873         return 0;
 874 }
 875
 876 /**
 877  * sdma_v5_0_start - setup and start the async dma engines
 878  *
 879  * @adev: amdgpu_device pointer
 880  *
 881  * Set up the DMA engines and enable them (NAVI10).
 882  * Returns 0 for success, error for failure.
 883  */
 884 static int sdma_v5_0_start(struct amdgpu_device *adev)
 885 {
 886         int r = 0;
 887
 888         if (amdgpu_sriov_vf(adev)) {
 889                 sdma_v5_0_ctx_switch_enable(adev, false);
 890                 sdma_v5_0_enable(adev, false);
 891
 892                 /* set RB registers */
 893                 r = sdma_v5_0_gfx_resume(adev);
 894                 return r;
 895         }
 896
 897         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 898                 r = sdma_v5_0_load_microcode(adev);
 899                 if (r)
 900                         return r;
 901         }
 902
 903         /* unhalt the MEs */
 904         sdma_v5_0_enable(adev, true);
 905         /* enable sdma ring preemption */
 906         sdma_v5_0_ctx_switch_enable(adev, true);
 907
 908         /* start the gfx rings and rlc compute queues */
 909         r = sdma_v5_0_gfx_resume(adev);
 910         if (r)
 911                 return r;
 912         r = sdma_v5_0_rlc_resume(adev);
 913
 914         return r;
 915 }
 916
 917 static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
 918                               struct amdgpu_mqd_prop *prop)
 919 {
 920         struct v10_sdma_mqd *m = mqd;
 921         uint64_t wb_gpu_addr;
 922
 923         m->sdmax_rlcx_rb_cntl =
 924                 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 925                 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 926                 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
 927                 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
 928
 929         m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
 930         m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
 931
 932         m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
 933                                                   mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 934
 935         wb_gpu_addr = prop->wptr_gpu_addr;
 936         m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
 937         m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
 938
 939         wb_gpu_addr = prop->rptr_gpu_addr;
 940         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
 941         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
 942
 943         m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
 944                                                         mmSDMA0_GFX_IB_CNTL));
 945
 946         m->sdmax_rlcx_doorbell_offset =
 947                 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
 948
 949         m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
 950
 951         return 0;
 952 }
 953
 954 static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
 955 {
 956         adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
 957         adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
 958 }
 959
 960 /**
 961  * sdma_v5_0_ring_test_ring - simple async dma engine test
 962  *
 963  * @ring: amdgpu_ring structure holding ring information
 964  *
 965  * Test the DMA engine by writing using it to write an
 966  * value to memory. (NAVI10).
 967  * Returns 0 for success, error for failure.
 968  */
 969 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 970 {
 971         struct amdgpu_device *adev = ring->adev;
 972         unsigned i;
 973         unsigned index;
 974         int r;
 975         u32 tmp;
 976         u64 gpu_addr;
 977         volatile uint32_t *cpu_ptr = NULL;
 978
 979         tmp = 0xCAFEDEAD;
 980
 981         if (ring->is_mes_queue) {
 982                 uint32_t offset = 0;
 983                 offset = amdgpu_mes_ctx_get_offs(ring,
 984                                          AMDGPU_MES_CTX_PADDING_OFFS);
 985                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 986                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 987                 *cpu_ptr = tmp;
 988         } else {
 989                 r = amdgpu_device_wb_get(adev, &index);
 990                 if (r) {
 991                         dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 992                         return r;
 993                 }
 994
 995                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 996                 adev->wb.wb[index] = cpu_to_le32(tmp);
 997         }
 998
 999         r = amdgpu_ring_alloc(ring, 20);
1000         if (r) {
1001                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1002                 if (!ring->is_mes_queue)
1003                         amdgpu_device_wb_free(adev, index);
1004                 return r;
1005         }
1006
1007         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1008                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1009         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1010         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1011         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1012         amdgpu_ring_write(ring, 0xDEADBEEF);
1013         amdgpu_ring_commit(ring);
1014
1015         for (i = 0; i < adev->usec_timeout; i++) {
1016                 if (ring->is_mes_queue)
1017                         tmp = le32_to_cpu(*cpu_ptr);
1018                 else
1019                         tmp = le32_to_cpu(adev->wb.wb[index]);
1020                 if (tmp == 0xDEADBEEF)
1021                         break;
1022                 if (amdgpu_emu_mode == 1)
1023                         msleep(1);
1024                 else
1025                         udelay(1);
1026         }
1027
1028         if (i >= adev->usec_timeout)
1029                 r = -ETIMEDOUT;
1030
1031         if (!ring->is_mes_queue)
1032                 amdgpu_device_wb_free(adev, index);
1033
1034         return r;
1035 }
1036
1037 /**
1038  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1039  *
1040  * @ring: amdgpu_ring structure holding ring information
1041  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1042  *
1043  * Test a simple IB in the DMA ring (NAVI10).
1044  * Returns 0 on success, error on failure.
1045  */
1046 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1047 {
1048         struct amdgpu_device *adev = ring->adev;
1049         struct amdgpu_ib ib;
1050         struct dma_fence *f = NULL;
1051         unsigned index;
1052         long r;
1053         u32 tmp = 0;
1054         u64 gpu_addr;
1055         volatile uint32_t *cpu_ptr = NULL;
1056
1057         tmp = 0xCAFEDEAD;
1058         memset(&ib, 0, sizeof(ib));
1059
1060         if (ring->is_mes_queue) {
1061                 uint32_t offset = 0;
1062                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1063                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1064                 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1065
1066                 offset = amdgpu_mes_ctx_get_offs(ring,
1067                                          AMDGPU_MES_CTX_PADDING_OFFS);
1068                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1069                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1070                 *cpu_ptr = tmp;
1071         } else {
1072                 r = amdgpu_device_wb_get(adev, &index);
1073                 if (r) {
1074                         dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1075                         return r;
1076                 }
1077
1078                 gpu_addr = adev->wb.gpu_addr + (index * 4);
1079                 adev->wb.wb[index] = cpu_to_le32(tmp);
1080
1081                 r = amdgpu_ib_get(adev, NULL, 256,
1082                                         AMDGPU_IB_POOL_DIRECT, &ib);
1083                 if (r) {
1084                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1085                         goto err0;
1086                 }
1087         }
1088
1089         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1090                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1091         ib.ptr[1] = lower_32_bits(gpu_addr);
1092         ib.ptr[2] = upper_32_bits(gpu_addr);
1093         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1094         ib.ptr[4] = 0xDEADBEEF;
1095         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1096         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1097         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1098         ib.length_dw = 8;
1099
1100         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1101         if (r)
1102                 goto err1;
1103
1104         r = dma_fence_wait_timeout(f, false, timeout);
1105         if (r == 0) {
1106                 DRM_ERROR("amdgpu: IB test timed out\n");
1107                 r = -ETIMEDOUT;
1108                 goto err1;
1109         } else if (r < 0) {
1110                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1111                 goto err1;
1112         }
1113
1114         if (ring->is_mes_queue)
1115                 tmp = le32_to_cpu(*cpu_ptr);
1116         else
1117                 tmp = le32_to_cpu(adev->wb.wb[index]);
1118
1119         if (tmp == 0xDEADBEEF)
1120                 r = 0;
1121         else
1122                 r = -EINVAL;
1123
1124 err1:
1125         amdgpu_ib_free(adev, &ib, NULL);
1126         dma_fence_put(f);
1127 err0:
1128         if (!ring->is_mes_queue)
1129                 amdgpu_device_wb_free(adev, index);
1130         return r;
1131 }
1132
1133
1134 /**
1135  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1136  *
1137  * @ib: indirect buffer to fill with commands
1138  * @pe: addr of the page entry
1139  * @src: src addr to copy from
1140  * @count: number of page entries to update
1141  *
1142  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1143  */
1144 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1145                                   uint64_t pe, uint64_t src,
1146                                   unsigned count)
1147 {
1148         unsigned bytes = count * 8;
1149
1150         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1151                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1152         ib->ptr[ib->length_dw++] = bytes - 1;
1153         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1154         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1155         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1156         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1157         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1158
1159 }
1160
1161 /**
1162  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1163  *
1164  * @ib: indirect buffer to fill with commands
1165  * @pe: addr of the page entry
1166  * @value: dst addr to write into pe
1167  * @count: number of page entries to update
1168  * @incr: increase next addr by incr bytes
1169  *
1170  * Update PTEs by writing them manually using sDMA (NAVI10).
1171  */
1172 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1173                                    uint64_t value, unsigned count,
1174                                    uint32_t incr)
1175 {
1176         unsigned ndw = count * 2;
1177
1178         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1179                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1180         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1181         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1182         ib->ptr[ib->length_dw++] = ndw - 1;
1183         for (; ndw > 0; ndw -= 2) {
1184                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1185                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1186                 value += incr;
1187         }
1188 }
1189
1190 /**
1191  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1192  *
1193  * @ib: indirect buffer to fill with commands
1194  * @pe: addr of the page entry
1195  * @addr: dst addr to write into pe
1196  * @count: number of page entries to update
1197  * @incr: increase next addr by incr bytes
1198  * @flags: access flags
1199  *
1200  * Update the page tables using sDMA (NAVI10).
1201  */
1202 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1203                                      uint64_t pe,
1204                                      uint64_t addr, unsigned count,
1205                                      uint32_t incr, uint64_t flags)
1206 {
1207         /* for physically contiguous pages (vram) */
1208         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1209         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1210         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1211         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1212         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1213         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1214         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1215         ib->ptr[ib->length_dw++] = incr; /* increment size */
1216         ib->ptr[ib->length_dw++] = 0;
1217         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1218 }
1219
1220 /**
1221  * sdma_v5_0_ring_pad_ib - pad the IB
1222  * @ring: amdgpu_ring structure holding ring information
1223  * @ib: indirect buffer to fill with padding
1224  *
1225  * Pad the IB with NOPs to a boundary multiple of 8.
1226  */
1227 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1228 {
1229         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1230         u32 pad_count;
1231         int i;
1232
1233         pad_count = (-ib->length_dw) & 0x7;
1234         for (i = 0; i < pad_count; i++)
1235                 if (sdma && sdma->burst_nop && (i == 0))
1236                         ib->ptr[ib->length_dw++] =
1237                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1238                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1239                 else
1240                         ib->ptr[ib->length_dw++] =
1241                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1242 }
1243
1244
1245 /**
1246  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1247  *
1248  * @ring: amdgpu_ring pointer
1249  *
1250  * Make sure all previous operations are completed (CIK).
1251  */
1252 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1253 {
1254         uint32_t seq = ring->fence_drv.sync_seq;
1255         uint64_t addr = ring->fence_drv.gpu_addr;
1256
1257         /* wait for idle */
1258         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1259                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1260                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1261                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1262         amdgpu_ring_write(ring, addr & 0xfffffffc);
1263         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1264         amdgpu_ring_write(ring, seq); /* reference */
1265         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1266         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1267                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1268 }
1269
1270
1271 /**
1272  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1273  *
1274  * @ring: amdgpu_ring pointer
1275  * @vmid: vmid number to use
1276  * @pd_addr: address
1277  *
1278  * Update the page table base and flush the VM TLB
1279  * using sDMA (NAVI10).
1280  */
1281 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1282                                          unsigned vmid, uint64_t pd_addr)
1283 {
1284         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1285 }
1286
1287 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1288                                      uint32_t reg, uint32_t val)
1289 {
1290         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1291                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1292         amdgpu_ring_write(ring, reg);
1293         amdgpu_ring_write(ring, val);
1294 }
1295
1296 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1297                                          uint32_t val, uint32_t mask)
1298 {
1299         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1300                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1301                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1302         amdgpu_ring_write(ring, reg << 2);
1303         amdgpu_ring_write(ring, 0);
1304         amdgpu_ring_write(ring, val); /* reference */
1305         amdgpu_ring_write(ring, mask); /* mask */
1306         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1307                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1308 }
1309
1310 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1311                                                    uint32_t reg0, uint32_t reg1,
1312                                                    uint32_t ref, uint32_t mask)
1313 {
1314         amdgpu_ring_emit_wreg(ring, reg0, ref);
1315         /* wait for a cycle to reset vm_inv_eng*_ack */
1316         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1317         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1318 }
1319
1320 static int sdma_v5_0_early_init(void *handle)
1321 {
1322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323         int r;
1324
1325         r = sdma_v5_0_init_microcode(adev);
1326         if (r)
1327                 return r;
1328
1329         sdma_v5_0_set_ring_funcs(adev);
1330         sdma_v5_0_set_buffer_funcs(adev);
1331         sdma_v5_0_set_vm_pte_funcs(adev);
1332         sdma_v5_0_set_irq_funcs(adev);
1333         sdma_v5_0_set_mqd_funcs(adev);
1334
1335         return 0;
1336 }
1337
1338
1339 static int sdma_v5_0_sw_init(void *handle)
1340 {
1341         struct amdgpu_ring *ring;
1342         int r, i;
1343         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344
1345         /* SDMA trap event */
1346         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1347                               SDMA0_5_0__SRCID__SDMA_TRAP,
1348                               &adev->sdma.trap_irq);
1349         if (r)
1350                 return r;
1351
1352         /* SDMA trap event */
1353         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1354                               SDMA1_5_0__SRCID__SDMA_TRAP,
1355                               &adev->sdma.trap_irq);
1356         if (r)
1357                 return r;
1358
1359         for (i = 0; i < adev->sdma.num_instances; i++) {
1360                 ring = &adev->sdma.instance[i].ring;
1361                 ring->ring_obj = NULL;
1362                 ring->use_doorbell = true;
1363
1364                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1365                                 ring->use_doorbell?"true":"false");
1366
1367                 ring->doorbell_index = (i == 0) ?
1368                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1369                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1370
1371                 ring->vm_hub = AMDGPU_GFXHUB(0);
1372                 sprintf(ring->name, "sdma%d", i);
1373                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1374                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1375                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1376                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1377                 if (r)
1378                         return r;
1379         }
1380
1381         return r;
1382 }
1383
1384 static int sdma_v5_0_sw_fini(void *handle)
1385 {
1386         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1387         int i;
1388
1389         for (i = 0; i < adev->sdma.num_instances; i++)
1390                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1391
1392         amdgpu_sdma_destroy_inst_ctx(adev, false);
1393
1394         return 0;
1395 }
1396
1397 static int sdma_v5_0_hw_init(void *handle)
1398 {
1399         int r;
1400         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1401
1402         sdma_v5_0_init_golden_registers(adev);
1403
1404         r = sdma_v5_0_start(adev);
1405
1406         return r;
1407 }
1408
1409 static int sdma_v5_0_hw_fini(void *handle)
1410 {
1411         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1412
1413         if (amdgpu_sriov_vf(adev))
1414                 return 0;
1415
1416         sdma_v5_0_ctx_switch_enable(adev, false);
1417         sdma_v5_0_enable(adev, false);
1418
1419         return 0;
1420 }
1421
1422 static int sdma_v5_0_suspend(void *handle)
1423 {
1424         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1425
1426         return sdma_v5_0_hw_fini(adev);
1427 }
1428
1429 static int sdma_v5_0_resume(void *handle)
1430 {
1431         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1432
1433         return sdma_v5_0_hw_init(adev);
1434 }
1435
1436 static bool sdma_v5_0_is_idle(void *handle)
1437 {
1438         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1439         u32 i;
1440
1441         for (i = 0; i < adev->sdma.num_instances; i++) {
1442                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1443
1444                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1445                         return false;
1446         }
1447
1448         return true;
1449 }
1450
1451 static int sdma_v5_0_wait_for_idle(void *handle)
1452 {
1453         unsigned i;
1454         u32 sdma0, sdma1;
1455         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1456
1457         for (i = 0; i < adev->usec_timeout; i++) {
1458                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1459                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1460
1461                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1462                         return 0;
1463                 udelay(1);
1464         }
1465         return -ETIMEDOUT;
1466 }
1467
1468 static int sdma_v5_0_soft_reset(void *handle)
1469 {
1470         /* todo */
1471
1472         return 0;
1473 }
1474
1475 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1476 {
1477         int i, r = 0;
1478         struct amdgpu_device *adev = ring->adev;
1479         u32 index = 0;
1480         u64 sdma_gfx_preempt;
1481
1482         amdgpu_sdma_get_index_from_ring(ring, &index);
1483         if (index == 0)
1484                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1485         else
1486                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1487
1488         /* assert preemption condition */
1489         amdgpu_ring_set_preempt_cond_exec(ring, false);
1490
1491         /* emit the trailing fence */
1492         ring->trail_seq += 1;
1493         amdgpu_ring_alloc(ring, 10);
1494         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1495                                   ring->trail_seq, 0);
1496         amdgpu_ring_commit(ring);
1497
1498         /* assert IB preemption */
1499         WREG32(sdma_gfx_preempt, 1);
1500
1501         /* poll the trailing fence */
1502         for (i = 0; i < adev->usec_timeout; i++) {
1503                 if (ring->trail_seq ==
1504                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1505                         break;
1506                 udelay(1);
1507         }
1508
1509         if (i >= adev->usec_timeout) {
1510                 r = -EINVAL;
1511                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1512         }
1513
1514         /* deassert IB preemption */
1515         WREG32(sdma_gfx_preempt, 0);
1516
1517         /* deassert the preemption condition */
1518         amdgpu_ring_set_preempt_cond_exec(ring, true);
1519         return r;
1520 }
1521
1522 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1523                                         struct amdgpu_irq_src *source,
1524                                         unsigned type,
1525                                         enum amdgpu_interrupt_state state)
1526 {
1527         u32 sdma_cntl;
1528
1529         if (!amdgpu_sriov_vf(adev)) {
1530                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1531                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1532                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1533
1534                 sdma_cntl = RREG32(reg_offset);
1535                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1536                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1537                 WREG32(reg_offset, sdma_cntl);
1538         }
1539
1540         return 0;
1541 }
1542
1543 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1544                                       struct amdgpu_irq_src *source,
1545                                       struct amdgpu_iv_entry *entry)
1546 {
1547         uint32_t mes_queue_id = entry->src_data[0];
1548
1549         DRM_DEBUG("IH: SDMA trap\n");
1550
1551         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1552                 struct amdgpu_mes_queue *queue;
1553
1554                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1555
1556                 spin_lock(&adev->mes.queue_id_lock);
1557                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1558                 if (queue) {
1559                         DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1560                         amdgpu_fence_process(queue->ring);
1561                 }
1562                 spin_unlock(&adev->mes.queue_id_lock);
1563                 return 0;
1564         }
1565
1566         switch (entry->client_id) {
1567         case SOC15_IH_CLIENTID_SDMA0:
1568                 switch (entry->ring_id) {
1569                 case 0:
1570                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1571                         break;
1572                 case 1:
1573                         /* XXX compute */
1574                         break;
1575                 case 2:
1576                         /* XXX compute */
1577                         break;
1578                 case 3:
1579                         /* XXX page queue*/
1580                         break;
1581                 }
1582                 break;
1583         case SOC15_IH_CLIENTID_SDMA1:
1584                 switch (entry->ring_id) {
1585                 case 0:
1586                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1587                         break;
1588                 case 1:
1589                         /* XXX compute */
1590                         break;
1591                 case 2:
1592                         /* XXX compute */
1593                         break;
1594                 case 3:
1595                         /* XXX page queue*/
1596                         break;
1597                 }
1598                 break;
1599         }
1600         return 0;
1601 }
1602
1603 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1604                                               struct amdgpu_irq_src *source,
1605                                               struct amdgpu_iv_entry *entry)
1606 {
1607         return 0;
1608 }
1609
1610 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1611                                                        bool enable)
1612 {
1613         uint32_t data, def;
1614         int i;
1615
1616         for (i = 0; i < adev->sdma.num_instances; i++) {
1617                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1618                         /* Enable sdma clock gating */
1619                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1620                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1621                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1622                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1623                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1624                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1625                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1626                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1627                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1628                         if (def != data)
1629                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1630                 } else {
1631                         /* Disable sdma clock gating */
1632                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1633                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1634                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1635                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1636                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1637                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1638                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1639                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1640                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1641                         if (def != data)
1642                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1643                 }
1644         }
1645 }
1646
1647 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1648                                                       bool enable)
1649 {
1650         uint32_t data, def;
1651         int i;
1652
1653         for (i = 0; i < adev->sdma.num_instances; i++) {
1654                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1655                         /* Enable sdma mem light sleep */
1656                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1657                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1658                         if (def != data)
1659                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1660
1661                 } else {
1662                         /* Disable sdma mem light sleep */
1663                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1664                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1665                         if (def != data)
1666                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1667
1668                 }
1669         }
1670 }
1671
1672 static int sdma_v5_0_set_clockgating_state(void *handle,
1673                                            enum amd_clockgating_state state)
1674 {
1675         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1676
1677         if (amdgpu_sriov_vf(adev))
1678                 return 0;
1679
1680         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1681         case IP_VERSION(5, 0, 0):
1682         case IP_VERSION(5, 0, 2):
1683         case IP_VERSION(5, 0, 5):
1684                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1685                                 state == AMD_CG_STATE_GATE);
1686                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1687                                 state == AMD_CG_STATE_GATE);
1688                 break;
1689         default:
1690                 break;
1691         }
1692
1693         return 0;
1694 }
1695
1696 static int sdma_v5_0_set_powergating_state(void *handle,
1697                                           enum amd_powergating_state state)
1698 {
1699         return 0;
1700 }
1701
1702 static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1703 {
1704         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1705         int data;
1706
1707         if (amdgpu_sriov_vf(adev))
1708                 *flags = 0;
1709
1710         /* AMD_CG_SUPPORT_SDMA_MGCG */
1711         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1712         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1713                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1714
1715         /* AMD_CG_SUPPORT_SDMA_LS */
1716         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1717         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1718                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1719 }
1720
1721 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1722         .name = "sdma_v5_0",
1723         .early_init = sdma_v5_0_early_init,
1724         .late_init = NULL,
1725         .sw_init = sdma_v5_0_sw_init,
1726         .sw_fini = sdma_v5_0_sw_fini,
1727         .hw_init = sdma_v5_0_hw_init,
1728         .hw_fini = sdma_v5_0_hw_fini,
1729         .suspend = sdma_v5_0_suspend,
1730         .resume = sdma_v5_0_resume,
1731         .is_idle = sdma_v5_0_is_idle,
1732         .wait_for_idle = sdma_v5_0_wait_for_idle,
1733         .soft_reset = sdma_v5_0_soft_reset,
1734         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1735         .set_powergating_state = sdma_v5_0_set_powergating_state,
1736         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1737 };
1738
1739 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1740         .type = AMDGPU_RING_TYPE_SDMA,
1741         .align_mask = 0xf,
1742         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1743         .support_64bit_ptrs = true,
1744         .secure_submission_supported = true,
1745         .get_rptr = sdma_v5_0_ring_get_rptr,
1746         .get_wptr = sdma_v5_0_ring_get_wptr,
1747         .set_wptr = sdma_v5_0_ring_set_wptr,
1748         .emit_frame_size =
1749                 5 + /* sdma_v5_0_ring_init_cond_exec */
1750                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1751                 3 + /* hdp_invalidate */
1752                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1753                 /* sdma_v5_0_ring_emit_vm_flush */
1754                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1755                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1756                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1757         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1758         .emit_ib = sdma_v5_0_ring_emit_ib,
1759         .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1760         .emit_fence = sdma_v5_0_ring_emit_fence,
1761         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1762         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1763         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1764         .test_ring = sdma_v5_0_ring_test_ring,
1765         .test_ib = sdma_v5_0_ring_test_ib,
1766         .insert_nop = sdma_v5_0_ring_insert_nop,
1767         .pad_ib = sdma_v5_0_ring_pad_ib,
1768         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1769         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1770         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1771         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1772         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1773 };
1774
1775 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1776 {
1777         int i;
1778
1779         for (i = 0; i < adev->sdma.num_instances; i++) {
1780                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1781                 adev->sdma.instance[i].ring.me = i;
1782         }
1783 }
1784
1785 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1786         .set = sdma_v5_0_set_trap_irq_state,
1787         .process = sdma_v5_0_process_trap_irq,
1788 };
1789
1790 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1791         .process = sdma_v5_0_process_illegal_inst_irq,
1792 };
1793
1794 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1795 {
1796         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1797                                         adev->sdma.num_instances;
1798         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1799         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1800 }
1801
1802 /**
1803  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1804  *
1805  * @ib: indirect buffer to copy to
1806  * @src_offset: src GPU address
1807  * @dst_offset: dst GPU address
1808  * @byte_count: number of bytes to xfer
1809  * @copy_flags: copy flags for the buffers
1810  *
1811  * Copy GPU buffers using the DMA engine (NAVI10).
1812  * Used by the amdgpu ttm implementation to move pages if
1813  * registered as the asic copy callback.
1814  */
1815 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1816                                        uint64_t src_offset,
1817                                        uint64_t dst_offset,
1818                                        uint32_t byte_count,
1819                                        uint32_t copy_flags)
1820 {
1821         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1822                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1823                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
1824         ib->ptr[ib->length_dw++] = byte_count - 1;
1825         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1826         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1827         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1828         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1829         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1830 }
1831
1832 /**
1833  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1834  *
1835  * @ib: indirect buffer to fill
1836  * @src_data: value to write to buffer
1837  * @dst_offset: dst GPU address
1838  * @byte_count: number of bytes to xfer
1839  *
1840  * Fill GPU buffers using the DMA engine (NAVI10).
1841  */
1842 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1843                                        uint32_t src_data,
1844                                        uint64_t dst_offset,
1845                                        uint32_t byte_count)
1846 {
1847         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1848         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1849         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1850         ib->ptr[ib->length_dw++] = src_data;
1851         ib->ptr[ib->length_dw++] = byte_count - 1;
1852 }
1853
1854 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1855         .copy_max_bytes = 0x400000,
1856         .copy_num_dw = 7,
1857         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1858
1859         .fill_max_bytes = 0x400000,
1860         .fill_num_dw = 5,
1861         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1862 };
1863
1864 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1865 {
1866         if (adev->mman.buffer_funcs == NULL) {
1867                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1868                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1869         }
1870 }
1871
1872 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1873         .copy_pte_num_dw = 7,
1874         .copy_pte = sdma_v5_0_vm_copy_pte,
1875         .write_pte = sdma_v5_0_vm_write_pte,
1876         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1877 };
1878
1879 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1880 {
1881         unsigned i;
1882
1883         if (adev->vm_manager.vm_pte_funcs == NULL) {
1884                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1885                 for (i = 0; i < adev->sdma.num_instances; i++) {
1886                         adev->vm_manager.vm_pte_scheds[i] =
1887                                 &adev->sdma.instance[i].ring.sched;
1888                 }
1889                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1890         }
1891 }
1892
1893 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1894         .type = AMD_IP_BLOCK_TYPE_SDMA,
1895         .major = 5,
1896         .minor = 0,
1897         .rev = 0,
1898         .funcs = &sdma_v5_0_ip_funcs,
1899 };