drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_11_0_0_offset.h"
  30 #include "gc/gc_11_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v11_structs.h"
  33 #include "mes_v11_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
  41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
  42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin");
  43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
  44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
  45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin");
  46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
  47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
  48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin");
  49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
  50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");
  51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");
  52 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");
  53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");
  54 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin");
  55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin");
  56
  57 static int mes_v11_0_hw_init(void *handle);
  58 static int mes_v11_0_hw_fini(void *handle);
  59 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
  60 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
  61
  62 #define MES_EOP_SIZE   2048
  63 #define GFX_MES_DRAM_SIZE       0x80000
  64
  65 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
  66 {
  67         struct amdgpu_device *adev = ring->adev;
  68
  69         if (ring->use_doorbell) {
  70                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  71                              ring->wptr);
  72                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  73         } else {
  74                 BUG();
  75         }
  76 }
  77
  78 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
  79 {
  80         return *ring->rptr_cpu_addr;
  81 }
  82
  83 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
  84 {
  85         u64 wptr;
  86
  87         if (ring->use_doorbell)
  88                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  89         else
  90                 BUG();
  91         return wptr;
  92 }
  93
  94 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
  95         .type = AMDGPU_RING_TYPE_MES,
  96         .align_mask = 1,
  97         .nop = 0,
  98         .support_64bit_ptrs = true,
  99         .get_rptr = mes_v11_0_ring_get_rptr,
 100         .get_wptr = mes_v11_0_ring_get_wptr,
 101         .set_wptr = mes_v11_0_ring_set_wptr,
 102         .insert_nop = amdgpu_ring_insert_nop,
 103 };
 104
 105 static const char *mes_v11_0_opcodes[] = {
 106         "SET_HW_RSRC",
 107         "SET_SCHEDULING_CONFIG",
 108         "ADD_QUEUE",
 109         "REMOVE_QUEUE",
 110         "PERFORM_YIELD",
 111         "SET_GANG_PRIORITY_LEVEL",
 112         "SUSPEND",
 113         "RESUME",
 114         "RESET",
 115         "SET_LOG_BUFFER",
 116         "CHANGE_GANG_PRORITY",
 117         "QUERY_SCHEDULER_STATUS",
 118         "PROGRAM_GDS",
 119         "SET_DEBUG_VMID",
 120         "MISC",
 121         "UPDATE_ROOT_PAGE_TABLE",
 122         "AMD_LOG",
 123         "unused",
 124         "unused",
 125         "SET_HW_RSRC_1",
 126 };
 127
 128 static const char *mes_v11_0_misc_opcodes[] = {
 129         "WRITE_REG",
 130         "INV_GART",
 131         "QUERY_STATUS",
 132         "READ_REG",
 133         "WAIT_REG_MEM",
 134         "SET_SHADER_DEBUGGER",
 135 };
 136
 137 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt)
 138 {
 139         const char *op_str = NULL;
 140
 141         if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes))
 142                 op_str = mes_v11_0_opcodes[x_pkt->header.opcode];
 143
 144         return op_str;
 145 }
 146
 147 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
 148 {
 149         const char *op_str = NULL;
 150
 151         if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
 152             (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes)))
 153                 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode];
 154
 155         return op_str;
 156 }
 157
 158 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
 159                                                     void *pkt, int size,
 160                                                     int api_status_off)
 161 {
 162         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 163         signed long timeout = 3000000; /* 3000 ms */
 164         struct amdgpu_device *adev = mes->adev;
 165         struct amdgpu_ring *ring = &mes->ring;
 166         struct MES_API_STATUS *api_status;
 167         union MESAPI__MISC *x_pkt = pkt;
 168         const char *op_str, *misc_op_str;
 169         unsigned long flags;
 170         u64 status_gpu_addr;
 171         u32 status_offset;
 172         u64 *status_ptr;
 173         signed long r;
 174         int ret;
 175
 176         if (x_pkt->header.opcode >= MES_SCH_API_MAX)
 177                 return -EINVAL;
 178
 179         if (amdgpu_emu_mode) {
 180                 timeout *= 100;
 181         } else if (amdgpu_sriov_vf(adev)) {
 182                 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
 183                 timeout = 15 * 600 * 1000;
 184         }
 185
 186         ret = amdgpu_device_wb_get(adev, &status_offset);
 187         if (ret)
 188                 return ret;
 189
 190         status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
 191         status_ptr = (u64 *)&adev->wb.wb[status_offset];
 192         *status_ptr = 0;
 193
 194         spin_lock_irqsave(&mes->ring_lock, flags);
 195         r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
 196         if (r)
 197                 goto error_unlock_free;
 198
 199         api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
 200         api_status->api_completion_fence_addr = status_gpu_addr;
 201         api_status->api_completion_fence_value = 1;
 202
 203         amdgpu_ring_write_multiple(ring, pkt, size / 4);
 204
 205         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 206         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 207         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 208         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 209         mes_status_pkt.api_status.api_completion_fence_addr =
 210                 ring->fence_drv.gpu_addr;
 211         mes_status_pkt.api_status.api_completion_fence_value =
 212                 ++ring->fence_drv.sync_seq;
 213
 214         amdgpu_ring_write_multiple(ring, &mes_status_pkt,
 215                                    sizeof(mes_status_pkt) / 4);
 216
 217         amdgpu_ring_commit(ring);
 218         spin_unlock_irqrestore(&mes->ring_lock, flags);
 219
 220         op_str = mes_v11_0_get_op_string(x_pkt);
 221         misc_op_str = mes_v11_0_get_misc_op_string(x_pkt);
 222
 223         if (misc_op_str)
 224                 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str,
 225                         misc_op_str);
 226         else if (op_str)
 227                 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str);
 228         else
 229                 dev_dbg(adev->dev, "MES msg=%d was emitted\n",
 230                         x_pkt->header.opcode);
 231
 232         r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, timeout);
 233         if (r < 1 || !*status_ptr) {
 234
 235                 if (misc_op_str)
 236                         dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n",
 237                                 op_str, misc_op_str);
 238                 else if (op_str)
 239                         dev_err(adev->dev, "MES failed to respond to msg=%s\n",
 240                                 op_str);
 241                 else
 242                         dev_err(adev->dev, "MES failed to respond to msg=%d\n",
 243                                 x_pkt->header.opcode);
 244
 245                 while (halt_if_hws_hang)
 246                         schedule();
 247
 248                 r = -ETIMEDOUT;
 249                 goto error_wb_free;
 250         }
 251
 252         amdgpu_device_wb_free(adev, status_offset);
 253         return 0;
 254
 255 error_unlock_free:
 256         spin_unlock_irqrestore(&mes->ring_lock, flags);
 257
 258 error_wb_free:
 259         amdgpu_device_wb_free(adev, status_offset);
 260         return r;
 261 }
 262
 263 static int convert_to_mes_queue_type(int queue_type)
 264 {
 265         if (queue_type == AMDGPU_RING_TYPE_GFX)
 266                 return MES_QUEUE_TYPE_GFX;
 267         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 268                 return MES_QUEUE_TYPE_COMPUTE;
 269         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 270                 return MES_QUEUE_TYPE_SDMA;
 271         else
 272                 BUG();
 273         return -1;
 274 }
 275
 276 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 277                                   struct mes_add_queue_input *input)
 278 {
 279         struct amdgpu_device *adev = mes->adev;
 280         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 281         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
 282         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 283
 284         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 285
 286         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 287         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 288         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 289
 290         mes_add_queue_pkt.process_id = input->process_id;
 291         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 292         mes_add_queue_pkt.process_va_start = input->process_va_start;
 293         mes_add_queue_pkt.process_va_end = input->process_va_end;
 294         mes_add_queue_pkt.process_quantum = input->process_quantum;
 295         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 296         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 297         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 298         mes_add_queue_pkt.inprocess_gang_priority =
 299                 input->inprocess_gang_priority;
 300         mes_add_queue_pkt.gang_global_priority_level =
 301                 input->gang_global_priority_level;
 302         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 303         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 304
 305         if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
 306                         AMDGPU_MES_API_VERSION_SHIFT) >= 2)
 307                 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
 308         else
 309                 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 310
 311         mes_add_queue_pkt.queue_type =
 312                 convert_to_mes_queue_type(input->queue_type);
 313         mes_add_queue_pkt.paging = input->paging;
 314         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 315         mes_add_queue_pkt.gws_base = input->gws_base;
 316         mes_add_queue_pkt.gws_size = input->gws_size;
 317         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 318         mes_add_queue_pkt.tma_addr = input->tma_addr;
 319         mes_add_queue_pkt.trap_en = input->trap_en;
 320         mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
 321         mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 322
 323         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 324         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 325         mes_add_queue_pkt.gds_size = input->queue_size;
 326
 327         mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled;
 328
 329         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 330                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 331                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 332 }
 333
 334 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
 335                                      struct mes_remove_queue_input *input)
 336 {
 337         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 338
 339         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 340
 341         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 342         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 343         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 344
 345         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 346         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 347
 348         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 349                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 350                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 351 }
 352
 353 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes,
 354                                       struct mes_map_legacy_queue_input *input)
 355 {
 356         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 357
 358         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 359
 360         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 361         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 362         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 363
 364         mes_add_queue_pkt.pipe_id = input->pipe_id;
 365         mes_add_queue_pkt.queue_id = input->queue_id;
 366         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 367         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 368         mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 369         mes_add_queue_pkt.queue_type =
 370                 convert_to_mes_queue_type(input->queue_type);
 371         mes_add_queue_pkt.map_legacy_kq = 1;
 372
 373         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 374                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 375                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 376 }
 377
 378 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 379                         struct mes_unmap_legacy_queue_input *input)
 380 {
 381         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 382
 383         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 384
 385         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 386         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 387         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 388
 389         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 390         mes_remove_queue_pkt.gang_context_addr = 0;
 391
 392         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 393         mes_remove_queue_pkt.queue_id = input->queue_id;
 394
 395         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 396                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 397                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 398                 mes_remove_queue_pkt.tf_data =
 399                         lower_32_bits(input->trail_fence_data);
 400         } else {
 401                 mes_remove_queue_pkt.unmap_legacy_queue = 1;
 402                 mes_remove_queue_pkt.queue_type =
 403                         convert_to_mes_queue_type(input->queue_type);
 404         }
 405
 406         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 407                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 408                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 409 }
 410
 411 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
 412                                   struct mes_suspend_gang_input *input)
 413 {
 414         return 0;
 415 }
 416
 417 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
 418                                  struct mes_resume_gang_input *input)
 419 {
 420         return 0;
 421 }
 422
 423 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
 424 {
 425         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 426
 427         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 428
 429         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 430         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 431         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 432
 433         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 434                         &mes_status_pkt, sizeof(mes_status_pkt),
 435                         offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
 436 }
 437
 438 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
 439                              struct mes_misc_op_input *input)
 440 {
 441         union MESAPI__MISC misc_pkt;
 442
 443         memset(&misc_pkt, 0, sizeof(misc_pkt));
 444
 445         misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
 446         misc_pkt.header.opcode = MES_SCH_API_MISC;
 447         misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 448
 449         switch (input->op) {
 450         case MES_MISC_OP_READ_REG:
 451                 misc_pkt.opcode = MESAPI_MISC__READ_REG;
 452                 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
 453                 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
 454                 break;
 455         case MES_MISC_OP_WRITE_REG:
 456                 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
 457                 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
 458                 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
 459                 break;
 460         case MES_MISC_OP_WRM_REG_WAIT:
 461                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 462                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
 463                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 464                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 465                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 466                 misc_pkt.wait_reg_mem.reg_offset2 = 0;
 467                 break;
 468         case MES_MISC_OP_WRM_REG_WR_WAIT:
 469                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 470                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
 471                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 472                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 473                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 474                 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
 475                 break;
 476         case MES_MISC_OP_SET_SHADER_DEBUGGER:
 477                 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
 478                 misc_pkt.set_shader_debugger.process_context_addr =
 479                                 input->set_shader_debugger.process_context_addr;
 480                 misc_pkt.set_shader_debugger.flags.u32all =
 481                                 input->set_shader_debugger.flags.u32all;
 482                 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
 483                                 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
 484                 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
 485                                 input->set_shader_debugger.tcp_watch_cntl,
 486                                 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
 487                 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
 488                 break;
 489         default:
 490                 DRM_ERROR("unsupported misc op (%d) \n", input->op);
 491                 return -EINVAL;
 492         }
 493
 494         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 495                         &misc_pkt, sizeof(misc_pkt),
 496                         offsetof(union MESAPI__MISC, api_status));
 497 }
 498
 499 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 500 {
 501         int i;
 502         struct amdgpu_device *adev = mes->adev;
 503         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 504
 505         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 506
 507         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 508         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 509         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 510
 511         mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 512         mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 513         mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 514         mes_set_hw_res_pkt.paging_vmid = 0;
 515         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
 516         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 517                 mes->query_status_fence_gpu_addr;
 518
 519         for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 520                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
 521                         mes->compute_hqd_mask[i];
 522
 523         for (i = 0; i < MAX_GFX_PIPES; i++)
 524                 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
 525
 526         for (i = 0; i < MAX_SDMA_PIPES; i++)
 527                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
 528
 529         for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 530                 mes_set_hw_res_pkt.aggregated_doorbells[i] =
 531                         mes->aggregated_doorbells[i];
 532
 533         for (i = 0; i < 5; i++) {
 534                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 535                 mes_set_hw_res_pkt.mmhub_base[i] =
 536                                 adev->reg_offset[MMHUB_HWIP][0][i];
 537                 mes_set_hw_res_pkt.osssys_base[i] =
 538                 adev->reg_offset[OSSSYS_HWIP][0][i];
 539         }
 540
 541         mes_set_hw_res_pkt.disable_reset = 1;
 542         mes_set_hw_res_pkt.disable_mes_log = 1;
 543         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 544         mes_set_hw_res_pkt.enable_reg_active_poll = 1;
 545         mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
 546         mes_set_hw_res_pkt.oversubscription_timer = 50;
 547         if (amdgpu_mes_log_enable) {
 548                 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
 549                 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
 550                                         mes->event_log_gpu_addr;
 551         }
 552
 553         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 554                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 555                         offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
 556 }
 557
 558 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
 559 {
 560         int size = 128 * PAGE_SIZE;
 561         int ret = 0;
 562         struct amdgpu_device *adev = mes->adev;
 563         union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
 564         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 565
 566         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 567         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
 568         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 569         mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
 570
 571         ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
 572                                 AMDGPU_GEM_DOMAIN_VRAM,
 573                                 &mes->resource_1,
 574                                 &mes->resource_1_gpu_addr,
 575                                 &mes->resource_1_addr);
 576         if (ret) {
 577                 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
 578                 return ret;
 579         }
 580
 581         mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr;
 582         mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size;
 583         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 584                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 585                         offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
 586 }
 587
 588 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
 589         .add_hw_queue = mes_v11_0_add_hw_queue,
 590         .remove_hw_queue = mes_v11_0_remove_hw_queue,
 591         .map_legacy_queue = mes_v11_0_map_legacy_queue,
 592         .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
 593         .suspend_gang = mes_v11_0_suspend_gang,
 594         .resume_gang = mes_v11_0_resume_gang,
 595         .misc_op = mes_v11_0_misc_op,
 596 };
 597
 598 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 599                                            enum admgpu_mes_pipe pipe)
 600 {
 601         int r;
 602         const struct mes_firmware_header_v1_0 *mes_hdr;
 603         const __le32 *fw_data;
 604         unsigned fw_size;
 605
 606         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 607                 adev->mes.fw[pipe]->data;
 608
 609         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 610                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 611         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 612
 613         r = amdgpu_bo_create_reserved(adev, fw_size,
 614                                       PAGE_SIZE,
 615                                       AMDGPU_GEM_DOMAIN_VRAM |
 616                                       AMDGPU_GEM_DOMAIN_GTT,
 617                                       &adev->mes.ucode_fw_obj[pipe],
 618                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 619                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 620         if (r) {
 621                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 622                 return r;
 623         }
 624
 625         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 626
 627         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 628         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 629
 630         return 0;
 631 }
 632
 633 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 634                                                 enum admgpu_mes_pipe pipe)
 635 {
 636         int r;
 637         const struct mes_firmware_header_v1_0 *mes_hdr;
 638         const __le32 *fw_data;
 639         unsigned fw_size;
 640
 641         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 642                 adev->mes.fw[pipe]->data;
 643
 644         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 645                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 646         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 647
 648         if (fw_size > GFX_MES_DRAM_SIZE) {
 649                 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n",
 650                         pipe, fw_size, GFX_MES_DRAM_SIZE);
 651                 return -EINVAL;
 652         }
 653
 654         r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE,
 655                                       64 * 1024,
 656                                       AMDGPU_GEM_DOMAIN_VRAM |
 657                                       AMDGPU_GEM_DOMAIN_GTT,
 658                                       &adev->mes.data_fw_obj[pipe],
 659                                       &adev->mes.data_fw_gpu_addr[pipe],
 660                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 661         if (r) {
 662                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 663                 return r;
 664         }
 665
 666         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 667
 668         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 669         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 670
 671         return 0;
 672 }
 673
 674 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
 675                                          enum admgpu_mes_pipe pipe)
 676 {
 677         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 678                               &adev->mes.data_fw_gpu_addr[pipe],
 679                               (void **)&adev->mes.data_fw_ptr[pipe]);
 680
 681         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 682                               &adev->mes.ucode_fw_gpu_addr[pipe],
 683                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 684 }
 685
 686 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 687 {
 688         uint64_t ucode_addr;
 689         uint32_t pipe, data = 0;
 690
 691         if (enable) {
 692                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 693                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 694                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 695                              MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
 696                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 697
 698                 mutex_lock(&adev->srbm_mutex);
 699                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 700                         if (!adev->enable_mes_kiq &&
 701                             pipe == AMDGPU_MES_KIQ_PIPE)
 702                                 continue;
 703
 704                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 705
 706                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 707                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 708                                      lower_32_bits(ucode_addr));
 709                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 710                                      upper_32_bits(ucode_addr));
 711                 }
 712                 soc21_grbm_select(adev, 0, 0, 0, 0);
 713                 mutex_unlock(&adev->srbm_mutex);
 714
 715                 /* unhalt MES and activate pipe0 */
 716                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 717                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 718                                      adev->enable_mes_kiq ? 1 : 0);
 719                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 720
 721                 if (amdgpu_emu_mode)
 722                         msleep(100);
 723                 else
 724                         udelay(500);
 725         } else {
 726                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 727                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 728                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 729                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 730                                      MES_INVALIDATE_ICACHE, 1);
 731                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 732                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 733                                      adev->enable_mes_kiq ? 1 : 0);
 734                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 735                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 736         }
 737 }
 738
 739 /* This function is for backdoor MES firmware */
 740 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
 741                                     enum admgpu_mes_pipe pipe, bool prime_icache)
 742 {
 743         int r;
 744         uint32_t data;
 745         uint64_t ucode_addr;
 746
 747         mes_v11_0_enable(adev, false);
 748
 749         if (!adev->mes.fw[pipe])
 750                 return -EINVAL;
 751
 752         r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
 753         if (r)
 754                 return r;
 755
 756         r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
 757         if (r) {
 758                 mes_v11_0_free_ucode_buffers(adev, pipe);
 759                 return r;
 760         }
 761
 762         mutex_lock(&adev->srbm_mutex);
 763         /* me=3, pipe=0, queue=0 */
 764         soc21_grbm_select(adev, 3, pipe, 0, 0);
 765
 766         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 767
 768         /* set ucode start address */
 769         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 770         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 771                      lower_32_bits(ucode_addr));
 772         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 773                      upper_32_bits(ucode_addr));
 774
 775         /* set ucode fimrware address */
 776         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 777                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 778         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 779                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 780
 781         /* set ucode instruction cache boundary to 2M-1 */
 782         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 783
 784         /* set ucode data firmware address */
 785         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 786                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 787         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 788                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 789
 790         /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */
 791         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
 792
 793         if (prime_icache) {
 794                 /* invalidate ICACHE */
 795                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 796                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 797                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 798                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 799
 800                 /* prime the ICACHE. */
 801                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 802                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 803                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 804         }
 805
 806         soc21_grbm_select(adev, 0, 0, 0, 0);
 807         mutex_unlock(&adev->srbm_mutex);
 808
 809         return 0;
 810 }
 811
 812 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
 813                                       enum admgpu_mes_pipe pipe)
 814 {
 815         int r;
 816         u32 *eop;
 817
 818         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 819                               AMDGPU_GEM_DOMAIN_GTT,
 820                               &adev->mes.eop_gpu_obj[pipe],
 821                               &adev->mes.eop_gpu_addr[pipe],
 822                               (void **)&eop);
 823         if (r) {
 824                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 825                 return r;
 826         }
 827
 828         memset(eop, 0,
 829                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 830
 831         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 832         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 833
 834         return 0;
 835 }
 836
 837 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
 838 {
 839         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 840         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 841         uint32_t tmp;
 842
 843         memset(mqd, 0, sizeof(*mqd));
 844
 845         mqd->header = 0xC0310800;
 846         mqd->compute_pipelinestat_enable = 0x00000001;
 847         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 848         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 849         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 850         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 851         mqd->compute_misc_reserved = 0x00000007;
 852
 853         eop_base_addr = ring->eop_gpu_addr >> 8;
 854
 855         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 856         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 857         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 858                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 859
 860         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 861         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 862         mqd->cp_hqd_eop_control = tmp;
 863
 864         /* disable the queue if it's active */
 865         ring->wptr = 0;
 866         mqd->cp_hqd_pq_rptr = 0;
 867         mqd->cp_hqd_pq_wptr_lo = 0;
 868         mqd->cp_hqd_pq_wptr_hi = 0;
 869
 870         /* set the pointer to the MQD */
 871         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 872         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 873
 874         /* set MQD vmid to 0 */
 875         tmp = regCP_MQD_CONTROL_DEFAULT;
 876         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 877         mqd->cp_mqd_control = tmp;
 878
 879         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 880         hqd_gpu_addr = ring->gpu_addr >> 8;
 881         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 882         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 883
 884         /* set the wb address whether it's enabled or not */
 885         wb_gpu_addr = ring->rptr_gpu_addr;
 886         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 887         mqd->cp_hqd_pq_rptr_report_addr_hi =
 888                 upper_32_bits(wb_gpu_addr) & 0xffff;
 889
 890         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 891         wb_gpu_addr = ring->wptr_gpu_addr;
 892         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 893         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 894
 895         /* set up the HQD, this is similar to CP_RB0_CNTL */
 896         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 897         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 898                             (order_base_2(ring->ring_size / 4) - 1));
 899         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 900                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 901         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 902         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 903         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 904         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 905         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 906         mqd->cp_hqd_pq_control = tmp;
 907
 908         /* enable doorbell */
 909         tmp = 0;
 910         if (ring->use_doorbell) {
 911                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 912                                     DOORBELL_OFFSET, ring->doorbell_index);
 913                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 914                                     DOORBELL_EN, 1);
 915                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 916                                     DOORBELL_SOURCE, 0);
 917                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 918                                     DOORBELL_HIT, 0);
 919         } else
 920                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 921                                     DOORBELL_EN, 0);
 922         mqd->cp_hqd_pq_doorbell_control = tmp;
 923
 924         mqd->cp_hqd_vmid = 0;
 925         /* activate the queue */
 926         mqd->cp_hqd_active = 1;
 927
 928         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
 929         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
 930                             PRELOAD_SIZE, 0x55);
 931         mqd->cp_hqd_persistent_state = tmp;
 932
 933         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
 934         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
 935         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
 936
 937         amdgpu_device_flush_hdp(ring->adev, NULL);
 938         return 0;
 939 }
 940
 941 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
 942 {
 943         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 944         struct amdgpu_device *adev = ring->adev;
 945         uint32_t data = 0;
 946
 947         mutex_lock(&adev->srbm_mutex);
 948         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 949
 950         /* set CP_HQD_VMID.VMID = 0. */
 951         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
 952         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
 953         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
 954
 955         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
 956         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
 957         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
 958                              DOORBELL_EN, 0);
 959         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
 960
 961         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
 962         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
 963         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
 964
 965         /* set CP_MQD_CONTROL.VMID=0 */
 966         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
 967         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
 968         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
 969
 970         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
 971         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
 972         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
 973
 974         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
 975         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
 976                      mqd->cp_hqd_pq_rptr_report_addr_lo);
 977         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 978                      mqd->cp_hqd_pq_rptr_report_addr_hi);
 979
 980         /* set CP_HQD_PQ_CONTROL */
 981         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
 982
 983         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
 984         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
 985                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
 986         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 987                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
 988
 989         /* set CP_HQD_PQ_DOORBELL_CONTROL */
 990         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
 991                      mqd->cp_hqd_pq_doorbell_control);
 992
 993         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
 994         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
 995
 996         /* set CP_HQD_ACTIVE.ACTIVE=1 */
 997         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
 998
 999         soc21_grbm_select(adev, 0, 0, 0, 0);
1000         mutex_unlock(&adev->srbm_mutex);
1001 }
1002
1003 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
1004 {
1005         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1006         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1007         int r;
1008
1009         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1010                 return -EINVAL;
1011
1012         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1013         if (r) {
1014                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1015                 return r;
1016         }
1017
1018         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
1019
1020         return amdgpu_ring_test_helper(kiq_ring);
1021 }
1022
1023 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
1024                                 enum admgpu_mes_pipe pipe)
1025 {
1026         struct amdgpu_ring *ring;
1027         int r;
1028
1029         if (pipe == AMDGPU_MES_KIQ_PIPE)
1030                 ring = &adev->gfx.kiq[0].ring;
1031         else if (pipe == AMDGPU_MES_SCHED_PIPE)
1032                 ring = &adev->mes.ring;
1033         else
1034                 BUG();
1035
1036         if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
1037             (amdgpu_in_reset(adev) || adev->in_suspend)) {
1038                 *(ring->wptr_cpu_addr) = 0;
1039                 *(ring->rptr_cpu_addr) = 0;
1040                 amdgpu_ring_clear_ring(ring);
1041         }
1042
1043         r = mes_v11_0_mqd_init(ring);
1044         if (r)
1045                 return r;
1046
1047         if (pipe == AMDGPU_MES_SCHED_PIPE) {
1048                 r = mes_v11_0_kiq_enable_queue(adev);
1049                 if (r)
1050                         return r;
1051         } else {
1052                 mes_v11_0_queue_init_register(ring);
1053         }
1054
1055         /* get MES scheduler/KIQ versions */
1056         mutex_lock(&adev->srbm_mutex);
1057         soc21_grbm_select(adev, 3, pipe, 0, 0);
1058
1059         if (pipe == AMDGPU_MES_SCHED_PIPE)
1060                 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1061         else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1062                 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1063
1064         soc21_grbm_select(adev, 0, 0, 0, 0);
1065         mutex_unlock(&adev->srbm_mutex);
1066
1067         return 0;
1068 }
1069
1070 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
1071 {
1072         struct amdgpu_ring *ring;
1073
1074         ring = &adev->mes.ring;
1075
1076         ring->funcs = &mes_v11_0_ring_funcs;
1077
1078         ring->me = 3;
1079         ring->pipe = 0;
1080         ring->queue = 0;
1081
1082         ring->ring_obj = NULL;
1083         ring->use_doorbell = true;
1084         ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1085         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
1086         ring->no_scheduler = true;
1087         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1088
1089         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1090                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1091 }
1092
1093 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
1094 {
1095         struct amdgpu_ring *ring;
1096
1097         spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1098
1099         ring = &adev->gfx.kiq[0].ring;
1100
1101         ring->me = 3;
1102         ring->pipe = 1;
1103         ring->queue = 0;
1104
1105         ring->adev = NULL;
1106         ring->ring_obj = NULL;
1107         ring->use_doorbell = true;
1108         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1109         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1110         ring->no_scheduler = true;
1111         sprintf(ring->name, "mes_kiq_%d.%d.%d",
1112                 ring->me, ring->pipe, ring->queue);
1113
1114         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1115                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1116 }
1117
1118 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
1119                                  enum admgpu_mes_pipe pipe)
1120 {
1121         int r, mqd_size = sizeof(struct v11_compute_mqd);
1122         struct amdgpu_ring *ring;
1123
1124         if (pipe == AMDGPU_MES_KIQ_PIPE)
1125                 ring = &adev->gfx.kiq[0].ring;
1126         else if (pipe == AMDGPU_MES_SCHED_PIPE)
1127                 ring = &adev->mes.ring;
1128         else
1129                 BUG();
1130
1131         if (ring->mqd_obj)
1132                 return 0;
1133
1134         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1135                                     AMDGPU_GEM_DOMAIN_VRAM |
1136                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1137                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
1138         if (r) {
1139                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1140                 return r;
1141         }
1142
1143         memset(ring->mqd_ptr, 0, mqd_size);
1144
1145         /* prepare MQD backup */
1146         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1147         if (!adev->mes.mqd_backup[pipe]) {
1148                 dev_warn(adev->dev,
1149                          "no memory to create MQD backup for ring %s\n",
1150                          ring->name);
1151                 return -ENOMEM;
1152         }
1153
1154         return 0;
1155 }
1156
1157 static int mes_v11_0_sw_init(void *handle)
1158 {
1159         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1160         int pipe, r;
1161
1162         adev->mes.funcs = &mes_v11_0_funcs;
1163         adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1164         adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1165
1166         r = amdgpu_mes_init(adev);
1167         if (r)
1168                 return r;
1169
1170         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1171                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1172                         continue;
1173
1174                 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1175                 if (r)
1176                         return r;
1177
1178                 r = mes_v11_0_mqd_sw_init(adev, pipe);
1179                 if (r)
1180                         return r;
1181         }
1182
1183         if (adev->enable_mes_kiq) {
1184                 r = mes_v11_0_kiq_ring_init(adev);
1185                 if (r)
1186                         return r;
1187         }
1188
1189         r = mes_v11_0_ring_init(adev);
1190         if (r)
1191                 return r;
1192
1193         return 0;
1194 }
1195
1196 static int mes_v11_0_sw_fini(void *handle)
1197 {
1198         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1199         int pipe;
1200
1201         amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1202         amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1203
1204         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1205                 kfree(adev->mes.mqd_backup[pipe]);
1206
1207                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1208                                       &adev->mes.eop_gpu_addr[pipe],
1209                                       NULL);
1210                 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1211         }
1212
1213         amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1214                               &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1215                               &adev->gfx.kiq[0].ring.mqd_ptr);
1216
1217         amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1218                               &adev->mes.ring.mqd_gpu_addr,
1219                               &adev->mes.ring.mqd_ptr);
1220
1221         amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1222         amdgpu_ring_fini(&adev->mes.ring);
1223
1224         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1225                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1226                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1227         }
1228
1229         amdgpu_mes_fini(adev);
1230         return 0;
1231 }
1232
1233 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring)
1234 {
1235         uint32_t data;
1236         int i;
1237         struct amdgpu_device *adev = ring->adev;
1238
1239         mutex_lock(&adev->srbm_mutex);
1240         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1241
1242         /* disable the queue if it's active */
1243         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1244                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1245                 for (i = 0; i < adev->usec_timeout; i++) {
1246                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1247                                 break;
1248                         udelay(1);
1249                 }
1250         }
1251         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1252         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1253                                 DOORBELL_EN, 0);
1254         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1255                                 DOORBELL_HIT, 1);
1256         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1257
1258         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1259
1260         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1261         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1262         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1263
1264         soc21_grbm_select(adev, 0, 0, 0, 0);
1265         mutex_unlock(&adev->srbm_mutex);
1266 }
1267
1268 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1269 {
1270         uint32_t tmp;
1271         struct amdgpu_device *adev = ring->adev;
1272
1273         /* tell RLC which is KIQ queue */
1274         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1275         tmp &= 0xffffff00;
1276         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1277         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1278         tmp |= 0x80;
1279         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1280 }
1281
1282 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
1283 {
1284         uint32_t tmp;
1285
1286         /* tell RLC which is KIQ dequeue */
1287         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1288         tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
1289         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1290 }
1291
1292 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1293 {
1294         int r = 0;
1295
1296         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1297
1298                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1299                 if (r) {
1300                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1301                         return r;
1302                 }
1303
1304                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1305                 if (r) {
1306                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1307                         return r;
1308                 }
1309
1310         }
1311
1312         mes_v11_0_enable(adev, true);
1313
1314         mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
1315
1316         r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1317         if (r)
1318                 goto failure;
1319
1320         r = mes_v11_0_hw_init(adev);
1321         if (r)
1322                 goto failure;
1323
1324         return r;
1325
1326 failure:
1327         mes_v11_0_hw_fini(adev);
1328         return r;
1329 }
1330
1331 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1332 {
1333         if (adev->mes.ring.sched.ready) {
1334                 mes_v11_0_kiq_dequeue(&adev->mes.ring);
1335                 adev->mes.ring.sched.ready = false;
1336         }
1337
1338         if (amdgpu_sriov_vf(adev)) {
1339                 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring);
1340                 mes_v11_0_kiq_clear(adev);
1341         }
1342
1343         mes_v11_0_enable(adev, false);
1344
1345         return 0;
1346 }
1347
1348 static int mes_v11_0_hw_init(void *handle)
1349 {
1350         int r;
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352
1353         if (adev->mes.ring.sched.ready)
1354                 goto out;
1355
1356         if (!adev->enable_mes_kiq) {
1357                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1358                         r = mes_v11_0_load_microcode(adev,
1359                                              AMDGPU_MES_SCHED_PIPE, true);
1360                         if (r) {
1361                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1362                                 return r;
1363                         }
1364                 }
1365
1366                 mes_v11_0_enable(adev, true);
1367         }
1368
1369         r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1370         if (r)
1371                 goto failure;
1372
1373         r = mes_v11_0_set_hw_resources(&adev->mes);
1374         if (r)
1375                 goto failure;
1376
1377         if (amdgpu_sriov_is_mes_info_enable(adev)) {
1378                 r = mes_v11_0_set_hw_resources_1(&adev->mes);
1379                 if (r) {
1380                         DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
1381                         goto failure;
1382                 }
1383         }
1384
1385         r = mes_v11_0_query_sched_status(&adev->mes);
1386         if (r) {
1387                 DRM_ERROR("MES is busy\n");
1388                 goto failure;
1389         }
1390
1391 out:
1392         /*
1393          * Disable KIQ ring usage from the driver once MES is enabled.
1394          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1395          * with MES enabled.
1396          */
1397         adev->gfx.kiq[0].ring.sched.ready = false;
1398         adev->mes.ring.sched.ready = true;
1399
1400         return 0;
1401
1402 failure:
1403         mes_v11_0_hw_fini(adev);
1404         return r;
1405 }
1406
1407 static int mes_v11_0_hw_fini(void *handle)
1408 {
1409         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1410         if (amdgpu_sriov_is_mes_info_enable(adev)) {
1411                 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
1412                                         &adev->mes.resource_1_addr);
1413         }
1414         return 0;
1415 }
1416
1417 static int mes_v11_0_suspend(void *handle)
1418 {
1419         int r;
1420         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1421
1422         r = amdgpu_mes_suspend(adev);
1423         if (r)
1424                 return r;
1425
1426         return mes_v11_0_hw_fini(adev);
1427 }
1428
1429 static int mes_v11_0_resume(void *handle)
1430 {
1431         int r;
1432         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1433
1434         r = mes_v11_0_hw_init(adev);
1435         if (r)
1436                 return r;
1437
1438         return amdgpu_mes_resume(adev);
1439 }
1440
1441 static int mes_v11_0_early_init(void *handle)
1442 {
1443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1444         int pipe, r;
1445
1446         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1447                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1448                         continue;
1449                 r = amdgpu_mes_init_microcode(adev, pipe);
1450                 if (r)
1451                         return r;
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int mes_v11_0_late_init(void *handle)
1458 {
1459         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1460
1461         /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1462         if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
1463             (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3)))
1464                 amdgpu_mes_self_test(adev);
1465
1466         return 0;
1467 }
1468
1469 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1470         .name = "mes_v11_0",
1471         .early_init = mes_v11_0_early_init,
1472         .late_init = mes_v11_0_late_init,
1473         .sw_init = mes_v11_0_sw_init,
1474         .sw_fini = mes_v11_0_sw_fini,
1475         .hw_init = mes_v11_0_hw_init,
1476         .hw_fini = mes_v11_0_hw_fini,
1477         .suspend = mes_v11_0_suspend,
1478         .resume = mes_v11_0_resume,
1479         .dump_ip_state = NULL,
1480         .print_ip_state = NULL,
1481 };
1482
1483 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1484         .type = AMD_IP_BLOCK_TYPE_MES,
1485         .major = 11,
1486         .minor = 0,
1487         .rev = 0,
1488         .funcs = &mes_v11_0_ip_funcs,
1489 };