drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/display/drm_dp_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_modeset_helper_vtables.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include "amdgpu.h"
  34 #include "atom.h"
  35 #include "atombios_encoders.h"
  36 #include "atombios_dp.h"
  37 #include "amdgpu_connectors.h"
  38 #include "amdgpu_i2c.h"
  39 #include "amdgpu_display.h"
  40
  41 #include <linux/pm_runtime.h>
  42
  43 void amdgpu_connector_hotplug(struct drm_connector *connector)
  44 {
  45         struct drm_device *dev = connector->dev;
  46         struct amdgpu_device *adev = drm_to_adev(dev);
  47         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  48
  49         /* bail if the connector does not have hpd pin, e.g.,
  50          * VGA, TV, etc.
  51          */
  52         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  53                 return;
  54
  55         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  56
  57         /* if the connector is already off, don't turn it back on */
  58         if (connector->dpms != DRM_MODE_DPMS_ON)
  59                 return;
  60
  61         /* just deal with DP (not eDP) here. */
  62         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  63                 struct amdgpu_connector_atom_dig *dig_connector =
  64                         amdgpu_connector->con_priv;
  65
  66                 /* if existing sink type was not DP no need to retrain */
  67                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  68                         return;
  69
  70                 /* first get sink type as it may be reset after (un)plug */
  71                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  72                 /* don't do anything if sink is not display port, i.e.,
  73                  * passive dp->(dvi|hdmi) adaptor
  74                  */
  75                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  76                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  77                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  78                         /* Don't start link training before we have the DPCD */
  79                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  80                                 return;
  81
  82                         /* Turn the connector off and back on immediately, which
  83                          * will trigger link training
  84                          */
  85                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  86                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  87                 }
  88         }
  89 }
  90
  91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  92 {
  93         struct drm_crtc *crtc = encoder->crtc;
  94
  95         if (crtc && crtc->enabled) {
  96                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  97                                          crtc->x, crtc->y, crtc->primary->fb);
  98         }
  99 }
 100
 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
 102 {
 103         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 104         struct amdgpu_connector_atom_dig *dig_connector;
 105         int bpc = 8;
 106         unsigned int mode_clock, max_tmds_clock;
 107
 108         switch (connector->connector_type) {
 109         case DRM_MODE_CONNECTOR_DVII:
 110         case DRM_MODE_CONNECTOR_HDMIB:
 111                 if (amdgpu_connector->use_digital) {
 112                         if (connector->display_info.is_hdmi) {
 113                                 if (connector->display_info.bpc)
 114                                         bpc = connector->display_info.bpc;
 115                         }
 116                 }
 117                 break;
 118         case DRM_MODE_CONNECTOR_DVID:
 119         case DRM_MODE_CONNECTOR_HDMIA:
 120                 if (connector->display_info.is_hdmi) {
 121                         if (connector->display_info.bpc)
 122                                 bpc = connector->display_info.bpc;
 123                 }
 124                 break;
 125         case DRM_MODE_CONNECTOR_DisplayPort:
 126                 dig_connector = amdgpu_connector->con_priv;
 127                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 128                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 129                     connector->display_info.is_hdmi) {
 130                         if (connector->display_info.bpc)
 131                                 bpc = connector->display_info.bpc;
 132                 }
 133                 break;
 134         case DRM_MODE_CONNECTOR_eDP:
 135         case DRM_MODE_CONNECTOR_LVDS:
 136                 if (connector->display_info.bpc)
 137                         bpc = connector->display_info.bpc;
 138                 else {
 139                         const struct drm_connector_helper_funcs *connector_funcs =
 140                                 connector->helper_private;
 141                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 142                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 143                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 144
 145                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 146                                 bpc = 6;
 147                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 148                                 bpc = 8;
 149                 }
 150                 break;
 151         }
 152
 153         if (connector->display_info.is_hdmi) {
 154                 /*
 155                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 156                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 157                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 158                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 159                  */
 160                 if (bpc > 12) {
 161                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 162                                   connector->name, bpc);
 163                         bpc = 12;
 164                 }
 165
 166                 /* Any defined maximum tmds clock limit we must not exceed? */
 167                 if (connector->display_info.max_tmds_clock > 0) {
 168                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 169                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 170
 171                         /* Maximum allowable input clock in kHz */
 172                         max_tmds_clock = connector->display_info.max_tmds_clock;
 173
 174                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 175                                   connector->name, mode_clock, max_tmds_clock);
 176
 177                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 178                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 179                                 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
 180                                     (mode_clock * 5/4 <= max_tmds_clock))
 181                                         bpc = 10;
 182                                 else
 183                                         bpc = 8;
 184
 185                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 186                                           connector->name, bpc);
 187                         }
 188
 189                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 190                                 bpc = 8;
 191                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 192                                           connector->name, bpc);
 193                         }
 194                 } else if (bpc > 8) {
 195                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 196                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 197                                   connector->name);
 198                         bpc = 8;
 199                 }
 200         }
 201
 202         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 203                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 204                           connector->name);
 205                 bpc = 8;
 206         }
 207
 208         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 209                   connector->name, connector->display_info.bpc, bpc);
 210
 211         return bpc;
 212 }
 213
 214 static void
 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 216                                       enum drm_connector_status status)
 217 {
 218         struct drm_encoder *best_encoder;
 219         struct drm_encoder *encoder;
 220         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 221         bool connected;
 222
 223         best_encoder = connector_funcs->best_encoder(connector);
 224
 225         drm_connector_for_each_possible_encoder(connector, encoder) {
 226                 if ((encoder == best_encoder) && (status == connector_status_connected))
 227                         connected = true;
 228                 else
 229                         connected = false;
 230
 231                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 232         }
 233 }
 234
 235 static struct drm_encoder *
 236 amdgpu_connector_find_encoder(struct drm_connector *connector,
 237                                int encoder_type)
 238 {
 239         struct drm_encoder *encoder;
 240
 241         drm_connector_for_each_possible_encoder(connector, encoder) {
 242                 if (encoder->encoder_type == encoder_type)
 243                         return encoder;
 244         }
 245
 246         return NULL;
 247 }
 248
 249 static struct edid *
 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 251 {
 252         if (adev->mode_info.bios_hardcoded_edid) {
 253                 return kmemdup((unsigned char *)adev->mode_info.bios_hardcoded_edid,
 254                                adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 255         }
 256         return NULL;
 257 }
 258
 259 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 260 {
 261         struct drm_device *dev = connector->dev;
 262         struct amdgpu_device *adev = drm_to_adev(dev);
 263         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 264
 265         if (amdgpu_connector->edid)
 266                 return;
 267
 268         /* on hw with routers, select right port */
 269         if (amdgpu_connector->router.ddc_valid)
 270                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 271
 272         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 273              ENCODER_OBJECT_ID_NONE) &&
 274             amdgpu_connector->ddc_bus->has_aux) {
 275                 amdgpu_connector->edid = drm_get_edid(connector,
 276                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 277         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 278                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 279                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 280
 281                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 282                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 283                     amdgpu_connector->ddc_bus->has_aux)
 284                         amdgpu_connector->edid = drm_get_edid(connector,
 285                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 286                 else if (amdgpu_connector->ddc_bus)
 287                         amdgpu_connector->edid = drm_get_edid(connector,
 288                                                               &amdgpu_connector->ddc_bus->adapter);
 289         } else if (amdgpu_connector->ddc_bus) {
 290                 amdgpu_connector->edid = drm_get_edid(connector,
 291                                                       &amdgpu_connector->ddc_bus->adapter);
 292         }
 293
 294         if (!amdgpu_connector->edid) {
 295                 /* some laptops provide a hardcoded edid in rom for LCDs */
 296                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 297                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
 298                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 299                         drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 300                 }
 301         }
 302 }
 303
 304 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 305 {
 306         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 307
 308         kfree(amdgpu_connector->edid);
 309         amdgpu_connector->edid = NULL;
 310 }
 311
 312 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 313 {
 314         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 315         int ret;
 316
 317         if (amdgpu_connector->edid) {
 318                 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 319                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 320                 return ret;
 321         }
 322         drm_connector_update_edid_property(connector, NULL);
 323         return 0;
 324 }
 325
 326 static struct drm_encoder *
 327 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 328 {
 329         struct drm_encoder *encoder;
 330
 331         /* pick the first one */
 332         drm_connector_for_each_possible_encoder(connector, encoder)
 333                 return encoder;
 334
 335         return NULL;
 336 }
 337
 338 static void amdgpu_get_native_mode(struct drm_connector *connector)
 339 {
 340         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 341         struct amdgpu_encoder *amdgpu_encoder;
 342
 343         if (encoder == NULL)
 344                 return;
 345
 346         amdgpu_encoder = to_amdgpu_encoder(encoder);
 347
 348         if (!list_empty(&connector->probed_modes)) {
 349                 struct drm_display_mode *preferred_mode =
 350                         list_first_entry(&connector->probed_modes,
 351                                          struct drm_display_mode, head);
 352
 353                 amdgpu_encoder->native_mode = *preferred_mode;
 354         } else {
 355                 amdgpu_encoder->native_mode.clock = 0;
 356         }
 357 }
 358
 359 static struct drm_display_mode *
 360 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 361 {
 362         struct drm_device *dev = encoder->dev;
 363         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 364         struct drm_display_mode *mode = NULL;
 365         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 366
 367         if (native_mode->hdisplay != 0 &&
 368             native_mode->vdisplay != 0 &&
 369             native_mode->clock != 0) {
 370                 mode = drm_mode_duplicate(dev, native_mode);
 371                 if (!mode)
 372                         return NULL;
 373
 374                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 375                 drm_mode_set_name(mode);
 376
 377                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 378         } else if (native_mode->hdisplay != 0 &&
 379                    native_mode->vdisplay != 0) {
 380                 /* mac laptops without an edid */
 381                 /* Note that this is not necessarily the exact panel mode,
 382                  * but an approximation based on the cvt formula.  For these
 383                  * systems we should ideally read the mode info out of the
 384                  * registers or add a mode table, but this works and is much
 385                  * simpler.
 386                  */
 387                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 388                 if (!mode)
 389                         return NULL;
 390
 391                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 392                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 393         }
 394         return mode;
 395 }
 396
 397 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 398                                                struct drm_connector *connector)
 399 {
 400         struct drm_device *dev = encoder->dev;
 401         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 402         struct drm_display_mode *mode = NULL;
 403         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 404         int i;
 405         static const struct mode_size {
 406                 int w;
 407                 int h;
 408         } common_modes[17] = {
 409                 { 640,  480},
 410                 { 720,  480},
 411                 { 800,  600},
 412                 { 848,  480},
 413                 {1024,  768},
 414                 {1152,  768},
 415                 {1280,  720},
 416                 {1280,  800},
 417                 {1280,  854},
 418                 {1280,  960},
 419                 {1280, 1024},
 420                 {1440,  900},
 421                 {1400, 1050},
 422                 {1680, 1050},
 423                 {1600, 1200},
 424                 {1920, 1080},
 425                 {1920, 1200}
 426         };
 427
 428         for (i = 0; i < 17; i++) {
 429                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 430                         if (common_modes[i].w > 1024 ||
 431                             common_modes[i].h > 768)
 432                                 continue;
 433                 }
 434                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 435                         if (common_modes[i].w > native_mode->hdisplay ||
 436                             common_modes[i].h > native_mode->vdisplay ||
 437                             (common_modes[i].w == native_mode->hdisplay &&
 438                              common_modes[i].h == native_mode->vdisplay))
 439                                 continue;
 440                 }
 441                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 442                         continue;
 443
 444                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 445                 drm_mode_probed_add(connector, mode);
 446         }
 447 }
 448
 449 static int amdgpu_connector_set_property(struct drm_connector *connector,
 450                                           struct drm_property *property,
 451                                           uint64_t val)
 452 {
 453         struct drm_device *dev = connector->dev;
 454         struct amdgpu_device *adev = drm_to_adev(dev);
 455         struct drm_encoder *encoder;
 456         struct amdgpu_encoder *amdgpu_encoder;
 457
 458         if (property == adev->mode_info.coherent_mode_property) {
 459                 struct amdgpu_encoder_atom_dig *dig;
 460                 bool new_coherent_mode;
 461
 462                 /* need to find digital encoder on connector */
 463                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 464                 if (!encoder)
 465                         return 0;
 466
 467                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 468
 469                 if (!amdgpu_encoder->enc_priv)
 470                         return 0;
 471
 472                 dig = amdgpu_encoder->enc_priv;
 473                 new_coherent_mode = val ? true : false;
 474                 if (dig->coherent_mode != new_coherent_mode) {
 475                         dig->coherent_mode = new_coherent_mode;
 476                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 477                 }
 478         }
 479
 480         if (property == adev->mode_info.audio_property) {
 481                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 482                 /* need to find digital encoder on connector */
 483                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 484                 if (!encoder)
 485                         return 0;
 486
 487                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 488
 489                 if (amdgpu_connector->audio != val) {
 490                         amdgpu_connector->audio = val;
 491                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 492                 }
 493         }
 494
 495         if (property == adev->mode_info.dither_property) {
 496                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 497                 /* need to find digital encoder on connector */
 498                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 499                 if (!encoder)
 500                         return 0;
 501
 502                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 503
 504                 if (amdgpu_connector->dither != val) {
 505                         amdgpu_connector->dither = val;
 506                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 507                 }
 508         }
 509
 510         if (property == adev->mode_info.underscan_property) {
 511                 /* need to find digital encoder on connector */
 512                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 513                 if (!encoder)
 514                         return 0;
 515
 516                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 517
 518                 if (amdgpu_encoder->underscan_type != val) {
 519                         amdgpu_encoder->underscan_type = val;
 520                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 521                 }
 522         }
 523
 524         if (property == adev->mode_info.underscan_hborder_property) {
 525                 /* need to find digital encoder on connector */
 526                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 527                 if (!encoder)
 528                         return 0;
 529
 530                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 531
 532                 if (amdgpu_encoder->underscan_hborder != val) {
 533                         amdgpu_encoder->underscan_hborder = val;
 534                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 535                 }
 536         }
 537
 538         if (property == adev->mode_info.underscan_vborder_property) {
 539                 /* need to find digital encoder on connector */
 540                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 541                 if (!encoder)
 542                         return 0;
 543
 544                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 545
 546                 if (amdgpu_encoder->underscan_vborder != val) {
 547                         amdgpu_encoder->underscan_vborder = val;
 548                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 549                 }
 550         }
 551
 552         if (property == adev->mode_info.load_detect_property) {
 553                 struct amdgpu_connector *amdgpu_connector =
 554                         to_amdgpu_connector(connector);
 555
 556                 if (val == 0)
 557                         amdgpu_connector->dac_load_detect = false;
 558                 else
 559                         amdgpu_connector->dac_load_detect = true;
 560         }
 561
 562         if (property == dev->mode_config.scaling_mode_property) {
 563                 enum amdgpu_rmx_type rmx_type;
 564
 565                 if (connector->encoder) {
 566                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 567                 } else {
 568                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 569
 570                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 571                 }
 572
 573                 switch (val) {
 574                 default:
 575                 case DRM_MODE_SCALE_NONE:
 576                         rmx_type = RMX_OFF;
 577                         break;
 578                 case DRM_MODE_SCALE_CENTER:
 579                         rmx_type = RMX_CENTER;
 580                         break;
 581                 case DRM_MODE_SCALE_ASPECT:
 582                         rmx_type = RMX_ASPECT;
 583                         break;
 584                 case DRM_MODE_SCALE_FULLSCREEN:
 585                         rmx_type = RMX_FULL;
 586                         break;
 587                 }
 588
 589                 if (amdgpu_encoder->rmx_type == rmx_type)
 590                         return 0;
 591
 592                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 593                     (amdgpu_encoder->native_mode.clock == 0))
 594                         return 0;
 595
 596                 amdgpu_encoder->rmx_type = rmx_type;
 597
 598                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 599         }
 600
 601         return 0;
 602 }
 603
 604 static void
 605 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 606                                         struct drm_connector *connector)
 607 {
 608         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 609         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 610         struct drm_display_mode *t, *mode;
 611
 612         /* If the EDID preferred mode doesn't match the native mode, use it */
 613         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 614                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 615                         if (mode->hdisplay != native_mode->hdisplay ||
 616                             mode->vdisplay != native_mode->vdisplay)
 617                                 drm_mode_copy(native_mode, mode);
 618                 }
 619         }
 620
 621         /* Try to get native mode details from EDID if necessary */
 622         if (!native_mode->clock) {
 623                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 624                         if (mode->hdisplay == native_mode->hdisplay &&
 625                             mode->vdisplay == native_mode->vdisplay) {
 626                                 drm_mode_copy(native_mode, mode);
 627                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 628                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 629                                 break;
 630                         }
 631                 }
 632         }
 633
 634         if (!native_mode->clock) {
 635                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 636                 amdgpu_encoder->rmx_type = RMX_OFF;
 637         }
 638 }
 639
 640 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 641 {
 642         struct drm_encoder *encoder;
 643         int ret = 0;
 644         struct drm_display_mode *mode;
 645
 646         amdgpu_connector_get_edid(connector);
 647         ret = amdgpu_connector_ddc_get_modes(connector);
 648         if (ret > 0) {
 649                 encoder = amdgpu_connector_best_single_encoder(connector);
 650                 if (encoder) {
 651                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 652                         /* add scaled modes */
 653                         amdgpu_connector_add_common_modes(encoder, connector);
 654                 }
 655                 return ret;
 656         }
 657
 658         encoder = amdgpu_connector_best_single_encoder(connector);
 659         if (!encoder)
 660                 return 0;
 661
 662         /* we have no EDID modes */
 663         mode = amdgpu_connector_lcd_native_mode(encoder);
 664         if (mode) {
 665                 ret = 1;
 666                 drm_mode_probed_add(connector, mode);
 667                 /* add the width/height from vbios tables if available */
 668                 connector->display_info.width_mm = mode->width_mm;
 669                 connector->display_info.height_mm = mode->height_mm;
 670                 /* add scaled modes */
 671                 amdgpu_connector_add_common_modes(encoder, connector);
 672         }
 673
 674         return ret;
 675 }
 676
 677 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 678                                              struct drm_display_mode *mode)
 679 {
 680         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 681
 682         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 683                 return MODE_PANEL;
 684
 685         if (encoder) {
 686                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 687                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 688
 689                 /* AVIVO hardware supports downscaling modes larger than the panel
 690                  * to the panel size, but I'm not sure this is desirable.
 691                  */
 692                 if ((mode->hdisplay > native_mode->hdisplay) ||
 693                     (mode->vdisplay > native_mode->vdisplay))
 694                         return MODE_PANEL;
 695
 696                 /* if scaling is disabled, block non-native modes */
 697                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 698                         if ((mode->hdisplay != native_mode->hdisplay) ||
 699                             (mode->vdisplay != native_mode->vdisplay))
 700                                 return MODE_PANEL;
 701                 }
 702         }
 703
 704         return MODE_OK;
 705 }
 706
 707 static enum drm_connector_status
 708 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 709 {
 710         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 711         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 712         enum drm_connector_status ret = connector_status_disconnected;
 713         int r;
 714
 715         if (!drm_kms_helper_is_poll_worker()) {
 716                 r = pm_runtime_get_sync(connector->dev->dev);
 717                 if (r < 0) {
 718                         pm_runtime_put_autosuspend(connector->dev->dev);
 719                         return connector_status_disconnected;
 720                 }
 721         }
 722
 723         if (encoder) {
 724                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 725                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 726
 727                 /* check if panel is valid */
 728                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 729                         ret = connector_status_connected;
 730
 731         }
 732
 733         /* check for edid as well */
 734         amdgpu_connector_get_edid(connector);
 735         if (amdgpu_connector->edid)
 736                 ret = connector_status_connected;
 737         /* check acpi lid status ??? */
 738
 739         amdgpu_connector_update_scratch_regs(connector, ret);
 740
 741         if (!drm_kms_helper_is_poll_worker()) {
 742                 pm_runtime_mark_last_busy(connector->dev->dev);
 743                 pm_runtime_put_autosuspend(connector->dev->dev);
 744         }
 745
 746         return ret;
 747 }
 748
 749 static void amdgpu_connector_unregister(struct drm_connector *connector)
 750 {
 751         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 752
 753         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 754                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 755                 amdgpu_connector->ddc_bus->has_aux = false;
 756         }
 757 }
 758
 759 static void amdgpu_connector_destroy(struct drm_connector *connector)
 760 {
 761         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 762
 763         amdgpu_connector_free_edid(connector);
 764         kfree(amdgpu_connector->con_priv);
 765         drm_connector_unregister(connector);
 766         drm_connector_cleanup(connector);
 767         kfree(connector);
 768 }
 769
 770 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 771                                               struct drm_property *property,
 772                                               uint64_t value)
 773 {
 774         struct drm_device *dev = connector->dev;
 775         struct amdgpu_encoder *amdgpu_encoder;
 776         enum amdgpu_rmx_type rmx_type;
 777
 778         DRM_DEBUG_KMS("\n");
 779         if (property != dev->mode_config.scaling_mode_property)
 780                 return 0;
 781
 782         if (connector->encoder)
 783                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 784         else {
 785                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 786
 787                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 788         }
 789
 790         switch (value) {
 791         case DRM_MODE_SCALE_NONE:
 792                 rmx_type = RMX_OFF;
 793                 break;
 794         case DRM_MODE_SCALE_CENTER:
 795                 rmx_type = RMX_CENTER;
 796                 break;
 797         case DRM_MODE_SCALE_ASPECT:
 798                 rmx_type = RMX_ASPECT;
 799                 break;
 800         default:
 801         case DRM_MODE_SCALE_FULLSCREEN:
 802                 rmx_type = RMX_FULL;
 803                 break;
 804         }
 805
 806         if (amdgpu_encoder->rmx_type == rmx_type)
 807                 return 0;
 808
 809         amdgpu_encoder->rmx_type = rmx_type;
 810
 811         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 812         return 0;
 813 }
 814
 815
 816 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 817         .get_modes = amdgpu_connector_lvds_get_modes,
 818         .mode_valid = amdgpu_connector_lvds_mode_valid,
 819         .best_encoder = amdgpu_connector_best_single_encoder,
 820 };
 821
 822 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 823         .dpms = drm_helper_connector_dpms,
 824         .detect = amdgpu_connector_lvds_detect,
 825         .fill_modes = drm_helper_probe_single_connector_modes,
 826         .early_unregister = amdgpu_connector_unregister,
 827         .destroy = amdgpu_connector_destroy,
 828         .set_property = amdgpu_connector_set_lcd_property,
 829 };
 830
 831 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 832 {
 833         int ret;
 834
 835         amdgpu_connector_get_edid(connector);
 836         ret = amdgpu_connector_ddc_get_modes(connector);
 837         amdgpu_get_native_mode(connector);
 838
 839         return ret;
 840 }
 841
 842 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 843                                             struct drm_display_mode *mode)
 844 {
 845         struct drm_device *dev = connector->dev;
 846         struct amdgpu_device *adev = drm_to_adev(dev);
 847
 848         /* XXX check mode bandwidth */
 849
 850         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 851                 return MODE_CLOCK_HIGH;
 852
 853         return MODE_OK;
 854 }
 855
 856 static enum drm_connector_status
 857 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 858 {
 859         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 860         struct drm_encoder *encoder;
 861         const struct drm_encoder_helper_funcs *encoder_funcs;
 862         bool dret = false;
 863         enum drm_connector_status ret = connector_status_disconnected;
 864         int r;
 865
 866         if (!drm_kms_helper_is_poll_worker()) {
 867                 r = pm_runtime_get_sync(connector->dev->dev);
 868                 if (r < 0) {
 869                         pm_runtime_put_autosuspend(connector->dev->dev);
 870                         return connector_status_disconnected;
 871                 }
 872         }
 873
 874         encoder = amdgpu_connector_best_single_encoder(connector);
 875         if (!encoder)
 876                 ret = connector_status_disconnected;
 877
 878         if (amdgpu_connector->ddc_bus)
 879                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 880         if (dret) {
 881                 amdgpu_connector->detected_by_load = false;
 882                 amdgpu_connector_free_edid(connector);
 883                 amdgpu_connector_get_edid(connector);
 884
 885                 if (!amdgpu_connector->edid) {
 886                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 887                                         connector->name);
 888                         ret = connector_status_connected;
 889                 } else {
 890                         amdgpu_connector->use_digital =
 891                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 892
 893                         /* some oems have boards with separate digital and analog connectors
 894                          * with a shared ddc line (often vga + hdmi)
 895                          */
 896                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 897                                 amdgpu_connector_free_edid(connector);
 898                                 ret = connector_status_disconnected;
 899                         } else {
 900                                 ret = connector_status_connected;
 901                         }
 902                 }
 903         } else {
 904
 905                 /* if we aren't forcing don't do destructive polling */
 906                 if (!force) {
 907                         /* only return the previous status if we last
 908                          * detected a monitor via load.
 909                          */
 910                         if (amdgpu_connector->detected_by_load)
 911                                 ret = connector->status;
 912                         goto out;
 913                 }
 914
 915                 if (amdgpu_connector->dac_load_detect && encoder) {
 916                         encoder_funcs = encoder->helper_private;
 917                         ret = encoder_funcs->detect(encoder, connector);
 918                         if (ret != connector_status_disconnected)
 919                                 amdgpu_connector->detected_by_load = true;
 920                 }
 921         }
 922
 923         amdgpu_connector_update_scratch_regs(connector, ret);
 924
 925 out:
 926         if (!drm_kms_helper_is_poll_worker()) {
 927                 pm_runtime_mark_last_busy(connector->dev->dev);
 928                 pm_runtime_put_autosuspend(connector->dev->dev);
 929         }
 930
 931         return ret;
 932 }
 933
 934 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 935         .get_modes = amdgpu_connector_vga_get_modes,
 936         .mode_valid = amdgpu_connector_vga_mode_valid,
 937         .best_encoder = amdgpu_connector_best_single_encoder,
 938 };
 939
 940 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 941         .dpms = drm_helper_connector_dpms,
 942         .detect = amdgpu_connector_vga_detect,
 943         .fill_modes = drm_helper_probe_single_connector_modes,
 944         .early_unregister = amdgpu_connector_unregister,
 945         .destroy = amdgpu_connector_destroy,
 946         .set_property = amdgpu_connector_set_property,
 947 };
 948
 949 static bool
 950 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 951 {
 952         struct drm_device *dev = connector->dev;
 953         struct amdgpu_device *adev = drm_to_adev(dev);
 954         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 955         enum drm_connector_status status;
 956
 957         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 958                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 959                         status = connector_status_connected;
 960                 else
 961                         status = connector_status_disconnected;
 962                 if (connector->status == status)
 963                         return true;
 964         }
 965
 966         return false;
 967 }
 968
 969 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status,
 970                                         struct drm_connector *connector,
 971                                         struct amdgpu_connector *amdgpu_connector)
 972 {
 973         struct drm_connector *list_connector;
 974         struct drm_connector_list_iter iter;
 975         struct amdgpu_connector *list_amdgpu_connector;
 976         struct drm_device *dev = connector->dev;
 977         struct amdgpu_device *adev = drm_to_adev(dev);
 978
 979         if (amdgpu_connector->shared_ddc && *status == connector_status_connected) {
 980                 drm_connector_list_iter_begin(dev, &iter);
 981                 drm_for_each_connector_iter(list_connector,
 982                                             &iter) {
 983                         if (connector == list_connector)
 984                                 continue;
 985                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
 986                         if (list_amdgpu_connector->shared_ddc &&
 987                             list_amdgpu_connector->ddc_bus->rec.i2c_id ==
 988                              amdgpu_connector->ddc_bus->rec.i2c_id) {
 989                                 /* cases where both connectors are digital */
 990                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
 991                                         /* hpd is our only option in this case */
 992                                         if (!amdgpu_display_hpd_sense(adev,
 993                                                                       amdgpu_connector->hpd.hpd)) {
 994                                                 amdgpu_connector_free_edid(connector);
 995                                                 *status = connector_status_disconnected;
 996                                         }
 997                                 }
 998                         }
 999                 }
1000                 drm_connector_list_iter_end(&iter);
1001         }
1002 }
1003
1004 /*
1005  * DVI is complicated
1006  * Do a DDC probe, if DDC probe passes, get the full EDID so
1007  * we can do analog/digital monitor detection at this point.
1008  * If the monitor is an analog monitor or we got no DDC,
1009  * we need to find the DAC encoder object for this connector.
1010  * If we got no DDC, we do load detection on the DAC encoder object.
1011  * If we got analog DDC or load detection passes on the DAC encoder
1012  * we have to check if this analog encoder is shared with anyone else (TV)
1013  * if its shared we have to set the other connector to disconnected.
1014  */
1015 static enum drm_connector_status
1016 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
1017 {
1018         struct drm_device *dev = connector->dev;
1019         struct amdgpu_device *adev = drm_to_adev(dev);
1020         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1021         const struct drm_encoder_helper_funcs *encoder_funcs;
1022         int r;
1023         enum drm_connector_status ret = connector_status_disconnected;
1024         bool dret = false, broken_edid = false;
1025
1026         if (!drm_kms_helper_is_poll_worker()) {
1027                 r = pm_runtime_get_sync(connector->dev->dev);
1028                 if (r < 0) {
1029                         pm_runtime_put_autosuspend(connector->dev->dev);
1030                         return connector_status_disconnected;
1031                 }
1032         }
1033
1034         if (amdgpu_connector->detected_hpd_without_ddc) {
1035                 force = true;
1036                 amdgpu_connector->detected_hpd_without_ddc = false;
1037         }
1038
1039         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1040                 ret = connector->status;
1041                 goto exit;
1042         }
1043
1044         if (amdgpu_connector->ddc_bus) {
1045                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1046
1047                 /* Sometimes the pins required for the DDC probe on DVI
1048                  * connectors don't make contact at the same time that the ones
1049                  * for HPD do. If the DDC probe fails even though we had an HPD
1050                  * signal, try again later
1051                  */
1052                 if (!dret && !force &&
1053                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1054                         DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1055                         amdgpu_connector->detected_hpd_without_ddc = true;
1056                         schedule_delayed_work(&adev->hotplug_work,
1057                                               msecs_to_jiffies(1000));
1058                         goto exit;
1059                 }
1060         }
1061         if (dret) {
1062                 amdgpu_connector->detected_by_load = false;
1063                 amdgpu_connector_free_edid(connector);
1064                 amdgpu_connector_get_edid(connector);
1065
1066                 if (!amdgpu_connector->edid) {
1067                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1068                                         connector->name);
1069                         ret = connector_status_connected;
1070                         broken_edid = true; /* defer use_digital to later */
1071                 } else {
1072                         amdgpu_connector->use_digital =
1073                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1074
1075                         /* some oems have boards with separate digital and analog connectors
1076                          * with a shared ddc line (often vga + hdmi)
1077                          */
1078                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1079                                 amdgpu_connector_free_edid(connector);
1080                                 ret = connector_status_disconnected;
1081                         } else {
1082                                 ret = connector_status_connected;
1083                         }
1084
1085                         /* This gets complicated.  We have boards with VGA + HDMI with a
1086                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1087                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1088                          * you don't really know what's connected to which port as both are digital.
1089                          */
1090                         amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector);
1091                 }
1092         }
1093
1094         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1095                 goto out;
1096
1097         /* DVI-D and HDMI-A are digital only */
1098         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1099             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1100                 goto out;
1101
1102         /* if we aren't forcing don't do destructive polling */
1103         if (!force) {
1104                 /* only return the previous status if we last
1105                  * detected a monitor via load.
1106                  */
1107                 if (amdgpu_connector->detected_by_load)
1108                         ret = connector->status;
1109                 goto out;
1110         }
1111
1112         /* find analog encoder */
1113         if (amdgpu_connector->dac_load_detect) {
1114                 struct drm_encoder *encoder;
1115
1116                 drm_connector_for_each_possible_encoder(connector, encoder) {
1117                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1118                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1119                                 continue;
1120
1121                         encoder_funcs = encoder->helper_private;
1122                         if (encoder_funcs->detect) {
1123                                 if (!broken_edid) {
1124                                         if (ret != connector_status_connected) {
1125                                                 /* deal with analog monitors without DDC */
1126                                                 ret = encoder_funcs->detect(encoder, connector);
1127                                                 if (ret == connector_status_connected) {
1128                                                         amdgpu_connector->use_digital = false;
1129                                                 }
1130                                                 if (ret != connector_status_disconnected)
1131                                                         amdgpu_connector->detected_by_load = true;
1132                                         }
1133                                 } else {
1134                                         enum drm_connector_status lret;
1135                                         /* assume digital unless load detected otherwise */
1136                                         amdgpu_connector->use_digital = true;
1137                                         lret = encoder_funcs->detect(encoder, connector);
1138                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",
1139                                                       encoder->encoder_type, lret);
1140                                         if (lret == connector_status_connected)
1141                                                 amdgpu_connector->use_digital = false;
1142                                 }
1143                                 break;
1144                         }
1145                 }
1146         }
1147
1148 out:
1149         /* updated in get modes as well since we need to know if it's analog or digital */
1150         amdgpu_connector_update_scratch_regs(connector, ret);
1151
1152 exit:
1153         if (!drm_kms_helper_is_poll_worker()) {
1154                 pm_runtime_mark_last_busy(connector->dev->dev);
1155                 pm_runtime_put_autosuspend(connector->dev->dev);
1156         }
1157
1158         return ret;
1159 }
1160
1161 /* okay need to be smart in here about which encoder to pick */
1162 static struct drm_encoder *
1163 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1164 {
1165         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1166         struct drm_encoder *encoder;
1167
1168         drm_connector_for_each_possible_encoder(connector, encoder) {
1169                 if (amdgpu_connector->use_digital == true) {
1170                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1171                                 return encoder;
1172                 } else {
1173                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1174                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1175                                 return encoder;
1176                 }
1177         }
1178
1179         /* see if we have a default encoder  TODO */
1180
1181         /* then check use digitial */
1182         /* pick the first one */
1183         drm_connector_for_each_possible_encoder(connector, encoder)
1184                 return encoder;
1185
1186         return NULL;
1187 }
1188
1189 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1190 {
1191         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1192
1193         if (connector->force == DRM_FORCE_ON)
1194                 amdgpu_connector->use_digital = false;
1195         if (connector->force == DRM_FORCE_ON_DIGITAL)
1196                 amdgpu_connector->use_digital = true;
1197 }
1198
1199 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1200                                             struct drm_display_mode *mode)
1201 {
1202         struct drm_device *dev = connector->dev;
1203         struct amdgpu_device *adev = drm_to_adev(dev);
1204         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1205
1206         /* XXX check mode bandwidth */
1207
1208         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1209                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1210                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1211                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1212                         return MODE_OK;
1213                 } else if (connector->display_info.is_hdmi) {
1214                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1215                         if (mode->clock > 340000)
1216                                 return MODE_CLOCK_HIGH;
1217                         else
1218                                 return MODE_OK;
1219                 } else {
1220                         return MODE_CLOCK_HIGH;
1221                 }
1222         }
1223
1224         /* check against the max pixel clock */
1225         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1226                 return MODE_CLOCK_HIGH;
1227
1228         return MODE_OK;
1229 }
1230
1231 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1232         .get_modes = amdgpu_connector_vga_get_modes,
1233         .mode_valid = amdgpu_connector_dvi_mode_valid,
1234         .best_encoder = amdgpu_connector_dvi_encoder,
1235 };
1236
1237 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1238         .dpms = drm_helper_connector_dpms,
1239         .detect = amdgpu_connector_dvi_detect,
1240         .fill_modes = drm_helper_probe_single_connector_modes,
1241         .set_property = amdgpu_connector_set_property,
1242         .early_unregister = amdgpu_connector_unregister,
1243         .destroy = amdgpu_connector_destroy,
1244         .force = amdgpu_connector_dvi_force,
1245 };
1246
1247 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1248 {
1249         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1250         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1251         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1252         int ret;
1253
1254         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1255             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1256                 struct drm_display_mode *mode;
1257
1258                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1259                         if (!amdgpu_dig_connector->edp_on)
1260                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1261                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1262                         amdgpu_connector_get_edid(connector);
1263                         ret = amdgpu_connector_ddc_get_modes(connector);
1264                         if (!amdgpu_dig_connector->edp_on)
1265                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1266                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1267                 } else {
1268                         /* need to setup ddc on the bridge */
1269                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1270                             ENCODER_OBJECT_ID_NONE) {
1271                                 if (encoder)
1272                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1273                         }
1274                         amdgpu_connector_get_edid(connector);
1275                         ret = amdgpu_connector_ddc_get_modes(connector);
1276                 }
1277
1278                 if (ret > 0) {
1279                         if (encoder) {
1280                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1281                                 /* add scaled modes */
1282                                 amdgpu_connector_add_common_modes(encoder, connector);
1283                         }
1284                         return ret;
1285                 }
1286
1287                 if (!encoder)
1288                         return 0;
1289
1290                 /* we have no EDID modes */
1291                 mode = amdgpu_connector_lcd_native_mode(encoder);
1292                 if (mode) {
1293                         ret = 1;
1294                         drm_mode_probed_add(connector, mode);
1295                         /* add the width/height from vbios tables if available */
1296                         connector->display_info.width_mm = mode->width_mm;
1297                         connector->display_info.height_mm = mode->height_mm;
1298                         /* add scaled modes */
1299                         amdgpu_connector_add_common_modes(encoder, connector);
1300                 }
1301         } else {
1302                 /* need to setup ddc on the bridge */
1303                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1304                         ENCODER_OBJECT_ID_NONE) {
1305                         if (encoder)
1306                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1307                 }
1308                 amdgpu_connector_get_edid(connector);
1309                 ret = amdgpu_connector_ddc_get_modes(connector);
1310
1311                 amdgpu_get_native_mode(connector);
1312         }
1313
1314         return ret;
1315 }
1316
1317 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1318 {
1319         struct drm_encoder *encoder;
1320         struct amdgpu_encoder *amdgpu_encoder;
1321
1322         drm_connector_for_each_possible_encoder(connector, encoder) {
1323                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1324
1325                 switch (amdgpu_encoder->encoder_id) {
1326                 case ENCODER_OBJECT_ID_TRAVIS:
1327                 case ENCODER_OBJECT_ID_NUTMEG:
1328                         return amdgpu_encoder->encoder_id;
1329                 default:
1330                         break;
1331                 }
1332         }
1333
1334         return ENCODER_OBJECT_ID_NONE;
1335 }
1336
1337 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1338 {
1339         struct drm_encoder *encoder;
1340         struct amdgpu_encoder *amdgpu_encoder;
1341         bool found = false;
1342
1343         drm_connector_for_each_possible_encoder(connector, encoder) {
1344                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1345                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1346                         found = true;
1347         }
1348
1349         return found;
1350 }
1351
1352 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1353 {
1354         struct drm_device *dev = connector->dev;
1355         struct amdgpu_device *adev = drm_to_adev(dev);
1356
1357         if ((adev->clock.default_dispclk >= 53900) &&
1358             amdgpu_connector_encoder_is_hbr2(connector)) {
1359                 return true;
1360         }
1361
1362         return false;
1363 }
1364
1365 static enum drm_connector_status
1366 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1367 {
1368         struct drm_device *dev = connector->dev;
1369         struct amdgpu_device *adev = drm_to_adev(dev);
1370         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1371         enum drm_connector_status ret = connector_status_disconnected;
1372         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1373         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1374         int r;
1375
1376         if (!drm_kms_helper_is_poll_worker()) {
1377                 r = pm_runtime_get_sync(connector->dev->dev);
1378                 if (r < 0) {
1379                         pm_runtime_put_autosuspend(connector->dev->dev);
1380                         return connector_status_disconnected;
1381                 }
1382         }
1383
1384         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1385                 ret = connector->status;
1386                 goto out;
1387         }
1388
1389         amdgpu_connector_free_edid(connector);
1390
1391         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1392             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1393                 if (encoder) {
1394                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1395                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1396
1397                         /* check if panel is valid */
1398                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1399                                 ret = connector_status_connected;
1400                 }
1401                 /* eDP is always DP */
1402                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1403                 if (!amdgpu_dig_connector->edp_on)
1404                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1405                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1406                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1407                         ret = connector_status_connected;
1408                 if (!amdgpu_dig_connector->edp_on)
1409                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1410                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1411         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1412                    ENCODER_OBJECT_ID_NONE) {
1413                 /* DP bridges are always DP */
1414                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1415                 /* get the DPCD from the bridge */
1416                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1417
1418                 if (encoder) {
1419                         /* setup ddc on the bridge */
1420                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1421                         /* bridge chips are always aux */
1422                         /* try DDC */
1423                         if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1424                                 ret = connector_status_connected;
1425                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1426                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1427
1428                                 ret = encoder_funcs->detect(encoder, connector);
1429                         }
1430                 }
1431         } else {
1432                 amdgpu_dig_connector->dp_sink_type =
1433                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1434                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1435                         ret = connector_status_connected;
1436                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1437                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1438                 } else {
1439                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1440                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1441                                         ret = connector_status_connected;
1442                         } else {
1443                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1444                                 if (amdgpu_display_ddc_probe(amdgpu_connector,
1445                                                              false))
1446                                         ret = connector_status_connected;
1447                         }
1448                 }
1449         }
1450
1451         amdgpu_connector_update_scratch_regs(connector, ret);
1452 out:
1453         if (!drm_kms_helper_is_poll_worker()) {
1454                 pm_runtime_mark_last_busy(connector->dev->dev);
1455                 pm_runtime_put_autosuspend(connector->dev->dev);
1456         }
1457
1458         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1459             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1460                 drm_dp_set_subconnector_property(&amdgpu_connector->base,
1461                                                  ret,
1462                                                  amdgpu_dig_connector->dpcd,
1463                                                  amdgpu_dig_connector->downstream_ports);
1464         return ret;
1465 }
1466
1467 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1468                                            struct drm_display_mode *mode)
1469 {
1470         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1471         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1472
1473         /* XXX check mode bandwidth */
1474
1475         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1476             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1477                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1478
1479                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1480                         return MODE_PANEL;
1481
1482                 if (encoder) {
1483                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1484                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1485
1486                         /* AVIVO hardware supports downscaling modes larger than the panel
1487                          * to the panel size, but I'm not sure this is desirable.
1488                          */
1489                         if ((mode->hdisplay > native_mode->hdisplay) ||
1490                             (mode->vdisplay > native_mode->vdisplay))
1491                                 return MODE_PANEL;
1492
1493                         /* if scaling is disabled, block non-native modes */
1494                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1495                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1496                                     (mode->vdisplay != native_mode->vdisplay))
1497                                         return MODE_PANEL;
1498                         }
1499                 }
1500                 return MODE_OK;
1501         } else {
1502                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1503                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1504                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1505                 } else {
1506                         if (connector->display_info.is_hdmi) {
1507                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1508                                 if (mode->clock > 340000)
1509                                         return MODE_CLOCK_HIGH;
1510                         } else {
1511                                 if (mode->clock > 165000)
1512                                         return MODE_CLOCK_HIGH;
1513                         }
1514                 }
1515         }
1516
1517         return MODE_OK;
1518 }
1519
1520 static int
1521 amdgpu_connector_late_register(struct drm_connector *connector)
1522 {
1523         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1524         int r = 0;
1525
1526         if (amdgpu_connector->ddc_bus->has_aux) {
1527                 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1528                 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1529         }
1530
1531         return r;
1532 }
1533
1534 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1535         .get_modes = amdgpu_connector_dp_get_modes,
1536         .mode_valid = amdgpu_connector_dp_mode_valid,
1537         .best_encoder = amdgpu_connector_dvi_encoder,
1538 };
1539
1540 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1541         .dpms = drm_helper_connector_dpms,
1542         .detect = amdgpu_connector_dp_detect,
1543         .fill_modes = drm_helper_probe_single_connector_modes,
1544         .set_property = amdgpu_connector_set_property,
1545         .early_unregister = amdgpu_connector_unregister,
1546         .destroy = amdgpu_connector_destroy,
1547         .force = amdgpu_connector_dvi_force,
1548         .late_register = amdgpu_connector_late_register,
1549 };
1550
1551 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1552         .dpms = drm_helper_connector_dpms,
1553         .detect = amdgpu_connector_dp_detect,
1554         .fill_modes = drm_helper_probe_single_connector_modes,
1555         .set_property = amdgpu_connector_set_lcd_property,
1556         .early_unregister = amdgpu_connector_unregister,
1557         .destroy = amdgpu_connector_destroy,
1558         .force = amdgpu_connector_dvi_force,
1559         .late_register = amdgpu_connector_late_register,
1560 };
1561
1562 void
1563 amdgpu_connector_add(struct amdgpu_device *adev,
1564                       uint32_t connector_id,
1565                       uint32_t supported_device,
1566                       int connector_type,
1567                       struct amdgpu_i2c_bus_rec *i2c_bus,
1568                       uint16_t connector_object_id,
1569                       struct amdgpu_hpd *hpd,
1570                       struct amdgpu_router *router)
1571 {
1572         struct drm_device *dev = adev_to_drm(adev);
1573         struct drm_connector *connector;
1574         struct drm_connector_list_iter iter;
1575         struct amdgpu_connector *amdgpu_connector;
1576         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1577         struct drm_encoder *encoder;
1578         struct amdgpu_encoder *amdgpu_encoder;
1579         struct i2c_adapter *ddc = NULL;
1580         uint32_t subpixel_order = SubPixelNone;
1581         bool shared_ddc = false;
1582         bool is_dp_bridge = false;
1583         bool has_aux = false;
1584
1585         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1586                 return;
1587
1588         /* see if we already added it */
1589         drm_connector_list_iter_begin(dev, &iter);
1590         drm_for_each_connector_iter(connector, &iter) {
1591                 amdgpu_connector = to_amdgpu_connector(connector);
1592                 if (amdgpu_connector->connector_id == connector_id) {
1593                         amdgpu_connector->devices |= supported_device;
1594                         drm_connector_list_iter_end(&iter);
1595                         return;
1596                 }
1597                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1598                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1599                                 amdgpu_connector->shared_ddc = true;
1600                                 shared_ddc = true;
1601                         }
1602                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1603                             (amdgpu_connector->router.router_id == router->router_id)) {
1604                                 amdgpu_connector->shared_ddc = false;
1605                                 shared_ddc = false;
1606                         }
1607                 }
1608         }
1609         drm_connector_list_iter_end(&iter);
1610
1611         /* check if it's a dp bridge */
1612         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1613                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1614                 if (amdgpu_encoder->devices & supported_device) {
1615                         switch (amdgpu_encoder->encoder_id) {
1616                         case ENCODER_OBJECT_ID_TRAVIS:
1617                         case ENCODER_OBJECT_ID_NUTMEG:
1618                                 is_dp_bridge = true;
1619                                 break;
1620                         default:
1621                                 break;
1622                         }
1623                 }
1624         }
1625
1626         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1627         if (!amdgpu_connector)
1628                 return;
1629
1630         connector = &amdgpu_connector->base;
1631
1632         amdgpu_connector->connector_id = connector_id;
1633         amdgpu_connector->devices = supported_device;
1634         amdgpu_connector->shared_ddc = shared_ddc;
1635         amdgpu_connector->connector_object_id = connector_object_id;
1636         amdgpu_connector->hpd = *hpd;
1637
1638         amdgpu_connector->router = *router;
1639         if (router->ddc_valid || router->cd_valid) {
1640                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1641                 if (!amdgpu_connector->router_bus)
1642                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1643         }
1644
1645         if (is_dp_bridge) {
1646                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1647                 if (!amdgpu_dig_connector)
1648                         goto failed;
1649                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1650                 if (i2c_bus->valid) {
1651                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1652                         if (amdgpu_connector->ddc_bus) {
1653                                 has_aux = true;
1654                                 ddc = &amdgpu_connector->ddc_bus->adapter;
1655                         } else {
1656                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1657                         }
1658                 }
1659                 switch (connector_type) {
1660                 case DRM_MODE_CONNECTOR_VGA:
1661                 case DRM_MODE_CONNECTOR_DVIA:
1662                 default:
1663                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1664                                                     &amdgpu_connector_dp_funcs,
1665                                                     connector_type,
1666                                                     ddc);
1667                         drm_connector_helper_add(&amdgpu_connector->base,
1668                                                  &amdgpu_connector_dp_helper_funcs);
1669                         connector->interlace_allowed = true;
1670                         connector->doublescan_allowed = true;
1671                         amdgpu_connector->dac_load_detect = true;
1672                         drm_object_attach_property(&amdgpu_connector->base.base,
1673                                                       adev->mode_info.load_detect_property,
1674                                                       1);
1675                         drm_object_attach_property(&amdgpu_connector->base.base,
1676                                                    dev->mode_config.scaling_mode_property,
1677                                                    DRM_MODE_SCALE_NONE);
1678                         break;
1679                 case DRM_MODE_CONNECTOR_DVII:
1680                 case DRM_MODE_CONNECTOR_DVID:
1681                 case DRM_MODE_CONNECTOR_HDMIA:
1682                 case DRM_MODE_CONNECTOR_HDMIB:
1683                 case DRM_MODE_CONNECTOR_DisplayPort:
1684                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1685                                                     &amdgpu_connector_dp_funcs,
1686                                                     connector_type,
1687                                                     ddc);
1688                         drm_connector_helper_add(&amdgpu_connector->base,
1689                                                  &amdgpu_connector_dp_helper_funcs);
1690                         drm_object_attach_property(&amdgpu_connector->base.base,
1691                                                       adev->mode_info.underscan_property,
1692                                                       UNDERSCAN_OFF);
1693                         drm_object_attach_property(&amdgpu_connector->base.base,
1694                                                       adev->mode_info.underscan_hborder_property,
1695                                                       0);
1696                         drm_object_attach_property(&amdgpu_connector->base.base,
1697                                                       adev->mode_info.underscan_vborder_property,
1698                                                       0);
1699
1700                         drm_object_attach_property(&amdgpu_connector->base.base,
1701                                                    dev->mode_config.scaling_mode_property,
1702                                                    DRM_MODE_SCALE_NONE);
1703
1704                         drm_object_attach_property(&amdgpu_connector->base.base,
1705                                                    adev->mode_info.dither_property,
1706                                                    AMDGPU_FMT_DITHER_DISABLE);
1707
1708                         if (amdgpu_audio != 0) {
1709                                 drm_object_attach_property(&amdgpu_connector->base.base,
1710                                                            adev->mode_info.audio_property,
1711                                                            AMDGPU_AUDIO_AUTO);
1712                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1713                         }
1714
1715                         subpixel_order = SubPixelHorizontalRGB;
1716                         connector->interlace_allowed = true;
1717                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1718                                 connector->doublescan_allowed = true;
1719                         else
1720                                 connector->doublescan_allowed = false;
1721                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1722                                 amdgpu_connector->dac_load_detect = true;
1723                                 drm_object_attach_property(&amdgpu_connector->base.base,
1724                                                               adev->mode_info.load_detect_property,
1725                                                               1);
1726                         }
1727                         break;
1728                 case DRM_MODE_CONNECTOR_LVDS:
1729                 case DRM_MODE_CONNECTOR_eDP:
1730                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1731                                                     &amdgpu_connector_edp_funcs,
1732                                                     connector_type,
1733                                                     ddc);
1734                         drm_connector_helper_add(&amdgpu_connector->base,
1735                                                  &amdgpu_connector_dp_helper_funcs);
1736                         drm_object_attach_property(&amdgpu_connector->base.base,
1737                                                       dev->mode_config.scaling_mode_property,
1738                                                       DRM_MODE_SCALE_FULLSCREEN);
1739                         subpixel_order = SubPixelHorizontalRGB;
1740                         connector->interlace_allowed = false;
1741                         connector->doublescan_allowed = false;
1742                         break;
1743                 }
1744         } else {
1745                 switch (connector_type) {
1746                 case DRM_MODE_CONNECTOR_VGA:
1747                         if (i2c_bus->valid) {
1748                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1749                                 if (!amdgpu_connector->ddc_bus)
1750                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1751                                 else
1752                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1753                         }
1754                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1755                                                     &amdgpu_connector_vga_funcs,
1756                                                     connector_type,
1757                                                     ddc);
1758                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1759                         amdgpu_connector->dac_load_detect = true;
1760                         drm_object_attach_property(&amdgpu_connector->base.base,
1761                                                       adev->mode_info.load_detect_property,
1762                                                       1);
1763                         drm_object_attach_property(&amdgpu_connector->base.base,
1764                                                    dev->mode_config.scaling_mode_property,
1765                                                    DRM_MODE_SCALE_NONE);
1766                         /* no HPD on analog connectors */
1767                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1768                         connector->interlace_allowed = true;
1769                         connector->doublescan_allowed = true;
1770                         break;
1771                 case DRM_MODE_CONNECTOR_DVIA:
1772                         if (i2c_bus->valid) {
1773                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1774                                 if (!amdgpu_connector->ddc_bus)
1775                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1776                                 else
1777                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1778                         }
1779                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1780                                                     &amdgpu_connector_vga_funcs,
1781                                                     connector_type,
1782                                                     ddc);
1783                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1784                         amdgpu_connector->dac_load_detect = true;
1785                         drm_object_attach_property(&amdgpu_connector->base.base,
1786                                                       adev->mode_info.load_detect_property,
1787                                                       1);
1788                         drm_object_attach_property(&amdgpu_connector->base.base,
1789                                                    dev->mode_config.scaling_mode_property,
1790                                                    DRM_MODE_SCALE_NONE);
1791                         /* no HPD on analog connectors */
1792                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1793                         connector->interlace_allowed = true;
1794                         connector->doublescan_allowed = true;
1795                         break;
1796                 case DRM_MODE_CONNECTOR_DVII:
1797                 case DRM_MODE_CONNECTOR_DVID:
1798                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1799                         if (!amdgpu_dig_connector)
1800                                 goto failed;
1801                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1802                         if (i2c_bus->valid) {
1803                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1804                                 if (!amdgpu_connector->ddc_bus)
1805                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1806                                 else
1807                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1808                         }
1809                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1810                                                     &amdgpu_connector_dvi_funcs,
1811                                                     connector_type,
1812                                                     ddc);
1813                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1814                         subpixel_order = SubPixelHorizontalRGB;
1815                         drm_object_attach_property(&amdgpu_connector->base.base,
1816                                                       adev->mode_info.coherent_mode_property,
1817                                                       1);
1818                         drm_object_attach_property(&amdgpu_connector->base.base,
1819                                                    adev->mode_info.underscan_property,
1820                                                    UNDERSCAN_OFF);
1821                         drm_object_attach_property(&amdgpu_connector->base.base,
1822                                                    adev->mode_info.underscan_hborder_property,
1823                                                    0);
1824                         drm_object_attach_property(&amdgpu_connector->base.base,
1825                                                    adev->mode_info.underscan_vborder_property,
1826                                                    0);
1827                         drm_object_attach_property(&amdgpu_connector->base.base,
1828                                                    dev->mode_config.scaling_mode_property,
1829                                                    DRM_MODE_SCALE_NONE);
1830
1831                         if (amdgpu_audio != 0) {
1832                                 drm_object_attach_property(&amdgpu_connector->base.base,
1833                                                            adev->mode_info.audio_property,
1834                                                            AMDGPU_AUDIO_AUTO);
1835                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1836                         }
1837                         drm_object_attach_property(&amdgpu_connector->base.base,
1838                                                    adev->mode_info.dither_property,
1839                                                    AMDGPU_FMT_DITHER_DISABLE);
1840                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1841                                 amdgpu_connector->dac_load_detect = true;
1842                                 drm_object_attach_property(&amdgpu_connector->base.base,
1843                                                            adev->mode_info.load_detect_property,
1844                                                            1);
1845                         }
1846                         connector->interlace_allowed = true;
1847                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1848                                 connector->doublescan_allowed = true;
1849                         else
1850                                 connector->doublescan_allowed = false;
1851                         break;
1852                 case DRM_MODE_CONNECTOR_HDMIA:
1853                 case DRM_MODE_CONNECTOR_HDMIB:
1854                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1855                         if (!amdgpu_dig_connector)
1856                                 goto failed;
1857                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1858                         if (i2c_bus->valid) {
1859                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1860                                 if (!amdgpu_connector->ddc_bus)
1861                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1862                                 else
1863                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1864                         }
1865                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1866                                                     &amdgpu_connector_dvi_funcs,
1867                                                     connector_type,
1868                                                     ddc);
1869                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1870                         drm_object_attach_property(&amdgpu_connector->base.base,
1871                                                       adev->mode_info.coherent_mode_property,
1872                                                       1);
1873                         drm_object_attach_property(&amdgpu_connector->base.base,
1874                                                    adev->mode_info.underscan_property,
1875                                                    UNDERSCAN_OFF);
1876                         drm_object_attach_property(&amdgpu_connector->base.base,
1877                                                    adev->mode_info.underscan_hborder_property,
1878                                                    0);
1879                         drm_object_attach_property(&amdgpu_connector->base.base,
1880                                                    adev->mode_info.underscan_vborder_property,
1881                                                    0);
1882                         drm_object_attach_property(&amdgpu_connector->base.base,
1883                                                    dev->mode_config.scaling_mode_property,
1884                                                    DRM_MODE_SCALE_NONE);
1885                         if (amdgpu_audio != 0) {
1886                                 drm_object_attach_property(&amdgpu_connector->base.base,
1887                                                            adev->mode_info.audio_property,
1888                                                            AMDGPU_AUDIO_AUTO);
1889                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1890                         }
1891                         drm_object_attach_property(&amdgpu_connector->base.base,
1892                                                    adev->mode_info.dither_property,
1893                                                    AMDGPU_FMT_DITHER_DISABLE);
1894                         subpixel_order = SubPixelHorizontalRGB;
1895                         connector->interlace_allowed = true;
1896                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1897                                 connector->doublescan_allowed = true;
1898                         else
1899                                 connector->doublescan_allowed = false;
1900                         break;
1901                 case DRM_MODE_CONNECTOR_DisplayPort:
1902                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1903                         if (!amdgpu_dig_connector)
1904                                 goto failed;
1905                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1906                         if (i2c_bus->valid) {
1907                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1908                                 if (amdgpu_connector->ddc_bus) {
1909                                         has_aux = true;
1910                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1911                                 } else {
1912                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1913                                 }
1914                         }
1915                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1916                                                     &amdgpu_connector_dp_funcs,
1917                                                     connector_type,
1918                                                     ddc);
1919                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1920                         subpixel_order = SubPixelHorizontalRGB;
1921                         drm_object_attach_property(&amdgpu_connector->base.base,
1922                                                       adev->mode_info.coherent_mode_property,
1923                                                       1);
1924                         drm_object_attach_property(&amdgpu_connector->base.base,
1925                                                    adev->mode_info.underscan_property,
1926                                                    UNDERSCAN_OFF);
1927                         drm_object_attach_property(&amdgpu_connector->base.base,
1928                                                    adev->mode_info.underscan_hborder_property,
1929                                                    0);
1930                         drm_object_attach_property(&amdgpu_connector->base.base,
1931                                                    adev->mode_info.underscan_vborder_property,
1932                                                    0);
1933                         drm_object_attach_property(&amdgpu_connector->base.base,
1934                                                    dev->mode_config.scaling_mode_property,
1935                                                    DRM_MODE_SCALE_NONE);
1936                         if (amdgpu_audio != 0) {
1937                                 drm_object_attach_property(&amdgpu_connector->base.base,
1938                                                            adev->mode_info.audio_property,
1939                                                            AMDGPU_AUDIO_AUTO);
1940                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1941                         }
1942                         drm_object_attach_property(&amdgpu_connector->base.base,
1943                                                    adev->mode_info.dither_property,
1944                                                    AMDGPU_FMT_DITHER_DISABLE);
1945                         connector->interlace_allowed = true;
1946                         /* in theory with a DP to VGA converter... */
1947                         connector->doublescan_allowed = false;
1948                         break;
1949                 case DRM_MODE_CONNECTOR_eDP:
1950                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1951                         if (!amdgpu_dig_connector)
1952                                 goto failed;
1953                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1954                         if (i2c_bus->valid) {
1955                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1956                                 if (amdgpu_connector->ddc_bus) {
1957                                         has_aux = true;
1958                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1959                                 } else {
1960                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1961                                 }
1962                         }
1963                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1964                                                     &amdgpu_connector_edp_funcs,
1965                                                     connector_type,
1966                                                     ddc);
1967                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1968                         drm_object_attach_property(&amdgpu_connector->base.base,
1969                                                       dev->mode_config.scaling_mode_property,
1970                                                       DRM_MODE_SCALE_FULLSCREEN);
1971                         subpixel_order = SubPixelHorizontalRGB;
1972                         connector->interlace_allowed = false;
1973                         connector->doublescan_allowed = false;
1974                         break;
1975                 case DRM_MODE_CONNECTOR_LVDS:
1976                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1977                         if (!amdgpu_dig_connector)
1978                                 goto failed;
1979                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1980                         if (i2c_bus->valid) {
1981                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1982                                 if (!amdgpu_connector->ddc_bus)
1983                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1984                                 else
1985                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1986                         }
1987                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1988                                                     &amdgpu_connector_lvds_funcs,
1989                                                     connector_type,
1990                                                     ddc);
1991                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1992                         drm_object_attach_property(&amdgpu_connector->base.base,
1993                                                       dev->mode_config.scaling_mode_property,
1994                                                       DRM_MODE_SCALE_FULLSCREEN);
1995                         subpixel_order = SubPixelHorizontalRGB;
1996                         connector->interlace_allowed = false;
1997                         connector->doublescan_allowed = false;
1998                         break;
1999                 }
2000         }
2001
2002         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
2003                 if (i2c_bus->valid) {
2004                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2005                                                 DRM_CONNECTOR_POLL_DISCONNECT;
2006                 }
2007         } else
2008                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2009
2010         connector->display_info.subpixel_order = subpixel_order;
2011
2012         if (has_aux)
2013                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
2014
2015         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2016             connector_type == DRM_MODE_CONNECTOR_eDP) {
2017                 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
2018         }
2019
2020         return;
2021
2022 failed:
2023         drm_connector_cleanup(connector);
2024         kfree(connector);
2025 }