drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34 #include "psp_v11_0.h"
  35
  36 static void psp_set_funcs(struct amdgpu_device *adev);
  37
  38 static int psp_early_init(void *handle)
  39 {
  40         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  41
  42         psp_set_funcs(adev);
  43
  44         return 0;
  45 }
  46
  47 static int psp_sw_init(void *handle)
  48 {
  49         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  50         struct psp_context *psp = &adev->psp;
  51         int ret;
  52
  53         switch (adev->asic_type) {
  54         case CHIP_VEGA10:
  55         case CHIP_VEGA12:
  56                 psp_v3_1_set_psp_funcs(psp);
  57                 break;
  58         case CHIP_RAVEN:
  59                 psp_v10_0_set_psp_funcs(psp);
  60                 break;
  61         case CHIP_VEGA20:
  62                 psp_v11_0_set_psp_funcs(psp);
  63                 break;
  64         default:
  65                 return -EINVAL;
  66         }
  67
  68         psp->adev = adev;
  69
  70         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  71                 return 0;
  72
  73         ret = psp_init_microcode(psp);
  74         if (ret) {
  75                 DRM_ERROR("Failed to load psp firmware!\n");
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 static int psp_sw_fini(void *handle)
  83 {
  84         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85
  86         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  87                 return 0;
  88
  89         release_firmware(adev->psp.sos_fw);
  90         adev->psp.sos_fw = NULL;
  91         release_firmware(adev->psp.asd_fw);
  92         adev->psp.asd_fw = NULL;
  93         release_firmware(adev->psp.ta_fw);
  94         adev->psp.ta_fw = NULL;
  95         return 0;
  96 }
  97
  98 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  99                  uint32_t reg_val, uint32_t mask, bool check_changed)
 100 {
 101         uint32_t val;
 102         int i;
 103         struct amdgpu_device *adev = psp->adev;
 104
 105         for (i = 0; i < adev->usec_timeout; i++) {
 106                 val = RREG32(reg_index);
 107                 if (check_changed) {
 108                         if (val != reg_val)
 109                                 return 0;
 110                 } else {
 111                         if ((val & mask) == reg_val)
 112                                 return 0;
 113                 }
 114                 udelay(1);
 115         }
 116
 117         return -ETIME;
 118 }
 119
 120 static int
 121 psp_cmd_submit_buf(struct psp_context *psp,
 122                    struct amdgpu_firmware_info *ucode,
 123                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 124 {
 125         int ret;
 126         int index;
 127
 128         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 129
 130         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 131
 132         index = atomic_inc_return(&psp->fence_value);
 133         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 134                              fence_mc_addr, index);
 135         if (ret) {
 136                 atomic_dec(&psp->fence_value);
 137                 return ret;
 138         }
 139
 140         while (*((unsigned int *)psp->fence_buf) != index)
 141                 msleep(1);
 142
 143         /* In some cases, psp response status is not 0 even there is no
 144          * problem while the command is submitted. Some version of PSP FW
 145          * doesn't write 0 to that field.
 146          * So here we would like to only print a warning instead of an error
 147          * during psp initialization to avoid breaking hw_init and it doesn't
 148          * return -EINVAL.
 149          */
 150         if (psp->cmd_buf_mem->resp.status) {
 151                 if (ucode)
 152                         DRM_WARN("failed to load ucode id (%d) ",
 153                                   ucode->ucode_id);
 154                 DRM_WARN("psp command failed and response status is (%d)\n",
 155                           psp->cmd_buf_mem->resp.status);
 156         }
 157
 158         /* get xGMI session id from response buffer */
 159         cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
 160
 161         if (ucode) {
 162                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 163                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 164         }
 165
 166         return ret;
 167 }
 168
 169 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 170                                  struct psp_gfx_cmd_resp *cmd,
 171                                  uint64_t tmr_mc, uint32_t size)
 172 {
 173         if (psp_support_vmr_ring(psp))
 174                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 175         else
 176                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 177         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 178         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 179         cmd->cmd.cmd_setup_tmr.buf_size = size;
 180 }
 181
 182 /* Set up Trusted Memory Region */
 183 static int psp_tmr_init(struct psp_context *psp)
 184 {
 185         int ret;
 186
 187         /*
 188          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 189          * physical).
 190          *
 191          * Note: this memory need be reserved till the driver
 192          * uninitializes.
 193          */
 194         ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000,
 195                                       AMDGPU_GEM_DOMAIN_VRAM,
 196                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 197
 198         return ret;
 199 }
 200
 201 static int psp_tmr_load(struct psp_context *psp)
 202 {
 203         int ret;
 204         struct psp_gfx_cmd_resp *cmd;
 205
 206         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 207         if (!cmd)
 208                 return -ENOMEM;
 209
 210         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, PSP_TMR_SIZE);
 211         DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
 212                         PSP_TMR_SIZE, psp->tmr_mc_addr);
 213
 214         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 215                                  psp->fence_buf_mc_addr);
 216         if (ret)
 217                 goto failed;
 218
 219         kfree(cmd);
 220
 221         return 0;
 222
 223 failed:
 224         kfree(cmd);
 225         return ret;
 226 }
 227
 228 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 229                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 230                                  uint32_t size, uint32_t shared_size)
 231 {
 232         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 233         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 234         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 235         cmd->cmd.cmd_load_ta.app_len = size;
 236
 237         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 238         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 239         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 240 }
 241
 242 static int psp_asd_init(struct psp_context *psp)
 243 {
 244         int ret;
 245
 246         /*
 247          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 248          * physical) for shared ASD <-> Driver
 249          */
 250         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 251                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 252                                       &psp->asd_shared_bo,
 253                                       &psp->asd_shared_mc_addr,
 254                                       &psp->asd_shared_buf);
 255
 256         return ret;
 257 }
 258
 259 static int psp_asd_load(struct psp_context *psp)
 260 {
 261         int ret;
 262         struct psp_gfx_cmd_resp *cmd;
 263
 264         /* If PSP version doesn't match ASD version, asd loading will be failed.
 265          * add workaround to bypass it for sriov now.
 266          * TODO: add version check to make it common
 267          */
 268         if (amdgpu_sriov_vf(psp->adev))
 269                 return 0;
 270
 271         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 272         if (!cmd)
 273                 return -ENOMEM;
 274
 275         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 276         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 277
 278         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 279                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 280
 281         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 282                                  psp->fence_buf_mc_addr);
 283
 284         kfree(cmd);
 285
 286         return ret;
 287 }
 288
 289 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 290                                           uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
 291                                           uint32_t xgmi_ta_size, uint32_t shared_size)
 292 {
 293         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 294         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
 295         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
 296         cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
 297
 298         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
 299         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
 300         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 301 }
 302
 303 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 304 {
 305         int ret;
 306
 307         /*
 308          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 309          * physical) for xgmi ta <-> Driver
 310          */
 311         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 312                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 313                                       &psp->xgmi_context.xgmi_shared_bo,
 314                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 315                                       &psp->xgmi_context.xgmi_shared_buf);
 316
 317         return ret;
 318 }
 319
 320 static int psp_xgmi_load(struct psp_context *psp)
 321 {
 322         int ret;
 323         struct psp_gfx_cmd_resp *cmd;
 324
 325         /*
 326          * TODO: bypass the loading in sriov for now
 327          */
 328         if (amdgpu_sriov_vf(psp->adev))
 329                 return 0;
 330
 331         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 332         if (!cmd)
 333                 return -ENOMEM;
 334
 335         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 336         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 337
 338         psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 339                                       psp->xgmi_context.xgmi_shared_mc_addr,
 340                                       psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
 341
 342         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 343                                  psp->fence_buf_mc_addr);
 344
 345         if (!ret) {
 346                 psp->xgmi_context.initialized = 1;
 347                 psp->xgmi_context.session_id = cmd->resp.session_id;
 348         }
 349
 350         kfree(cmd);
 351
 352         return ret;
 353 }
 354
 355 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 356                                             uint32_t xgmi_session_id)
 357 {
 358         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 359         cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
 360 }
 361
 362 static int psp_xgmi_unload(struct psp_context *psp)
 363 {
 364         int ret;
 365         struct psp_gfx_cmd_resp *cmd;
 366
 367         /*
 368          * TODO: bypass the unloading in sriov for now
 369          */
 370         if (amdgpu_sriov_vf(psp->adev))
 371                 return 0;
 372
 373         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 374         if (!cmd)
 375                 return -ENOMEM;
 376
 377         psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 378
 379         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 380                                  psp->fence_buf_mc_addr);
 381
 382         kfree(cmd);
 383
 384         return ret;
 385 }
 386
 387 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 388                                             uint32_t ta_cmd_id,
 389                                             uint32_t xgmi_session_id)
 390 {
 391         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 392         cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
 393         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 394         /* Note: cmd_invoke_cmd.buf is not used for now */
 395 }
 396
 397 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 398 {
 399         int ret;
 400         struct psp_gfx_cmd_resp *cmd;
 401
 402         /*
 403          * TODO: bypass the loading in sriov for now
 404         */
 405         if (amdgpu_sriov_vf(psp->adev))
 406                 return 0;
 407
 408         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 409         if (!cmd)
 410                 return -ENOMEM;
 411
 412         psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 413                                         psp->xgmi_context.session_id);
 414
 415         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 416                                  psp->fence_buf_mc_addr);
 417
 418         kfree(cmd);
 419
 420         return ret;
 421 }
 422
 423 static int psp_xgmi_terminate(struct psp_context *psp)
 424 {
 425         int ret;
 426
 427         if (!psp->xgmi_context.initialized)
 428                 return 0;
 429
 430         ret = psp_xgmi_unload(psp);
 431         if (ret)
 432                 return ret;
 433
 434         psp->xgmi_context.initialized = 0;
 435
 436         /* free xgmi shared memory */
 437         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 438                         &psp->xgmi_context.xgmi_shared_mc_addr,
 439                         &psp->xgmi_context.xgmi_shared_buf);
 440
 441         return 0;
 442 }
 443
 444 static int psp_xgmi_initialize(struct psp_context *psp)
 445 {
 446         struct ta_xgmi_shared_memory *xgmi_cmd;
 447         int ret;
 448
 449         if (!psp->xgmi_context.initialized) {
 450                 ret = psp_xgmi_init_shared_buf(psp);
 451                 if (ret)
 452                         return ret;
 453         }
 454
 455         /* Load XGMI TA */
 456         ret = psp_xgmi_load(psp);
 457         if (ret)
 458                 return ret;
 459
 460         /* Initialize XGMI session */
 461         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 462         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 463         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 464
 465         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 466
 467         return ret;
 468 }
 469
 470 static int psp_hw_start(struct psp_context *psp)
 471 {
 472         struct amdgpu_device *adev = psp->adev;
 473         int ret;
 474
 475         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
 476                 ret = psp_bootloader_load_sysdrv(psp);
 477                 if (ret)
 478                         return ret;
 479
 480                 ret = psp_bootloader_load_sos(psp);
 481                 if (ret)
 482                         return ret;
 483         }
 484
 485         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 486         if (ret)
 487                 return ret;
 488
 489         ret = psp_tmr_load(psp);
 490         if (ret)
 491                 return ret;
 492
 493         ret = psp_asd_load(psp);
 494         if (ret)
 495                 return ret;
 496
 497         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 498                 ret = psp_xgmi_initialize(psp);
 499                 /* Warning the XGMI seesion initialize failure
 500                  * Instead of stop driver initialization
 501                  */
 502                 if (ret)
 503                         dev_err(psp->adev->dev,
 504                                 "XGMI: Failed to initialize XGMI session\n");
 505         }
 506         return 0;
 507 }
 508
 509 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
 510                            enum psp_gfx_fw_type *type)
 511 {
 512         switch (ucode->ucode_id) {
 513         case AMDGPU_UCODE_ID_SDMA0:
 514                 *type = GFX_FW_TYPE_SDMA0;
 515                 break;
 516         case AMDGPU_UCODE_ID_SDMA1:
 517                 *type = GFX_FW_TYPE_SDMA1;
 518                 break;
 519         case AMDGPU_UCODE_ID_CP_CE:
 520                 *type = GFX_FW_TYPE_CP_CE;
 521                 break;
 522         case AMDGPU_UCODE_ID_CP_PFP:
 523                 *type = GFX_FW_TYPE_CP_PFP;
 524                 break;
 525         case AMDGPU_UCODE_ID_CP_ME:
 526                 *type = GFX_FW_TYPE_CP_ME;
 527                 break;
 528         case AMDGPU_UCODE_ID_CP_MEC1:
 529                 *type = GFX_FW_TYPE_CP_MEC;
 530                 break;
 531         case AMDGPU_UCODE_ID_CP_MEC1_JT:
 532                 *type = GFX_FW_TYPE_CP_MEC_ME1;
 533                 break;
 534         case AMDGPU_UCODE_ID_CP_MEC2:
 535                 *type = GFX_FW_TYPE_CP_MEC;
 536                 break;
 537         case AMDGPU_UCODE_ID_CP_MEC2_JT:
 538                 *type = GFX_FW_TYPE_CP_MEC_ME2;
 539                 break;
 540         case AMDGPU_UCODE_ID_RLC_G:
 541                 *type = GFX_FW_TYPE_RLC_G;
 542                 break;
 543         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
 544                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
 545                 break;
 546         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
 547                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
 548                 break;
 549         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
 550                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
 551                 break;
 552         case AMDGPU_UCODE_ID_SMC:
 553                 *type = GFX_FW_TYPE_SMU;
 554                 break;
 555         case AMDGPU_UCODE_ID_UVD:
 556                 *type = GFX_FW_TYPE_UVD;
 557                 break;
 558         case AMDGPU_UCODE_ID_UVD1:
 559                 *type = GFX_FW_TYPE_UVD1;
 560                 break;
 561         case AMDGPU_UCODE_ID_VCE:
 562                 *type = GFX_FW_TYPE_VCE;
 563                 break;
 564         case AMDGPU_UCODE_ID_VCN:
 565                 *type = GFX_FW_TYPE_VCN;
 566                 break;
 567         case AMDGPU_UCODE_ID_DMCU_ERAM:
 568                 *type = GFX_FW_TYPE_DMCU_ERAM;
 569                 break;
 570         case AMDGPU_UCODE_ID_DMCU_INTV:
 571                 *type = GFX_FW_TYPE_DMCU_ISR;
 572                 break;
 573         case AMDGPU_UCODE_ID_MAXIMUM:
 574         default:
 575                 return -EINVAL;
 576         }
 577
 578         return 0;
 579 }
 580
 581 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
 582                                        struct psp_gfx_cmd_resp *cmd)
 583 {
 584         int ret;
 585         uint64_t fw_mem_mc_addr = ucode->mc_addr;
 586
 587         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 588
 589         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 590         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
 591         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 592         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
 593
 594         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
 595         if (ret)
 596                 DRM_ERROR("Unknown firmware type\n");
 597
 598         return ret;
 599 }
 600
 601 static int psp_np_fw_load(struct psp_context *psp)
 602 {
 603         int i, ret;
 604         struct amdgpu_firmware_info *ucode;
 605         struct amdgpu_device* adev = psp->adev;
 606
 607         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 608                 ucode = &adev->firmware.ucode[i];
 609                 if (!ucode->fw)
 610                         continue;
 611
 612                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 613                     psp_smu_reload_quirk(psp))
 614                         continue;
 615                 if (amdgpu_sriov_vf(adev) &&
 616                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 617                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 618                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 619                         /*skip ucode loading in SRIOV VF */
 620                         continue;
 621
 622                 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
 623                 if (ret)
 624                         return ret;
 625
 626                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 627                                          psp->fence_buf_mc_addr);
 628                 if (ret)
 629                         return ret;
 630
 631 #if 0
 632                 /* check if firmware loaded sucessfully */
 633                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 634                         return -EINVAL;
 635 #endif
 636         }
 637
 638         return 0;
 639 }
 640
 641 static int psp_load_fw(struct amdgpu_device *adev)
 642 {
 643         int ret;
 644         struct psp_context *psp = &adev->psp;
 645
 646         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
 647                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
 648                 goto skip_memalloc;
 649         }
 650
 651         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 652         if (!psp->cmd)
 653                 return -ENOMEM;
 654
 655         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 656                                         AMDGPU_GEM_DOMAIN_GTT,
 657                                         &psp->fw_pri_bo,
 658                                         &psp->fw_pri_mc_addr,
 659                                         &psp->fw_pri_buf);
 660         if (ret)
 661                 goto failed;
 662
 663         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 664                                         AMDGPU_GEM_DOMAIN_VRAM,
 665                                         &psp->fence_buf_bo,
 666                                         &psp->fence_buf_mc_addr,
 667                                         &psp->fence_buf);
 668         if (ret)
 669                 goto failed_mem2;
 670
 671         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 672                                       AMDGPU_GEM_DOMAIN_VRAM,
 673                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 674                                       (void **)&psp->cmd_buf_mem);
 675         if (ret)
 676                 goto failed_mem1;
 677
 678         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 679
 680         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 681         if (ret)
 682                 goto failed_mem;
 683
 684         ret = psp_tmr_init(psp);
 685         if (ret)
 686                 goto failed_mem;
 687
 688         ret = psp_asd_init(psp);
 689         if (ret)
 690                 goto failed_mem;
 691
 692 skip_memalloc:
 693         ret = psp_hw_start(psp);
 694         if (ret)
 695                 goto failed_mem;
 696
 697         ret = psp_np_fw_load(psp);
 698         if (ret)
 699                 goto failed_mem;
 700
 701         return 0;
 702
 703 failed_mem:
 704         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 705                               &psp->cmd_buf_mc_addr,
 706                               (void **)&psp->cmd_buf_mem);
 707 failed_mem1:
 708         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 709                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 710 failed_mem2:
 711         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 712                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 713 failed:
 714         kfree(psp->cmd);
 715         psp->cmd = NULL;
 716         return ret;
 717 }
 718
 719 static int psp_hw_init(void *handle)
 720 {
 721         int ret;
 722         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 723
 724
 725         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 726                 return 0;
 727
 728         mutex_lock(&adev->firmware.mutex);
 729         /*
 730          * This sequence is just used on hw_init only once, no need on
 731          * resume.
 732          */
 733         ret = amdgpu_ucode_init_bo(adev);
 734         if (ret)
 735                 goto failed;
 736
 737         ret = psp_load_fw(adev);
 738         if (ret) {
 739                 DRM_ERROR("PSP firmware loading failed\n");
 740                 goto failed;
 741         }
 742
 743         mutex_unlock(&adev->firmware.mutex);
 744         return 0;
 745
 746 failed:
 747         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 748         mutex_unlock(&adev->firmware.mutex);
 749         return -EINVAL;
 750 }
 751
 752 static int psp_hw_fini(void *handle)
 753 {
 754         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 755         struct psp_context *psp = &adev->psp;
 756
 757         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 758                 return 0;
 759
 760         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
 761             psp->xgmi_context.initialized == 1)
 762                 psp_xgmi_terminate(psp);
 763
 764         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 765
 766         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 767         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 768                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 769         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 770                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 771         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 772                               &psp->asd_shared_buf);
 773         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 774                               (void **)&psp->cmd_buf_mem);
 775
 776         kfree(psp->cmd);
 777         psp->cmd = NULL;
 778
 779         return 0;
 780 }
 781
 782 static int psp_suspend(void *handle)
 783 {
 784         int ret;
 785         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 786         struct psp_context *psp = &adev->psp;
 787
 788         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 789                 return 0;
 790
 791         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
 792             psp->xgmi_context.initialized == 1) {
 793                 ret = psp_xgmi_terminate(psp);
 794                 if (ret) {
 795                         DRM_ERROR("Failed to terminate xgmi ta\n");
 796                         return ret;
 797                 }
 798         }
 799
 800         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
 801         if (ret) {
 802                 DRM_ERROR("PSP ring stop failed\n");
 803                 return ret;
 804         }
 805
 806         return 0;
 807 }
 808
 809 static int psp_resume(void *handle)
 810 {
 811         int ret;
 812         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 813         struct psp_context *psp = &adev->psp;
 814
 815         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 816                 return 0;
 817
 818         DRM_INFO("PSP is resuming...\n");
 819
 820         mutex_lock(&adev->firmware.mutex);
 821
 822         ret = psp_hw_start(psp);
 823         if (ret)
 824                 goto failed;
 825
 826         ret = psp_np_fw_load(psp);
 827         if (ret)
 828                 goto failed;
 829
 830         mutex_unlock(&adev->firmware.mutex);
 831
 832         return 0;
 833
 834 failed:
 835         DRM_ERROR("PSP resume failed\n");
 836         mutex_unlock(&adev->firmware.mutex);
 837         return ret;
 838 }
 839
 840 int psp_gpu_reset(struct amdgpu_device *adev)
 841 {
 842         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 843                 return 0;
 844
 845         return psp_mode1_reset(&adev->psp);
 846 }
 847
 848 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 849                                         enum AMDGPU_UCODE_ID ucode_type)
 850 {
 851         struct amdgpu_firmware_info *ucode = NULL;
 852
 853         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 854                 DRM_INFO("firmware is not loaded by PSP\n");
 855                 return true;
 856         }
 857
 858         if (!adev->firmware.fw_size)
 859                 return false;
 860
 861         ucode = &adev->firmware.ucode[ucode_type];
 862         if (!ucode->fw || !ucode->ucode_size)
 863                 return false;
 864
 865         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 866 }
 867
 868 static int psp_set_clockgating_state(void *handle,
 869                                      enum amd_clockgating_state state)
 870 {
 871         return 0;
 872 }
 873
 874 static int psp_set_powergating_state(void *handle,
 875                                      enum amd_powergating_state state)
 876 {
 877         return 0;
 878 }
 879
 880 const struct amd_ip_funcs psp_ip_funcs = {
 881         .name = "psp",
 882         .early_init = psp_early_init,
 883         .late_init = NULL,
 884         .sw_init = psp_sw_init,
 885         .sw_fini = psp_sw_fini,
 886         .hw_init = psp_hw_init,
 887         .hw_fini = psp_hw_fini,
 888         .suspend = psp_suspend,
 889         .resume = psp_resume,
 890         .is_idle = NULL,
 891         .check_soft_reset = NULL,
 892         .wait_for_idle = NULL,
 893         .soft_reset = NULL,
 894         .set_clockgating_state = psp_set_clockgating_state,
 895         .set_powergating_state = psp_set_powergating_state,
 896 };
 897
 898 static const struct amdgpu_psp_funcs psp_funcs = {
 899         .check_fw_loading_status = psp_check_fw_loading_status,
 900 };
 901
 902 static void psp_set_funcs(struct amdgpu_device *adev)
 903 {
 904         if (NULL == adev->firmware.funcs)
 905                 adev->firmware.funcs = &psp_funcs;
 906 }
 907
 908 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 909 {
 910         .type = AMD_IP_BLOCK_TYPE_PSP,
 911         .major = 3,
 912         .minor = 1,
 913         .rev = 0,
 914         .funcs = &psp_ip_funcs,
 915 };
 916
 917 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 918 {
 919         .type = AMD_IP_BLOCK_TYPE_PSP,
 920         .major = 10,
 921         .minor = 0,
 922         .rev = 0,
 923         .funcs = &psp_ip_funcs,
 924 };
 925
 926 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
 927 {
 928         .type = AMD_IP_BLOCK_TYPE_PSP,
 929         .major = 11,
 930         .minor = 0,
 931         .rev = 0,
 932         .funcs = &psp_ip_funcs,
 933 };