drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_ucode.h"
  30 #include "amdgpu_trace.h"
  31 #include "cikd.h"
  32 #include "cik.h"
  33
  34 #include "bif/bif_4_1_d.h"
  35 #include "bif/bif_4_1_sh_mask.h"
  36
  37 #include "gca/gfx_7_2_d.h"
  38 #include "gca/gfx_7_2_enum.h"
  39 #include "gca/gfx_7_2_sh_mask.h"
  40
  41 #include "gmc/gmc_7_1_d.h"
  42 #include "gmc/gmc_7_1_sh_mask.h"
  43
  44 #include "oss/oss_2_0_d.h"
  45 #include "oss/oss_2_0_sh_mask.h"
  46
  47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  48 {
  49         SDMA0_REGISTER_OFFSET,
  50         SDMA1_REGISTER_OFFSET
  51 };
  52
  53 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  55 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  56 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  57 static int cik_sdma_soft_reset(void *handle);
  58
  59 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
  69
  70 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  71
  72
  73 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  74 {
  75         int i;
  76
  77         for (i = 0; i < adev->sdma.num_instances; i++)
  78                 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
  79 }
  80
  81 /*
  82  * sDMA - System DMA
  83  * Starting with CIK, the GPU has new asynchronous
  84  * DMA engines.  These engines are used for compute
  85  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  86  * and each one supports 1 ring buffer used for gfx
  87  * and 2 queues used for compute.
  88  *
  89  * The programming model is very similar to the CP
  90  * (ring buffer, IBs, etc.), but sDMA has it's own
  91  * packet format that is different from the PM4 format
  92  * used by the CP. sDMA supports copying data, writing
  93  * embedded data, solid fills, and a number of other
  94  * things.  It also has support for tiling/detiling of
  95  * buffers.
  96  */
  97
  98 /**
  99  * cik_sdma_init_microcode - load ucode images from disk
 100  *
 101  * @adev: amdgpu_device pointer
 102  *
 103  * Use the firmware interface to load the ucode images into
 104  * the driver (not loaded into hw).
 105  * Returns 0 on success, error on failure.
 106  */
 107 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
 108 {
 109         const char *chip_name;
 110         char fw_name[30];
 111         int err = 0, i;
 112
 113         DRM_DEBUG("\n");
 114
 115         switch (adev->asic_type) {
 116         case CHIP_BONAIRE:
 117                 chip_name = "bonaire";
 118                 break;
 119         case CHIP_HAWAII:
 120                 chip_name = "hawaii";
 121                 break;
 122         case CHIP_KAVERI:
 123                 chip_name = "kaveri";
 124                 break;
 125         case CHIP_KABINI:
 126                 chip_name = "kabini";
 127                 break;
 128         case CHIP_MULLINS:
 129                 chip_name = "mullins";
 130                 break;
 131         default: BUG();
 132         }
 133
 134         for (i = 0; i < adev->sdma.num_instances; i++) {
 135                 if (i == 0)
 136                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 137                 else
 138                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 139                 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name);
 140                 if (err)
 141                         goto out;
 142         }
 143 out:
 144         if (err) {
 145                 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
 146                 for (i = 0; i < adev->sdma.num_instances; i++)
 147                         amdgpu_ucode_release(&adev->sdma.instance[i].fw);
 148         }
 149         return err;
 150 }
 151
 152 /**
 153  * cik_sdma_ring_get_rptr - get the current read pointer
 154  *
 155  * @ring: amdgpu ring pointer
 156  *
 157  * Get the current rptr from the hardware (CIK+).
 158  */
 159 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 160 {
 161         u32 rptr;
 162
 163         rptr = *ring->rptr_cpu_addr;
 164
 165         return (rptr & 0x3fffc) >> 2;
 166 }
 167
 168 /**
 169  * cik_sdma_ring_get_wptr - get the current write pointer
 170  *
 171  * @ring: amdgpu ring pointer
 172  *
 173  * Get the current wptr from the hardware (CIK+).
 174  */
 175 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_device *adev = ring->adev;
 178
 179         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
 180 }
 181
 182 /**
 183  * cik_sdma_ring_set_wptr - commit the write pointer
 184  *
 185  * @ring: amdgpu ring pointer
 186  *
 187  * Write the wptr back to the hardware (CIK+).
 188  */
 189 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 190 {
 191         struct amdgpu_device *adev = ring->adev;
 192
 193         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
 194                (ring->wptr << 2) & 0x3fffc);
 195 }
 196
 197 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 198 {
 199         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 200         int i;
 201
 202         for (i = 0; i < count; i++)
 203                 if (sdma && sdma->burst_nop && (i == 0))
 204                         amdgpu_ring_write(ring, ring->funcs->nop |
 205                                           SDMA_NOP_COUNT(count - 1));
 206                 else
 207                         amdgpu_ring_write(ring, ring->funcs->nop);
 208 }
 209
 210 /**
 211  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 212  *
 213  * @ring: amdgpu ring pointer
 214  * @job: job to retrive vmid from
 215  * @ib: IB object to schedule
 216  * @flags: unused
 217  *
 218  * Schedule an IB in the DMA ring (CIK).
 219  */
 220 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 221                                   struct amdgpu_job *job,
 222                                   struct amdgpu_ib *ib,
 223                                   uint32_t flags)
 224 {
 225         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 226         u32 extra_bits = vmid & 0xf;
 227
 228         /* IB packet must end on a 8 DW boundary */
 229         cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
 230
 231         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 232         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 233         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 234         amdgpu_ring_write(ring, ib->length_dw);
 235
 236 }
 237
 238 /**
 239  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 240  *
 241  * @ring: amdgpu ring pointer
 242  *
 243  * Emit an hdp flush packet on the requested DMA ring.
 244  */
 245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 246 {
 247         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 248                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 249         u32 ref_and_mask;
 250
 251         if (ring->me == 0)
 252                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 253         else
 254                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 255
 256         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 257         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 258         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 259         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 260         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 261         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 262 }
 263
 264 /**
 265  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 266  *
 267  * @ring: amdgpu ring pointer
 268  * @addr: address
 269  * @seq: sequence number
 270  * @flags: fence related flags
 271  *
 272  * Add a DMA fence packet to the ring to write
 273  * the fence seq number and DMA trap packet to generate
 274  * an interrupt if needed (CIK).
 275  */
 276 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 277                                      unsigned flags)
 278 {
 279         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 280         /* write the fence */
 281         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 282         amdgpu_ring_write(ring, lower_32_bits(addr));
 283         amdgpu_ring_write(ring, upper_32_bits(addr));
 284         amdgpu_ring_write(ring, lower_32_bits(seq));
 285
 286         /* optionally write high bits as well */
 287         if (write64bit) {
 288                 addr += 4;
 289                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 290                 amdgpu_ring_write(ring, lower_32_bits(addr));
 291                 amdgpu_ring_write(ring, upper_32_bits(addr));
 292                 amdgpu_ring_write(ring, upper_32_bits(seq));
 293         }
 294
 295         /* generate an interrupt */
 296         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 297 }
 298
 299 /**
 300  * cik_sdma_gfx_stop - stop the gfx async dma engines
 301  *
 302  * @adev: amdgpu_device pointer
 303  *
 304  * Stop the gfx async dma ring buffers (CIK).
 305  */
 306 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 307 {
 308         u32 rb_cntl;
 309         int i;
 310
 311         amdgpu_sdma_unset_buffer_funcs_helper(adev);
 312
 313         for (i = 0; i < adev->sdma.num_instances; i++) {
 314                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 315                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 316                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 317                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 318         }
 319 }
 320
 321 /**
 322  * cik_sdma_rlc_stop - stop the compute async dma engines
 323  *
 324  * @adev: amdgpu_device pointer
 325  *
 326  * Stop the compute async dma queues (CIK).
 327  */
 328 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 329 {
 330         /* XXX todo */
 331 }
 332
 333 /**
 334  * cik_ctx_switch_enable - stop the async dma engines context switch
 335  *
 336  * @adev: amdgpu_device pointer
 337  * @enable: enable/disable the DMA MEs context switch.
 338  *
 339  * Halt or unhalt the async dma engines context switch (VI).
 340  */
 341 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 342 {
 343         u32 f32_cntl, phase_quantum = 0;
 344         int i;
 345
 346         if (amdgpu_sdma_phase_quantum) {
 347                 unsigned value = amdgpu_sdma_phase_quantum;
 348                 unsigned unit = 0;
 349
 350                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 351                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 352                         value = (value + 1) >> 1;
 353                         unit++;
 354                 }
 355                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 356                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 357                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 358                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 359                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 360                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 361                         WARN_ONCE(1,
 362                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 363                                   value << unit);
 364                 }
 365                 phase_quantum =
 366                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 367                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 368         }
 369
 370         for (i = 0; i < adev->sdma.num_instances; i++) {
 371                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 372                 if (enable) {
 373                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 374                                         AUTO_CTXSW_ENABLE, 1);
 375                         if (amdgpu_sdma_phase_quantum) {
 376                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 377                                        phase_quantum);
 378                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 379                                        phase_quantum);
 380                         }
 381                 } else {
 382                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 383                                         AUTO_CTXSW_ENABLE, 0);
 384                 }
 385
 386                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 387         }
 388 }
 389
 390 /**
 391  * cik_sdma_enable - stop the async dma engines
 392  *
 393  * @adev: amdgpu_device pointer
 394  * @enable: enable/disable the DMA MEs.
 395  *
 396  * Halt or unhalt the async dma engines (CIK).
 397  */
 398 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 399 {
 400         u32 me_cntl;
 401         int i;
 402
 403         if (!enable) {
 404                 cik_sdma_gfx_stop(adev);
 405                 cik_sdma_rlc_stop(adev);
 406         }
 407
 408         for (i = 0; i < adev->sdma.num_instances; i++) {
 409                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 410                 if (enable)
 411                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 412                 else
 413                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 414                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 415         }
 416 }
 417
 418 /**
 419  * cik_sdma_gfx_resume - setup and start the async dma engines
 420  *
 421  * @adev: amdgpu_device pointer
 422  *
 423  * Set up the gfx DMA ring buffers and enable them (CIK).
 424  * Returns 0 for success, error for failure.
 425  */
 426 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 427 {
 428         struct amdgpu_ring *ring;
 429         u32 rb_cntl, ib_cntl;
 430         u32 rb_bufsz;
 431         int i, j, r;
 432
 433         for (i = 0; i < adev->sdma.num_instances; i++) {
 434                 ring = &adev->sdma.instance[i].ring;
 435
 436                 mutex_lock(&adev->srbm_mutex);
 437                 for (j = 0; j < 16; j++) {
 438                         cik_srbm_select(adev, 0, 0, 0, j);
 439                         /* SDMA GFX */
 440                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 441                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 442                         /* XXX SDMA RLC - todo */
 443                 }
 444                 cik_srbm_select(adev, 0, 0, 0, 0);
 445                 mutex_unlock(&adev->srbm_mutex);
 446
 447                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 448                        adev->gfx.config.gb_addr_config & 0x70);
 449
 450                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 451                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 452
 453                 /* Set ring buffer size in dwords */
 454                 rb_bufsz = order_base_2(ring->ring_size / 4);
 455                 rb_cntl = rb_bufsz << 1;
 456 #ifdef __BIG_ENDIAN
 457                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 458                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 459 #endif
 460                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 461
 462                 /* Initialize the ring buffer's read and write pointers */
 463                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 464                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 465                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 466                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 467
 468                 /* set the wb address whether it's enabled or not */
 469                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 470                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 471                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 472                        ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
 473
 474                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 475
 476                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 477                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 478
 479                 ring->wptr = 0;
 480                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 481
 482                 /* enable DMA RB */
 483                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 484                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 485
 486                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 487 #ifdef __BIG_ENDIAN
 488                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 489 #endif
 490                 /* enable DMA IBs */
 491                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 492
 493                 ring->sched.ready = true;
 494         }
 495
 496         cik_sdma_enable(adev, true);
 497
 498         for (i = 0; i < adev->sdma.num_instances; i++) {
 499                 ring = &adev->sdma.instance[i].ring;
 500                 r = amdgpu_ring_test_helper(ring);
 501                 if (r)
 502                         return r;
 503
 504                 if (adev->mman.buffer_funcs_ring == ring)
 505                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 506         }
 507
 508         return 0;
 509 }
 510
 511 /**
 512  * cik_sdma_rlc_resume - setup and start the async dma engines
 513  *
 514  * @adev: amdgpu_device pointer
 515  *
 516  * Set up the compute DMA queues and enable them (CIK).
 517  * Returns 0 for success, error for failure.
 518  */
 519 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 520 {
 521         /* XXX todo */
 522         return 0;
 523 }
 524
 525 /**
 526  * cik_sdma_load_microcode - load the sDMA ME ucode
 527  *
 528  * @adev: amdgpu_device pointer
 529  *
 530  * Loads the sDMA0/1 ucode.
 531  * Returns 0 for success, -EINVAL if the ucode is not available.
 532  */
 533 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 534 {
 535         const struct sdma_firmware_header_v1_0 *hdr;
 536         const __le32 *fw_data;
 537         u32 fw_size;
 538         int i, j;
 539
 540         /* halt the MEs */
 541         cik_sdma_enable(adev, false);
 542
 543         for (i = 0; i < adev->sdma.num_instances; i++) {
 544                 if (!adev->sdma.instance[i].fw)
 545                         return -EINVAL;
 546                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 547                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 548                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 549                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 550                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 551                 if (adev->sdma.instance[i].feature_version >= 20)
 552                         adev->sdma.instance[i].burst_nop = true;
 553                 fw_data = (const __le32 *)
 554                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 555                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 556                 for (j = 0; j < fw_size; j++)
 557                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 558                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 559         }
 560
 561         return 0;
 562 }
 563
 564 /**
 565  * cik_sdma_start - setup and start the async dma engines
 566  *
 567  * @adev: amdgpu_device pointer
 568  *
 569  * Set up the DMA engines and enable them (CIK).
 570  * Returns 0 for success, error for failure.
 571  */
 572 static int cik_sdma_start(struct amdgpu_device *adev)
 573 {
 574         int r;
 575
 576         r = cik_sdma_load_microcode(adev);
 577         if (r)
 578                 return r;
 579
 580         /* halt the engine before programing */
 581         cik_sdma_enable(adev, false);
 582         /* enable sdma ring preemption */
 583         cik_ctx_switch_enable(adev, true);
 584
 585         /* start the gfx rings and rlc compute queues */
 586         r = cik_sdma_gfx_resume(adev);
 587         if (r)
 588                 return r;
 589         r = cik_sdma_rlc_resume(adev);
 590         if (r)
 591                 return r;
 592
 593         return 0;
 594 }
 595
 596 /**
 597  * cik_sdma_ring_test_ring - simple async dma engine test
 598  *
 599  * @ring: amdgpu_ring structure holding ring information
 600  *
 601  * Test the DMA engine by writing using it to write an
 602  * value to memory. (CIK).
 603  * Returns 0 for success, error for failure.
 604  */
 605 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 606 {
 607         struct amdgpu_device *adev = ring->adev;
 608         unsigned i;
 609         unsigned index;
 610         int r;
 611         u32 tmp;
 612         u64 gpu_addr;
 613
 614         r = amdgpu_device_wb_get(adev, &index);
 615         if (r)
 616                 return r;
 617
 618         gpu_addr = adev->wb.gpu_addr + (index * 4);
 619         tmp = 0xCAFEDEAD;
 620         adev->wb.wb[index] = cpu_to_le32(tmp);
 621
 622         r = amdgpu_ring_alloc(ring, 5);
 623         if (r)
 624                 goto error_free_wb;
 625
 626         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 627         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 628         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 629         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 630         amdgpu_ring_write(ring, 0xDEADBEEF);
 631         amdgpu_ring_commit(ring);
 632
 633         for (i = 0; i < adev->usec_timeout; i++) {
 634                 tmp = le32_to_cpu(adev->wb.wb[index]);
 635                 if (tmp == 0xDEADBEEF)
 636                         break;
 637                 udelay(1);
 638         }
 639
 640         if (i >= adev->usec_timeout)
 641                 r = -ETIMEDOUT;
 642
 643 error_free_wb:
 644         amdgpu_device_wb_free(adev, index);
 645         return r;
 646 }
 647
 648 /**
 649  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 650  *
 651  * @ring: amdgpu_ring structure holding ring information
 652  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 653  *
 654  * Test a simple IB in the DMA ring (CIK).
 655  * Returns 0 on success, error on failure.
 656  */
 657 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 658 {
 659         struct amdgpu_device *adev = ring->adev;
 660         struct amdgpu_ib ib;
 661         struct dma_fence *f = NULL;
 662         unsigned index;
 663         u32 tmp = 0;
 664         u64 gpu_addr;
 665         long r;
 666
 667         r = amdgpu_device_wb_get(adev, &index);
 668         if (r)
 669                 return r;
 670
 671         gpu_addr = adev->wb.gpu_addr + (index * 4);
 672         tmp = 0xCAFEDEAD;
 673         adev->wb.wb[index] = cpu_to_le32(tmp);
 674         memset(&ib, 0, sizeof(ib));
 675         r = amdgpu_ib_get(adev, NULL, 256,
 676                                         AMDGPU_IB_POOL_DIRECT, &ib);
 677         if (r)
 678                 goto err0;
 679
 680         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 681                                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 682         ib.ptr[1] = lower_32_bits(gpu_addr);
 683         ib.ptr[2] = upper_32_bits(gpu_addr);
 684         ib.ptr[3] = 1;
 685         ib.ptr[4] = 0xDEADBEEF;
 686         ib.length_dw = 5;
 687         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 688         if (r)
 689                 goto err1;
 690
 691         r = dma_fence_wait_timeout(f, false, timeout);
 692         if (r == 0) {
 693                 r = -ETIMEDOUT;
 694                 goto err1;
 695         } else if (r < 0) {
 696                 goto err1;
 697         }
 698         tmp = le32_to_cpu(adev->wb.wb[index]);
 699         if (tmp == 0xDEADBEEF)
 700                 r = 0;
 701         else
 702                 r = -EINVAL;
 703
 704 err1:
 705         amdgpu_ib_free(adev, &ib, NULL);
 706         dma_fence_put(f);
 707 err0:
 708         amdgpu_device_wb_free(adev, index);
 709         return r;
 710 }
 711
 712 /**
 713  * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
 714  *
 715  * @ib: indirect buffer to fill with commands
 716  * @pe: addr of the page entry
 717  * @src: src addr to copy from
 718  * @count: number of page entries to update
 719  *
 720  * Update PTEs by copying them from the GART using sDMA (CIK).
 721  */
 722 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 723                                  uint64_t pe, uint64_t src,
 724                                  unsigned count)
 725 {
 726         unsigned bytes = count * 8;
 727
 728         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 729                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 730         ib->ptr[ib->length_dw++] = bytes;
 731         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 732         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 733         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 734         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 735         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 736 }
 737
 738 /**
 739  * cik_sdma_vm_write_pte - update PTEs by writing them manually
 740  *
 741  * @ib: indirect buffer to fill with commands
 742  * @pe: addr of the page entry
 743  * @value: dst addr to write into pe
 744  * @count: number of page entries to update
 745  * @incr: increase next addr by incr bytes
 746  *
 747  * Update PTEs by writing them manually using sDMA (CIK).
 748  */
 749 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 750                                   uint64_t value, unsigned count,
 751                                   uint32_t incr)
 752 {
 753         unsigned ndw = count * 2;
 754
 755         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 756                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 757         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 758         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 759         ib->ptr[ib->length_dw++] = ndw;
 760         for (; ndw > 0; ndw -= 2) {
 761                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 762                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 763                 value += incr;
 764         }
 765 }
 766
 767 /**
 768  * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
 769  *
 770  * @ib: indirect buffer to fill with commands
 771  * @pe: addr of the page entry
 772  * @addr: dst addr to write into pe
 773  * @count: number of page entries to update
 774  * @incr: increase next addr by incr bytes
 775  * @flags: access flags
 776  *
 777  * Update the page tables using sDMA (CIK).
 778  */
 779 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 780                                     uint64_t addr, unsigned count,
 781                                     uint32_t incr, uint64_t flags)
 782 {
 783         /* for physically contiguous pages (vram) */
 784         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 785         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 786         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 787         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 788         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 789         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 790         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 791         ib->ptr[ib->length_dw++] = incr; /* increment size */
 792         ib->ptr[ib->length_dw++] = 0;
 793         ib->ptr[ib->length_dw++] = count; /* number of entries */
 794 }
 795
 796 /**
 797  * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
 798  *
 799  * @ring: amdgpu_ring structure holding ring information
 800  * @ib: indirect buffer to fill with padding
 801  *
 802  */
 803 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 804 {
 805         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 806         u32 pad_count;
 807         int i;
 808
 809         pad_count = (-ib->length_dw) & 7;
 810         for (i = 0; i < pad_count; i++)
 811                 if (sdma && sdma->burst_nop && (i == 0))
 812                         ib->ptr[ib->length_dw++] =
 813                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 814                                         SDMA_NOP_COUNT(pad_count - 1);
 815                 else
 816                         ib->ptr[ib->length_dw++] =
 817                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 818 }
 819
 820 /**
 821  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 822  *
 823  * @ring: amdgpu_ring pointer
 824  *
 825  * Make sure all previous operations are completed (CIK).
 826  */
 827 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 828 {
 829         uint32_t seq = ring->fence_drv.sync_seq;
 830         uint64_t addr = ring->fence_drv.gpu_addr;
 831
 832         /* wait for idle */
 833         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 834                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 835                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 836                                             SDMA_POLL_REG_MEM_EXTRA_M));
 837         amdgpu_ring_write(ring, addr & 0xfffffffc);
 838         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 839         amdgpu_ring_write(ring, seq); /* reference */
 840         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 841         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 842 }
 843
 844 /**
 845  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 846  *
 847  * @ring: amdgpu_ring pointer
 848  * @vmid: vmid number to use
 849  * @pd_addr: address
 850  *
 851  * Update the page table base and flush the VM TLB
 852  * using sDMA (CIK).
 853  */
 854 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 855                                         unsigned vmid, uint64_t pd_addr)
 856 {
 857         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 858                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 859
 860         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 861
 862         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 863         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 864         amdgpu_ring_write(ring, 0);
 865         amdgpu_ring_write(ring, 0); /* reference */
 866         amdgpu_ring_write(ring, 0); /* mask */
 867         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 868 }
 869
 870 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
 871                                     uint32_t reg, uint32_t val)
 872 {
 873         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 874         amdgpu_ring_write(ring, reg);
 875         amdgpu_ring_write(ring, val);
 876 }
 877
 878 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 879                                  bool enable)
 880 {
 881         u32 orig, data;
 882
 883         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 884                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 885                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 886         } else {
 887                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 888                 data |= 0xff000000;
 889                 if (data != orig)
 890                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 891
 892                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 893                 data |= 0xff000000;
 894                 if (data != orig)
 895                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 896         }
 897 }
 898
 899 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 900                                  bool enable)
 901 {
 902         u32 orig, data;
 903
 904         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 905                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 906                 data |= 0x100;
 907                 if (orig != data)
 908                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 909
 910                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 911                 data |= 0x100;
 912                 if (orig != data)
 913                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 914         } else {
 915                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 916                 data &= ~0x100;
 917                 if (orig != data)
 918                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 919
 920                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 921                 data &= ~0x100;
 922                 if (orig != data)
 923                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 924         }
 925 }
 926
 927 static int cik_sdma_early_init(void *handle)
 928 {
 929         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 930
 931         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 932
 933         cik_sdma_set_ring_funcs(adev);
 934         cik_sdma_set_irq_funcs(adev);
 935         cik_sdma_set_buffer_funcs(adev);
 936         cik_sdma_set_vm_pte_funcs(adev);
 937
 938         return 0;
 939 }
 940
 941 static int cik_sdma_sw_init(void *handle)
 942 {
 943         struct amdgpu_ring *ring;
 944         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 945         int r, i;
 946
 947         r = cik_sdma_init_microcode(adev);
 948         if (r) {
 949                 DRM_ERROR("Failed to load sdma firmware!\n");
 950                 return r;
 951         }
 952
 953         /* SDMA trap event */
 954         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
 955                               &adev->sdma.trap_irq);
 956         if (r)
 957                 return r;
 958
 959         /* SDMA Privileged inst */
 960         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
 961                               &adev->sdma.illegal_inst_irq);
 962         if (r)
 963                 return r;
 964
 965         /* SDMA Privileged inst */
 966         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
 967                               &adev->sdma.illegal_inst_irq);
 968         if (r)
 969                 return r;
 970
 971         for (i = 0; i < adev->sdma.num_instances; i++) {
 972                 ring = &adev->sdma.instance[i].ring;
 973                 ring->ring_obj = NULL;
 974                 sprintf(ring->name, "sdma%d", i);
 975                 r = amdgpu_ring_init(adev, ring, 1024,
 976                                      &adev->sdma.trap_irq,
 977                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
 978                                      AMDGPU_SDMA_IRQ_INSTANCE1,
 979                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
 980                 if (r)
 981                         return r;
 982         }
 983
 984         return r;
 985 }
 986
 987 static int cik_sdma_sw_fini(void *handle)
 988 {
 989         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 990         int i;
 991
 992         for (i = 0; i < adev->sdma.num_instances; i++)
 993                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 994
 995         cik_sdma_free_microcode(adev);
 996         return 0;
 997 }
 998
 999 static int cik_sdma_hw_init(void *handle)
1000 {
1001         int r;
1002         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1003
1004         r = cik_sdma_start(adev);
1005         if (r)
1006                 return r;
1007
1008         return r;
1009 }
1010
1011 static int cik_sdma_hw_fini(void *handle)
1012 {
1013         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1014
1015         cik_ctx_switch_enable(adev, false);
1016         cik_sdma_enable(adev, false);
1017
1018         return 0;
1019 }
1020
1021 static int cik_sdma_suspend(void *handle)
1022 {
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025         return cik_sdma_hw_fini(adev);
1026 }
1027
1028 static int cik_sdma_resume(void *handle)
1029 {
1030         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031
1032         cik_sdma_soft_reset(handle);
1033
1034         return cik_sdma_hw_init(adev);
1035 }
1036
1037 static bool cik_sdma_is_idle(void *handle)
1038 {
1039         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1040         u32 tmp = RREG32(mmSRBM_STATUS2);
1041
1042         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1043                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1044             return false;
1045
1046         return true;
1047 }
1048
1049 static int cik_sdma_wait_for_idle(void *handle)
1050 {
1051         unsigned i;
1052         u32 tmp;
1053         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054
1055         for (i = 0; i < adev->usec_timeout; i++) {
1056                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1057                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1058
1059                 if (!tmp)
1060                         return 0;
1061                 udelay(1);
1062         }
1063         return -ETIMEDOUT;
1064 }
1065
1066 static int cik_sdma_soft_reset(void *handle)
1067 {
1068         u32 srbm_soft_reset = 0;
1069         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1070         u32 tmp;
1071
1072         /* sdma0 */
1073         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1074         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1075         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1076         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1077
1078         /* sdma1 */
1079         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1080         tmp |= SDMA0_F32_CNTL__HALT_MASK;
1081         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1082         srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1083
1084         if (srbm_soft_reset) {
1085                 tmp = RREG32(mmSRBM_SOFT_RESET);
1086                 tmp |= srbm_soft_reset;
1087                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1088                 WREG32(mmSRBM_SOFT_RESET, tmp);
1089                 tmp = RREG32(mmSRBM_SOFT_RESET);
1090
1091                 udelay(50);
1092
1093                 tmp &= ~srbm_soft_reset;
1094                 WREG32(mmSRBM_SOFT_RESET, tmp);
1095                 tmp = RREG32(mmSRBM_SOFT_RESET);
1096
1097                 /* Wait a little for things to settle down */
1098                 udelay(50);
1099         }
1100
1101         return 0;
1102 }
1103
1104 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1105                                        struct amdgpu_irq_src *src,
1106                                        unsigned type,
1107                                        enum amdgpu_interrupt_state state)
1108 {
1109         u32 sdma_cntl;
1110
1111         switch (type) {
1112         case AMDGPU_SDMA_IRQ_INSTANCE0:
1113                 switch (state) {
1114                 case AMDGPU_IRQ_STATE_DISABLE:
1115                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1116                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1117                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1118                         break;
1119                 case AMDGPU_IRQ_STATE_ENABLE:
1120                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1121                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1122                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1123                         break;
1124                 default:
1125                         break;
1126                 }
1127                 break;
1128         case AMDGPU_SDMA_IRQ_INSTANCE1:
1129                 switch (state) {
1130                 case AMDGPU_IRQ_STATE_DISABLE:
1131                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1132                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1133                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1134                         break;
1135                 case AMDGPU_IRQ_STATE_ENABLE:
1136                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1137                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1138                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1139                         break;
1140                 default:
1141                         break;
1142                 }
1143                 break;
1144         default:
1145                 break;
1146         }
1147         return 0;
1148 }
1149
1150 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1151                                      struct amdgpu_irq_src *source,
1152                                      struct amdgpu_iv_entry *entry)
1153 {
1154         u8 instance_id, queue_id;
1155
1156         instance_id = (entry->ring_id & 0x3) >> 0;
1157         queue_id = (entry->ring_id & 0xc) >> 2;
1158         DRM_DEBUG("IH: SDMA trap\n");
1159         switch (instance_id) {
1160         case 0:
1161                 switch (queue_id) {
1162                 case 0:
1163                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1164                         break;
1165                 case 1:
1166                         /* XXX compute */
1167                         break;
1168                 case 2:
1169                         /* XXX compute */
1170                         break;
1171                 }
1172                 break;
1173         case 1:
1174                 switch (queue_id) {
1175                 case 0:
1176                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1177                         break;
1178                 case 1:
1179                         /* XXX compute */
1180                         break;
1181                 case 2:
1182                         /* XXX compute */
1183                         break;
1184                 }
1185                 break;
1186         }
1187
1188         return 0;
1189 }
1190
1191 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1192                                              struct amdgpu_irq_src *source,
1193                                              struct amdgpu_iv_entry *entry)
1194 {
1195         u8 instance_id;
1196
1197         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1198         instance_id = (entry->ring_id & 0x3) >> 0;
1199         drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1200         return 0;
1201 }
1202
1203 static int cik_sdma_set_clockgating_state(void *handle,
1204                                           enum amd_clockgating_state state)
1205 {
1206         bool gate = false;
1207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208
1209         if (state == AMD_CG_STATE_GATE)
1210                 gate = true;
1211
1212         cik_enable_sdma_mgcg(adev, gate);
1213         cik_enable_sdma_mgls(adev, gate);
1214
1215         return 0;
1216 }
1217
1218 static int cik_sdma_set_powergating_state(void *handle,
1219                                           enum amd_powergating_state state)
1220 {
1221         return 0;
1222 }
1223
1224 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1225         .name = "cik_sdma",
1226         .early_init = cik_sdma_early_init,
1227         .late_init = NULL,
1228         .sw_init = cik_sdma_sw_init,
1229         .sw_fini = cik_sdma_sw_fini,
1230         .hw_init = cik_sdma_hw_init,
1231         .hw_fini = cik_sdma_hw_fini,
1232         .suspend = cik_sdma_suspend,
1233         .resume = cik_sdma_resume,
1234         .is_idle = cik_sdma_is_idle,
1235         .wait_for_idle = cik_sdma_wait_for_idle,
1236         .soft_reset = cik_sdma_soft_reset,
1237         .set_clockgating_state = cik_sdma_set_clockgating_state,
1238         .set_powergating_state = cik_sdma_set_powergating_state,
1239 };
1240
1241 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1242         .type = AMDGPU_RING_TYPE_SDMA,
1243         .align_mask = 0xf,
1244         .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1245         .support_64bit_ptrs = false,
1246         .get_rptr = cik_sdma_ring_get_rptr,
1247         .get_wptr = cik_sdma_ring_get_wptr,
1248         .set_wptr = cik_sdma_ring_set_wptr,
1249         .emit_frame_size =
1250                 6 + /* cik_sdma_ring_emit_hdp_flush */
1251                 3 + /* hdp invalidate */
1252                 6 + /* cik_sdma_ring_emit_pipeline_sync */
1253                 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1254                 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1255         .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1256         .emit_ib = cik_sdma_ring_emit_ib,
1257         .emit_fence = cik_sdma_ring_emit_fence,
1258         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1259         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1260         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1261         .test_ring = cik_sdma_ring_test_ring,
1262         .test_ib = cik_sdma_ring_test_ib,
1263         .insert_nop = cik_sdma_ring_insert_nop,
1264         .pad_ib = cik_sdma_ring_pad_ib,
1265         .emit_wreg = cik_sdma_ring_emit_wreg,
1266 };
1267
1268 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1269 {
1270         int i;
1271
1272         for (i = 0; i < adev->sdma.num_instances; i++) {
1273                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1274                 adev->sdma.instance[i].ring.me = i;
1275         }
1276 }
1277
1278 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1279         .set = cik_sdma_set_trap_irq_state,
1280         .process = cik_sdma_process_trap_irq,
1281 };
1282
1283 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1284         .process = cik_sdma_process_illegal_inst_irq,
1285 };
1286
1287 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1288 {
1289         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1290         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1291         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1292 }
1293
1294 /**
1295  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1296  *
1297  * @ib: indirect buffer to copy to
1298  * @src_offset: src GPU address
1299  * @dst_offset: dst GPU address
1300  * @byte_count: number of bytes to xfer
1301  * @tmz: is this a secure operation
1302  *
1303  * Copy GPU buffers using the DMA engine (CIK).
1304  * Used by the amdgpu ttm implementation to move pages if
1305  * registered as the asic copy callback.
1306  */
1307 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1308                                       uint64_t src_offset,
1309                                       uint64_t dst_offset,
1310                                       uint32_t byte_count,
1311                                       bool tmz)
1312 {
1313         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1314         ib->ptr[ib->length_dw++] = byte_count;
1315         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1316         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1317         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1318         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1319         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1320 }
1321
1322 /**
1323  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1324  *
1325  * @ib: indirect buffer to fill
1326  * @src_data: value to write to buffer
1327  * @dst_offset: dst GPU address
1328  * @byte_count: number of bytes to xfer
1329  *
1330  * Fill GPU buffers using the DMA engine (CIK).
1331  */
1332 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1333                                       uint32_t src_data,
1334                                       uint64_t dst_offset,
1335                                       uint32_t byte_count)
1336 {
1337         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1338         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1339         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1340         ib->ptr[ib->length_dw++] = src_data;
1341         ib->ptr[ib->length_dw++] = byte_count;
1342 }
1343
1344 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1345         .copy_max_bytes = 0x1fffff,
1346         .copy_num_dw = 7,
1347         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1348
1349         .fill_max_bytes = 0x1fffff,
1350         .fill_num_dw = 5,
1351         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1352 };
1353
1354 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1355 {
1356         adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1357         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1358 }
1359
1360 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1361         .copy_pte_num_dw = 7,
1362         .copy_pte = cik_sdma_vm_copy_pte,
1363
1364         .write_pte = cik_sdma_vm_write_pte,
1365         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1366 };
1367
1368 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1369 {
1370         unsigned i;
1371
1372         adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1373         for (i = 0; i < adev->sdma.num_instances; i++) {
1374                 adev->vm_manager.vm_pte_scheds[i] =
1375                         &adev->sdma.instance[i].ring.sched;
1376         }
1377         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1378 }
1379
1380 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1381 {
1382         .type = AMD_IP_BLOCK_TYPE_SDMA,
1383         .major = 2,
1384         .minor = 0,
1385         .rev = 0,
1386         .funcs = &cik_sdma_ip_funcs,
1387 };