drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 union firmware_info {
  33         struct atom_firmware_info_v3_1 v31;
  34         struct atom_firmware_info_v3_2 v32;
  35         struct atom_firmware_info_v3_3 v33;
  36         struct atom_firmware_info_v3_4 v34;
  37 };
  38
  39 /*
  40  * Helper function to query firmware capability
  41  *
  42  * @adev: amdgpu_device pointer
  43  *
  44  * Return firmware_capability in firmwareinfo table on success or 0 if not
  45  */
  46 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_mode_info *mode_info = &adev->mode_info;
  49         int index;
  50         u16 data_offset, size;
  51         union firmware_info *firmware_info;
  52         u8 frev, crev;
  53         u32 fw_cap = 0;
  54
  55         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  56                         firmwareinfo);
  57
  58         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
  59                                 index, &size, &frev, &crev, &data_offset)) {
  60                 /* support firmware_info 3.1 + */
  61                 if ((frev == 3 && crev >=1) || (frev > 3)) {
  62                         firmware_info = (union firmware_info *)
  63                                 (mode_info->atom_context->bios + data_offset);
  64                         fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
  65                 }
  66         }
  67
  68         return fw_cap;
  69 }
  70
  71 /*
  72  * Helper function to query gpu virtualizaiton capability
  73  *
  74  * @adev: amdgpu_device pointer
  75  *
  76  * Return true if gpu virtualization is supported or false if not
  77  */
  78 bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
  79 {
  80         u32 fw_cap;
  81
  82         fw_cap = adev->mode_info.firmware_flags;
  83
  84         return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
  85 }
  86
  87 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  88 {
  89         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  90                                                 firmwareinfo);
  91         uint16_t data_offset;
  92
  93         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  94                                           NULL, NULL, &data_offset)) {
  95                 struct atom_firmware_info_v3_1 *firmware_info =
  96                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  97                                                            data_offset);
  98
  99                 adev->bios_scratch_reg_offset =
 100                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
 101         }
 102 }
 103
 104 static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
 105         struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes)
 106 {
 107         u32 start_addr, fw_size, drv_size;
 108
 109         start_addr = le32_to_cpu(fw_usage->start_address_in_kb);
 110         fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
 111         drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb);
 112
 113         DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
 114                           start_addr,
 115                           fw_size,
 116                           drv_size);
 117
 118         if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
 119                 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
 120                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
 121                 /* Firmware request VRAM reservation for SR-IOV */
 122                 adev->mman.fw_vram_usage_start_offset = (start_addr &
 123                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 124                 adev->mman.fw_vram_usage_size = fw_size << 10;
 125                 /* Use the default scratch size */
 126                 *usage_bytes = 0;
 127         } else {
 128                 *usage_bytes = drv_size << 10;
 129         }
 130         return 0;
 131 }
 132
 133 static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
 134                 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes)
 135 {
 136         u32 fw_start_addr, fw_size, drv_start_addr, drv_size;
 137
 138         fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb);
 139         fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
 140
 141         drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb);
 142         drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb);
 143
 144         DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n",
 145                           fw_start_addr,
 146                           fw_size,
 147                           drv_start_addr,
 148                           drv_size);
 149
 150         if (amdgpu_sriov_vf(adev) &&
 151             ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 152                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 153                 /* Firmware request VRAM reservation for SR-IOV */
 154                 adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
 155                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 156                 adev->mman.fw_vram_usage_size = fw_size << 10;
 157         }
 158
 159         if (amdgpu_sriov_vf(adev) &&
 160             ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 161                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 162                 /* driver request VRAM reservation for SR-IOV */
 163                 adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
 164                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 165                 adev->mman.drv_vram_usage_size = drv_size << 10;
 166         }
 167
 168         *usage_bytes = 0;
 169         return 0;
 170 }
 171
 172 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 173 {
 174         struct atom_context *ctx = adev->mode_info.atom_context;
 175         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 176                                                 vram_usagebyfirmware);
 177         struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1;
 178         struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2;
 179         u16 data_offset;
 180         u8 frev, crev;
 181         int usage_bytes = 0;
 182
 183         if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) {
 184                 if (frev == 2 && crev == 1) {
 185                         fw_usage_v2_1 =
 186                                 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
 187                         amdgpu_atomfirmware_allocate_fb_v2_1(adev,
 188                                         fw_usage_v2_1,
 189                                         &usage_bytes);
 190                 } else if (frev >= 2 && crev >= 2) {
 191                         fw_usage_v2_2 =
 192                                 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
 193                         amdgpu_atomfirmware_allocate_fb_v2_2(adev,
 194                                         fw_usage_v2_2,
 195                                         &usage_bytes);
 196                 }
 197         }
 198
 199         ctx->scratch_size_bytes = 0;
 200         if (usage_bytes == 0)
 201                 usage_bytes = 20 * 1024;
 202         /* allocate some scratch memory */
 203         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 204         if (!ctx->scratch)
 205                 return -ENOMEM;
 206         ctx->scratch_size_bytes = usage_bytes;
 207         return 0;
 208 }
 209
 210 union igp_info {
 211         struct atom_integrated_system_info_v1_11 v11;
 212         struct atom_integrated_system_info_v1_12 v12;
 213         struct atom_integrated_system_info_v2_1 v21;
 214 };
 215
 216 union umc_info {
 217         struct atom_umc_info_v3_1 v31;
 218         struct atom_umc_info_v3_2 v32;
 219         struct atom_umc_info_v3_3 v33;
 220 };
 221
 222 union vram_info {
 223         struct atom_vram_info_header_v2_3 v23;
 224         struct atom_vram_info_header_v2_4 v24;
 225         struct atom_vram_info_header_v2_5 v25;
 226         struct atom_vram_info_header_v2_6 v26;
 227         struct atom_vram_info_header_v3_0 v30;
 228 };
 229
 230 union vram_module {
 231         struct atom_vram_module_v9 v9;
 232         struct atom_vram_module_v10 v10;
 233         struct atom_vram_module_v11 v11;
 234         struct atom_vram_module_v3_0 v30;
 235 };
 236
 237 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 238                                               int atom_mem_type)
 239 {
 240         int vram_type;
 241
 242         if (adev->flags & AMD_IS_APU) {
 243                 switch (atom_mem_type) {
 244                 case Ddr2MemType:
 245                 case LpDdr2MemType:
 246                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 247                         break;
 248                 case Ddr3MemType:
 249                 case LpDdr3MemType:
 250                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 251                         break;
 252                 case Ddr4MemType:
 253                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 254                         break;
 255                 case LpDdr4MemType:
 256                         vram_type = AMDGPU_VRAM_TYPE_LPDDR4;
 257                         break;
 258                 case Ddr5MemType:
 259                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 260                         break;
 261                 case LpDdr5MemType:
 262                         vram_type = AMDGPU_VRAM_TYPE_LPDDR5;
 263                         break;
 264                 default:
 265                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 266                         break;
 267                 }
 268         } else {
 269                 switch (atom_mem_type) {
 270                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 271                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 272                         break;
 273                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 274                 case ATOM_DGPU_VRAM_TYPE_HBM2E:
 275                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 276                         break;
 277                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 278                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 279                         break;
 280                 default:
 281                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 282                         break;
 283                 }
 284         }
 285
 286         return vram_type;
 287 }
 288
 289
 290 int
 291 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 292                                   int *vram_width, int *vram_type,
 293                                   int *vram_vendor)
 294 {
 295         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 296         int index, i = 0;
 297         u16 data_offset, size;
 298         union igp_info *igp_info;
 299         union vram_info *vram_info;
 300         union vram_module *vram_module;
 301         u8 frev, crev;
 302         u8 mem_type;
 303         u8 mem_vendor;
 304         u32 mem_channel_number;
 305         u32 mem_channel_width;
 306         u32 module_id;
 307
 308         if (adev->flags & AMD_IS_APU)
 309                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 310                                                     integratedsysteminfo);
 311         else
 312                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 313                                                     vram_info);
 314
 315         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 316                                           index, &size,
 317                                           &frev, &crev, &data_offset)) {
 318                 if (adev->flags & AMD_IS_APU) {
 319                         igp_info = (union igp_info *)
 320                                 (mode_info->atom_context->bios + data_offset);
 321                         switch (frev) {
 322                         case 1:
 323                                 switch (crev) {
 324                                 case 11:
 325                                 case 12:
 326                                         mem_channel_number = igp_info->v11.umachannelnumber;
 327                                         if (!mem_channel_number)
 328                                                 mem_channel_number = 1;
 329                                         /* channel width is 64 */
 330                                         if (vram_width)
 331                                                 *vram_width = mem_channel_number * 64;
 332                                         mem_type = igp_info->v11.memorytype;
 333                                         if (vram_type)
 334                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 335                                         break;
 336                                 default:
 337                                         return -EINVAL;
 338                                 }
 339                                 break;
 340                         case 2:
 341                                 switch (crev) {
 342                                 case 1:
 343                                 case 2:
 344                                         mem_channel_number = igp_info->v21.umachannelnumber;
 345                                         if (!mem_channel_number)
 346                                                 mem_channel_number = 1;
 347                                         /* channel width is 64 */
 348                                         if (vram_width)
 349                                                 *vram_width = mem_channel_number * 64;
 350                                         mem_type = igp_info->v21.memorytype;
 351                                         if (vram_type)
 352                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 353                                         break;
 354                                 default:
 355                                         return -EINVAL;
 356                                 }
 357                                 break;
 358                         default:
 359                                 return -EINVAL;
 360                         }
 361                 } else {
 362                         vram_info = (union vram_info *)
 363                                 (mode_info->atom_context->bios + data_offset);
 364                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 365                         if (frev == 3) {
 366                                 switch (crev) {
 367                                 /* v30 */
 368                                 case 0:
 369                                         vram_module = (union vram_module *)vram_info->v30.vram_module;
 370                                         mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
 371                                         if (vram_vendor)
 372                                                 *vram_vendor = mem_vendor;
 373                                         mem_type = vram_info->v30.memory_type;
 374                                         if (vram_type)
 375                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 376                                         mem_channel_number = vram_info->v30.channel_num;
 377                                         mem_channel_width = vram_info->v30.channel_width;
 378                                         if (vram_width)
 379                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 380                                         break;
 381                                 default:
 382                                         return -EINVAL;
 383                                 }
 384                         } else if (frev == 2) {
 385                                 switch (crev) {
 386                                 /* v23 */
 387                                 case 3:
 388                                         if (module_id > vram_info->v23.vram_module_num)
 389                                                 module_id = 0;
 390                                         vram_module = (union vram_module *)vram_info->v23.vram_module;
 391                                         while (i < module_id) {
 392                                                 vram_module = (union vram_module *)
 393                                                         ((u8 *)vram_module + vram_module->v9.vram_module_size);
 394                                                 i++;
 395                                         }
 396                                         mem_type = vram_module->v9.memory_type;
 397                                         if (vram_type)
 398                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 399                                         mem_channel_number = vram_module->v9.channel_num;
 400                                         mem_channel_width = vram_module->v9.channel_width;
 401                                         if (vram_width)
 402                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 403                                         mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 404                                         if (vram_vendor)
 405                                                 *vram_vendor = mem_vendor;
 406                                         break;
 407                                 /* v24 */
 408                                 case 4:
 409                                         if (module_id > vram_info->v24.vram_module_num)
 410                                                 module_id = 0;
 411                                         vram_module = (union vram_module *)vram_info->v24.vram_module;
 412                                         while (i < module_id) {
 413                                                 vram_module = (union vram_module *)
 414                                                         ((u8 *)vram_module + vram_module->v10.vram_module_size);
 415                                                 i++;
 416                                         }
 417                                         mem_type = vram_module->v10.memory_type;
 418                                         if (vram_type)
 419                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 420                                         mem_channel_number = vram_module->v10.channel_num;
 421                                         mem_channel_width = vram_module->v10.channel_width;
 422                                         if (vram_width)
 423                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 424                                         mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 425                                         if (vram_vendor)
 426                                                 *vram_vendor = mem_vendor;
 427                                         break;
 428                                 /* v25 */
 429                                 case 5:
 430                                         if (module_id > vram_info->v25.vram_module_num)
 431                                                 module_id = 0;
 432                                         vram_module = (union vram_module *)vram_info->v25.vram_module;
 433                                         while (i < module_id) {
 434                                                 vram_module = (union vram_module *)
 435                                                         ((u8 *)vram_module + vram_module->v11.vram_module_size);
 436                                                 i++;
 437                                         }
 438                                         mem_type = vram_module->v11.memory_type;
 439                                         if (vram_type)
 440                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 441                                         mem_channel_number = vram_module->v11.channel_num;
 442                                         mem_channel_width = vram_module->v11.channel_width;
 443                                         if (vram_width)
 444                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 445                                         mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 446                                         if (vram_vendor)
 447                                                 *vram_vendor = mem_vendor;
 448                                         break;
 449                                 /* v26 */
 450                                 case 6:
 451                                         if (module_id > vram_info->v26.vram_module_num)
 452                                                 module_id = 0;
 453                                         vram_module = (union vram_module *)vram_info->v26.vram_module;
 454                                         while (i < module_id) {
 455                                                 vram_module = (union vram_module *)
 456                                                         ((u8 *)vram_module + vram_module->v9.vram_module_size);
 457                                                 i++;
 458                                         }
 459                                         mem_type = vram_module->v9.memory_type;
 460                                         if (vram_type)
 461                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 462                                         mem_channel_number = vram_module->v9.channel_num;
 463                                         mem_channel_width = vram_module->v9.channel_width;
 464                                         if (vram_width)
 465                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 466                                         mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 467                                         if (vram_vendor)
 468                                                 *vram_vendor = mem_vendor;
 469                                         break;
 470                                 default:
 471                                         return -EINVAL;
 472                                 }
 473                         } else {
 474                                 /* invalid frev */
 475                                 return -EINVAL;
 476                         }
 477                 }
 478
 479         }
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * Return true if vbios enabled ecc by default, if umc info table is available
 486  * or false if ecc is not enabled or umc info table is not available
 487  */
 488 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 489 {
 490         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 491         int index;
 492         u16 data_offset, size;
 493         union umc_info *umc_info;
 494         u8 frev, crev;
 495         bool ecc_default_enabled = false;
 496         u8 umc_config;
 497         u32 umc_config1;
 498
 499         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 500                         umc_info);
 501
 502         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 503                                 index, &size, &frev, &crev, &data_offset)) {
 504                 if (frev == 3) {
 505                         umc_info = (union umc_info *)
 506                                 (mode_info->atom_context->bios + data_offset);
 507                         switch (crev) {
 508                         case 1:
 509                                 umc_config = le32_to_cpu(umc_info->v31.umc_config);
 510                                 ecc_default_enabled =
 511                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 512                                 break;
 513                         case 2:
 514                                 umc_config = le32_to_cpu(umc_info->v32.umc_config);
 515                                 ecc_default_enabled =
 516                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 517                                 break;
 518                         case 3:
 519                                 umc_config = le32_to_cpu(umc_info->v33.umc_config);
 520                                 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
 521                                 ecc_default_enabled =
 522                                         ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
 523                                          (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
 524                                 break;
 525                         default:
 526                                 /* unsupported crev */
 527                                 return false;
 528                         }
 529                 }
 530         }
 531
 532         return ecc_default_enabled;
 533 }
 534
 535 /*
 536  * Helper function to query sram ecc capablity
 537  *
 538  * @adev: amdgpu_device pointer
 539  *
 540  * Return true if vbios supports sram ecc or false if not
 541  */
 542 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 543 {
 544         u32 fw_cap;
 545
 546         fw_cap = adev->mode_info.firmware_flags;
 547
 548         return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 549 }
 550
 551 /*
 552  * Helper function to query dynamic boot config capability
 553  *
 554  * @adev: amdgpu_device pointer
 555  *
 556  * Return true if vbios supports dynamic boot config or false if not
 557  */
 558 bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
 559 {
 560         u32 fw_cap;
 561
 562         fw_cap = adev->mode_info.firmware_flags;
 563
 564         return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
 565 }
 566
 567 /**
 568  * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
 569  * @adev: amdgpu_device pointer
 570  * @i2c_address: pointer to u8; if not NULL, will contain
 571  *    the RAS EEPROM address if the function returns true
 572  *
 573  * Return true if VBIOS supports RAS EEPROM address reporting,
 574  * else return false. If true and @i2c_address is not NULL,
 575  * will contain the RAS ROM address.
 576  */
 577 bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
 578                                       u8 *i2c_address)
 579 {
 580         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 581         int index;
 582         u16 data_offset, size;
 583         union firmware_info *firmware_info;
 584         u8 frev, crev;
 585
 586         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 587                                             firmwareinfo);
 588
 589         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 590                                           index, &size, &frev, &crev,
 591                                           &data_offset)) {
 592                 /* support firmware_info 3.4 + */
 593                 if ((frev == 3 && crev >=4) || (frev > 3)) {
 594                         firmware_info = (union firmware_info *)
 595                                 (mode_info->atom_context->bios + data_offset);
 596                         /* The ras_rom_i2c_slave_addr should ideally
 597                          * be a 19-bit EEPROM address, which would be
 598                          * used as is by the driver; see top of
 599                          * amdgpu_eeprom.c.
 600                          *
 601                          * When this is the case, 0 is of course a
 602                          * valid RAS EEPROM address, in which case,
 603                          * we'll drop the first "if (firm...)" and only
 604                          * leave the check for the pointer.
 605                          *
 606                          * The reason this works right now is because
 607                          * ras_rom_i2c_slave_addr contains the EEPROM
 608                          * device type qualifier 1010b in the top 4
 609                          * bits.
 610                          */
 611                         if (firmware_info->v34.ras_rom_i2c_slave_addr) {
 612                                 if (i2c_address)
 613                                         *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
 614                                 return true;
 615                         }
 616                 }
 617         }
 618
 619         return false;
 620 }
 621
 622
 623 union smu_info {
 624         struct atom_smu_info_v3_1 v31;
 625         struct atom_smu_info_v4_0 v40;
 626 };
 627
 628 union gfx_info {
 629         struct atom_gfx_info_v2_2 v22;
 630         struct atom_gfx_info_v2_4 v24;
 631         struct atom_gfx_info_v2_7 v27;
 632         struct atom_gfx_info_v3_0 v30;
 633 };
 634
 635 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 636 {
 637         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 638         struct amdgpu_pll *spll = &adev->clock.spll;
 639         struct amdgpu_pll *mpll = &adev->clock.mpll;
 640         uint8_t frev, crev;
 641         uint16_t data_offset;
 642         int ret = -EINVAL, index;
 643
 644         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 645                                             firmwareinfo);
 646         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 647                                    &frev, &crev, &data_offset)) {
 648                 union firmware_info *firmware_info =
 649                         (union firmware_info *)(mode_info->atom_context->bios +
 650                                                 data_offset);
 651
 652                 adev->clock.default_sclk =
 653                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 654                 adev->clock.default_mclk =
 655                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 656
 657                 adev->pm.current_sclk = adev->clock.default_sclk;
 658                 adev->pm.current_mclk = adev->clock.default_mclk;
 659
 660                 ret = 0;
 661         }
 662
 663         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 664                                             smu_info);
 665         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 666                                    &frev, &crev, &data_offset)) {
 667                 union smu_info *smu_info =
 668                         (union smu_info *)(mode_info->atom_context->bios +
 669                                            data_offset);
 670
 671                 /* system clock */
 672                 if (frev == 3)
 673                         spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 674                 else if (frev == 4)
 675                         spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
 676
 677                 spll->reference_div = 0;
 678                 spll->min_post_div = 1;
 679                 spll->max_post_div = 1;
 680                 spll->min_ref_div = 2;
 681                 spll->max_ref_div = 0xff;
 682                 spll->min_feedback_div = 4;
 683                 spll->max_feedback_div = 0xff;
 684                 spll->best_vco = 0;
 685
 686                 ret = 0;
 687         }
 688
 689         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 690                                             umc_info);
 691         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 692                                    &frev, &crev, &data_offset)) {
 693                 union umc_info *umc_info =
 694                         (union umc_info *)(mode_info->atom_context->bios +
 695                                            data_offset);
 696
 697                 /* memory clock */
 698                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 699
 700                 mpll->reference_div = 0;
 701                 mpll->min_post_div = 1;
 702                 mpll->max_post_div = 1;
 703                 mpll->min_ref_div = 2;
 704                 mpll->max_ref_div = 0xff;
 705                 mpll->min_feedback_div = 4;
 706                 mpll->max_feedback_div = 0xff;
 707                 mpll->best_vco = 0;
 708
 709                 ret = 0;
 710         }
 711
 712         /* if asic is Navi+, the rlc reference clock is used for system clock
 713          * from vbios gfx_info table */
 714         if (adev->asic_type >= CHIP_NAVI10) {
 715                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 716                                                    gfx_info);
 717                 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 718                                           &frev, &crev, &data_offset)) {
 719                         union gfx_info *gfx_info = (union gfx_info *)
 720                                 (mode_info->atom_context->bios + data_offset);
 721                         if ((frev == 3) ||
 722                             (frev == 2 && crev == 6)) {
 723                                 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
 724                                 ret = 0;
 725                         } else if ((frev == 2) &&
 726                                    (crev >= 2) &&
 727                                    (crev != 6)) {
 728                                 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
 729                                 ret = 0;
 730                         } else {
 731                                 BUG();
 732                         }
 733                 }
 734         }
 735
 736         return ret;
 737 }
 738
 739 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 740 {
 741         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 742         int index;
 743         uint8_t frev, crev;
 744         uint16_t data_offset;
 745
 746         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 747                                             gfx_info);
 748         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 749                                    &frev, &crev, &data_offset)) {
 750                 union gfx_info *gfx_info = (union gfx_info *)
 751                         (mode_info->atom_context->bios + data_offset);
 752                 if (frev == 2) {
 753                         switch (crev) {
 754                         case 4:
 755                                 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 756                                 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 757                                 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 758                                 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 759                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 760                                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 761                                 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 762                                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 763                                 adev->gfx.config.gs_prim_buffer_depth =
 764                                         le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 765                                 adev->gfx.config.double_offchip_lds_buf =
 766                                         gfx_info->v24.gc_double_offchip_lds_buffer;
 767                                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 768                                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 769                                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 770                                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 771                                 return 0;
 772                         case 7:
 773                                 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
 774                                 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
 775                                 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
 776                                 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
 777                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
 778                                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
 779                                 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
 780                                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
 781                                 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
 782                                 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
 783                                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
 784                                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
 785                                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
 786                                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
 787                                 return 0;
 788                         default:
 789                                 return -EINVAL;
 790                         }
 791                 } else if (frev == 3) {
 792                         switch (crev) {
 793                         case 0:
 794                                 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
 795                                 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
 796                                 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
 797                                 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
 798                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
 799                                 return 0;
 800                         default:
 801                                 return -EINVAL;
 802                         }
 803                 } else {
 804                         return -EINVAL;
 805                 }
 806
 807         }
 808         return -EINVAL;
 809 }
 810
 811 /*
 812  * Helper function to query two stage mem training capability
 813  *
 814  * @adev: amdgpu_device pointer
 815  *
 816  * Return true if two stage mem training is supported or false if not
 817  */
 818 bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
 819 {
 820         u32 fw_cap;
 821
 822         fw_cap = adev->mode_info.firmware_flags;
 823
 824         return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
 825 }
 826
 827 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 828 {
 829         struct atom_context *ctx = adev->mode_info.atom_context;
 830         union firmware_info *firmware_info;
 831         int index;
 832         u16 data_offset, size;
 833         u8 frev, crev;
 834         int fw_reserved_fb_size;
 835
 836         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 837                         firmwareinfo);
 838
 839         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 840                                 &frev, &crev, &data_offset))
 841                 /* fail to parse data_header */
 842                 return 0;
 843
 844         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 845
 846         if (frev !=3)
 847                 return -EINVAL;
 848
 849         switch (crev) {
 850         case 4:
 851                 fw_reserved_fb_size =
 852                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 853                 break;
 854         default:
 855                 fw_reserved_fb_size = 0;
 856                 break;
 857         }
 858
 859         return fw_reserved_fb_size;
 860 }
 861
 862 /*
 863  * Helper function to execute asic_init table
 864  *
 865  * @adev: amdgpu_device pointer
 866  * @fb_reset: flag to indicate whether fb is reset or not
 867  *
 868  * Return 0 if succeed, otherwise failed
 869  */
 870 int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
 871 {
 872         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 873         struct atom_context *ctx;
 874         uint8_t frev, crev;
 875         uint16_t data_offset;
 876         uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;
 877         struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;
 878         int index;
 879
 880         if (!mode_info)
 881                 return -EINVAL;
 882
 883         ctx = mode_info->atom_context;
 884         if (!ctx)
 885                 return -EINVAL;
 886
 887         /* query bootup sclk/mclk from firmware_info table */
 888         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 889                                             firmwareinfo);
 890         if (amdgpu_atom_parse_data_header(ctx, index, NULL,
 891                                 &frev, &crev, &data_offset)) {
 892                 union firmware_info *firmware_info =
 893                         (union firmware_info *)(ctx->bios +
 894                                                 data_offset);
 895
 896                 bootup_sclk_in10khz =
 897                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 898                 bootup_mclk_in10khz =
 899                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 900         } else {
 901                 return -EINVAL;
 902         }
 903
 904         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 905                                             asic_init);
 906         if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
 907                 if (frev == 2 && crev >= 1) {
 908                         memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));
 909                         asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;
 910                         asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;
 911                         asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;
 912                         if (!fb_reset)
 913                                 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;
 914                         else
 915                                 asic_init_ps_v2_1.param.memparam.memflag = 0;
 916                 } else {
 917                         return -EINVAL;
 918                 }
 919         } else {
 920                 return -EINVAL;
 921         }
 922
 923         return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1);
 924 }