drivers/gpu/drm/i915/intel_engine_cs.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_print.h>
  26
  27 #include "i915_drv.h"
  28 #include "intel_ringbuffer.h"
  29 #include "intel_lrc.h"
  30
  31 /* Haswell does have the CXT_SIZE register however it does not appear to be
  32  * valid. Now, docs explain in dwords what is in the context object. The full
  33  * size is 70720 bytes, however, the power context and execlist context will
  34  * never be saved (power context is stored elsewhere, and execlists don't work
  35  * on HSW) - so the final size, including the extra state required for the
  36  * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
  37  */
  38 #define HSW_CXT_TOTAL_SIZE              (17 * PAGE_SIZE)
  39
  40 #define DEFAULT_LR_CONTEXT_RENDER_SIZE  (22 * PAGE_SIZE)
  41 #define GEN8_LR_CONTEXT_RENDER_SIZE     (20 * PAGE_SIZE)
  42 #define GEN9_LR_CONTEXT_RENDER_SIZE     (22 * PAGE_SIZE)
  43 #define GEN10_LR_CONTEXT_RENDER_SIZE    (18 * PAGE_SIZE)
  44 #define GEN11_LR_CONTEXT_RENDER_SIZE    (14 * PAGE_SIZE)
  45
  46 #define GEN8_LR_CONTEXT_OTHER_SIZE      ( 2 * PAGE_SIZE)
  47
  48 struct engine_class_info {
  49         const char *name;
  50         int (*init_legacy)(struct intel_engine_cs *engine);
  51         int (*init_execlists)(struct intel_engine_cs *engine);
  52
  53         u8 uabi_class;
  54 };
  55
  56 static const struct engine_class_info intel_engine_classes[] = {
  57         [RENDER_CLASS] = {
  58                 .name = "rcs",
  59                 .init_execlists = logical_render_ring_init,
  60                 .init_legacy = intel_init_render_ring_buffer,
  61                 .uabi_class = I915_ENGINE_CLASS_RENDER,
  62         },
  63         [COPY_ENGINE_CLASS] = {
  64                 .name = "bcs",
  65                 .init_execlists = logical_xcs_ring_init,
  66                 .init_legacy = intel_init_blt_ring_buffer,
  67                 .uabi_class = I915_ENGINE_CLASS_COPY,
  68         },
  69         [VIDEO_DECODE_CLASS] = {
  70                 .name = "vcs",
  71                 .init_execlists = logical_xcs_ring_init,
  72                 .init_legacy = intel_init_bsd_ring_buffer,
  73                 .uabi_class = I915_ENGINE_CLASS_VIDEO,
  74         },
  75         [VIDEO_ENHANCEMENT_CLASS] = {
  76                 .name = "vecs",
  77                 .init_execlists = logical_xcs_ring_init,
  78                 .init_legacy = intel_init_vebox_ring_buffer,
  79                 .uabi_class = I915_ENGINE_CLASS_VIDEO_ENHANCE,
  80         },
  81 };
  82
  83 #define MAX_MMIO_BASES 3
  84 struct engine_info {
  85         unsigned int hw_id;
  86         unsigned int uabi_id;
  87         u8 class;
  88         u8 instance;
  89         /* mmio bases table *must* be sorted in reverse gen order */
  90         struct engine_mmio_base {
  91                 u32 gen : 8;
  92                 u32 base : 24;
  93         } mmio_bases[MAX_MMIO_BASES];
  94 };
  95
  96 static const struct engine_info intel_engines[] = {
  97         [RCS] = {
  98                 .hw_id = RCS_HW,
  99                 .uabi_id = I915_EXEC_RENDER,
 100                 .class = RENDER_CLASS,
 101                 .instance = 0,
 102                 .mmio_bases = {
 103                         { .gen = 1, .base = RENDER_RING_BASE }
 104                 },
 105         },
 106         [BCS] = {
 107                 .hw_id = BCS_HW,
 108                 .uabi_id = I915_EXEC_BLT,
 109                 .class = COPY_ENGINE_CLASS,
 110                 .instance = 0,
 111                 .mmio_bases = {
 112                         { .gen = 6, .base = BLT_RING_BASE }
 113                 },
 114         },
 115         [VCS] = {
 116                 .hw_id = VCS_HW,
 117                 .uabi_id = I915_EXEC_BSD,
 118                 .class = VIDEO_DECODE_CLASS,
 119                 .instance = 0,
 120                 .mmio_bases = {
 121                         { .gen = 11, .base = GEN11_BSD_RING_BASE },
 122                         { .gen = 6, .base = GEN6_BSD_RING_BASE },
 123                         { .gen = 4, .base = BSD_RING_BASE }
 124                 },
 125         },
 126         [VCS2] = {
 127                 .hw_id = VCS2_HW,
 128                 .uabi_id = I915_EXEC_BSD,
 129                 .class = VIDEO_DECODE_CLASS,
 130                 .instance = 1,
 131                 .mmio_bases = {
 132                         { .gen = 11, .base = GEN11_BSD2_RING_BASE },
 133                         { .gen = 8, .base = GEN8_BSD2_RING_BASE }
 134                 },
 135         },
 136         [VCS3] = {
 137                 .hw_id = VCS3_HW,
 138                 .uabi_id = I915_EXEC_BSD,
 139                 .class = VIDEO_DECODE_CLASS,
 140                 .instance = 2,
 141                 .mmio_bases = {
 142                         { .gen = 11, .base = GEN11_BSD3_RING_BASE }
 143                 },
 144         },
 145         [VCS4] = {
 146                 .hw_id = VCS4_HW,
 147                 .uabi_id = I915_EXEC_BSD,
 148                 .class = VIDEO_DECODE_CLASS,
 149                 .instance = 3,
 150                 .mmio_bases = {
 151                         { .gen = 11, .base = GEN11_BSD4_RING_BASE }
 152                 },
 153         },
 154         [VECS] = {
 155                 .hw_id = VECS_HW,
 156                 .uabi_id = I915_EXEC_VEBOX,
 157                 .class = VIDEO_ENHANCEMENT_CLASS,
 158                 .instance = 0,
 159                 .mmio_bases = {
 160                         { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
 161                         { .gen = 7, .base = VEBOX_RING_BASE }
 162                 },
 163         },
 164         [VECS2] = {
 165                 .hw_id = VECS2_HW,
 166                 .uabi_id = I915_EXEC_VEBOX,
 167                 .class = VIDEO_ENHANCEMENT_CLASS,
 168                 .instance = 1,
 169                 .mmio_bases = {
 170                         { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
 171                 },
 172         },
 173 };
 174
 175 /**
 176  * ___intel_engine_context_size() - return the size of the context for an engine
 177  * @dev_priv: i915 device private
 178  * @class: engine class
 179  *
 180  * Each engine class may require a different amount of space for a context
 181  * image.
 182  *
 183  * Return: size (in bytes) of an engine class specific context image
 184  *
 185  * Note: this size includes the HWSP, which is part of the context image
 186  * in LRC mode, but does not include the "shared data page" used with
 187  * GuC submission. The caller should account for this if using the GuC.
 188  */
 189 static u32
 190 __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
 191 {
 192         u32 cxt_size;
 193
 194         BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
 195
 196         switch (class) {
 197         case RENDER_CLASS:
 198                 switch (INTEL_GEN(dev_priv)) {
 199                 default:
 200                         MISSING_CASE(INTEL_GEN(dev_priv));
 201                         return DEFAULT_LR_CONTEXT_RENDER_SIZE;
 202                 case 11:
 203                         return GEN11_LR_CONTEXT_RENDER_SIZE;
 204                 case 10:
 205                         return GEN10_LR_CONTEXT_RENDER_SIZE;
 206                 case 9:
 207                         return GEN9_LR_CONTEXT_RENDER_SIZE;
 208                 case 8:
 209                         return GEN8_LR_CONTEXT_RENDER_SIZE;
 210                 case 7:
 211                         if (IS_HASWELL(dev_priv))
 212                                 return HSW_CXT_TOTAL_SIZE;
 213
 214                         cxt_size = I915_READ(GEN7_CXT_SIZE);
 215                         return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
 216                                         PAGE_SIZE);
 217                 case 6:
 218                         cxt_size = I915_READ(CXT_SIZE);
 219                         return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
 220                                         PAGE_SIZE);
 221                 case 5:
 222                 case 4:
 223                 case 3:
 224                 case 2:
 225                 /* For the special day when i810 gets merged. */
 226                 case 1:
 227                         return 0;
 228                 }
 229                 break;
 230         default:
 231                 MISSING_CASE(class);
 232                 /* fall through */
 233         case VIDEO_DECODE_CLASS:
 234         case VIDEO_ENHANCEMENT_CLASS:
 235         case COPY_ENGINE_CLASS:
 236                 if (INTEL_GEN(dev_priv) < 8)
 237                         return 0;
 238                 return GEN8_LR_CONTEXT_OTHER_SIZE;
 239         }
 240 }
 241
 242 static u32 __engine_mmio_base(struct drm_i915_private *i915,
 243                               const struct engine_mmio_base *bases)
 244 {
 245         int i;
 246
 247         for (i = 0; i < MAX_MMIO_BASES; i++)
 248                 if (INTEL_GEN(i915) >= bases[i].gen)
 249                         break;
 250
 251         GEM_BUG_ON(i == MAX_MMIO_BASES);
 252         GEM_BUG_ON(!bases[i].base);
 253
 254         return bases[i].base;
 255 }
 256
 257 static void __sprint_engine_name(char *name, const struct engine_info *info)
 258 {
 259         WARN_ON(snprintf(name, INTEL_ENGINE_CS_MAX_NAME, "%s%u",
 260                          intel_engine_classes[info->class].name,
 261                          info->instance) >= INTEL_ENGINE_CS_MAX_NAME);
 262 }
 263
 264 static int
 265 intel_engine_setup(struct drm_i915_private *dev_priv,
 266                    enum intel_engine_id id)
 267 {
 268         const struct engine_info *info = &intel_engines[id];
 269         struct intel_engine_cs *engine;
 270
 271         GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));
 272
 273         BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
 274         BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
 275
 276         if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
 277                 return -EINVAL;
 278
 279         if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
 280                 return -EINVAL;
 281
 282         if (GEM_DEBUG_WARN_ON(dev_priv->engine_class[info->class][info->instance]))
 283                 return -EINVAL;
 284
 285         GEM_BUG_ON(dev_priv->engine[id]);
 286         engine = kzalloc(sizeof(*engine), GFP_KERNEL);
 287         if (!engine)
 288                 return -ENOMEM;
 289
 290         engine->id = id;
 291         engine->i915 = dev_priv;
 292         __sprint_engine_name(engine->name, info);
 293         engine->hw_id = engine->guc_id = info->hw_id;
 294         engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases);
 295         engine->class = info->class;
 296         engine->instance = info->instance;
 297
 298         engine->uabi_id = info->uabi_id;
 299         engine->uabi_class = intel_engine_classes[info->class].uabi_class;
 300
 301         engine->context_size = __intel_engine_context_size(dev_priv,
 302                                                            engine->class);
 303         if (WARN_ON(engine->context_size > BIT(20)))
 304                 engine->context_size = 0;
 305         if (engine->context_size)
 306                 DRIVER_CAPS(dev_priv)->has_logical_contexts = true;
 307
 308         /* Nothing to do here, execute in order of dependencies */
 309         engine->schedule = NULL;
 310
 311         seqlock_init(&engine->stats.lock);
 312
 313         ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
 314
 315         dev_priv->engine_class[info->class][info->instance] = engine;
 316         dev_priv->engine[id] = engine;
 317         return 0;
 318 }
 319
 320 /**
 321  * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
 322  * @dev_priv: i915 device private
 323  *
 324  * Return: non-zero if the initialization failed.
 325  */
 326 int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
 327 {
 328         struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
 329         const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
 330         struct intel_engine_cs *engine;
 331         enum intel_engine_id id;
 332         unsigned int mask = 0;
 333         unsigned int i;
 334         int err;
 335
 336         WARN_ON(ring_mask == 0);
 337         WARN_ON(ring_mask &
 338                 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
 339
 340         if (i915_inject_load_failure())
 341                 return -ENODEV;
 342
 343         for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
 344                 if (!HAS_ENGINE(dev_priv, i))
 345                         continue;
 346
 347                 err = intel_engine_setup(dev_priv, i);
 348                 if (err)
 349                         goto cleanup;
 350
 351                 mask |= ENGINE_MASK(i);
 352         }
 353
 354         /*
 355          * Catch failures to update intel_engines table when the new engines
 356          * are added to the driver by a warning and disabling the forgotten
 357          * engines.
 358          */
 359         if (WARN_ON(mask != ring_mask))
 360                 device_info->ring_mask = mask;
 361
 362         /* We always presume we have at least RCS available for later probing */
 363         if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) {
 364                 err = -ENODEV;
 365                 goto cleanup;
 366         }
 367
 368         device_info->num_rings = hweight32(mask);
 369
 370         i915_check_and_clear_faults(dev_priv);
 371
 372         return 0;
 373
 374 cleanup:
 375         for_each_engine(engine, dev_priv, id)
 376                 kfree(engine);
 377         return err;
 378 }
 379
 380 /**
 381  * intel_engines_init() - init the Engine Command Streamers
 382  * @dev_priv: i915 device private
 383  *
 384  * Return: non-zero if the initialization failed.
 385  */
 386 int intel_engines_init(struct drm_i915_private *dev_priv)
 387 {
 388         struct intel_engine_cs *engine;
 389         enum intel_engine_id id, err_id;
 390         int err;
 391
 392         for_each_engine(engine, dev_priv, id) {
 393                 const struct engine_class_info *class_info =
 394                         &intel_engine_classes[engine->class];
 395                 int (*init)(struct intel_engine_cs *engine);
 396
 397                 if (HAS_EXECLISTS(dev_priv))
 398                         init = class_info->init_execlists;
 399                 else
 400                         init = class_info->init_legacy;
 401
 402                 err = -EINVAL;
 403                 err_id = id;
 404
 405                 if (GEM_DEBUG_WARN_ON(!init))
 406                         goto cleanup;
 407
 408                 err = init(engine);
 409                 if (err)
 410                         goto cleanup;
 411
 412                 GEM_BUG_ON(!engine->submit_request);
 413         }
 414
 415         return 0;
 416
 417 cleanup:
 418         for_each_engine(engine, dev_priv, id) {
 419                 if (id >= err_id) {
 420                         kfree(engine);
 421                         dev_priv->engine[id] = NULL;
 422                 } else {
 423                         dev_priv->gt.cleanup_engine(engine);
 424                 }
 425         }
 426         return err;
 427 }
 428
 429 void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
 430 {
 431         struct drm_i915_private *dev_priv = engine->i915;
 432
 433         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
 434          * so long as the semaphore value in the register/page is greater
 435          * than the sync value), so whenever we reset the seqno,
 436          * so long as we reset the tracking semaphore value to 0, it will
 437          * always be before the next request's seqno. If we don't reset
 438          * the semaphore value, then when the seqno moves backwards all
 439          * future waits will complete instantly (causing rendering corruption).
 440          */
 441         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
 442                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
 443                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
 444                 if (HAS_VEBOX(dev_priv))
 445                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
 446         }
 447
 448         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
 449         clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
 450
 451         /* After manually advancing the seqno, fake the interrupt in case
 452          * there are any waiters for that seqno.
 453          */
 454         intel_engine_wakeup(engine);
 455
 456         GEM_BUG_ON(intel_engine_get_seqno(engine) != seqno);
 457 }
 458
 459 static void intel_engine_init_batch_pool(struct intel_engine_cs *engine)
 460 {
 461         i915_gem_batch_pool_init(&engine->batch_pool, engine);
 462 }
 463
 464 static void intel_engine_init_execlist(struct intel_engine_cs *engine)
 465 {
 466         struct intel_engine_execlists * const execlists = &engine->execlists;
 467
 468         execlists->port_mask = 1;
 469         GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
 470         GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
 471
 472         execlists->queue_priority = INT_MIN;
 473         execlists->queue = RB_ROOT_CACHED;
 474 }
 475
 476 /**
 477  * intel_engines_setup_common - setup engine state not requiring hw access
 478  * @engine: Engine to setup.
 479  *
 480  * Initializes @engine@ structure members shared between legacy and execlists
 481  * submission modes which do not require hardware access.
 482  *
 483  * Typically done early in the submission mode specific engine setup stage.
 484  */
 485 void intel_engine_setup_common(struct intel_engine_cs *engine)
 486 {
 487         i915_timeline_init(engine->i915, &engine->timeline, engine->name);
 488         i915_timeline_set_subclass(&engine->timeline, TIMELINE_ENGINE);
 489
 490         intel_engine_init_execlist(engine);
 491         intel_engine_init_hangcheck(engine);
 492         intel_engine_init_batch_pool(engine);
 493         intel_engine_init_cmd_parser(engine);
 494 }
 495
 496 static void cleanup_status_page(struct intel_engine_cs *engine)
 497 {
 498         if (HWS_NEEDS_PHYSICAL(engine->i915)) {
 499                 void *addr = fetch_and_zero(&engine->status_page.page_addr);
 500
 501                 __free_page(virt_to_page(addr));
 502         }
 503
 504         i915_vma_unpin_and_release(&engine->status_page.vma,
 505                                    I915_VMA_RELEASE_MAP);
 506 }
 507
 508 static int init_status_page(struct intel_engine_cs *engine)
 509 {
 510         struct drm_i915_gem_object *obj;
 511         struct i915_vma *vma;
 512         unsigned int flags;
 513         void *vaddr;
 514         int ret;
 515
 516         obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
 517         if (IS_ERR(obj)) {
 518                 DRM_ERROR("Failed to allocate status page\n");
 519                 return PTR_ERR(obj);
 520         }
 521
 522         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 523         if (ret)
 524                 goto err;
 525
 526         vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
 527         if (IS_ERR(vma)) {
 528                 ret = PTR_ERR(vma);
 529                 goto err;
 530         }
 531
 532         flags = PIN_GLOBAL;
 533         if (!HAS_LLC(engine->i915))
 534                 /* On g33, we cannot place HWS above 256MiB, so
 535                  * restrict its pinning to the low mappable arena.
 536                  * Though this restriction is not documented for
 537                  * gen4, gen5, or byt, they also behave similarly
 538                  * and hang if the HWS is placed at the top of the
 539                  * GTT. To generalise, it appears that all !llc
 540                  * platforms have issues with us placing the HWS
 541                  * above the mappable region (even though we never
 542                  * actually map it).
 543                  */
 544                 flags |= PIN_MAPPABLE;
 545         else
 546                 flags |= PIN_HIGH;
 547         ret = i915_vma_pin(vma, 0, 0, flags);
 548         if (ret)
 549                 goto err;
 550
 551         vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
 552         if (IS_ERR(vaddr)) {
 553                 ret = PTR_ERR(vaddr);
 554                 goto err_unpin;
 555         }
 556
 557         engine->status_page.vma = vma;
 558         engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
 559         engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
 560         return 0;
 561
 562 err_unpin:
 563         i915_vma_unpin(vma);
 564 err:
 565         i915_gem_object_put(obj);
 566         return ret;
 567 }
 568
 569 static int init_phys_status_page(struct intel_engine_cs *engine)
 570 {
 571         struct page *page;
 572
 573         /*
 574          * Though the HWS register does support 36bit addresses, historically
 575          * we have had hangs and corruption reported due to wild writes if
 576          * the HWS is placed above 4G.
 577          */
 578         page = alloc_page(GFP_KERNEL | __GFP_DMA32 | __GFP_ZERO);
 579         if (!page)
 580                 return -ENOMEM;
 581
 582         engine->status_page.page_addr = page_address(page);
 583
 584         return 0;
 585 }
 586
 587 static void __intel_context_unpin(struct i915_gem_context *ctx,
 588                                   struct intel_engine_cs *engine)
 589 {
 590         intel_context_unpin(to_intel_context(ctx, engine));
 591 }
 592
 593 /**
 594  * intel_engines_init_common - initialize cengine state which might require hw access
 595  * @engine: Engine to initialize.
 596  *
 597  * Initializes @engine@ structure members shared between legacy and execlists
 598  * submission modes which do require hardware access.
 599  *
 600  * Typcally done at later stages of submission mode specific engine setup.
 601  *
 602  * Returns zero on success or an error code on failure.
 603  */
 604 int intel_engine_init_common(struct intel_engine_cs *engine)
 605 {
 606         struct drm_i915_private *i915 = engine->i915;
 607         struct intel_context *ce;
 608         int ret;
 609
 610         engine->set_default_submission(engine);
 611
 612         /* We may need to do things with the shrinker which
 613          * require us to immediately switch back to the default
 614          * context. This can cause a problem as pinning the
 615          * default context also requires GTT space which may not
 616          * be available. To avoid this we always pin the default
 617          * context.
 618          */
 619         ce = intel_context_pin(i915->kernel_context, engine);
 620         if (IS_ERR(ce))
 621                 return PTR_ERR(ce);
 622
 623         /*
 624          * Similarly the preempt context must always be available so that
 625          * we can interrupt the engine at any time.
 626          */
 627         if (i915->preempt_context) {
 628                 ce = intel_context_pin(i915->preempt_context, engine);
 629                 if (IS_ERR(ce)) {
 630                         ret = PTR_ERR(ce);
 631                         goto err_unpin_kernel;
 632                 }
 633         }
 634
 635         ret = intel_engine_init_breadcrumbs(engine);
 636         if (ret)
 637                 goto err_unpin_preempt;
 638
 639         if (HWS_NEEDS_PHYSICAL(i915))
 640                 ret = init_phys_status_page(engine);
 641         else
 642                 ret = init_status_page(engine);
 643         if (ret)
 644                 goto err_breadcrumbs;
 645
 646         return 0;
 647
 648 err_breadcrumbs:
 649         intel_engine_fini_breadcrumbs(engine);
 650 err_unpin_preempt:
 651         if (i915->preempt_context)
 652                 __intel_context_unpin(i915->preempt_context, engine);
 653
 654 err_unpin_kernel:
 655         __intel_context_unpin(i915->kernel_context, engine);
 656         return ret;
 657 }
 658
 659 /**
 660  * intel_engines_cleanup_common - cleans up the engine state created by
 661  *                                the common initiailizers.
 662  * @engine: Engine to cleanup.
 663  *
 664  * This cleans up everything created by the common helpers.
 665  */
 666 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 667 {
 668         struct drm_i915_private *i915 = engine->i915;
 669
 670         cleanup_status_page(engine);
 671
 672         intel_engine_fini_breadcrumbs(engine);
 673         intel_engine_cleanup_cmd_parser(engine);
 674         i915_gem_batch_pool_fini(&engine->batch_pool);
 675
 676         if (engine->default_state)
 677                 i915_gem_object_put(engine->default_state);
 678
 679         if (i915->preempt_context)
 680                 __intel_context_unpin(i915->preempt_context, engine);
 681         __intel_context_unpin(i915->kernel_context, engine);
 682
 683         i915_timeline_fini(&engine->timeline);
 684
 685         intel_wa_list_free(&engine->ctx_wa_list);
 686         intel_wa_list_free(&engine->wa_list);
 687         intel_wa_list_free(&engine->whitelist);
 688 }
 689
 690 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
 691 {
 692         struct drm_i915_private *dev_priv = engine->i915;
 693         u64 acthd;
 694
 695         if (INTEL_GEN(dev_priv) >= 8)
 696                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 697                                          RING_ACTHD_UDW(engine->mmio_base));
 698         else if (INTEL_GEN(dev_priv) >= 4)
 699                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 700         else
 701                 acthd = I915_READ(ACTHD);
 702
 703         return acthd;
 704 }
 705
 706 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
 707 {
 708         struct drm_i915_private *dev_priv = engine->i915;
 709         u64 bbaddr;
 710
 711         if (INTEL_GEN(dev_priv) >= 8)
 712                 bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
 713                                           RING_BBADDR_UDW(engine->mmio_base));
 714         else
 715                 bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
 716
 717         return bbaddr;
 718 }
 719
 720 int intel_engine_stop_cs(struct intel_engine_cs *engine)
 721 {
 722         struct drm_i915_private *dev_priv = engine->i915;
 723         const u32 base = engine->mmio_base;
 724         const i915_reg_t mode = RING_MI_MODE(base);
 725         int err;
 726
 727         if (INTEL_GEN(dev_priv) < 3)
 728                 return -ENODEV;
 729
 730         GEM_TRACE("%s\n", engine->name);
 731
 732         I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
 733
 734         err = 0;
 735         if (__intel_wait_for_register_fw(dev_priv,
 736                                          mode, MODE_IDLE, MODE_IDLE,
 737                                          1000, 0,
 738                                          NULL)) {
 739                 GEM_TRACE("%s: timed out on STOP_RING -> IDLE\n", engine->name);
 740                 err = -ETIMEDOUT;
 741         }
 742
 743         /* A final mmio read to let GPU writes be hopefully flushed to memory */
 744         POSTING_READ_FW(mode);
 745
 746         return err;
 747 }
 748
 749 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
 750 {
 751         struct drm_i915_private *dev_priv = engine->i915;
 752
 753         GEM_TRACE("%s\n", engine->name);
 754
 755         I915_WRITE_FW(RING_MI_MODE(engine->mmio_base),
 756                       _MASKED_BIT_DISABLE(STOP_RING));
 757 }
 758
 759 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 760 {
 761         switch (type) {
 762         case I915_CACHE_NONE: return " uncached";
 763         case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
 764         case I915_CACHE_L3_LLC: return " L3+LLC";
 765         case I915_CACHE_WT: return " WT";
 766         default: return "";
 767         }
 768 }
 769
 770 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
 771 {
 772         const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
 773         u32 mcr_s_ss_select;
 774         u32 slice = fls(sseu->slice_mask);
 775         u32 subslice = fls(sseu->subslice_mask[slice]);
 776
 777         if (IS_GEN10(dev_priv))
 778                 mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
 779                                   GEN8_MCR_SUBSLICE(subslice);
 780         else if (INTEL_GEN(dev_priv) >= 11)
 781                 mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
 782                                   GEN11_MCR_SUBSLICE(subslice);
 783         else
 784                 mcr_s_ss_select = 0;
 785
 786         return mcr_s_ss_select;
 787 }
 788
 789 static inline uint32_t
 790 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 791                   int subslice, i915_reg_t reg)
 792 {
 793         uint32_t mcr_slice_subslice_mask;
 794         uint32_t mcr_slice_subslice_select;
 795         uint32_t default_mcr_s_ss_select;
 796         uint32_t mcr;
 797         uint32_t ret;
 798         enum forcewake_domains fw_domains;
 799
 800         if (INTEL_GEN(dev_priv) >= 11) {
 801                 mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
 802                                           GEN11_MCR_SUBSLICE_MASK;
 803                 mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
 804                                             GEN11_MCR_SUBSLICE(subslice);
 805         } else {
 806                 mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
 807                                           GEN8_MCR_SUBSLICE_MASK;
 808                 mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
 809                                             GEN8_MCR_SUBSLICE(subslice);
 810         }
 811
 812         default_mcr_s_ss_select = intel_calculate_mcr_s_ss_select(dev_priv);
 813
 814         fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
 815                                                     FW_REG_READ);
 816         fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
 817                                                      GEN8_MCR_SELECTOR,
 818                                                      FW_REG_READ | FW_REG_WRITE);
 819
 820         spin_lock_irq(&dev_priv->uncore.lock);
 821         intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 822
 823         mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
 824
 825         WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
 826                      default_mcr_s_ss_select);
 827
 828         mcr &= ~mcr_slice_subslice_mask;
 829         mcr |= mcr_slice_subslice_select;
 830         I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 831
 832         ret = I915_READ_FW(reg);
 833
 834         mcr &= ~mcr_slice_subslice_mask;
 835         mcr |= default_mcr_s_ss_select;
 836
 837         I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 838
 839         intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
 840         spin_unlock_irq(&dev_priv->uncore.lock);
 841
 842         return ret;
 843 }
 844
 845 /* NB: please notice the memset */
 846 void intel_engine_get_instdone(struct intel_engine_cs *engine,
 847                                struct intel_instdone *instdone)
 848 {
 849         struct drm_i915_private *dev_priv = engine->i915;
 850         u32 mmio_base = engine->mmio_base;
 851         int slice;
 852         int subslice;
 853
 854         memset(instdone, 0, sizeof(*instdone));
 855
 856         switch (INTEL_GEN(dev_priv)) {
 857         default:
 858                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 859
 860                 if (engine->id != RCS)
 861                         break;
 862
 863                 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
 864                 for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
 865                         instdone->sampler[slice][subslice] =
 866                                 read_subslice_reg(dev_priv, slice, subslice,
 867                                                   GEN7_SAMPLER_INSTDONE);
 868                         instdone->row[slice][subslice] =
 869                                 read_subslice_reg(dev_priv, slice, subslice,
 870                                                   GEN7_ROW_INSTDONE);
 871                 }
 872                 break;
 873         case 7:
 874                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 875
 876                 if (engine->id != RCS)
 877                         break;
 878
 879                 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
 880                 instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
 881                 instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
 882
 883                 break;
 884         case 6:
 885         case 5:
 886         case 4:
 887                 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
 888
 889                 if (engine->id == RCS)
 890                         /* HACK: Using the wrong struct member */
 891                         instdone->slice_common = I915_READ(GEN4_INSTDONE1);
 892                 break;
 893         case 3:
 894         case 2:
 895                 instdone->instdone = I915_READ(GEN2_INSTDONE);
 896                 break;
 897         }
 898 }
 899
 900 static bool ring_is_idle(struct intel_engine_cs *engine)
 901 {
 902         struct drm_i915_private *dev_priv = engine->i915;
 903         bool idle = true;
 904
 905         /* If the whole device is asleep, the engine must be idle */
 906         if (!intel_runtime_pm_get_if_in_use(dev_priv))
 907                 return true;
 908
 909         /* First check that no commands are left in the ring */
 910         if ((I915_READ_HEAD(engine) & HEAD_ADDR) !=
 911             (I915_READ_TAIL(engine) & TAIL_ADDR))
 912                 idle = false;
 913
 914         /* No bit for gen2, so assume the CS parser is idle */
 915         if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
 916                 idle = false;
 917
 918         intel_runtime_pm_put(dev_priv);
 919
 920         return idle;
 921 }
 922
 923 /**
 924  * intel_engine_is_idle() - Report if the engine has finished process all work
 925  * @engine: the intel_engine_cs
 926  *
 927  * Return true if there are no requests pending, nothing left to be submitted
 928  * to hardware, and that the engine is idle.
 929  */
 930 bool intel_engine_is_idle(struct intel_engine_cs *engine)
 931 {
 932         struct drm_i915_private *dev_priv = engine->i915;
 933
 934         /* More white lies, if wedged, hw state is inconsistent */
 935         if (i915_terminally_wedged(&dev_priv->gpu_error))
 936                 return true;
 937
 938         /* Any inflight/incomplete requests? */
 939         if (!intel_engine_signaled(engine, intel_engine_last_submit(engine)))
 940                 return false;
 941
 942         if (I915_SELFTEST_ONLY(engine->breadcrumbs.mock))
 943                 return true;
 944
 945         /* Waiting to drain ELSP? */
 946         if (READ_ONCE(engine->execlists.active)) {
 947                 struct tasklet_struct *t = &engine->execlists.tasklet;
 948
 949                 local_bh_disable();
 950                 if (tasklet_trylock(t)) {
 951                         /* Must wait for any GPU reset in progress. */
 952                         if (__tasklet_is_enabled(t))
 953                                 t->func(t->data);
 954                         tasklet_unlock(t);
 955                 }
 956                 local_bh_enable();
 957
 958                 /* Otherwise flush the tasklet if it was on another cpu */
 959                 tasklet_unlock_wait(t);
 960
 961                 if (READ_ONCE(engine->execlists.active))
 962                         return false;
 963         }
 964
 965         /* ELSP is empty, but there are ready requests? E.g. after reset */
 966         if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
 967                 return false;
 968
 969         /* Ring stopped? */
 970         if (!ring_is_idle(engine))
 971                 return false;
 972
 973         return true;
 974 }
 975
 976 bool intel_engines_are_idle(struct drm_i915_private *dev_priv)
 977 {
 978         struct intel_engine_cs *engine;
 979         enum intel_engine_id id;
 980
 981         /*
 982          * If the driver is wedged, HW state may be very inconsistent and
 983          * report that it is still busy, even though we have stopped using it.
 984          */
 985         if (i915_terminally_wedged(&dev_priv->gpu_error))
 986                 return true;
 987
 988         for_each_engine(engine, dev_priv, id) {
 989                 if (!intel_engine_is_idle(engine))
 990                         return false;
 991         }
 992
 993         return true;
 994 }
 995
 996 /**
 997  * intel_engine_has_kernel_context:
 998  * @engine: the engine
 999  *
1000  * Returns true if the last context to be executed on this engine, or has been
1001  * executed if the engine is already idle, is the kernel context
1002  * (#i915.kernel_context).
1003  */
1004 bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine)
1005 {
1006         const struct intel_context *kernel_context =
1007                 to_intel_context(engine->i915->kernel_context, engine);
1008         struct i915_request *rq;
1009
1010         lockdep_assert_held(&engine->i915->drm.struct_mutex);
1011
1012         /*
1013          * Check the last context seen by the engine. If active, it will be
1014          * the last request that remains in the timeline. When idle, it is
1015          * the last executed context as tracked by retirement.
1016          */
1017         rq = __i915_gem_active_peek(&engine->timeline.last_request);
1018         if (rq)
1019                 return rq->hw_context == kernel_context;
1020         else
1021                 return engine->last_retired_context == kernel_context;
1022 }
1023
1024 void intel_engines_reset_default_submission(struct drm_i915_private *i915)
1025 {
1026         struct intel_engine_cs *engine;
1027         enum intel_engine_id id;
1028
1029         for_each_engine(engine, i915, id)
1030                 engine->set_default_submission(engine);
1031 }
1032
1033 /**
1034  * intel_engines_sanitize: called after the GPU has lost power
1035  * @i915: the i915 device
1036  *
1037  * Anytime we reset the GPU, either with an explicit GPU reset or through a
1038  * PCI power cycle, the GPU loses state and we must reset our state tracking
1039  * to match. Note that calling intel_engines_sanitize() if the GPU has not
1040  * been reset results in much confusion!
1041  */
1042 void intel_engines_sanitize(struct drm_i915_private *i915)
1043 {
1044         struct intel_engine_cs *engine;
1045         enum intel_engine_id id;
1046
1047         GEM_TRACE("\n");
1048
1049         for_each_engine(engine, i915, id) {
1050                 if (engine->reset.reset)
1051                         engine->reset.reset(engine, NULL);
1052         }
1053 }
1054
1055 /**
1056  * intel_engines_park: called when the GT is transitioning from busy->idle
1057  * @i915: the i915 device
1058  *
1059  * The GT is now idle and about to go to sleep (maybe never to wake again?).
1060  * Time for us to tidy and put away our toys (release resources back to the
1061  * system).
1062  */
1063 void intel_engines_park(struct drm_i915_private *i915)
1064 {
1065         struct intel_engine_cs *engine;
1066         enum intel_engine_id id;
1067
1068         for_each_engine(engine, i915, id) {
1069                 /* Flush the residual irq tasklets first. */
1070                 intel_engine_disarm_breadcrumbs(engine);
1071                 tasklet_kill(&engine->execlists.tasklet);
1072
1073                 /*
1074                  * We are committed now to parking the engines, make sure there
1075                  * will be no more interrupts arriving later and the engines
1076                  * are truly idle.
1077                  */
1078                 if (wait_for(intel_engine_is_idle(engine), 10)) {
1079                         struct drm_printer p = drm_debug_printer(__func__);
1080
1081                         dev_err(i915->drm.dev,
1082                                 "%s is not idle before parking\n",
1083                                 engine->name);
1084                         intel_engine_dump(engine, &p, NULL);
1085                 }
1086
1087                 /* Must be reset upon idling, or we may miss the busy wakeup. */
1088                 GEM_BUG_ON(engine->execlists.queue_priority != INT_MIN);
1089
1090                 if (engine->park)
1091                         engine->park(engine);
1092
1093                 if (engine->pinned_default_state) {
1094                         i915_gem_object_unpin_map(engine->default_state);
1095                         engine->pinned_default_state = NULL;
1096                 }
1097
1098                 i915_gem_batch_pool_fini(&engine->batch_pool);
1099                 engine->execlists.no_priolist = false;
1100         }
1101 }
1102
1103 /**
1104  * intel_engines_unpark: called when the GT is transitioning from idle->busy
1105  * @i915: the i915 device
1106  *
1107  * The GT was idle and now about to fire up with some new user requests.
1108  */
1109 void intel_engines_unpark(struct drm_i915_private *i915)
1110 {
1111         struct intel_engine_cs *engine;
1112         enum intel_engine_id id;
1113
1114         for_each_engine(engine, i915, id) {
1115                 void *map;
1116
1117                 /* Pin the default state for fast resets from atomic context. */
1118                 map = NULL;
1119                 if (engine->default_state)
1120                         map = i915_gem_object_pin_map(engine->default_state,
1121                                                       I915_MAP_WB);
1122                 if (!IS_ERR_OR_NULL(map))
1123                         engine->pinned_default_state = map;
1124
1125                 if (engine->unpark)
1126                         engine->unpark(engine);
1127
1128                 intel_engine_init_hangcheck(engine);
1129         }
1130 }
1131
1132 /**
1133  * intel_engine_lost_context: called when the GPU is reset into unknown state
1134  * @engine: the engine
1135  *
1136  * We have either reset the GPU or otherwise about to lose state tracking of
1137  * the current GPU logical state (e.g. suspend). On next use, it is therefore
1138  * imperative that we make no presumptions about the current state and load
1139  * from scratch.
1140  */
1141 void intel_engine_lost_context(struct intel_engine_cs *engine)
1142 {
1143         struct intel_context *ce;
1144
1145         lockdep_assert_held(&engine->i915->drm.struct_mutex);
1146
1147         ce = fetch_and_zero(&engine->last_retired_context);
1148         if (ce)
1149                 intel_context_unpin(ce);
1150 }
1151
1152 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1153 {
1154         switch (INTEL_GEN(engine->i915)) {
1155         case 2:
1156                 return false; /* uses physical not virtual addresses */
1157         case 3:
1158                 /* maybe only uses physical not virtual addresses */
1159                 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1160         case 6:
1161                 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1162         default:
1163                 return true;
1164         }
1165 }
1166
1167 unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915)
1168 {
1169         struct intel_engine_cs *engine;
1170         enum intel_engine_id id;
1171         unsigned int which;
1172
1173         which = 0;
1174         for_each_engine(engine, i915, id)
1175                 if (engine->default_state)
1176                         which |= BIT(engine->uabi_class);
1177
1178         return which;
1179 }
1180
1181 static int print_sched_attr(struct drm_i915_private *i915,
1182                             const struct i915_sched_attr *attr,
1183                             char *buf, int x, int len)
1184 {
1185         if (attr->priority == I915_PRIORITY_INVALID)
1186                 return x;
1187
1188         x += snprintf(buf + x, len - x,
1189                       " prio=%d", attr->priority);
1190
1191         return x;
1192 }
1193
1194 static void print_request(struct drm_printer *m,
1195                           struct i915_request *rq,
1196                           const char *prefix)
1197 {
1198         const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
1199         char buf[80] = "";
1200         int x = 0;
1201
1202         x = print_sched_attr(rq->i915, &rq->sched.attr, buf, x, sizeof(buf));
1203
1204         drm_printf(m, "%s%x%s [%llx:%x]%s @ %dms: %s\n",
1205                    prefix,
1206                    rq->global_seqno,
1207                    i915_request_completed(rq) ? "!" : "",
1208                    rq->fence.context, rq->fence.seqno,
1209                    buf,
1210                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
1211                    name);
1212 }
1213
1214 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1215 {
1216         const size_t rowsize = 8 * sizeof(u32);
1217         const void *prev = NULL;
1218         bool skip = false;
1219         size_t pos;
1220
1221         for (pos = 0; pos < len; pos += rowsize) {
1222                 char line[128];
1223
1224                 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1225                         if (!skip) {
1226                                 drm_printf(m, "*\n");
1227                                 skip = true;
1228                         }
1229                         continue;
1230                 }
1231
1232                 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1233                                                 rowsize, sizeof(u32),
1234                                                 line, sizeof(line),
1235                                                 false) >= sizeof(line));
1236                 drm_printf(m, "[%04zx] %s\n", pos, line);
1237
1238                 prev = buf + pos;
1239                 skip = false;
1240         }
1241 }
1242
1243 static void intel_engine_print_registers(const struct intel_engine_cs *engine,
1244                                          struct drm_printer *m)
1245 {
1246         struct drm_i915_private *dev_priv = engine->i915;
1247         const struct intel_engine_execlists * const execlists =
1248                 &engine->execlists;
1249         u64 addr;
1250
1251         if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
1252                 drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
1253         drm_printf(m, "\tRING_START: 0x%08x\n",
1254                    I915_READ(RING_START(engine->mmio_base)));
1255         drm_printf(m, "\tRING_HEAD:  0x%08x\n",
1256                    I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR);
1257         drm_printf(m, "\tRING_TAIL:  0x%08x\n",
1258                    I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR);
1259         drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
1260                    I915_READ(RING_CTL(engine->mmio_base)),
1261                    I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1262         if (INTEL_GEN(engine->i915) > 2) {
1263                 drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
1264                            I915_READ(RING_MI_MODE(engine->mmio_base)),
1265                            I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
1266         }
1267
1268         if (INTEL_GEN(dev_priv) >= 6) {
1269                 drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine));
1270         }
1271
1272         if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
1273                 drm_printf(m, "\tSYNC_0: 0x%08x\n",
1274                            I915_READ(RING_SYNC_0(engine->mmio_base)));
1275                 drm_printf(m, "\tSYNC_1: 0x%08x\n",
1276                            I915_READ(RING_SYNC_1(engine->mmio_base)));
1277                 if (HAS_VEBOX(dev_priv))
1278                         drm_printf(m, "\tSYNC_2: 0x%08x\n",
1279                                    I915_READ(RING_SYNC_2(engine->mmio_base)));
1280         }
1281
1282         addr = intel_engine_get_active_head(engine);
1283         drm_printf(m, "\tACTHD:  0x%08x_%08x\n",
1284                    upper_32_bits(addr), lower_32_bits(addr));
1285         addr = intel_engine_get_last_batch_head(engine);
1286         drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1287                    upper_32_bits(addr), lower_32_bits(addr));
1288         if (INTEL_GEN(dev_priv) >= 8)
1289                 addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
1290                                         RING_DMA_FADD_UDW(engine->mmio_base));
1291         else if (INTEL_GEN(dev_priv) >= 4)
1292                 addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1293         else
1294                 addr = I915_READ(DMA_FADD_I8XX);
1295         drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1296                    upper_32_bits(addr), lower_32_bits(addr));
1297         if (INTEL_GEN(dev_priv) >= 4) {
1298                 drm_printf(m, "\tIPEIR: 0x%08x\n",
1299                            I915_READ(RING_IPEIR(engine->mmio_base)));
1300                 drm_printf(m, "\tIPEHR: 0x%08x\n",
1301                            I915_READ(RING_IPEHR(engine->mmio_base)));
1302         } else {
1303                 drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
1304                 drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
1305         }
1306
1307         if (HAS_EXECLISTS(dev_priv)) {
1308                 const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
1309                 unsigned int idx;
1310                 u8 read, write;
1311
1312                 drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
1313                            I915_READ(RING_EXECLIST_STATUS_LO(engine)),
1314                            I915_READ(RING_EXECLIST_STATUS_HI(engine)));
1315
1316                 read = execlists->csb_head;
1317                 write = READ_ONCE(*execlists->csb_write);
1318
1319                 drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
1320                            read, write,
1321                            GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
1322                            yesno(test_bit(TASKLET_STATE_SCHED,
1323                                           &engine->execlists.tasklet.state)),
1324                            enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
1325                 if (read >= GEN8_CSB_ENTRIES)
1326                         read = 0;
1327                 if (write >= GEN8_CSB_ENTRIES)
1328                         write = 0;
1329                 if (read > write)
1330                         write += GEN8_CSB_ENTRIES;
1331                 while (read < write) {
1332                         idx = ++read % GEN8_CSB_ENTRIES;
1333                         drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
1334                                    idx,
1335                                    hws[idx * 2],
1336                                    I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
1337                                    hws[idx * 2 + 1],
1338                                    I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
1339                 }
1340
1341                 rcu_read_lock();
1342                 for (idx = 0; idx < execlists_num_ports(execlists); idx++) {
1343                         struct i915_request *rq;
1344                         unsigned int count;
1345
1346                         rq = port_unpack(&execlists->port[idx], &count);
1347                         if (rq) {
1348                                 char hdr[80];
1349
1350                                 snprintf(hdr, sizeof(hdr),
1351                                          "\t\tELSP[%d] count=%d, ring->start=%08x, rq: ",
1352                                          idx, count,
1353                                          i915_ggtt_offset(rq->ring->vma));
1354                                 print_request(m, rq, hdr);
1355                         } else {
1356                                 drm_printf(m, "\t\tELSP[%d] idle\n", idx);
1357                         }
1358                 }
1359                 drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
1360                 rcu_read_unlock();
1361         } else if (INTEL_GEN(dev_priv) > 6) {
1362                 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1363                            I915_READ(RING_PP_DIR_BASE(engine)));
1364                 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1365                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
1366                 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1367                            I915_READ(RING_PP_DIR_DCLV(engine)));
1368         }
1369 }
1370
1371 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1372 {
1373         void *ring;
1374         int size;
1375
1376         drm_printf(m,
1377                    "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1378                    rq->head, rq->postfix, rq->tail,
1379                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
1380                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
1381
1382         size = rq->tail - rq->head;
1383         if (rq->tail < rq->head)
1384                 size += rq->ring->size;
1385
1386         ring = kmalloc(size, GFP_ATOMIC);
1387         if (ring) {
1388                 const void *vaddr = rq->ring->vaddr;
1389                 unsigned int head = rq->head;
1390                 unsigned int len = 0;
1391
1392                 if (rq->tail < head) {
1393                         len = rq->ring->size - head;
1394                         memcpy(ring, vaddr + head, len);
1395                         head = 0;
1396                 }
1397                 memcpy(ring + len, vaddr + head, size - len);
1398
1399                 hexdump(m, ring, size);
1400                 kfree(ring);
1401         }
1402 }
1403
1404 void intel_engine_dump(struct intel_engine_cs *engine,
1405                        struct drm_printer *m,
1406                        const char *header, ...)
1407 {
1408         const int MAX_REQUESTS_TO_SHOW = 8;
1409         struct intel_breadcrumbs * const b = &engine->breadcrumbs;
1410         const struct intel_engine_execlists * const execlists = &engine->execlists;
1411         struct i915_gpu_error * const error = &engine->i915->gpu_error;
1412         struct i915_request *rq, *last;
1413         unsigned long flags;
1414         struct rb_node *rb;
1415         int count;
1416
1417         if (header) {
1418                 va_list ap;
1419
1420                 va_start(ap, header);
1421                 drm_vprintf(m, header, &ap);
1422                 va_end(ap);
1423         }
1424
1425         if (i915_terminally_wedged(&engine->i915->gpu_error))
1426                 drm_printf(m, "*** WEDGED ***\n");
1427
1428         drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n",
1429                    intel_engine_get_seqno(engine),
1430                    intel_engine_last_submit(engine),
1431                    engine->hangcheck.seqno,
1432                    jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
1433         drm_printf(m, "\tReset count: %d (global %d)\n",
1434                    i915_reset_engine_count(error, engine),
1435                    i915_reset_count(error));
1436
1437         rcu_read_lock();
1438
1439         drm_printf(m, "\tRequests:\n");
1440
1441         rq = list_first_entry(&engine->timeline.requests,
1442                               struct i915_request, link);
1443         if (&rq->link != &engine->timeline.requests)
1444                 print_request(m, rq, "\t\tfirst  ");
1445
1446         rq = list_last_entry(&engine->timeline.requests,
1447                              struct i915_request, link);
1448         if (&rq->link != &engine->timeline.requests)
1449                 print_request(m, rq, "\t\tlast   ");
1450
1451         rq = i915_gem_find_active_request(engine);
1452         if (rq) {
1453                 print_request(m, rq, "\t\tactive ");
1454
1455                 drm_printf(m, "\t\tring->start:  0x%08x\n",
1456                            i915_ggtt_offset(rq->ring->vma));
1457                 drm_printf(m, "\t\tring->head:   0x%08x\n",
1458                            rq->ring->head);
1459                 drm_printf(m, "\t\tring->tail:   0x%08x\n",
1460                            rq->ring->tail);
1461                 drm_printf(m, "\t\tring->emit:   0x%08x\n",
1462                            rq->ring->emit);
1463                 drm_printf(m, "\t\tring->space:  0x%08x\n",
1464                            rq->ring->space);
1465
1466                 print_request_ring(m, rq);
1467         }
1468
1469         rcu_read_unlock();
1470
1471         if (intel_runtime_pm_get_if_in_use(engine->i915)) {
1472                 intel_engine_print_registers(engine, m);
1473                 intel_runtime_pm_put(engine->i915);
1474         } else {
1475                 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
1476         }
1477
1478         local_irq_save(flags);
1479         spin_lock(&engine->timeline.lock);
1480
1481         last = NULL;
1482         count = 0;
1483         list_for_each_entry(rq, &engine->timeline.requests, link) {
1484                 if (count++ < MAX_REQUESTS_TO_SHOW - 1)
1485                         print_request(m, rq, "\t\tE ");
1486                 else
1487                         last = rq;
1488         }
1489         if (last) {
1490                 if (count > MAX_REQUESTS_TO_SHOW) {
1491                         drm_printf(m,
1492                                    "\t\t...skipping %d executing requests...\n",
1493                                    count - MAX_REQUESTS_TO_SHOW);
1494                 }
1495                 print_request(m, last, "\t\tE ");
1496         }
1497
1498         last = NULL;
1499         count = 0;
1500         drm_printf(m, "\t\tQueue priority: %d\n", execlists->queue_priority);
1501         for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
1502                 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
1503                 int i;
1504
1505                 priolist_for_each_request(rq, p, i) {
1506                         if (count++ < MAX_REQUESTS_TO_SHOW - 1)
1507                                 print_request(m, rq, "\t\tQ ");
1508                         else
1509                                 last = rq;
1510                 }
1511         }
1512         if (last) {
1513                 if (count > MAX_REQUESTS_TO_SHOW) {
1514                         drm_printf(m,
1515                                    "\t\t...skipping %d queued requests...\n",
1516                                    count - MAX_REQUESTS_TO_SHOW);
1517                 }
1518                 print_request(m, last, "\t\tQ ");
1519         }
1520
1521         spin_unlock(&engine->timeline.lock);
1522
1523         spin_lock(&b->rb_lock);
1524         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1525                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1526
1527                 drm_printf(m, "\t%s [%d:%c] waiting for %x\n",
1528                            w->tsk->comm, w->tsk->pid,
1529                            task_state_to_char(w->tsk),
1530                            w->seqno);
1531         }
1532         spin_unlock(&b->rb_lock);
1533         local_irq_restore(flags);
1534
1535         drm_printf(m, "IRQ? 0x%lx (breadcrumbs? %s)\n",
1536                    engine->irq_posted,
1537                    yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
1538                                   &engine->irq_posted)));
1539
1540         drm_printf(m, "HWSP:\n");
1541         hexdump(m, engine->status_page.page_addr, PAGE_SIZE);
1542
1543         drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
1544 }
1545
1546 static u8 user_class_map[] = {
1547         [I915_ENGINE_CLASS_RENDER] = RENDER_CLASS,
1548         [I915_ENGINE_CLASS_COPY] = COPY_ENGINE_CLASS,
1549         [I915_ENGINE_CLASS_VIDEO] = VIDEO_DECODE_CLASS,
1550         [I915_ENGINE_CLASS_VIDEO_ENHANCE] = VIDEO_ENHANCEMENT_CLASS,
1551 };
1552
1553 struct intel_engine_cs *
1554 intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance)
1555 {
1556         if (class >= ARRAY_SIZE(user_class_map))
1557                 return NULL;
1558
1559         class = user_class_map[class];
1560
1561         GEM_BUG_ON(class > MAX_ENGINE_CLASS);
1562
1563         if (instance > MAX_ENGINE_INSTANCE)
1564                 return NULL;
1565
1566         return i915->engine_class[class][instance];
1567 }
1568
1569 /**
1570  * intel_enable_engine_stats() - Enable engine busy tracking on engine
1571  * @engine: engine to enable stats collection
1572  *
1573  * Start collecting the engine busyness data for @engine.
1574  *
1575  * Returns 0 on success or a negative error code.
1576  */
1577 int intel_enable_engine_stats(struct intel_engine_cs *engine)
1578 {
1579         struct intel_engine_execlists *execlists = &engine->execlists;
1580         unsigned long flags;
1581         int err = 0;
1582
1583         if (!intel_engine_supports_stats(engine))
1584                 return -ENODEV;
1585
1586         spin_lock_irqsave(&engine->timeline.lock, flags);
1587         write_seqlock(&engine->stats.lock);
1588
1589         if (unlikely(engine->stats.enabled == ~0)) {
1590                 err = -EBUSY;
1591                 goto unlock;
1592         }
1593
1594         if (engine->stats.enabled++ == 0) {
1595                 const struct execlist_port *port = execlists->port;
1596                 unsigned int num_ports = execlists_num_ports(execlists);
1597
1598                 engine->stats.enabled_at = ktime_get();
1599
1600                 /* XXX submission method oblivious? */
1601                 while (num_ports-- && port_isset(port)) {
1602                         engine->stats.active++;
1603                         port++;
1604                 }
1605
1606                 if (engine->stats.active)
1607                         engine->stats.start = engine->stats.enabled_at;
1608         }
1609
1610 unlock:
1611         write_sequnlock(&engine->stats.lock);
1612         spin_unlock_irqrestore(&engine->timeline.lock, flags);
1613
1614         return err;
1615 }
1616
1617 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
1618 {
1619         ktime_t total = engine->stats.total;
1620
1621         /*
1622          * If the engine is executing something at the moment
1623          * add it to the total.
1624          */
1625         if (engine->stats.active)
1626                 total = ktime_add(total,
1627                                   ktime_sub(ktime_get(), engine->stats.start));
1628
1629         return total;
1630 }
1631
1632 /**
1633  * intel_engine_get_busy_time() - Return current accumulated engine busyness
1634  * @engine: engine to report on
1635  *
1636  * Returns accumulated time @engine was busy since engine stats were enabled.
1637  */
1638 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine)
1639 {
1640         unsigned int seq;
1641         ktime_t total;
1642
1643         do {
1644                 seq = read_seqbegin(&engine->stats.lock);
1645                 total = __intel_engine_get_busy_time(engine);
1646         } while (read_seqretry(&engine->stats.lock, seq));
1647
1648         return total;
1649 }
1650
1651 /**
1652  * intel_disable_engine_stats() - Disable engine busy tracking on engine
1653  * @engine: engine to disable stats collection
1654  *
1655  * Stops collecting the engine busyness data for @engine.
1656  */
1657 void intel_disable_engine_stats(struct intel_engine_cs *engine)
1658 {
1659         unsigned long flags;
1660
1661         if (!intel_engine_supports_stats(engine))
1662                 return;
1663
1664         write_seqlock_irqsave(&engine->stats.lock, flags);
1665         WARN_ON_ONCE(engine->stats.enabled == 0);
1666         if (--engine->stats.enabled == 0) {
1667                 engine->stats.total = __intel_engine_get_busy_time(engine);
1668                 engine->stats.active = 0;
1669         }
1670         write_sequnlock_irqrestore(&engine->stats.lock, flags);
1671 }
1672
1673 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1674 #include "selftests/mock_engine.c"
1675 #include "selftests/intel_engine_cs.c"
1676 #endif