drivers/gpu/drm/i915/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Panel Self Refresh (PSR/SRD)
  26  *
  27  * Since Haswell Display controller supports Panel Self-Refresh on display
  28  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  29  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  30  * when system is idle but display is on as it eliminates display refresh
  31  * request to DDR memory completely as long as the frame buffer for that
  32  * display is unchanged.
  33  *
  34  * Panel Self Refresh must be supported by both Hardware (source) and
  35  * Panel (sink).
  36  *
  37  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  38  * to power down the link and memory controller. For DSI panels the same idea
  39  * is called "manual mode".
  40  *
  41  * The implementation uses the hardware-based PSR support which automatically
  42  * enters/exits self-refresh mode. The hardware takes care of sending the
  43  * required DP aux message and could even retrain the link (that part isn't
  44  * enabled yet though). The hardware also keeps track of any frontbuffer
  45  * changes to know when to exit self-refresh mode again. Unfortunately that
  46  * part doesn't work too well, hence why the i915 PSR support uses the
  47  * software frontbuffer tracking to make sure it doesn't miss a screen
  48  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  49  * get called by the frontbuffer tracking code. Note that because of locking
  50  * issues the self-refresh re-enable code is done from a work queue, which
  51  * must be correctly synchronized/cancelled when shutting down the pipe."
  52  */
  53
  54 #include <drm/drmP.h>
  55
  56 #include "intel_drv.h"
  57 #include "i915_drv.h"
  58
  59 static inline enum intel_display_power_domain
  60 psr_aux_domain(struct intel_dp *intel_dp)
  61 {
  62         /* CNL HW requires corresponding AUX IOs to be powered up for PSR.
  63          * However, for non-A AUX ports the corresponding non-EDP transcoders
  64          * would have already enabled power well 2 and DC_OFF. This means we can
  65          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
  66          * specific AUX_IO reference without powering up any extra wells.
  67          * Note that PSR is enabled only on Port A even though this function
  68          * returns the correct domain for other ports too.
  69          */
  70         return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
  71                                               intel_dp->aux_power_domain;
  72 }
  73
  74 static void psr_aux_io_power_get(struct intel_dp *intel_dp)
  75 {
  76         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  77         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
  78
  79         if (INTEL_GEN(dev_priv) < 10)
  80                 return;
  81
  82         intel_display_power_get(dev_priv, psr_aux_domain(intel_dp));
  83 }
  84
  85 static void psr_aux_io_power_put(struct intel_dp *intel_dp)
  86 {
  87         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  88         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
  89
  90         if (INTEL_GEN(dev_priv) < 10)
  91                 return;
  92
  93         intel_display_power_put(dev_priv, psr_aux_domain(intel_dp));
  94 }
  95
  96 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)
  97 {
  98         u32 debug_mask, mask;
  99
 100         /* No PSR interrupts on VLV/CHV */
 101         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 102                 return;
 103
 104         mask = EDP_PSR_ERROR(TRANSCODER_EDP);
 105         debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) |
 106                      EDP_PSR_PRE_ENTRY(TRANSCODER_EDP);
 107
 108         if (INTEL_GEN(dev_priv) >= 8) {
 109                 mask |= EDP_PSR_ERROR(TRANSCODER_A) |
 110                         EDP_PSR_ERROR(TRANSCODER_B) |
 111                         EDP_PSR_ERROR(TRANSCODER_C);
 112
 113                 debug_mask |= EDP_PSR_POST_EXIT(TRANSCODER_A) |
 114                               EDP_PSR_PRE_ENTRY(TRANSCODER_A) |
 115                               EDP_PSR_POST_EXIT(TRANSCODER_B) |
 116                               EDP_PSR_PRE_ENTRY(TRANSCODER_B) |
 117                               EDP_PSR_POST_EXIT(TRANSCODER_C) |
 118                               EDP_PSR_PRE_ENTRY(TRANSCODER_C);
 119         }
 120
 121         if (debug)
 122                 mask |= debug_mask;
 123
 124         WRITE_ONCE(dev_priv->psr.debug, debug);
 125         I915_WRITE(EDP_PSR_IMR, ~mask);
 126 }
 127
 128 static void psr_event_print(u32 val, bool psr2_enabled)
 129 {
 130         DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val);
 131         if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 132                 DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");
 133         if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
 134                 DRM_DEBUG_KMS("\tPSR2 disabled\n");
 135         if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 136                 DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");
 137         if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
 138                 DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");
 139         if (val & PSR_EVENT_GRAPHICS_RESET)
 140                 DRM_DEBUG_KMS("\tGraphics reset\n");
 141         if (val & PSR_EVENT_PCH_INTERRUPT)
 142                 DRM_DEBUG_KMS("\tPCH interrupt\n");
 143         if (val & PSR_EVENT_MEMORY_UP)
 144                 DRM_DEBUG_KMS("\tMemory up\n");
 145         if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 146                 DRM_DEBUG_KMS("\tFront buffer modification\n");
 147         if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 148                 DRM_DEBUG_KMS("\tPSR watchdog timer expired\n");
 149         if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 150                 DRM_DEBUG_KMS("\tPIPE registers updated\n");
 151         if (val & PSR_EVENT_REGISTER_UPDATE)
 152                 DRM_DEBUG_KMS("\tRegister updated\n");
 153         if (val & PSR_EVENT_HDCP_ENABLE)
 154                 DRM_DEBUG_KMS("\tHDCP enabled\n");
 155         if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 156                 DRM_DEBUG_KMS("\tKVMR session enabled\n");
 157         if (val & PSR_EVENT_VBI_ENABLE)
 158                 DRM_DEBUG_KMS("\tVBI enabled\n");
 159         if (val & PSR_EVENT_LPSP_MODE_EXIT)
 160                 DRM_DEBUG_KMS("\tLPSP mode exited\n");
 161         if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
 162                 DRM_DEBUG_KMS("\tPSR disabled\n");
 163 }
 164
 165 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 166 {
 167         u32 transcoders = BIT(TRANSCODER_EDP);
 168         enum transcoder cpu_transcoder;
 169         ktime_t time_ns =  ktime_get();
 170
 171         if (INTEL_GEN(dev_priv) >= 8)
 172                 transcoders |= BIT(TRANSCODER_A) |
 173                                BIT(TRANSCODER_B) |
 174                                BIT(TRANSCODER_C);
 175
 176         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
 177                 /* FIXME: Exit PSR and link train manually when this happens. */
 178                 if (psr_iir & EDP_PSR_ERROR(cpu_transcoder))
 179                         DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n",
 180                                       transcoder_name(cpu_transcoder));
 181
 182                 if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
 183                         dev_priv->psr.last_entry_attempt = time_ns;
 184                         DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
 185                                       transcoder_name(cpu_transcoder));
 186                 }
 187
 188                 if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
 189                         dev_priv->psr.last_exit = time_ns;
 190                         DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
 191                                       transcoder_name(cpu_transcoder));
 192
 193                         if (INTEL_GEN(dev_priv) >= 9) {
 194                                 u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
 195                                 bool psr2_enabled = dev_priv->psr.psr2_enabled;
 196
 197                                 I915_WRITE(PSR_EVENT(cpu_transcoder), val);
 198                                 psr_event_print(val, psr2_enabled);
 199                         }
 200                 }
 201         }
 202 }
 203
 204 static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp)
 205 {
 206         uint8_t psr_caps = 0;
 207
 208         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
 209                 return false;
 210         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 211 }
 212
 213 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
 214 {
 215         uint8_t dprx = 0;
 216
 217         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
 218                               &dprx) != 1)
 219                 return false;
 220         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
 221 }
 222
 223 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 224 {
 225         uint8_t alpm_caps = 0;
 226
 227         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
 228                               &alpm_caps) != 1)
 229                 return false;
 230         return alpm_caps & DP_ALPM_CAP;
 231 }
 232
 233 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 234 {
 235         u8 val = 0;
 236
 237         if (drm_dp_dpcd_readb(&intel_dp->aux,
 238                               DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 239                 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 240         else
 241                 DRM_ERROR("Unable to get sink synchronization latency\n");
 242         return val;
 243 }
 244
 245 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 246 {
 247         struct drm_i915_private *dev_priv =
 248                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 249
 250         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 251                          sizeof(intel_dp->psr_dpcd));
 252
 253         if (intel_dp->psr_dpcd[0]) {
 254                 dev_priv->psr.sink_support = true;
 255                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
 256         }
 257
 258         if (INTEL_GEN(dev_priv) >= 9 &&
 259             (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 260                 /*
 261                  * All panels that supports PSR version 03h (PSR2 +
 262                  * Y-coordinate) can handle Y-coordinates in VSC but we are
 263                  * only sure that it is going to be used when required by the
 264                  * panel. This way panel is capable to do selective update
 265                  * without a aux frame sync.
 266                  *
 267                  * To support PSR version 02h and PSR version 03h without
 268                  * Y-coordinate requirement panels we would need to enable
 269                  * GTC first.
 270                  */
 271                 dev_priv->psr.sink_psr2_support =
 272                                 intel_dp_get_y_coord_required(intel_dp);
 273                 DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.sink_psr2_support
 274                               ? "supported" : "not supported");
 275
 276                 if (dev_priv->psr.sink_psr2_support) {
 277                         dev_priv->psr.colorimetry_support =
 278                                 intel_dp_get_colorimetry_status(intel_dp);
 279                         dev_priv->psr.alpm =
 280                                 intel_dp_get_alpm_status(intel_dp);
 281                         dev_priv->psr.sink_sync_latency =
 282                                 intel_dp_get_sink_sync_latency(intel_dp);
 283                 }
 284         }
 285 }
 286
 287 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
 288 {
 289         struct drm_i915_private *dev_priv = to_i915(dev);
 290         uint32_t val;
 291
 292         val = I915_READ(VLV_PSRSTAT(pipe)) &
 293               VLV_EDP_PSR_CURR_STATE_MASK;
 294         return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 295                (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
 296 }
 297
 298 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp,
 299                               const struct intel_crtc_state *crtc_state)
 300 {
 301         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 302         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 303         uint32_t val;
 304
 305         /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
 306         val  = I915_READ(VLV_VSCSDP(crtc->pipe));
 307         val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
 308         val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
 309         I915_WRITE(VLV_VSCSDP(crtc->pipe), val);
 310 }
 311
 312 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
 313                               const struct intel_crtc_state *crtc_state)
 314 {
 315         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 316         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 317         struct edp_vsc_psr psr_vsc;
 318
 319         if (dev_priv->psr.psr2_enabled) {
 320                 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 321                 memset(&psr_vsc, 0, sizeof(psr_vsc));
 322                 psr_vsc.sdp_header.HB0 = 0;
 323                 psr_vsc.sdp_header.HB1 = 0x7;
 324                 if (dev_priv->psr.colorimetry_support) {
 325                         psr_vsc.sdp_header.HB2 = 0x5;
 326                         psr_vsc.sdp_header.HB3 = 0x13;
 327                 } else {
 328                         psr_vsc.sdp_header.HB2 = 0x4;
 329                         psr_vsc.sdp_header.HB3 = 0xe;
 330                 }
 331         } else {
 332                 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 333                 memset(&psr_vsc, 0, sizeof(psr_vsc));
 334                 psr_vsc.sdp_header.HB0 = 0;
 335                 psr_vsc.sdp_header.HB1 = 0x7;
 336                 psr_vsc.sdp_header.HB2 = 0x2;
 337                 psr_vsc.sdp_header.HB3 = 0x8;
 338         }
 339
 340         intel_dig_port->write_infoframe(&intel_dig_port->base.base, crtc_state,
 341                                         DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
 342 }
 343
 344 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 345 {
 346         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 347                            DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
 348 }
 349
 350 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 351 {
 352         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 353         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 354         u32 aux_clock_divider, aux_ctl;
 355         int i;
 356         static const uint8_t aux_msg[] = {
 357                 [0] = DP_AUX_NATIVE_WRITE << 4,
 358                 [1] = DP_SET_POWER >> 8,
 359                 [2] = DP_SET_POWER & 0xff,
 360                 [3] = 1 - 1,
 361                 [4] = DP_SET_POWER_D0,
 362         };
 363         u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
 364                            EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
 365                            EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
 366                            EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
 367
 368         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 369         for (i = 0; i < sizeof(aux_msg); i += 4)
 370                 I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
 371                            intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 372
 373         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 374
 375         /* Start with bits set for DDI_AUX_CTL register */
 376         aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
 377                                              aux_clock_divider);
 378
 379         /* Select only valid bits for SRD_AUX_CTL */
 380         aux_ctl &= psr_aux_mask;
 381         I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
 382 }
 383
 384 static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 385 {
 386         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 387         struct drm_device *dev = dig_port->base.base.dev;
 388         struct drm_i915_private *dev_priv = to_i915(dev);
 389         u8 dpcd_val = DP_PSR_ENABLE;
 390
 391         /* Enable ALPM at sink for psr2 */
 392         if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
 393                 drm_dp_dpcd_writeb(&intel_dp->aux,
 394                                 DP_RECEIVER_ALPM_CONFIG,
 395                                 DP_ALPM_ENABLE);
 396
 397         if (dev_priv->psr.psr2_enabled)
 398                 dpcd_val |= DP_PSR_ENABLE_PSR2;
 399         if (dev_priv->psr.link_standby)
 400                 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 401         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 402
 403         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 404 }
 405
 406 static void vlv_psr_enable_source(struct intel_dp *intel_dp,
 407                                   const struct intel_crtc_state *crtc_state)
 408 {
 409         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 410         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 411         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 412
 413         /* Transition from PSR_state 0 (disabled) to PSR_state 1 (inactive) */
 414         I915_WRITE(VLV_PSRCTL(crtc->pipe),
 415                    VLV_EDP_PSR_MODE_SW_TIMER |
 416                    VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
 417                    VLV_EDP_PSR_ENABLE);
 418 }
 419
 420 static void vlv_psr_activate(struct intel_dp *intel_dp)
 421 {
 422         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 423         struct drm_device *dev = dig_port->base.base.dev;
 424         struct drm_i915_private *dev_priv = to_i915(dev);
 425         struct drm_crtc *crtc = dig_port->base.base.crtc;
 426         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 427
 428         /*
 429          * Let's do the transition from PSR_state 1 (inactive) to
 430          * PSR_state 2 (transition to active - static frame transmission).
 431          * Then Hardware is responsible for the transition to
 432          * PSR_state 3 (active - no Remote Frame Buffer (RFB) update).
 433          */
 434         I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
 435                    VLV_EDP_PSR_ACTIVE_ENTRY);
 436 }
 437
 438 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 439 {
 440         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 441         struct drm_device *dev = dig_port->base.base.dev;
 442         struct drm_i915_private *dev_priv = to_i915(dev);
 443
 444         uint32_t max_sleep_time = 0x1f;
 445         /*
 446          * Let's respect VBT in case VBT asks a higher idle_frame value.
 447          * Let's use 6 as the minimum to cover all known cases including
 448          * the off-by-one issue that HW has in some cases. Also there are
 449          * cases where sink should be able to train
 450          * with the 5 or 6 idle patterns.
 451          */
 452         uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 453         uint32_t val = EDP_PSR_ENABLE;
 454
 455         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 456         val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 457
 458         if (IS_HASWELL(dev_priv))
 459                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 460
 461         if (dev_priv->psr.link_standby)
 462                 val |= EDP_PSR_LINK_STANDBY;
 463
 464         if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
 465                 val |= EDP_PSR_TP1_TIME_2500us;
 466         else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
 467                 val |= EDP_PSR_TP1_TIME_500us;
 468         else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
 469                 val |= EDP_PSR_TP1_TIME_100us;
 470         else
 471                 val |= EDP_PSR_TP1_TIME_0us;
 472
 473         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 474                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 475         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
 476                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 477         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
 478                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 479         else
 480                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 481
 482         if (intel_dp_source_supports_hbr2(intel_dp) &&
 483             drm_dp_tps3_supported(intel_dp->dpcd))
 484                 val |= EDP_PSR_TP1_TP3_SEL;
 485         else
 486                 val |= EDP_PSR_TP1_TP2_SEL;
 487
 488         val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
 489         I915_WRITE(EDP_PSR_CTL, val);
 490 }
 491
 492 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 493 {
 494         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 495         struct drm_device *dev = dig_port->base.base.dev;
 496         struct drm_i915_private *dev_priv = to_i915(dev);
 497         /*
 498          * Let's respect VBT in case VBT asks a higher idle_frame value.
 499          * Let's use 6 as the minimum to cover all known cases including
 500          * the off-by-one issue that HW has in some cases. Also there are
 501          * cases where sink should be able to train
 502          * with the 5 or 6 idle patterns.
 503          */
 504         uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 505         u32 val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
 506
 507         /* FIXME: selective update is probably totally broken because it doesn't
 508          * mesh at all with our frontbuffer tracking. And the hw alone isn't
 509          * good enough. */
 510         val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 511         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 512                 val |= EDP_Y_COORDINATE_ENABLE;
 513
 514         val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 515
 516         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 517                 val |= EDP_PSR2_TP2_TIME_2500;
 518         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
 519                 val |= EDP_PSR2_TP2_TIME_500;
 520         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
 521                 val |= EDP_PSR2_TP2_TIME_100;
 522         else
 523                 val |= EDP_PSR2_TP2_TIME_50;
 524
 525         I915_WRITE(EDP_PSR2_CTL, val);
 526 }
 527
 528 static void hsw_psr_activate(struct intel_dp *intel_dp)
 529 {
 530         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 531         struct drm_device *dev = dig_port->base.base.dev;
 532         struct drm_i915_private *dev_priv = to_i915(dev);
 533
 534         /* On HSW+ after we enable PSR on source it will activate it
 535          * as soon as it match configure idle_frame count. So
 536          * we just actually enable it here on activation time.
 537          */
 538
 539         /* psr1 and psr2 are mutually exclusive.*/
 540         if (dev_priv->psr.psr2_enabled)
 541                 hsw_activate_psr2(intel_dp);
 542         else
 543                 hsw_activate_psr1(intel_dp);
 544 }
 545
 546 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 547                                     struct intel_crtc_state *crtc_state)
 548 {
 549         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 550         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 551         int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
 552         int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
 553         int psr_max_h = 0, psr_max_v = 0;
 554
 555         /*
 556          * FIXME psr2_support is messed up. It's both computed
 557          * dynamically during PSR enable, and extracted from sink
 558          * caps during eDP detection.
 559          */
 560         if (!dev_priv->psr.sink_psr2_support)
 561                 return false;
 562
 563         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 564                 psr_max_h = 4096;
 565                 psr_max_v = 2304;
 566         } else if (IS_GEN9(dev_priv)) {
 567                 psr_max_h = 3640;
 568                 psr_max_v = 2304;
 569         }
 570
 571         if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
 572                 DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 573                               crtc_hdisplay, crtc_vdisplay,
 574                               psr_max_h, psr_max_v);
 575                 return false;
 576         }
 577
 578         return true;
 579 }
 580
 581 void intel_psr_compute_config(struct intel_dp *intel_dp,
 582                               struct intel_crtc_state *crtc_state)
 583 {
 584         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 585         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 586         const struct drm_display_mode *adjusted_mode =
 587                 &crtc_state->base.adjusted_mode;
 588         int psr_setup_time;
 589
 590         if (!CAN_PSR(dev_priv))
 591                 return;
 592
 593         if (!i915_modparams.enable_psr) {
 594                 DRM_DEBUG_KMS("PSR disable by flag\n");
 595                 return;
 596         }
 597
 598         /*
 599          * HSW spec explicitly says PSR is tied to port A.
 600          * BDW+ platforms with DDI implementation of PSR have different
 601          * PSR registers per transcoder and we only implement transcoder EDP
 602          * ones. Since by Display design transcoder EDP is tied to port A
 603          * we can safely escape based on the port A.
 604          */
 605         if (HAS_DDI(dev_priv) && dig_port->base.port != PORT_A) {
 606                 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
 607                 return;
 608         }
 609
 610         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 611             !dev_priv->psr.link_standby) {
 612                 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
 613                 return;
 614         }
 615
 616         if (IS_HASWELL(dev_priv) &&
 617             I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
 618                       S3D_ENABLE) {
 619                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 620                 return;
 621         }
 622
 623         if (IS_HASWELL(dev_priv) &&
 624             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 625                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 626                 return;
 627         }
 628
 629         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
 630         if (psr_setup_time < 0) {
 631                 DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
 632                               intel_dp->psr_dpcd[1]);
 633                 return;
 634         }
 635
 636         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
 637             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
 638                 DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
 639                               psr_setup_time);
 640                 return;
 641         }
 642
 643         if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 644                 DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n");
 645                 return;
 646         }
 647
 648         crtc_state->has_psr = true;
 649         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
 650         DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
 651 }
 652
 653 static void intel_psr_activate(struct intel_dp *intel_dp)
 654 {
 655         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 656         struct drm_device *dev = intel_dig_port->base.base.dev;
 657         struct drm_i915_private *dev_priv = to_i915(dev);
 658
 659         if (dev_priv->psr.psr2_enabled)
 660                 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 661         else
 662                 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 663         WARN_ON(dev_priv->psr.active);
 664         lockdep_assert_held(&dev_priv->psr.lock);
 665
 666         dev_priv->psr.activate(intel_dp);
 667         dev_priv->psr.active = true;
 668 }
 669
 670 static void hsw_psr_enable_source(struct intel_dp *intel_dp,
 671                                   const struct intel_crtc_state *crtc_state)
 672 {
 673         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 674         struct drm_device *dev = dig_port->base.base.dev;
 675         struct drm_i915_private *dev_priv = to_i915(dev);
 676         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 677
 678         psr_aux_io_power_get(intel_dp);
 679
 680         /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
 681          * use hardcoded values PSR AUX transactions
 682          */
 683         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 684                 hsw_psr_setup_aux(intel_dp);
 685
 686         if (dev_priv->psr.psr2_enabled) {
 687                 u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
 688
 689                 if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
 690                         chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
 691                                    | PSR2_ADD_VERTICAL_LINE_COUNT);
 692
 693                 else
 694                         chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
 695                 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
 696
 697                 I915_WRITE(EDP_PSR_DEBUG,
 698                            EDP_PSR_DEBUG_MASK_MEMUP |
 699                            EDP_PSR_DEBUG_MASK_HPD |
 700                            EDP_PSR_DEBUG_MASK_LPSP |
 701                            EDP_PSR_DEBUG_MASK_MAX_SLEEP |
 702                            EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 703         } else {
 704                 /*
 705                  * Per Spec: Avoid continuous PSR exit by masking MEMUP
 706                  * and HPD. also mask LPSP to avoid dependency on other
 707                  * drivers that might block runtime_pm besides
 708                  * preventing  other hw tracking issues now we can rely
 709                  * on frontbuffer tracking.
 710                  */
 711                 I915_WRITE(EDP_PSR_DEBUG,
 712                            EDP_PSR_DEBUG_MASK_MEMUP |
 713                            EDP_PSR_DEBUG_MASK_HPD |
 714                            EDP_PSR_DEBUG_MASK_LPSP |
 715                            EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 716         }
 717 }
 718
 719 /**
 720  * intel_psr_enable - Enable PSR
 721  * @intel_dp: Intel DP
 722  * @crtc_state: new CRTC state
 723  *
 724  * This function can only be called after the pipe is fully trained and enabled.
 725  */
 726 void intel_psr_enable(struct intel_dp *intel_dp,
 727                       const struct intel_crtc_state *crtc_state)
 728 {
 729         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 730         struct drm_device *dev = intel_dig_port->base.base.dev;
 731         struct drm_i915_private *dev_priv = to_i915(dev);
 732
 733         if (!crtc_state->has_psr)
 734                 return;
 735
 736         if (WARN_ON(!CAN_PSR(dev_priv)))
 737                 return;
 738
 739         WARN_ON(dev_priv->drrs.dp);
 740         mutex_lock(&dev_priv->psr.lock);
 741         if (dev_priv->psr.enabled) {
 742                 DRM_DEBUG_KMS("PSR already in use\n");
 743                 goto unlock;
 744         }
 745
 746         dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
 747         dev_priv->psr.busy_frontbuffer_bits = 0;
 748
 749         dev_priv->psr.setup_vsc(intel_dp, crtc_state);
 750         dev_priv->psr.enable_sink(intel_dp);
 751         dev_priv->psr.enable_source(intel_dp, crtc_state);
 752         dev_priv->psr.enabled = intel_dp;
 753
 754         if (INTEL_GEN(dev_priv) >= 9) {
 755                 intel_psr_activate(intel_dp);
 756         } else {
 757                 /*
 758                  * FIXME: Activation should happen immediately since this
 759                  * function is just called after pipe is fully trained and
 760                  * enabled.
 761                  * However on some platforms we face issues when first
 762                  * activation follows a modeset so quickly.
 763                  *     - On VLV/CHV we get bank screen on first activation
 764                  *     - On HSW/BDW we get a recoverable frozen screen until
 765                  *       next exit-activate sequence.
 766                  */
 767                 schedule_delayed_work(&dev_priv->psr.work,
 768                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
 769         }
 770
 771 unlock:
 772         mutex_unlock(&dev_priv->psr.lock);
 773 }
 774
 775 static void vlv_psr_disable(struct intel_dp *intel_dp,
 776                             const struct intel_crtc_state *old_crtc_state)
 777 {
 778         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 779         struct drm_device *dev = intel_dig_port->base.base.dev;
 780         struct drm_i915_private *dev_priv = to_i915(dev);
 781         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 782         uint32_t val;
 783
 784         if (dev_priv->psr.active) {
 785                 /* Put VLV PSR back to PSR_state 0 (disabled). */
 786                 if (intel_wait_for_register(dev_priv,
 787                                             VLV_PSRSTAT(crtc->pipe),
 788                                             VLV_EDP_PSR_IN_TRANS,
 789                                             0,
 790                                             1))
 791                         WARN(1, "PSR transition took longer than expected\n");
 792
 793                 val = I915_READ(VLV_PSRCTL(crtc->pipe));
 794                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 795                 val &= ~VLV_EDP_PSR_ENABLE;
 796                 val &= ~VLV_EDP_PSR_MODE_MASK;
 797                 I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
 798
 799                 dev_priv->psr.active = false;
 800         } else {
 801                 WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe));
 802         }
 803 }
 804
 805 static void hsw_psr_disable(struct intel_dp *intel_dp,
 806                             const struct intel_crtc_state *old_crtc_state)
 807 {
 808         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 809         struct drm_device *dev = intel_dig_port->base.base.dev;
 810         struct drm_i915_private *dev_priv = to_i915(dev);
 811
 812         if (dev_priv->psr.active) {
 813                 i915_reg_t psr_status;
 814                 u32 psr_status_mask;
 815
 816                 if (dev_priv->psr.psr2_enabled) {
 817                         psr_status = EDP_PSR2_STATUS;
 818                         psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 819
 820                         I915_WRITE(EDP_PSR2_CTL,
 821                                    I915_READ(EDP_PSR2_CTL) &
 822                                    ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
 823
 824                 } else {
 825                         psr_status = EDP_PSR_STATUS;
 826                         psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
 827
 828                         I915_WRITE(EDP_PSR_CTL,
 829                                    I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 830                 }
 831
 832                 /* Wait till PSR is idle */
 833                 if (intel_wait_for_register(dev_priv,
 834                                             psr_status, psr_status_mask, 0,
 835                                             2000))
 836                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
 837
 838                 dev_priv->psr.active = false;
 839         } else {
 840                 if (dev_priv->psr.psr2_enabled)
 841                         WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 842                 else
 843                         WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 844         }
 845
 846         psr_aux_io_power_put(intel_dp);
 847 }
 848
 849 /**
 850  * intel_psr_disable - Disable PSR
 851  * @intel_dp: Intel DP
 852  * @old_crtc_state: old CRTC state
 853  *
 854  * This function needs to be called before disabling pipe.
 855  */
 856 void intel_psr_disable(struct intel_dp *intel_dp,
 857                        const struct intel_crtc_state *old_crtc_state)
 858 {
 859         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 860         struct drm_device *dev = intel_dig_port->base.base.dev;
 861         struct drm_i915_private *dev_priv = to_i915(dev);
 862
 863         if (!old_crtc_state->has_psr)
 864                 return;
 865
 866         if (WARN_ON(!CAN_PSR(dev_priv)))
 867                 return;
 868
 869         mutex_lock(&dev_priv->psr.lock);
 870         if (!dev_priv->psr.enabled) {
 871                 mutex_unlock(&dev_priv->psr.lock);
 872                 return;
 873         }
 874
 875         dev_priv->psr.disable_source(intel_dp, old_crtc_state);
 876
 877         /* Disable PSR on Sink */
 878         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 879
 880         dev_priv->psr.enabled = NULL;
 881         mutex_unlock(&dev_priv->psr.lock);
 882
 883         cancel_delayed_work_sync(&dev_priv->psr.work);
 884 }
 885
 886 static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
 887 {
 888         struct intel_dp *intel_dp;
 889         i915_reg_t reg;
 890         u32 mask;
 891         int err;
 892
 893         intel_dp = dev_priv->psr.enabled;
 894         if (!intel_dp)
 895                 return false;
 896
 897         if (HAS_DDI(dev_priv)) {
 898                 if (dev_priv->psr.psr2_enabled) {
 899                         reg = EDP_PSR2_STATUS;
 900                         mask = EDP_PSR2_STATUS_STATE_MASK;
 901                 } else {
 902                         reg = EDP_PSR_STATUS;
 903                         mask = EDP_PSR_STATUS_STATE_MASK;
 904                 }
 905         } else {
 906                 struct drm_crtc *crtc =
 907                         dp_to_dig_port(intel_dp)->base.base.crtc;
 908                 enum pipe pipe = to_intel_crtc(crtc)->pipe;
 909
 910                 reg = VLV_PSRSTAT(pipe);
 911                 mask = VLV_EDP_PSR_IN_TRANS;
 912         }
 913
 914         mutex_unlock(&dev_priv->psr.lock);
 915
 916         err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
 917         if (err)
 918                 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
 919
 920         /* After the unlocked wait, verify that PSR is still wanted! */
 921         mutex_lock(&dev_priv->psr.lock);
 922         return err == 0 && dev_priv->psr.enabled;
 923 }
 924
 925 static void intel_psr_work(struct work_struct *work)
 926 {
 927         struct drm_i915_private *dev_priv =
 928                 container_of(work, typeof(*dev_priv), psr.work.work);
 929
 930         mutex_lock(&dev_priv->psr.lock);
 931
 932         /*
 933          * We have to make sure PSR is ready for re-enable
 934          * otherwise it keeps disabled until next full enable/disable cycle.
 935          * PSR might take some time to get fully disabled
 936          * and be ready for re-enable.
 937          */
 938         if (!psr_wait_for_idle(dev_priv))
 939                 goto unlock;
 940
 941         /*
 942          * The delayed work can race with an invalidate hence we need to
 943          * recheck. Since psr_flush first clears this and then reschedules we
 944          * won't ever miss a flush when bailing out here.
 945          */
 946         if (dev_priv->psr.busy_frontbuffer_bits)
 947                 goto unlock;
 948
 949         intel_psr_activate(dev_priv->psr.enabled);
 950 unlock:
 951         mutex_unlock(&dev_priv->psr.lock);
 952 }
 953
 954 static void intel_psr_exit(struct drm_i915_private *dev_priv)
 955 {
 956         struct intel_dp *intel_dp = dev_priv->psr.enabled;
 957         struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
 958         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 959         u32 val;
 960
 961         if (!dev_priv->psr.active)
 962                 return;
 963
 964         if (HAS_DDI(dev_priv)) {
 965                 if (dev_priv->psr.psr2_enabled) {
 966                         val = I915_READ(EDP_PSR2_CTL);
 967                         WARN_ON(!(val & EDP_PSR2_ENABLE));
 968                         I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
 969                 } else {
 970                         val = I915_READ(EDP_PSR_CTL);
 971                         WARN_ON(!(val & EDP_PSR_ENABLE));
 972                         I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
 973                 }
 974         } else {
 975                 val = I915_READ(VLV_PSRCTL(pipe));
 976
 977                 /*
 978                  * Here we do the transition drirectly from
 979                  * PSR_state 3 (active - no Remote Frame Buffer (RFB) update) to
 980                  * PSR_state 5 (exit).
 981                  * PSR State 4 (active with single frame update) can be skipped.
 982                  * On PSR_state 5 (exit) Hardware is responsible to transition
 983                  * back to PSR_state 1 (inactive).
 984                  * Now we are at Same state after vlv_psr_enable_source.
 985                  */
 986                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
 987                 I915_WRITE(VLV_PSRCTL(pipe), val);
 988
 989                 /*
 990                  * Send AUX wake up - Spec says after transitioning to PSR
 991                  * active we have to send AUX wake up by writing 01h in DPCD
 992                  * 600h of sink device.
 993                  * XXX: This might slow down the transition, but without this
 994                  * HW doesn't complete the transition to PSR_state 1 and we
 995                  * never get the screen updated.
 996                  */
 997                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
 998                                    DP_SET_POWER_D0);
 999         }
1000
1001         dev_priv->psr.active = false;
1002 }
1003
1004 /**
1005  * intel_psr_single_frame_update - Single Frame Update
1006  * @dev_priv: i915 device
1007  * @frontbuffer_bits: frontbuffer plane tracking bits
1008  *
1009  * Some platforms support a single frame update feature that is used to
1010  * send and update only one frame on Remote Frame Buffer.
1011  * So far it is only implemented for Valleyview and Cherryview because
1012  * hardware requires this to be done before a page flip.
1013  */
1014 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1015                                    unsigned frontbuffer_bits)
1016 {
1017         struct drm_crtc *crtc;
1018         enum pipe pipe;
1019         u32 val;
1020
1021         if (!CAN_PSR(dev_priv))
1022                 return;
1023
1024         /*
1025          * Single frame update is already supported on BDW+ but it requires
1026          * many W/A and it isn't really needed.
1027          */
1028         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1029                 return;
1030
1031         mutex_lock(&dev_priv->psr.lock);
1032         if (!dev_priv->psr.enabled) {
1033                 mutex_unlock(&dev_priv->psr.lock);
1034                 return;
1035         }
1036
1037         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1038         pipe = to_intel_crtc(crtc)->pipe;
1039
1040         if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
1041                 val = I915_READ(VLV_PSRCTL(pipe));
1042
1043                 /*
1044                  * We need to set this bit before writing registers for a flip.
1045                  * This bit will be self-clear when it gets to the PSR active state.
1046                  */
1047                 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
1048         }
1049         mutex_unlock(&dev_priv->psr.lock);
1050 }
1051
1052 /**
1053  * intel_psr_invalidate - Invalidade PSR
1054  * @dev_priv: i915 device
1055  * @frontbuffer_bits: frontbuffer plane tracking bits
1056  * @origin: which operation caused the invalidate
1057  *
1058  * Since the hardware frontbuffer tracking has gaps we need to integrate
1059  * with the software frontbuffer tracking. This function gets called every
1060  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
1061  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
1062  *
1063  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
1064  */
1065 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1066                           unsigned frontbuffer_bits, enum fb_op_origin origin)
1067 {
1068         struct drm_crtc *crtc;
1069         enum pipe pipe;
1070
1071         if (!CAN_PSR(dev_priv))
1072                 return;
1073
1074         if (dev_priv->psr.has_hw_tracking && origin == ORIGIN_FLIP)
1075                 return;
1076
1077         mutex_lock(&dev_priv->psr.lock);
1078         if (!dev_priv->psr.enabled) {
1079                 mutex_unlock(&dev_priv->psr.lock);
1080                 return;
1081         }
1082
1083         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1084         pipe = to_intel_crtc(crtc)->pipe;
1085
1086         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1087         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1088
1089         if (frontbuffer_bits)
1090                 intel_psr_exit(dev_priv);
1091
1092         mutex_unlock(&dev_priv->psr.lock);
1093 }
1094
1095 /**
1096  * intel_psr_flush - Flush PSR
1097  * @dev_priv: i915 device
1098  * @frontbuffer_bits: frontbuffer plane tracking bits
1099  * @origin: which operation caused the flush
1100  *
1101  * Since the hardware frontbuffer tracking has gaps we need to integrate
1102  * with the software frontbuffer tracking. This function gets called every
1103  * time frontbuffer rendering has completed and flushed out to memory. PSR
1104  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
1105  *
1106  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
1107  */
1108 void intel_psr_flush(struct drm_i915_private *dev_priv,
1109                      unsigned frontbuffer_bits, enum fb_op_origin origin)
1110 {
1111         struct drm_crtc *crtc;
1112         enum pipe pipe;
1113
1114         if (!CAN_PSR(dev_priv))
1115                 return;
1116
1117         if (dev_priv->psr.has_hw_tracking && origin == ORIGIN_FLIP)
1118                 return;
1119
1120         mutex_lock(&dev_priv->psr.lock);
1121         if (!dev_priv->psr.enabled) {
1122                 mutex_unlock(&dev_priv->psr.lock);
1123                 return;
1124         }
1125
1126         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1127         pipe = to_intel_crtc(crtc)->pipe;
1128
1129         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1130         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
1131
1132         /* By definition flush = invalidate + flush */
1133         if (frontbuffer_bits) {
1134                 if (dev_priv->psr.psr2_enabled ||
1135                     IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1136                         intel_psr_exit(dev_priv);
1137                 } else {
1138                         /*
1139                          * Display WA #0884: all
1140                          * This documented WA for bxt can be safely applied
1141                          * broadly so we can force HW tracking to exit PSR
1142                          * instead of disabling and re-enabling.
1143                          * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1144                          * but it makes more sense write to the current active
1145                          * pipe.
1146                          */
1147                         I915_WRITE(CURSURFLIVE(pipe), 0);
1148                 }
1149         }
1150
1151         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
1152                 if (!work_busy(&dev_priv->psr.work.work))
1153                         schedule_delayed_work(&dev_priv->psr.work,
1154                                               msecs_to_jiffies(100));
1155         mutex_unlock(&dev_priv->psr.lock);
1156 }
1157
1158 /**
1159  * intel_psr_init - Init basic PSR work and mutex.
1160  * @dev_priv: i915 device private
1161  *
1162  * This function is  called only once at driver load to initialize basic
1163  * PSR stuff.
1164  */
1165 void intel_psr_init(struct drm_i915_private *dev_priv)
1166 {
1167         if (!HAS_PSR(dev_priv))
1168                 return;
1169
1170         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
1171                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
1172
1173         if (!dev_priv->psr.sink_support)
1174                 return;
1175
1176         if (i915_modparams.enable_psr == -1) {
1177                 i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
1178
1179                 /* Per platform default: all disabled. */
1180                 i915_modparams.enable_psr = 0;
1181         }
1182
1183         /* Set link_standby x link_off defaults */
1184         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1185                 /* HSW and BDW require workarounds that we don't implement. */
1186                 dev_priv->psr.link_standby = false;
1187         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1188                 /* On VLV and CHV only standby mode is supported. */
1189                 dev_priv->psr.link_standby = true;
1190         else
1191                 /* For new platforms let's respect VBT back again */
1192                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
1193
1194         /* Override link_standby x link_off defaults */
1195         if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) {
1196                 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
1197                 dev_priv->psr.link_standby = true;
1198         }
1199         if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) {
1200                 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
1201                 dev_priv->psr.link_standby = false;
1202         }
1203
1204         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
1205         mutex_init(&dev_priv->psr.lock);
1206
1207         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1208                 dev_priv->psr.enable_source = vlv_psr_enable_source;
1209                 dev_priv->psr.disable_source = vlv_psr_disable;
1210                 dev_priv->psr.enable_sink = vlv_psr_enable_sink;
1211                 dev_priv->psr.activate = vlv_psr_activate;
1212                 dev_priv->psr.setup_vsc = vlv_psr_setup_vsc;
1213         } else {
1214                 dev_priv->psr.has_hw_tracking = true;
1215                 dev_priv->psr.enable_source = hsw_psr_enable_source;
1216                 dev_priv->psr.disable_source = hsw_psr_disable;
1217                 dev_priv->psr.enable_sink = hsw_psr_enable_sink;
1218                 dev_priv->psr.activate = hsw_psr_activate;
1219                 dev_priv->psr.setup_vsc = hsw_psr_setup_vsc;
1220         }
1221 }