drivers/net/dsa/qca8k.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <[email protected]>
   4  * Copyright (C) 2011-2012 Gabor Juhos <[email protected]>
   5  * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2016 John Crispin <[email protected]>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/phy.h>
  11 #include <linux/netdevice.h>
  12 #include <net/dsa.h>
  13 #include <linux/of_net.h>
  14 #include <linux/of_mdio.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/if_bridge.h>
  17 #include <linux/mdio.h>
  18 #include <linux/phylink.h>
  19 #include <linux/gpio/consumer.h>
  20 #include <linux/etherdevice.h>
  21
  22 #include "qca8k.h"
  23
  24 #define MIB_DESC(_s, _o, _n)    \
  25         {                       \
  26                 .size = (_s),   \
  27                 .offset = (_o), \
  28                 .name = (_n),   \
  29         }
  30
  31 static const struct qca8k_mib_desc ar8327_mib[] = {
  32         MIB_DESC(1, 0x00, "RxBroad"),
  33         MIB_DESC(1, 0x04, "RxPause"),
  34         MIB_DESC(1, 0x08, "RxMulti"),
  35         MIB_DESC(1, 0x0c, "RxFcsErr"),
  36         MIB_DESC(1, 0x10, "RxAlignErr"),
  37         MIB_DESC(1, 0x14, "RxRunt"),
  38         MIB_DESC(1, 0x18, "RxFragment"),
  39         MIB_DESC(1, 0x1c, "Rx64Byte"),
  40         MIB_DESC(1, 0x20, "Rx128Byte"),
  41         MIB_DESC(1, 0x24, "Rx256Byte"),
  42         MIB_DESC(1, 0x28, "Rx512Byte"),
  43         MIB_DESC(1, 0x2c, "Rx1024Byte"),
  44         MIB_DESC(1, 0x30, "Rx1518Byte"),
  45         MIB_DESC(1, 0x34, "RxMaxByte"),
  46         MIB_DESC(1, 0x38, "RxTooLong"),
  47         MIB_DESC(2, 0x3c, "RxGoodByte"),
  48         MIB_DESC(2, 0x44, "RxBadByte"),
  49         MIB_DESC(1, 0x4c, "RxOverFlow"),
  50         MIB_DESC(1, 0x50, "Filtered"),
  51         MIB_DESC(1, 0x54, "TxBroad"),
  52         MIB_DESC(1, 0x58, "TxPause"),
  53         MIB_DESC(1, 0x5c, "TxMulti"),
  54         MIB_DESC(1, 0x60, "TxUnderRun"),
  55         MIB_DESC(1, 0x64, "Tx64Byte"),
  56         MIB_DESC(1, 0x68, "Tx128Byte"),
  57         MIB_DESC(1, 0x6c, "Tx256Byte"),
  58         MIB_DESC(1, 0x70, "Tx512Byte"),
  59         MIB_DESC(1, 0x74, "Tx1024Byte"),
  60         MIB_DESC(1, 0x78, "Tx1518Byte"),
  61         MIB_DESC(1, 0x7c, "TxMaxByte"),
  62         MIB_DESC(1, 0x80, "TxOverSize"),
  63         MIB_DESC(2, 0x84, "TxByte"),
  64         MIB_DESC(1, 0x8c, "TxCollision"),
  65         MIB_DESC(1, 0x90, "TxAbortCol"),
  66         MIB_DESC(1, 0x94, "TxMultiCol"),
  67         MIB_DESC(1, 0x98, "TxSingleCol"),
  68         MIB_DESC(1, 0x9c, "TxExcDefer"),
  69         MIB_DESC(1, 0xa0, "TxDefer"),
  70         MIB_DESC(1, 0xa4, "TxLateCol"),
  71 };
  72
  73 /* The 32bit switch registers are accessed indirectly. To achieve this we need
  74  * to set the page of the register. Track the last page that was set to reduce
  75  * mdio writes
  76  */
  77 static u16 qca8k_current_page = 0xffff;
  78
  79 static void
  80 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  81 {
  82         regaddr >>= 1;
  83         *r1 = regaddr & 0x1e;
  84
  85         regaddr >>= 5;
  86         *r2 = regaddr & 0x7;
  87
  88         regaddr >>= 3;
  89         *page = regaddr & 0x3ff;
  90 }
  91
  92 static int
  93 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  94 {
  95         int ret;
  96
  97         ret = bus->read(bus, phy_id, regnum);
  98         if (ret >= 0) {
  99                 *val = ret;
 100                 ret = bus->read(bus, phy_id, regnum + 1);
 101                 *val |= ret << 16;
 102         }
 103
 104         if (ret < 0) {
 105                 dev_err_ratelimited(&bus->dev,
 106                                     "failed to read qca8k 32bit register\n");
 107                 *val = 0;
 108                 return ret;
 109         }
 110
 111         return 0;
 112 }
 113
 114 static void
 115 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 116 {
 117         u16 lo, hi;
 118         int ret;
 119
 120         lo = val & 0xffff;
 121         hi = (u16)(val >> 16);
 122
 123         ret = bus->write(bus, phy_id, regnum, lo);
 124         if (ret >= 0)
 125                 ret = bus->write(bus, phy_id, regnum + 1, hi);
 126         if (ret < 0)
 127                 dev_err_ratelimited(&bus->dev,
 128                                     "failed to write qca8k 32bit register\n");
 129 }
 130
 131 static int
 132 qca8k_set_page(struct mii_bus *bus, u16 page)
 133 {
 134         int ret;
 135
 136         if (page == qca8k_current_page)
 137                 return 0;
 138
 139         ret = bus->write(bus, 0x18, 0, page);
 140         if (ret < 0) {
 141                 dev_err_ratelimited(&bus->dev,
 142                                     "failed to set qca8k page\n");
 143                 return ret;
 144         }
 145
 146         qca8k_current_page = page;
 147         usleep_range(1000, 2000);
 148         return 0;
 149 }
 150
 151 static int
 152 qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
 153 {
 154         struct mii_bus *bus = priv->bus;
 155         u16 r1, r2, page;
 156         int ret;
 157
 158         qca8k_split_addr(reg, &r1, &r2, &page);
 159
 160         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 161
 162         ret = qca8k_set_page(bus, page);
 163         if (ret < 0)
 164                 goto exit;
 165
 166         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
 167
 168 exit:
 169         mutex_unlock(&bus->mdio_lock);
 170         return ret;
 171 }
 172
 173 static int
 174 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
 175 {
 176         struct mii_bus *bus = priv->bus;
 177         u16 r1, r2, page;
 178         int ret;
 179
 180         qca8k_split_addr(reg, &r1, &r2, &page);
 181
 182         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 183
 184         ret = qca8k_set_page(bus, page);
 185         if (ret < 0)
 186                 goto exit;
 187
 188         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 189
 190 exit:
 191         mutex_unlock(&bus->mdio_lock);
 192         return ret;
 193 }
 194
 195 static int
 196 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
 197 {
 198         struct mii_bus *bus = priv->bus;
 199         u16 r1, r2, page;
 200         u32 val;
 201         int ret;
 202
 203         qca8k_split_addr(reg, &r1, &r2, &page);
 204
 205         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 206
 207         ret = qca8k_set_page(bus, page);
 208         if (ret < 0)
 209                 goto exit;
 210
 211         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 212         if (ret < 0)
 213                 goto exit;
 214
 215         val &= ~mask;
 216         val |= write_val;
 217         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 218
 219 exit:
 220         mutex_unlock(&bus->mdio_lock);
 221
 222         return ret;
 223 }
 224
 225 static int
 226 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
 227 {
 228         return qca8k_rmw(priv, reg, 0, val);
 229 }
 230
 231 static int
 232 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
 233 {
 234         return qca8k_rmw(priv, reg, val, 0);
 235 }
 236
 237 static int
 238 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 239 {
 240         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 241
 242         return qca8k_read(priv, reg, val);
 243 }
 244
 245 static int
 246 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 247 {
 248         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 249
 250         return qca8k_write(priv, reg, val);
 251 }
 252
 253 static const struct regmap_range qca8k_readable_ranges[] = {
 254         regmap_reg_range(0x0000, 0x00e4), /* Global control */
 255         regmap_reg_range(0x0100, 0x0168), /* EEE control */
 256         regmap_reg_range(0x0200, 0x0270), /* Parser control */
 257         regmap_reg_range(0x0400, 0x0454), /* ACL */
 258         regmap_reg_range(0x0600, 0x0718), /* Lookup */
 259         regmap_reg_range(0x0800, 0x0b70), /* QM */
 260         regmap_reg_range(0x0c00, 0x0c80), /* PKT */
 261         regmap_reg_range(0x0e00, 0x0e98), /* L3 */
 262         regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
 263         regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
 264         regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
 265         regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
 266         regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
 267         regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
 268         regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
 269
 270 };
 271
 272 static const struct regmap_access_table qca8k_readable_table = {
 273         .yes_ranges = qca8k_readable_ranges,
 274         .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
 275 };
 276
 277 static struct regmap_config qca8k_regmap_config = {
 278         .reg_bits = 16,
 279         .val_bits = 32,
 280         .reg_stride = 4,
 281         .max_register = 0x16ac, /* end MIB - Port6 range */
 282         .reg_read = qca8k_regmap_read,
 283         .reg_write = qca8k_regmap_write,
 284         .rd_table = &qca8k_readable_table,
 285 };
 286
 287 static int
 288 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
 289 {
 290         int ret, ret1;
 291         u32 val;
 292
 293         ret = read_poll_timeout(qca8k_read, ret1, !(val & mask),
 294                                 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 295                                 priv, reg, &val);
 296
 297         /* Check if qca8k_read has failed for a different reason
 298          * before returning -ETIMEDOUT
 299          */
 300         if (ret < 0 && ret1 < 0)
 301                 return ret1;
 302
 303         return ret;
 304 }
 305
 306 static int
 307 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
 308 {
 309         u32 reg[4], val;
 310         int i, ret;
 311
 312         /* load the ARL table into an array */
 313         for (i = 0; i < 4; i++) {
 314                 ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
 315                 if (ret < 0)
 316                         return ret;
 317
 318                 reg[i] = val;
 319         }
 320
 321         /* vid - 83:72 */
 322         fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
 323         /* aging - 67:64 */
 324         fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
 325         /* portmask - 54:48 */
 326         fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
 327         /* mac - 47:0 */
 328         fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
 329         fdb->mac[1] = reg[1] & 0xff;
 330         fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
 331         fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
 332         fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
 333         fdb->mac[5] = reg[0] & 0xff;
 334
 335         return 0;
 336 }
 337
 338 static void
 339 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
 340                 u8 aging)
 341 {
 342         u32 reg[3] = { 0 };
 343         int i;
 344
 345         /* vid - 83:72 */
 346         reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
 347         /* aging - 67:64 */
 348         reg[2] |= aging & QCA8K_ATU_STATUS_M;
 349         /* portmask - 54:48 */
 350         reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
 351         /* mac - 47:0 */
 352         reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
 353         reg[1] |= mac[1];
 354         reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
 355         reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
 356         reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
 357         reg[0] |= mac[5];
 358
 359         /* load the array into the ARL table */
 360         for (i = 0; i < 3; i++)
 361                 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
 362 }
 363
 364 static int
 365 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
 366 {
 367         u32 reg;
 368         int ret;
 369
 370         /* Set the command and FDB index */
 371         reg = QCA8K_ATU_FUNC_BUSY;
 372         reg |= cmd;
 373         if (port >= 0) {
 374                 reg |= QCA8K_ATU_FUNC_PORT_EN;
 375                 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
 376         }
 377
 378         /* Write the function register triggering the table access */
 379         ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
 380         if (ret)
 381                 return ret;
 382
 383         /* wait for completion */
 384         ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
 385         if (ret)
 386                 return ret;
 387
 388         /* Check for table full violation when adding an entry */
 389         if (cmd == QCA8K_FDB_LOAD) {
 390                 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
 391                 if (ret < 0)
 392                         return ret;
 393                 if (reg & QCA8K_ATU_FUNC_FULL)
 394                         return -1;
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int
 401 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
 402 {
 403         int ret;
 404
 405         qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
 406         ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
 407         if (ret < 0)
 408                 return ret;
 409
 410         return qca8k_fdb_read(priv, fdb);
 411 }
 412
 413 static int
 414 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
 415               u16 vid, u8 aging)
 416 {
 417         int ret;
 418
 419         mutex_lock(&priv->reg_mutex);
 420         qca8k_fdb_write(priv, vid, port_mask, mac, aging);
 421         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 422         mutex_unlock(&priv->reg_mutex);
 423
 424         return ret;
 425 }
 426
 427 static int
 428 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
 429 {
 430         int ret;
 431
 432         mutex_lock(&priv->reg_mutex);
 433         qca8k_fdb_write(priv, vid, port_mask, mac, 0);
 434         ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 435         mutex_unlock(&priv->reg_mutex);
 436
 437         return ret;
 438 }
 439
 440 static void
 441 qca8k_fdb_flush(struct qca8k_priv *priv)
 442 {
 443         mutex_lock(&priv->reg_mutex);
 444         qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
 445         mutex_unlock(&priv->reg_mutex);
 446 }
 447
 448 static int
 449 qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
 450 {
 451         u32 reg;
 452         int ret;
 453
 454         /* Set the command and VLAN index */
 455         reg = QCA8K_VTU_FUNC1_BUSY;
 456         reg |= cmd;
 457         reg |= vid << QCA8K_VTU_FUNC1_VID_S;
 458
 459         /* Write the function register triggering the table access */
 460         ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
 461         if (ret)
 462                 return ret;
 463
 464         /* wait for completion */
 465         ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
 466         if (ret)
 467                 return ret;
 468
 469         /* Check for table full violation when adding an entry */
 470         if (cmd == QCA8K_VLAN_LOAD) {
 471                 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
 472                 if (ret < 0)
 473                         return ret;
 474                 if (reg & QCA8K_VTU_FUNC1_FULL)
 475                         return -ENOMEM;
 476         }
 477
 478         return 0;
 479 }
 480
 481 static int
 482 qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
 483 {
 484         u32 reg;
 485         int ret;
 486
 487         /*
 488            We do the right thing with VLAN 0 and treat it as untagged while
 489            preserving the tag on egress.
 490          */
 491         if (vid == 0)
 492                 return 0;
 493
 494         mutex_lock(&priv->reg_mutex);
 495         ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
 496         if (ret < 0)
 497                 goto out;
 498
 499         ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
 500         if (ret < 0)
 501                 goto out;
 502         reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
 503         reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
 504         if (untagged)
 505                 reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
 506                                 QCA8K_VTU_FUNC0_EG_MODE_S(port);
 507         else
 508                 reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
 509                                 QCA8K_VTU_FUNC0_EG_MODE_S(port);
 510
 511         ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
 512         if (ret)
 513                 goto out;
 514         ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 515
 516 out:
 517         mutex_unlock(&priv->reg_mutex);
 518
 519         return ret;
 520 }
 521
 522 static int
 523 qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
 524 {
 525         u32 reg, mask;
 526         int ret, i;
 527         bool del;
 528
 529         mutex_lock(&priv->reg_mutex);
 530         ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
 531         if (ret < 0)
 532                 goto out;
 533
 534         ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
 535         if (ret < 0)
 536                 goto out;
 537         reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
 538         reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
 539                         QCA8K_VTU_FUNC0_EG_MODE_S(port);
 540
 541         /* Check if we're the last member to be removed */
 542         del = true;
 543         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 544                 mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
 545                 mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
 546
 547                 if ((reg & mask) != mask) {
 548                         del = false;
 549                         break;
 550                 }
 551         }
 552
 553         if (del) {
 554                 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
 555         } else {
 556                 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
 557                 if (ret)
 558                         goto out;
 559                 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 560         }
 561
 562 out:
 563         mutex_unlock(&priv->reg_mutex);
 564
 565         return ret;
 566 }
 567
 568 static int
 569 qca8k_mib_init(struct qca8k_priv *priv)
 570 {
 571         int ret;
 572
 573         mutex_lock(&priv->reg_mutex);
 574         ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
 575         if (ret)
 576                 goto exit;
 577
 578         ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
 579         if (ret)
 580                 goto exit;
 581
 582         ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
 583         if (ret)
 584                 goto exit;
 585
 586         ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
 587
 588 exit:
 589         mutex_unlock(&priv->reg_mutex);
 590         return ret;
 591 }
 592
 593 static void
 594 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
 595 {
 596         u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
 597
 598         /* Port 0 and 6 have no internal PHY */
 599         if (port > 0 && port < 6)
 600                 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
 601
 602         if (enable)
 603                 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
 604         else
 605                 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
 606 }
 607
 608 static u32
 609 qca8k_port_to_phy(int port)
 610 {
 611         /* From Andrew Lunn:
 612          * Port 0 has no internal phy.
 613          * Port 1 has an internal PHY at MDIO address 0.
 614          * Port 2 has an internal PHY at MDIO address 1.
 615          * ...
 616          * Port 5 has an internal PHY at MDIO address 4.
 617          * Port 6 has no internal PHY.
 618          */
 619
 620         return port - 1;
 621 }
 622
 623 static int
 624 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
 625 {
 626         u16 r1, r2, page;
 627         u32 val;
 628         int ret, ret1;
 629
 630         qca8k_split_addr(reg, &r1, &r2, &page);
 631
 632         ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
 633                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 634                                 bus, 0x10 | r2, r1, &val);
 635
 636         /* Check if qca8k_read has failed for a different reason
 637          * before returnting -ETIMEDOUT
 638          */
 639         if (ret < 0 && ret1 < 0)
 640                 return ret1;
 641
 642         return ret;
 643 }
 644
 645 static int
 646 qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data)
 647 {
 648         u16 r1, r2, page;
 649         u32 val;
 650         int ret;
 651
 652         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 653                 return -EINVAL;
 654
 655         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 656               QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 657               QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
 658               QCA8K_MDIO_MASTER_DATA(data);
 659
 660         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 661
 662         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 663
 664         ret = qca8k_set_page(bus, page);
 665         if (ret)
 666                 goto exit;
 667
 668         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 669
 670         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 671                                    QCA8K_MDIO_MASTER_BUSY);
 672
 673 exit:
 674         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 675         qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 676
 677         mutex_unlock(&bus->mdio_lock);
 678
 679         return ret;
 680 }
 681
 682 static int
 683 qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum)
 684 {
 685         u16 r1, r2, page;
 686         u32 val;
 687         int ret;
 688
 689         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 690                 return -EINVAL;
 691
 692         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 693               QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 694               QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 695
 696         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 697
 698         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 699
 700         ret = qca8k_set_page(bus, page);
 701         if (ret)
 702                 goto exit;
 703
 704         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 705
 706         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 707                                    QCA8K_MDIO_MASTER_BUSY);
 708         if (ret)
 709                 goto exit;
 710
 711         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 712
 713 exit:
 714         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 715         qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 716
 717         mutex_unlock(&bus->mdio_lock);
 718
 719         if (ret >= 0)
 720                 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
 721
 722         return ret;
 723 }
 724
 725 static int
 726 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
 727 {
 728         struct qca8k_priv *priv = slave_bus->priv;
 729         struct mii_bus *bus = priv->bus;
 730
 731         return qca8k_mdio_write(bus, phy, regnum, data);
 732 }
 733
 734 static int
 735 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
 736 {
 737         struct qca8k_priv *priv = slave_bus->priv;
 738         struct mii_bus *bus = priv->bus;
 739
 740         return qca8k_mdio_read(bus, phy, regnum);
 741 }
 742
 743 static int
 744 qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
 745 {
 746         struct qca8k_priv *priv = ds->priv;
 747
 748         /* Check if the legacy mapping should be used and the
 749          * port is not correctly mapped to the right PHY in the
 750          * devicetree
 751          */
 752         if (priv->legacy_phy_port_mapping)
 753                 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 754
 755         return qca8k_mdio_write(priv->bus, port, regnum, data);
 756 }
 757
 758 static int
 759 qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
 760 {
 761         struct qca8k_priv *priv = ds->priv;
 762         int ret;
 763
 764         /* Check if the legacy mapping should be used and the
 765          * port is not correctly mapped to the right PHY in the
 766          * devicetree
 767          */
 768         if (priv->legacy_phy_port_mapping)
 769                 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 770
 771         ret = qca8k_mdio_read(priv->bus, port, regnum);
 772
 773         if (ret < 0)
 774                 return 0xffff;
 775
 776         return ret;
 777 }
 778
 779 static int
 780 qca8k_mdio_register(struct qca8k_priv *priv, struct device_node *mdio)
 781 {
 782         struct dsa_switch *ds = priv->ds;
 783         struct mii_bus *bus;
 784
 785         bus = devm_mdiobus_alloc(ds->dev);
 786
 787         if (!bus)
 788                 return -ENOMEM;
 789
 790         bus->priv = (void *)priv;
 791         bus->name = "qca8k slave mii";
 792         bus->read = qca8k_internal_mdio_read;
 793         bus->write = qca8k_internal_mdio_write;
 794         snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d",
 795                  ds->index);
 796
 797         bus->parent = ds->dev;
 798         bus->phy_mask = ~ds->phys_mii_mask;
 799
 800         ds->slave_mii_bus = bus;
 801
 802         return devm_of_mdiobus_register(priv->dev, bus, mdio);
 803 }
 804
 805 static int
 806 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 807 {
 808         u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
 809         struct device_node *ports, *port, *mdio;
 810         phy_interface_t mode;
 811         int err;
 812
 813         ports = of_get_child_by_name(priv->dev->of_node, "ports");
 814         if (!ports)
 815                 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
 816
 817         if (!ports)
 818                 return -EINVAL;
 819
 820         for_each_available_child_of_node(ports, port) {
 821                 err = of_property_read_u32(port, "reg", &reg);
 822                 if (err) {
 823                         of_node_put(port);
 824                         of_node_put(ports);
 825                         return err;
 826                 }
 827
 828                 if (!dsa_is_user_port(priv->ds, reg))
 829                         continue;
 830
 831                 of_get_phy_mode(port, &mode);
 832
 833                 if (of_property_read_bool(port, "phy-handle") &&
 834                     mode != PHY_INTERFACE_MODE_INTERNAL)
 835                         external_mdio_mask |= BIT(reg);
 836                 else
 837                         internal_mdio_mask |= BIT(reg);
 838         }
 839
 840         of_node_put(ports);
 841         if (!external_mdio_mask && !internal_mdio_mask) {
 842                 dev_err(priv->dev, "no PHYs are defined.\n");
 843                 return -EINVAL;
 844         }
 845
 846         /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
 847          * the MDIO_MASTER register also _disconnects_ the external MDC
 848          * passthrough to the internal PHYs. It's not possible to use both
 849          * configurations at the same time!
 850          *
 851          * Because this came up during the review process:
 852          * If the external mdio-bus driver is capable magically disabling
 853          * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
 854          * accessors for the time being, it would be possible to pull this
 855          * off.
 856          */
 857         if (!!external_mdio_mask && !!internal_mdio_mask) {
 858                 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
 859                 return -EINVAL;
 860         }
 861
 862         if (external_mdio_mask) {
 863                 /* Make sure to disable the internal mdio bus in cases
 864                  * a dt-overlay and driver reload changed the configuration
 865                  */
 866
 867                 return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
 868                                        QCA8K_MDIO_MASTER_EN);
 869         }
 870
 871         /* Check if the devicetree declare the port:phy mapping */
 872         mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
 873         if (of_device_is_available(mdio)) {
 874                 err = qca8k_mdio_register(priv, mdio);
 875                 if (err)
 876                         of_node_put(mdio);
 877
 878                 return err;
 879         }
 880
 881         /* If a mapping can't be found the legacy mapping is used,
 882          * using the qca8k_port_to_phy function
 883          */
 884         priv->legacy_phy_port_mapping = true;
 885         priv->ops.phy_read = qca8k_phy_read;
 886         priv->ops.phy_write = qca8k_phy_write;
 887
 888         return 0;
 889 }
 890
 891 static int
 892 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
 893 {
 894         u32 mask = 0;
 895         int ret = 0;
 896
 897         /* SoC specific settings for ipq8064.
 898          * If more device require this consider adding
 899          * a dedicated binding.
 900          */
 901         if (of_machine_is_compatible("qcom,ipq8064"))
 902                 mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
 903
 904         /* SoC specific settings for ipq8065 */
 905         if (of_machine_is_compatible("qcom,ipq8065"))
 906                 mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
 907
 908         if (mask) {
 909                 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
 910                                 QCA8K_MAC_PWR_RGMII0_1_8V |
 911                                 QCA8K_MAC_PWR_RGMII1_1_8V,
 912                                 mask);
 913         }
 914
 915         return ret;
 916 }
 917
 918 static int qca8k_find_cpu_port(struct dsa_switch *ds)
 919 {
 920         struct qca8k_priv *priv = ds->priv;
 921
 922         /* Find the connected cpu port. Valid port are 0 or 6 */
 923         if (dsa_is_cpu_port(ds, 0))
 924                 return 0;
 925
 926         dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
 927
 928         if (dsa_is_cpu_port(ds, 6))
 929                 return 6;
 930
 931         return -EINVAL;
 932 }
 933
 934 static int
 935 qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
 936 {
 937         struct device_node *node = priv->dev->of_node;
 938         const struct qca8k_match_data *data;
 939         u32 val = 0;
 940         int ret;
 941
 942         /* QCA8327 require to set to the correct mode.
 943          * His bigger brother QCA8328 have the 172 pin layout.
 944          * Should be applied by default but we set this just to make sure.
 945          */
 946         if (priv->switch_id == QCA8K_ID_QCA8327) {
 947                 data = of_device_get_match_data(priv->dev);
 948
 949                 /* Set the correct package of 148 pin for QCA8327 */
 950                 if (data->reduced_package)
 951                         val |= QCA8327_PWS_PACKAGE148_EN;
 952
 953                 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
 954                                 val);
 955                 if (ret)
 956                         return ret;
 957         }
 958
 959         if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
 960                 val |= QCA8K_PWS_POWER_ON_SEL;
 961
 962         if (of_property_read_bool(node, "qca,led-open-drain")) {
 963                 if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
 964                         dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
 965                         return -EINVAL;
 966                 }
 967
 968                 val |= QCA8K_PWS_LED_OPEN_EN_CSR;
 969         }
 970
 971         return qca8k_rmw(priv, QCA8K_REG_PWS,
 972                         QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
 973                         val);
 974 }
 975
 976 static int
 977 qca8k_parse_port_config(struct qca8k_priv *priv)
 978 {
 979         int port, cpu_port_index = -1, ret;
 980         struct device_node *port_dn;
 981         phy_interface_t mode;
 982         struct dsa_port *dp;
 983         u32 delay;
 984
 985         /* We have 2 CPU port. Check them */
 986         for (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {
 987                 /* Skip every other port */
 988                 if (port != 0 && port != 6)
 989                         continue;
 990
 991                 dp = dsa_to_port(priv->ds, port);
 992                 port_dn = dp->dn;
 993                 cpu_port_index++;
 994
 995                 if (!of_device_is_available(port_dn))
 996                         continue;
 997
 998                 ret = of_get_phy_mode(port_dn, &mode);
 999                 if (ret)
1000                         continue;
1001
1002                 switch (mode) {
1003                 case PHY_INTERFACE_MODE_RGMII:
1004                 case PHY_INTERFACE_MODE_RGMII_ID:
1005                 case PHY_INTERFACE_MODE_RGMII_TXID:
1006                 case PHY_INTERFACE_MODE_RGMII_RXID:
1007                 case PHY_INTERFACE_MODE_SGMII:
1008                         delay = 0;
1009
1010                         if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
1011                                 /* Switch regs accept value in ns, convert ps to ns */
1012                                 delay = delay / 1000;
1013                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1014                                  mode == PHY_INTERFACE_MODE_RGMII_TXID)
1015                                 delay = 1;
1016
1017                         if (delay > QCA8K_MAX_DELAY) {
1018                                 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
1019                                 delay = 3;
1020                         }
1021
1022                         priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
1023
1024                         delay = 0;
1025
1026                         if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
1027                                 /* Switch regs accept value in ns, convert ps to ns */
1028                                 delay = delay / 1000;
1029                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1030                                  mode == PHY_INTERFACE_MODE_RGMII_RXID)
1031                                 delay = 2;
1032
1033                         if (delay > QCA8K_MAX_DELAY) {
1034                                 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
1035                                 delay = 3;
1036                         }
1037
1038                         priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
1039
1040                         /* Skip sgmii parsing for rgmii* mode */
1041                         if (mode == PHY_INTERFACE_MODE_RGMII ||
1042                             mode == PHY_INTERFACE_MODE_RGMII_ID ||
1043                             mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1044                             mode == PHY_INTERFACE_MODE_RGMII_RXID)
1045                                 break;
1046
1047                         if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
1048                                 priv->ports_config.sgmii_tx_clk_falling_edge = true;
1049
1050                         if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
1051                                 priv->ports_config.sgmii_rx_clk_falling_edge = true;
1052
1053                         if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
1054                                 priv->ports_config.sgmii_enable_pll = true;
1055
1056                                 if (priv->switch_id == QCA8K_ID_QCA8327) {
1057                                         dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
1058                                         priv->ports_config.sgmii_enable_pll = false;
1059                                 }
1060
1061                                 if (priv->switch_revision < 2)
1062                                         dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
1063                         }
1064
1065                         break;
1066                 default:
1067                         continue;
1068                 }
1069         }
1070
1071         return 0;
1072 }
1073
1074 static int
1075 qca8k_setup(struct dsa_switch *ds)
1076 {
1077         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1078         int cpu_port, ret, i;
1079         u32 mask;
1080
1081         cpu_port = qca8k_find_cpu_port(ds);
1082         if (cpu_port < 0) {
1083                 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
1084                 return cpu_port;
1085         }
1086
1087         /* Parse CPU port config to be later used in phy_link mac_config */
1088         ret = qca8k_parse_port_config(priv);
1089         if (ret)
1090                 return ret;
1091
1092         mutex_init(&priv->reg_mutex);
1093
1094         /* Start by setting up the register mapping */
1095         priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
1096                                         &qca8k_regmap_config);
1097         if (IS_ERR(priv->regmap))
1098                 dev_warn(priv->dev, "regmap initialization failed");
1099
1100         ret = qca8k_setup_mdio_bus(priv);
1101         if (ret)
1102                 return ret;
1103
1104         ret = qca8k_setup_of_pws_reg(priv);
1105         if (ret)
1106                 return ret;
1107
1108         ret = qca8k_setup_mac_pwr_sel(priv);
1109         if (ret)
1110                 return ret;
1111
1112         /* Make sure MAC06 is disabled */
1113         ret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL,
1114                               QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
1115         if (ret) {
1116                 dev_err(priv->dev, "failed disabling MAC06 exchange");
1117                 return ret;
1118         }
1119
1120         /* Enable CPU Port */
1121         ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
1122                             QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1123         if (ret) {
1124                 dev_err(priv->dev, "failed enabling CPU port");
1125                 return ret;
1126         }
1127
1128         /* Enable MIB counters */
1129         ret = qca8k_mib_init(priv);
1130         if (ret)
1131                 dev_warn(priv->dev, "mib init failed");
1132
1133         /* Initial setup of all ports */
1134         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1135                 /* Disable forwarding by default on all ports */
1136                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1137                                 QCA8K_PORT_LOOKUP_MEMBER, 0);
1138                 if (ret)
1139                         return ret;
1140
1141                 /* Enable QCA header mode on all cpu ports */
1142                 if (dsa_is_cpu_port(ds, i)) {
1143                         ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
1144                                           QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
1145                                           QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
1146                         if (ret) {
1147                                 dev_err(priv->dev, "failed enabling QCA header mode");
1148                                 return ret;
1149                         }
1150                 }
1151
1152                 /* Disable MAC by default on all user ports */
1153                 if (dsa_is_user_port(ds, i))
1154                         qca8k_port_set_status(priv, i, 0);
1155         }
1156
1157         /* Forward all unknown frames to CPU port for Linux processing
1158          * Notice that in multi-cpu config only one port should be set
1159          * for igmp, unknown, multicast and broadcast packet
1160          */
1161         ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1162                           BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
1163                           BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
1164                           BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
1165                           BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
1166         if (ret)
1167                 return ret;
1168
1169         /* Setup connection between CPU port & user ports
1170          * Configure specific switch configuration for ports
1171          */
1172         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1173                 /* CPU port gets connected to all user ports of the switch */
1174                 if (dsa_is_cpu_port(ds, i)) {
1175                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1176                                         QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1177                         if (ret)
1178                                 return ret;
1179                 }
1180
1181                 /* Individual user ports get connected to CPU port only */
1182                 if (dsa_is_user_port(ds, i)) {
1183                         int shift = 16 * (i % 2);
1184
1185                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1186                                         QCA8K_PORT_LOOKUP_MEMBER,
1187                                         BIT(cpu_port));
1188                         if (ret)
1189                                 return ret;
1190
1191                         /* Enable ARP Auto-learning by default */
1192                         ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1193                                             QCA8K_PORT_LOOKUP_LEARN);
1194                         if (ret)
1195                                 return ret;
1196
1197                         /* For port based vlans to work we need to set the
1198                          * default egress vid
1199                          */
1200                         ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
1201                                         0xfff << shift,
1202                                         QCA8K_PORT_VID_DEF << shift);
1203                         if (ret)
1204                                 return ret;
1205
1206                         ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
1207                                           QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1208                                           QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1209                         if (ret)
1210                                 return ret;
1211                 }
1212
1213                 /* The port 5 of the qca8337 have some problem in flood condition. The
1214                  * original legacy driver had some specific buffer and priority settings
1215                  * for the different port suggested by the QCA switch team. Add this
1216                  * missing settings to improve switch stability under load condition.
1217                  * This problem is limited to qca8337 and other qca8k switch are not affected.
1218                  */
1219                 if (priv->switch_id == QCA8K_ID_QCA8337) {
1220                         switch (i) {
1221                         /* The 2 CPU port and port 5 requires some different
1222                          * priority than any other ports.
1223                          */
1224                         case 0:
1225                         case 5:
1226                         case 6:
1227                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1228                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1229                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1230                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1231                                         QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1232                                         QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1233                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1234                                 break;
1235                         default:
1236                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1237                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1238                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1239                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1240                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1241                         }
1242                         qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
1243
1244                         mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1245                         QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1246                         QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1247                         QCA8K_PORT_HOL_CTRL1_WRED_EN;
1248                         qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
1249                                   QCA8K_PORT_HOL_CTRL1_ING_BUF |
1250                                   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1251                                   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1252                                   QCA8K_PORT_HOL_CTRL1_WRED_EN,
1253                                   mask);
1254                 }
1255
1256                 /* Set initial MTU for every port.
1257                  * We have only have a general MTU setting. So track
1258                  * every port and set the max across all port.
1259                  * Set per port MTU to 1500 as the MTU change function
1260                  * will add the overhead and if its set to 1518 then it
1261                  * will apply the overhead again and we will end up with
1262                  * MTU of 1536 instead of 1518
1263                  */
1264                 priv->port_mtu[i] = ETH_DATA_LEN;
1265         }
1266
1267         /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1268         if (priv->switch_id == QCA8K_ID_QCA8327) {
1269                 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1270                        QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1271                 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1272                           QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
1273                           QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
1274                           mask);
1275         }
1276
1277         /* Setup our port MTUs to match power on defaults */
1278         ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1279         if (ret)
1280                 dev_warn(priv->dev, "failed setting MTU settings");
1281
1282         /* Flush the FDB table */
1283         qca8k_fdb_flush(priv);
1284
1285         /* We don't have interrupts for link changes, so we need to poll */
1286         ds->pcs_poll = true;
1287
1288         return 0;
1289 }
1290
1291 static void
1292 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
1293                                       u32 reg)
1294 {
1295         u32 delay, val = 0;
1296         int ret;
1297
1298         /* Delay can be declared in 3 different way.
1299          * Mode to rgmii and internal-delay standard binding defined
1300          * rgmii-id or rgmii-tx/rx phy mode set.
1301          * The parse logic set a delay different than 0 only when one
1302          * of the 3 different way is used. In all other case delay is
1303          * not enabled. With ID or TX/RXID delay is enabled and set
1304          * to the default and recommended value.
1305          */
1306         if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
1307                 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
1308
1309                 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
1310                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
1311         }
1312
1313         if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
1314                 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
1315
1316                 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
1317                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
1318         }
1319
1320         /* Set RGMII delay based on the selected values */
1321         ret = qca8k_rmw(priv, reg,
1322                         QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
1323                         QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
1324                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1325                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
1326                         val);
1327         if (ret)
1328                 dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
1329                         cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
1330 }
1331
1332 static void
1333 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1334                          const struct phylink_link_state *state)
1335 {
1336         struct qca8k_priv *priv = ds->priv;
1337         int cpu_port_index, ret;
1338         u32 reg, val;
1339
1340         switch (port) {
1341         case 0: /* 1st CPU port */
1342                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1343                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1344                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1345                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1346                     state->interface != PHY_INTERFACE_MODE_SGMII)
1347                         return;
1348
1349                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1350                 cpu_port_index = QCA8K_CPU_PORT0;
1351                 break;
1352         case 1:
1353         case 2:
1354         case 3:
1355         case 4:
1356         case 5:
1357                 /* Internal PHY, nothing to do */
1358                 return;
1359         case 6: /* 2nd CPU port / external PHY */
1360                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1361                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1362                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1363                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1364                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1365                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1366                         return;
1367
1368                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1369                 cpu_port_index = QCA8K_CPU_PORT6;
1370                 break;
1371         default:
1372                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1373                 return;
1374         }
1375
1376         if (port != 6 && phylink_autoneg_inband(mode)) {
1377                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1378                         __func__);
1379                 return;
1380         }
1381
1382         switch (state->interface) {
1383         case PHY_INTERFACE_MODE_RGMII:
1384         case PHY_INTERFACE_MODE_RGMII_ID:
1385         case PHY_INTERFACE_MODE_RGMII_TXID:
1386         case PHY_INTERFACE_MODE_RGMII_RXID:
1387                 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1388
1389                 /* Configure rgmii delay */
1390                 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1391
1392                 /* QCA8337 requires to set rgmii rx delay for all ports.
1393                  * This is enabled through PORT5_PAD_CTRL for all ports,
1394                  * rather than individual port registers.
1395                  */
1396                 if (priv->switch_id == QCA8K_ID_QCA8337)
1397                         qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1398                                     QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1399                 break;
1400         case PHY_INTERFACE_MODE_SGMII:
1401         case PHY_INTERFACE_MODE_1000BASEX:
1402                 /* Enable SGMII on the port */
1403                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1404
1405                 /* Enable/disable SerDes auto-negotiation as necessary */
1406                 ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
1407                 if (ret)
1408                         return;
1409                 if (phylink_autoneg_inband(mode))
1410                         val &= ~QCA8K_PWS_SERDES_AEN_DIS;
1411                 else
1412                         val |= QCA8K_PWS_SERDES_AEN_DIS;
1413                 qca8k_write(priv, QCA8K_REG_PWS, val);
1414
1415                 /* Configure the SGMII parameters */
1416                 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1417                 if (ret)
1418                         return;
1419
1420                 val |= QCA8K_SGMII_EN_SD;
1421
1422                 if (priv->ports_config.sgmii_enable_pll)
1423                         val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1424                                QCA8K_SGMII_EN_TX;
1425
1426                 if (dsa_is_cpu_port(ds, port)) {
1427                         /* CPU port, we're talking to the CPU MAC, be a PHY */
1428                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1429                         val |= QCA8K_SGMII_MODE_CTRL_PHY;
1430                 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
1431                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1432                         val |= QCA8K_SGMII_MODE_CTRL_MAC;
1433                 } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
1434                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1435                         val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1436                 }
1437
1438                 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1439
1440                 /* From original code is reported port instability as SGMII also
1441                  * require delay set. Apply advised values here or take them from DT.
1442                  */
1443                 if (state->interface == PHY_INTERFACE_MODE_SGMII)
1444                         qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1445
1446                 /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
1447                  * falling edge is set writing in the PORT0 PAD reg
1448                  */
1449                 if (priv->switch_id == QCA8K_ID_QCA8327 ||
1450                     priv->switch_id == QCA8K_ID_QCA8337)
1451                         reg = QCA8K_REG_PORT0_PAD_CTRL;
1452
1453                 val = 0;
1454
1455                 /* SGMII Clock phase configuration */
1456                 if (priv->ports_config.sgmii_rx_clk_falling_edge)
1457                         val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
1458
1459                 if (priv->ports_config.sgmii_tx_clk_falling_edge)
1460                         val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
1461
1462                 if (val)
1463                         ret = qca8k_rmw(priv, reg,
1464                                         QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
1465                                         QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
1466                                         val);
1467
1468                 break;
1469         default:
1470                 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1471                         phy_modes(state->interface), port);
1472                 return;
1473         }
1474 }
1475
1476 static void
1477 qca8k_phylink_validate(struct dsa_switch *ds, int port,
1478                        unsigned long *supported,
1479                        struct phylink_link_state *state)
1480 {
1481         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1482
1483         switch (port) {
1484         case 0: /* 1st CPU port */
1485                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1486                     state->interface != PHY_INTERFACE_MODE_RGMII &&
1487                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1488                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1489                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1490                     state->interface != PHY_INTERFACE_MODE_SGMII)
1491                         goto unsupported;
1492                 break;
1493         case 1:
1494         case 2:
1495         case 3:
1496         case 4:
1497         case 5:
1498                 /* Internal PHY */
1499                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1500                     state->interface != PHY_INTERFACE_MODE_GMII &&
1501                     state->interface != PHY_INTERFACE_MODE_INTERNAL)
1502                         goto unsupported;
1503                 break;
1504         case 6: /* 2nd CPU port / external PHY */
1505                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1506                     state->interface != PHY_INTERFACE_MODE_RGMII &&
1507                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1508                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1509                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1510                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1511                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1512                         goto unsupported;
1513                 break;
1514         default:
1515 unsupported:
1516                 linkmode_zero(supported);
1517                 return;
1518         }
1519
1520         phylink_set_port_modes(mask);
1521         phylink_set(mask, Autoneg);
1522
1523         phylink_set(mask, 1000baseT_Full);
1524         phylink_set(mask, 10baseT_Half);
1525         phylink_set(mask, 10baseT_Full);
1526         phylink_set(mask, 100baseT_Half);
1527         phylink_set(mask, 100baseT_Full);
1528
1529         if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
1530                 phylink_set(mask, 1000baseX_Full);
1531
1532         phylink_set(mask, Pause);
1533         phylink_set(mask, Asym_Pause);
1534
1535         linkmode_and(supported, supported, mask);
1536         linkmode_and(state->advertising, state->advertising, mask);
1537 }
1538
1539 static int
1540 qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
1541                              struct phylink_link_state *state)
1542 {
1543         struct qca8k_priv *priv = ds->priv;
1544         u32 reg;
1545         int ret;
1546
1547         ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1548         if (ret < 0)
1549                 return ret;
1550
1551         state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1552         state->an_complete = state->link;
1553         state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
1554         state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1555                                                            DUPLEX_HALF;
1556
1557         switch (reg & QCA8K_PORT_STATUS_SPEED) {
1558         case QCA8K_PORT_STATUS_SPEED_10:
1559                 state->speed = SPEED_10;
1560                 break;
1561         case QCA8K_PORT_STATUS_SPEED_100:
1562                 state->speed = SPEED_100;
1563                 break;
1564         case QCA8K_PORT_STATUS_SPEED_1000:
1565                 state->speed = SPEED_1000;
1566                 break;
1567         default:
1568                 state->speed = SPEED_UNKNOWN;
1569                 break;
1570         }
1571
1572         state->pause = MLO_PAUSE_NONE;
1573         if (reg & QCA8K_PORT_STATUS_RXFLOW)
1574                 state->pause |= MLO_PAUSE_RX;
1575         if (reg & QCA8K_PORT_STATUS_TXFLOW)
1576                 state->pause |= MLO_PAUSE_TX;
1577
1578         return 1;
1579 }
1580
1581 static void
1582 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1583                             phy_interface_t interface)
1584 {
1585         struct qca8k_priv *priv = ds->priv;
1586
1587         qca8k_port_set_status(priv, port, 0);
1588 }
1589
1590 static void
1591 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1592                           phy_interface_t interface, struct phy_device *phydev,
1593                           int speed, int duplex, bool tx_pause, bool rx_pause)
1594 {
1595         struct qca8k_priv *priv = ds->priv;
1596         u32 reg;
1597
1598         if (phylink_autoneg_inband(mode)) {
1599                 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1600         } else {
1601                 switch (speed) {
1602                 case SPEED_10:
1603                         reg = QCA8K_PORT_STATUS_SPEED_10;
1604                         break;
1605                 case SPEED_100:
1606                         reg = QCA8K_PORT_STATUS_SPEED_100;
1607                         break;
1608                 case SPEED_1000:
1609                         reg = QCA8K_PORT_STATUS_SPEED_1000;
1610                         break;
1611                 default:
1612                         reg = QCA8K_PORT_STATUS_LINK_AUTO;
1613                         break;
1614                 }
1615
1616                 if (duplex == DUPLEX_FULL)
1617                         reg |= QCA8K_PORT_STATUS_DUPLEX;
1618
1619                 if (rx_pause || dsa_is_cpu_port(ds, port))
1620                         reg |= QCA8K_PORT_STATUS_RXFLOW;
1621
1622                 if (tx_pause || dsa_is_cpu_port(ds, port))
1623                         reg |= QCA8K_PORT_STATUS_TXFLOW;
1624         }
1625
1626         reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1627
1628         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1629 }
1630
1631 static void
1632 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
1633 {
1634         int i;
1635
1636         if (stringset != ETH_SS_STATS)
1637                 return;
1638
1639         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
1640                 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
1641                         ETH_GSTRING_LEN);
1642 }
1643
1644 static void
1645 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
1646                         uint64_t *data)
1647 {
1648         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1649         const struct qca8k_mib_desc *mib;
1650         u32 reg, i, val;
1651         u32 hi = 0;
1652         int ret;
1653
1654         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
1655                 mib = &ar8327_mib[i];
1656                 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
1657
1658                 ret = qca8k_read(priv, reg, &val);
1659                 if (ret < 0)
1660                         continue;
1661
1662                 if (mib->size == 2) {
1663                         ret = qca8k_read(priv, reg + 4, &hi);
1664                         if (ret < 0)
1665                                 continue;
1666                 }
1667
1668                 data[i] = val;
1669                 if (mib->size == 2)
1670                         data[i] |= (u64)hi << 32;
1671         }
1672 }
1673
1674 static int
1675 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
1676 {
1677         if (sset != ETH_SS_STATS)
1678                 return 0;
1679
1680         return ARRAY_SIZE(ar8327_mib);
1681 }
1682
1683 static int
1684 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
1685 {
1686         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1687         u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
1688         u32 reg;
1689         int ret;
1690
1691         mutex_lock(&priv->reg_mutex);
1692         ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
1693         if (ret < 0)
1694                 goto exit;
1695
1696         if (eee->eee_enabled)
1697                 reg |= lpi_en;
1698         else
1699                 reg &= ~lpi_en;
1700         ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
1701
1702 exit:
1703         mutex_unlock(&priv->reg_mutex);
1704         return ret;
1705 }
1706
1707 static int
1708 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1709 {
1710         /* Nothing to do on the port's MAC */
1711         return 0;
1712 }
1713
1714 static void
1715 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1716 {
1717         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1718         u32 stp_state;
1719
1720         switch (state) {
1721         case BR_STATE_DISABLED:
1722                 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
1723                 break;
1724         case BR_STATE_BLOCKING:
1725                 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
1726                 break;
1727         case BR_STATE_LISTENING:
1728                 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
1729                 break;
1730         case BR_STATE_LEARNING:
1731                 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
1732                 break;
1733         case BR_STATE_FORWARDING:
1734         default:
1735                 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
1736                 break;
1737         }
1738
1739         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1740                   QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
1741 }
1742
1743 static int
1744 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
1745 {
1746         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1747         int port_mask, cpu_port;
1748         int i, ret;
1749
1750         cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1751         port_mask = BIT(cpu_port);
1752
1753         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1754                 if (dsa_is_cpu_port(ds, i))
1755                         continue;
1756                 if (dsa_to_port(ds, i)->bridge_dev != br)
1757                         continue;
1758                 /* Add this port to the portvlan mask of the other ports
1759                  * in the bridge
1760                  */
1761                 ret = qca8k_reg_set(priv,
1762                                     QCA8K_PORT_LOOKUP_CTRL(i),
1763                                     BIT(port));
1764                 if (ret)
1765                         return ret;
1766                 if (i != port)
1767                         port_mask |= BIT(i);
1768         }
1769
1770         /* Add all other ports to this ports portvlan mask */
1771         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1772                         QCA8K_PORT_LOOKUP_MEMBER, port_mask);
1773
1774         return ret;
1775 }
1776
1777 static void
1778 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
1779 {
1780         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1781         int cpu_port, i;
1782
1783         cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1784
1785         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1786                 if (dsa_is_cpu_port(ds, i))
1787                         continue;
1788                 if (dsa_to_port(ds, i)->bridge_dev != br)
1789                         continue;
1790                 /* Remove this port to the portvlan mask of the other ports
1791                  * in the bridge
1792                  */
1793                 qca8k_reg_clear(priv,
1794                                 QCA8K_PORT_LOOKUP_CTRL(i),
1795                                 BIT(port));
1796         }
1797
1798         /* Set the cpu port to be the only one in the portvlan mask of
1799          * this port
1800          */
1801         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1802                   QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
1803 }
1804
1805 static int
1806 qca8k_port_enable(struct dsa_switch *ds, int port,
1807                   struct phy_device *phy)
1808 {
1809         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1810
1811         qca8k_port_set_status(priv, port, 1);
1812         priv->port_sts[port].enabled = 1;
1813
1814         if (dsa_is_user_port(ds, port))
1815                 phy_support_asym_pause(phy);
1816
1817         return 0;
1818 }
1819
1820 static void
1821 qca8k_port_disable(struct dsa_switch *ds, int port)
1822 {
1823         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1824
1825         qca8k_port_set_status(priv, port, 0);
1826         priv->port_sts[port].enabled = 0;
1827 }
1828
1829 static int
1830 qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1831 {
1832         struct qca8k_priv *priv = ds->priv;
1833         int i, mtu = 0;
1834
1835         priv->port_mtu[port] = new_mtu;
1836
1837         for (i = 0; i < QCA8K_NUM_PORTS; i++)
1838                 if (priv->port_mtu[i] > mtu)
1839                         mtu = priv->port_mtu[i];
1840
1841         /* Include L2 header / FCS length */
1842         return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
1843 }
1844
1845 static int
1846 qca8k_port_max_mtu(struct dsa_switch *ds, int port)
1847 {
1848         return QCA8K_MAX_MTU;
1849 }
1850
1851 static int
1852 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
1853                       u16 port_mask, u16 vid)
1854 {
1855         /* Set the vid to the port vlan id if no vid is set */
1856         if (!vid)
1857                 vid = QCA8K_PORT_VID_DEF;
1858
1859         return qca8k_fdb_add(priv, addr, port_mask, vid,
1860                              QCA8K_ATU_STATUS_STATIC);
1861 }
1862
1863 static int
1864 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
1865                    const unsigned char *addr, u16 vid)
1866 {
1867         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1868         u16 port_mask = BIT(port);
1869
1870         return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
1871 }
1872
1873 static int
1874 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
1875                    const unsigned char *addr, u16 vid)
1876 {
1877         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1878         u16 port_mask = BIT(port);
1879
1880         if (!vid)
1881                 vid = QCA8K_PORT_VID_DEF;
1882
1883         return qca8k_fdb_del(priv, addr, port_mask, vid);
1884 }
1885
1886 static int
1887 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
1888                     dsa_fdb_dump_cb_t *cb, void *data)
1889 {
1890         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1891         struct qca8k_fdb _fdb = { 0 };
1892         int cnt = QCA8K_NUM_FDB_RECORDS;
1893         bool is_static;
1894         int ret = 0;
1895
1896         mutex_lock(&priv->reg_mutex);
1897         while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1898                 if (!_fdb.aging)
1899                         break;
1900                 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1901                 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
1902                 if (ret)
1903                         break;
1904         }
1905         mutex_unlock(&priv->reg_mutex);
1906
1907         return 0;
1908 }
1909
1910 static int
1911 qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1912                           struct netlink_ext_ack *extack)
1913 {
1914         struct qca8k_priv *priv = ds->priv;
1915         int ret;
1916
1917         if (vlan_filtering) {
1918                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1919                                 QCA8K_PORT_LOOKUP_VLAN_MODE,
1920                                 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
1921         } else {
1922                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1923                                 QCA8K_PORT_LOOKUP_VLAN_MODE,
1924                                 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
1925         }
1926
1927         return ret;
1928 }
1929
1930 static int
1931 qca8k_port_vlan_add(struct dsa_switch *ds, int port,
1932                     const struct switchdev_obj_port_vlan *vlan,
1933                     struct netlink_ext_ack *extack)
1934 {
1935         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1936         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1937         struct qca8k_priv *priv = ds->priv;
1938         int ret;
1939
1940         ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
1941         if (ret) {
1942                 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
1943                 return ret;
1944         }
1945
1946         if (pvid) {
1947                 int shift = 16 * (port % 2);
1948
1949                 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1950                                 0xfff << shift, vlan->vid << shift);
1951                 if (ret)
1952                         return ret;
1953
1954                 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1955                                   QCA8K_PORT_VLAN_CVID(vlan->vid) |
1956                                   QCA8K_PORT_VLAN_SVID(vlan->vid));
1957         }
1958
1959         return ret;
1960 }
1961
1962 static int
1963 qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1964                     const struct switchdev_obj_port_vlan *vlan)
1965 {
1966         struct qca8k_priv *priv = ds->priv;
1967         int ret;
1968
1969         ret = qca8k_vlan_del(priv, port, vlan->vid);
1970         if (ret)
1971                 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1972
1973         return ret;
1974 }
1975
1976 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
1977 {
1978         struct qca8k_priv *priv = ds->priv;
1979
1980         /* Communicate to the phy internal driver the switch revision.
1981          * Based on the switch revision different values needs to be
1982          * set to the dbg and mmd reg on the phy.
1983          * The first 2 bit are used to communicate the switch revision
1984          * to the phy driver.
1985          */
1986         if (port > 0 && port < 6)
1987                 return priv->switch_revision;
1988
1989         return 0;
1990 }
1991
1992 static enum dsa_tag_protocol
1993 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1994                        enum dsa_tag_protocol mp)
1995 {
1996         return DSA_TAG_PROTO_QCA;
1997 }
1998
1999 static const struct dsa_switch_ops qca8k_switch_ops = {
2000         .get_tag_protocol       = qca8k_get_tag_protocol,
2001         .setup                  = qca8k_setup,
2002         .get_strings            = qca8k_get_strings,
2003         .get_ethtool_stats      = qca8k_get_ethtool_stats,
2004         .get_sset_count         = qca8k_get_sset_count,
2005         .get_mac_eee            = qca8k_get_mac_eee,
2006         .set_mac_eee            = qca8k_set_mac_eee,
2007         .port_enable            = qca8k_port_enable,
2008         .port_disable           = qca8k_port_disable,
2009         .port_change_mtu        = qca8k_port_change_mtu,
2010         .port_max_mtu           = qca8k_port_max_mtu,
2011         .port_stp_state_set     = qca8k_port_stp_state_set,
2012         .port_bridge_join       = qca8k_port_bridge_join,
2013         .port_bridge_leave      = qca8k_port_bridge_leave,
2014         .port_fdb_add           = qca8k_port_fdb_add,
2015         .port_fdb_del           = qca8k_port_fdb_del,
2016         .port_fdb_dump          = qca8k_port_fdb_dump,
2017         .port_vlan_filtering    = qca8k_port_vlan_filtering,
2018         .port_vlan_add          = qca8k_port_vlan_add,
2019         .port_vlan_del          = qca8k_port_vlan_del,
2020         .phylink_validate       = qca8k_phylink_validate,
2021         .phylink_mac_link_state = qca8k_phylink_mac_link_state,
2022         .phylink_mac_config     = qca8k_phylink_mac_config,
2023         .phylink_mac_link_down  = qca8k_phylink_mac_link_down,
2024         .phylink_mac_link_up    = qca8k_phylink_mac_link_up,
2025         .get_phy_flags          = qca8k_get_phy_flags,
2026 };
2027
2028 static int qca8k_read_switch_id(struct qca8k_priv *priv)
2029 {
2030         const struct qca8k_match_data *data;
2031         u32 val;
2032         u8 id;
2033         int ret;
2034
2035         /* get the switches ID from the compatible */
2036         data = of_device_get_match_data(priv->dev);
2037         if (!data)
2038                 return -ENODEV;
2039
2040         ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
2041         if (ret < 0)
2042                 return -ENODEV;
2043
2044         id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
2045         if (id != data->id) {
2046                 dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
2047                 return -ENODEV;
2048         }
2049
2050         priv->switch_id = id;
2051
2052         /* Save revision to communicate to the internal PHY driver */
2053         priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
2054
2055         return 0;
2056 }
2057
2058 static int
2059 qca8k_sw_probe(struct mdio_device *mdiodev)
2060 {
2061         struct qca8k_priv *priv;
2062         int ret;
2063
2064         /* allocate the private data struct so that we can probe the switches
2065          * ID register
2066          */
2067         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2068         if (!priv)
2069                 return -ENOMEM;
2070
2071         priv->bus = mdiodev->bus;
2072         priv->dev = &mdiodev->dev;
2073
2074         priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
2075                                                    GPIOD_ASIS);
2076         if (IS_ERR(priv->reset_gpio))
2077                 return PTR_ERR(priv->reset_gpio);
2078
2079         if (priv->reset_gpio) {
2080                 gpiod_set_value_cansleep(priv->reset_gpio, 1);
2081                 /* The active low duration must be greater than 10 ms
2082                  * and checkpatch.pl wants 20 ms.
2083                  */
2084                 msleep(20);
2085                 gpiod_set_value_cansleep(priv->reset_gpio, 0);
2086         }
2087
2088         /* Check the detected switch id */
2089         ret = qca8k_read_switch_id(priv);
2090         if (ret)
2091                 return ret;
2092
2093         priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2094         if (!priv->ds)
2095                 return -ENOMEM;
2096
2097         priv->ds->dev = &mdiodev->dev;
2098         priv->ds->num_ports = QCA8K_NUM_PORTS;
2099         priv->ds->priv = priv;
2100         priv->ops = qca8k_switch_ops;
2101         priv->ds->ops = &priv->ops;
2102         mutex_init(&priv->reg_mutex);
2103         dev_set_drvdata(&mdiodev->dev, priv);
2104
2105         return dsa_register_switch(priv->ds);
2106 }
2107
2108 static void
2109 qca8k_sw_remove(struct mdio_device *mdiodev)
2110 {
2111         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2112         int i;
2113
2114         if (!priv)
2115                 return;
2116
2117         for (i = 0; i < QCA8K_NUM_PORTS; i++)
2118                 qca8k_port_set_status(priv, i, 0);
2119
2120         dsa_unregister_switch(priv->ds);
2121
2122         dev_set_drvdata(&mdiodev->dev, NULL);
2123 }
2124
2125 static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
2126 {
2127         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2128
2129         if (!priv)
2130                 return;
2131
2132         dsa_switch_shutdown(priv->ds);
2133
2134         dev_set_drvdata(&mdiodev->dev, NULL);
2135 }
2136
2137 #ifdef CONFIG_PM_SLEEP
2138 static void
2139 qca8k_set_pm(struct qca8k_priv *priv, int enable)
2140 {
2141         int i;
2142
2143         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
2144                 if (!priv->port_sts[i].enabled)
2145                         continue;
2146
2147                 qca8k_port_set_status(priv, i, enable);
2148         }
2149 }
2150
2151 static int qca8k_suspend(struct device *dev)
2152 {
2153         struct qca8k_priv *priv = dev_get_drvdata(dev);
2154
2155         qca8k_set_pm(priv, 0);
2156
2157         return dsa_switch_suspend(priv->ds);
2158 }
2159
2160 static int qca8k_resume(struct device *dev)
2161 {
2162         struct qca8k_priv *priv = dev_get_drvdata(dev);
2163
2164         qca8k_set_pm(priv, 1);
2165
2166         return dsa_switch_resume(priv->ds);
2167 }
2168 #endif /* CONFIG_PM_SLEEP */
2169
2170 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
2171                          qca8k_suspend, qca8k_resume);
2172
2173 static const struct qca8k_match_data qca8327 = {
2174         .id = QCA8K_ID_QCA8327,
2175         .reduced_package = true,
2176 };
2177
2178 static const struct qca8k_match_data qca8328 = {
2179         .id = QCA8K_ID_QCA8327,
2180 };
2181
2182 static const struct qca8k_match_data qca833x = {
2183         .id = QCA8K_ID_QCA8337,
2184 };
2185
2186 static const struct of_device_id qca8k_of_match[] = {
2187         { .compatible = "qca,qca8327", .data = &qca8327 },
2188         { .compatible = "qca,qca8328", .data = &qca8328 },
2189         { .compatible = "qca,qca8334", .data = &qca833x },
2190         { .compatible = "qca,qca8337", .data = &qca833x },
2191         { /* sentinel */ },
2192 };
2193
2194 static struct mdio_driver qca8kmdio_driver = {
2195         .probe  = qca8k_sw_probe,
2196         .remove = qca8k_sw_remove,
2197         .shutdown = qca8k_sw_shutdown,
2198         .mdiodrv.driver = {
2199                 .name = "qca8k",
2200                 .of_match_table = qca8k_of_match,
2201                 .pm = &qca8k_pm_ops,
2202         },
2203 };
2204
2205 mdio_module_driver(qca8kmdio_driver);
2206
2207 MODULE_AUTHOR("Mathieu Olivari, John Crispin <[email protected]>");
2208 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
2209 MODULE_LICENSE("GPL v2");
2210 MODULE_ALIAS("platform:qca8k");