drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/drm_cache.h>
  29 #include "amdgpu.h"
  30 #include "gmc_v8_0.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_amdkfd.h"
  33 #include "amdgpu_gem.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "oss/oss_3_0_d.h"
  42 #include "oss/oss_3_0_sh_mask.h"
  43
  44 #include "dce/dce_10_0_d.h"
  45 #include "dce/dce_10_0_sh_mask.h"
  46
  47 #include "vid.h"
  48 #include "vi.h"
  49
  50 #include "amdgpu_atombios.h"
  51
  52 #include "ivsrcid/ivsrcid_vislands30.h"
  53
  54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
  55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  56 static int gmc_v8_0_wait_for_idle(void *handle);
  57
  58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  62 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin");
  63 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
  64 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
  65 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
  66
  67 static const u32 golden_settings_tonga_a11[] = {
  68         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  69         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  70         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  71         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  72         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  73         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  74         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  75 };
  76
  77 static const u32 tonga_mgcg_cgcg_init[] = {
  78         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  79 };
  80
  81 static const u32 golden_settings_fiji_a10[] = {
  82         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  83         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  84         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  85         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  86 };
  87
  88 static const u32 fiji_mgcg_cgcg_init[] = {
  89         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  90 };
  91
  92 static const u32 golden_settings_polaris11_a11[] = {
  93         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  94         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  95         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  96         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  97 };
  98
  99 static const u32 golden_settings_polaris10_a11[] = {
 100         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
 101         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 102         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 103         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 104         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 105 };
 106
 107 static const u32 cz_mgcg_cgcg_init[] = {
 108         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 109 };
 110
 111 static const u32 stoney_mgcg_cgcg_init[] = {
 112         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 113         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 114 };
 115
 116 static const u32 golden_settings_stoney_common[] = {
 117         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 118         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 119 };
 120
 121 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 122 {
 123         switch (adev->asic_type) {
 124         case CHIP_FIJI:
 125                 amdgpu_device_program_register_sequence(adev,
 126                                                         fiji_mgcg_cgcg_init,
 127                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 128                 amdgpu_device_program_register_sequence(adev,
 129                                                         golden_settings_fiji_a10,
 130                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 131                 break;
 132         case CHIP_TONGA:
 133                 amdgpu_device_program_register_sequence(adev,
 134                                                         tonga_mgcg_cgcg_init,
 135                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 136                 amdgpu_device_program_register_sequence(adev,
 137                                                         golden_settings_tonga_a11,
 138                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 139                 break;
 140         case CHIP_POLARIS11:
 141         case CHIP_POLARIS12:
 142         case CHIP_VEGAM:
 143                 amdgpu_device_program_register_sequence(adev,
 144                                                         golden_settings_polaris11_a11,
 145                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 146                 break;
 147         case CHIP_POLARIS10:
 148                 amdgpu_device_program_register_sequence(adev,
 149                                                         golden_settings_polaris10_a11,
 150                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 151                 break;
 152         case CHIP_CARRIZO:
 153                 amdgpu_device_program_register_sequence(adev,
 154                                                         cz_mgcg_cgcg_init,
 155                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 156                 break;
 157         case CHIP_STONEY:
 158                 amdgpu_device_program_register_sequence(adev,
 159                                                         stoney_mgcg_cgcg_init,
 160                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 161                 amdgpu_device_program_register_sequence(adev,
 162                                                         golden_settings_stoney_common,
 163                                                         ARRAY_SIZE(golden_settings_stoney_common));
 164                 break;
 165         default:
 166                 break;
 167         }
 168 }
 169
 170 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 171 {
 172         u32 blackout;
 173
 174         gmc_v8_0_wait_for_idle(adev);
 175
 176         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 177         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 178                 /* Block CPU access */
 179                 WREG32(mmBIF_FB_EN, 0);
 180                 /* blackout the MC */
 181                 blackout = REG_SET_FIELD(blackout,
 182                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 183                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 184         }
 185         /* wait for the MC to settle */
 186         udelay(100);
 187 }
 188
 189 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 190 {
 191         u32 tmp;
 192
 193         /* unblackout the MC */
 194         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 195         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 196         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 197         /* allow CPU access */
 198         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 199         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 200         WREG32(mmBIF_FB_EN, tmp);
 201 }
 202
 203 /**
 204  * gmc_v8_0_init_microcode - load ucode images from disk
 205  *
 206  * @adev: amdgpu_device pointer
 207  *
 208  * Use the firmware interface to load the ucode images into
 209  * the driver (not loaded into hw).
 210  * Returns 0 on success, error on failure.
 211  */
 212 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 213 {
 214         const char *chip_name;
 215         char fw_name[30];
 216         int err;
 217
 218         DRM_DEBUG("\n");
 219
 220         switch (adev->asic_type) {
 221         case CHIP_TONGA:
 222                 chip_name = "tonga";
 223                 break;
 224         case CHIP_POLARIS11:
 225                 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
 226                     ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
 227                         chip_name = "polaris11_k";
 228                 else
 229                         chip_name = "polaris11";
 230                 break;
 231         case CHIP_POLARIS10:
 232                 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
 233                         chip_name = "polaris10_k";
 234                 else
 235                         chip_name = "polaris10";
 236                 break;
 237         case CHIP_POLARIS12:
 238                 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
 239                         chip_name = "polaris12_k";
 240                 } else {
 241                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);
 242                         /* Polaris12 32bit ASIC needs a special MC firmware */
 243                         if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40)
 244                                 chip_name = "polaris12_32";
 245                         else
 246                                 chip_name = "polaris12";
 247                 }
 248                 break;
 249         case CHIP_FIJI:
 250         case CHIP_CARRIZO:
 251         case CHIP_STONEY:
 252         case CHIP_VEGAM:
 253                 return 0;
 254         default:
 255                 return -EINVAL;
 256         }
 257
 258         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 259         err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name);
 260         if (err) {
 261                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 262                 amdgpu_ucode_release(&adev->gmc.fw);
 263         }
 264         return err;
 265 }
 266
 267 /**
 268  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 269  *
 270  * @adev: amdgpu_device pointer
 271  *
 272  * Load the GDDR MC ucode into the hw (VI).
 273  * Returns 0 on success, error on failure.
 274  */
 275 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 276 {
 277         const struct mc_firmware_header_v1_0 *hdr;
 278         const __le32 *fw_data = NULL;
 279         const __le32 *io_mc_regs = NULL;
 280         u32 running;
 281         int i, ucode_size, regs_size;
 282
 283         /* Skip MC ucode loading on SR-IOV capable boards.
 284          * vbios does this for us in asic_init in that case.
 285          * Skip MC ucode loading on VF, because hypervisor will do that
 286          * for this adaptor.
 287          */
 288         if (amdgpu_sriov_bios(adev))
 289                 return 0;
 290
 291         if (!adev->gmc.fw)
 292                 return -EINVAL;
 293
 294         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 295         amdgpu_ucode_print_mc_hdr(&hdr->header);
 296
 297         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 298         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 299         io_mc_regs = (const __le32 *)
 300                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 301         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 302         fw_data = (const __le32 *)
 303                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 304
 305         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 306
 307         if (running == 0) {
 308                 /* reset the engine and set to writable */
 309                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 310                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 311
 312                 /* load mc io regs */
 313                 for (i = 0; i < regs_size; i++) {
 314                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 315                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 316                 }
 317                 /* load the MC ucode */
 318                 for (i = 0; i < ucode_size; i++)
 319                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 320
 321                 /* put the engine back into the active state */
 322                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 323                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 324                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 325
 326                 /* wait for training to complete */
 327                 for (i = 0; i < adev->usec_timeout; i++) {
 328                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 329                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 330                                 break;
 331                         udelay(1);
 332                 }
 333                 for (i = 0; i < adev->usec_timeout; i++) {
 334                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 335                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 336                                 break;
 337                         udelay(1);
 338                 }
 339         }
 340
 341         return 0;
 342 }
 343
 344 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 345 {
 346         const struct mc_firmware_header_v1_0 *hdr;
 347         const __le32 *fw_data = NULL;
 348         const __le32 *io_mc_regs = NULL;
 349         u32 data;
 350         int i, ucode_size, regs_size;
 351
 352         /* Skip MC ucode loading on SR-IOV capable boards.
 353          * vbios does this for us in asic_init in that case.
 354          * Skip MC ucode loading on VF, because hypervisor will do that
 355          * for this adaptor.
 356          */
 357         if (amdgpu_sriov_bios(adev))
 358                 return 0;
 359
 360         if (!adev->gmc.fw)
 361                 return -EINVAL;
 362
 363         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 364         amdgpu_ucode_print_mc_hdr(&hdr->header);
 365
 366         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 367         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 368         io_mc_regs = (const __le32 *)
 369                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 370         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 371         fw_data = (const __le32 *)
 372                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 373
 374         data = RREG32(mmMC_SEQ_MISC0);
 375         data &= ~(0x40);
 376         WREG32(mmMC_SEQ_MISC0, data);
 377
 378         /* load mc io regs */
 379         for (i = 0; i < regs_size; i++) {
 380                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 381                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 382         }
 383
 384         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 385         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 386
 387         /* load the MC ucode */
 388         for (i = 0; i < ucode_size; i++)
 389                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 390
 391         /* put the engine back into the active state */
 392         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 393         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 394         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 395
 396         /* wait for training to complete */
 397         for (i = 0; i < adev->usec_timeout; i++) {
 398                 data = RREG32(mmMC_SEQ_MISC0);
 399                 if (data & 0x80)
 400                         break;
 401                 udelay(1);
 402         }
 403
 404         return 0;
 405 }
 406
 407 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 408                                        struct amdgpu_gmc *mc)
 409 {
 410         u64 base = 0;
 411
 412         if (!amdgpu_sriov_vf(adev))
 413                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 414         base <<= 24;
 415
 416         amdgpu_gmc_set_agp_default(adev, mc);
 417         amdgpu_gmc_vram_location(adev, mc, base);
 418         amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
 419 }
 420
 421 /**
 422  * gmc_v8_0_mc_program - program the GPU memory controller
 423  *
 424  * @adev: amdgpu_device pointer
 425  *
 426  * Set the location of vram, gart, and AGP in the GPU's
 427  * physical address space (VI).
 428  */
 429 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 430 {
 431         u32 tmp;
 432         int i, j;
 433
 434         /* Initialize HDP */
 435         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 436                 WREG32((0xb05 + j), 0x00000000);
 437                 WREG32((0xb06 + j), 0x00000000);
 438                 WREG32((0xb07 + j), 0x00000000);
 439                 WREG32((0xb08 + j), 0x00000000);
 440                 WREG32((0xb09 + j), 0x00000000);
 441         }
 442         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 443
 444         if (gmc_v8_0_wait_for_idle((void *)adev))
 445                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 446
 447         if (adev->mode_info.num_crtc) {
 448                 /* Lockout access through VGA aperture*/
 449                 tmp = RREG32(mmVGA_HDP_CONTROL);
 450                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 451                 WREG32(mmVGA_HDP_CONTROL, tmp);
 452
 453                 /* disable VGA render */
 454                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 455                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 456                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 457         }
 458         /* Update configuration */
 459         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 460                adev->gmc.vram_start >> 12);
 461         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 462                adev->gmc.vram_end >> 12);
 463         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 464                adev->mem_scratch.gpu_addr >> 12);
 465
 466         if (amdgpu_sriov_vf(adev)) {
 467                 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 468                 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
 469                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 470                 /* XXX double check these! */
 471                 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 472                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 473                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 474         }
 475
 476         WREG32(mmMC_VM_AGP_BASE, 0);
 477         WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
 478         WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
 479         if (gmc_v8_0_wait_for_idle((void *)adev))
 480                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 481
 482         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 483
 484         tmp = RREG32(mmHDP_MISC_CNTL);
 485         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 486         WREG32(mmHDP_MISC_CNTL, tmp);
 487
 488         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 489         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 490 }
 491
 492 /**
 493  * gmc_v8_0_mc_init - initialize the memory controller driver params
 494  *
 495  * @adev: amdgpu_device pointer
 496  *
 497  * Look up the amount of vram, vram width, and decide how to place
 498  * vram and gart within the GPU's physical address space (VI).
 499  * Returns 0 for success.
 500  */
 501 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 502 {
 503         int r;
 504         u32 tmp;
 505
 506         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 507         if (!adev->gmc.vram_width) {
 508                 int chansize, numchan;
 509
 510                 /* Get VRAM informations */
 511                 tmp = RREG32(mmMC_ARB_RAMCFG);
 512                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
 513                         chansize = 64;
 514                 else
 515                         chansize = 32;
 516
 517                 tmp = RREG32(mmMC_SHARED_CHMAP);
 518                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 519                 case 0:
 520                 default:
 521                         numchan = 1;
 522                         break;
 523                 case 1:
 524                         numchan = 2;
 525                         break;
 526                 case 2:
 527                         numchan = 4;
 528                         break;
 529                 case 3:
 530                         numchan = 8;
 531                         break;
 532                 case 4:
 533                         numchan = 3;
 534                         break;
 535                 case 5:
 536                         numchan = 6;
 537                         break;
 538                 case 6:
 539                         numchan = 10;
 540                         break;
 541                 case 7:
 542                         numchan = 12;
 543                         break;
 544                 case 8:
 545                         numchan = 16;
 546                         break;
 547                 }
 548                 adev->gmc.vram_width = numchan * chansize;
 549         }
 550         /* size in MB on si */
 551         tmp = RREG32(mmCONFIG_MEMSIZE);
 552         /* some boards may have garbage in the upper 16 bits */
 553         if (tmp & 0xffff0000) {
 554                 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
 555                 if (tmp & 0xffff)
 556                         tmp &= 0xffff;
 557         }
 558         adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
 559         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 560
 561         if (!(adev->flags & AMD_IS_APU)) {
 562                 r = amdgpu_device_resize_fb_bar(adev);
 563                 if (r)
 564                         return r;
 565         }
 566         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 567         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 568
 569 #ifdef CONFIG_X86_64
 570         if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
 571                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 572                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 573         }
 574 #endif
 575
 576         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 577
 578         /* set the gart size */
 579         if (amdgpu_gart_size == -1) {
 580                 switch (adev->asic_type) {
 581                 case CHIP_POLARIS10: /* all engines support GPUVM */
 582                 case CHIP_POLARIS11: /* all engines support GPUVM */
 583                 case CHIP_POLARIS12: /* all engines support GPUVM */
 584                 case CHIP_VEGAM:     /* all engines support GPUVM */
 585                 default:
 586                         adev->gmc.gart_size = 256ULL << 20;
 587                         break;
 588                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 589                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 590                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 591                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 592                         adev->gmc.gart_size = 1024ULL << 20;
 593                         break;
 594                 }
 595         } else {
 596                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 597         }
 598
 599         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
 600         gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
 601
 602         return 0;
 603 }
 604
 605 /**
 606  * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
 607  *
 608  * @adev: amdgpu_device pointer
 609  * @pasid: pasid to be flush
 610  * @flush_type: type of flush
 611  * @all_hub: flush all hubs
 612  * @inst: is used to select which instance of KIQ to use for the invalidation
 613  *
 614  * Flush the TLB for the requested pasid.
 615  */
 616 static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 617                                          uint16_t pasid, uint32_t flush_type,
 618                                          bool all_hub, uint32_t inst)
 619 {
 620         u32 mask = 0x0;
 621         int vmid;
 622
 623         for (vmid = 1; vmid < 16; vmid++) {
 624                 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 625
 626                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 627                     (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
 628                         mask |= 1 << vmid;
 629         }
 630
 631         WREG32(mmVM_INVALIDATE_REQUEST, mask);
 632         RREG32(mmVM_INVALIDATE_RESPONSE);
 633 }
 634
 635 /*
 636  * GART
 637  * VMID 0 is the physical GPU addresses as used by the kernel.
 638  * VMIDs 1-15 are used for userspace clients and are handled
 639  * by the amdgpu vm/hsa code.
 640  */
 641
 642 /**
 643  * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
 644  *
 645  * @adev: amdgpu_device pointer
 646  * @vmid: vm instance to flush
 647  * @vmhub: which hub to flush
 648  * @flush_type: type of flush
 649  *
 650  * Flush the TLB for the requested page table (VI).
 651  */
 652 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 653                                         uint32_t vmhub, uint32_t flush_type)
 654 {
 655         /* bits 0-15 are the VM contexts0-15 */
 656         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 657 }
 658
 659 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 660                                             unsigned int vmid, uint64_t pd_addr)
 661 {
 662         uint32_t reg;
 663
 664         if (vmid < 8)
 665                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 666         else
 667                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 668         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 669
 670         /* bits 0-15 are the VM contexts0-15 */
 671         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 672
 673         return pd_addr;
 674 }
 675
 676 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
 677                                         unsigned int pasid)
 678 {
 679         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 680 }
 681
 682 /*
 683  * PTE format on VI:
 684  * 63:40 reserved
 685  * 39:12 4k physical page base address
 686  * 11:7 fragment
 687  * 6 write
 688  * 5 read
 689  * 4 exe
 690  * 3 reserved
 691  * 2 snooped
 692  * 1 system
 693  * 0 valid
 694  *
 695  * PDE format on VI:
 696  * 63:59 block fragment size
 697  * 58:40 reserved
 698  * 39:1 physical base address of PTE
 699  * bits 5:1 must be 0.
 700  * 0 valid
 701  */
 702
 703 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
 704                                 uint64_t *addr, uint64_t *flags)
 705 {
 706         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 707 }
 708
 709 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
 710                                 struct amdgpu_bo_va_mapping *mapping,
 711                                 uint64_t *flags)
 712 {
 713         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 714         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 715         *flags &= ~AMDGPU_PTE_PRT;
 716 }
 717
 718 /**
 719  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 720  *
 721  * @adev: amdgpu_device pointer
 722  * @value: true redirects VM faults to the default page
 723  */
 724 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 725                                               bool value)
 726 {
 727         u32 tmp;
 728
 729         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 730         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 731                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 732         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 733                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 734         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 735                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 736         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 737                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 738         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 739                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 740         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 741                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 742         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 743                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 744         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 745 }
 746
 747 /**
 748  * gmc_v8_0_set_prt() - set PRT VM fault
 749  *
 750  * @adev: amdgpu_device pointer
 751  * @enable: enable/disable VM fault handling for PRT
 752  */
 753 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 754 {
 755         u32 tmp;
 756
 757         if (enable && !adev->gmc.prt_warning) {
 758                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 759                 adev->gmc.prt_warning = true;
 760         }
 761
 762         tmp = RREG32(mmVM_PRT_CNTL);
 763         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 764                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 765         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 766                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 767         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 768                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 769         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 770                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 771         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 772                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 773         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 774                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 775         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 776                             MASK_PDE0_FAULT, enable);
 777         WREG32(mmVM_PRT_CNTL, tmp);
 778
 779         if (enable) {
 780                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 781                 uint32_t high = adev->vm_manager.max_pfn -
 782                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 783
 784                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 785                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 786                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 787                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 788                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 789                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 790                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 791                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 792         } else {
 793                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 794                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 795                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 796                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 797                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 798                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 799                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 800                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 801         }
 802 }
 803
 804 /**
 805  * gmc_v8_0_gart_enable - gart enable
 806  *
 807  * @adev: amdgpu_device pointer
 808  *
 809  * This sets up the TLBs, programs the page tables for VMID0,
 810  * sets up the hw for VMIDs 1-15 which are allocated on
 811  * demand, and sets up the global locations for the LDS, GDS,
 812  * and GPUVM for FSA64 clients (VI).
 813  * Returns 0 for success, errors for failure.
 814  */
 815 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 816 {
 817         uint64_t table_addr;
 818         u32 tmp, field;
 819         int i;
 820
 821         if (adev->gart.bo == NULL) {
 822                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 823                 return -EINVAL;
 824         }
 825         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 826         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 827
 828         /* Setup TLB control */
 829         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 830         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 831         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 832         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 833         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 834         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 835         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 836         /* Setup L2 cache */
 837         tmp = RREG32(mmVM_L2_CNTL);
 838         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 839         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 840         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 841         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 842         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 843         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 844         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 845         WREG32(mmVM_L2_CNTL, tmp);
 846         tmp = RREG32(mmVM_L2_CNTL2);
 847         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 848         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 849         WREG32(mmVM_L2_CNTL2, tmp);
 850
 851         field = adev->vm_manager.fragment_size;
 852         tmp = RREG32(mmVM_L2_CNTL3);
 853         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 854         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 855         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 856         WREG32(mmVM_L2_CNTL3, tmp);
 857         /* XXX: set to enable PTE/PDE in system memory */
 858         tmp = RREG32(mmVM_L2_CNTL4);
 859         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 860         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 861         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 862         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 863         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 864         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 865         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 866         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 867         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 868         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 869         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 870         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 871         WREG32(mmVM_L2_CNTL4, tmp);
 872         /* setup context0 */
 873         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 874         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 875         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 876         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 877                         (u32)(adev->dummy_page_addr >> 12));
 878         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 879         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 880         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 881         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 882         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 883         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 884
 885         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 886         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 887         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 888
 889         /* empty context1-15 */
 890         /* FIXME start with 4G, once using 2 level pt switch to full
 891          * vm size space
 892          */
 893         /* set vm size, must be a multiple of 4 */
 894         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 895         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 896         for (i = 1; i < AMDGPU_NUM_VMID; i++) {
 897                 if (i < 8)
 898                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 899                                table_addr >> 12);
 900                 else
 901                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 902                                table_addr >> 12);
 903         }
 904
 905         /* enable context1-15 */
 906         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 907                (u32)(adev->dummy_page_addr >> 12));
 908         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 909         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 910         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 911         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 912         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 913         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 914         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 915         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 916         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 917         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 918         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 919         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 920                             adev->vm_manager.block_size - 9);
 921         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 922         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 923                 gmc_v8_0_set_fault_enable_default(adev, false);
 924         else
 925                 gmc_v8_0_set_fault_enable_default(adev, true);
 926
 927         gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
 928         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 929                  (unsigned int)(adev->gmc.gart_size >> 20),
 930                  (unsigned long long)table_addr);
 931         return 0;
 932 }
 933
 934 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 935 {
 936         int r;
 937
 938         if (adev->gart.bo) {
 939                 WARN(1, "R600 PCIE GART already initialized\n");
 940                 return 0;
 941         }
 942         /* Initialize common gart structure */
 943         r = amdgpu_gart_init(adev);
 944         if (r)
 945                 return r;
 946         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 947         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 948         return amdgpu_gart_table_vram_alloc(adev);
 949 }
 950
 951 /**
 952  * gmc_v8_0_gart_disable - gart disable
 953  *
 954  * @adev: amdgpu_device pointer
 955  *
 956  * This disables all VM page table (VI).
 957  */
 958 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 959 {
 960         u32 tmp;
 961
 962         /* Disable all tables */
 963         WREG32(mmVM_CONTEXT0_CNTL, 0);
 964         WREG32(mmVM_CONTEXT1_CNTL, 0);
 965         /* Setup TLB control */
 966         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 967         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 968         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 969         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 970         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 971         /* Setup L2 cache */
 972         tmp = RREG32(mmVM_L2_CNTL);
 973         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 974         WREG32(mmVM_L2_CNTL, tmp);
 975         WREG32(mmVM_L2_CNTL2, 0);
 976 }
 977
 978 /**
 979  * gmc_v8_0_vm_decode_fault - print human readable fault info
 980  *
 981  * @adev: amdgpu_device pointer
 982  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 983  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 984  * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
 985  * @pasid: debug logging only - no functional use
 986  *
 987  * Print human readable fault information (VI).
 988  */
 989 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
 990                                      u32 addr, u32 mc_client, unsigned int pasid)
 991 {
 992         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 993         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 994                                         PROTECTIONS);
 995         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 996                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 997         u32 mc_id;
 998
 999         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1000                               MEMORY_CLIENT_ID);
1001
1002         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1003                protections, vmid, pasid, addr,
1004                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1005                              MEMORY_CLIENT_RW) ?
1006                "write" : "read", block, mc_client, mc_id);
1007 }
1008
1009 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1010 {
1011         switch (mc_seq_vram_type) {
1012         case MC_SEQ_MISC0__MT__GDDR1:
1013                 return AMDGPU_VRAM_TYPE_GDDR1;
1014         case MC_SEQ_MISC0__MT__DDR2:
1015                 return AMDGPU_VRAM_TYPE_DDR2;
1016         case MC_SEQ_MISC0__MT__GDDR3:
1017                 return AMDGPU_VRAM_TYPE_GDDR3;
1018         case MC_SEQ_MISC0__MT__GDDR4:
1019                 return AMDGPU_VRAM_TYPE_GDDR4;
1020         case MC_SEQ_MISC0__MT__GDDR5:
1021                 return AMDGPU_VRAM_TYPE_GDDR5;
1022         case MC_SEQ_MISC0__MT__HBM:
1023                 return AMDGPU_VRAM_TYPE_HBM;
1024         case MC_SEQ_MISC0__MT__DDR3:
1025                 return AMDGPU_VRAM_TYPE_DDR3;
1026         default:
1027                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1028         }
1029 }
1030
1031 static int gmc_v8_0_early_init(void *handle)
1032 {
1033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035         gmc_v8_0_set_gmc_funcs(adev);
1036         gmc_v8_0_set_irq_funcs(adev);
1037
1038         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1039         adev->gmc.shared_aperture_end =
1040                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1041         adev->gmc.private_aperture_start =
1042                 adev->gmc.shared_aperture_end + 1;
1043         adev->gmc.private_aperture_end =
1044                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1045         adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1046
1047         return 0;
1048 }
1049
1050 static int gmc_v8_0_late_init(void *handle)
1051 {
1052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1055                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1056         else
1057                 return 0;
1058 }
1059
1060 static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1061 {
1062         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1063         unsigned int size;
1064
1065         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1066                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1067         } else {
1068                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1069
1070                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1071                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1072                         4);
1073         }
1074
1075         return size;
1076 }
1077
1078 #define mmMC_SEQ_MISC0_FIJI 0xA71
1079
1080 static int gmc_v8_0_sw_init(void *handle)
1081 {
1082         int r;
1083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084
1085         set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
1086
1087         if (adev->flags & AMD_IS_APU) {
1088                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1089         } else {
1090                 u32 tmp;
1091
1092                 if ((adev->asic_type == CHIP_FIJI) ||
1093                     (adev->asic_type == CHIP_VEGAM))
1094                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1095                 else
1096                         tmp = RREG32(mmMC_SEQ_MISC0);
1097                 tmp &= MC_SEQ_MISC0__MT__MASK;
1098                 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1099         }
1100
1101         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1102         if (r)
1103                 return r;
1104
1105         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1106         if (r)
1107                 return r;
1108
1109         /* Adjust VM size here.
1110          * Currently set to 4GB ((1 << 20) 4k pages).
1111          * Max GPUVM size for cayman and SI is 40 bits.
1112          */
1113         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1114
1115         /* Set the internal MC address mask
1116          * This is the max address of the GPU's
1117          * internal address space.
1118          */
1119         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1120
1121         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1122         if (r) {
1123                 pr_warn("No suitable DMA available\n");
1124                 return r;
1125         }
1126         adev->need_swiotlb = drm_need_swiotlb(40);
1127
1128         r = gmc_v8_0_init_microcode(adev);
1129         if (r) {
1130                 DRM_ERROR("Failed to load mc firmware!\n");
1131                 return r;
1132         }
1133
1134         r = gmc_v8_0_mc_init(adev);
1135         if (r)
1136                 return r;
1137
1138         amdgpu_gmc_get_vbios_allocations(adev);
1139
1140         /* Memory manager */
1141         r = amdgpu_bo_init(adev);
1142         if (r)
1143                 return r;
1144
1145         r = gmc_v8_0_gart_init(adev);
1146         if (r)
1147                 return r;
1148
1149         /*
1150          * number of VMs
1151          * VMID 0 is reserved for System
1152          * amdgpu graphics/compute will use VMIDs 1-7
1153          * amdkfd will use VMIDs 8-15
1154          */
1155         adev->vm_manager.first_kfd_vmid = 8;
1156         amdgpu_vm_manager_init(adev);
1157
1158         /* base offset of vram pages */
1159         if (adev->flags & AMD_IS_APU) {
1160                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1161
1162                 tmp <<= 22;
1163                 adev->vm_manager.vram_base_offset = tmp;
1164         } else {
1165                 adev->vm_manager.vram_base_offset = 0;
1166         }
1167
1168         adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1169                                         GFP_KERNEL);
1170         if (!adev->gmc.vm_fault_info)
1171                 return -ENOMEM;
1172         atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1173
1174         return 0;
1175 }
1176
1177 static int gmc_v8_0_sw_fini(void *handle)
1178 {
1179         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1180
1181         amdgpu_gem_force_release(adev);
1182         amdgpu_vm_manager_fini(adev);
1183         kfree(adev->gmc.vm_fault_info);
1184         amdgpu_gart_table_vram_free(adev);
1185         amdgpu_bo_fini(adev);
1186         amdgpu_ucode_release(&adev->gmc.fw);
1187
1188         return 0;
1189 }
1190
1191 static int gmc_v8_0_hw_init(void *handle)
1192 {
1193         int r;
1194         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1195
1196         gmc_v8_0_init_golden_registers(adev);
1197
1198         gmc_v8_0_mc_program(adev);
1199
1200         if (adev->asic_type == CHIP_TONGA) {
1201                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1202                 if (r) {
1203                         DRM_ERROR("Failed to load MC firmware!\n");
1204                         return r;
1205                 }
1206         } else if (adev->asic_type == CHIP_POLARIS11 ||
1207                         adev->asic_type == CHIP_POLARIS10 ||
1208                         adev->asic_type == CHIP_POLARIS12) {
1209                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1210                 if (r) {
1211                         DRM_ERROR("Failed to load MC firmware!\n");
1212                         return r;
1213                 }
1214         }
1215
1216         r = gmc_v8_0_gart_enable(adev);
1217         if (r)
1218                 return r;
1219
1220         if (amdgpu_emu_mode == 1)
1221                 return amdgpu_gmc_vram_checking(adev);
1222         else
1223                 return r;
1224 }
1225
1226 static int gmc_v8_0_hw_fini(void *handle)
1227 {
1228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229
1230         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1231         gmc_v8_0_gart_disable(adev);
1232
1233         return 0;
1234 }
1235
1236 static int gmc_v8_0_suspend(void *handle)
1237 {
1238         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1239
1240         gmc_v8_0_hw_fini(adev);
1241
1242         return 0;
1243 }
1244
1245 static int gmc_v8_0_resume(void *handle)
1246 {
1247         int r;
1248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249
1250         r = gmc_v8_0_hw_init(adev);
1251         if (r)
1252                 return r;
1253
1254         amdgpu_vmid_reset_all(adev);
1255
1256         return 0;
1257 }
1258
1259 static bool gmc_v8_0_is_idle(void *handle)
1260 {
1261         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262         u32 tmp = RREG32(mmSRBM_STATUS);
1263
1264         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1265                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1266                 return false;
1267
1268         return true;
1269 }
1270
1271 static int gmc_v8_0_wait_for_idle(void *handle)
1272 {
1273         unsigned int i;
1274         u32 tmp;
1275         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1276
1277         for (i = 0; i < adev->usec_timeout; i++) {
1278                 /* read MC_STATUS */
1279                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1280                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1281                                                SRBM_STATUS__MCC_BUSY_MASK |
1282                                                SRBM_STATUS__MCD_BUSY_MASK |
1283                                                SRBM_STATUS__VMC_BUSY_MASK |
1284                                                SRBM_STATUS__VMC1_BUSY_MASK);
1285                 if (!tmp)
1286                         return 0;
1287                 udelay(1);
1288         }
1289         return -ETIMEDOUT;
1290
1291 }
1292
1293 static bool gmc_v8_0_check_soft_reset(void *handle)
1294 {
1295         u32 srbm_soft_reset = 0;
1296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297         u32 tmp = RREG32(mmSRBM_STATUS);
1298
1299         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1300                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1301                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1302
1303         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1304                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1305                 if (!(adev->flags & AMD_IS_APU))
1306                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1307                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1308         }
1309
1310         if (srbm_soft_reset) {
1311                 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1312                 return true;
1313         }
1314
1315         adev->gmc.srbm_soft_reset = 0;
1316
1317         return false;
1318 }
1319
1320 static int gmc_v8_0_pre_soft_reset(void *handle)
1321 {
1322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323
1324         if (!adev->gmc.srbm_soft_reset)
1325                 return 0;
1326
1327         gmc_v8_0_mc_stop(adev);
1328         if (gmc_v8_0_wait_for_idle(adev))
1329                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1330
1331         return 0;
1332 }
1333
1334 static int gmc_v8_0_soft_reset(void *handle)
1335 {
1336         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1337         u32 srbm_soft_reset;
1338
1339         if (!adev->gmc.srbm_soft_reset)
1340                 return 0;
1341         srbm_soft_reset = adev->gmc.srbm_soft_reset;
1342
1343         if (srbm_soft_reset) {
1344                 u32 tmp;
1345
1346                 tmp = RREG32(mmSRBM_SOFT_RESET);
1347                 tmp |= srbm_soft_reset;
1348                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1349                 WREG32(mmSRBM_SOFT_RESET, tmp);
1350                 tmp = RREG32(mmSRBM_SOFT_RESET);
1351
1352                 udelay(50);
1353
1354                 tmp &= ~srbm_soft_reset;
1355                 WREG32(mmSRBM_SOFT_RESET, tmp);
1356                 tmp = RREG32(mmSRBM_SOFT_RESET);
1357
1358                 /* Wait a little for things to settle down */
1359                 udelay(50);
1360         }
1361
1362         return 0;
1363 }
1364
1365 static int gmc_v8_0_post_soft_reset(void *handle)
1366 {
1367         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1368
1369         if (!adev->gmc.srbm_soft_reset)
1370                 return 0;
1371
1372         gmc_v8_0_mc_resume(adev);
1373         return 0;
1374 }
1375
1376 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1377                                              struct amdgpu_irq_src *src,
1378                                              unsigned int type,
1379                                              enum amdgpu_interrupt_state state)
1380 {
1381         u32 tmp;
1382         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1383                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1384                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1385                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1386                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1387                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1388                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1389
1390         switch (state) {
1391         case AMDGPU_IRQ_STATE_DISABLE:
1392                 /* system context */
1393                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1394                 tmp &= ~bits;
1395                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1396                 /* VMs */
1397                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1398                 tmp &= ~bits;
1399                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1400                 break;
1401         case AMDGPU_IRQ_STATE_ENABLE:
1402                 /* system context */
1403                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1404                 tmp |= bits;
1405                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1406                 /* VMs */
1407                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1408                 tmp |= bits;
1409                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1410                 break;
1411         default:
1412                 break;
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1419                                       struct amdgpu_irq_src *source,
1420                                       struct amdgpu_iv_entry *entry)
1421 {
1422         u32 addr, status, mc_client, vmid;
1423
1424         if (amdgpu_sriov_vf(adev)) {
1425                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1426                         entry->src_id, entry->src_data[0]);
1427                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1428                 return 0;
1429         }
1430
1431         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1432         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1433         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1434         /* reset addr and status */
1435         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1436
1437         if (!addr && !status)
1438                 return 0;
1439
1440         amdgpu_vm_update_fault_cache(adev, entry->pasid,
1441                                      ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));
1442
1443         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1444                 gmc_v8_0_set_fault_enable_default(adev, false);
1445
1446         if (printk_ratelimit()) {
1447                 struct amdgpu_task_info task_info;
1448
1449                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1450                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1451
1452                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1453                         entry->src_id, entry->src_data[0], task_info.process_name,
1454                         task_info.tgid, task_info.task_name, task_info.pid);
1455                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1456                         addr);
1457                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1458                         status);
1459                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1460                                          entry->pasid);
1461         }
1462
1463         vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1464                              VMID);
1465         if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1466                 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1467                 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1468                 u32 protections = REG_GET_FIELD(status,
1469                                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1470                                         PROTECTIONS);
1471
1472                 info->vmid = vmid;
1473                 info->mc_id = REG_GET_FIELD(status,
1474                                             VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1475                                             MEMORY_CLIENT_ID);
1476                 info->status = status;
1477                 info->page_addr = addr;
1478                 info->prot_valid = protections & 0x7 ? true : false;
1479                 info->prot_read = protections & 0x8 ? true : false;
1480                 info->prot_write = protections & 0x10 ? true : false;
1481                 info->prot_exec = protections & 0x20 ? true : false;
1482                 mb();
1483                 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1484         }
1485
1486         return 0;
1487 }
1488
1489 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1490                                                      bool enable)
1491 {
1492         uint32_t data;
1493
1494         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1495                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1496                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1497                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1498
1499                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1500                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1501                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1502
1503                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1504                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1505                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1506
1507                 data = RREG32(mmMC_XPB_CLK_GAT);
1508                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1509                 WREG32(mmMC_XPB_CLK_GAT, data);
1510
1511                 data = RREG32(mmATC_MISC_CG);
1512                 data |= ATC_MISC_CG__ENABLE_MASK;
1513                 WREG32(mmATC_MISC_CG, data);
1514
1515                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1516                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1517                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1518
1519                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1520                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1521                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1522
1523                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1524                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1525                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1526
1527                 data = RREG32(mmVM_L2_CG);
1528                 data |= VM_L2_CG__ENABLE_MASK;
1529                 WREG32(mmVM_L2_CG, data);
1530         } else {
1531                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1532                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1533                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1534
1535                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1536                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1537                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1538
1539                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1540                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1541                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1542
1543                 data = RREG32(mmMC_XPB_CLK_GAT);
1544                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1545                 WREG32(mmMC_XPB_CLK_GAT, data);
1546
1547                 data = RREG32(mmATC_MISC_CG);
1548                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1549                 WREG32(mmATC_MISC_CG, data);
1550
1551                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1552                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1553                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1554
1555                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1556                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1557                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1558
1559                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1560                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1561                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1562
1563                 data = RREG32(mmVM_L2_CG);
1564                 data &= ~VM_L2_CG__ENABLE_MASK;
1565                 WREG32(mmVM_L2_CG, data);
1566         }
1567 }
1568
1569 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1570                                        bool enable)
1571 {
1572         uint32_t data;
1573
1574         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1575                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1576                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1577                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1578
1579                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1580                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1581                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1582
1583                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1584                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1585                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1586
1587                 data = RREG32(mmMC_XPB_CLK_GAT);
1588                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1589                 WREG32(mmMC_XPB_CLK_GAT, data);
1590
1591                 data = RREG32(mmATC_MISC_CG);
1592                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1593                 WREG32(mmATC_MISC_CG, data);
1594
1595                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1596                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1597                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1598
1599                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1600                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1601                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1602
1603                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1604                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1605                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1606
1607                 data = RREG32(mmVM_L2_CG);
1608                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1609                 WREG32(mmVM_L2_CG, data);
1610         } else {
1611                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1612                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1613                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1614
1615                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1616                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1617                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1618
1619                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1620                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1621                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1622
1623                 data = RREG32(mmMC_XPB_CLK_GAT);
1624                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1625                 WREG32(mmMC_XPB_CLK_GAT, data);
1626
1627                 data = RREG32(mmATC_MISC_CG);
1628                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1629                 WREG32(mmATC_MISC_CG, data);
1630
1631                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1632                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1633                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1634
1635                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1636                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1637                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1638
1639                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1640                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1641                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1642
1643                 data = RREG32(mmVM_L2_CG);
1644                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1645                 WREG32(mmVM_L2_CG, data);
1646         }
1647 }
1648
1649 static int gmc_v8_0_set_clockgating_state(void *handle,
1650                                           enum amd_clockgating_state state)
1651 {
1652         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1653
1654         if (amdgpu_sriov_vf(adev))
1655                 return 0;
1656
1657         switch (adev->asic_type) {
1658         case CHIP_FIJI:
1659                 fiji_update_mc_medium_grain_clock_gating(adev,
1660                                 state == AMD_CG_STATE_GATE);
1661                 fiji_update_mc_light_sleep(adev,
1662                                 state == AMD_CG_STATE_GATE);
1663                 break;
1664         default:
1665                 break;
1666         }
1667         return 0;
1668 }
1669
1670 static int gmc_v8_0_set_powergating_state(void *handle,
1671                                           enum amd_powergating_state state)
1672 {
1673         return 0;
1674 }
1675
1676 static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags)
1677 {
1678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1679         int data;
1680
1681         if (amdgpu_sriov_vf(adev))
1682                 *flags = 0;
1683
1684         /* AMD_CG_SUPPORT_MC_MGCG */
1685         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1686         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1687                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1688
1689         /* AMD_CG_SUPPORT_MC_LS */
1690         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1691                 *flags |= AMD_CG_SUPPORT_MC_LS;
1692 }
1693
1694 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1695         .name = "gmc_v8_0",
1696         .early_init = gmc_v8_0_early_init,
1697         .late_init = gmc_v8_0_late_init,
1698         .sw_init = gmc_v8_0_sw_init,
1699         .sw_fini = gmc_v8_0_sw_fini,
1700         .hw_init = gmc_v8_0_hw_init,
1701         .hw_fini = gmc_v8_0_hw_fini,
1702         .suspend = gmc_v8_0_suspend,
1703         .resume = gmc_v8_0_resume,
1704         .is_idle = gmc_v8_0_is_idle,
1705         .wait_for_idle = gmc_v8_0_wait_for_idle,
1706         .check_soft_reset = gmc_v8_0_check_soft_reset,
1707         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1708         .soft_reset = gmc_v8_0_soft_reset,
1709         .post_soft_reset = gmc_v8_0_post_soft_reset,
1710         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1711         .set_powergating_state = gmc_v8_0_set_powergating_state,
1712         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1713 };
1714
1715 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1716         .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1717         .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1718         .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1719         .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1720         .set_prt = gmc_v8_0_set_prt,
1721         .get_vm_pde = gmc_v8_0_get_vm_pde,
1722         .get_vm_pte = gmc_v8_0_get_vm_pte,
1723         .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size,
1724 };
1725
1726 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1727         .set = gmc_v8_0_vm_fault_interrupt_state,
1728         .process = gmc_v8_0_process_interrupt,
1729 };
1730
1731 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1732 {
1733         adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1734 }
1735
1736 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1737 {
1738         adev->gmc.vm_fault.num_types = 1;
1739         adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1740 }
1741
1742 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = {
1743         .type = AMD_IP_BLOCK_TYPE_GMC,
1744         .major = 8,
1745         .minor = 0,
1746         .rev = 0,
1747         .funcs = &gmc_v8_0_ip_funcs,
1748 };
1749
1750 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = {
1751         .type = AMD_IP_BLOCK_TYPE_GMC,
1752         .major = 8,
1753         .minor = 1,
1754         .rev = 0,
1755         .funcs = &gmc_v8_0_ip_funcs,
1756 };
1757
1758 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = {
1759         .type = AMD_IP_BLOCK_TYPE_GMC,
1760         .major = 8,
1761         .minor = 5,
1762         .rev = 0,
1763         .funcs = &gmc_v8_0_ip_funcs,
1764 };