drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "mmhub_v1_8.h"
  25
  26 #include "mmhub/mmhub_1_8_0_offset.h"
  27 #include "mmhub/mmhub_1_8_0_sh_mask.h"
  28 #include "vega10_enum.h"
  29
  30 #include "soc15_common.h"
  31 #include "soc15.h"
  32
  33 #define regVM_L2_CNTL3_DEFAULT  0x80100007
  34 #define regVM_L2_CNTL4_DEFAULT  0x000000c1
  35
  36 static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev)
  37 {
  38         u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);
  39         u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);
  40
  41         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  42         base <<= 24;
  43
  44         top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  45         top <<= 24;
  46
  47         adev->gmc.fb_start = base;
  48         adev->gmc.fb_end = top;
  49
  50         return base;
  51 }
  52
  53 static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  54                                 uint64_t page_table_base)
  55 {
  56         struct amdgpu_vmhub *hub;
  57         int i;
  58
  59         for (i = 0; i < adev->num_aid; i++) {
  60                 hub = &adev->vmhub[AMDGPU_MMHUB0(i)];
  61                 WREG32_SOC15_OFFSET(MMHUB, i,
  62                                     regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  63                                     hub->ctx_addr_distance * vmid,
  64                                     lower_32_bits(page_table_base));
  65
  66                 WREG32_SOC15_OFFSET(MMHUB, i,
  67                                     regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  68                                     hub->ctx_addr_distance * vmid,
  69                                     upper_32_bits(page_table_base));
  70         }
  71 }
  72
  73 static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
  74 {
  75         uint64_t pt_base;
  76         int i;
  77
  78         if (adev->gmc.pdb0_bo)
  79                 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
  80         else
  81                 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  82
  83         mmhub_v1_8_setup_vm_pt_regs(adev, 0, pt_base);
  84
  85         /* If use GART for FB translation, vmid0 page table covers both
  86          * vram and system memory (gart)
  87          */
  88         for (i = 0; i < adev->num_aid; i++) {
  89                 if (adev->gmc.pdb0_bo) {
  90                         WREG32_SOC15(MMHUB, i,
  91                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  92                                      (u32)(adev->gmc.fb_start >> 12));
  93                         WREG32_SOC15(MMHUB, i,
  94                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  95                                      (u32)(adev->gmc.fb_start >> 44));
  96
  97                         WREG32_SOC15(MMHUB, i,
  98                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  99                                      (u32)(adev->gmc.gart_end >> 12));
 100                         WREG32_SOC15(MMHUB, i,
 101                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 102                                      (u32)(adev->gmc.gart_end >> 44));
 103
 104                 } else {
 105                         WREG32_SOC15(MMHUB, i,
 106                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 107                                      (u32)(adev->gmc.gart_start >> 12));
 108                         WREG32_SOC15(MMHUB, i,
 109                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 110                                      (u32)(adev->gmc.gart_start >> 44));
 111
 112                         WREG32_SOC15(MMHUB, i,
 113                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 114                                      (u32)(adev->gmc.gart_end >> 12));
 115                         WREG32_SOC15(MMHUB, i,
 116                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 117                                      (u32)(adev->gmc.gart_end >> 44));
 118                 }
 119         }
 120 }
 121
 122 static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
 123 {
 124         uint64_t value;
 125         uint32_t tmp;
 126         int i;
 127
 128         for (i = 0; i < adev->num_aid; i++) {
 129                 /* Program the AGP BAR */
 130                 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0);
 131                 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT,
 132                              adev->gmc.agp_start >> 24);
 133                 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP,
 134                              adev->gmc.agp_end >> 24);
 135
 136                 if (amdgpu_sriov_vf(adev))
 137                         return;
 138
 139                 /* Program the system aperture low logical page number. */
 140                 WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 141                         min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 142
 143                 WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 144                         max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 145
 146                 /* In the case squeezing vram into GART aperture, we don't use
 147                  * FB aperture and AGP aperture. Disable them.
 148                  */
 149                 if (adev->gmc.pdb0_bo) {
 150                         WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT, 0xFFFFFF);
 151                         WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP, 0);
 152                         WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_TOP, 0);
 153                         WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_BASE,
 154                                      0x00FFFFFF);
 155                         WREG32_SOC15(MMHUB, i,
 156                                      regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 157                                      0x3FFFFFFF);
 158                         WREG32_SOC15(MMHUB, i,
 159                                      regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 160                 }
 161
 162                 /* Set default page address. */
 163                 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
 164                 WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 165                              (u32)(value >> 12));
 166                 WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 167                              (u32)(value >> 44));
 168
 169                 /* Program "protection fault". */
 170                 WREG32_SOC15(MMHUB, i,
 171                              regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 172                              (u32)(adev->dummy_page_addr >> 12));
 173                 WREG32_SOC15(MMHUB, i,
 174                              regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 175                              (u32)((u64)adev->dummy_page_addr >> 44));
 176
 177                 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2);
 178                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 179                                     ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 180                 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 181         }
 182 }
 183
 184 static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
 185 {
 186         uint32_t tmp;
 187         int i;
 188
 189         /* Setup TLB control */
 190         for (i = 0; i < adev->num_aid; i++) {
 191                 tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);
 192
 193                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
 194                                     1);
 195                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 196                                     SYSTEM_ACCESS_MODE, 3);
 197                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 198                                     ENABLE_ADVANCED_DRIVER_MODEL, 1);
 199                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 200                                     SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 201                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 202                                     MTYPE, MTYPE_UC);/* XXX for emulation. */
 203                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 204
 205                 WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);
 206         }
 207 }
 208
 209 static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
 210 {
 211         uint32_t tmp;
 212         int i;
 213
 214         if (amdgpu_sriov_vf(adev))
 215                 return;
 216
 217         /* Setup L2 cache */
 218         for (i = 0; i < adev->num_aid; i++) {
 219                 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);
 220                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 221                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
 222                                     ENABLE_L2_FRAGMENT_PROCESSING, 1);
 223                 /* XXX for emulation, Refer to closed source code.*/
 224                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
 225                                     L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 226                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION,
 227                                     0);
 228                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
 229                                     CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 230                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
 231                                     IDENTITY_MODE_FRAGMENT_SIZE, 0);
 232                 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL, tmp);
 233
 234                 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL2);
 235                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS,
 236                                     1);
 237                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 238                 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL2, tmp);
 239
 240                 tmp = regVM_L2_CNTL3_DEFAULT;
 241                 if (adev->gmc.translate_further) {
 242                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 243                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 244                                             L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 245                 } else {
 246                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 247                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 248                                             L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 249                 }
 250                 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL3, tmp);
 251
 252                 tmp = regVM_L2_CNTL4_DEFAULT;
 253                 if (adev->gmc.xgmi.connected_to_cpu) {
 254                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 255                                             VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 256                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 257                                             VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 258                 } else {
 259                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 260                                             VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 261                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 262                                             VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 263                 }
 264                 WREG32_SOC15(MMHUB, i, regVM_L2_CNTL4, tmp);
 265         }
 266 }
 267
 268 static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
 269 {
 270         uint32_t tmp;
 271         int i;
 272
 273         for (i = 0; i < adev->num_aid; i++) {
 274                 tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);
 275                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 276                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
 277                                 adev->gmc.vmid0_page_table_depth);
 278                 tmp = REG_SET_FIELD(tmp,
 279                                     VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
 280                                     adev->gmc.vmid0_page_table_block_size);
 281                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 282                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 283                 WREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL, tmp);
 284         }
 285 }
 286
 287 static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)
 288 {
 289         int i;
 290
 291         if (amdgpu_sriov_vf(adev))
 292                 return;
 293
 294         for (i = 0; i < adev->num_aid; i++) {
 295                 WREG32_SOC15(MMHUB, i,
 296                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 297                              0XFFFFFFFF);
 298                 WREG32_SOC15(MMHUB, i,
 299                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 300                              0x0000000F);
 301
 302                 WREG32_SOC15(MMHUB, i,
 303                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 304                              0);
 305                 WREG32_SOC15(MMHUB, i,
 306                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 307                              0);
 308
 309                 WREG32_SOC15(MMHUB, i,
 310                              regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 311                 WREG32_SOC15(MMHUB, i,
 312                              regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 313         }
 314 }
 315
 316 static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
 317 {
 318         struct amdgpu_vmhub *hub;
 319         unsigned num_level, block_size;
 320         uint32_t tmp;
 321         int i, j;
 322
 323         num_level = adev->vm_manager.num_level;
 324         block_size = adev->vm_manager.block_size;
 325         if (adev->gmc.translate_further)
 326                 num_level -= 1;
 327         else
 328                 block_size -= 9;
 329
 330         for (j = 0; j < adev->num_aid; j++) {
 331                 hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
 332                 for (i = 0; i <= 14; i++) {
 333                         tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
 334                                                   i);
 335                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 336                                             ENABLE_CONTEXT, 1);
 337                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 338                                             PAGE_TABLE_DEPTH, num_level);
 339                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 340                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 341                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 342                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 343                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 344                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 345                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 346                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 347                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 348                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 349                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 350                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 351                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 352                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 353                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 354                                             PAGE_TABLE_BLOCK_SIZE,
 355                                             block_size);
 356                         /* On 9.4.3, XNACK can be enabled in the SQ
 357                          * per-process. Retry faults need to be enabled for
 358                          * that to work.
 359                          */
 360                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 361                                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1);
 362                         WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
 363                                             i * hub->ctx_distance, tmp);
 364                         WREG32_SOC15_OFFSET(MMHUB, j,
 365                                 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 366                                 i * hub->ctx_addr_distance, 0);
 367                         WREG32_SOC15_OFFSET(MMHUB, j,
 368                                 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 369                                 i * hub->ctx_addr_distance, 0);
 370                         WREG32_SOC15_OFFSET(MMHUB, j,
 371                                 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 372                                 i * hub->ctx_addr_distance,
 373                                 lower_32_bits(adev->vm_manager.max_pfn - 1));
 374                         WREG32_SOC15_OFFSET(MMHUB, j,
 375                                 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 376                                 i * hub->ctx_addr_distance,
 377                                 upper_32_bits(adev->vm_manager.max_pfn - 1));
 378                 }
 379         }
 380 }
 381
 382 static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)
 383 {
 384         struct amdgpu_vmhub *hub;
 385         unsigned i, j;
 386
 387         for (j = 0; j < adev->num_aid; j++) {
 388                 hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
 389                 for (i = 0; i < 18; ++i) {
 390                         WREG32_SOC15_OFFSET(MMHUB, j,
 391                                         regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 392                                         i * hub->eng_addr_distance, 0xffffffff);
 393                         WREG32_SOC15_OFFSET(MMHUB, j,
 394                                         regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 395                                         i * hub->eng_addr_distance, 0x1f);
 396                 }
 397         }
 398 }
 399
 400 static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)
 401 {
 402         if (amdgpu_sriov_vf(adev)) {
 403                 /*
 404                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 405                  * VF copy registers so vbios post doesn't program them, for
 406                  * SRIOV driver need to program them
 407                  */
 408                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE,
 409                              adev->gmc.vram_start >> 24);
 410                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP,
 411                              adev->gmc.vram_end >> 24);
 412         }
 413
 414         /* GART Enable. */
 415         mmhub_v1_8_init_gart_aperture_regs(adev);
 416         mmhub_v1_8_init_system_aperture_regs(adev);
 417         mmhub_v1_8_init_tlb_regs(adev);
 418         mmhub_v1_8_init_cache_regs(adev);
 419
 420         mmhub_v1_8_enable_system_domain(adev);
 421         mmhub_v1_8_disable_identity_aperture(adev);
 422         mmhub_v1_8_setup_vmid_config(adev);
 423         mmhub_v1_8_program_invalidation(adev);
 424
 425         return 0;
 426 }
 427
 428 static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
 429 {
 430         struct amdgpu_vmhub *hub;
 431         u32 tmp;
 432         u32 i, j;
 433
 434         /* Disable all tables */
 435         for (j = 0; j < adev->num_aid; j++) {
 436                 hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
 437                 for (i = 0; i < 16; i++)
 438                         WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT0_CNTL,
 439                                             i * hub->ctx_distance, 0);
 440
 441                 /* Setup TLB control */
 442                 tmp = RREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL);
 443                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
 444                                     0);
 445                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 446                                     ENABLE_ADVANCED_DRIVER_MODEL, 0);
 447                 WREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL, tmp);
 448
 449                 if (!amdgpu_sriov_vf(adev)) {
 450                         /* Setup L2 cache */
 451                         tmp = RREG32_SOC15(MMHUB, j, regVM_L2_CNTL);
 452                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE,
 453                                             0);
 454                         WREG32_SOC15(MMHUB, j, regVM_L2_CNTL, tmp);
 455                         WREG32_SOC15(MMHUB, j, regVM_L2_CNTL3, 0);
 456                 }
 457         }
 458 }
 459
 460 /**
 461  * mmhub_v1_8_set_fault_enable_default - update GART/VM fault handling
 462  *
 463  * @adev: amdgpu_device pointer
 464  * @value: true redirects VM faults to the default page
 465  */
 466 static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 467 {
 468         u32 tmp;
 469         int i;
 470
 471         if (amdgpu_sriov_vf(adev))
 472                 return;
 473
 474         for (i = 0; i < adev->num_aid; i++) {
 475                 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);
 476                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 477                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 478                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 479                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 480                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 481                                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 482                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 483                                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 484                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 485                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 486                         value);
 487                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 488                                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 489                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 490                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 491                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 492                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 493                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 494                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 495                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 496                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 497                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 498                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 499                 if (!value) {
 500                         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 501                                             CRASH_ON_NO_RETRY_FAULT, 1);
 502                         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 503                                             CRASH_ON_RETRY_FAULT, 1);
 504                 }
 505
 506                 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
 507         }
 508 }
 509
 510 static void mmhub_v1_8_init(struct amdgpu_device *adev)
 511 {
 512         struct amdgpu_vmhub *hub;
 513         int i;
 514
 515         for (i = 0; i < adev->num_aid; i++) {
 516                 hub = &adev->vmhub[AMDGPU_MMHUB0(i)];
 517
 518                 hub->ctx0_ptb_addr_lo32 = SOC15_REG_OFFSET(MMHUB, 0,
 519                         regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 520                 hub->ctx0_ptb_addr_hi32 = SOC15_REG_OFFSET(MMHUB, 0,
 521                         regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 522                 hub->vm_inv_eng0_req =
 523                         SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
 524                 hub->vm_inv_eng0_ack =
 525                         SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);
 526                 hub->vm_context0_cntl =
 527                         SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);
 528                 hub->vm_l2_pro_fault_status = SOC15_REG_OFFSET(MMHUB, 0,
 529                         regVM_L2_PROTECTION_FAULT_STATUS);
 530                 hub->vm_l2_pro_fault_cntl = SOC15_REG_OFFSET(MMHUB, 0,
 531                         regVM_L2_PROTECTION_FAULT_CNTL);
 532
 533                 hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;
 534                 hub->ctx_addr_distance =
 535                         regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 536                         regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 537                 hub->eng_distance = regVM_INVALIDATE_ENG1_REQ -
 538                         regVM_INVALIDATE_ENG0_REQ;
 539                 hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 540                         regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 541         }
 542 }
 543
 544 static int mmhub_v1_8_set_clockgating(struct amdgpu_device *adev,
 545                                       enum amd_clockgating_state state)
 546 {
 547         return 0;
 548 }
 549
 550 static void mmhub_v1_8_get_clockgating(struct amdgpu_device *adev, u64 *flags)
 551 {
 552
 553 }
 554
 555 const struct amdgpu_mmhub_funcs mmhub_v1_8_funcs = {
 556         .get_fb_location = mmhub_v1_8_get_fb_location,
 557         .init = mmhub_v1_8_init,
 558         .gart_enable = mmhub_v1_8_gart_enable,
 559         .set_fault_enable_default = mmhub_v1_8_set_fault_enable_default,
 560         .gart_disable = mmhub_v1_8_gart_disable,
 561         .setup_vm_pt_regs = mmhub_v1_8_setup_vm_pt_regs,
 562         .set_clockgating = mmhub_v1_8_set_clockgating,
 563         .get_clockgating = mmhub_v1_8_get_clockgating,
 564 };