drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "gfxhub_v1_2.h"
  25 #include "gfxhub_v1_1.h"
  26
  27 #include "gc/gc_9_4_3_offset.h"
  28 #include "gc/gc_9_4_3_sh_mask.h"
  29 #include "vega10_enum.h"
  30
  31 #include "soc15_common.h"
  32
  33 #define regVM_L2_CNTL3_DEFAULT  0x80100007
  34 #define regVM_L2_CNTL4_DEFAULT  0x000000c1
  35
  36 static u64 gfxhub_v1_2_get_mc_fb_offset(struct amdgpu_device *adev)
  37 {
  38         return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;
  39 }
  40
  41 static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev,
  42                                          uint32_t vmid,
  43                                          uint64_t page_table_base)
  44 {
  45         struct amdgpu_vmhub *hub;
  46         int i, num_xcc;
  47
  48         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
  49         for (i = 0; i < num_xcc; i++) {
  50                 hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
  51                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),
  52                                     regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  53                                     hub->ctx_addr_distance * vmid,
  54                                     lower_32_bits(page_table_base));
  55
  56                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),
  57                                     regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  58                                     hub->ctx_addr_distance * vmid,
  59                                     upper_32_bits(page_table_base));
  60
  61         }
  62 }
  63
  64 static void gfxhub_v1_2_init_gart_aperture_regs(struct amdgpu_device *adev)
  65 {
  66         uint64_t pt_base;
  67         int i, num_xcc;
  68
  69         if (adev->gmc.pdb0_bo)
  70                 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
  71         else
  72                 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  73
  74         gfxhub_v1_2_setup_vm_pt_regs(adev, 0, pt_base);
  75
  76         /* If use GART for FB translation, vmid0 page table covers both
  77          * vram and system memory (gart)
  78          */
  79         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
  80         for (i = 0; i < num_xcc; i++) {
  81                 if (adev->gmc.pdb0_bo) {
  82                         WREG32_SOC15(GC, GET_INST(GC, i),
  83                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  84                                      (u32)(adev->gmc.fb_start >> 12));
  85                         WREG32_SOC15(GC, GET_INST(GC, i),
  86                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  87                                      (u32)(adev->gmc.fb_start >> 44));
  88
  89                         WREG32_SOC15(GC, GET_INST(GC, i),
  90                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  91                                      (u32)(adev->gmc.gart_end >> 12));
  92                         WREG32_SOC15(GC, GET_INST(GC, i),
  93                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  94                                      (u32)(adev->gmc.gart_end >> 44));
  95                 } else {
  96                         WREG32_SOC15(GC, GET_INST(GC, i),
  97                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  98                                      (u32)(adev->gmc.gart_start >> 12));
  99                         WREG32_SOC15(GC, GET_INST(GC, i),
 100                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 101                                      (u32)(adev->gmc.gart_start >> 44));
 102
 103                         WREG32_SOC15(GC, GET_INST(GC, i),
 104                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 105                                      (u32)(adev->gmc.gart_end >> 12));
 106                         WREG32_SOC15(GC, GET_INST(GC, i),
 107                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 108                                      (u32)(adev->gmc.gart_end >> 44));
 109                 }
 110         }
 111 }
 112
 113 static void gfxhub_v1_2_init_system_aperture_regs(struct amdgpu_device *adev)
 114 {
 115         uint64_t value;
 116         uint32_t tmp;
 117         int i, num_xcc;
 118
 119         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 120         for (i = 0; i < num_xcc; i++) {
 121                 /* Program the AGP BAR */
 122                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0);
 123                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 124                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 125
 126                 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
 127                         /* Program the system aperture low logical page number. */
 128                         WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 129                                 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 130
 131                         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 132                                 /*
 133                                 * Raven2 has a HW issue that it is unable to use the
 134                                 * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
 135                                 * So here is the workaround that increase system
 136                                 * aperture high address (add 1) to get rid of the VM
 137                                 * fault and hardware hang.
 138                                 */
 139                                 WREG32_SOC15_RLC(GC, GET_INST(GC, i),
 140                                                  regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 141                                                  max((adev->gmc.fb_end >> 18) + 0x1,
 142                                                      adev->gmc.agp_end >> 18));
 143                         else
 144                                 WREG32_SOC15_RLC(GC, GET_INST(GC, i),
 145                                         regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 146                                         max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 147
 148                         /* Set default page address. */
 149                         value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
 150                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 151                                      (u32)(value >> 12));
 152                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 153                                      (u32)(value >> 44));
 154
 155                         /* Program "protection fault". */
 156                         WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 157                                      (u32)(adev->dummy_page_addr >> 12));
 158                         WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 159                                      (u32)((u64)adev->dummy_page_addr >> 44));
 160
 161                         tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);
 162                         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 163                                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 164                         WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 165                 }
 166
 167                 /* In the case squeezing vram into GART aperture, we don't use
 168                  * FB aperture and AGP aperture. Disable them.
 169                  */
 170                 if (adev->gmc.pdb0_bo) {
 171                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, 0);
 172                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
 173                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, 0);
 174                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, 0xFFFFFF);
 175                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 176                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 177                 }
 178         }
 179 }
 180
 181 static void gfxhub_v1_2_init_tlb_regs(struct amdgpu_device *adev)
 182 {
 183         uint32_t tmp;
 184         int i, num_xcc;
 185
 186         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 187         for (i = 0; i < num_xcc; i++) {
 188                 /* Setup TLB control */
 189                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);
 190
 191                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 192                                     ENABLE_L1_TLB, 1);
 193                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 194                                     SYSTEM_ACCESS_MODE, 3);
 195                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 196                                     ENABLE_ADVANCED_DRIVER_MODEL, 1);
 197                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 198                                     SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 199                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 200                                     MTYPE, MTYPE_UC);/* XXX for emulation. */
 201                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 202
 203                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp);
 204         }
 205 }
 206
 207 static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev)
 208 {
 209         uint32_t tmp;
 210         int i, num_xcc;
 211
 212         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 213         for (i = 0; i < num_xcc; i++) {
 214                 /* Setup L2 cache */
 215                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);
 216                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 217                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 218                 /* XXX for emulation, Refer to closed source code.*/
 219                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 220                                     0);
 221                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 222                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 223                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 224                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp);
 225
 226                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);
 227                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 228                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 229                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp);
 230
 231                 tmp = regVM_L2_CNTL3_DEFAULT;
 232                 if (adev->gmc.translate_further) {
 233                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 234                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 235                                             L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 236                 } else {
 237                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 238                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 239                                             L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 240                 }
 241                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);
 242
 243                 tmp = regVM_L2_CNTL4_DEFAULT;
 244                 if (adev->gmc.xgmi.connected_to_cpu) {
 245                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 246                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 247                 } else {
 248                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 249                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 250                 }
 251                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp);
 252         }
 253 }
 254
 255 static void gfxhub_v1_2_enable_system_domain(struct amdgpu_device *adev)
 256 {
 257         uint32_t tmp;
 258         int i, num_xcc;
 259
 260         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 261         for (i = 0; i < num_xcc; i++) {
 262                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);
 263                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 264                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
 265                                 adev->gmc.vmid0_page_table_depth);
 266                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
 267                                 adev->gmc.vmid0_page_table_block_size);
 268                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 269                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 270                 WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp);
 271         }
 272 }
 273
 274 static void gfxhub_v1_2_disable_identity_aperture(struct amdgpu_device *adev)
 275 {
 276         int i, num_xcc;
 277
 278         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 279         for (i = 0; i < num_xcc; i++) {
 280                 WREG32_SOC15(GC, GET_INST(GC, i),
 281                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 282                              0XFFFFFFFF);
 283                 WREG32_SOC15(GC, GET_INST(GC, i),
 284                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 285                              0x0000000F);
 286
 287                 WREG32_SOC15(GC, GET_INST(GC, i),
 288                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 289                              0);
 290                 WREG32_SOC15(GC, GET_INST(GC, i),
 291                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 292                              0);
 293
 294                 WREG32_SOC15(GC, GET_INST(GC, i),
 295                              regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 296                 WREG32_SOC15(GC, GET_INST(GC, i),
 297                              regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 298         }
 299 }
 300
 301 static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev)
 302 {
 303         struct amdgpu_vmhub *hub;
 304         unsigned num_level, block_size;
 305         uint32_t tmp;
 306         int i, j, num_xcc;
 307
 308         num_level = adev->vm_manager.num_level;
 309         block_size = adev->vm_manager.block_size;
 310         if (adev->gmc.translate_further)
 311                 num_level -= 1;
 312         else
 313                 block_size -= 9;
 314
 315         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 316         for (j = 0; j < num_xcc; j++) {
 317                 hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
 318                 for (i = 0; i <= 14; i++) {
 319                         tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, i);
 320                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 321                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 322                                             num_level);
 323                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 324                                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 325                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 326                                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 327                                             1);
 328                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 329                                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 330                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 331                                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 332                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 333                                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 334                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 335                                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 336                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 337                                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 338                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 339                                             PAGE_TABLE_BLOCK_SIZE,
 340                                             block_size);
 341                         /* Send no-retry XNACK on fault to suppress VM fault storm.
 342                          * On 9.4.2 and 9.4.3, XNACK can be enabled in
 343                          * the SQ per-process.
 344                          * Retry faults need to be enabled for that to work.
 345                          */
 346                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 347                                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 348                                             !adev->gmc.noretry ||
 349                                             adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
 350                                             adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3));
 351                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,
 352                                             i * hub->ctx_distance, tmp);
 353                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
 354                                             regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 355                                             i * hub->ctx_addr_distance, 0);
 356                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
 357                                             regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 358                                             i * hub->ctx_addr_distance, 0);
 359                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
 360                                             regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 361                                             i * hub->ctx_addr_distance,
 362                                             lower_32_bits(adev->vm_manager.max_pfn - 1));
 363                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
 364                                             regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 365                                             i * hub->ctx_addr_distance,
 366                                             upper_32_bits(adev->vm_manager.max_pfn - 1));
 367                 }
 368         }
 369 }
 370
 371 static void gfxhub_v1_2_program_invalidation(struct amdgpu_device *adev)
 372 {
 373         struct amdgpu_vmhub *hub;
 374         unsigned i, j, num_xcc;
 375
 376         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 377         for (j = 0; j < num_xcc; j++) {
 378                 hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
 379
 380                 for (i = 0 ; i < 18; ++i) {
 381                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 382                                             i * hub->eng_addr_distance, 0xffffffff);
 383                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 384                                             i * hub->eng_addr_distance, 0x1f);
 385                 }
 386         }
 387 }
 388
 389 static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev)
 390 {
 391         int i, num_xcc;
 392
 393         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 394         for (i = 0; i < num_xcc; i++) {
 395                 if (amdgpu_sriov_vf(adev)) {
 396                 /*
 397                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 398                  * VF copy registers so vbios post doesn't program them, for
 399                  * SRIOV driver need to program them
 400                  */
 401                         WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE,
 402                                      adev->gmc.vram_start >> 24);
 403                         WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP,
 404                                      adev->gmc.vram_end >> 24);
 405                 }
 406         }
 407
 408         /* GART Enable. */
 409         gfxhub_v1_2_init_gart_aperture_regs(adev);
 410         gfxhub_v1_2_init_system_aperture_regs(adev);
 411         gfxhub_v1_2_init_tlb_regs(adev);
 412         if (!amdgpu_sriov_vf(adev))
 413                 gfxhub_v1_2_init_cache_regs(adev);
 414
 415         gfxhub_v1_2_enable_system_domain(adev);
 416         if (!amdgpu_sriov_vf(adev))
 417                 gfxhub_v1_2_disable_identity_aperture(adev);
 418         gfxhub_v1_2_setup_vmid_config(adev);
 419         gfxhub_v1_2_program_invalidation(adev);
 420
 421         return 0;
 422 }
 423
 424 static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev)
 425 {
 426         struct amdgpu_vmhub *hub;
 427         u32 tmp;
 428         u32 i, j, num_xcc;
 429
 430         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 431         for (j = 0; j < num_xcc; j++) {
 432                 hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
 433                 /* Disable all tables */
 434                 for (i = 0; i < 16; i++)
 435                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT0_CNTL,
 436                                             i * hub->ctx_distance, 0);
 437
 438                 /* Setup TLB control */
 439                 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);
 440                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 441                 tmp = REG_SET_FIELD(tmp,
 442                                         MC_VM_MX_L1_TLB_CNTL,
 443                                         ENABLE_ADVANCED_DRIVER_MODEL,
 444                                         0);
 445                 WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);
 446
 447                 /* Setup L2 cache */
 448                 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);
 449                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 450                 WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);
 451                 WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);
 452         }
 453 }
 454
 455 /**
 456  * gfxhub_v1_2_set_fault_enable_default - update GART/VM fault handling
 457  *
 458  * @adev: amdgpu_device pointer
 459  * @value: true redirects VM faults to the default page
 460  */
 461 static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev,
 462                                                  bool value)
 463 {
 464         u32 tmp;
 465         int i, num_xcc;
 466
 467         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 468         for (i = 0; i < num_xcc; i++) {
 469                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);
 470                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 471                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 472                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 473                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 474                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 475                                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 476                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 477                                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 478                 tmp = REG_SET_FIELD(tmp,
 479                                 VM_L2_PROTECTION_FAULT_CNTL,
 480                                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 481                                 value);
 482                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 483                                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 484                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 485                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 486                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 487                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 488                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 489                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 490                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 491                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 492                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 493                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 494                 if (!value) {
 495                         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 496                                         CRASH_ON_NO_RETRY_FAULT, 1);
 497                         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 498                                         CRASH_ON_RETRY_FAULT, 1);
 499                 }
 500                 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp);
 501         }
 502 }
 503
 504 static void gfxhub_v1_2_init(struct amdgpu_device *adev)
 505 {
 506         struct amdgpu_vmhub *hub;
 507         int i, num_xcc;
 508
 509         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 510         for (i = 0; i < num_xcc; i++) {
 511                 hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
 512
 513                 hub->ctx0_ptb_addr_lo32 =
 514                         SOC15_REG_OFFSET(GC, GET_INST(GC, i),
 515                                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 516                 hub->ctx0_ptb_addr_hi32 =
 517                         SOC15_REG_OFFSET(GC, GET_INST(GC, i),
 518                                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 519                 hub->vm_inv_eng0_sem =
 520                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);
 521                 hub->vm_inv_eng0_req =
 522                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);
 523                 hub->vm_inv_eng0_ack =
 524                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);
 525                 hub->vm_context0_cntl =
 526                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);
 527                 hub->vm_l2_pro_fault_status =
 528                         SOC15_REG_OFFSET(GC, GET_INST(GC, i),
 529                                 regVM_L2_PROTECTION_FAULT_STATUS);
 530                 hub->vm_l2_pro_fault_cntl =
 531                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);
 532
 533                 hub->ctx_distance = regVM_CONTEXT1_CNTL -
 534                                 regVM_CONTEXT0_CNTL;
 535                 hub->ctx_addr_distance =
 536                                 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 537                                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 538                 hub->eng_distance = regVM_INVALIDATE_ENG1_REQ -
 539                                 regVM_INVALIDATE_ENG0_REQ;
 540                 hub->eng_addr_distance =
 541                                 regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 542                                 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 543         }
 544 }
 545
 546 static int gfxhub_v1_2_get_xgmi_info(struct amdgpu_device *adev)
 547 {
 548         u32 max_num_physical_nodes;
 549         u32 max_physical_node_id;
 550         u32 xgmi_lfb_cntl;
 551         u32 max_region;
 552         u64 seg_size;
 553
 554         xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_CNTL);
 555         seg_size = REG_GET_FIELD(
 556                 RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_SIZE),
 557                 MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
 558         max_region =
 559                 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
 560
 561
 562
 563         max_num_physical_nodes   = 8;
 564         max_physical_node_id     = 7;
 565
 566         /* PF_MAX_REGION=0 means xgmi is disabled */
 567         if (max_region || adev->gmc.xgmi.connected_to_cpu) {
 568                 adev->gmc.xgmi.num_physical_nodes = max_region + 1;
 569
 570                 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
 571                         return -EINVAL;
 572
 573                 adev->gmc.xgmi.physical_node_id =
 574                         REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
 575                                         PF_LFB_REGION);
 576
 577                 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
 578                         return -EINVAL;
 579
 580                 adev->gmc.xgmi.node_segment_size = seg_size;
 581         }
 582
 583         return 0;
 584 }
 585
 586 const struct amdgpu_gfxhub_funcs gfxhub_v1_2_funcs = {
 587         .get_mc_fb_offset = gfxhub_v1_2_get_mc_fb_offset,
 588         .setup_vm_pt_regs = gfxhub_v1_2_setup_vm_pt_regs,
 589         .gart_enable = gfxhub_v1_2_gart_enable,
 590         .gart_disable = gfxhub_v1_2_gart_disable,
 591         .set_fault_enable_default = gfxhub_v1_2_set_fault_enable_default,
 592         .init = gfxhub_v1_2_init,
 593         .get_xgmi_info = gfxhub_v1_2_get_xgmi_info,
 594 };