drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_sysfs_init(struct amdgpu_device *adev);
  49 static void psp_sysfs_fini(struct amdgpu_device *adev);
  50
  51 static int psp_load_smu_fw(struct psp_context *psp);
  52 static int psp_rap_terminate(struct psp_context *psp);
  53 static int psp_securedisplay_terminate(struct psp_context *psp);
  54
  55 static int psp_ring_init(struct psp_context *psp,
  56                          enum psp_ring_type ring_type)
  57 {
  58         int ret = 0;
  59         struct psp_ring *ring;
  60         struct amdgpu_device *adev = psp->adev;
  61
  62         ring = &psp->km_ring;
  63
  64         ring->ring_type = ring_type;
  65
  66         /* allocate 4k Page of Local Frame Buffer memory for ring */
  67         ring->ring_size = 0x1000;
  68         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  69                                       AMDGPU_GEM_DOMAIN_VRAM |
  70                                       AMDGPU_GEM_DOMAIN_GTT,
  71                                       &adev->firmware.rbuf,
  72                                       &ring->ring_mem_mc_addr,
  73                                       (void **)&ring->ring_mem);
  74         if (ret) {
  75                 ring->ring_size = 0;
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 /*
  83  * Due to DF Cstate management centralized to PMFW, the firmware
  84  * loading sequence will be updated as below:
  85  *   - Load KDB
  86  *   - Load SYS_DRV
  87  *   - Load tOS
  88  *   - Load PMFW
  89  *   - Setup TMR
  90  *   - Load other non-psp fw
  91  *   - Load ASD
  92  *   - Load XGMI/RAS/HDCP/DTM TA if any
  93  *
  94  * This new sequence is required for
  95  *   - Arcturus and onwards
  96  */
  97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  98 {
  99         struct amdgpu_device *adev = psp->adev;
 100
 101         if (amdgpu_sriov_vf(adev)) {
 102                 psp->pmfw_centralized_cstate_management = false;
 103                 return;
 104         }
 105
 106         switch (adev->ip_versions[MP0_HWIP][0]) {
 107         case IP_VERSION(11, 0, 0):
 108         case IP_VERSION(11, 0, 4):
 109         case IP_VERSION(11, 0, 5):
 110         case IP_VERSION(11, 0, 7):
 111         case IP_VERSION(11, 0, 9):
 112         case IP_VERSION(11, 0, 11):
 113         case IP_VERSION(11, 0, 12):
 114         case IP_VERSION(11, 0, 13):
 115         case IP_VERSION(13, 0, 0):
 116         case IP_VERSION(13, 0, 2):
 117         case IP_VERSION(13, 0, 7):
 118                 psp->pmfw_centralized_cstate_management = true;
 119                 break;
 120         default:
 121                 psp->pmfw_centralized_cstate_management = false;
 122                 break;
 123         }
 124 }
 125
 126 static int psp_init_sriov_microcode(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         char ucode_prefix[30];
 130         int ret = 0;
 131
 132         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 133
 134         switch (adev->ip_versions[MP0_HWIP][0]) {
 135         case IP_VERSION(9, 0, 0):
 136         case IP_VERSION(11, 0, 7):
 137         case IP_VERSION(11, 0, 9):
 138                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 139                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 140                 break;
 141         case IP_VERSION(13, 0, 2):
 142                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 143                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 144                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 145                 break;
 146         case IP_VERSION(13, 0, 0):
 147                 adev->virt.autoload_ucode_id = 0;
 148                 break;
 149         case IP_VERSION(13, 0, 10):
 150                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 151                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 152                 break;
 153         default:
 154                 return -EINVAL;
 155         }
 156         return ret;
 157 }
 158
 159 static int psp_early_init(void *handle)
 160 {
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162         struct psp_context *psp = &adev->psp;
 163
 164         switch (adev->ip_versions[MP0_HWIP][0]) {
 165         case IP_VERSION(9, 0, 0):
 166                 psp_v3_1_set_psp_funcs(psp);
 167                 psp->autoload_supported = false;
 168                 break;
 169         case IP_VERSION(10, 0, 0):
 170         case IP_VERSION(10, 0, 1):
 171                 psp_v10_0_set_psp_funcs(psp);
 172                 psp->autoload_supported = false;
 173                 break;
 174         case IP_VERSION(11, 0, 2):
 175         case IP_VERSION(11, 0, 4):
 176                 psp_v11_0_set_psp_funcs(psp);
 177                 psp->autoload_supported = false;
 178                 break;
 179         case IP_VERSION(11, 0, 0):
 180         case IP_VERSION(11, 0, 5):
 181         case IP_VERSION(11, 0, 9):
 182         case IP_VERSION(11, 0, 7):
 183         case IP_VERSION(11, 0, 11):
 184         case IP_VERSION(11, 5, 0):
 185         case IP_VERSION(11, 0, 12):
 186         case IP_VERSION(11, 0, 13):
 187                 psp_v11_0_set_psp_funcs(psp);
 188                 psp->autoload_supported = true;
 189                 break;
 190         case IP_VERSION(11, 0, 3):
 191         case IP_VERSION(12, 0, 1):
 192                 psp_v12_0_set_psp_funcs(psp);
 193                 break;
 194         case IP_VERSION(13, 0, 2):
 195         case IP_VERSION(13, 0, 6):
 196                 psp_v13_0_set_psp_funcs(psp);
 197                 break;
 198         case IP_VERSION(13, 0, 1):
 199         case IP_VERSION(13, 0, 3):
 200         case IP_VERSION(13, 0, 5):
 201         case IP_VERSION(13, 0, 8):
 202         case IP_VERSION(13, 0, 10):
 203         case IP_VERSION(13, 0, 11):
 204                 psp_v13_0_set_psp_funcs(psp);
 205                 psp->autoload_supported = true;
 206                 break;
 207         case IP_VERSION(11, 0, 8):
 208                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 209                         psp_v11_0_8_set_psp_funcs(psp);
 210                         psp->autoload_supported = false;
 211                 }
 212                 break;
 213         case IP_VERSION(13, 0, 0):
 214         case IP_VERSION(13, 0, 7):
 215                 psp_v13_0_set_psp_funcs(psp);
 216                 psp->autoload_supported = true;
 217                 break;
 218         case IP_VERSION(13, 0, 4):
 219                 psp_v13_0_4_set_psp_funcs(psp);
 220                 psp->autoload_supported = true;
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225
 226         psp->adev = adev;
 227
 228         psp_check_pmfw_centralized_cstate_management(psp);
 229
 230         if (amdgpu_sriov_vf(adev))
 231                 return psp_init_sriov_microcode(psp);
 232         else
 233                 return psp_init_microcode(psp);
 234 }
 235
 236 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 237 {
 238         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 239                               &mem_ctx->shared_buf);
 240         mem_ctx->shared_bo = NULL;
 241 }
 242
 243 static void psp_free_shared_bufs(struct psp_context *psp)
 244 {
 245         void *tmr_buf;
 246         void **pptr;
 247
 248         /* free TMR memory buffer */
 249         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 250         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 251         psp->tmr_bo = NULL;
 252
 253         /* free xgmi shared memory */
 254         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 255
 256         /* free ras shared memory */
 257         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 258
 259         /* free hdcp shared memory */
 260         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 261
 262         /* free dtm shared memory */
 263         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 264
 265         /* free rap shared memory */
 266         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 267
 268         /* free securedisplay shared memory */
 269         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 270
 271
 272 }
 273
 274 static void psp_memory_training_fini(struct psp_context *psp)
 275 {
 276         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 277
 278         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 279         kfree(ctx->sys_cache);
 280         ctx->sys_cache = NULL;
 281 }
 282
 283 static int psp_memory_training_init(struct psp_context *psp)
 284 {
 285         int ret;
 286         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 287
 288         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 289                 DRM_DEBUG("memory training is not supported!\n");
 290                 return 0;
 291         }
 292
 293         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 294         if (ctx->sys_cache == NULL) {
 295                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 296                 ret = -ENOMEM;
 297                 goto Err_out;
 298         }
 299
 300         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 301                   ctx->train_data_size,
 302                   ctx->p2c_train_data_offset,
 303                   ctx->c2p_train_data_offset);
 304         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 305         return 0;
 306
 307 Err_out:
 308         psp_memory_training_fini(psp);
 309         return ret;
 310 }
 311
 312 /*
 313  * Helper funciton to query psp runtime database entry
 314  *
 315  * @adev: amdgpu_device pointer
 316  * @entry_type: the type of psp runtime database entry
 317  * @db_entry: runtime database entry pointer
 318  *
 319  * Return false if runtime database doesn't exit or entry is invalid
 320  * or true if the specific database entry is found, and copy to @db_entry
 321  */
 322 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 323                                      enum psp_runtime_entry_type entry_type,
 324                                      void *db_entry)
 325 {
 326         uint64_t db_header_pos, db_dir_pos;
 327         struct psp_runtime_data_header db_header = {0};
 328         struct psp_runtime_data_directory db_dir = {0};
 329         bool ret = false;
 330         int i;
 331
 332         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 333         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 334
 335         /* read runtime db header from vram */
 336         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 337                         sizeof(struct psp_runtime_data_header), false);
 338
 339         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 340                 /* runtime db doesn't exist, exit */
 341                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 342                 return false;
 343         }
 344
 345         /* read runtime database entry from vram */
 346         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 347                         sizeof(struct psp_runtime_data_directory), false);
 348
 349         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 350                 /* invalid db entry count, exit */
 351                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 352                 return false;
 353         }
 354
 355         /* look up for requested entry type */
 356         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 357                 if (db_dir.entry_list[i].entry_type == entry_type) {
 358                         switch (entry_type) {
 359                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 360                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 361                                         /* invalid db entry size */
 362                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 363                                         return false;
 364                                 }
 365                                 /* read runtime database entry */
 366                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 367                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 368                                 ret = true;
 369                                 break;
 370                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 371                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 372                                         /* invalid db entry size */
 373                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 374                                         return false;
 375                                 }
 376                                 /* read runtime database entry */
 377                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 378                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 379                                 ret = true;
 380                                 break;
 381                         default:
 382                                 ret = false;
 383                                 break;
 384                         }
 385                 }
 386         }
 387
 388         return ret;
 389 }
 390
 391 static int psp_sw_init(void *handle)
 392 {
 393         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 394         struct psp_context *psp = &adev->psp;
 395         int ret;
 396         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 397         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 398         struct psp_runtime_scpm_entry scpm_entry;
 399
 400         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 401         if (!psp->cmd) {
 402                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 403                 ret = -ENOMEM;
 404         }
 405
 406         adev->psp.xgmi_context.supports_extended_data =
 407                 !adev->gmc.xgmi.connected_to_cpu &&
 408                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 409
 410         memset(&scpm_entry, 0, sizeof(scpm_entry));
 411         if ((psp_get_runtime_db_entry(adev,
 412                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 413                                 &scpm_entry)) &&
 414             (scpm_entry.scpm_status != SCPM_DISABLE)) {
 415                 adev->scpm_enabled = true;
 416                 adev->scpm_status = scpm_entry.scpm_status;
 417         } else {
 418                 adev->scpm_enabled = false;
 419                 adev->scpm_status = SCPM_DISABLE;
 420         }
 421
 422         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 423
 424         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 425         if (psp_get_runtime_db_entry(adev,
 426                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 427                                 &boot_cfg_entry)) {
 428                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 429                 if ((psp->boot_cfg_bitmask) &
 430                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 431                         /* If psp runtime database exists, then
 432                          * only enable two stage memory training
 433                          * when TWO_STAGE_DRAM_TRAINING bit is set
 434                          * in runtime database */
 435                         mem_training_ctx->enable_mem_training = true;
 436                 }
 437
 438         } else {
 439                 /* If psp runtime database doesn't exist or
 440                  * is invalid, force enable two stage memory
 441                  * training */
 442                 mem_training_ctx->enable_mem_training = true;
 443         }
 444
 445         if (mem_training_ctx->enable_mem_training) {
 446                 ret = psp_memory_training_init(psp);
 447                 if (ret) {
 448                         DRM_ERROR("Failed to initialize memory training!\n");
 449                         return ret;
 450                 }
 451
 452                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 453                 if (ret) {
 454                         DRM_ERROR("Failed to process memory training!\n");
 455                         return ret;
 456                 }
 457         }
 458
 459         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 460             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 461                 ret = psp_sysfs_init(adev);
 462                 if (ret)
 463                         return ret;
 464         }
 465
 466         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 467                                       amdgpu_sriov_vf(adev) ?
 468                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 469                                       &psp->fw_pri_bo,
 470                                       &psp->fw_pri_mc_addr,
 471                                       &psp->fw_pri_buf);
 472         if (ret)
 473                 return ret;
 474
 475         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 476                                       AMDGPU_GEM_DOMAIN_VRAM,
 477                                       &psp->fence_buf_bo,
 478                                       &psp->fence_buf_mc_addr,
 479                                       &psp->fence_buf);
 480         if (ret)
 481                 goto failed1;
 482
 483         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 484                                       AMDGPU_GEM_DOMAIN_VRAM,
 485                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 486                                       (void **)&psp->cmd_buf_mem);
 487         if (ret)
 488                 goto failed2;
 489
 490         return 0;
 491
 492 failed2:
 493         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 494                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 495 failed1:
 496         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 497                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 498         return ret;
 499 }
 500
 501 static int psp_sw_fini(void *handle)
 502 {
 503         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 504         struct psp_context *psp = &adev->psp;
 505         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 506
 507         psp_memory_training_fini(psp);
 508
 509         amdgpu_ucode_release(&psp->sos_fw);
 510         amdgpu_ucode_release(&psp->asd_fw);
 511         amdgpu_ucode_release(&psp->ta_fw);
 512         amdgpu_ucode_release(&psp->cap_fw);
 513         amdgpu_ucode_release(&psp->toc_fw);
 514
 515         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 516             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 517                 psp_sysfs_fini(adev);
 518
 519         kfree(cmd);
 520         cmd = NULL;
 521
 522         psp_free_shared_bufs(psp);
 523
 524         if (psp->km_ring.ring_mem)
 525                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 526                                       &psp->km_ring.ring_mem_mc_addr,
 527                                       (void **)&psp->km_ring.ring_mem);
 528
 529         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 530                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 531         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 532                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 533         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 534                               (void **)&psp->cmd_buf_mem);
 535
 536         return 0;
 537 }
 538
 539 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 540                  uint32_t reg_val, uint32_t mask, bool check_changed)
 541 {
 542         uint32_t val;
 543         int i;
 544         struct amdgpu_device *adev = psp->adev;
 545
 546         if (psp->adev->no_hw_access)
 547                 return 0;
 548
 549         for (i = 0; i < adev->usec_timeout; i++) {
 550                 val = RREG32(reg_index);
 551                 if (check_changed) {
 552                         if (val != reg_val)
 553                                 return 0;
 554                 } else {
 555                         if ((val & mask) == reg_val)
 556                                 return 0;
 557                 }
 558                 udelay(1);
 559         }
 560
 561         return -ETIME;
 562 }
 563
 564 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 565 {
 566         switch (cmd_id) {
 567         case GFX_CMD_ID_LOAD_TA:
 568                 return "LOAD_TA";
 569         case GFX_CMD_ID_UNLOAD_TA:
 570                 return "UNLOAD_TA";
 571         case GFX_CMD_ID_INVOKE_CMD:
 572                 return "INVOKE_CMD";
 573         case GFX_CMD_ID_LOAD_ASD:
 574                 return "LOAD_ASD";
 575         case GFX_CMD_ID_SETUP_TMR:
 576                 return "SETUP_TMR";
 577         case GFX_CMD_ID_LOAD_IP_FW:
 578                 return "LOAD_IP_FW";
 579         case GFX_CMD_ID_DESTROY_TMR:
 580                 return "DESTROY_TMR";
 581         case GFX_CMD_ID_SAVE_RESTORE:
 582                 return "SAVE_RESTORE_IP_FW";
 583         case GFX_CMD_ID_SETUP_VMR:
 584                 return "SETUP_VMR";
 585         case GFX_CMD_ID_DESTROY_VMR:
 586                 return "DESTROY_VMR";
 587         case GFX_CMD_ID_PROG_REG:
 588                 return "PROG_REG";
 589         case GFX_CMD_ID_GET_FW_ATTESTATION:
 590                 return "GET_FW_ATTESTATION";
 591         case GFX_CMD_ID_LOAD_TOC:
 592                 return "ID_LOAD_TOC";
 593         case GFX_CMD_ID_AUTOLOAD_RLC:
 594                 return "AUTOLOAD_RLC";
 595         case GFX_CMD_ID_BOOT_CFG:
 596                 return "BOOT_CFG";
 597         default:
 598                 return "UNKNOWN CMD";
 599         }
 600 }
 601
 602 static int
 603 psp_cmd_submit_buf(struct psp_context *psp,
 604                    struct amdgpu_firmware_info *ucode,
 605                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 606 {
 607         int ret;
 608         int index;
 609         int timeout = 20000;
 610         bool ras_intr = false;
 611         bool skip_unsupport = false;
 612
 613         if (psp->adev->no_hw_access)
 614                 return 0;
 615
 616         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 617
 618         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 619
 620         index = atomic_inc_return(&psp->fence_value);
 621         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 622         if (ret) {
 623                 atomic_dec(&psp->fence_value);
 624                 goto exit;
 625         }
 626
 627         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 628         while (*((unsigned int *)psp->fence_buf) != index) {
 629                 if (--timeout == 0)
 630                         break;
 631                 /*
 632                  * Shouldn't wait for timeout when err_event_athub occurs,
 633                  * because gpu reset thread triggered and lock resource should
 634                  * be released for psp resume sequence.
 635                  */
 636                 ras_intr = amdgpu_ras_intr_triggered();
 637                 if (ras_intr)
 638                         break;
 639                 usleep_range(10, 100);
 640                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 641         }
 642
 643         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 644         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 645                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 646
 647         memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 648
 649         /* In some cases, psp response status is not 0 even there is no
 650          * problem while the command is submitted. Some version of PSP FW
 651          * doesn't write 0 to that field.
 652          * So here we would like to only print a warning instead of an error
 653          * during psp initialization to avoid breaking hw_init and it doesn't
 654          * return -EINVAL.
 655          */
 656         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 657                 if (ucode)
 658                         DRM_WARN("failed to load ucode %s(0x%X) ",
 659                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 660                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 661                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 662                          psp->cmd_buf_mem->resp.status);
 663                 /* If any firmware (including CAP) load fails under SRIOV, it should
 664                  * return failure to stop the VF from initializing.
 665                  * Also return failure in case of timeout
 666                  */
 667                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 668                         ret = -EINVAL;
 669                         goto exit;
 670                 }
 671         }
 672
 673         if (ucode) {
 674                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 675                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 676         }
 677
 678 exit:
 679         return ret;
 680 }
 681
 682 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 683 {
 684         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 685
 686         mutex_lock(&psp->mutex);
 687
 688         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 689
 690         return cmd;
 691 }
 692
 693 static void release_psp_cmd_buf(struct psp_context *psp)
 694 {
 695         mutex_unlock(&psp->mutex);
 696 }
 697
 698 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 699                                  struct psp_gfx_cmd_resp *cmd,
 700                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 701 {
 702         struct amdgpu_device *adev = psp->adev;
 703         uint32_t size = amdgpu_bo_size(tmr_bo);
 704         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 705
 706         if (amdgpu_sriov_vf(psp->adev))
 707                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 708         else
 709                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 710         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 711         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 712         cmd->cmd.cmd_setup_tmr.buf_size = size;
 713         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 714         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 715         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 716 }
 717
 718 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 719                                       uint64_t pri_buf_mc, uint32_t size)
 720 {
 721         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 722         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 723         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 724         cmd->cmd.cmd_load_toc.toc_size = size;
 725 }
 726
 727 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 728 static int psp_load_toc(struct psp_context *psp,
 729                         uint32_t *tmr_size)
 730 {
 731         int ret;
 732         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 733
 734         /* Copy toc to psp firmware private buffer */
 735         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 736
 737         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 738
 739         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 740                                  psp->fence_buf_mc_addr);
 741         if (!ret)
 742                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 743
 744         release_psp_cmd_buf(psp);
 745
 746         return ret;
 747 }
 748
 749 /* Set up Trusted Memory Region */
 750 static int psp_tmr_init(struct psp_context *psp)
 751 {
 752         int ret = 0;
 753         int tmr_size;
 754         void *tmr_buf;
 755         void **pptr;
 756
 757         /*
 758          * According to HW engineer, they prefer the TMR address be "naturally
 759          * aligned" , e.g. the start address be an integer divide of TMR size.
 760          *
 761          * Note: this memory need be reserved till the driver
 762          * uninitializes.
 763          */
 764         tmr_size = PSP_TMR_SIZE(psp->adev);
 765
 766         /* For ASICs support RLC autoload, psp will parse the toc
 767          * and calculate the total size of TMR needed */
 768         if (!amdgpu_sriov_vf(psp->adev) &&
 769             psp->toc.start_addr &&
 770             psp->toc.size_bytes &&
 771             psp->fw_pri_buf) {
 772                 ret = psp_load_toc(psp, &tmr_size);
 773                 if (ret) {
 774                         DRM_ERROR("Failed to load toc\n");
 775                         return ret;
 776                 }
 777         }
 778
 779         if (!psp->tmr_bo) {
 780                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 781                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 782                                               PSP_TMR_ALIGNMENT,
 783                                               AMDGPU_HAS_VRAM(psp->adev) ?
 784                                               AMDGPU_GEM_DOMAIN_VRAM :
 785                                               AMDGPU_GEM_DOMAIN_GTT,
 786                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 787                                               pptr);
 788         }
 789
 790         return ret;
 791 }
 792
 793 static bool psp_skip_tmr(struct psp_context *psp)
 794 {
 795         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 796         case IP_VERSION(11, 0, 9):
 797         case IP_VERSION(11, 0, 7):
 798         case IP_VERSION(13, 0, 2):
 799         case IP_VERSION(13, 0, 10):
 800                 return true;
 801         default:
 802                 return false;
 803         }
 804 }
 805
 806 static int psp_tmr_load(struct psp_context *psp)
 807 {
 808         int ret;
 809         struct psp_gfx_cmd_resp *cmd;
 810
 811         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 812          * Already set up by host driver.
 813          */
 814         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 815                 return 0;
 816
 817         cmd = acquire_psp_cmd_buf(psp);
 818
 819         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 820         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 821                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 822
 823         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 824                                  psp->fence_buf_mc_addr);
 825
 826         release_psp_cmd_buf(psp);
 827
 828         return ret;
 829 }
 830
 831 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 832                                         struct psp_gfx_cmd_resp *cmd)
 833 {
 834         if (amdgpu_sriov_vf(psp->adev))
 835                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 836         else
 837                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 838 }
 839
 840 static int psp_tmr_unload(struct psp_context *psp)
 841 {
 842         int ret;
 843         struct psp_gfx_cmd_resp *cmd;
 844
 845         /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
 846          * as TMR is not loaded at all
 847          */
 848         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 849                 return 0;
 850
 851         cmd = acquire_psp_cmd_buf(psp);
 852
 853         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 854         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 855
 856         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 857                                  psp->fence_buf_mc_addr);
 858
 859         release_psp_cmd_buf(psp);
 860
 861         return ret;
 862 }
 863
 864 static int psp_tmr_terminate(struct psp_context *psp)
 865 {
 866         return psp_tmr_unload(psp);
 867 }
 868
 869 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 870                                         uint64_t *output_ptr)
 871 {
 872         int ret;
 873         struct psp_gfx_cmd_resp *cmd;
 874
 875         if (!output_ptr)
 876                 return -EINVAL;
 877
 878         if (amdgpu_sriov_vf(psp->adev))
 879                 return 0;
 880
 881         cmd = acquire_psp_cmd_buf(psp);
 882
 883         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 884
 885         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 886                                  psp->fence_buf_mc_addr);
 887
 888         if (!ret) {
 889                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 890                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 891         }
 892
 893         release_psp_cmd_buf(psp);
 894
 895         return ret;
 896 }
 897
 898 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 899 {
 900         struct psp_context *psp = &adev->psp;
 901         struct psp_gfx_cmd_resp *cmd;
 902         int ret;
 903
 904         if (amdgpu_sriov_vf(adev))
 905                 return 0;
 906
 907         cmd = acquire_psp_cmd_buf(psp);
 908
 909         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 910         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 911
 912         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 913         if (!ret) {
 914                 *boot_cfg =
 915                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 916         }
 917
 918         release_psp_cmd_buf(psp);
 919
 920         return ret;
 921 }
 922
 923 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 924 {
 925         int ret;
 926         struct psp_context *psp = &adev->psp;
 927         struct psp_gfx_cmd_resp *cmd;
 928
 929         if (amdgpu_sriov_vf(adev))
 930                 return 0;
 931
 932         cmd = acquire_psp_cmd_buf(psp);
 933
 934         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 935         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 936         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 937         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 938
 939         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 940
 941         release_psp_cmd_buf(psp);
 942
 943         return ret;
 944 }
 945
 946 static int psp_rl_load(struct amdgpu_device *adev)
 947 {
 948         int ret;
 949         struct psp_context *psp = &adev->psp;
 950         struct psp_gfx_cmd_resp *cmd;
 951
 952         if (!is_psp_fw_valid(psp->rl))
 953                 return 0;
 954
 955         cmd = acquire_psp_cmd_buf(psp);
 956
 957         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 958         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 959
 960         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 961         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 962         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 963         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 964         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 965
 966         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 967
 968         release_psp_cmd_buf(psp);
 969
 970         return ret;
 971 }
 972
 973 static int psp_asd_initialize(struct psp_context *psp)
 974 {
 975         int ret;
 976
 977         /* If PSP version doesn't match ASD version, asd loading will be failed.
 978          * add workaround to bypass it for sriov now.
 979          * TODO: add version check to make it common
 980          */
 981         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
 982                 return 0;
 983
 984         psp->asd_context.mem_context.shared_mc_addr  = 0;
 985         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
 986         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
 987
 988         ret = psp_ta_load(psp, &psp->asd_context);
 989         if (!ret)
 990                 psp->asd_context.initialized = true;
 991
 992         return ret;
 993 }
 994
 995 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 996                                        uint32_t session_id)
 997 {
 998         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 999         cmd->cmd.cmd_unload_ta.session_id = session_id;
1000 }
1001
1002 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1003 {
1004         int ret;
1005         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1006
1007         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1008
1009         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1010
1011         context->resp_status = cmd->resp.status;
1012
1013         release_psp_cmd_buf(psp);
1014
1015         return ret;
1016 }
1017
1018 static int psp_asd_terminate(struct psp_context *psp)
1019 {
1020         int ret;
1021
1022         if (amdgpu_sriov_vf(psp->adev))
1023                 return 0;
1024
1025         if (!psp->asd_context.initialized)
1026                 return 0;
1027
1028         ret = psp_ta_unload(psp, &psp->asd_context);
1029         if (!ret)
1030                 psp->asd_context.initialized = false;
1031
1032         return ret;
1033 }
1034
1035 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1036                 uint32_t id, uint32_t value)
1037 {
1038         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1039         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1040         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1041 }
1042
1043 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1044                 uint32_t value)
1045 {
1046         struct psp_gfx_cmd_resp *cmd;
1047         int ret = 0;
1048
1049         if (reg >= PSP_REG_LAST)
1050                 return -EINVAL;
1051
1052         cmd = acquire_psp_cmd_buf(psp);
1053
1054         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1055         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1056         if (ret)
1057                 DRM_ERROR("PSP failed to program reg id %d", reg);
1058
1059         release_psp_cmd_buf(psp);
1060
1061         return ret;
1062 }
1063
1064 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1065                                      uint64_t ta_bin_mc,
1066                                      struct ta_context *context)
1067 {
1068         cmd->cmd_id                             = context->ta_load_type;
1069         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1070         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1071         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1072
1073         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1074                 lower_32_bits(context->mem_context.shared_mc_addr);
1075         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1076                 upper_32_bits(context->mem_context.shared_mc_addr);
1077         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1078 }
1079
1080 int psp_ta_init_shared_buf(struct psp_context *psp,
1081                                   struct ta_mem_context *mem_ctx)
1082 {
1083         /*
1084         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1085         * physical) for ta to host memory
1086         */
1087         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1088                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1089                                       AMDGPU_GEM_DOMAIN_GTT,
1090                                       &mem_ctx->shared_bo,
1091                                       &mem_ctx->shared_mc_addr,
1092                                       &mem_ctx->shared_buf);
1093 }
1094
1095 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1096                                        uint32_t ta_cmd_id,
1097                                        uint32_t session_id)
1098 {
1099         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1100         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1101         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1102 }
1103
1104 int psp_ta_invoke(struct psp_context *psp,
1105                   uint32_t ta_cmd_id,
1106                   struct ta_context *context)
1107 {
1108         int ret;
1109         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1110
1111         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1112
1113         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1114                                  psp->fence_buf_mc_addr);
1115
1116         context->resp_status = cmd->resp.status;
1117
1118         release_psp_cmd_buf(psp);
1119
1120         return ret;
1121 }
1122
1123 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1124 {
1125         int ret;
1126         struct psp_gfx_cmd_resp *cmd;
1127
1128         cmd = acquire_psp_cmd_buf(psp);
1129
1130         psp_copy_fw(psp, context->bin_desc.start_addr,
1131                     context->bin_desc.size_bytes);
1132
1133         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1134
1135         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1136                                  psp->fence_buf_mc_addr);
1137
1138         context->resp_status = cmd->resp.status;
1139
1140         if (!ret)
1141                 context->session_id = cmd->resp.session_id;
1142
1143         release_psp_cmd_buf(psp);
1144
1145         return ret;
1146 }
1147
1148 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1149 {
1150         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1151 }
1152
1153 int psp_xgmi_terminate(struct psp_context *psp)
1154 {
1155         int ret;
1156         struct amdgpu_device *adev = psp->adev;
1157
1158         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1159         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1160             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1161              adev->gmc.xgmi.connected_to_cpu))
1162                 return 0;
1163
1164         if (!psp->xgmi_context.context.initialized)
1165                 return 0;
1166
1167         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1168
1169         psp->xgmi_context.context.initialized = false;
1170
1171         return ret;
1172 }
1173
1174 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1175 {
1176         struct ta_xgmi_shared_memory *xgmi_cmd;
1177         int ret;
1178
1179         if (!psp->ta_fw ||
1180             !psp->xgmi_context.context.bin_desc.size_bytes ||
1181             !psp->xgmi_context.context.bin_desc.start_addr)
1182                 return -ENOENT;
1183
1184         if (!load_ta)
1185                 goto invoke;
1186
1187         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1188         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1189
1190         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1191                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1192                 if (ret)
1193                         return ret;
1194         }
1195
1196         /* Load XGMI TA */
1197         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1198         if (!ret)
1199                 psp->xgmi_context.context.initialized = true;
1200         else
1201                 return ret;
1202
1203 invoke:
1204         /* Initialize XGMI session */
1205         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1206         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1207         xgmi_cmd->flag_extend_link_record = set_extended_data;
1208         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1209
1210         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1211
1212         return ret;
1213 }
1214
1215 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1216 {
1217         struct ta_xgmi_shared_memory *xgmi_cmd;
1218         int ret;
1219
1220         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1221         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1222
1223         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1224
1225         /* Invoke xgmi ta to get hive id */
1226         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1227         if (ret)
1228                 return ret;
1229
1230         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1231
1232         return 0;
1233 }
1234
1235 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1236 {
1237         struct ta_xgmi_shared_memory *xgmi_cmd;
1238         int ret;
1239
1240         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1241         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1242
1243         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1244
1245         /* Invoke xgmi ta to get the node id */
1246         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1247         if (ret)
1248                 return ret;
1249
1250         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1251
1252         return 0;
1253 }
1254
1255 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1256 {
1257         return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1258                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1259                 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6);
1260 }
1261
1262 /*
1263  * Chips that support extended topology information require the driver to
1264  * reflect topology information in the opposite direction.  This is
1265  * because the TA has already exceeded its link record limit and if the
1266  * TA holds bi-directional information, the driver would have to do
1267  * multiple fetches instead of just two.
1268  */
1269 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1270                                         struct psp_xgmi_node_info node_info)
1271 {
1272         struct amdgpu_device *mirror_adev;
1273         struct amdgpu_hive_info *hive;
1274         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1275         uint64_t dst_node_id = node_info.node_id;
1276         uint8_t dst_num_hops = node_info.num_hops;
1277         uint8_t dst_num_links = node_info.num_links;
1278
1279         hive = amdgpu_get_xgmi_hive(psp->adev);
1280         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1281                 struct psp_xgmi_topology_info *mirror_top_info;
1282                 int j;
1283
1284                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1285                         continue;
1286
1287                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1288                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1289                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1290                                 continue;
1291
1292                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1293                         /*
1294                          * prevent 0 num_links value re-reflection since reflection
1295                          * criteria is based on num_hops (direct or indirect).
1296                          *
1297                          */
1298                         if (dst_num_links)
1299                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1300
1301                         break;
1302                 }
1303
1304                 break;
1305         }
1306
1307         amdgpu_put_xgmi_hive(hive);
1308 }
1309
1310 int psp_xgmi_get_topology_info(struct psp_context *psp,
1311                                int number_devices,
1312                                struct psp_xgmi_topology_info *topology,
1313                                bool get_extended_data)
1314 {
1315         struct ta_xgmi_shared_memory *xgmi_cmd;
1316         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1317         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1318         int i;
1319         int ret;
1320
1321         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1322                 return -EINVAL;
1323
1324         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1325         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1326         xgmi_cmd->flag_extend_link_record = get_extended_data;
1327
1328         /* Fill in the shared memory with topology information as input */
1329         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1330         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1331         topology_info_input->num_nodes = number_devices;
1332
1333         for (i = 0; i < topology_info_input->num_nodes; i++) {
1334                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1335                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1336                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1337                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1338         }
1339
1340         /* Invoke xgmi ta to get the topology information */
1341         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1342         if (ret)
1343                 return ret;
1344
1345         /* Read the output topology information from the shared memory */
1346         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1347         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1348         for (i = 0; i < topology->num_nodes; i++) {
1349                 /* extended data will either be 0 or equal to non-extended data */
1350                 if (topology_info_output->nodes[i].num_hops)
1351                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1352
1353                 /* non-extended data gets everything here so no need to update */
1354                 if (!get_extended_data) {
1355                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1356                         topology->nodes[i].is_sharing_enabled =
1357                                         topology_info_output->nodes[i].is_sharing_enabled;
1358                         topology->nodes[i].sdma_engine =
1359                                         topology_info_output->nodes[i].sdma_engine;
1360                 }
1361
1362         }
1363
1364         /* Invoke xgmi ta again to get the link information */
1365         if (psp_xgmi_peer_link_info_supported(psp)) {
1366                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1367                 bool requires_reflection =
1368                         (psp->xgmi_context.supports_extended_data && get_extended_data) ||
1369                                 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6);
1370
1371                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1372
1373                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1374
1375                 if (ret)
1376                         return ret;
1377
1378                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1379                 for (i = 0; i < topology->num_nodes; i++) {
1380                         /* accumulate num_links on extended data */
1381                         topology->nodes[i].num_links = get_extended_data ?
1382                                         topology->nodes[i].num_links +
1383                                                         link_info_output->nodes[i].num_links :
1384                                         link_info_output->nodes[i].num_links;
1385
1386                         /* reflect the topology information for bi-directionality */
1387                         if (requires_reflection && topology->nodes[i].num_hops)
1388                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1389                 }
1390         }
1391
1392         return 0;
1393 }
1394
1395 int psp_xgmi_set_topology_info(struct psp_context *psp,
1396                                int number_devices,
1397                                struct psp_xgmi_topology_info *topology)
1398 {
1399         struct ta_xgmi_shared_memory *xgmi_cmd;
1400         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1401         int i;
1402
1403         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1404                 return -EINVAL;
1405
1406         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1407         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1408
1409         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1410         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1411         topology_info_input->num_nodes = number_devices;
1412
1413         for (i = 0; i < topology_info_input->num_nodes; i++) {
1414                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1415                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1416                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1417                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1418         }
1419
1420         /* Invoke xgmi ta to set topology information */
1421         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1422 }
1423
1424 // ras begin
1425 static void psp_ras_ta_check_status(struct psp_context *psp)
1426 {
1427         struct ta_ras_shared_memory *ras_cmd =
1428                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1429
1430         switch (ras_cmd->ras_status) {
1431         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1432                 dev_warn(psp->adev->dev,
1433                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1434                 break;
1435         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1436                 dev_warn(psp->adev->dev,
1437                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1438                 break;
1439         case TA_RAS_STATUS__SUCCESS:
1440                 break;
1441         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1442                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1443                         dev_warn(psp->adev->dev,
1444                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1445                 break;
1446         default:
1447                 dev_warn(psp->adev->dev,
1448                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1449                 break;
1450         }
1451 }
1452
1453 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1454 {
1455         struct ta_ras_shared_memory *ras_cmd;
1456         int ret;
1457
1458         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1459
1460         /*
1461          * TODO: bypass the loading in sriov for now
1462          */
1463         if (amdgpu_sriov_vf(psp->adev))
1464                 return 0;
1465
1466         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1467
1468         if (amdgpu_ras_intr_triggered())
1469                 return ret;
1470
1471         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1472                 DRM_WARN("RAS: Unsupported Interface");
1473                 return -EINVAL;
1474         }
1475
1476         if (!ret) {
1477                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1478                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1479
1480                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1481                 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1482                         dev_warn(psp->adev->dev,
1483                                  "RAS internal register access blocked\n");
1484
1485                 psp_ras_ta_check_status(psp);
1486         }
1487
1488         return ret;
1489 }
1490
1491 int psp_ras_enable_features(struct psp_context *psp,
1492                 union ta_ras_cmd_input *info, bool enable)
1493 {
1494         struct ta_ras_shared_memory *ras_cmd;
1495         int ret;
1496
1497         if (!psp->ras_context.context.initialized)
1498                 return -EINVAL;
1499
1500         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1501         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1502
1503         if (enable)
1504                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1505         else
1506                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1507
1508         ras_cmd->ras_in_message = *info;
1509
1510         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1511         if (ret)
1512                 return -EINVAL;
1513
1514         return 0;
1515 }
1516
1517 int psp_ras_terminate(struct psp_context *psp)
1518 {
1519         int ret;
1520
1521         /*
1522          * TODO: bypass the terminate in sriov for now
1523          */
1524         if (amdgpu_sriov_vf(psp->adev))
1525                 return 0;
1526
1527         if (!psp->ras_context.context.initialized)
1528                 return 0;
1529
1530         ret = psp_ta_unload(psp, &psp->ras_context.context);
1531
1532         psp->ras_context.context.initialized = false;
1533
1534         return ret;
1535 }
1536
1537 int psp_ras_initialize(struct psp_context *psp)
1538 {
1539         int ret;
1540         uint32_t boot_cfg = 0xFF;
1541         struct amdgpu_device *adev = psp->adev;
1542         struct ta_ras_shared_memory *ras_cmd;
1543
1544         /*
1545          * TODO: bypass the initialize in sriov for now
1546          */
1547         if (amdgpu_sriov_vf(adev))
1548                 return 0;
1549
1550         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1551             !adev->psp.ras_context.context.bin_desc.start_addr) {
1552                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1553                 return 0;
1554         }
1555
1556         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1557                 /* query GECC enablement status from boot config
1558                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1559                  */
1560                 ret = psp_boot_config_get(adev, &boot_cfg);
1561                 if (ret)
1562                         dev_warn(adev->dev, "PSP get boot config failed\n");
1563
1564                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1565                         if (!boot_cfg) {
1566                                 dev_info(adev->dev, "GECC is disabled\n");
1567                         } else {
1568                                 /* disable GECC in next boot cycle if ras is
1569                                  * disabled by module parameter amdgpu_ras_enable
1570                                  * and/or amdgpu_ras_mask, or boot_config_get call
1571                                  * is failed
1572                                  */
1573                                 ret = psp_boot_config_set(adev, 0);
1574                                 if (ret)
1575                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1576                                 else
1577                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1578                         }
1579                 } else {
1580                         if (boot_cfg == 1) {
1581                                 dev_info(adev->dev, "GECC is enabled\n");
1582                         } else {
1583                                 /* enable GECC in next boot cycle if it is disabled
1584                                  * in boot config, or force enable GECC if failed to
1585                                  * get boot configuration
1586                                  */
1587                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1588                                 if (ret)
1589                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1590                                 else
1591                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1592                         }
1593                 }
1594         }
1595
1596         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1597         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1598
1599         if (!psp->ras_context.context.mem_context.shared_buf) {
1600                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1601                 if (ret)
1602                         return ret;
1603         }
1604
1605         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1606         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1607
1608         if (amdgpu_ras_is_poison_mode_supported(adev))
1609                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1610         if (!adev->gmc.xgmi.connected_to_cpu)
1611                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1612
1613         ret = psp_ta_load(psp, &psp->ras_context.context);
1614
1615         if (!ret && !ras_cmd->ras_status)
1616                 psp->ras_context.context.initialized = true;
1617         else {
1618                 if (ras_cmd->ras_status)
1619                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1620
1621                 /* fail to load RAS TA */
1622                 psp->ras_context.context.initialized = false;
1623         }
1624
1625         return ret;
1626 }
1627
1628 int psp_ras_trigger_error(struct psp_context *psp,
1629                           struct ta_ras_trigger_error_input *info)
1630 {
1631         struct ta_ras_shared_memory *ras_cmd;
1632         int ret;
1633
1634         if (!psp->ras_context.context.initialized)
1635                 return -EINVAL;
1636
1637         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1638         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1639
1640         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1641         ras_cmd->ras_in_message.trigger_error = *info;
1642
1643         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1644         if (ret)
1645                 return -EINVAL;
1646
1647         /* If err_event_athub occurs error inject was successful, however
1648            return status from TA is no long reliable */
1649         if (amdgpu_ras_intr_triggered())
1650                 return 0;
1651
1652         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1653                 return -EACCES;
1654         else if (ras_cmd->ras_status)
1655                 return -EINVAL;
1656
1657         return 0;
1658 }
1659 // ras end
1660
1661 // HDCP start
1662 static int psp_hdcp_initialize(struct psp_context *psp)
1663 {
1664         int ret;
1665
1666         /*
1667          * TODO: bypass the initialize in sriov for now
1668          */
1669         if (amdgpu_sriov_vf(psp->adev))
1670                 return 0;
1671
1672         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1673             !psp->hdcp_context.context.bin_desc.start_addr) {
1674                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1675                 return 0;
1676         }
1677
1678         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1679         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1680
1681         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1682                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1683                 if (ret)
1684                         return ret;
1685         }
1686
1687         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1688         if (!ret) {
1689                 psp->hdcp_context.context.initialized = true;
1690                 mutex_init(&psp->hdcp_context.mutex);
1691         }
1692
1693         return ret;
1694 }
1695
1696 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1697 {
1698         /*
1699          * TODO: bypass the loading in sriov for now
1700          */
1701         if (amdgpu_sriov_vf(psp->adev))
1702                 return 0;
1703
1704         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1705 }
1706
1707 static int psp_hdcp_terminate(struct psp_context *psp)
1708 {
1709         int ret;
1710
1711         /*
1712          * TODO: bypass the terminate in sriov for now
1713          */
1714         if (amdgpu_sriov_vf(psp->adev))
1715                 return 0;
1716
1717         if (!psp->hdcp_context.context.initialized)
1718                 return 0;
1719
1720         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1721
1722         psp->hdcp_context.context.initialized = false;
1723
1724         return ret;
1725 }
1726 // HDCP end
1727
1728 // DTM start
1729 static int psp_dtm_initialize(struct psp_context *psp)
1730 {
1731         int ret;
1732
1733         /*
1734          * TODO: bypass the initialize in sriov for now
1735          */
1736         if (amdgpu_sriov_vf(psp->adev))
1737                 return 0;
1738
1739         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1740             !psp->dtm_context.context.bin_desc.start_addr) {
1741                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1742                 return 0;
1743         }
1744
1745         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1746         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1747
1748         if (!psp->dtm_context.context.mem_context.shared_buf) {
1749                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1750                 if (ret)
1751                         return ret;
1752         }
1753
1754         ret = psp_ta_load(psp, &psp->dtm_context.context);
1755         if (!ret) {
1756                 psp->dtm_context.context.initialized = true;
1757                 mutex_init(&psp->dtm_context.mutex);
1758         }
1759
1760         return ret;
1761 }
1762
1763 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1764 {
1765         /*
1766          * TODO: bypass the loading in sriov for now
1767          */
1768         if (amdgpu_sriov_vf(psp->adev))
1769                 return 0;
1770
1771         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1772 }
1773
1774 static int psp_dtm_terminate(struct psp_context *psp)
1775 {
1776         int ret;
1777
1778         /*
1779          * TODO: bypass the terminate in sriov for now
1780          */
1781         if (amdgpu_sriov_vf(psp->adev))
1782                 return 0;
1783
1784         if (!psp->dtm_context.context.initialized)
1785                 return 0;
1786
1787         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1788
1789         psp->dtm_context.context.initialized = false;
1790
1791         return ret;
1792 }
1793 // DTM end
1794
1795 // RAP start
1796 static int psp_rap_initialize(struct psp_context *psp)
1797 {
1798         int ret;
1799         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1800
1801         /*
1802          * TODO: bypass the initialize in sriov for now
1803          */
1804         if (amdgpu_sriov_vf(psp->adev))
1805                 return 0;
1806
1807         if (!psp->rap_context.context.bin_desc.size_bytes ||
1808             !psp->rap_context.context.bin_desc.start_addr) {
1809                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1810                 return 0;
1811         }
1812
1813         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1814         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1815
1816         if (!psp->rap_context.context.mem_context.shared_buf) {
1817                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1818                 if (ret)
1819                         return ret;
1820         }
1821
1822         ret = psp_ta_load(psp, &psp->rap_context.context);
1823         if (!ret) {
1824                 psp->rap_context.context.initialized = true;
1825                 mutex_init(&psp->rap_context.mutex);
1826         } else
1827                 return ret;
1828
1829         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1830         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1831                 psp_rap_terminate(psp);
1832                 /* free rap shared memory */
1833                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1834
1835                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1836                          ret, status);
1837
1838                 return ret;
1839         }
1840
1841         return 0;
1842 }
1843
1844 static int psp_rap_terminate(struct psp_context *psp)
1845 {
1846         int ret;
1847
1848         if (!psp->rap_context.context.initialized)
1849                 return 0;
1850
1851         ret = psp_ta_unload(psp, &psp->rap_context.context);
1852
1853         psp->rap_context.context.initialized = false;
1854
1855         return ret;
1856 }
1857
1858 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1859 {
1860         struct ta_rap_shared_memory *rap_cmd;
1861         int ret = 0;
1862
1863         if (!psp->rap_context.context.initialized)
1864                 return 0;
1865
1866         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1867             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1868                 return -EINVAL;
1869
1870         mutex_lock(&psp->rap_context.mutex);
1871
1872         rap_cmd = (struct ta_rap_shared_memory *)
1873                   psp->rap_context.context.mem_context.shared_buf;
1874         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1875
1876         rap_cmd->cmd_id = ta_cmd_id;
1877         rap_cmd->validation_method_id = METHOD_A;
1878
1879         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1880         if (ret)
1881                 goto out_unlock;
1882
1883         if (status)
1884                 *status = rap_cmd->rap_status;
1885
1886 out_unlock:
1887         mutex_unlock(&psp->rap_context.mutex);
1888
1889         return ret;
1890 }
1891 // RAP end
1892
1893 /* securedisplay start */
1894 static int psp_securedisplay_initialize(struct psp_context *psp)
1895 {
1896         int ret;
1897         struct ta_securedisplay_cmd *securedisplay_cmd;
1898
1899         /*
1900          * TODO: bypass the initialize in sriov for now
1901          */
1902         if (amdgpu_sriov_vf(psp->adev))
1903                 return 0;
1904
1905         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1906             !psp->securedisplay_context.context.bin_desc.start_addr) {
1907                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1908                 return 0;
1909         }
1910
1911         psp->securedisplay_context.context.mem_context.shared_mem_size =
1912                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1913         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1914
1915         if (!psp->securedisplay_context.context.initialized) {
1916                 ret = psp_ta_init_shared_buf(psp,
1917                                              &psp->securedisplay_context.context.mem_context);
1918                 if (ret)
1919                         return ret;
1920         }
1921
1922         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1923         if (!ret) {
1924                 psp->securedisplay_context.context.initialized = true;
1925                 mutex_init(&psp->securedisplay_context.mutex);
1926         } else
1927                 return ret;
1928
1929         mutex_lock(&psp->securedisplay_context.mutex);
1930
1931         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1932                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1933
1934         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1935
1936         mutex_unlock(&psp->securedisplay_context.mutex);
1937
1938         if (ret) {
1939                 psp_securedisplay_terminate(psp);
1940                 /* free securedisplay shared memory */
1941                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1942                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1943                 return -EINVAL;
1944         }
1945
1946         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1947                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1948                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1949                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1950         }
1951
1952         return 0;
1953 }
1954
1955 static int psp_securedisplay_terminate(struct psp_context *psp)
1956 {
1957         int ret;
1958
1959         /*
1960          * TODO:bypass the terminate in sriov for now
1961          */
1962         if (amdgpu_sriov_vf(psp->adev))
1963                 return 0;
1964
1965         if (!psp->securedisplay_context.context.initialized)
1966                 return 0;
1967
1968         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1969
1970         psp->securedisplay_context.context.initialized = false;
1971
1972         return ret;
1973 }
1974
1975 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1976 {
1977         int ret;
1978
1979         if (!psp->securedisplay_context.context.initialized)
1980                 return -EINVAL;
1981
1982         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1983             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1984                 return -EINVAL;
1985
1986         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1987
1988         return ret;
1989 }
1990 /* SECUREDISPLAY end */
1991
1992 static int psp_hw_start(struct psp_context *psp)
1993 {
1994         struct amdgpu_device *adev = psp->adev;
1995         int ret;
1996
1997         if (!amdgpu_sriov_vf(adev)) {
1998                 if ((is_psp_fw_valid(psp->kdb)) &&
1999                     (psp->funcs->bootloader_load_kdb != NULL)) {
2000                         ret = psp_bootloader_load_kdb(psp);
2001                         if (ret) {
2002                                 DRM_ERROR("PSP load kdb failed!\n");
2003                                 return ret;
2004                         }
2005                 }
2006
2007                 if ((is_psp_fw_valid(psp->spl)) &&
2008                     (psp->funcs->bootloader_load_spl != NULL)) {
2009                         ret = psp_bootloader_load_spl(psp);
2010                         if (ret) {
2011                                 DRM_ERROR("PSP load spl failed!\n");
2012                                 return ret;
2013                         }
2014                 }
2015
2016                 if ((is_psp_fw_valid(psp->sys)) &&
2017                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2018                         ret = psp_bootloader_load_sysdrv(psp);
2019                         if (ret) {
2020                                 DRM_ERROR("PSP load sys drv failed!\n");
2021                                 return ret;
2022                         }
2023                 }
2024
2025                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2026                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2027                         ret = psp_bootloader_load_soc_drv(psp);
2028                         if (ret) {
2029                                 DRM_ERROR("PSP load soc drv failed!\n");
2030                                 return ret;
2031                         }
2032                 }
2033
2034                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2035                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2036                         ret = psp_bootloader_load_intf_drv(psp);
2037                         if (ret) {
2038                                 DRM_ERROR("PSP load intf drv failed!\n");
2039                                 return ret;
2040                         }
2041                 }
2042
2043                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2044                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2045                         ret = psp_bootloader_load_dbg_drv(psp);
2046                         if (ret) {
2047                                 DRM_ERROR("PSP load dbg drv failed!\n");
2048                                 return ret;
2049                         }
2050                 }
2051
2052                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2053                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2054                         ret = psp_bootloader_load_ras_drv(psp);
2055                         if (ret) {
2056                                 DRM_ERROR("PSP load ras_drv failed!\n");
2057                                 return ret;
2058                         }
2059                 }
2060
2061                 if ((is_psp_fw_valid(psp->sos)) &&
2062                     (psp->funcs->bootloader_load_sos != NULL)) {
2063                         ret = psp_bootloader_load_sos(psp);
2064                         if (ret) {
2065                                 DRM_ERROR("PSP load sos failed!\n");
2066                                 return ret;
2067                         }
2068                 }
2069         }
2070
2071         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2072         if (ret) {
2073                 DRM_ERROR("PSP create ring failed!\n");
2074                 return ret;
2075         }
2076
2077         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2078                 goto skip_pin_bo;
2079
2080         ret = psp_tmr_init(psp);
2081         if (ret) {
2082                 DRM_ERROR("PSP tmr init failed!\n");
2083                 return ret;
2084         }
2085
2086 skip_pin_bo:
2087         /*
2088          * For ASICs with DF Cstate management centralized
2089          * to PMFW, TMR setup should be performed after PMFW
2090          * loaded and before other non-psp firmware loaded.
2091          */
2092         if (psp->pmfw_centralized_cstate_management) {
2093                 ret = psp_load_smu_fw(psp);
2094                 if (ret)
2095                         return ret;
2096         }
2097
2098         ret = psp_tmr_load(psp);
2099         if (ret) {
2100                 DRM_ERROR("PSP load tmr failed!\n");
2101                 return ret;
2102         }
2103
2104         return 0;
2105 }
2106
2107 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2108                            enum psp_gfx_fw_type *type)
2109 {
2110         switch (ucode->ucode_id) {
2111         case AMDGPU_UCODE_ID_CAP:
2112                 *type = GFX_FW_TYPE_CAP;
2113                 break;
2114         case AMDGPU_UCODE_ID_SDMA0:
2115                 *type = GFX_FW_TYPE_SDMA0;
2116                 break;
2117         case AMDGPU_UCODE_ID_SDMA1:
2118                 *type = GFX_FW_TYPE_SDMA1;
2119                 break;
2120         case AMDGPU_UCODE_ID_SDMA2:
2121                 *type = GFX_FW_TYPE_SDMA2;
2122                 break;
2123         case AMDGPU_UCODE_ID_SDMA3:
2124                 *type = GFX_FW_TYPE_SDMA3;
2125                 break;
2126         case AMDGPU_UCODE_ID_SDMA4:
2127                 *type = GFX_FW_TYPE_SDMA4;
2128                 break;
2129         case AMDGPU_UCODE_ID_SDMA5:
2130                 *type = GFX_FW_TYPE_SDMA5;
2131                 break;
2132         case AMDGPU_UCODE_ID_SDMA6:
2133                 *type = GFX_FW_TYPE_SDMA6;
2134                 break;
2135         case AMDGPU_UCODE_ID_SDMA7:
2136                 *type = GFX_FW_TYPE_SDMA7;
2137                 break;
2138         case AMDGPU_UCODE_ID_CP_MES:
2139                 *type = GFX_FW_TYPE_CP_MES;
2140                 break;
2141         case AMDGPU_UCODE_ID_CP_MES_DATA:
2142                 *type = GFX_FW_TYPE_MES_STACK;
2143                 break;
2144         case AMDGPU_UCODE_ID_CP_MES1:
2145                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2146                 break;
2147         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2148                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2149                 break;
2150         case AMDGPU_UCODE_ID_CP_CE:
2151                 *type = GFX_FW_TYPE_CP_CE;
2152                 break;
2153         case AMDGPU_UCODE_ID_CP_PFP:
2154                 *type = GFX_FW_TYPE_CP_PFP;
2155                 break;
2156         case AMDGPU_UCODE_ID_CP_ME:
2157                 *type = GFX_FW_TYPE_CP_ME;
2158                 break;
2159         case AMDGPU_UCODE_ID_CP_MEC1:
2160                 *type = GFX_FW_TYPE_CP_MEC;
2161                 break;
2162         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2163                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2164                 break;
2165         case AMDGPU_UCODE_ID_CP_MEC2:
2166                 *type = GFX_FW_TYPE_CP_MEC;
2167                 break;
2168         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2169                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2170                 break;
2171         case AMDGPU_UCODE_ID_RLC_P:
2172                 *type = GFX_FW_TYPE_RLC_P;
2173                 break;
2174         case AMDGPU_UCODE_ID_RLC_V:
2175                 *type = GFX_FW_TYPE_RLC_V;
2176                 break;
2177         case AMDGPU_UCODE_ID_RLC_G:
2178                 *type = GFX_FW_TYPE_RLC_G;
2179                 break;
2180         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2181                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2182                 break;
2183         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2184                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2185                 break;
2186         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2187                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2188                 break;
2189         case AMDGPU_UCODE_ID_RLC_IRAM:
2190                 *type = GFX_FW_TYPE_RLC_IRAM;
2191                 break;
2192         case AMDGPU_UCODE_ID_RLC_DRAM:
2193                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2194                 break;
2195         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2196                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2197                 break;
2198         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2199                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2200                 break;
2201         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2202                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2203                 break;
2204         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2205                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2206                 break;
2207         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2208                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2209                 break;
2210         case AMDGPU_UCODE_ID_SMC:
2211                 *type = GFX_FW_TYPE_SMU;
2212                 break;
2213         case AMDGPU_UCODE_ID_PPTABLE:
2214                 *type = GFX_FW_TYPE_PPTABLE;
2215                 break;
2216         case AMDGPU_UCODE_ID_UVD:
2217                 *type = GFX_FW_TYPE_UVD;
2218                 break;
2219         case AMDGPU_UCODE_ID_UVD1:
2220                 *type = GFX_FW_TYPE_UVD1;
2221                 break;
2222         case AMDGPU_UCODE_ID_VCE:
2223                 *type = GFX_FW_TYPE_VCE;
2224                 break;
2225         case AMDGPU_UCODE_ID_VCN:
2226                 *type = GFX_FW_TYPE_VCN;
2227                 break;
2228         case AMDGPU_UCODE_ID_VCN1:
2229                 *type = GFX_FW_TYPE_VCN1;
2230                 break;
2231         case AMDGPU_UCODE_ID_DMCU_ERAM:
2232                 *type = GFX_FW_TYPE_DMCU_ERAM;
2233                 break;
2234         case AMDGPU_UCODE_ID_DMCU_INTV:
2235                 *type = GFX_FW_TYPE_DMCU_ISR;
2236                 break;
2237         case AMDGPU_UCODE_ID_VCN0_RAM:
2238                 *type = GFX_FW_TYPE_VCN0_RAM;
2239                 break;
2240         case AMDGPU_UCODE_ID_VCN1_RAM:
2241                 *type = GFX_FW_TYPE_VCN1_RAM;
2242                 break;
2243         case AMDGPU_UCODE_ID_DMCUB:
2244                 *type = GFX_FW_TYPE_DMUB;
2245                 break;
2246         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2247                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2248                 break;
2249         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2250                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2251                 break;
2252         case AMDGPU_UCODE_ID_IMU_I:
2253                 *type = GFX_FW_TYPE_IMU_I;
2254                 break;
2255         case AMDGPU_UCODE_ID_IMU_D:
2256                 *type = GFX_FW_TYPE_IMU_D;
2257                 break;
2258         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2259                 *type = GFX_FW_TYPE_RS64_PFP;
2260                 break;
2261         case AMDGPU_UCODE_ID_CP_RS64_ME:
2262                 *type = GFX_FW_TYPE_RS64_ME;
2263                 break;
2264         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2265                 *type = GFX_FW_TYPE_RS64_MEC;
2266                 break;
2267         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2268                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2269                 break;
2270         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2271                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2272                 break;
2273         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2274                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2275                 break;
2276         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2277                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2278                 break;
2279         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2280                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2281                 break;
2282         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2283                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2284                 break;
2285         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2286                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2287                 break;
2288         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2289                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2290                 break;
2291         case AMDGPU_UCODE_ID_MAXIMUM:
2292         default:
2293                 return -EINVAL;
2294         }
2295
2296         return 0;
2297 }
2298
2299 static void psp_print_fw_hdr(struct psp_context *psp,
2300                              struct amdgpu_firmware_info *ucode)
2301 {
2302         struct amdgpu_device *adev = psp->adev;
2303         struct common_firmware_header *hdr;
2304
2305         switch (ucode->ucode_id) {
2306         case AMDGPU_UCODE_ID_SDMA0:
2307         case AMDGPU_UCODE_ID_SDMA1:
2308         case AMDGPU_UCODE_ID_SDMA2:
2309         case AMDGPU_UCODE_ID_SDMA3:
2310         case AMDGPU_UCODE_ID_SDMA4:
2311         case AMDGPU_UCODE_ID_SDMA5:
2312         case AMDGPU_UCODE_ID_SDMA6:
2313         case AMDGPU_UCODE_ID_SDMA7:
2314                 hdr = (struct common_firmware_header *)
2315                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2316                 amdgpu_ucode_print_sdma_hdr(hdr);
2317                 break;
2318         case AMDGPU_UCODE_ID_CP_CE:
2319                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2320                 amdgpu_ucode_print_gfx_hdr(hdr);
2321                 break;
2322         case AMDGPU_UCODE_ID_CP_PFP:
2323                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2324                 amdgpu_ucode_print_gfx_hdr(hdr);
2325                 break;
2326         case AMDGPU_UCODE_ID_CP_ME:
2327                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2328                 amdgpu_ucode_print_gfx_hdr(hdr);
2329                 break;
2330         case AMDGPU_UCODE_ID_CP_MEC1:
2331                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2332                 amdgpu_ucode_print_gfx_hdr(hdr);
2333                 break;
2334         case AMDGPU_UCODE_ID_RLC_G:
2335                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2336                 amdgpu_ucode_print_rlc_hdr(hdr);
2337                 break;
2338         case AMDGPU_UCODE_ID_SMC:
2339                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2340                 amdgpu_ucode_print_smc_hdr(hdr);
2341                 break;
2342         default:
2343                 break;
2344         }
2345 }
2346
2347 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2348                                        struct psp_gfx_cmd_resp *cmd)
2349 {
2350         int ret;
2351         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2352
2353         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2354         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2355         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2356         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2357
2358         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2359         if (ret)
2360                 DRM_ERROR("Unknown firmware type\n");
2361
2362         return ret;
2363 }
2364
2365 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2366                                   struct amdgpu_firmware_info *ucode)
2367 {
2368         int ret = 0;
2369         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2370
2371         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2372         if (!ret) {
2373                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2374                                          psp->fence_buf_mc_addr);
2375         }
2376
2377         release_psp_cmd_buf(psp);
2378
2379         return ret;
2380 }
2381
2382 static int psp_load_smu_fw(struct psp_context *psp)
2383 {
2384         int ret;
2385         struct amdgpu_device *adev = psp->adev;
2386         struct amdgpu_firmware_info *ucode =
2387                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2388         struct amdgpu_ras *ras = psp->ras_context.ras;
2389
2390         /*
2391          * Skip SMU FW reloading in case of using BACO for runpm only,
2392          * as SMU is always alive.
2393          */
2394         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2395                 return 0;
2396
2397         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2398                 return 0;
2399
2400         if ((amdgpu_in_reset(adev) &&
2401              ras && adev->ras_enabled &&
2402              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2403               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2404                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2405                 if (ret)
2406                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2407         }
2408
2409         ret = psp_execute_non_psp_fw_load(psp, ucode);
2410
2411         if (ret)
2412                 DRM_ERROR("PSP load smu failed!\n");
2413
2414         return ret;
2415 }
2416
2417 static bool fw_load_skip_check(struct psp_context *psp,
2418                                struct amdgpu_firmware_info *ucode)
2419 {
2420         if (!ucode->fw || !ucode->ucode_size)
2421                 return true;
2422
2423         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2424             (psp_smu_reload_quirk(psp) ||
2425              psp->autoload_supported ||
2426              psp->pmfw_centralized_cstate_management))
2427                 return true;
2428
2429         if (amdgpu_sriov_vf(psp->adev) &&
2430             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2431                 return true;
2432
2433         if (psp->autoload_supported &&
2434             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2435              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2436                 /* skip mec JT when autoload is enabled */
2437                 return true;
2438
2439         return false;
2440 }
2441
2442 int psp_load_fw_list(struct psp_context *psp,
2443                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2444 {
2445         int ret = 0, i;
2446         struct amdgpu_firmware_info *ucode;
2447
2448         for (i = 0; i < ucode_count; ++i) {
2449                 ucode = ucode_list[i];
2450                 psp_print_fw_hdr(psp, ucode);
2451                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2452                 if (ret)
2453                         return ret;
2454         }
2455         return ret;
2456 }
2457
2458 static int psp_load_non_psp_fw(struct psp_context *psp)
2459 {
2460         int i, ret;
2461         struct amdgpu_firmware_info *ucode;
2462         struct amdgpu_device *adev = psp->adev;
2463
2464         if (psp->autoload_supported &&
2465             !psp->pmfw_centralized_cstate_management) {
2466                 ret = psp_load_smu_fw(psp);
2467                 if (ret)
2468                         return ret;
2469         }
2470
2471         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2472                 ucode = &adev->firmware.ucode[i];
2473
2474                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2475                     !fw_load_skip_check(psp, ucode)) {
2476                         ret = psp_load_smu_fw(psp);
2477                         if (ret)
2478                                 return ret;
2479                         continue;
2480                 }
2481
2482                 if (fw_load_skip_check(psp, ucode))
2483                         continue;
2484
2485                 if (psp->autoload_supported &&
2486                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2487                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2488                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2489                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2490                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2491                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2492                         /* PSP only receive one SDMA fw for sienna_cichlid,
2493                          * as all four sdma fw are same */
2494                         continue;
2495
2496                 psp_print_fw_hdr(psp, ucode);
2497
2498                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2499                 if (ret)
2500                         return ret;
2501
2502                 /* Start rlc autoload after psp recieved all the gfx firmware */
2503                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2504                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2505                         ret = psp_rlc_autoload_start(psp);
2506                         if (ret) {
2507                                 DRM_ERROR("Failed to start rlc autoload\n");
2508                                 return ret;
2509                         }
2510                 }
2511         }
2512
2513         return 0;
2514 }
2515
2516 static int psp_load_fw(struct amdgpu_device *adev)
2517 {
2518         int ret;
2519         struct psp_context *psp = &adev->psp;
2520
2521         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2522                 /* should not destroy ring, only stop */
2523                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2524         } else {
2525                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2526
2527                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2528                 if (ret) {
2529                         DRM_ERROR("PSP ring init failed!\n");
2530                         goto failed;
2531                 }
2532         }
2533
2534         ret = psp_hw_start(psp);
2535         if (ret)
2536                 goto failed;
2537
2538         ret = psp_load_non_psp_fw(psp);
2539         if (ret)
2540                 goto failed1;
2541
2542         ret = psp_asd_initialize(psp);
2543         if (ret) {
2544                 DRM_ERROR("PSP load asd failed!\n");
2545                 goto failed1;
2546         }
2547
2548         ret = psp_rl_load(adev);
2549         if (ret) {
2550                 DRM_ERROR("PSP load RL failed!\n");
2551                 goto failed1;
2552         }
2553
2554         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2555                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2556                         ret = psp_xgmi_initialize(psp, false, true);
2557                         /* Warning the XGMI seesion initialize failure
2558                         * Instead of stop driver initialization
2559                         */
2560                         if (ret)
2561                                 dev_err(psp->adev->dev,
2562                                         "XGMI: Failed to initialize XGMI session\n");
2563                 }
2564         }
2565
2566         if (psp->ta_fw) {
2567                 ret = psp_ras_initialize(psp);
2568                 if (ret)
2569                         dev_err(psp->adev->dev,
2570                                         "RAS: Failed to initialize RAS\n");
2571
2572                 ret = psp_hdcp_initialize(psp);
2573                 if (ret)
2574                         dev_err(psp->adev->dev,
2575                                 "HDCP: Failed to initialize HDCP\n");
2576
2577                 ret = psp_dtm_initialize(psp);
2578                 if (ret)
2579                         dev_err(psp->adev->dev,
2580                                 "DTM: Failed to initialize DTM\n");
2581
2582                 ret = psp_rap_initialize(psp);
2583                 if (ret)
2584                         dev_err(psp->adev->dev,
2585                                 "RAP: Failed to initialize RAP\n");
2586
2587                 ret = psp_securedisplay_initialize(psp);
2588                 if (ret)
2589                         dev_err(psp->adev->dev,
2590                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2591         }
2592
2593         return 0;
2594
2595 failed1:
2596         psp_free_shared_bufs(psp);
2597 failed:
2598         /*
2599          * all cleanup jobs (xgmi terminate, ras terminate,
2600          * ring destroy, cmd/fence/fw buffers destory,
2601          * psp->cmd destory) are delayed to psp_hw_fini
2602          */
2603         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2604         return ret;
2605 }
2606
2607 static int psp_hw_init(void *handle)
2608 {
2609         int ret;
2610         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2611
2612         mutex_lock(&adev->firmware.mutex);
2613         /*
2614          * This sequence is just used on hw_init only once, no need on
2615          * resume.
2616          */
2617         ret = amdgpu_ucode_init_bo(adev);
2618         if (ret)
2619                 goto failed;
2620
2621         ret = psp_load_fw(adev);
2622         if (ret) {
2623                 DRM_ERROR("PSP firmware loading failed\n");
2624                 goto failed;
2625         }
2626
2627         mutex_unlock(&adev->firmware.mutex);
2628         return 0;
2629
2630 failed:
2631         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2632         mutex_unlock(&adev->firmware.mutex);
2633         return -EINVAL;
2634 }
2635
2636 static int psp_hw_fini(void *handle)
2637 {
2638         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2639         struct psp_context *psp = &adev->psp;
2640
2641         if (psp->ta_fw) {
2642                 psp_ras_terminate(psp);
2643                 psp_securedisplay_terminate(psp);
2644                 psp_rap_terminate(psp);
2645                 psp_dtm_terminate(psp);
2646                 psp_hdcp_terminate(psp);
2647
2648                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2649                         psp_xgmi_terminate(psp);
2650         }
2651
2652         psp_asd_terminate(psp);
2653         psp_tmr_terminate(psp);
2654
2655         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2656
2657         return 0;
2658 }
2659
2660 static int psp_suspend(void *handle)
2661 {
2662         int ret = 0;
2663         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2664         struct psp_context *psp = &adev->psp;
2665
2666         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2667             psp->xgmi_context.context.initialized) {
2668                 ret = psp_xgmi_terminate(psp);
2669                 if (ret) {
2670                         DRM_ERROR("Failed to terminate xgmi ta\n");
2671                         goto out;
2672                 }
2673         }
2674
2675         if (psp->ta_fw) {
2676                 ret = psp_ras_terminate(psp);
2677                 if (ret) {
2678                         DRM_ERROR("Failed to terminate ras ta\n");
2679                         goto out;
2680                 }
2681                 ret = psp_hdcp_terminate(psp);
2682                 if (ret) {
2683                         DRM_ERROR("Failed to terminate hdcp ta\n");
2684                         goto out;
2685                 }
2686                 ret = psp_dtm_terminate(psp);
2687                 if (ret) {
2688                         DRM_ERROR("Failed to terminate dtm ta\n");
2689                         goto out;
2690                 }
2691                 ret = psp_rap_terminate(psp);
2692                 if (ret) {
2693                         DRM_ERROR("Failed to terminate rap ta\n");
2694                         goto out;
2695                 }
2696                 ret = psp_securedisplay_terminate(psp);
2697                 if (ret) {
2698                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2699                         goto out;
2700                 }
2701         }
2702
2703         ret = psp_asd_terminate(psp);
2704         if (ret) {
2705                 DRM_ERROR("Failed to terminate asd\n");
2706                 goto out;
2707         }
2708
2709         ret = psp_tmr_terminate(psp);
2710         if (ret) {
2711                 DRM_ERROR("Failed to terminate tmr\n");
2712                 goto out;
2713         }
2714
2715         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2716         if (ret)
2717                 DRM_ERROR("PSP ring stop failed\n");
2718
2719 out:
2720         return ret;
2721 }
2722
2723 static int psp_resume(void *handle)
2724 {
2725         int ret;
2726         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2727         struct psp_context *psp = &adev->psp;
2728
2729         DRM_INFO("PSP is resuming...\n");
2730
2731         if (psp->mem_train_ctx.enable_mem_training) {
2732                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2733                 if (ret) {
2734                         DRM_ERROR("Failed to process memory training!\n");
2735                         return ret;
2736                 }
2737         }
2738
2739         mutex_lock(&adev->firmware.mutex);
2740
2741         ret = psp_hw_start(psp);
2742         if (ret)
2743                 goto failed;
2744
2745         ret = psp_load_non_psp_fw(psp);
2746         if (ret)
2747                 goto failed;
2748
2749         ret = psp_asd_initialize(psp);
2750         if (ret) {
2751                 DRM_ERROR("PSP load asd failed!\n");
2752                 goto failed;
2753         }
2754
2755         ret = psp_rl_load(adev);
2756         if (ret) {
2757                 dev_err(adev->dev, "PSP load RL failed!\n");
2758                 goto failed;
2759         }
2760
2761         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2762                 ret = psp_xgmi_initialize(psp, false, true);
2763                 /* Warning the XGMI seesion initialize failure
2764                  * Instead of stop driver initialization
2765                  */
2766                 if (ret)
2767                         dev_err(psp->adev->dev,
2768                                 "XGMI: Failed to initialize XGMI session\n");
2769         }
2770
2771         if (psp->ta_fw) {
2772                 ret = psp_ras_initialize(psp);
2773                 if (ret)
2774                         dev_err(psp->adev->dev,
2775                                         "RAS: Failed to initialize RAS\n");
2776
2777                 ret = psp_hdcp_initialize(psp);
2778                 if (ret)
2779                         dev_err(psp->adev->dev,
2780                                 "HDCP: Failed to initialize HDCP\n");
2781
2782                 ret = psp_dtm_initialize(psp);
2783                 if (ret)
2784                         dev_err(psp->adev->dev,
2785                                 "DTM: Failed to initialize DTM\n");
2786
2787                 ret = psp_rap_initialize(psp);
2788                 if (ret)
2789                         dev_err(psp->adev->dev,
2790                                 "RAP: Failed to initialize RAP\n");
2791
2792                 ret = psp_securedisplay_initialize(psp);
2793                 if (ret)
2794                         dev_err(psp->adev->dev,
2795                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2796         }
2797
2798         mutex_unlock(&adev->firmware.mutex);
2799
2800         return 0;
2801
2802 failed:
2803         DRM_ERROR("PSP resume failed\n");
2804         mutex_unlock(&adev->firmware.mutex);
2805         return ret;
2806 }
2807
2808 int psp_gpu_reset(struct amdgpu_device *adev)
2809 {
2810         int ret;
2811
2812         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2813                 return 0;
2814
2815         mutex_lock(&adev->psp.mutex);
2816         ret = psp_mode1_reset(&adev->psp);
2817         mutex_unlock(&adev->psp.mutex);
2818
2819         return ret;
2820 }
2821
2822 int psp_rlc_autoload_start(struct psp_context *psp)
2823 {
2824         int ret;
2825         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2826
2827         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2828
2829         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2830                                  psp->fence_buf_mc_addr);
2831
2832         release_psp_cmd_buf(psp);
2833
2834         return ret;
2835 }
2836
2837 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2838                         uint64_t cmd_gpu_addr, int cmd_size)
2839 {
2840         struct amdgpu_firmware_info ucode = {0};
2841
2842         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2843                 AMDGPU_UCODE_ID_VCN0_RAM;
2844         ucode.mc_addr = cmd_gpu_addr;
2845         ucode.ucode_size = cmd_size;
2846
2847         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2848 }
2849
2850 int psp_ring_cmd_submit(struct psp_context *psp,
2851                         uint64_t cmd_buf_mc_addr,
2852                         uint64_t fence_mc_addr,
2853                         int index)
2854 {
2855         unsigned int psp_write_ptr_reg = 0;
2856         struct psp_gfx_rb_frame *write_frame;
2857         struct psp_ring *ring = &psp->km_ring;
2858         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2859         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2860                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2861         struct amdgpu_device *adev = psp->adev;
2862         uint32_t ring_size_dw = ring->ring_size / 4;
2863         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2864
2865         /* KM (GPCOM) prepare write pointer */
2866         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2867
2868         /* Update KM RB frame pointer to new frame */
2869         /* write_frame ptr increments by size of rb_frame in bytes */
2870         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2871         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2872                 write_frame = ring_buffer_start;
2873         else
2874                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2875         /* Check invalid write_frame ptr address */
2876         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2877                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2878                           ring_buffer_start, ring_buffer_end, write_frame);
2879                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2880                 return -EINVAL;
2881         }
2882
2883         /* Initialize KM RB frame */
2884         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2885
2886         /* Update KM RB frame */
2887         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2888         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2889         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2890         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2891         write_frame->fence_value = index;
2892         amdgpu_device_flush_hdp(adev, NULL);
2893
2894         /* Update the write Pointer in DWORDs */
2895         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2896         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2897         return 0;
2898 }
2899
2900 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2901 {
2902         struct amdgpu_device *adev = psp->adev;
2903         char fw_name[PSP_FW_NAME_LEN];
2904         const struct psp_firmware_header_v1_0 *asd_hdr;
2905         int err = 0;
2906
2907         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2908         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
2909         if (err)
2910                 goto out;
2911
2912         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2913         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2914         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2915         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2916         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2917                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2918         return 0;
2919 out:
2920         amdgpu_ucode_release(&adev->psp.asd_fw);
2921         return err;
2922 }
2923
2924 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
2925 {
2926         struct amdgpu_device *adev = psp->adev;
2927         char fw_name[PSP_FW_NAME_LEN];
2928         const struct psp_firmware_header_v1_0 *toc_hdr;
2929         int err = 0;
2930
2931         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2932         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
2933         if (err)
2934                 goto out;
2935
2936         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2937         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2938         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2939         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2940         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2941                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2942         return 0;
2943 out:
2944         amdgpu_ucode_release(&adev->psp.toc_fw);
2945         return err;
2946 }
2947
2948 static int parse_sos_bin_descriptor(struct psp_context *psp,
2949                                    const struct psp_fw_bin_desc *desc,
2950                                    const struct psp_firmware_header_v2_0 *sos_hdr)
2951 {
2952         uint8_t *ucode_start_addr  = NULL;
2953
2954         if (!psp || !desc || !sos_hdr)
2955                 return -EINVAL;
2956
2957         ucode_start_addr  = (uint8_t *)sos_hdr +
2958                             le32_to_cpu(desc->offset_bytes) +
2959                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2960
2961         switch (desc->fw_type) {
2962         case PSP_FW_TYPE_PSP_SOS:
2963                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
2964                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
2965                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
2966                 psp->sos.start_addr        = ucode_start_addr;
2967                 break;
2968         case PSP_FW_TYPE_PSP_SYS_DRV:
2969                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
2970                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
2971                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
2972                 psp->sys.start_addr        = ucode_start_addr;
2973                 break;
2974         case PSP_FW_TYPE_PSP_KDB:
2975                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
2976                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
2977                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
2978                 psp->kdb.start_addr        = ucode_start_addr;
2979                 break;
2980         case PSP_FW_TYPE_PSP_TOC:
2981                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
2982                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
2983                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
2984                 psp->toc.start_addr        = ucode_start_addr;
2985                 break;
2986         case PSP_FW_TYPE_PSP_SPL:
2987                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
2988                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
2989                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
2990                 psp->spl.start_addr        = ucode_start_addr;
2991                 break;
2992         case PSP_FW_TYPE_PSP_RL:
2993                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
2994                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
2995                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
2996                 psp->rl.start_addr         = ucode_start_addr;
2997                 break;
2998         case PSP_FW_TYPE_PSP_SOC_DRV:
2999                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3000                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3001                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3002                 psp->soc_drv.start_addr         = ucode_start_addr;
3003                 break;
3004         case PSP_FW_TYPE_PSP_INTF_DRV:
3005                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3006                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3007                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3008                 psp->intf_drv.start_addr        = ucode_start_addr;
3009                 break;
3010         case PSP_FW_TYPE_PSP_DBG_DRV:
3011                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3012                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3013                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3014                 psp->dbg_drv.start_addr         = ucode_start_addr;
3015                 break;
3016         case PSP_FW_TYPE_PSP_RAS_DRV:
3017                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3018                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3019                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3020                 psp->ras_drv.start_addr         = ucode_start_addr;
3021                 break;
3022         default:
3023                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3024                 break;
3025         }
3026
3027         return 0;
3028 }
3029
3030 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3031 {
3032         const struct psp_firmware_header_v1_0 *sos_hdr;
3033         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3034         uint8_t *ucode_array_start_addr;
3035
3036         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3037         ucode_array_start_addr = (uint8_t *)sos_hdr +
3038                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3039
3040         if (adev->gmc.xgmi.connected_to_cpu ||
3041             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3042                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3043                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3044
3045                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3046                 adev->psp.sys.start_addr = ucode_array_start_addr;
3047
3048                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3049                 adev->psp.sos.start_addr = ucode_array_start_addr +
3050                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3051         } else {
3052                 /* Load alternate PSP SOS FW */
3053                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3054
3055                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3056                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3057
3058                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3059                 adev->psp.sys.start_addr = ucode_array_start_addr +
3060                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3061
3062                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3063                 adev->psp.sos.start_addr = ucode_array_start_addr +
3064                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3065         }
3066
3067         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3068                 dev_warn(adev->dev, "PSP SOS FW not available");
3069                 return -EINVAL;
3070         }
3071
3072         return 0;
3073 }
3074
3075 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3076 {
3077         struct amdgpu_device *adev = psp->adev;
3078         char fw_name[PSP_FW_NAME_LEN];
3079         const struct psp_firmware_header_v1_0 *sos_hdr;
3080         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3081         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3082         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3083         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3084         int err = 0;
3085         uint8_t *ucode_array_start_addr;
3086         int fw_index = 0;
3087
3088         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3089         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3090         if (err)
3091                 goto out;
3092
3093         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3094         ucode_array_start_addr = (uint8_t *)sos_hdr +
3095                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3096         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3097
3098         switch (sos_hdr->header.header_version_major) {
3099         case 1:
3100                 err = psp_init_sos_base_fw(adev);
3101                 if (err)
3102                         goto out;
3103
3104                 if (sos_hdr->header.header_version_minor == 1) {
3105                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3106                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3107                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3108                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3109                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3110                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3111                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3112                 }
3113                 if (sos_hdr->header.header_version_minor == 2) {
3114                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3115                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3116                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3117                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3118                 }
3119                 if (sos_hdr->header.header_version_minor == 3) {
3120                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3121                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3122                         adev->psp.toc.start_addr = ucode_array_start_addr +
3123                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3124                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3125                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3126                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3127                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3128                         adev->psp.spl.start_addr = ucode_array_start_addr +
3129                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3130                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3131                         adev->psp.rl.start_addr = ucode_array_start_addr +
3132                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3133                 }
3134                 break;
3135         case 2:
3136                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3137
3138                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3139                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3140                         err = -EINVAL;
3141                         goto out;
3142                 }
3143
3144                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3145                         err = parse_sos_bin_descriptor(psp,
3146                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3147                                                        sos_hdr_v2_0);
3148                         if (err)
3149                                 goto out;
3150                 }
3151                 break;
3152         default:
3153                 dev_err(adev->dev,
3154                         "unsupported psp sos firmware\n");
3155                 err = -EINVAL;
3156                 goto out;
3157         }
3158
3159         return 0;
3160 out:
3161         amdgpu_ucode_release(&adev->psp.sos_fw);
3162
3163         return err;
3164 }
3165
3166 static int parse_ta_bin_descriptor(struct psp_context *psp,
3167                                    const struct psp_fw_bin_desc *desc,
3168                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3169 {
3170         uint8_t *ucode_start_addr  = NULL;
3171
3172         if (!psp || !desc || !ta_hdr)
3173                 return -EINVAL;
3174
3175         ucode_start_addr  = (uint8_t *)ta_hdr +
3176                             le32_to_cpu(desc->offset_bytes) +
3177                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3178
3179         switch (desc->fw_type) {
3180         case TA_FW_TYPE_PSP_ASD:
3181                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3182                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3183                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3184                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3185                 break;
3186         case TA_FW_TYPE_PSP_XGMI:
3187                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3188                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3189                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3190                 break;
3191         case TA_FW_TYPE_PSP_RAS:
3192                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3193                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3194                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3195                 break;
3196         case TA_FW_TYPE_PSP_HDCP:
3197                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3198                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3199                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3200                 break;
3201         case TA_FW_TYPE_PSP_DTM:
3202                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3203                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3204                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3205                 break;
3206         case TA_FW_TYPE_PSP_RAP:
3207                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3208                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3209                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3210                 break;
3211         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3212                 psp->securedisplay_context.context.bin_desc.fw_version =
3213                         le32_to_cpu(desc->fw_version);
3214                 psp->securedisplay_context.context.bin_desc.size_bytes =
3215                         le32_to_cpu(desc->size_bytes);
3216                 psp->securedisplay_context.context.bin_desc.start_addr =
3217                         ucode_start_addr;
3218                 break;
3219         default:
3220                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3221                 break;
3222         }
3223
3224         return 0;
3225 }
3226
3227 static int parse_ta_v1_microcode(struct psp_context *psp)
3228 {
3229         const struct ta_firmware_header_v1_0 *ta_hdr;
3230         struct amdgpu_device *adev = psp->adev;
3231
3232         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3233
3234         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3235                 return -EINVAL;
3236
3237         adev->psp.xgmi_context.context.bin_desc.fw_version =
3238                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3239         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3240                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3241         adev->psp.xgmi_context.context.bin_desc.start_addr =
3242                 (uint8_t *)ta_hdr +
3243                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3244
3245         adev->psp.ras_context.context.bin_desc.fw_version =
3246                 le32_to_cpu(ta_hdr->ras.fw_version);
3247         adev->psp.ras_context.context.bin_desc.size_bytes =
3248                 le32_to_cpu(ta_hdr->ras.size_bytes);
3249         adev->psp.ras_context.context.bin_desc.start_addr =
3250                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3251                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3252
3253         adev->psp.hdcp_context.context.bin_desc.fw_version =
3254                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3255         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3256                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3257         adev->psp.hdcp_context.context.bin_desc.start_addr =
3258                 (uint8_t *)ta_hdr +
3259                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3260
3261         adev->psp.dtm_context.context.bin_desc.fw_version =
3262                 le32_to_cpu(ta_hdr->dtm.fw_version);
3263         adev->psp.dtm_context.context.bin_desc.size_bytes =
3264                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3265         adev->psp.dtm_context.context.bin_desc.start_addr =
3266                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3267                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3268
3269         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3270                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3271         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3272                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3273         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3274                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3275                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3276
3277         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3278
3279         return 0;
3280 }
3281
3282 static int parse_ta_v2_microcode(struct psp_context *psp)
3283 {
3284         const struct ta_firmware_header_v2_0 *ta_hdr;
3285         struct amdgpu_device *adev = psp->adev;
3286         int err = 0;
3287         int ta_index = 0;
3288
3289         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3290
3291         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3292                 return -EINVAL;
3293
3294         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3295                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3296                 return -EINVAL;
3297         }
3298
3299         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3300                 err = parse_ta_bin_descriptor(psp,
3301                                               &ta_hdr->ta_fw_bin[ta_index],
3302                                               ta_hdr);
3303                 if (err)
3304                         return err;
3305         }
3306
3307         return 0;
3308 }
3309
3310 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3311 {
3312         const struct common_firmware_header *hdr;
3313         struct amdgpu_device *adev = psp->adev;
3314         char fw_name[PSP_FW_NAME_LEN];
3315         int err;
3316
3317         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3318         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3319         if (err)
3320                 return err;
3321
3322         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3323         switch (le16_to_cpu(hdr->header_version_major)) {
3324         case 1:
3325                 err = parse_ta_v1_microcode(psp);
3326                 break;
3327         case 2:
3328                 err = parse_ta_v2_microcode(psp);
3329                 break;
3330         default:
3331                 dev_err(adev->dev, "unsupported TA header version\n");
3332                 err = -EINVAL;
3333         }
3334
3335         if (err)
3336                 amdgpu_ucode_release(&adev->psp.ta_fw);
3337
3338         return err;
3339 }
3340
3341 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3342 {
3343         struct amdgpu_device *adev = psp->adev;
3344         char fw_name[PSP_FW_NAME_LEN];
3345         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3346         struct amdgpu_firmware_info *info = NULL;
3347         int err = 0;
3348
3349         if (!amdgpu_sriov_vf(adev)) {
3350                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3351                 return -EINVAL;
3352         }
3353
3354         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3355         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3356         if (err) {
3357                 if (err == -ENODEV) {
3358                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3359                         err = 0;
3360                         goto out;
3361                 }
3362                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3363         }
3364
3365         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3366         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3367         info->fw = adev->psp.cap_fw;
3368         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3369                 adev->psp.cap_fw->data;
3370         adev->firmware.fw_size += ALIGN(
3371                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3372         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3373         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3374         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3375
3376         return 0;
3377
3378 out:
3379         amdgpu_ucode_release(&adev->psp.cap_fw);
3380         return err;
3381 }
3382
3383 static int psp_set_clockgating_state(void *handle,
3384                                      enum amd_clockgating_state state)
3385 {
3386         return 0;
3387 }
3388
3389 static int psp_set_powergating_state(void *handle,
3390                                      enum amd_powergating_state state)
3391 {
3392         return 0;
3393 }
3394
3395 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3396                                          struct device_attribute *attr,
3397                                          char *buf)
3398 {
3399         struct drm_device *ddev = dev_get_drvdata(dev);
3400         struct amdgpu_device *adev = drm_to_adev(ddev);
3401         uint32_t fw_ver;
3402         int ret;
3403
3404         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3405                 DRM_INFO("PSP block is not ready yet.");
3406                 return -EBUSY;
3407         }
3408
3409         mutex_lock(&adev->psp.mutex);
3410         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3411         mutex_unlock(&adev->psp.mutex);
3412
3413         if (ret) {
3414                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3415                 return ret;
3416         }
3417
3418         return sysfs_emit(buf, "%x\n", fw_ver);
3419 }
3420
3421 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3422                                                        struct device_attribute *attr,
3423                                                        const char *buf,
3424                                                        size_t count)
3425 {
3426         struct drm_device *ddev = dev_get_drvdata(dev);
3427         struct amdgpu_device *adev = drm_to_adev(ddev);
3428         int ret, idx;
3429         char fw_name[100];
3430         const struct firmware *usbc_pd_fw;
3431         struct amdgpu_bo *fw_buf_bo = NULL;
3432         uint64_t fw_pri_mc_addr;
3433         void *fw_pri_cpu_addr;
3434
3435         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3436                 DRM_INFO("PSP block is not ready yet.");
3437                 return -EBUSY;
3438         }
3439
3440         if (!drm_dev_enter(ddev, &idx))
3441                 return -ENODEV;
3442
3443         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3444         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3445         if (ret)
3446                 goto fail;
3447
3448         /* LFB address which is aligned to 1MB boundary per PSP request */
3449         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3450                                       AMDGPU_GEM_DOMAIN_VRAM |
3451                                       AMDGPU_GEM_DOMAIN_GTT,
3452                                       &fw_buf_bo, &fw_pri_mc_addr,
3453                                       &fw_pri_cpu_addr);
3454         if (ret)
3455                 goto rel_buf;
3456
3457         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3458
3459         mutex_lock(&adev->psp.mutex);
3460         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3461         mutex_unlock(&adev->psp.mutex);
3462
3463         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3464
3465 rel_buf:
3466         release_firmware(usbc_pd_fw);
3467 fail:
3468         if (ret) {
3469                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3470                 count = ret;
3471         }
3472
3473         drm_dev_exit(idx);
3474         return count;
3475 }
3476
3477 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3478 {
3479         int idx;
3480
3481         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3482                 return;
3483
3484         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3485         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3486
3487         drm_dev_exit(idx);
3488 }
3489
3490 static DEVICE_ATTR(usbc_pd_fw, 0644,
3491                    psp_usbc_pd_fw_sysfs_read,
3492                    psp_usbc_pd_fw_sysfs_write);
3493
3494 int is_psp_fw_valid(struct psp_bin_desc bin)
3495 {
3496         return bin.size_bytes;
3497 }
3498
3499 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3500                                         struct bin_attribute *bin_attr,
3501                                         char *buffer, loff_t pos, size_t count)
3502 {
3503         struct device *dev = kobj_to_dev(kobj);
3504         struct drm_device *ddev = dev_get_drvdata(dev);
3505         struct amdgpu_device *adev = drm_to_adev(ddev);
3506
3507         adev->psp.vbflash_done = false;
3508
3509         /* Safeguard against memory drain */
3510         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3511                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3512                 kvfree(adev->psp.vbflash_tmp_buf);
3513                 adev->psp.vbflash_tmp_buf = NULL;
3514                 adev->psp.vbflash_image_size = 0;
3515                 return -ENOMEM;
3516         }
3517
3518         /* TODO Just allocate max for now and optimize to realloc later if needed */
3519         if (!adev->psp.vbflash_tmp_buf) {
3520                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3521                 if (!adev->psp.vbflash_tmp_buf)
3522                         return -ENOMEM;
3523         }
3524
3525         mutex_lock(&adev->psp.mutex);
3526         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3527         adev->psp.vbflash_image_size += count;
3528         mutex_unlock(&adev->psp.mutex);
3529
3530         dev_info(adev->dev, "VBIOS flash write PSP done");
3531
3532         return count;
3533 }
3534
3535 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3536                                        struct bin_attribute *bin_attr, char *buffer,
3537                                        loff_t pos, size_t count)
3538 {
3539         struct device *dev = kobj_to_dev(kobj);
3540         struct drm_device *ddev = dev_get_drvdata(dev);
3541         struct amdgpu_device *adev = drm_to_adev(ddev);
3542         struct amdgpu_bo *fw_buf_bo = NULL;
3543         uint64_t fw_pri_mc_addr;
3544         void *fw_pri_cpu_addr;
3545         int ret;
3546
3547         dev_info(adev->dev, "VBIOS flash to PSP started");
3548
3549         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3550                                         AMDGPU_GPU_PAGE_SIZE,
3551                                         AMDGPU_GEM_DOMAIN_VRAM,
3552                                         &fw_buf_bo,
3553                                         &fw_pri_mc_addr,
3554                                         &fw_pri_cpu_addr);
3555         if (ret)
3556                 goto rel_buf;
3557
3558         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3559
3560         mutex_lock(&adev->psp.mutex);
3561         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3562         mutex_unlock(&adev->psp.mutex);
3563
3564         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3565
3566 rel_buf:
3567         kvfree(adev->psp.vbflash_tmp_buf);
3568         adev->psp.vbflash_tmp_buf = NULL;
3569         adev->psp.vbflash_image_size = 0;
3570
3571         if (ret) {
3572                 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3573                 return ret;
3574         }
3575
3576         dev_info(adev->dev, "VBIOS flash to PSP done");
3577         return 0;
3578 }
3579
3580 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3581                                          struct device_attribute *attr,
3582                                          char *buf)
3583 {
3584         struct drm_device *ddev = dev_get_drvdata(dev);
3585         struct amdgpu_device *adev = drm_to_adev(ddev);
3586         uint32_t vbflash_status;
3587
3588         vbflash_status = psp_vbflash_status(&adev->psp);
3589         if (!adev->psp.vbflash_done)
3590                 vbflash_status = 0;
3591         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3592                 vbflash_status = 1;
3593
3594         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3595 }
3596
3597 static const struct bin_attribute psp_vbflash_bin_attr = {
3598         .attr = {.name = "psp_vbflash", .mode = 0664},
3599         .size = 0,
3600         .write = amdgpu_psp_vbflash_write,
3601         .read = amdgpu_psp_vbflash_read,
3602 };
3603
3604 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3605
3606 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3607 {
3608         int ret = 0;
3609         struct psp_context *psp = &adev->psp;
3610
3611         if (amdgpu_sriov_vf(adev))
3612                 return -EINVAL;
3613
3614         switch (adev->ip_versions[MP0_HWIP][0]) {
3615         case IP_VERSION(13, 0, 0):
3616         case IP_VERSION(13, 0, 7):
3617         case IP_VERSION(13, 0, 10):
3618                 if (!psp->adev) {
3619                         psp->adev = adev;
3620                         psp_v13_0_set_psp_funcs(psp);
3621                 }
3622                 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3623                 if (ret)
3624                         dev_err(adev->dev, "Failed to create device file psp_vbflash");
3625                 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3626                 if (ret)
3627                         dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3628                 return ret;
3629         default:
3630                 return 0;
3631         }
3632 }
3633
3634 const struct amd_ip_funcs psp_ip_funcs = {
3635         .name = "psp",
3636         .early_init = psp_early_init,
3637         .late_init = NULL,
3638         .sw_init = psp_sw_init,
3639         .sw_fini = psp_sw_fini,
3640         .hw_init = psp_hw_init,
3641         .hw_fini = psp_hw_fini,
3642         .suspend = psp_suspend,
3643         .resume = psp_resume,
3644         .is_idle = NULL,
3645         .check_soft_reset = NULL,
3646         .wait_for_idle = NULL,
3647         .soft_reset = NULL,
3648         .set_clockgating_state = psp_set_clockgating_state,
3649         .set_powergating_state = psp_set_powergating_state,
3650 };
3651
3652 static int psp_sysfs_init(struct amdgpu_device *adev)
3653 {
3654         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3655
3656         if (ret)
3657                 DRM_ERROR("Failed to create USBC PD FW control file!");
3658
3659         return ret;
3660 }
3661
3662 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3663 {
3664         sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3665         device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3666 }
3667
3668 static void psp_sysfs_fini(struct amdgpu_device *adev)
3669 {
3670         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3671 }
3672
3673 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
3674         .type = AMD_IP_BLOCK_TYPE_PSP,
3675         .major = 3,
3676         .minor = 1,
3677         .rev = 0,
3678         .funcs = &psp_ip_funcs,
3679 };
3680
3681 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
3682         .type = AMD_IP_BLOCK_TYPE_PSP,
3683         .major = 10,
3684         .minor = 0,
3685         .rev = 0,
3686         .funcs = &psp_ip_funcs,
3687 };
3688
3689 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
3690         .type = AMD_IP_BLOCK_TYPE_PSP,
3691         .major = 11,
3692         .minor = 0,
3693         .rev = 0,
3694         .funcs = &psp_ip_funcs,
3695 };
3696
3697 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3698         .type = AMD_IP_BLOCK_TYPE_PSP,
3699         .major = 11,
3700         .minor = 0,
3701         .rev = 8,
3702         .funcs = &psp_ip_funcs,
3703 };
3704
3705 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
3706         .type = AMD_IP_BLOCK_TYPE_PSP,
3707         .major = 12,
3708         .minor = 0,
3709         .rev = 0,
3710         .funcs = &psp_ip_funcs,
3711 };
3712
3713 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3714         .type = AMD_IP_BLOCK_TYPE_PSP,
3715         .major = 13,
3716         .minor = 0,
3717         .rev = 0,
3718         .funcs = &psp_ip_funcs,
3719 };
3720
3721 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3722         .type = AMD_IP_BLOCK_TYPE_PSP,
3723         .major = 13,
3724         .minor = 0,
3725         .rev = 4,
3726         .funcs = &psp_ip_funcs,
3727 };