drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_GFX_H__
  25 #define __AMDGPU_GFX_H__
  26
  27 /*
  28  * GFX stuff
  29  */
  30 #include "clearstate_defs.h"
  31 #include "amdgpu_ring.h"
  32 #include "amdgpu_rlc.h"
  33 #include "amdgpu_imu.h"
  34 #include "soc15.h"
  35 #include "amdgpu_ras.h"
  36 #include "amdgpu_ring_mux.h"
  37
  38 /* GFX current status */
  39 #define AMDGPU_GFX_NORMAL_MODE                  0x00000000L
  40 #define AMDGPU_GFX_SAFE_MODE                    0x00000001L
  41 #define AMDGPU_GFX_PG_DISABLED_MODE             0x00000002L
  42 #define AMDGPU_GFX_CG_DISABLED_MODE             0x00000004L
  43 #define AMDGPU_GFX_LBPW_DISABLED_MODE           0x00000008L
  44
  45 #define AMDGPU_MAX_GC_INSTANCES         8
  46
  47 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
  48 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
  49
  50 enum amdgpu_gfx_pipe_priority {
  51         AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
  52         AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
  53 };
  54
  55 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
  56 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
  57
  58 enum amdgpu_gfx_partition {
  59         AMDGPU_SPX_PARTITION_MODE = 0,
  60         AMDGPU_DPX_PARTITION_MODE = 1,
  61         AMDGPU_TPX_PARTITION_MODE = 2,
  62         AMDGPU_QPX_PARTITION_MODE = 3,
  63         AMDGPU_CPX_PARTITION_MODE = 4,
  64         AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE,
  65 };
  66
  67 #define NUM_XCC(x) hweight16(x)
  68
  69 struct amdgpu_mec {
  70         struct amdgpu_bo        *hpd_eop_obj;
  71         u64                     hpd_eop_gpu_addr;
  72         struct amdgpu_bo        *mec_fw_obj;
  73         u64                     mec_fw_gpu_addr;
  74         struct amdgpu_bo        *mec_fw_data_obj;
  75         u64                     mec_fw_data_gpu_addr;
  76
  77         u32 num_mec;
  78         u32 num_pipe_per_mec;
  79         u32 num_queue_per_pipe;
  80         void                    *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
  81 };
  82
  83 struct amdgpu_mec_bitmap {
  84         /* These are the resources for which amdgpu takes ownership */
  85         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
  86 };
  87
  88 enum amdgpu_unmap_queues_action {
  89         PREEMPT_QUEUES = 0,
  90         RESET_QUEUES,
  91         DISABLE_PROCESS_QUEUES,
  92         PREEMPT_QUEUES_NO_UNMAP,
  93 };
  94
  95 struct kiq_pm4_funcs {
  96         /* Support ASIC-specific kiq pm4 packets*/
  97         void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
  98                                         uint64_t queue_mask);
  99         void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
 100                                         struct amdgpu_ring *ring);
 101         void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
 102                                  struct amdgpu_ring *ring,
 103                                  enum amdgpu_unmap_queues_action action,
 104                                  u64 gpu_addr, u64 seq);
 105         void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
 106                                         struct amdgpu_ring *ring,
 107                                         u64 addr,
 108                                         u64 seq);
 109         void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
 110                                 uint16_t pasid, uint32_t flush_type,
 111                                 bool all_hub);
 112         /* Packet sizes */
 113         int set_resources_size;
 114         int map_queues_size;
 115         int unmap_queues_size;
 116         int query_status_size;
 117         int invalidate_tlbs_size;
 118 };
 119
 120 struct amdgpu_kiq {
 121         u64                     eop_gpu_addr;
 122         struct amdgpu_bo        *eop_obj;
 123         spinlock_t              ring_lock;
 124         struct amdgpu_ring      ring;
 125         struct amdgpu_irq_src   irq;
 126         const struct kiq_pm4_funcs *pmf;
 127         void                    *mqd_backup;
 128 };
 129
 130 /*
 131  * GFX configurations
 132  */
 133 #define AMDGPU_GFX_MAX_SE 4
 134 #define AMDGPU_GFX_MAX_SH_PER_SE 2
 135
 136 struct amdgpu_rb_config {
 137         uint32_t rb_backend_disable;
 138         uint32_t user_rb_backend_disable;
 139         uint32_t raster_config;
 140         uint32_t raster_config_1;
 141 };
 142
 143 struct gb_addr_config {
 144         uint16_t pipe_interleave_size;
 145         uint8_t num_pipes;
 146         uint8_t max_compress_frags;
 147         uint8_t num_banks;
 148         uint8_t num_se;
 149         uint8_t num_rb_per_se;
 150         uint8_t num_pkrs;
 151 };
 152
 153 struct amdgpu_gfx_config {
 154         unsigned max_shader_engines;
 155         unsigned max_tile_pipes;
 156         unsigned max_cu_per_sh;
 157         unsigned max_sh_per_se;
 158         unsigned max_backends_per_se;
 159         unsigned max_texture_channel_caches;
 160         unsigned max_gprs;
 161         unsigned max_gs_threads;
 162         unsigned max_hw_contexts;
 163         unsigned sc_prim_fifo_size_frontend;
 164         unsigned sc_prim_fifo_size_backend;
 165         unsigned sc_hiz_tile_fifo_size;
 166         unsigned sc_earlyz_tile_fifo_size;
 167
 168         unsigned num_tile_pipes;
 169         unsigned backend_enable_mask;
 170         unsigned mem_max_burst_length_bytes;
 171         unsigned mem_row_size_in_kb;
 172         unsigned shader_engine_tile_size;
 173         unsigned num_gpus;
 174         unsigned multi_gpu_tile_size;
 175         unsigned mc_arb_ramcfg;
 176         unsigned num_banks;
 177         unsigned num_ranks;
 178         unsigned gb_addr_config;
 179         unsigned num_rbs;
 180         unsigned gs_vgt_table_depth;
 181         unsigned gs_prim_buffer_depth;
 182
 183         uint32_t tile_mode_array[32];
 184         uint32_t macrotile_mode_array[16];
 185
 186         struct gb_addr_config gb_addr_config_fields;
 187         struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
 188
 189         /* gfx configure feature */
 190         uint32_t double_offchip_lds_buf;
 191         /* cached value of DB_DEBUG2 */
 192         uint32_t db_debug2;
 193         /* gfx10 specific config */
 194         uint32_t num_sc_per_sh;
 195         uint32_t num_packer_per_sc;
 196         uint32_t pa_sc_tile_steering_override;
 197         /* Whether texture coordinate truncation is conformant. */
 198         bool ta_cntl2_truncate_coord_mode;
 199         uint64_t tcc_disabled_mask;
 200         uint32_t gc_num_tcp_per_sa;
 201         uint32_t gc_num_sdp_interface;
 202         uint32_t gc_num_tcps;
 203         uint32_t gc_num_tcp_per_wpg;
 204         uint32_t gc_tcp_l1_size;
 205         uint32_t gc_num_sqc_per_wgp;
 206         uint32_t gc_l1_instruction_cache_size_per_sqc;
 207         uint32_t gc_l1_data_cache_size_per_sqc;
 208         uint32_t gc_gl1c_per_sa;
 209         uint32_t gc_gl1c_size_per_instance;
 210         uint32_t gc_gl2c_per_gpu;
 211 };
 212
 213 struct amdgpu_cu_info {
 214         uint32_t simd_per_cu;
 215         uint32_t max_waves_per_simd;
 216         uint32_t wave_front_size;
 217         uint32_t max_scratch_slots_per_cu;
 218         uint32_t lds_size;
 219
 220         /* total active CU number */
 221         uint32_t number;
 222         uint32_t ao_cu_mask;
 223         uint32_t ao_cu_bitmap[4][4];
 224         uint32_t bitmap[4][4];
 225 };
 226
 227 struct amdgpu_gfx_ras {
 228         struct amdgpu_ras_block_object  ras_block;
 229         void (*enable_watchdog_timer)(struct amdgpu_device *adev);
 230         bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
 231         int (*rlc_gc_fed_irq)(struct amdgpu_device *adev,
 232                                 struct amdgpu_irq_src *source,
 233                                 struct amdgpu_iv_entry *entry);
 234         int (*poison_consumption_handler)(struct amdgpu_device *adev,
 235                                                 struct amdgpu_iv_entry *entry);
 236 };
 237
 238 struct amdgpu_gfx_shadow_info {
 239         u32 shadow_size;
 240         u32 shadow_alignment;
 241         u32 csa_size;
 242         u32 csa_alignment;
 243 };
 244
 245 struct amdgpu_gfx_funcs {
 246         /* get the gpu clock counter */
 247         uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
 248         void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
 249                              u32 sh_num, u32 instance, int xcc_id);
 250         void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
 251                                uint32_t wave, uint32_t *dst, int *no_fields);
 252         void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
 253                                 uint32_t wave, uint32_t thread, uint32_t start,
 254                                 uint32_t size, uint32_t *dst);
 255         void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
 256                                 uint32_t wave, uint32_t start, uint32_t size,
 257                                 uint32_t *dst);
 258         void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
 259                                  u32 queue, u32 vmid);
 260         void (*init_spm_golden)(struct amdgpu_device *adev);
 261         void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
 262         int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
 263                                    struct amdgpu_gfx_shadow_info *shadow_info);
 264         enum amdgpu_gfx_partition
 265                         (*query_partition_mode)(struct amdgpu_device *adev);
 266         int (*switch_partition_mode)(struct amdgpu_device *adev,
 267                                      enum amdgpu_gfx_partition mode);
 268 };
 269
 270 struct sq_work {
 271         struct work_struct      work;
 272         unsigned ih_data;
 273 };
 274
 275 struct amdgpu_pfp {
 276         struct amdgpu_bo                *pfp_fw_obj;
 277         uint64_t                        pfp_fw_gpu_addr;
 278         uint32_t                        *pfp_fw_ptr;
 279
 280         struct amdgpu_bo                *pfp_fw_data_obj;
 281         uint64_t                        pfp_fw_data_gpu_addr;
 282         uint32_t                        *pfp_fw_data_ptr;
 283 };
 284
 285 struct amdgpu_ce {
 286         struct amdgpu_bo                *ce_fw_obj;
 287         uint64_t                        ce_fw_gpu_addr;
 288         uint32_t                        *ce_fw_ptr;
 289 };
 290
 291 struct amdgpu_me {
 292         struct amdgpu_bo                *me_fw_obj;
 293         uint64_t                        me_fw_gpu_addr;
 294         uint32_t                        *me_fw_ptr;
 295
 296         struct amdgpu_bo                *me_fw_data_obj;
 297         uint64_t                        me_fw_data_gpu_addr;
 298         uint32_t                        *me_fw_data_ptr;
 299
 300         uint32_t                        num_me;
 301         uint32_t                        num_pipe_per_me;
 302         uint32_t                        num_queue_per_pipe;
 303         void                            *mqd_backup[AMDGPU_MAX_GFX_RINGS];
 304
 305         /* These are the resources for which amdgpu takes ownership */
 306         DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 307 };
 308
 309 struct amdgpu_gfx {
 310         struct mutex                    gpu_clock_mutex;
 311         struct amdgpu_gfx_config        config;
 312         struct amdgpu_rlc               rlc;
 313         struct amdgpu_pfp               pfp;
 314         struct amdgpu_ce                ce;
 315         struct amdgpu_me                me;
 316         struct amdgpu_mec               mec;
 317         struct amdgpu_mec_bitmap        mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
 318         struct amdgpu_kiq               kiq[AMDGPU_MAX_GC_INSTANCES];
 319         struct amdgpu_imu               imu;
 320         bool                            rs64_enable; /* firmware format */
 321         const struct firmware           *me_fw; /* ME firmware */
 322         uint32_t                        me_fw_version;
 323         const struct firmware           *pfp_fw; /* PFP firmware */
 324         uint32_t                        pfp_fw_version;
 325         const struct firmware           *ce_fw; /* CE firmware */
 326         uint32_t                        ce_fw_version;
 327         const struct firmware           *rlc_fw; /* RLC firmware */
 328         uint32_t                        rlc_fw_version;
 329         const struct firmware           *mec_fw; /* MEC firmware */
 330         uint32_t                        mec_fw_version;
 331         const struct firmware           *mec2_fw; /* MEC2 firmware */
 332         uint32_t                        mec2_fw_version;
 333         const struct firmware           *imu_fw; /* IMU firmware */
 334         uint32_t                        imu_fw_version;
 335         uint32_t                        me_feature_version;
 336         uint32_t                        ce_feature_version;
 337         uint32_t                        pfp_feature_version;
 338         uint32_t                        rlc_feature_version;
 339         uint32_t                        rlc_srlc_fw_version;
 340         uint32_t                        rlc_srlc_feature_version;
 341         uint32_t                        rlc_srlg_fw_version;
 342         uint32_t                        rlc_srlg_feature_version;
 343         uint32_t                        rlc_srls_fw_version;
 344         uint32_t                        rlc_srls_feature_version;
 345         uint32_t                        rlcp_ucode_version;
 346         uint32_t                        rlcp_ucode_feature_version;
 347         uint32_t                        rlcv_ucode_version;
 348         uint32_t                        rlcv_ucode_feature_version;
 349         uint32_t                        mec_feature_version;
 350         uint32_t                        mec2_feature_version;
 351         bool                            mec_fw_write_wait;
 352         bool                            me_fw_write_wait;
 353         bool                            cp_fw_write_wait;
 354         struct amdgpu_ring              gfx_ring[AMDGPU_MAX_GFX_RINGS];
 355         unsigned                        num_gfx_rings;
 356         struct amdgpu_ring              compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
 357         unsigned                        num_compute_rings;
 358         struct amdgpu_irq_src           eop_irq;
 359         struct amdgpu_irq_src           priv_reg_irq;
 360         struct amdgpu_irq_src           priv_inst_irq;
 361         struct amdgpu_irq_src           cp_ecc_error_irq;
 362         struct amdgpu_irq_src           sq_irq;
 363         struct amdgpu_irq_src           rlc_gc_fed_irq;
 364         struct sq_work                  sq_work;
 365
 366         /* gfx status */
 367         uint32_t                        gfx_current_status;
 368         /* ce ram size*/
 369         unsigned                        ce_ram_size;
 370         struct amdgpu_cu_info           cu_info;
 371         const struct amdgpu_gfx_funcs   *funcs;
 372
 373         /* reset mask */
 374         uint32_t                        grbm_soft_reset;
 375         uint32_t                        srbm_soft_reset;
 376
 377         /* gfx off */
 378         bool                            gfx_off_state;      /* true: enabled, false: disabled */
 379         struct mutex                    gfx_off_mutex;      /* mutex to change gfxoff state */
 380         uint32_t                        gfx_off_req_count;  /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
 381         struct delayed_work             gfx_off_delay_work; /* async work to set gfx block off */
 382         uint32_t                        gfx_off_residency;  /* last logged residency */
 383         uint64_t                        gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */
 384
 385         /* pipe reservation */
 386         struct mutex                    pipe_reserve_mutex;
 387         DECLARE_BITMAP                  (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 388
 389         /*ras */
 390         struct ras_common_if            *ras_if;
 391         struct amdgpu_gfx_ras           *ras;
 392
 393         bool                            is_poweron;
 394
 395         struct amdgpu_ring              sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
 396         struct amdgpu_ring_mux          muxer;
 397
 398         bool                            cp_gfx_shadow; /* for gfx11 */
 399
 400         enum amdgpu_gfx_partition       partition_mode;
 401         uint16_t                        xcc_mask;
 402         uint32_t                        num_xcc_per_xcp;
 403         struct mutex                    partition_mutex;
 404 };
 405
 406 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
 407 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
 408 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
 409 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
 410 #define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))
 411
 412 /**
 413  * amdgpu_gfx_create_bitmask - create a bitmask
 414  *
 415  * @bit_width: length of the mask
 416  *
 417  * create a variable length bit mask.
 418  * Returns the bitmask.
 419  */
 420 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
 421 {
 422         return (u32)((1ULL << bit_width) - 1);
 423 }
 424
 425 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
 426                                  unsigned max_sh);
 427
 428 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 429                              struct amdgpu_ring *ring,
 430                              struct amdgpu_irq_src *irq, int xcc_id);
 431
 432 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
 433
 434 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
 435 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 436                         unsigned hpd_size, int xcc_id);
 437
 438 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 439                            unsigned mqd_size, int xcc_id);
 440 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id);
 441 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id);
 442 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
 443 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id);
 444 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id);
 445
 446 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
 447 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
 448
 449 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
 450                                 int pipe, int queue);
 451 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
 452                                  int *mec, int *pipe, int *queue);
 453 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
 454                                      int mec, int pipe, int queue);
 455 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 456                                                struct amdgpu_ring *ring);
 457 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 458                                                 struct amdgpu_ring *ring);
 459 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
 460                                int pipe, int queue);
 461 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
 462                                 int *me, int *pipe, int *queue);
 463 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
 464                                     int pipe, int queue);
 465 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
 466 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
 467 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 468 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
 469 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
 470 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
 471 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
 472 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 473                 void *err_data,
 474                 struct amdgpu_iv_entry *entry);
 475 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 476                                   struct amdgpu_irq_src *source,
 477                                   struct amdgpu_iv_entry *entry);
 478 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
 479 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
 480 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
 481 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
 482
 483 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev);
 484 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 485                                                 struct amdgpu_iv_entry *entry);
 486
 487 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
 488 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev);
 489 #endif