drivers/gpu/drm/rcar-du/rcar_lvds.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * rcar_lvds.c  --  R-Car LVDS Encoder
   4  *
   5  * Copyright (C) 2013-2018 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart ([email protected])
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/sys_soc.h>
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_bridge.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_probe_helper.h>
  26
  27 #include "rcar_lvds.h"
  28 #include "rcar_lvds_regs.h"
  29
  30 struct rcar_lvds;
  31
  32 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
  33 enum rcar_lvds_mode {
  34         RCAR_LVDS_MODE_JEIDA = 0,
  35         RCAR_LVDS_MODE_MIRROR = 1,
  36         RCAR_LVDS_MODE_VESA = 4,
  37 };
  38
  39 #define RCAR_LVDS_QUIRK_LANES           BIT(0)  /* LVDS lanes 1 and 3 inverted */
  40 #define RCAR_LVDS_QUIRK_GEN3_LVEN       BIT(1)  /* LVEN bit needs to be set on R8A77970/R8A7799x */
  41 #define RCAR_LVDS_QUIRK_PWD             BIT(2)  /* PWD bit available (all of Gen3 but E3) */
  42 #define RCAR_LVDS_QUIRK_EXT_PLL         BIT(3)  /* Has extended PLL */
  43 #define RCAR_LVDS_QUIRK_DUAL_LINK       BIT(4)  /* Supports dual-link operation */
  44
  45 struct rcar_lvds_device_info {
  46         unsigned int gen;
  47         unsigned int quirks;
  48         void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
  49 };
  50
  51 struct rcar_lvds {
  52         struct device *dev;
  53         const struct rcar_lvds_device_info *info;
  54
  55         struct drm_bridge bridge;
  56
  57         struct drm_bridge *next_bridge;
  58         struct drm_connector connector;
  59         struct drm_panel *panel;
  60
  61         void __iomem *mmio;
  62         struct {
  63                 struct clk *mod;                /* CPG module clock */
  64                 struct clk *extal;              /* External clock */
  65                 struct clk *dotclkin[2];        /* External DU clocks */
  66         } clocks;
  67
  68         struct drm_display_mode display_mode;
  69         enum rcar_lvds_mode mode;
  70
  71         struct drm_bridge *companion;
  72         bool dual_link;
  73 };
  74
  75 #define bridge_to_rcar_lvds(b) \
  76         container_of(b, struct rcar_lvds, bridge)
  77
  78 #define connector_to_rcar_lvds(c) \
  79         container_of(c, struct rcar_lvds, connector)
  80
  81 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
  82 {
  83         iowrite32(data, lvds->mmio + reg);
  84 }
  85
  86 /* -----------------------------------------------------------------------------
  87  * Connector & Panel
  88  */
  89
  90 static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
  91 {
  92         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
  93
  94         return drm_panel_get_modes(lvds->panel);
  95 }
  96
  97 static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
  98                                             struct drm_atomic_state *state)
  99 {
 100         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
 101         const struct drm_display_mode *panel_mode;
 102         struct drm_connector_state *conn_state;
 103         struct drm_crtc_state *crtc_state;
 104
 105         conn_state = drm_atomic_get_new_connector_state(state, connector);
 106         if (!conn_state->crtc)
 107                 return 0;
 108
 109         if (list_empty(&connector->modes)) {
 110                 dev_dbg(lvds->dev, "connector: empty modes list\n");
 111                 return -EINVAL;
 112         }
 113
 114         panel_mode = list_first_entry(&connector->modes,
 115                                       struct drm_display_mode, head);
 116
 117         /* We're not allowed to modify the resolution. */
 118         crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
 119         if (IS_ERR(crtc_state))
 120                 return PTR_ERR(crtc_state);
 121
 122         if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
 123             crtc_state->mode.vdisplay != panel_mode->vdisplay)
 124                 return -EINVAL;
 125
 126         /* The flat panel mode is fixed, just copy it to the adjusted mode. */
 127         drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
 128
 129         return 0;
 130 }
 131
 132 static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
 133         .get_modes = rcar_lvds_connector_get_modes,
 134         .atomic_check = rcar_lvds_connector_atomic_check,
 135 };
 136
 137 static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
 138         .reset = drm_atomic_helper_connector_reset,
 139         .fill_modes = drm_helper_probe_single_connector_modes,
 140         .destroy = drm_connector_cleanup,
 141         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 142         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 143 };
 144
 145 /* -----------------------------------------------------------------------------
 146  * PLL Setup
 147  */
 148
 149 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
 150 {
 151         u32 val;
 152
 153         if (freq < 39000000)
 154                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
 155         else if (freq < 61000000)
 156                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
 157         else if (freq < 121000000)
 158                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
 159         else
 160                 val = LVDPLLCR_PLLDLYCNT_150M;
 161
 162         rcar_lvds_write(lvds, LVDPLLCR, val);
 163 }
 164
 165 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
 166 {
 167         u32 val;
 168
 169         if (freq < 42000000)
 170                 val = LVDPLLCR_PLLDIVCNT_42M;
 171         else if (freq < 85000000)
 172                 val = LVDPLLCR_PLLDIVCNT_85M;
 173         else if (freq < 128000000)
 174                 val = LVDPLLCR_PLLDIVCNT_128M;
 175         else
 176                 val = LVDPLLCR_PLLDIVCNT_148M;
 177
 178         rcar_lvds_write(lvds, LVDPLLCR, val);
 179 }
 180
 181 struct pll_info {
 182         unsigned long diff;
 183         unsigned int pll_m;
 184         unsigned int pll_n;
 185         unsigned int pll_e;
 186         unsigned int div;
 187         u32 clksel;
 188 };
 189
 190 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
 191                                      unsigned long target, struct pll_info *pll,
 192                                      u32 clksel, bool dot_clock_only)
 193 {
 194         unsigned int div7 = dot_clock_only ? 1 : 7;
 195         unsigned long output;
 196         unsigned long fin;
 197         unsigned int m_min;
 198         unsigned int m_max;
 199         unsigned int m;
 200         int error;
 201
 202         if (!clk)
 203                 return;
 204
 205         /*
 206          * The LVDS PLL is made of a pre-divider and a multiplier (strangely
 207          * enough called M and N respectively), followed by a post-divider E.
 208          *
 209          *         ,-----.         ,-----.     ,-----.         ,-----.
 210          * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
 211          *         `-----'     ,-> |     |     `-----'   |     `-----'
 212          *                     |   `-----'               |
 213          *                     |         ,-----.         |
 214          *                     `-------- | 1/N | <-------'
 215          *                               `-----'
 216          *
 217          * The clock output by the PLL is then further divided by a programmable
 218          * divider DIV to achieve the desired target frequency. Finally, an
 219          * optional fixed /7 divider is used to convert the bit clock to a pixel
 220          * clock (as LVDS transmits 7 bits per lane per clock sample).
 221          *
 222          *          ,-------.     ,-----.     |\
 223          * Fout --> | 1/DIV | --> | 1/7 | --> | |
 224          *          `-------'  |  `-----'     | | --> dot clock
 225          *                     `------------> | |
 226          *                                    |/
 227          *
 228          * The /7 divider is optional, it is enabled when the LVDS PLL is used
 229          * to drive the LVDS encoder, and disabled when  used to generate a dot
 230          * clock for the DU RGB output, without using the LVDS encoder.
 231          *
 232          * The PLL allowed input frequency range is 12 MHz to 192 MHz.
 233          */
 234
 235         fin = clk_get_rate(clk);
 236         if (fin < 12000000 || fin > 192000000)
 237                 return;
 238
 239         /*
 240          * The comparison frequency range is 12 MHz to 24 MHz, which limits the
 241          * allowed values for the pre-divider M (normal range 1-8).
 242          *
 243          * Fpfd = Fin / M
 244          */
 245         m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
 246         m_max = min_t(unsigned int, 8, fin / 12000000);
 247
 248         for (m = m_min; m <= m_max; ++m) {
 249                 unsigned long fpfd;
 250                 unsigned int n_min;
 251                 unsigned int n_max;
 252                 unsigned int n;
 253
 254                 /*
 255                  * The VCO operating range is 900 Mhz to 1800 MHz, which limits
 256                  * the allowed values for the multiplier N (normal range
 257                  * 60-120).
 258                  *
 259                  * Fvco = Fin * N / M
 260                  */
 261                 fpfd = fin / m;
 262                 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
 263                 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
 264
 265                 for (n = n_min; n < n_max; ++n) {
 266                         unsigned long fvco;
 267                         unsigned int e_min;
 268                         unsigned int e;
 269
 270                         /*
 271                          * The output frequency is limited to 1039.5 MHz,
 272                          * limiting again the allowed values for the
 273                          * post-divider E (normal value 1, 2 or 4).
 274                          *
 275                          * Fout = Fvco / E
 276                          */
 277                         fvco = fpfd * n;
 278                         e_min = fvco > 1039500000 ? 1 : 0;
 279
 280                         for (e = e_min; e < 3; ++e) {
 281                                 unsigned long fout;
 282                                 unsigned long diff;
 283                                 unsigned int div;
 284
 285                                 /*
 286                                  * Finally we have a programable divider after
 287                                  * the PLL, followed by a an optional fixed /7
 288                                  * divider.
 289                                  */
 290                                 fout = fvco / (1 << e) / div7;
 291                                 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
 292                                 diff = abs(fout / div - target);
 293
 294                                 if (diff < pll->diff) {
 295                                         pll->diff = diff;
 296                                         pll->pll_m = m;
 297                                         pll->pll_n = n;
 298                                         pll->pll_e = e;
 299                                         pll->div = div;
 300                                         pll->clksel = clksel;
 301
 302                                         if (diff == 0)
 303                                                 goto done;
 304                                 }
 305                         }
 306                 }
 307         }
 308
 309 done:
 310         output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
 311                / div7 / pll->div;
 312         error = (long)(output - target) * 10000 / (long)target;
 313
 314         dev_dbg(lvds->dev,
 315                 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
 316                 clk, fin, output, target, error / 100,
 317                 error < 0 ? -error % 100 : error % 100,
 318                 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
 319 }
 320
 321 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
 322                                         unsigned int freq, bool dot_clock_only)
 323 {
 324         struct pll_info pll = { .diff = (unsigned long)-1 };
 325         u32 lvdpllcr;
 326
 327         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
 328                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
 329         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
 330                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
 331         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
 332                                  LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
 333
 334         lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
 335                  | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
 336
 337         if (pll.pll_e > 0)
 338                 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
 339                          |  LVDPLLCR_PLLE(pll.pll_e - 1);
 340
 341         if (dot_clock_only)
 342                 lvdpllcr |= LVDPLLCR_OCKSEL;
 343
 344         rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
 345
 346         if (pll.div > 1)
 347                 /*
 348                  * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
 349                  * divisor reset.
 350                  */
 351                 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
 352                                 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
 353         else
 354                 rcar_lvds_write(lvds, LVDDIV, 0);
 355 }
 356
 357 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
 358 {
 359         __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
 360 }
 361
 362 /* -----------------------------------------------------------------------------
 363  * Clock - D3/E3 only
 364  */
 365
 366 int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
 367 {
 368         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 369         int ret;
 370
 371         if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
 372                 return -ENODEV;
 373
 374         dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
 375
 376         ret = clk_prepare_enable(lvds->clocks.mod);
 377         if (ret < 0)
 378                 return ret;
 379
 380         __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
 381
 382         return 0;
 383 }
 384 EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
 385
 386 void rcar_lvds_clk_disable(struct drm_bridge *bridge)
 387 {
 388         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 389
 390         if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
 391                 return;
 392
 393         dev_dbg(lvds->dev, "disabling LVDS PLL\n");
 394
 395         rcar_lvds_write(lvds, LVDPLLCR, 0);
 396
 397         clk_disable_unprepare(lvds->clocks.mod);
 398 }
 399 EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
 400
 401 /* -----------------------------------------------------------------------------
 402  * Bridge
 403  */
 404
 405 static void rcar_lvds_enable(struct drm_bridge *bridge)
 406 {
 407         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 408         const struct drm_display_mode *mode = &lvds->display_mode;
 409         u32 lvdhcr;
 410         u32 lvdcr0;
 411         int ret;
 412
 413         ret = clk_prepare_enable(lvds->clocks.mod);
 414         if (ret < 0)
 415                 return;
 416
 417         /* Enable the companion LVDS encoder in dual-link mode. */
 418         if (lvds->dual_link && lvds->companion)
 419                 lvds->companion->funcs->enable(lvds->companion);
 420
 421         /*
 422          * Hardcode the channels and control signals routing for now.
 423          *
 424          * HSYNC -> CTRL0
 425          * VSYNC -> CTRL1
 426          * DISP  -> CTRL2
 427          * 0     -> CTRL3
 428          */
 429         rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
 430                         LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
 431                         LVDCTRCR_CTR0SEL_HSYNC);
 432
 433         if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
 434                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
 435                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
 436         else
 437                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
 438                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
 439
 440         rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
 441
 442         if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
 443                 /*
 444                  * Configure vertical stripe based on the mode of operation of
 445                  * the connected device.
 446                  */
 447                 rcar_lvds_write(lvds, LVDSTRIPE,
 448                                 lvds->dual_link ? LVDSTRIPE_ST_ON : 0);
 449         }
 450
 451         /*
 452          * PLL clock configuration on all instances but the companion in
 453          * dual-link mode.
 454          */
 455         if (!lvds->dual_link || lvds->companion)
 456                 lvds->info->pll_setup(lvds, mode->clock * 1000);
 457
 458         /* Set the LVDS mode and select the input. */
 459         lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
 460
 461         if (lvds->bridge.encoder) {
 462                 /*
 463                  * FIXME: We should really retrieve the CRTC through the state,
 464                  * but how do we get a state pointer?
 465                  */
 466                 if (drm_crtc_index(lvds->bridge.encoder->crtc) == 2)
 467                         lvdcr0 |= LVDCR0_DUSEL;
 468         }
 469
 470         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 471
 472         /* Turn all the channels on. */
 473         rcar_lvds_write(lvds, LVDCR1,
 474                         LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
 475                         LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
 476
 477         if (lvds->info->gen < 3) {
 478                 /* Enable LVDS operation and turn the bias circuitry on. */
 479                 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
 480                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 481         }
 482
 483         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 484                 /*
 485                  * Turn the PLL on (simple PLL only, extended PLL is fully
 486                  * controlled through LVDPLLCR).
 487                  */
 488                 lvdcr0 |= LVDCR0_PLLON;
 489                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 490         }
 491
 492         if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
 493                 /* Set LVDS normal mode. */
 494                 lvdcr0 |= LVDCR0_PWD;
 495                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 496         }
 497
 498         if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
 499                 /*
 500                  * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
 501                  * set at the same time, so don't write the register yet.
 502                  */
 503                 lvdcr0 |= LVDCR0_LVEN;
 504                 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
 505                         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 506         }
 507
 508         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 509                 /* Wait for the PLL startup delay (simple PLL only). */
 510                 usleep_range(100, 150);
 511         }
 512
 513         /* Turn the output on. */
 514         lvdcr0 |= LVDCR0_LVRES;
 515         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 516
 517         if (lvds->panel) {
 518                 drm_panel_prepare(lvds->panel);
 519                 drm_panel_enable(lvds->panel);
 520         }
 521 }
 522
 523 static void rcar_lvds_disable(struct drm_bridge *bridge)
 524 {
 525         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 526
 527         if (lvds->panel) {
 528                 drm_panel_disable(lvds->panel);
 529                 drm_panel_unprepare(lvds->panel);
 530         }
 531
 532         rcar_lvds_write(lvds, LVDCR0, 0);
 533         rcar_lvds_write(lvds, LVDCR1, 0);
 534         rcar_lvds_write(lvds, LVDPLLCR, 0);
 535
 536         /* Disable the companion LVDS encoder in dual-link mode. */
 537         if (lvds->dual_link && lvds->companion)
 538                 lvds->companion->funcs->disable(lvds->companion);
 539
 540         clk_disable_unprepare(lvds->clocks.mod);
 541 }
 542
 543 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
 544                                  const struct drm_display_mode *mode,
 545                                  struct drm_display_mode *adjusted_mode)
 546 {
 547         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 548         int min_freq;
 549
 550         /*
 551          * The internal LVDS encoder has a restricted clock frequency operating
 552          * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
 553          * 148.5MHz on all other platforms. Clamp the clock accordingly.
 554          */
 555         min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
 556         adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
 557
 558         return true;
 559 }
 560
 561 static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
 562 {
 563         struct drm_display_info *info = &lvds->connector.display_info;
 564         enum rcar_lvds_mode mode;
 565
 566         /*
 567          * There is no API yet to retrieve LVDS mode from a bridge, only panels
 568          * are supported.
 569          */
 570         if (!lvds->panel)
 571                 return;
 572
 573         if (!info->num_bus_formats || !info->bus_formats) {
 574                 dev_err(lvds->dev, "no LVDS bus format reported\n");
 575                 return;
 576         }
 577
 578         switch (info->bus_formats[0]) {
 579         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 580         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 581                 mode = RCAR_LVDS_MODE_JEIDA;
 582                 break;
 583         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 584                 mode = RCAR_LVDS_MODE_VESA;
 585                 break;
 586         default:
 587                 dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
 588                         info->bus_formats[0]);
 589                 return;
 590         }
 591
 592         if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
 593                 mode |= RCAR_LVDS_MODE_MIRROR;
 594
 595         lvds->mode = mode;
 596 }
 597
 598 static void rcar_lvds_mode_set(struct drm_bridge *bridge,
 599                                const struct drm_display_mode *mode,
 600                                const struct drm_display_mode *adjusted_mode)
 601 {
 602         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 603
 604         lvds->display_mode = *adjusted_mode;
 605
 606         rcar_lvds_get_lvds_mode(lvds);
 607 }
 608
 609 static int rcar_lvds_attach(struct drm_bridge *bridge)
 610 {
 611         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 612         struct drm_connector *connector = &lvds->connector;
 613         struct drm_encoder *encoder = bridge->encoder;
 614         int ret;
 615
 616         /* If we have a next bridge just attach it. */
 617         if (lvds->next_bridge)
 618                 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
 619                                          bridge);
 620
 621         /* Otherwise if we have a panel, create a connector. */
 622         if (!lvds->panel)
 623                 return 0;
 624
 625         ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
 626                                  DRM_MODE_CONNECTOR_LVDS);
 627         if (ret < 0)
 628                 return ret;
 629
 630         drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
 631
 632         ret = drm_connector_attach_encoder(connector, encoder);
 633         if (ret < 0)
 634                 return ret;
 635
 636         return drm_panel_attach(lvds->panel, connector);
 637 }
 638
 639 static void rcar_lvds_detach(struct drm_bridge *bridge)
 640 {
 641         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 642
 643         if (lvds->panel)
 644                 drm_panel_detach(lvds->panel);
 645 }
 646
 647 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
 648         .attach = rcar_lvds_attach,
 649         .detach = rcar_lvds_detach,
 650         .enable = rcar_lvds_enable,
 651         .disable = rcar_lvds_disable,
 652         .mode_fixup = rcar_lvds_mode_fixup,
 653         .mode_set = rcar_lvds_mode_set,
 654 };
 655
 656 bool rcar_lvds_dual_link(struct drm_bridge *bridge)
 657 {
 658         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 659
 660         return lvds->dual_link;
 661 }
 662 EXPORT_SYMBOL_GPL(rcar_lvds_dual_link);
 663
 664 /* -----------------------------------------------------------------------------
 665  * Probe & Remove
 666  */
 667
 668 static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
 669 {
 670         const struct of_device_id *match;
 671         struct device_node *companion;
 672         struct device *dev = lvds->dev;
 673         int ret = 0;
 674
 675         /* Locate the companion LVDS encoder for dual-link operation, if any. */
 676         companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
 677         if (!companion)
 678                 return 0;
 679
 680         /*
 681          * Sanity check: the companion encoder must have the same compatible
 682          * string.
 683          */
 684         match = of_match_device(dev->driver->of_match_table, dev);
 685         if (!of_device_is_compatible(companion, match->compatible)) {
 686                 dev_err(dev, "Companion LVDS encoder is invalid\n");
 687                 ret = -ENXIO;
 688                 goto done;
 689         }
 690
 691         lvds->companion = of_drm_find_bridge(companion);
 692         if (!lvds->companion) {
 693                 ret = -EPROBE_DEFER;
 694                 goto done;
 695         }
 696
 697         dev_dbg(dev, "Found companion encoder %pOF\n", companion);
 698
 699 done:
 700         of_node_put(companion);
 701
 702         return ret;
 703 }
 704
 705 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
 706 {
 707         struct device_node *local_output = NULL;
 708         struct device_node *remote_input = NULL;
 709         struct device_node *remote = NULL;
 710         struct device_node *node;
 711         bool is_bridge = false;
 712         int ret = 0;
 713
 714         local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
 715         if (!local_output) {
 716                 dev_dbg(lvds->dev, "unconnected port@1\n");
 717                 ret = -ENODEV;
 718                 goto done;
 719         }
 720
 721         /*
 722          * Locate the connected entity and infer its type from the number of
 723          * endpoints.
 724          */
 725         remote = of_graph_get_remote_port_parent(local_output);
 726         if (!remote) {
 727                 dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
 728                 ret = -ENODEV;
 729                 goto done;
 730         }
 731
 732         if (!of_device_is_available(remote)) {
 733                 dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
 734                         remote);
 735                 ret = -ENODEV;
 736                 goto done;
 737         }
 738
 739         remote_input = of_graph_get_remote_endpoint(local_output);
 740
 741         for_each_endpoint_of_node(remote, node) {
 742                 if (node != remote_input) {
 743                         /*
 744                          * We've found one endpoint other than the input, this
 745                          * must be a bridge.
 746                          */
 747                         is_bridge = true;
 748                         of_node_put(node);
 749                         break;
 750                 }
 751         }
 752
 753         if (is_bridge) {
 754                 lvds->next_bridge = of_drm_find_bridge(remote);
 755                 if (!lvds->next_bridge) {
 756                         ret = -EPROBE_DEFER;
 757                         goto done;
 758                 }
 759
 760                 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
 761                         lvds->dual_link = lvds->next_bridge->timings
 762                                         ? lvds->next_bridge->timings->dual_link
 763                                         : false;
 764         } else {
 765                 lvds->panel = of_drm_find_panel(remote);
 766                 if (IS_ERR(lvds->panel)) {
 767                         ret = PTR_ERR(lvds->panel);
 768                         goto done;
 769                 }
 770         }
 771
 772         if (lvds->dual_link)
 773                 ret = rcar_lvds_parse_dt_companion(lvds);
 774
 775 done:
 776         of_node_put(local_output);
 777         of_node_put(remote_input);
 778         of_node_put(remote);
 779
 780         /*
 781          * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
 782          * used for the DPAD output even when the LVDS output is not connected.
 783          * Don't fail probe in that case as the DU will need the bridge to
 784          * control the clock.
 785          */
 786         if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
 787                 return ret == -ENODEV ? 0 : ret;
 788
 789         return ret;
 790 }
 791
 792 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
 793                                        bool optional)
 794 {
 795         struct clk *clk;
 796
 797         clk = devm_clk_get(lvds->dev, name);
 798         if (!IS_ERR(clk))
 799                 return clk;
 800
 801         if (PTR_ERR(clk) == -ENOENT && optional)
 802                 return NULL;
 803
 804         if (PTR_ERR(clk) != -EPROBE_DEFER)
 805                 dev_err(lvds->dev, "failed to get %s clock\n",
 806                         name ? name : "module");
 807
 808         return clk;
 809 }
 810
 811 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
 812 {
 813         lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
 814         if (IS_ERR(lvds->clocks.mod))
 815                 return PTR_ERR(lvds->clocks.mod);
 816
 817         /*
 818          * LVDS encoders without an extended PLL have no external clock inputs.
 819          */
 820         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
 821                 return 0;
 822
 823         lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
 824         if (IS_ERR(lvds->clocks.extal))
 825                 return PTR_ERR(lvds->clocks.extal);
 826
 827         lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
 828         if (IS_ERR(lvds->clocks.dotclkin[0]))
 829                 return PTR_ERR(lvds->clocks.dotclkin[0]);
 830
 831         lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
 832         if (IS_ERR(lvds->clocks.dotclkin[1]))
 833                 return PTR_ERR(lvds->clocks.dotclkin[1]);
 834
 835         /* At least one input to the PLL must be available. */
 836         if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
 837             !lvds->clocks.dotclkin[1]) {
 838                 dev_err(lvds->dev,
 839                         "no input clock (extal, dclkin.0 or dclkin.1)\n");
 840                 return -EINVAL;
 841         }
 842
 843         return 0;
 844 }
 845
 846 static const struct rcar_lvds_device_info rcar_lvds_r8a7790es1_info = {
 847         .gen = 2,
 848         .quirks = RCAR_LVDS_QUIRK_LANES,
 849         .pll_setup = rcar_lvds_pll_setup_gen2,
 850 };
 851
 852 static const struct soc_device_attribute lvds_quirk_matches[] = {
 853         {
 854                 .soc_id = "r8a7790", .revision = "ES1.*",
 855                 .data = &rcar_lvds_r8a7790es1_info,
 856         },
 857         { /* sentinel */ }
 858 };
 859
 860 static int rcar_lvds_probe(struct platform_device *pdev)
 861 {
 862         const struct soc_device_attribute *attr;
 863         struct rcar_lvds *lvds;
 864         struct resource *mem;
 865         int ret;
 866
 867         lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
 868         if (lvds == NULL)
 869                 return -ENOMEM;
 870
 871         platform_set_drvdata(pdev, lvds);
 872
 873         lvds->dev = &pdev->dev;
 874         lvds->info = of_device_get_match_data(&pdev->dev);
 875
 876         attr = soc_device_match(lvds_quirk_matches);
 877         if (attr)
 878                 lvds->info = attr->data;
 879
 880         ret = rcar_lvds_parse_dt(lvds);
 881         if (ret < 0)
 882                 return ret;
 883
 884         lvds->bridge.driver_private = lvds;
 885         lvds->bridge.funcs = &rcar_lvds_bridge_ops;
 886         lvds->bridge.of_node = pdev->dev.of_node;
 887
 888         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 889         lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
 890         if (IS_ERR(lvds->mmio))
 891                 return PTR_ERR(lvds->mmio);
 892
 893         ret = rcar_lvds_get_clocks(lvds);
 894         if (ret < 0)
 895                 return ret;
 896
 897         drm_bridge_add(&lvds->bridge);
 898
 899         return 0;
 900 }
 901
 902 static int rcar_lvds_remove(struct platform_device *pdev)
 903 {
 904         struct rcar_lvds *lvds = platform_get_drvdata(pdev);
 905
 906         drm_bridge_remove(&lvds->bridge);
 907
 908         return 0;
 909 }
 910
 911 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
 912         .gen = 2,
 913         .pll_setup = rcar_lvds_pll_setup_gen2,
 914 };
 915
 916 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
 917         .gen = 3,
 918         .quirks = RCAR_LVDS_QUIRK_PWD,
 919         .pll_setup = rcar_lvds_pll_setup_gen3,
 920 };
 921
 922 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
 923         .gen = 3,
 924         .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
 925         .pll_setup = rcar_lvds_pll_setup_gen2,
 926 };
 927
 928 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
 929         .gen = 3,
 930         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
 931                 | RCAR_LVDS_QUIRK_DUAL_LINK,
 932         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 933 };
 934
 935 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
 936         .gen = 3,
 937         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
 938                 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
 939         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 940 };
 941
 942 static const struct of_device_id rcar_lvds_of_table[] = {
 943         { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
 944         { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
 945         { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
 946         { .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info },
 947         { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
 948         { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info },
 949         { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
 950         { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
 951         { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
 952         { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
 953         { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
 954         { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
 955         { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
 956         { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
 957         { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
 958         { }
 959 };
 960
 961 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
 962
 963 static struct platform_driver rcar_lvds_platform_driver = {
 964         .probe          = rcar_lvds_probe,
 965         .remove         = rcar_lvds_remove,
 966         .driver         = {
 967                 .name   = "rcar-lvds",
 968                 .of_match_table = rcar_lvds_of_table,
 969         },
 970 };
 971
 972 module_platform_driver(rcar_lvds_platform_driver);
 973
 974 MODULE_AUTHOR("Laurent Pinchart <[email protected]>");
 975 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
 976 MODULE_LICENSE("GPL");