drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "hdp/hdp_4_0_sh_mask.h"
  36 #include "gc/gc_9_0_sh_mask.h"
  37 #include "dce/dce_12_0_offset.h"
  38 #include "dce/dce_12_0_sh_mask.h"
  39 #include "vega10_enum.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "athub/athub_1_0_offset.h"
  42 #include "oss/osssys_4_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "mmhub_v9_4.h"
  53 #include "umc_v6_1.h"
  54 #include "umc_v6_0.h"
  55
  56 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  57
  58 #include "amdgpu_ras.h"
  59 #include "amdgpu_xgmi.h"
  60
  61 /* add these here since we already include dce12 headers and these are for DCN */
  62 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  63 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  68
  69 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
  70 #define AMDGPU_NUM_OF_VMIDS                     8
  71
  72 static const u32 golden_settings_vega10_hdp[] =
  73 {
  74         0xf64, 0x0fffffff, 0x00000000,
  75         0xf65, 0x0fffffff, 0x00000000,
  76         0xf66, 0x0fffffff, 0x00000000,
  77         0xf67, 0x0fffffff, 0x00000000,
  78         0xf68, 0x0fffffff, 0x00000000,
  79         0xf6a, 0x0fffffff, 0x00000000,
  80         0xf6b, 0x0fffffff, 0x00000000,
  81         0xf6c, 0x0fffffff, 0x00000000,
  82         0xf6d, 0x0fffffff, 0x00000000,
  83         0xf6e, 0x0fffffff, 0x00000000,
  84 };
  85
  86 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
  87 {
  88         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
  89         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
  90 };
  91
  92 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
  93 {
  94         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
  95         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
  96 };
  97
  98 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
  99         (0x000143c0 + 0x00000000),
 100         (0x000143c0 + 0x00000800),
 101         (0x000143c0 + 0x00001000),
 102         (0x000143c0 + 0x00001800),
 103         (0x000543c0 + 0x00000000),
 104         (0x000543c0 + 0x00000800),
 105         (0x000543c0 + 0x00001000),
 106         (0x000543c0 + 0x00001800),
 107         (0x000943c0 + 0x00000000),
 108         (0x000943c0 + 0x00000800),
 109         (0x000943c0 + 0x00001000),
 110         (0x000943c0 + 0x00001800),
 111         (0x000d43c0 + 0x00000000),
 112         (0x000d43c0 + 0x00000800),
 113         (0x000d43c0 + 0x00001000),
 114         (0x000d43c0 + 0x00001800),
 115         (0x001143c0 + 0x00000000),
 116         (0x001143c0 + 0x00000800),
 117         (0x001143c0 + 0x00001000),
 118         (0x001143c0 + 0x00001800),
 119         (0x001543c0 + 0x00000000),
 120         (0x001543c0 + 0x00000800),
 121         (0x001543c0 + 0x00001000),
 122         (0x001543c0 + 0x00001800),
 123         (0x001943c0 + 0x00000000),
 124         (0x001943c0 + 0x00000800),
 125         (0x001943c0 + 0x00001000),
 126         (0x001943c0 + 0x00001800),
 127         (0x001d43c0 + 0x00000000),
 128         (0x001d43c0 + 0x00000800),
 129         (0x001d43c0 + 0x00001000),
 130         (0x001d43c0 + 0x00001800),
 131 };
 132
 133 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 134         (0x000143e0 + 0x00000000),
 135         (0x000143e0 + 0x00000800),
 136         (0x000143e0 + 0x00001000),
 137         (0x000143e0 + 0x00001800),
 138         (0x000543e0 + 0x00000000),
 139         (0x000543e0 + 0x00000800),
 140         (0x000543e0 + 0x00001000),
 141         (0x000543e0 + 0x00001800),
 142         (0x000943e0 + 0x00000000),
 143         (0x000943e0 + 0x00000800),
 144         (0x000943e0 + 0x00001000),
 145         (0x000943e0 + 0x00001800),
 146         (0x000d43e0 + 0x00000000),
 147         (0x000d43e0 + 0x00000800),
 148         (0x000d43e0 + 0x00001000),
 149         (0x000d43e0 + 0x00001800),
 150         (0x001143e0 + 0x00000000),
 151         (0x001143e0 + 0x00000800),
 152         (0x001143e0 + 0x00001000),
 153         (0x001143e0 + 0x00001800),
 154         (0x001543e0 + 0x00000000),
 155         (0x001543e0 + 0x00000800),
 156         (0x001543e0 + 0x00001000),
 157         (0x001543e0 + 0x00001800),
 158         (0x001943e0 + 0x00000000),
 159         (0x001943e0 + 0x00000800),
 160         (0x001943e0 + 0x00001000),
 161         (0x001943e0 + 0x00001800),
 162         (0x001d43e0 + 0x00000000),
 163         (0x001d43e0 + 0x00000800),
 164         (0x001d43e0 + 0x00001000),
 165         (0x001d43e0 + 0x00001800),
 166 };
 167
 168 static const uint32_t ecc_umc_mcumc_status_addrs[] = {
 169         (0x000143c2 + 0x00000000),
 170         (0x000143c2 + 0x00000800),
 171         (0x000143c2 + 0x00001000),
 172         (0x000143c2 + 0x00001800),
 173         (0x000543c2 + 0x00000000),
 174         (0x000543c2 + 0x00000800),
 175         (0x000543c2 + 0x00001000),
 176         (0x000543c2 + 0x00001800),
 177         (0x000943c2 + 0x00000000),
 178         (0x000943c2 + 0x00000800),
 179         (0x000943c2 + 0x00001000),
 180         (0x000943c2 + 0x00001800),
 181         (0x000d43c2 + 0x00000000),
 182         (0x000d43c2 + 0x00000800),
 183         (0x000d43c2 + 0x00001000),
 184         (0x000d43c2 + 0x00001800),
 185         (0x001143c2 + 0x00000000),
 186         (0x001143c2 + 0x00000800),
 187         (0x001143c2 + 0x00001000),
 188         (0x001143c2 + 0x00001800),
 189         (0x001543c2 + 0x00000000),
 190         (0x001543c2 + 0x00000800),
 191         (0x001543c2 + 0x00001000),
 192         (0x001543c2 + 0x00001800),
 193         (0x001943c2 + 0x00000000),
 194         (0x001943c2 + 0x00000800),
 195         (0x001943c2 + 0x00001000),
 196         (0x001943c2 + 0x00001800),
 197         (0x001d43c2 + 0x00000000),
 198         (0x001d43c2 + 0x00000800),
 199         (0x001d43c2 + 0x00001000),
 200         (0x001d43c2 + 0x00001800),
 201 };
 202
 203 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 204                 struct amdgpu_irq_src *src,
 205                 unsigned type,
 206                 enum amdgpu_interrupt_state state)
 207 {
 208         u32 bits, i, tmp, reg;
 209
 210         bits = 0x7f;
 211
 212         switch (state) {
 213         case AMDGPU_IRQ_STATE_DISABLE:
 214                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 215                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 216                         tmp = RREG32(reg);
 217                         tmp &= ~bits;
 218                         WREG32(reg, tmp);
 219                 }
 220                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 221                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 222                         tmp = RREG32(reg);
 223                         tmp &= ~bits;
 224                         WREG32(reg, tmp);
 225                 }
 226                 break;
 227         case AMDGPU_IRQ_STATE_ENABLE:
 228                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 229                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 230                         tmp = RREG32(reg);
 231                         tmp |= bits;
 232                         WREG32(reg, tmp);
 233                 }
 234                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 235                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 236                         tmp = RREG32(reg);
 237                         tmp |= bits;
 238                         WREG32(reg, tmp);
 239                 }
 240                 break;
 241         default:
 242                 break;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 249                                         struct amdgpu_irq_src *src,
 250                                         unsigned type,
 251                                         enum amdgpu_interrupt_state state)
 252 {
 253         struct amdgpu_vmhub *hub;
 254         u32 tmp, reg, bits, i, j;
 255
 256         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 257                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 258                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 259                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 260                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 261                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 262                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 263
 264         switch (state) {
 265         case AMDGPU_IRQ_STATE_DISABLE:
 266                 for (j = 0; j < adev->num_vmhubs; j++) {
 267                         hub = &adev->vmhub[j];
 268                         for (i = 0; i < 16; i++) {
 269                                 reg = hub->vm_context0_cntl + i;
 270                                 tmp = RREG32(reg);
 271                                 tmp &= ~bits;
 272                                 WREG32(reg, tmp);
 273                         }
 274                 }
 275                 break;
 276         case AMDGPU_IRQ_STATE_ENABLE:
 277                 for (j = 0; j < adev->num_vmhubs; j++) {
 278                         hub = &adev->vmhub[j];
 279                         for (i = 0; i < 16; i++) {
 280                                 reg = hub->vm_context0_cntl + i;
 281                                 tmp = RREG32(reg);
 282                                 tmp |= bits;
 283                                 WREG32(reg, tmp);
 284                         }
 285                 }
 286         default:
 287                 break;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 294                                 struct amdgpu_irq_src *source,
 295                                 struct amdgpu_iv_entry *entry)
 296 {
 297         struct amdgpu_vmhub *hub;
 298         bool retry_fault = !!(entry->src_data[1] & 0x80);
 299         uint32_t status = 0;
 300         u64 addr;
 301         char hub_name[10];
 302
 303         addr = (u64)entry->src_data[0] << 12;
 304         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 305
 306         if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 307                                                     entry->timestamp))
 308                 return 1; /* This also prevents sending it to KFD */
 309
 310         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 311                 snprintf(hub_name, sizeof(hub_name), "mmhub0");
 312                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 313         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 314                 snprintf(hub_name, sizeof(hub_name), "mmhub1");
 315                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 316         } else {
 317                 snprintf(hub_name, sizeof(hub_name), "gfxhub0");
 318                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 319         }
 320
 321         /* If it's the first fault for this address, process it normally */
 322         if (retry_fault && !in_interrupt() &&
 323             amdgpu_vm_handle_fault(adev, entry->pasid, addr))
 324                 return 1; /* This also prevents sending it to KFD */
 325
 326         if (!amdgpu_sriov_vf(adev)) {
 327                 /*
 328                  * Issue a dummy read to wait for the status register to
 329                  * be updated to avoid reading an incorrect value due to
 330                  * the new fast GRBM interface.
 331                  */
 332                 if (entry->vmid_src == AMDGPU_GFXHUB_0)
 333                         RREG32(hub->vm_l2_pro_fault_status);
 334
 335                 status = RREG32(hub->vm_l2_pro_fault_status);
 336                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 337         }
 338
 339         if (printk_ratelimit()) {
 340                 struct amdgpu_task_info task_info;
 341
 342                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 343                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 344
 345                 dev_err(adev->dev,
 346                         "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 347                         "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 348                         hub_name, retry_fault ? "retry" : "no-retry",
 349                         entry->src_id, entry->ring_id, entry->vmid,
 350                         entry->pasid, task_info.process_name, task_info.tgid,
 351                         task_info.task_name, task_info.pid);
 352                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 353                         addr, entry->client_id);
 354                 if (!amdgpu_sriov_vf(adev)) {
 355                         dev_err(adev->dev,
 356                                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 357                                 status);
 358                         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 359                                 REG_GET_FIELD(status,
 360                                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 361                         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 362                                 REG_GET_FIELD(status,
 363                                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 364                         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 365                                 REG_GET_FIELD(status,
 366                                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 367                         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 368                                 REG_GET_FIELD(status,
 369                                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 370                         dev_err(adev->dev, "\t RW: 0x%lx\n",
 371                                 REG_GET_FIELD(status,
 372                                 VM_L2_PROTECTION_FAULT_STATUS, RW));
 373
 374                 }
 375         }
 376
 377         return 0;
 378 }
 379
 380 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 381         .set = gmc_v9_0_vm_fault_interrupt_state,
 382         .process = gmc_v9_0_process_interrupt,
 383 };
 384
 385
 386 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 387         .set = gmc_v9_0_ecc_interrupt_state,
 388         .process = amdgpu_umc_process_ecc_irq,
 389 };
 390
 391 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 392 {
 393         adev->gmc.vm_fault.num_types = 1;
 394         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 395
 396         adev->gmc.ecc_irq.num_types = 1;
 397         adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 398 }
 399
 400 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 401                                         uint32_t flush_type)
 402 {
 403         u32 req = 0;
 404
 405         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 406                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 407         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 408         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 409         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 410         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 411         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 412         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 413         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 414                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 415
 416         return req;
 417 }
 418
 419 /*
 420  * GART
 421  * VMID 0 is the physical GPU addresses as used by the kernel.
 422  * VMIDs 1-15 are used for userspace clients and are handled
 423  * by the amdgpu vm/hsa code.
 424  */
 425
 426 /**
 427  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 428  *
 429  * @adev: amdgpu_device pointer
 430  * @vmid: vm instance to flush
 431  * @flush_type: the flush type
 432  *
 433  * Flush the TLB for the requested page table using certain type.
 434  */
 435 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 436                                         uint32_t vmhub, uint32_t flush_type)
 437 {
 438         const unsigned eng = 17;
 439         u32 j, tmp;
 440         struct amdgpu_vmhub *hub;
 441
 442         BUG_ON(vmhub >= adev->num_vmhubs);
 443
 444         hub = &adev->vmhub[vmhub];
 445         tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 446
 447         /* This is necessary for a HW workaround under SRIOV as well
 448          * as GFXOFF under bare metal
 449          */
 450         if (adev->gfx.kiq.ring.sched.ready &&
 451                         (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 452                         !adev->in_gpu_reset) {
 453                 uint32_t req = hub->vm_inv_eng0_req + eng;
 454                 uint32_t ack = hub->vm_inv_eng0_ack + eng;
 455
 456                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
 457                                 1 << vmid);
 458                 return;
 459         }
 460
 461         spin_lock(&adev->gmc.invalidate_lock);
 462
 463         /*
 464          * It may lose gpuvm invalidate acknowldege state across power-gating
 465          * off cycle, add semaphore acquire before invalidation and semaphore
 466          * release after invalidation to avoid entering power gated state
 467          * to WA the Issue
 468          */
 469
 470         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 471         if (vmhub == AMDGPU_MMHUB_0 ||
 472             vmhub == AMDGPU_MMHUB_1) {
 473                 for (j = 0; j < adev->usec_timeout; j++) {
 474                         /* a read return value of 1 means semaphore acuqire */
 475                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
 476                         if (tmp & 0x1)
 477                                 break;
 478                         udelay(1);
 479                 }
 480
 481                 if (j >= adev->usec_timeout)
 482                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 483         }
 484
 485         WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 486
 487         /*
 488          * Issue a dummy read to wait for the ACK register to be cleared
 489          * to avoid a false ACK due to the new fast GRBM interface.
 490          */
 491         if (vmhub == AMDGPU_GFXHUB_0)
 492                 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
 493
 494         for (j = 0; j < adev->usec_timeout; j++) {
 495                 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 496                 if (tmp & (1 << vmid))
 497                         break;
 498                 udelay(1);
 499         }
 500
 501         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 502         if (vmhub == AMDGPU_MMHUB_0 ||
 503             vmhub == AMDGPU_MMHUB_1)
 504                 /*
 505                  * add semaphore release after invalidation,
 506                  * write with 0 means semaphore release
 507                  */
 508                 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
 509
 510         spin_unlock(&adev->gmc.invalidate_lock);
 511
 512         if (j < adev->usec_timeout)
 513                 return;
 514
 515         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 516 }
 517
 518 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 519                                             unsigned vmid, uint64_t pd_addr)
 520 {
 521         struct amdgpu_device *adev = ring->adev;
 522         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 523         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 524         unsigned eng = ring->vm_inv_eng;
 525
 526         /*
 527          * It may lose gpuvm invalidate acknowldege state across power-gating
 528          * off cycle, add semaphore acquire before invalidation and semaphore
 529          * release after invalidation to avoid entering power gated state
 530          * to WA the Issue
 531          */
 532
 533         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 534         if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
 535             ring->funcs->vmhub == AMDGPU_MMHUB_1)
 536                 /* a read return value of 1 means semaphore acuqire */
 537                 amdgpu_ring_emit_reg_wait(ring,
 538                                           hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
 539
 540         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 541                               lower_32_bits(pd_addr));
 542
 543         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 544                               upper_32_bits(pd_addr));
 545
 546         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
 547                                             hub->vm_inv_eng0_ack + eng,
 548                                             req, 1 << vmid);
 549
 550         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 551         if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
 552             ring->funcs->vmhub == AMDGPU_MMHUB_1)
 553                 /*
 554                  * add semaphore release after invalidation,
 555                  * write with 0 means semaphore release
 556                  */
 557                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
 558
 559         return pd_addr;
 560 }
 561
 562 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 563                                         unsigned pasid)
 564 {
 565         struct amdgpu_device *adev = ring->adev;
 566         uint32_t reg;
 567
 568         /* Do nothing because there's no lut register for mmhub1. */
 569         if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
 570                 return;
 571
 572         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 573                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 574         else
 575                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 576
 577         amdgpu_ring_emit_wreg(ring, reg, pasid);
 578 }
 579
 580 /*
 581  * PTE format on VEGA 10:
 582  * 63:59 reserved
 583  * 58:57 mtype
 584  * 56 F
 585  * 55 L
 586  * 54 P
 587  * 53 SW
 588  * 52 T
 589  * 50:48 reserved
 590  * 47:12 4k physical page base address
 591  * 11:7 fragment
 592  * 6 write
 593  * 5 read
 594  * 4 exe
 595  * 3 Z
 596  * 2 snooped
 597  * 1 system
 598  * 0 valid
 599  *
 600  * PDE format on VEGA 10:
 601  * 63:59 block fragment size
 602  * 58:55 reserved
 603  * 54 P
 604  * 53:48 reserved
 605  * 47:6 physical base address of PD or PTE
 606  * 5:3 reserved
 607  * 2 C
 608  * 1 system
 609  * 0 valid
 610  */
 611
 612 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 613
 614 {
 615         switch (flags) {
 616         case AMDGPU_VM_MTYPE_DEFAULT:
 617                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 618         case AMDGPU_VM_MTYPE_NC:
 619                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 620         case AMDGPU_VM_MTYPE_WC:
 621                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
 622         case AMDGPU_VM_MTYPE_RW:
 623                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
 624         case AMDGPU_VM_MTYPE_CC:
 625                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
 626         case AMDGPU_VM_MTYPE_UC:
 627                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
 628         default:
 629                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 630         }
 631 }
 632
 633 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 634                                 uint64_t *addr, uint64_t *flags)
 635 {
 636         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 637                 *addr = adev->vm_manager.vram_base_offset + *addr -
 638                         adev->gmc.vram_start;
 639         BUG_ON(*addr & 0xFFFF00000000003FULL);
 640
 641         if (!adev->gmc.translate_further)
 642                 return;
 643
 644         if (level == AMDGPU_VM_PDB1) {
 645                 /* Set the block fragment size */
 646                 if (!(*flags & AMDGPU_PDE_PTE))
 647                         *flags |= AMDGPU_PDE_BFS(0x9);
 648
 649         } else if (level == AMDGPU_VM_PDB0) {
 650                 if (*flags & AMDGPU_PDE_PTE)
 651                         *flags &= ~AMDGPU_PDE_PTE;
 652                 else
 653                         *flags |= AMDGPU_PTE_TF;
 654         }
 655 }
 656
 657 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
 658                                 struct amdgpu_bo_va_mapping *mapping,
 659                                 uint64_t *flags)
 660 {
 661         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 662         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 663
 664         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 665         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
 666
 667         if (mapping->flags & AMDGPU_PTE_PRT) {
 668                 *flags |= AMDGPU_PTE_PRT;
 669                 *flags &= ~AMDGPU_PTE_VALID;
 670         }
 671
 672         if (adev->asic_type == CHIP_ARCTURUS &&
 673             !(*flags & AMDGPU_PTE_SYSTEM) &&
 674             mapping->bo_va->is_xgmi)
 675                 *flags |= AMDGPU_PTE_SNOOPED;
 676 }
 677
 678 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 679         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
 680         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 681         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
 682         .map_mtype = gmc_v9_0_map_mtype,
 683         .get_vm_pde = gmc_v9_0_get_vm_pde,
 684         .get_vm_pte = gmc_v9_0_get_vm_pte
 685 };
 686
 687 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
 688 {
 689         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
 690 }
 691
 692 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
 693 {
 694         switch (adev->asic_type) {
 695         case CHIP_VEGA10:
 696                 adev->umc.funcs = &umc_v6_0_funcs;
 697                 break;
 698         case CHIP_VEGA20:
 699                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
 700                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
 701                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
 702                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET;
 703                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
 704                 adev->umc.funcs = &umc_v6_1_funcs;
 705                 break;
 706         default:
 707                 break;
 708         }
 709 }
 710
 711 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
 712 {
 713         switch (adev->asic_type) {
 714         case CHIP_VEGA20:
 715                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
 716                 break;
 717         default:
 718                 break;
 719         }
 720 }
 721
 722 static int gmc_v9_0_early_init(void *handle)
 723 {
 724         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 725
 726         gmc_v9_0_set_gmc_funcs(adev);
 727         gmc_v9_0_set_irq_funcs(adev);
 728         gmc_v9_0_set_umc_funcs(adev);
 729         gmc_v9_0_set_mmhub_funcs(adev);
 730
 731         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 732         adev->gmc.shared_aperture_end =
 733                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 734         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 735         adev->gmc.private_aperture_end =
 736                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 737
 738         return 0;
 739 }
 740
 741 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
 742 {
 743
 744         /*
 745          * TODO:
 746          * Currently there is a bug where some memory client outside
 747          * of the driver writes to first 8M of VRAM on S3 resume,
 748          * this overrides GART which by default gets placed in first 8M and
 749          * causes VM_FAULTS once GTT is accessed.
 750          * Keep the stolen memory reservation until the while this is not solved.
 751          * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
 752          */
 753         switch (adev->asic_type) {
 754         case CHIP_VEGA10:
 755         case CHIP_RAVEN:
 756         case CHIP_ARCTURUS:
 757         case CHIP_RENOIR:
 758                 return true;
 759         case CHIP_VEGA12:
 760         case CHIP_VEGA20:
 761         default:
 762                 return false;
 763         }
 764 }
 765
 766 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 767 {
 768         struct amdgpu_ring *ring;
 769         unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
 770                 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
 771                 GFXHUB_FREE_VM_INV_ENGS_BITMAP};
 772         unsigned i;
 773         unsigned vmhub, inv_eng;
 774
 775         for (i = 0; i < adev->num_rings; ++i) {
 776                 ring = adev->rings[i];
 777                 vmhub = ring->funcs->vmhub;
 778
 779                 inv_eng = ffs(vm_inv_engs[vmhub]);
 780                 if (!inv_eng) {
 781                         dev_err(adev->dev, "no VM inv eng for ring %s\n",
 782                                 ring->name);
 783                         return -EINVAL;
 784                 }
 785
 786                 ring->vm_inv_eng = inv_eng - 1;
 787                 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
 788
 789                 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
 790                          ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int gmc_v9_0_late_init(void *handle)
 797 {
 798         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 799         int r;
 800
 801         if (!gmc_v9_0_keep_stolen_memory(adev))
 802                 amdgpu_bo_late_init(adev);
 803
 804         r = gmc_v9_0_allocate_vm_inv_eng(adev);
 805         if (r)
 806                 return r;
 807         /* Check if ecc is available */
 808         if (!amdgpu_sriov_vf(adev)) {
 809                 switch (adev->asic_type) {
 810                 case CHIP_VEGA10:
 811                 case CHIP_VEGA20:
 812                         r = amdgpu_atomfirmware_mem_ecc_supported(adev);
 813                         if (!r) {
 814                                 DRM_INFO("ECC is not present.\n");
 815                                 if (adev->df_funcs->enable_ecc_force_par_wr_rmw)
 816                                         adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
 817                         } else {
 818                                 DRM_INFO("ECC is active.\n");
 819                         }
 820
 821                         r = amdgpu_atomfirmware_sram_ecc_supported(adev);
 822                         if (!r) {
 823                                 DRM_INFO("SRAM ECC is not present.\n");
 824                         } else {
 825                                 DRM_INFO("SRAM ECC is active.\n");
 826                         }
 827                         break;
 828                 default:
 829                         break;
 830                 }
 831         }
 832
 833         r = amdgpu_gmc_ras_late_init(adev);
 834         if (r)
 835                 return r;
 836
 837         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 838 }
 839
 840 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 841                                         struct amdgpu_gmc *mc)
 842 {
 843         u64 base = 0;
 844
 845         if (adev->asic_type == CHIP_ARCTURUS)
 846                 base = mmhub_v9_4_get_fb_location(adev);
 847         else if (!amdgpu_sriov_vf(adev))
 848                 base = mmhub_v1_0_get_fb_location(adev);
 849
 850         /* add the xgmi offset of the physical node */
 851         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 852         amdgpu_gmc_vram_location(adev, mc, base);
 853         amdgpu_gmc_gart_location(adev, mc);
 854         amdgpu_gmc_agp_location(adev, mc);
 855         /* base offset of vram pages */
 856         adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 857
 858         /* XXX: add the xgmi offset of the physical node? */
 859         adev->vm_manager.vram_base_offset +=
 860                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 861 }
 862
 863 /**
 864  * gmc_v9_0_mc_init - initialize the memory controller driver params
 865  *
 866  * @adev: amdgpu_device pointer
 867  *
 868  * Look up the amount of vram, vram width, and decide how to place
 869  * vram and gart within the GPU's physical address space.
 870  * Returns 0 for success.
 871  */
 872 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 873 {
 874         int r;
 875
 876         /* size in MB on si */
 877         adev->gmc.mc_vram_size =
 878                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 879         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 880
 881         if (!(adev->flags & AMD_IS_APU)) {
 882                 r = amdgpu_device_resize_fb_bar(adev);
 883                 if (r)
 884                         return r;
 885         }
 886         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 887         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 888
 889 #ifdef CONFIG_X86_64
 890         if (adev->flags & AMD_IS_APU) {
 891                 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
 892                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 893         }
 894 #endif
 895         /* In case the PCI BAR is larger than the actual amount of vram */
 896         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 897         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 898                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 899
 900         /* set the gart size */
 901         if (amdgpu_gart_size == -1) {
 902                 switch (adev->asic_type) {
 903                 case CHIP_VEGA10:  /* all engines support GPUVM */
 904                 case CHIP_VEGA12:  /* all engines support GPUVM */
 905                 case CHIP_VEGA20:
 906                 case CHIP_ARCTURUS:
 907                 default:
 908                         adev->gmc.gart_size = 512ULL << 20;
 909                         break;
 910                 case CHIP_RAVEN:   /* DCE SG support */
 911                 case CHIP_RENOIR:
 912                         adev->gmc.gart_size = 1024ULL << 20;
 913                         break;
 914                 }
 915         } else {
 916                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 917         }
 918
 919         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
 920
 921         return 0;
 922 }
 923
 924 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 925 {
 926         int r;
 927
 928         if (adev->gart.bo) {
 929                 WARN(1, "VEGA10 PCIE GART already initialized\n");
 930                 return 0;
 931         }
 932         /* Initialize common gart structure */
 933         r = amdgpu_gart_init(adev);
 934         if (r)
 935                 return r;
 936         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 937         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
 938                                  AMDGPU_PTE_EXECUTABLE;
 939         return amdgpu_gart_table_vram_alloc(adev);
 940 }
 941
 942 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 943 {
 944         u32 d1vga_control;
 945         unsigned size;
 946
 947         /*
 948          * TODO Remove once GART corruption is resolved
 949          * Check related code in gmc_v9_0_sw_fini
 950          * */
 951         if (gmc_v9_0_keep_stolen_memory(adev))
 952                 return 9 * 1024 * 1024;
 953
 954         d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 955         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 956                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 957         } else {
 958                 u32 viewport;
 959
 960                 switch (adev->asic_type) {
 961                 case CHIP_RAVEN:
 962                 case CHIP_RENOIR:
 963                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 964                         size = (REG_GET_FIELD(viewport,
 965                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 966                                 REG_GET_FIELD(viewport,
 967                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
 968                                 4);
 969                         break;
 970                 case CHIP_VEGA10:
 971                 case CHIP_VEGA12:
 972                 case CHIP_VEGA20:
 973                 default:
 974                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
 975                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 976                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 977                                 4);
 978                         break;
 979                 }
 980         }
 981         /* return 0 if the pre-OS buffer uses up most of vram */
 982         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
 983                 return 0;
 984
 985         return size;
 986 }
 987
 988 static int gmc_v9_0_sw_init(void *handle)
 989 {
 990         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 991         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 992
 993         gfxhub_v1_0_init(adev);
 994         if (adev->asic_type == CHIP_ARCTURUS)
 995                 mmhub_v9_4_init(adev);
 996         else
 997                 mmhub_v1_0_init(adev);
 998
 999         spin_lock_init(&adev->gmc.invalidate_lock);
1000
1001         r = amdgpu_atomfirmware_get_vram_info(adev,
1002                 &vram_width, &vram_type, &vram_vendor);
1003         if (amdgpu_sriov_vf(adev))
1004                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1005                  * and DF related registers is not readable, seems hardcord is the
1006                  * only way to set the correct vram_width
1007                  */
1008                 adev->gmc.vram_width = 2048;
1009         else if (amdgpu_emu_mode != 1)
1010                 adev->gmc.vram_width = vram_width;
1011
1012         if (!adev->gmc.vram_width) {
1013                 int chansize, numchan;
1014
1015                 /* hbm memory channel size */
1016                 if (adev->flags & AMD_IS_APU)
1017                         chansize = 64;
1018                 else
1019                         chansize = 128;
1020
1021                 numchan = adev->df_funcs->get_hbm_channel_number(adev);
1022                 adev->gmc.vram_width = numchan * chansize;
1023         }
1024
1025         adev->gmc.vram_type = vram_type;
1026         adev->gmc.vram_vendor = vram_vendor;
1027         switch (adev->asic_type) {
1028         case CHIP_RAVEN:
1029                 adev->num_vmhubs = 2;
1030
1031                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1032                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1033                 } else {
1034                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1035                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1036                         adev->gmc.translate_further =
1037                                 adev->vm_manager.num_level > 1;
1038                 }
1039                 break;
1040         case CHIP_VEGA10:
1041         case CHIP_VEGA12:
1042         case CHIP_VEGA20:
1043         case CHIP_RENOIR:
1044                 adev->num_vmhubs = 2;
1045
1046
1047                 /*
1048                  * To fulfill 4-level page support,
1049                  * vm size is 256TB (48bit), maximum size of Vega10,
1050                  * block size 512 (9bit)
1051                  */
1052                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1053                 if (amdgpu_sriov_vf(adev))
1054                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1055                 else
1056                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1057                 break;
1058         case CHIP_ARCTURUS:
1059                 adev->num_vmhubs = 3;
1060
1061                 /* Keep the vm size same with Vega20 */
1062                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1063                 break;
1064         default:
1065                 break;
1066         }
1067
1068         /* This interrupt is VMC page fault.*/
1069         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1070                                 &adev->gmc.vm_fault);
1071         if (r)
1072                 return r;
1073
1074         if (adev->asic_type == CHIP_ARCTURUS) {
1075                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1076                                         &adev->gmc.vm_fault);
1077                 if (r)
1078                         return r;
1079         }
1080
1081         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1082                                 &adev->gmc.vm_fault);
1083
1084         if (r)
1085                 return r;
1086
1087         /* interrupt sent to DF. */
1088         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1089                         &adev->gmc.ecc_irq);
1090         if (r)
1091                 return r;
1092
1093         /* Set the internal MC address mask
1094          * This is the max address of the GPU's
1095          * internal address space.
1096          */
1097         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1098
1099         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1100         if (r) {
1101                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1102                 return r;
1103         }
1104         adev->need_swiotlb = drm_need_swiotlb(44);
1105
1106         if (adev->gmc.xgmi.supported) {
1107                 r = gfxhub_v1_1_get_xgmi_info(adev);
1108                 if (r)
1109                         return r;
1110         }
1111
1112         r = gmc_v9_0_mc_init(adev);
1113         if (r)
1114                 return r;
1115
1116         adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1117
1118         /* Memory manager */
1119         r = amdgpu_bo_init(adev);
1120         if (r)
1121                 return r;
1122
1123         r = gmc_v9_0_gart_init(adev);
1124         if (r)
1125                 return r;
1126
1127         /*
1128          * number of VMs
1129          * VMID 0 is reserved for System
1130          * amdgpu graphics/compute will use VMIDs 1-7
1131          * amdkfd will use VMIDs 8-15
1132          */
1133         adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1134         adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
1135         adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
1136
1137         amdgpu_vm_manager_init(adev);
1138
1139         return 0;
1140 }
1141
1142 static int gmc_v9_0_sw_fini(void *handle)
1143 {
1144         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1145         void *stolen_vga_buf;
1146
1147         amdgpu_gmc_ras_fini(adev);
1148         amdgpu_gem_force_release(adev);
1149         amdgpu_vm_manager_fini(adev);
1150
1151         if (gmc_v9_0_keep_stolen_memory(adev))
1152                 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1153
1154         amdgpu_gart_table_vram_free(adev);
1155         amdgpu_bo_fini(adev);
1156         amdgpu_gart_fini(adev);
1157
1158         return 0;
1159 }
1160
1161 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1162 {
1163
1164         switch (adev->asic_type) {
1165         case CHIP_VEGA10:
1166                 if (amdgpu_sriov_vf(adev))
1167                         break;
1168                 /* fall through */
1169         case CHIP_VEGA20:
1170                 soc15_program_register_sequence(adev,
1171                                                 golden_settings_mmhub_1_0_0,
1172                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1173                 soc15_program_register_sequence(adev,
1174                                                 golden_settings_athub_1_0_0,
1175                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1176                 break;
1177         case CHIP_VEGA12:
1178                 break;
1179         case CHIP_RAVEN:
1180                 /* TODO for renoir */
1181                 soc15_program_register_sequence(adev,
1182                                                 golden_settings_athub_1_0_0,
1183                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1184                 break;
1185         default:
1186                 break;
1187         }
1188 }
1189
1190 /**
1191  * gmc_v9_0_gart_enable - gart enable
1192  *
1193  * @adev: amdgpu_device pointer
1194  */
1195 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1196 {
1197         int r;
1198
1199         if (adev->gart.bo == NULL) {
1200                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1201                 return -EINVAL;
1202         }
1203         r = amdgpu_gart_table_vram_pin(adev);
1204         if (r)
1205                 return r;
1206
1207         r = gfxhub_v1_0_gart_enable(adev);
1208         if (r)
1209                 return r;
1210
1211         if (adev->asic_type == CHIP_ARCTURUS)
1212                 r = mmhub_v9_4_gart_enable(adev);
1213         else
1214                 r = mmhub_v1_0_gart_enable(adev);
1215         if (r)
1216                 return r;
1217
1218         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1219                  (unsigned)(adev->gmc.gart_size >> 20),
1220                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1221         adev->gart.ready = true;
1222         return 0;
1223 }
1224
1225 static int gmc_v9_0_hw_init(void *handle)
1226 {
1227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1228         bool value;
1229         int r, i;
1230         u32 tmp;
1231
1232         /* The sequence of these two function calls matters.*/
1233         gmc_v9_0_init_golden_registers(adev);
1234
1235         if (adev->mode_info.num_crtc) {
1236                 if (adev->asic_type != CHIP_ARCTURUS) {
1237                         /* Lockout access through VGA aperture*/
1238                         WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1239
1240                         /* disable VGA render */
1241                         WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1242                 }
1243         }
1244
1245         amdgpu_device_program_register_sequence(adev,
1246                                                 golden_settings_vega10_hdp,
1247                                                 ARRAY_SIZE(golden_settings_vega10_hdp));
1248
1249         switch (adev->asic_type) {
1250         case CHIP_RAVEN:
1251                 /* TODO for renoir */
1252                 mmhub_v1_0_update_power_gating(adev, true);
1253                 break;
1254         case CHIP_ARCTURUS:
1255                 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
1256                 break;
1257         default:
1258                 break;
1259         }
1260
1261         WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1262
1263         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1264         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1265
1266         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1267         WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1268
1269         /* After HDP is initialized, flush HDP.*/
1270         adev->nbio.funcs->hdp_flush(adev, NULL);
1271
1272         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1273                 value = false;
1274         else
1275                 value = true;
1276
1277         gfxhub_v1_0_set_fault_enable_default(adev, value);
1278         if (adev->asic_type == CHIP_ARCTURUS)
1279                 mmhub_v9_4_set_fault_enable_default(adev, value);
1280         else
1281                 mmhub_v1_0_set_fault_enable_default(adev, value);
1282
1283         for (i = 0; i < adev->num_vmhubs; ++i)
1284                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1285
1286         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1287                 adev->umc.funcs->init_registers(adev);
1288
1289         r = gmc_v9_0_gart_enable(adev);
1290
1291         return r;
1292 }
1293
1294 /**
1295  * gmc_v9_0_gart_disable - gart disable
1296  *
1297  * @adev: amdgpu_device pointer
1298  *
1299  * This disables all VM page table.
1300  */
1301 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1302 {
1303         gfxhub_v1_0_gart_disable(adev);
1304         if (adev->asic_type == CHIP_ARCTURUS)
1305                 mmhub_v9_4_gart_disable(adev);
1306         else
1307                 mmhub_v1_0_gart_disable(adev);
1308         amdgpu_gart_table_vram_unpin(adev);
1309 }
1310
1311 static int gmc_v9_0_hw_fini(void *handle)
1312 {
1313         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314
1315         if (amdgpu_sriov_vf(adev)) {
1316                 /* full access mode, so don't touch any GMC register */
1317                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1318                 return 0;
1319         }
1320
1321         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1322         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1323         gmc_v9_0_gart_disable(adev);
1324
1325         return 0;
1326 }
1327
1328 static int gmc_v9_0_suspend(void *handle)
1329 {
1330         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331
1332         return gmc_v9_0_hw_fini(adev);
1333 }
1334
1335 static int gmc_v9_0_resume(void *handle)
1336 {
1337         int r;
1338         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339
1340         r = gmc_v9_0_hw_init(adev);
1341         if (r)
1342                 return r;
1343
1344         amdgpu_vmid_reset_all(adev);
1345
1346         return 0;
1347 }
1348
1349 static bool gmc_v9_0_is_idle(void *handle)
1350 {
1351         /* MC is always ready in GMC v9.*/
1352         return true;
1353 }
1354
1355 static int gmc_v9_0_wait_for_idle(void *handle)
1356 {
1357         /* There is no need to wait for MC idle in GMC v9.*/
1358         return 0;
1359 }
1360
1361 static int gmc_v9_0_soft_reset(void *handle)
1362 {
1363         /* XXX for emulation.*/
1364         return 0;
1365 }
1366
1367 static int gmc_v9_0_set_clockgating_state(void *handle,
1368                                         enum amd_clockgating_state state)
1369 {
1370         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1371
1372         if (adev->asic_type == CHIP_ARCTURUS)
1373                 mmhub_v9_4_set_clockgating(adev, state);
1374         else
1375                 mmhub_v1_0_set_clockgating(adev, state);
1376
1377         athub_v1_0_set_clockgating(adev, state);
1378
1379         return 0;
1380 }
1381
1382 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1383 {
1384         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1385
1386         if (adev->asic_type == CHIP_ARCTURUS)
1387                 mmhub_v9_4_get_clockgating(adev, flags);
1388         else
1389                 mmhub_v1_0_get_clockgating(adev, flags);
1390
1391         athub_v1_0_get_clockgating(adev, flags);
1392 }
1393
1394 static int gmc_v9_0_set_powergating_state(void *handle,
1395                                         enum amd_powergating_state state)
1396 {
1397         return 0;
1398 }
1399
1400 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1401         .name = "gmc_v9_0",
1402         .early_init = gmc_v9_0_early_init,
1403         .late_init = gmc_v9_0_late_init,
1404         .sw_init = gmc_v9_0_sw_init,
1405         .sw_fini = gmc_v9_0_sw_fini,
1406         .hw_init = gmc_v9_0_hw_init,
1407         .hw_fini = gmc_v9_0_hw_fini,
1408         .suspend = gmc_v9_0_suspend,
1409         .resume = gmc_v9_0_resume,
1410         .is_idle = gmc_v9_0_is_idle,
1411         .wait_for_idle = gmc_v9_0_wait_for_idle,
1412         .soft_reset = gmc_v9_0_soft_reset,
1413         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1414         .set_powergating_state = gmc_v9_0_set_powergating_state,
1415         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1416 };
1417
1418 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1419 {
1420         .type = AMD_IP_BLOCK_TYPE_GMC,
1421         .major = 9,
1422         .minor = 0,
1423         .rev = 0,
1424         .funcs = &gmc_v9_0_ip_funcs,
1425 };