drivers/platform/x86/amd/pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <[email protected]>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/limits.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/rtc.h>
  25 #include <linux/suspend.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/uaccess.h>
  28
  29 /* SMU communication registers */
  30 #define AMD_PMC_REGISTER_MESSAGE        0x538
  31 #define AMD_PMC_REGISTER_RESPONSE       0x980
  32 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  33
  34 /* PMC Scratch Registers */
  35 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  36 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  37
  38 /* STB Registers */
  39 #define AMD_PMC_STB_INDEX_ADDRESS       0xF8
  40 #define AMD_PMC_STB_INDEX_DATA          0xFC
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_PREDEF              0xC6000001
  43
  44 /* STB S2D(Spill to DRAM) has different message port offset */
  45 #define STB_SPILL_TO_DRAM               0xBE
  46 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  47 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  48 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  49
  50 /* STB Spill to DRAM Parameters */
  51 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  52 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  53
  54 /* Base address of SMU for mapping physical address to virtual address */
  55 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  56 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  57 #define AMD_PMC_MAPPING_SIZE            0x01000
  58 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  59 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  60 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  61 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  62 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  63
  64 /* SMU Response Codes */
  65 #define AMD_PMC_RESULT_OK                    0x01
  66 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  67 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  68 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  69 #define AMD_PMC_RESULT_FAILED                0xFF
  70
  71 /* FCH SSC Registers */
  72 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  73 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  74 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  75 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  76 #define FCH_SSC_MAPPING_SIZE            0x800
  77 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  78 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  79
  80 /* SMU Message Definations */
  81 #define SMU_MSG_GETSMUVERSION           0x02
  82 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  83 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  84 #define SMU_MSG_LOG_START               0x06
  85 #define SMU_MSG_LOG_RESET               0x07
  86 #define SMU_MSG_LOG_DUMP_DATA           0x08
  87 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  88 /* List of supported CPU ids */
  89 #define AMD_CPU_ID_RV                   0x15D0
  90 #define AMD_CPU_ID_RN                   0x1630
  91 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  92 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  93 #define AMD_CPU_ID_YC                   0x14B5
  94 #define AMD_CPU_ID_CB                   0x14D8
  95 #define AMD_CPU_ID_PS                   0x14E8
  96
  97 #define PMC_MSG_DELAY_MIN_US            50
  98 #define RESPONSE_REGISTER_LOOP_MAX      20000
  99
 100 #define SOC_SUBSYSTEM_IP_MAX    12
 101 #define DELAY_MIN_US            2000
 102 #define DELAY_MAX_US            3000
 103 #define FIFO_SIZE               4096
 104 enum amd_pmc_def {
 105         MSG_TEST = 0x01,
 106         MSG_OS_HINT_PCO,
 107         MSG_OS_HINT_RN,
 108 };
 109
 110 enum s2d_arg {
 111         S2D_TELEMETRY_SIZE = 0x01,
 112         S2D_PHYS_ADDR_LOW,
 113         S2D_PHYS_ADDR_HIGH,
 114 };
 115
 116 struct amd_pmc_bit_map {
 117         const char *name;
 118         u32 bit_mask;
 119 };
 120
 121 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 122         {"DISPLAY",     BIT(0)},
 123         {"CPU",         BIT(1)},
 124         {"GFX",         BIT(2)},
 125         {"VDD",         BIT(3)},
 126         {"ACP",         BIT(4)},
 127         {"VCN",         BIT(5)},
 128         {"ISP",         BIT(6)},
 129         {"NBIO",        BIT(7)},
 130         {"DF",          BIT(8)},
 131         {"USB0",        BIT(9)},
 132         {"USB1",        BIT(10)},
 133         {"LAPIC",       BIT(11)},
 134         {}
 135 };
 136
 137 struct amd_pmc_dev {
 138         void __iomem *regbase;
 139         void __iomem *smu_virt_addr;
 140         void __iomem *stb_virt_addr;
 141         void __iomem *fch_virt_addr;
 142         bool msg_port;
 143         u32 base_addr;
 144         u32 cpu_id;
 145         u32 active_ips;
 146 /* SMU version information */
 147         u8 smu_program;
 148         u8 major;
 149         u8 minor;
 150         u8 rev;
 151         struct device *dev;
 152         struct pci_dev *rdev;
 153         struct mutex lock; /* generic mutex lock */
 154 #if IS_ENABLED(CONFIG_DEBUG_FS)
 155         struct dentry *dbgfs_dir;
 156 #endif /* CONFIG_DEBUG_FS */
 157 };
 158
 159 static bool enable_stb;
 160 module_param(enable_stb, bool, 0644);
 161 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 162
 163 static struct amd_pmc_dev pmc;
 164 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 165 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 166 #ifdef CONFIG_SUSPEND
 167 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 168 #endif
 169
 170 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 171 {
 172         return ioread32(dev->regbase + reg_offset);
 173 }
 174
 175 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 176 {
 177         iowrite32(val, dev->regbase + reg_offset);
 178 }
 179
 180 struct smu_metrics {
 181         u32 table_version;
 182         u32 hint_count;
 183         u32 s0i3_last_entry_status;
 184         u32 timein_s0i2;
 185         u64 timeentering_s0i3_lastcapture;
 186         u64 timeentering_s0i3_totaltime;
 187         u64 timeto_resume_to_os_lastcapture;
 188         u64 timeto_resume_to_os_totaltime;
 189         u64 timein_s0i3_lastcapture;
 190         u64 timein_s0i3_totaltime;
 191         u64 timein_swdrips_lastcapture;
 192         u64 timein_swdrips_totaltime;
 193         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 194         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 195 } __packed;
 196
 197 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 198 {
 199         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 200         u32 size = FIFO_SIZE * sizeof(u32);
 201         u32 *buf;
 202         int rc;
 203
 204         buf = kzalloc(size, GFP_KERNEL);
 205         if (!buf)
 206                 return -ENOMEM;
 207
 208         rc = amd_pmc_read_stb(dev, buf);
 209         if (rc) {
 210                 kfree(buf);
 211                 return rc;
 212         }
 213
 214         filp->private_data = buf;
 215         return rc;
 216 }
 217
 218 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 219                                         loff_t *pos)
 220 {
 221         if (!filp->private_data)
 222                 return -EINVAL;
 223
 224         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 225                                        FIFO_SIZE * sizeof(u32));
 226 }
 227
 228 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 229 {
 230         kfree(filp->private_data);
 231         return 0;
 232 }
 233
 234 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 235         .owner = THIS_MODULE,
 236         .open = amd_pmc_stb_debugfs_open,
 237         .read = amd_pmc_stb_debugfs_read,
 238         .release = amd_pmc_stb_debugfs_release,
 239 };
 240
 241 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 242 {
 243         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 244         u32 *buf;
 245
 246         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 247         if (!buf)
 248                 return -ENOMEM;
 249
 250         memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
 251         filp->private_data = buf;
 252
 253         return 0;
 254 }
 255
 256 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 257                                            loff_t *pos)
 258 {
 259         if (!filp->private_data)
 260                 return -EINVAL;
 261
 262         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 263                                         S2D_TELEMETRY_BYTES_MAX);
 264 }
 265
 266 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 267 {
 268         kfree(filp->private_data);
 269         return 0;
 270 }
 271
 272 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 273         .owner = THIS_MODULE,
 274         .open = amd_pmc_stb_debugfs_open_v2,
 275         .read = amd_pmc_stb_debugfs_read_v2,
 276         .release = amd_pmc_stb_debugfs_release_v2,
 277 };
 278
 279 #if defined(CONFIG_SUSPEND) || defined(CONFIG_DEBUG_FS)
 280 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 281 {
 282         if (dev->cpu_id == AMD_CPU_ID_PCO) {
 283                 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
 284                 return -EINVAL;
 285         }
 286
 287         /* Get Active devices list from SMU */
 288         if (!dev->active_ips)
 289                 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 290
 291         /* Get dram address */
 292         if (!dev->smu_virt_addr) {
 293                 u32 phys_addr_low, phys_addr_hi;
 294                 u64 smu_phys_addr;
 295
 296                 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 297                 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 298                 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 299
 300                 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
 301                                                   sizeof(struct smu_metrics));
 302                 if (!dev->smu_virt_addr)
 303                         return -ENOMEM;
 304         }
 305
 306         /* Start the logging */
 307         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 308         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 309
 310         return 0;
 311 }
 312
 313 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 314                                  struct seq_file *s)
 315 {
 316         u32 val;
 317
 318         switch (pdev->cpu_id) {
 319         case AMD_CPU_ID_CZN:
 320                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 321                 break;
 322         case AMD_CPU_ID_YC:
 323         case AMD_CPU_ID_CB:
 324         case AMD_CPU_ID_PS:
 325                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 326                 break;
 327         default:
 328                 return -EINVAL;
 329         }
 330
 331         if (dev)
 332                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 333
 334         if (s)
 335                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 336
 337         return 0;
 338 }
 339
 340 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 341 {
 342         if (!pdev->smu_virt_addr) {
 343                 int ret = amd_pmc_setup_smu_logging(pdev);
 344
 345                 if (ret)
 346                         return ret;
 347         }
 348
 349         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 350                 return -ENODEV;
 351         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 352         return 0;
 353 }
 354 #endif /* CONFIG_SUSPEND || CONFIG_DEBUG_FS */
 355
 356 #ifdef CONFIG_SUSPEND
 357 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 358 {
 359         struct smu_metrics table;
 360
 361         if (get_metrics_table(pdev, &table))
 362                 return;
 363
 364         if (!table.s0i3_last_entry_status)
 365                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 366         else
 367                 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
 368                          table.timein_s0i3_lastcapture);
 369 }
 370 #endif
 371
 372 #ifdef CONFIG_DEBUG_FS
 373 static int smu_fw_info_show(struct seq_file *s, void *unused)
 374 {
 375         struct amd_pmc_dev *dev = s->private;
 376         struct smu_metrics table;
 377         int idx;
 378
 379         if (get_metrics_table(dev, &table))
 380                 return -EINVAL;
 381
 382         seq_puts(s, "\n=== SMU Statistics ===\n");
 383         seq_printf(s, "Table Version: %d\n", table.table_version);
 384         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 385         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 386                    "Unknown/Fail");
 387         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 388         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 389         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 390                    table.timeto_resume_to_os_lastcapture);
 391
 392         seq_puts(s, "\n=== Active time (in us) ===\n");
 393         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 394                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 395                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 396                                    table.timecondition_notmet_lastcapture[idx]);
 397         }
 398
 399         return 0;
 400 }
 401 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 402
 403 static int s0ix_stats_show(struct seq_file *s, void *unused)
 404 {
 405         struct amd_pmc_dev *dev = s->private;
 406         u64 entry_time, exit_time, residency;
 407
 408         /* Use FCH registers to get the S0ix stats */
 409         if (!dev->fch_virt_addr) {
 410                 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 411                 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 412                 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 413
 414                 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 415                 if (!dev->fch_virt_addr)
 416                         return -ENOMEM;
 417         }
 418
 419         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 420         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 421
 422         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 423         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 424
 425         /* It's in 48MHz. We need to convert it */
 426         residency = exit_time - entry_time;
 427         do_div(residency, 48);
 428
 429         seq_puts(s, "=== S0ix statistics ===\n");
 430         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 431         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 432         seq_printf(s, "Residency Time: %lld\n", residency);
 433
 434         return 0;
 435 }
 436 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 437
 438 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 439 {
 440         int rc;
 441         u32 val;
 442
 443         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 444         if (rc)
 445                 return rc;
 446
 447         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 448         dev->major = (val >> 16) & GENMASK(7, 0);
 449         dev->minor = (val >> 8) & GENMASK(7, 0);
 450         dev->rev = (val >> 0) & GENMASK(7, 0);
 451
 452         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 453                 dev->smu_program, dev->major, dev->minor, dev->rev);
 454
 455         return 0;
 456 }
 457
 458 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 459 {
 460         struct amd_pmc_dev *dev = s->private;
 461         int rc;
 462
 463         /* we haven't yet read SMU version */
 464         if (!dev->major) {
 465                 rc = amd_pmc_get_smu_version(dev);
 466                 if (rc)
 467                         return rc;
 468         }
 469
 470         if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
 471                 rc = amd_pmc_idlemask_read(dev, NULL, s);
 472                 if (rc)
 473                         return rc;
 474         } else {
 475                 seq_puts(s, "Unsupported SMU version for Idlemask\n");
 476         }
 477
 478         return 0;
 479 }
 480 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 481
 482 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 483 {
 484         debugfs_remove_recursive(dev->dbgfs_dir);
 485 }
 486
 487 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 488 {
 489         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 490         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 491                             &smu_fw_info_fops);
 492         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 493                             &s0ix_stats_fops);
 494         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 495                             &amd_pmc_idlemask_fops);
 496         /* Enable STB only when the module_param is set */
 497         if (enable_stb) {
 498                 if (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
 499                     dev->cpu_id == AMD_CPU_ID_PS)
 500                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 501                                             &amd_pmc_stb_debugfs_fops_v2);
 502                 else
 503                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 504                                             &amd_pmc_stb_debugfs_fops);
 505         }
 506 }
 507 #else
 508 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 509 {
 510 }
 511
 512 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 513 {
 514 }
 515 #endif /* CONFIG_DEBUG_FS */
 516
 517 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 518 {
 519         u32 value, message, argument, response;
 520
 521         if (dev->msg_port) {
 522                 message = AMD_S2D_REGISTER_MESSAGE;
 523                 argument = AMD_S2D_REGISTER_ARGUMENT;
 524                 response = AMD_S2D_REGISTER_RESPONSE;
 525         } else {
 526                 message = AMD_PMC_REGISTER_MESSAGE;
 527                 argument = AMD_PMC_REGISTER_ARGUMENT;
 528                 response = AMD_PMC_REGISTER_RESPONSE;
 529         }
 530
 531         value = amd_pmc_reg_read(dev, response);
 532         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
 533
 534         value = amd_pmc_reg_read(dev, argument);
 535         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
 536
 537         value = amd_pmc_reg_read(dev, message);
 538         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
 539 }
 540
 541 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 542 {
 543         int rc;
 544         u32 val, message, argument, response;
 545
 546         mutex_lock(&dev->lock);
 547
 548         if (dev->msg_port) {
 549                 message = AMD_S2D_REGISTER_MESSAGE;
 550                 argument = AMD_S2D_REGISTER_ARGUMENT;
 551                 response = AMD_S2D_REGISTER_RESPONSE;
 552         } else {
 553                 message = AMD_PMC_REGISTER_MESSAGE;
 554                 argument = AMD_PMC_REGISTER_ARGUMENT;
 555                 response = AMD_PMC_REGISTER_RESPONSE;
 556         }
 557
 558         /* Wait until we get a valid response */
 559         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 560                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 561                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 562         if (rc) {
 563                 dev_err(dev->dev, "failed to talk to SMU\n");
 564                 goto out_unlock;
 565         }
 566
 567         /* Write zero to response register */
 568         amd_pmc_reg_write(dev, response, 0);
 569
 570         /* Write argument into response register */
 571         amd_pmc_reg_write(dev, argument, arg);
 572
 573         /* Write message ID to message ID register */
 574         amd_pmc_reg_write(dev, message, msg);
 575
 576         /* Wait until we get a valid response */
 577         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 578                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 579                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 580         if (rc) {
 581                 dev_err(dev->dev, "SMU response timed out\n");
 582                 goto out_unlock;
 583         }
 584
 585         switch (val) {
 586         case AMD_PMC_RESULT_OK:
 587                 if (ret) {
 588                         /* PMFW may take longer time to return back the data */
 589                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 590                         *data = amd_pmc_reg_read(dev, argument);
 591                 }
 592                 break;
 593         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 594                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 595                 rc = -EBUSY;
 596                 goto out_unlock;
 597         case AMD_PMC_RESULT_CMD_UNKNOWN:
 598                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 599                 rc = -EINVAL;
 600                 goto out_unlock;
 601         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 602         case AMD_PMC_RESULT_FAILED:
 603         default:
 604                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 605                 rc = -EIO;
 606                 goto out_unlock;
 607         }
 608
 609 out_unlock:
 610         mutex_unlock(&dev->lock);
 611         amd_pmc_dump_registers(dev);
 612         return rc;
 613 }
 614
 615 #ifdef CONFIG_SUSPEND
 616 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 617 {
 618         switch (dev->cpu_id) {
 619         case AMD_CPU_ID_PCO:
 620                 return MSG_OS_HINT_PCO;
 621         case AMD_CPU_ID_RN:
 622         case AMD_CPU_ID_YC:
 623         case AMD_CPU_ID_CB:
 624         case AMD_CPU_ID_PS:
 625                 return MSG_OS_HINT_RN;
 626         }
 627         return -EINVAL;
 628 }
 629
 630 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 631 {
 632         struct rtc_device *rtc_device;
 633         time64_t then, now, duration;
 634         struct rtc_wkalrm alarm;
 635         struct rtc_time tm;
 636         int rc;
 637
 638         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 639                 return 0;
 640
 641         rtc_device = rtc_class_open("rtc0");
 642         if (!rtc_device)
 643                 return 0;
 644         rc = rtc_read_alarm(rtc_device, &alarm);
 645         if (rc)
 646                 return rc;
 647         if (!alarm.enabled) {
 648                 dev_dbg(pdev->dev, "alarm not enabled\n");
 649                 return 0;
 650         }
 651         rc = rtc_read_time(rtc_device, &tm);
 652         if (rc)
 653                 return rc;
 654         then = rtc_tm_to_time64(&alarm.time);
 655         now = rtc_tm_to_time64(&tm);
 656         duration = then-now;
 657
 658         /* in the past */
 659         if (then < now)
 660                 return 0;
 661
 662         /* will be stored in upper 16 bits of s0i3 hint argument,
 663          * so timer wakeup from s0i3 is limited to ~18 hours or less
 664          */
 665         if (duration <= 4 || duration > U16_MAX)
 666                 return -EINVAL;
 667
 668         *arg |= (duration << 16);
 669         rc = rtc_alarm_irq_enable(rtc_device, 0);
 670         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 671
 672         return rc;
 673 }
 674
 675 static void amd_pmc_s2idle_prepare(void)
 676 {
 677         struct amd_pmc_dev *pdev = &pmc;
 678         int rc;
 679         u8 msg;
 680         u32 arg = 1;
 681
 682         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 683         amd_pmc_setup_smu_logging(pdev);
 684
 685         /* Activate CZN specific RTC functionality */
 686         if (pdev->cpu_id == AMD_CPU_ID_CZN) {
 687                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 688                 if (rc) {
 689                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 690                         return;
 691                 }
 692         }
 693
 694         /* Dump the IdleMask before we send hint to SMU */
 695         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 696         msg = amd_pmc_get_os_hint(pdev);
 697         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 698         if (rc) {
 699                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 700                 return;
 701         }
 702
 703         if (enable_stb) {
 704                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);
 705                 if (rc)
 706                         dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 707         }
 708 }
 709
 710 static void amd_pmc_s2idle_restore(void)
 711 {
 712         struct amd_pmc_dev *pdev = &pmc;
 713         int rc;
 714         u8 msg;
 715
 716         msg = amd_pmc_get_os_hint(pdev);
 717         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 718         if (rc)
 719                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 720
 721         /* Let SMU know that we are looking for stats */
 722         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 723
 724         /* Dump the IdleMask to see the blockers */
 725         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 726
 727         /* Write data incremented by 1 to distinguish in stb_read */
 728         if (enable_stb) {
 729                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);
 730                 if (rc)
 731                         dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 732         }
 733
 734         /* Notify on failed entry */
 735         amd_pmc_validate_deepest(pdev);
 736 }
 737
 738 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 739         .prepare = amd_pmc_s2idle_prepare,
 740         .restore = amd_pmc_s2idle_restore,
 741 };
 742 #endif
 743
 744 static const struct pci_device_id pmc_pci_ids[] = {
 745         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
 746         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
 747         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 748         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 749         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 750         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 751         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 752         { }
 753 };
 754
 755 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 756 {
 757         u32 phys_addr_low, phys_addr_hi;
 758         u64 stb_phys_addr;
 759         u32 size = 0;
 760
 761         /* Spill to DRAM feature uses separate SMU message port */
 762         dev->msg_port = 1;
 763
 764         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
 765         if (size != S2D_TELEMETRY_BYTES_MAX)
 766                 return -EIO;
 767
 768         /* Get STB DRAM address */
 769         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
 770         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
 771
 772         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 773
 774         /* Clear msg_port for other SMU operation */
 775         dev->msg_port = 0;
 776
 777         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
 778         if (!dev->stb_virt_addr)
 779                 return -ENOMEM;
 780
 781         return 0;
 782 }
 783
 784 #ifdef CONFIG_SUSPEND
 785 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 786 {
 787         int err;
 788
 789         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 790         if (err) {
 791                 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
 792                         AMD_PMC_STB_INDEX_ADDRESS);
 793                 return pcibios_err_to_errno(err);
 794         }
 795
 796         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
 797         if (err) {
 798                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
 799                         AMD_PMC_STB_INDEX_DATA);
 800                 return pcibios_err_to_errno(err);
 801         }
 802
 803         return 0;
 804 }
 805 #endif
 806
 807 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 808 {
 809         int i, err;
 810
 811         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 812         if (err) {
 813                 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
 814                         AMD_PMC_STB_INDEX_ADDRESS);
 815                 return pcibios_err_to_errno(err);
 816         }
 817
 818         for (i = 0; i < FIFO_SIZE; i++) {
 819                 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
 820                 if (err) {
 821                         dev_err(dev->dev, "error reading data from stb: 0x%X\n",
 822                                 AMD_PMC_STB_INDEX_DATA);
 823                         return pcibios_err_to_errno(err);
 824                 }
 825         }
 826
 827         return 0;
 828 }
 829
 830 static int amd_pmc_probe(struct platform_device *pdev)
 831 {
 832         struct amd_pmc_dev *dev = &pmc;
 833         struct pci_dev *rdev;
 834         u32 base_addr_lo, base_addr_hi;
 835         u64 base_addr;
 836         int err;
 837         u32 val;
 838
 839         dev->dev = &pdev->dev;
 840
 841         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 842         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 843                 err = -ENODEV;
 844                 goto err_pci_dev_put;
 845         }
 846
 847         dev->cpu_id = rdev->device;
 848         dev->rdev = rdev;
 849         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 850         if (err) {
 851                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 852                 err = pcibios_err_to_errno(err);
 853                 goto err_pci_dev_put;
 854         }
 855
 856         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 857         if (err) {
 858                 err = pcibios_err_to_errno(err);
 859                 goto err_pci_dev_put;
 860         }
 861
 862         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 863
 864         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 865         if (err) {
 866                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 867                 err = pcibios_err_to_errno(err);
 868                 goto err_pci_dev_put;
 869         }
 870
 871         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 872         if (err) {
 873                 err = pcibios_err_to_errno(err);
 874                 goto err_pci_dev_put;
 875         }
 876
 877         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 878         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 879
 880         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 881                                     AMD_PMC_MAPPING_SIZE);
 882         if (!dev->regbase) {
 883                 err = -ENOMEM;
 884                 goto err_pci_dev_put;
 885         }
 886
 887         mutex_init(&dev->lock);
 888
 889         if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
 890                 err = amd_pmc_s2d_init(dev);
 891                 if (err)
 892                         return err;
 893         }
 894
 895         platform_set_drvdata(pdev, dev);
 896 #ifdef CONFIG_SUSPEND
 897         err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
 898         if (err)
 899                 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
 900 #endif
 901
 902         amd_pmc_dbgfs_register(dev);
 903         return 0;
 904
 905 err_pci_dev_put:
 906         pci_dev_put(rdev);
 907         return err;
 908 }
 909
 910 static int amd_pmc_remove(struct platform_device *pdev)
 911 {
 912         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
 913
 914 #ifdef CONFIG_SUSPEND
 915         acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
 916 #endif
 917         amd_pmc_dbgfs_unregister(dev);
 918         pci_dev_put(dev->rdev);
 919         mutex_destroy(&dev->lock);
 920         return 0;
 921 }
 922
 923 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 924         {"AMDI0005", 0},
 925         {"AMDI0006", 0},
 926         {"AMDI0007", 0},
 927         {"AMDI0008", 0},
 928         {"AMD0004", 0},
 929         {"AMD0005", 0},
 930         { }
 931 };
 932 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
 933
 934 static struct platform_driver amd_pmc_driver = {
 935         .driver = {
 936                 .name = "amd_pmc",
 937                 .acpi_match_table = amd_pmc_acpi_ids,
 938         },
 939         .probe = amd_pmc_probe,
 940         .remove = amd_pmc_remove,
 941 };
 942 module_platform_driver(amd_pmc_driver);
 943
 944 MODULE_LICENSE("GPL v2");
 945 MODULE_DESCRIPTION("AMD PMC Driver");