drivers/net/dsa/qca8k.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <[email protected]>
   4  * Copyright (C) 2011-2012 Gabor Juhos <[email protected]>
   5  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #ifndef __QCA8K_H
   9 #define __QCA8K_H
  10
  11 #include <linux/delay.h>
  12 #include <linux/regmap.h>
  13 #include <linux/gpio.h>
  14
  15 #define QCA8K_NUM_PORTS                                 7
  16 #define QCA8K_NUM_CPU_PORTS                             2
  17 #define QCA8K_MAX_MTU                                   9000
  18 #define QCA8K_NUM_LAGS                                  4
  19 #define QCA8K_NUM_PORTS_FOR_LAG                         4
  20
  21 #define PHY_ID_QCA8327                                  0x004dd034
  22 #define QCA8K_ID_QCA8327                                0x12
  23 #define PHY_ID_QCA8337                                  0x004dd036
  24 #define QCA8K_ID_QCA8337                                0x13
  25
  26 #define QCA8K_QCA832X_MIB_COUNT                         39
  27 #define QCA8K_QCA833X_MIB_COUNT                         41
  28
  29 #define QCA8K_BUSY_WAIT_TIMEOUT                         2000
  30
  31 #define QCA8K_NUM_FDB_RECORDS                           2048
  32
  33 #define QCA8K_PORT_VID_DEF                              1
  34
  35 /* Global control registers */
  36 #define QCA8K_REG_MASK_CTRL                             0x000
  37 #define   QCA8K_MASK_CTRL_REV_ID_MASK                   GENMASK(7, 0)
  38 #define   QCA8K_MASK_CTRL_REV_ID(x)                     FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
  39 #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK                GENMASK(15, 8)
  40 #define   QCA8K_MASK_CTRL_DEVICE_ID(x)                  FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
  41 #define QCA8K_REG_PORT0_PAD_CTRL                        0x004
  42 #define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN             BIT(31)
  43 #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE      BIT(19)
  44 #define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE      BIT(18)
  45 #define QCA8K_REG_PORT5_PAD_CTRL                        0x008
  46 #define QCA8K_REG_PORT6_PAD_CTRL                        0x00c
  47 #define   QCA8K_PORT_PAD_RGMII_EN                       BIT(26)
  48 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK            GENMASK(23, 22)
  49 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)              FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
  50 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK            GENMASK(21, 20)
  51 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)              FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
  52 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_EN              BIT(25)
  53 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN              BIT(24)
  54 #define   QCA8K_PORT_PAD_SGMII_EN                       BIT(7)
  55 #define QCA8K_REG_PWS                                   0x010
  56 #define   QCA8K_PWS_POWER_ON_SEL                        BIT(31)
  57 /* This reg is only valid for QCA832x and toggle the package
  58  * type from 176 pin (by default) to 148 pin used on QCA8327
  59  */
  60 #define   QCA8327_PWS_PACKAGE148_EN                     BIT(30)
  61 #define   QCA8K_PWS_LED_OPEN_EN_CSR                     BIT(24)
  62 #define   QCA8K_PWS_SERDES_AEN_DIS                      BIT(7)
  63 #define QCA8K_REG_MODULE_EN                             0x030
  64 #define   QCA8K_MODULE_EN_MIB                           BIT(0)
  65 #define QCA8K_REG_MIB                                   0x034
  66 #define   QCA8K_MIB_FLUSH                               BIT(24)
  67 #define   QCA8K_MIB_CPU_KEEP                            BIT(20)
  68 #define   QCA8K_MIB_BUSY                                BIT(17)
  69 #define QCA8K_MDIO_MASTER_CTRL                          0x3c
  70 #define   QCA8K_MDIO_MASTER_BUSY                        BIT(31)
  71 #define   QCA8K_MDIO_MASTER_EN                          BIT(30)
  72 #define   QCA8K_MDIO_MASTER_READ                        BIT(27)
  73 #define   QCA8K_MDIO_MASTER_WRITE                       0
  74 #define   QCA8K_MDIO_MASTER_SUP_PRE                     BIT(26)
  75 #define   QCA8K_MDIO_MASTER_PHY_ADDR_MASK               GENMASK(25, 21)
  76 #define   QCA8K_MDIO_MASTER_PHY_ADDR(x)                 FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
  77 #define   QCA8K_MDIO_MASTER_REG_ADDR_MASK               GENMASK(20, 16)
  78 #define   QCA8K_MDIO_MASTER_REG_ADDR(x)                 FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
  79 #define   QCA8K_MDIO_MASTER_DATA_MASK                   GENMASK(15, 0)
  80 #define   QCA8K_MDIO_MASTER_DATA(x)                     FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
  81 #define   QCA8K_MDIO_MASTER_MAX_PORTS                   5
  82 #define   QCA8K_MDIO_MASTER_MAX_REG                     32
  83 #define QCA8K_GOL_MAC_ADDR0                             0x60
  84 #define QCA8K_GOL_MAC_ADDR1                             0x64
  85 #define QCA8K_MAX_FRAME_SIZE                            0x78
  86 #define QCA8K_REG_PORT_STATUS(_i)                       (0x07c + (_i) * 4)
  87 #define   QCA8K_PORT_STATUS_SPEED                       GENMASK(1, 0)
  88 #define   QCA8K_PORT_STATUS_SPEED_10                    0
  89 #define   QCA8K_PORT_STATUS_SPEED_100                   0x1
  90 #define   QCA8K_PORT_STATUS_SPEED_1000                  0x2
  91 #define   QCA8K_PORT_STATUS_TXMAC                       BIT(2)
  92 #define   QCA8K_PORT_STATUS_RXMAC                       BIT(3)
  93 #define   QCA8K_PORT_STATUS_TXFLOW                      BIT(4)
  94 #define   QCA8K_PORT_STATUS_RXFLOW                      BIT(5)
  95 #define   QCA8K_PORT_STATUS_DUPLEX                      BIT(6)
  96 #define   QCA8K_PORT_STATUS_LINK_UP                     BIT(8)
  97 #define   QCA8K_PORT_STATUS_LINK_AUTO                   BIT(9)
  98 #define   QCA8K_PORT_STATUS_LINK_PAUSE                  BIT(10)
  99 #define   QCA8K_PORT_STATUS_FLOW_AUTO                   BIT(12)
 100 #define QCA8K_REG_PORT_HDR_CTRL(_i)                     (0x9c + (_i * 4))
 101 #define   QCA8K_PORT_HDR_CTRL_RX_MASK                   GENMASK(3, 2)
 102 #define   QCA8K_PORT_HDR_CTRL_TX_MASK                   GENMASK(1, 0)
 103 #define   QCA8K_PORT_HDR_CTRL_ALL                       2
 104 #define   QCA8K_PORT_HDR_CTRL_MGMT                      1
 105 #define   QCA8K_PORT_HDR_CTRL_NONE                      0
 106 #define QCA8K_REG_SGMII_CTRL                            0x0e0
 107 #define   QCA8K_SGMII_EN_PLL                            BIT(1)
 108 #define   QCA8K_SGMII_EN_RX                             BIT(2)
 109 #define   QCA8K_SGMII_EN_TX                             BIT(3)
 110 #define   QCA8K_SGMII_EN_SD                             BIT(4)
 111 #define   QCA8K_SGMII_CLK125M_DELAY                     BIT(7)
 112 #define   QCA8K_SGMII_MODE_CTRL_MASK                    GENMASK(23, 22)
 113 #define   QCA8K_SGMII_MODE_CTRL(x)                      FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
 114 #define   QCA8K_SGMII_MODE_CTRL_BASEX                   QCA8K_SGMII_MODE_CTRL(0x0)
 115 #define   QCA8K_SGMII_MODE_CTRL_PHY                     QCA8K_SGMII_MODE_CTRL(0x1)
 116 #define   QCA8K_SGMII_MODE_CTRL_MAC                     QCA8K_SGMII_MODE_CTRL(0x2)
 117
 118 /* MAC_PWR_SEL registers */
 119 #define QCA8K_REG_MAC_PWR_SEL                           0x0e4
 120 #define   QCA8K_MAC_PWR_RGMII1_1_8V                     BIT(18)
 121 #define   QCA8K_MAC_PWR_RGMII0_1_8V                     BIT(19)
 122
 123 /* EEE control registers */
 124 #define QCA8K_REG_EEE_CTRL                              0x100
 125 #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)                  ((_i + 1) * 2)
 126
 127 /* TRUNK_HASH_EN registers */
 128 #define QCA8K_TRUNK_HASH_EN_CTRL                        0x270
 129 #define   QCA8K_TRUNK_HASH_SIP_EN                       BIT(3)
 130 #define   QCA8K_TRUNK_HASH_DIP_EN                       BIT(2)
 131 #define   QCA8K_TRUNK_HASH_SA_EN                        BIT(1)
 132 #define   QCA8K_TRUNK_HASH_DA_EN                        BIT(0)
 133 #define   QCA8K_TRUNK_HASH_MASK                         GENMASK(3, 0)
 134
 135 /* ACL registers */
 136 #define QCA8K_REG_PORT_VLAN_CTRL0(_i)                   (0x420 + (_i * 8))
 137 #define   QCA8K_PORT_VLAN_CVID_MASK                     GENMASK(27, 16)
 138 #define   QCA8K_PORT_VLAN_CVID(x)                       FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
 139 #define   QCA8K_PORT_VLAN_SVID_MASK                     GENMASK(11, 0)
 140 #define   QCA8K_PORT_VLAN_SVID(x)                       FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
 141 #define QCA8K_REG_PORT_VLAN_CTRL1(_i)                   (0x424 + (_i * 8))
 142 #define QCA8K_REG_IPV4_PRI_BASE_ADDR                    0x470
 143 #define QCA8K_REG_IPV4_PRI_ADDR_MASK                    0x474
 144
 145 /* Lookup registers */
 146 #define QCA8K_REG_ATU_DATA0                             0x600
 147 #define   QCA8K_ATU_ADDR2_MASK                          GENMASK(31, 24)
 148 #define   QCA8K_ATU_ADDR3_MASK                          GENMASK(23, 16)
 149 #define   QCA8K_ATU_ADDR4_MASK                          GENMASK(15, 8)
 150 #define   QCA8K_ATU_ADDR5_MASK                          GENMASK(7, 0)
 151 #define QCA8K_REG_ATU_DATA1                             0x604
 152 #define   QCA8K_ATU_PORT_MASK                           GENMASK(22, 16)
 153 #define   QCA8K_ATU_ADDR0_MASK                          GENMASK(15, 8)
 154 #define   QCA8K_ATU_ADDR1_MASK                          GENMASK(7, 0)
 155 #define QCA8K_REG_ATU_DATA2                             0x608
 156 #define   QCA8K_ATU_VID_MASK                            GENMASK(19, 8)
 157 #define   QCA8K_ATU_STATUS_MASK                         GENMASK(3, 0)
 158 #define   QCA8K_ATU_STATUS_STATIC                       0xf
 159 #define QCA8K_REG_ATU_FUNC                              0x60c
 160 #define   QCA8K_ATU_FUNC_BUSY                           BIT(31)
 161 #define   QCA8K_ATU_FUNC_PORT_EN                        BIT(14)
 162 #define   QCA8K_ATU_FUNC_MULTI_EN                       BIT(13)
 163 #define   QCA8K_ATU_FUNC_FULL                           BIT(12)
 164 #define   QCA8K_ATU_FUNC_PORT_MASK                      GENMASK(11, 8)
 165 #define QCA8K_REG_VTU_FUNC0                             0x610
 166 #define   QCA8K_VTU_FUNC0_VALID                         BIT(20)
 167 #define   QCA8K_VTU_FUNC0_IVL_EN                        BIT(19)
 168 /*        QCA8K_VTU_FUNC0_EG_MODE_MASK                  GENMASK(17, 4)
 169  *          It does contain VLAN_MODE for each port [5:4] for port0,
 170  *          [7:6] for port1 ... [17:16] for port6. Use virtual port
 171  *          define to handle this.
 172  */
 173 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)        (4 + (_i) * 2)
 174 #define   QCA8K_VTU_FUNC0_EG_MODE_MASK                  GENMASK(1, 0)
 175 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i)         (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 176 #define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD                 FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
 177 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i)        (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 178 #define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG                 FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
 179 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i)        (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 180 #define   QCA8K_VTU_FUNC0_EG_MODE_TAG                   FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
 181 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i)          (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 182 #define   QCA8K_VTU_FUNC0_EG_MODE_NOT                   FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
 183 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i)          (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 184 #define QCA8K_REG_VTU_FUNC1                             0x614
 185 #define   QCA8K_VTU_FUNC1_BUSY                          BIT(31)
 186 #define   QCA8K_VTU_FUNC1_VID_MASK                      GENMASK(27, 16)
 187 #define   QCA8K_VTU_FUNC1_FULL                          BIT(4)
 188 #define QCA8K_REG_ATU_CTRL                              0x618
 189 #define   QCA8K_ATU_AGE_TIME_MASK                       GENMASK(15, 0)
 190 #define   QCA8K_ATU_AGE_TIME(x)                         FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
 191 #define QCA8K_REG_GLOBAL_FW_CTRL0                       0x620
 192 #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN             BIT(10)
 193 #define   QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM         GENMASK(7, 4)
 194 #define QCA8K_REG_GLOBAL_FW_CTRL1                       0x624
 195 #define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK            GENMASK(30, 24)
 196 #define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK              GENMASK(22, 16)
 197 #define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK              GENMASK(14, 8)
 198 #define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK              GENMASK(6, 0)
 199 #define QCA8K_PORT_LOOKUP_CTRL(_i)                      (0x660 + (_i) * 0xc)
 200 #define   QCA8K_PORT_LOOKUP_MEMBER                      GENMASK(6, 0)
 201 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_MASK              GENMASK(9, 8)
 202 #define   QCA8K_PORT_LOOKUP_VLAN_MODE(x)                FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
 203 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE              QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
 204 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK          QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
 205 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK             QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
 206 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE            QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
 207 #define   QCA8K_PORT_LOOKUP_STATE_MASK                  GENMASK(18, 16)
 208 #define   QCA8K_PORT_LOOKUP_STATE(x)                    FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
 209 #define   QCA8K_PORT_LOOKUP_STATE_DISABLED              QCA8K_PORT_LOOKUP_STATE(0x0)
 210 #define   QCA8K_PORT_LOOKUP_STATE_BLOCKING              QCA8K_PORT_LOOKUP_STATE(0x1)
 211 #define   QCA8K_PORT_LOOKUP_STATE_LISTENING             QCA8K_PORT_LOOKUP_STATE(0x2)
 212 #define   QCA8K_PORT_LOOKUP_STATE_LEARNING              QCA8K_PORT_LOOKUP_STATE(0x3)
 213 #define   QCA8K_PORT_LOOKUP_STATE_FORWARD               QCA8K_PORT_LOOKUP_STATE(0x4)
 214 #define   QCA8K_PORT_LOOKUP_LEARN                       BIT(20)
 215 #define   QCA8K_PORT_LOOKUP_ING_MIRROR_EN               BIT(25)
 216
 217 #define QCA8K_REG_GOL_TRUNK_CTRL0                       0x700
 218 /* 4 max trunk first
 219  * first 6 bit for member bitmap
 220  * 7th bit is to enable trunk port
 221  */
 222 #define QCA8K_REG_GOL_TRUNK_SHIFT(_i)                   ((_i) * 8)
 223 #define QCA8K_REG_GOL_TRUNK_EN_MASK                     BIT(7)
 224 #define QCA8K_REG_GOL_TRUNK_EN(_i)                      (QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
 225 #define QCA8K_REG_GOL_TRUNK_MEMBER_MASK                 GENMASK(6, 0)
 226 #define QCA8K_REG_GOL_TRUNK_MEMBER(_i)                  (QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
 227 /* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
 228 #define QCA8K_REG_GOL_TRUNK_CTRL(_i)                    (0x704 + (((_i) / 2) * 4))
 229 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK              GENMASK(3, 0)
 230 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK           BIT(3)
 231 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK         GENMASK(2, 0)
 232 #define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i)                (((_i) / 2) * 16)
 233 #define QCA8K_REG_GOL_MEM_ID_SHIFT(_i)                  ((_i) * 4)
 234 /* Complex shift: FIRST shift for port THEN shift for trunk */
 235 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j)     (QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))
 236 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j)        (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
 237 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j)      (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
 238
 239 #define QCA8K_REG_GLOBAL_FC_THRESH                      0x800
 240 #define   QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK            GENMASK(24, 16)
 241 #define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)              FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
 242 #define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK           GENMASK(8, 0)
 243 #define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)             FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
 244
 245 #define QCA8K_REG_PORT_HOL_CTRL0(_i)                    (0x970 + (_i) * 0x8)
 246 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK         GENMASK(3, 0)
 247 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
 248 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK         GENMASK(7, 4)
 249 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
 250 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK         GENMASK(11, 8)
 251 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
 252 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK         GENMASK(15, 12)
 253 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
 254 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK         GENMASK(19, 16)
 255 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
 256 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK         GENMASK(23, 20)
 257 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
 258 #define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK         GENMASK(29, 24)
 259 #define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
 260
 261 #define QCA8K_REG_PORT_HOL_CTRL1(_i)                    (0x974 + (_i) * 0x8)
 262 #define   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK             GENMASK(3, 0)
 263 #define   QCA8K_PORT_HOL_CTRL1_ING(x)                   FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
 264 #define   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN            BIT(6)
 265 #define   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN           BIT(7)
 266 #define   QCA8K_PORT_HOL_CTRL1_WRED_EN                  BIT(8)
 267 #define   QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN             BIT(16)
 268
 269 /* Pkt edit registers */
 270 #define QCA8K_EGREES_VLAN_PORT_SHIFT(_i)                (16 * ((_i) % 2))
 271 #define QCA8K_EGREES_VLAN_PORT_MASK(_i)                 (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
 272 #define QCA8K_EGREES_VLAN_PORT(_i, x)                   ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
 273 #define QCA8K_EGRESS_VLAN(x)                            (0x0c70 + (4 * (x / 2)))
 274
 275 /* L3 registers */
 276 #define QCA8K_HROUTER_CONTROL                           0xe00
 277 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M          GENMASK(17, 16)
 278 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S          16
 279 #define   QCA8K_HROUTER_CONTROL_ARP_AGE_MODE            1
 280 #define QCA8K_HROUTER_PBASED_CONTROL1                   0xe08
 281 #define QCA8K_HROUTER_PBASED_CONTROL2                   0xe0c
 282 #define QCA8K_HNAT_CONTROL                              0xe38
 283
 284 /* MIB registers */
 285 #define QCA8K_PORT_MIB_COUNTER(_i)                      (0x1000 + (_i) * 0x100)
 286
 287 /* QCA specific MII registers */
 288 #define MII_ATH_MMD_ADDR                                0x0d
 289 #define MII_ATH_MMD_DATA                                0x0e
 290
 291 enum {
 292         QCA8K_PORT_SPEED_10M = 0,
 293         QCA8K_PORT_SPEED_100M = 1,
 294         QCA8K_PORT_SPEED_1000M = 2,
 295         QCA8K_PORT_SPEED_ERR = 3,
 296 };
 297
 298 enum qca8k_fdb_cmd {
 299         QCA8K_FDB_FLUSH = 1,
 300         QCA8K_FDB_LOAD = 2,
 301         QCA8K_FDB_PURGE = 3,
 302         QCA8K_FDB_FLUSH_PORT = 5,
 303         QCA8K_FDB_NEXT = 6,
 304         QCA8K_FDB_SEARCH = 7,
 305 };
 306
 307 enum qca8k_vlan_cmd {
 308         QCA8K_VLAN_FLUSH = 1,
 309         QCA8K_VLAN_LOAD = 2,
 310         QCA8K_VLAN_PURGE = 3,
 311         QCA8K_VLAN_REMOVE_PORT = 4,
 312         QCA8K_VLAN_NEXT = 5,
 313         QCA8K_VLAN_READ = 6,
 314 };
 315
 316 struct ar8xxx_port_status {
 317         int enabled;
 318 };
 319
 320 struct qca8k_match_data {
 321         u8 id;
 322         bool reduced_package;
 323         u8 mib_count;
 324 };
 325
 326 enum {
 327         QCA8K_CPU_PORT0,
 328         QCA8K_CPU_PORT6,
 329 };
 330
 331 struct qca8k_ports_config {
 332         bool sgmii_rx_clk_falling_edge;
 333         bool sgmii_tx_clk_falling_edge;
 334         bool sgmii_enable_pll;
 335         u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
 336         u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
 337 };
 338
 339 struct qca8k_priv {
 340         u8 switch_id;
 341         u8 switch_revision;
 342         u8 mirror_rx;
 343         u8 mirror_tx;
 344         u8 lag_hash_mode;
 345         bool legacy_phy_port_mapping;
 346         struct qca8k_ports_config ports_config;
 347         struct regmap *regmap;
 348         struct mii_bus *bus;
 349         struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
 350         struct dsa_switch *ds;
 351         struct mutex reg_mutex;
 352         struct device *dev;
 353         struct dsa_switch_ops ops;
 354         struct gpio_desc *reset_gpio;
 355         unsigned int port_mtu[QCA8K_NUM_PORTS];
 356 };
 357
 358 struct qca8k_mib_desc {
 359         unsigned int size;
 360         unsigned int offset;
 361         const char *name;
 362 };
 363
 364 struct qca8k_fdb {
 365         u16 vid;
 366         u8 port_mask;
 367         u8 aging;
 368         u8 mac[6];
 369 };
 370
 371 #endif /* __QCA8K_H */