drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/uaccess.h>
  27
  28 #include "dc.h"
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "amdgpu_dm_debugfs.h"
  32 #include "dm_helpers.h"
  33 #include "dmub/dmub_srv.h"
  34 #include "resource.h"
  35 #include "dsc.h"
  36 #include "dc_link_dp.h"
  37 #include "link_hwss.h"
  38 #include "dc/dc_dmub_srv.h"
  39
  40 struct dmub_debugfs_trace_header {
  41         uint32_t entry_count;
  42         uint32_t reserved[3];
  43 };
  44
  45 struct dmub_debugfs_trace_entry {
  46         uint32_t trace_code;
  47         uint32_t tick_count;
  48         uint32_t param0;
  49         uint32_t param1;
  50 };
  51
  52 static inline const char *yesno(bool v)
  53 {
  54         return v ? "yes" : "no";
  55 }
  56
  57 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  58  *
  59  * Function takes in attributes passed to debugfs write entry
  60  * and writes into param array.
  61  * The user passes max_param_num to identify maximum number of
  62  * parameters that could be parsed.
  63  *
  64  */
  65 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  66                                           long *param, const char __user *buf,
  67                                           int max_param_num,
  68                                           uint8_t *param_nums)
  69 {
  70         char *wr_buf_ptr = NULL;
  71         uint32_t wr_buf_count = 0;
  72         int r;
  73         char *sub_str = NULL;
  74         const char delimiter[3] = {' ', '\n', '\0'};
  75         uint8_t param_index = 0;
  76
  77         *param_nums = 0;
  78
  79         wr_buf_ptr = wr_buf;
  80
  81         r = copy_from_user(wr_buf_ptr, buf, wr_buf_size);
  82
  83                 /* r is bytes not be copied */
  84         if (r >= wr_buf_size) {
  85                 DRM_DEBUG_DRIVER("user data not be read\n");
  86                 return -EINVAL;
  87         }
  88
  89         /* check number of parameters. isspace could not differ space and \n */
  90         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  91                 /* skip space*/
  92                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  93                         wr_buf_ptr++;
  94                         wr_buf_count++;
  95                         }
  96
  97                 if (wr_buf_count == wr_buf_size)
  98                         break;
  99
 100                 /* skip non-space*/
 101                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 102                         wr_buf_ptr++;
 103                         wr_buf_count++;
 104                 }
 105
 106                 (*param_nums)++;
 107
 108                 if (wr_buf_count == wr_buf_size)
 109                         break;
 110         }
 111
 112         if (*param_nums > max_param_num)
 113                 *param_nums = max_param_num;
 114
 115         wr_buf_ptr = wr_buf; /* reset buf pointer */
 116         wr_buf_count = 0; /* number of char already checked */
 117
 118         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 119                 wr_buf_ptr++;
 120                 wr_buf_count++;
 121         }
 122
 123         while (param_index < *param_nums) {
 124                 /* after strsep, wr_buf_ptr will be moved to after space */
 125                 sub_str = strsep(&wr_buf_ptr, delimiter);
 126
 127                 r = kstrtol(sub_str, 16, &(param[param_index]));
 128
 129                 if (r)
 130                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 131
 132                 param_index++;
 133         }
 134
 135         return 0;
 136 }
 137
 138 /* function description
 139  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 140  *
 141  * valid lane count value: 1, 2, 4
 142  * valid link rate value:
 143  * 06h = 1.62Gbps per lane
 144  * 0Ah = 2.7Gbps per lane
 145  * 0Ch = 3.24Gbps per lane
 146  * 14h = 5.4Gbps per lane
 147  * 1Eh = 8.1Gbps per lane
 148  *
 149  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 150  *
 151  * --- to get dp configuration
 152  *
 153  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 154  *
 155  * It will list current, verified, reported, preferred dp configuration.
 156  * current -- for current video mode
 157  * verified --- maximum configuration which pass link training
 158  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 159  * preferred --- user force settings
 160  *
 161  * --- set (or force) dp configuration
 162  *
 163  * echo <lane_count>  <link_rate> > link_settings
 164  *
 165  * for example, to force to  2 lane, 2.7GHz,
 166  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 167  *
 168  * spread_spectrum could not be changed dynamically.
 169  *
 170  * in case invalid lane count, link rate are force, no hw programming will be
 171  * done. please check link settings after force operation to see if HW get
 172  * programming.
 173  *
 174  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 175  *
 176  * check current and preferred settings.
 177  *
 178  */
 179 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 180                                  size_t size, loff_t *pos)
 181 {
 182         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 183         struct dc_link *link = connector->dc_link;
 184         char *rd_buf = NULL;
 185         char *rd_buf_ptr = NULL;
 186         const uint32_t rd_buf_size = 100;
 187         uint32_t result = 0;
 188         uint8_t str_len = 0;
 189         int r;
 190
 191         if (*pos & 3 || size & 3)
 192                 return -EINVAL;
 193
 194         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 195         if (!rd_buf)
 196                 return 0;
 197
 198         rd_buf_ptr = rd_buf;
 199
 200         str_len = strlen("Current:  %d  %d  %d  ");
 201         snprintf(rd_buf_ptr, str_len, "Current:  %d  %d  %d  ",
 202                         link->cur_link_settings.lane_count,
 203                         link->cur_link_settings.link_rate,
 204                         link->cur_link_settings.link_spread);
 205         rd_buf_ptr += str_len;
 206
 207         str_len = strlen("Verified:  %d  %d  %d  ");
 208         snprintf(rd_buf_ptr, str_len, "Verified:  %d  %d  %d  ",
 209                         link->verified_link_cap.lane_count,
 210                         link->verified_link_cap.link_rate,
 211                         link->verified_link_cap.link_spread);
 212         rd_buf_ptr += str_len;
 213
 214         str_len = strlen("Reported:  %d  %d  %d  ");
 215         snprintf(rd_buf_ptr, str_len, "Reported:  %d  %d  %d  ",
 216                         link->reported_link_cap.lane_count,
 217                         link->reported_link_cap.link_rate,
 218                         link->reported_link_cap.link_spread);
 219         rd_buf_ptr += str_len;
 220
 221         str_len = strlen("Preferred:  %d  %d  %d  ");
 222         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  %d  %d\n",
 223                         link->preferred_link_setting.lane_count,
 224                         link->preferred_link_setting.link_rate,
 225                         link->preferred_link_setting.link_spread);
 226
 227         while (size) {
 228                 if (*pos >= rd_buf_size)
 229                         break;
 230
 231                 r = put_user(*(rd_buf + result), buf);
 232                 if (r)
 233                         return r; /* r = -EFAULT */
 234
 235                 buf += 1;
 236                 size -= 1;
 237                 *pos += 1;
 238                 result += 1;
 239         }
 240
 241         kfree(rd_buf);
 242         return result;
 243 }
 244
 245 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 246                                  size_t size, loff_t *pos)
 247 {
 248         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 249         struct dc_link *link = connector->dc_link;
 250         struct dc_link_settings prefer_link_settings;
 251         char *wr_buf = NULL;
 252         const uint32_t wr_buf_size = 40;
 253         /* 0: lane_count; 1: link_rate */
 254         int max_param_num = 2;
 255         uint8_t param_nums = 0;
 256         long param[2];
 257         bool valid_input = true;
 258
 259         if (size == 0)
 260                 return -EINVAL;
 261
 262         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 263         if (!wr_buf)
 264                 return -ENOSPC;
 265
 266         if (parse_write_buffer_into_params(wr_buf, size,
 267                                            (long *)param, buf,
 268                                            max_param_num,
 269                                            &param_nums)) {
 270                 kfree(wr_buf);
 271                 return -EINVAL;
 272         }
 273
 274         if (param_nums <= 0) {
 275                 kfree(wr_buf);
 276                 DRM_DEBUG_DRIVER("user data not be read\n");
 277                 return -EINVAL;
 278         }
 279
 280         switch (param[0]) {
 281         case LANE_COUNT_ONE:
 282         case LANE_COUNT_TWO:
 283         case LANE_COUNT_FOUR:
 284                 break;
 285         default:
 286                 valid_input = false;
 287                 break;
 288         }
 289
 290         switch (param[1]) {
 291         case LINK_RATE_LOW:
 292         case LINK_RATE_HIGH:
 293         case LINK_RATE_RBR2:
 294         case LINK_RATE_HIGH2:
 295         case LINK_RATE_HIGH3:
 296                 break;
 297         default:
 298                 valid_input = false;
 299                 break;
 300         }
 301
 302         if (!valid_input) {
 303                 kfree(wr_buf);
 304                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 305                 return size;
 306         }
 307
 308         /* save user force lane_count, link_rate to preferred settings
 309          * spread spectrum will not be changed
 310          */
 311         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 312         prefer_link_settings.use_link_rate_set = false;
 313         prefer_link_settings.lane_count = param[0];
 314         prefer_link_settings.link_rate = param[1];
 315
 316         dp_retrain_link_dp_test(link, &prefer_link_settings, false);
 317
 318         kfree(wr_buf);
 319         return size;
 320 }
 321
 322 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 323  * post-cursor2 (defined by VESA DP specification)
 324  *
 325  * valid values
 326  * voltage swing: 0,1,2,3
 327  * pre-emphasis : 0,1,2,3
 328  * post cursor2 : 0,1,2,3
 329  *
 330  *
 331  * how to use this debugfs
 332  *
 333  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 334  *
 335  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 336  *
 337  * To figure out which DP-x is the display for DP to be check,
 338  * cd DP-x
 339  * ls -ll
 340  * There should be debugfs file, like link_settings, phy_settings.
 341  * cat link_settings
 342  * from lane_count, link_rate to figure which DP-x is for display to be worked
 343  * on
 344  *
 345  * To get current DP PHY settings,
 346  * cat phy_settings
 347  *
 348  * To change DP PHY settings,
 349  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 350  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 351  * 0,
 352  * echo 2 3 0 > phy_settings
 353  *
 354  * To check if change be applied, get current phy settings by
 355  * cat phy_settings
 356  *
 357  * In case invalid values are set by user, like
 358  * echo 1 4 0 > phy_settings
 359  *
 360  * HW will NOT be programmed by these settings.
 361  * cat phy_settings will show the previous valid settings.
 362  */
 363 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 364                                  size_t size, loff_t *pos)
 365 {
 366         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 367         struct dc_link *link = connector->dc_link;
 368         char *rd_buf = NULL;
 369         const uint32_t rd_buf_size = 20;
 370         uint32_t result = 0;
 371         int r;
 372
 373         if (*pos & 3 || size & 3)
 374                 return -EINVAL;
 375
 376         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 377         if (!rd_buf)
 378                 return -EINVAL;
 379
 380         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d  ",
 381                         link->cur_lane_setting.VOLTAGE_SWING,
 382                         link->cur_lane_setting.PRE_EMPHASIS,
 383                         link->cur_lane_setting.POST_CURSOR2);
 384
 385         while (size) {
 386                 if (*pos >= rd_buf_size)
 387                         break;
 388
 389                 r = put_user((*(rd_buf + result)), buf);
 390                 if (r)
 391                         return r; /* r = -EFAULT */
 392
 393                 buf += 1;
 394                 size -= 1;
 395                 *pos += 1;
 396                 result += 1;
 397         }
 398
 399         kfree(rd_buf);
 400         return result;
 401 }
 402
 403 static int dp_lttpr_status_show(struct seq_file *m, void *d)
 404 {
 405         char *data;
 406         struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private;
 407         struct dc_link *link = connector->dc_link;
 408         uint32_t read_size = 1;
 409         uint8_t repeater_count = 0;
 410
 411         data = kzalloc(read_size, GFP_KERNEL);
 412         if (!data)
 413                 return 0;
 414
 415         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size);
 416
 417         switch ((uint8_t)*data) {
 418         case 0x80:
 419                 repeater_count = 1;
 420                 break;
 421         case 0x40:
 422                 repeater_count = 2;
 423                 break;
 424         case 0x20:
 425                 repeater_count = 3;
 426                 break;
 427         case 0x10:
 428                 repeater_count = 4;
 429                 break;
 430         case 0x8:
 431                 repeater_count = 5;
 432                 break;
 433         case 0x4:
 434                 repeater_count = 6;
 435                 break;
 436         case 0x2:
 437                 repeater_count = 7;
 438                 break;
 439         case 0x1:
 440                 repeater_count = 8;
 441                 break;
 442         case 0x0:
 443                 repeater_count = 0;
 444                 break;
 445         default:
 446                 repeater_count = (uint8_t)*data;
 447                 break;
 448         }
 449
 450         seq_printf(m, "phy repeater count: %d\n", repeater_count);
 451
 452         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size);
 453
 454         if ((uint8_t)*data == 0x55)
 455                 seq_printf(m, "phy repeater mode: transparent\n");
 456         else if ((uint8_t)*data == 0xAA)
 457                 seq_printf(m, "phy repeater mode: non-transparent\n");
 458         else if ((uint8_t)*data == 0x00)
 459                 seq_printf(m, "phy repeater mode: non lttpr\n");
 460         else
 461                 seq_printf(m, "phy repeater mode: read error\n");
 462
 463         kfree(data);
 464         return 0;
 465 }
 466
 467 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 468                                  size_t size, loff_t *pos)
 469 {
 470         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 471         struct dc_link *link = connector->dc_link;
 472         struct dc *dc = (struct dc *)link->dc;
 473         char *wr_buf = NULL;
 474         uint32_t wr_buf_size = 40;
 475         long param[3];
 476         bool use_prefer_link_setting;
 477         struct link_training_settings link_lane_settings;
 478         int max_param_num = 3;
 479         uint8_t param_nums = 0;
 480         int r = 0;
 481
 482
 483         if (size == 0)
 484                 return -EINVAL;
 485
 486         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 487         if (!wr_buf)
 488                 return -ENOSPC;
 489
 490         if (parse_write_buffer_into_params(wr_buf, size,
 491                                            (long *)param, buf,
 492                                            max_param_num,
 493                                            &param_nums)) {
 494                 kfree(wr_buf);
 495                 return -EINVAL;
 496         }
 497
 498         if (param_nums <= 0) {
 499                 kfree(wr_buf);
 500                 DRM_DEBUG_DRIVER("user data not be read\n");
 501                 return -EINVAL;
 502         }
 503
 504         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 505                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 506                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 507                 kfree(wr_buf);
 508                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 509                 return size;
 510         }
 511
 512         /* get link settings: lane count, link rate */
 513         use_prefer_link_setting =
 514                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 515                 (link->test_pattern_enabled));
 516
 517         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 518
 519         if (use_prefer_link_setting) {
 520                 link_lane_settings.link_settings.lane_count =
 521                                 link->preferred_link_setting.lane_count;
 522                 link_lane_settings.link_settings.link_rate =
 523                                 link->preferred_link_setting.link_rate;
 524                 link_lane_settings.link_settings.link_spread =
 525                                 link->preferred_link_setting.link_spread;
 526         } else {
 527                 link_lane_settings.link_settings.lane_count =
 528                                 link->cur_link_settings.lane_count;
 529                 link_lane_settings.link_settings.link_rate =
 530                                 link->cur_link_settings.link_rate;
 531                 link_lane_settings.link_settings.link_spread =
 532                                 link->cur_link_settings.link_spread;
 533         }
 534
 535         /* apply phy settings from user */
 536         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 537                 link_lane_settings.lane_settings[r].VOLTAGE_SWING =
 538                                 (enum dc_voltage_swing) (param[0]);
 539                 link_lane_settings.lane_settings[r].PRE_EMPHASIS =
 540                                 (enum dc_pre_emphasis) (param[1]);
 541                 link_lane_settings.lane_settings[r].POST_CURSOR2 =
 542                                 (enum dc_post_cursor2) (param[2]);
 543         }
 544
 545         /* program ASIC registers and DPCD registers */
 546         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 547
 548         kfree(wr_buf);
 549         return size;
 550 }
 551
 552 /* function description
 553  *
 554  * set PHY layer or Link layer test pattern
 555  * PHY test pattern is used for PHY SI check.
 556  * Link layer test will not affect PHY SI.
 557  *
 558  * Reset Test Pattern:
 559  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 560  *
 561  * PHY test pattern supported:
 562  * 1 = DP_TEST_PATTERN_D102
 563  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 564  * 3 = DP_TEST_PATTERN_PRBS7
 565  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 566  * 5 = DP_TEST_PATTERN_CP2520_1
 567  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 568  * 7 = DP_TEST_PATTERN_CP2520_3
 569  *
 570  * DP PHY Link Training Patterns
 571  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 572  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 573  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 574  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 575  *
 576  * DP Link Layer Test pattern
 577  * c = DP_TEST_PATTERN_COLOR_SQUARES
 578  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 579  * e = DP_TEST_PATTERN_VERTICAL_BARS
 580  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 581  * 10= DP_TEST_PATTERN_COLOR_RAMP
 582  *
 583  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 584  *
 585  * --- set test pattern
 586  * echo <test pattern #> > test_pattern
 587  *
 588  * If test pattern # is not supported, NO HW programming will be done.
 589  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 590  * for the user pattern. input 10 bytes data are separated by space
 591  *
 592  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 593  *
 594  * --- reset test pattern
 595  * echo 0 > test_pattern
 596  *
 597  * --- HPD detection is disabled when set PHY test pattern
 598  *
 599  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 600  * is disable. User could unplug DP display from DP connected and plug scope to
 601  * check test pattern PHY SI.
 602  * If there is need unplug scope and plug DP display back, do steps below:
 603  * echo 0 > phy_test_pattern
 604  * unplug scope
 605  * plug DP display.
 606  *
 607  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 608  * driver could detect "unplug scope" and "plug DP display"
 609  */
 610 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 611                                  size_t size, loff_t *pos)
 612 {
 613         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 614         struct dc_link *link = connector->dc_link;
 615         char *wr_buf = NULL;
 616         uint32_t wr_buf_size = 100;
 617         long param[11] = {0x0};
 618         int max_param_num = 11;
 619         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 620         bool disable_hpd = false;
 621         bool valid_test_pattern = false;
 622         uint8_t param_nums = 0;
 623         /* init with default 80bit custom pattern */
 624         uint8_t custom_pattern[10] = {
 625                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 626                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 627                         };
 628         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 629                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 630         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 631                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 632         struct link_training_settings link_training_settings;
 633         int i;
 634
 635         if (size == 0)
 636                 return -EINVAL;
 637
 638         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 639         if (!wr_buf)
 640                 return -ENOSPC;
 641
 642         if (parse_write_buffer_into_params(wr_buf, size,
 643                                            (long *)param, buf,
 644                                            max_param_num,
 645                                            &param_nums)) {
 646                 kfree(wr_buf);
 647                 return -EINVAL;
 648         }
 649
 650         if (param_nums <= 0) {
 651                 kfree(wr_buf);
 652                 DRM_DEBUG_DRIVER("user data not be read\n");
 653                 return -EINVAL;
 654         }
 655
 656
 657         test_pattern = param[0];
 658
 659         switch (test_pattern) {
 660         case DP_TEST_PATTERN_VIDEO_MODE:
 661         case DP_TEST_PATTERN_COLOR_SQUARES:
 662         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 663         case DP_TEST_PATTERN_VERTICAL_BARS:
 664         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 665         case DP_TEST_PATTERN_COLOR_RAMP:
 666                 valid_test_pattern = true;
 667                 break;
 668
 669         case DP_TEST_PATTERN_D102:
 670         case DP_TEST_PATTERN_SYMBOL_ERROR:
 671         case DP_TEST_PATTERN_PRBS7:
 672         case DP_TEST_PATTERN_80BIT_CUSTOM:
 673         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 674         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 675                 disable_hpd = true;
 676                 valid_test_pattern = true;
 677                 break;
 678
 679         default:
 680                 valid_test_pattern = false;
 681                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 682                 break;
 683         }
 684
 685         if (!valid_test_pattern) {
 686                 kfree(wr_buf);
 687                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 688                 return size;
 689         }
 690
 691         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 692                 for (i = 0; i < 10; i++) {
 693                         if ((uint8_t) param[i + 1] != 0x0)
 694                                 break;
 695                 }
 696
 697                 if (i < 10) {
 698                         /* not use default value */
 699                         for (i = 0; i < 10; i++)
 700                                 custom_pattern[i] = (uint8_t) param[i + 1];
 701                 }
 702         }
 703
 704         /* Usage: set DP physical test pattern using debugfs with normal DP
 705          * panel. Then plug out DP panel and connect a scope to measure
 706          * For normal video mode and test pattern generated from CRCT,
 707          * they are visibile to user. So do not disable HPD.
 708          * Video Mode is also set to clear the test pattern, so enable HPD
 709          * because it might have been disabled after a test pattern was set.
 710          * AUX depends on HPD * sequence dependent, do not move!
 711          */
 712         if (!disable_hpd)
 713                 dc_link_enable_hpd(link);
 714
 715         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 716         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 717         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 718
 719         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 720         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 721         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 722
 723         link_training_settings.link_settings = cur_link_settings;
 724
 725
 726         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 727                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 728                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 729                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 730                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 731                         link_training_settings.link_settings = prefer_link_settings;
 732         }
 733
 734         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 735                 link_training_settings.lane_settings[i] = link->cur_lane_setting;
 736
 737         dc_link_set_test_pattern(
 738                 link,
 739                 test_pattern,
 740                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 741                 &link_training_settings,
 742                 custom_pattern,
 743                 10);
 744
 745         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 746          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 747          * Need disable interrupt to avoid SW driver disable DP output. This is
 748          * done after the test pattern is set.
 749          */
 750         if (valid_test_pattern && disable_hpd)
 751                 dc_link_disable_hpd(link);
 752
 753         kfree(wr_buf);
 754
 755         return size;
 756 }
 757
 758 /*
 759  * Returns the DMCUB tracebuffer contents.
 760  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 761  */
 762 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 763 {
 764         struct amdgpu_device *adev = m->private;
 765         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 766         struct dmub_debugfs_trace_entry *entries;
 767         uint8_t *tbuf_base;
 768         uint32_t tbuf_size, max_entries, num_entries, i;
 769
 770         if (!fb_info)
 771                 return 0;
 772
 773         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 774         if (!tbuf_base)
 775                 return 0;
 776
 777         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 778         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 779                       sizeof(struct dmub_debugfs_trace_entry);
 780
 781         num_entries =
 782                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 783
 784         num_entries = min(num_entries, max_entries);
 785
 786         entries = (struct dmub_debugfs_trace_entry
 787                            *)(tbuf_base +
 788                               sizeof(struct dmub_debugfs_trace_header));
 789
 790         for (i = 0; i < num_entries; ++i) {
 791                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 792
 793                 seq_printf(m,
 794                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 795                            entry->trace_code, entry->tick_count, entry->param0,
 796                            entry->param1);
 797         }
 798
 799         return 0;
 800 }
 801
 802 /*
 803  * Returns the DMCUB firmware state contents.
 804  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 805  */
 806 static int dmub_fw_state_show(struct seq_file *m, void *data)
 807 {
 808         struct amdgpu_device *adev = m->private;
 809         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 810         uint8_t *state_base;
 811         uint32_t state_size;
 812
 813         if (!fb_info)
 814                 return 0;
 815
 816         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 817         if (!state_base)
 818                 return 0;
 819
 820         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 821
 822         return seq_write(m, state_base, state_size);
 823 }
 824
 825 /*
 826  * Returns the current and maximum output bpc for the connector.
 827  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc
 828  */
 829 static int output_bpc_show(struct seq_file *m, void *data)
 830 {
 831         struct drm_connector *connector = m->private;
 832         struct drm_device *dev = connector->dev;
 833         struct drm_crtc *crtc = NULL;
 834         struct dm_crtc_state *dm_crtc_state = NULL;
 835         int res = -ENODEV;
 836         unsigned int bpc;
 837
 838         mutex_lock(&dev->mode_config.mutex);
 839         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 840
 841         if (connector->state == NULL)
 842                 goto unlock;
 843
 844         crtc = connector->state->crtc;
 845         if (crtc == NULL)
 846                 goto unlock;
 847
 848         drm_modeset_lock(&crtc->mutex, NULL);
 849         if (crtc->state == NULL)
 850                 goto unlock;
 851
 852         dm_crtc_state = to_dm_crtc_state(crtc->state);
 853         if (dm_crtc_state->stream == NULL)
 854                 goto unlock;
 855
 856         switch (dm_crtc_state->stream->timing.display_color_depth) {
 857         case COLOR_DEPTH_666:
 858                 bpc = 6;
 859                 break;
 860         case COLOR_DEPTH_888:
 861                 bpc = 8;
 862                 break;
 863         case COLOR_DEPTH_101010:
 864                 bpc = 10;
 865                 break;
 866         case COLOR_DEPTH_121212:
 867                 bpc = 12;
 868                 break;
 869         case COLOR_DEPTH_161616:
 870                 bpc = 16;
 871                 break;
 872         default:
 873                 goto unlock;
 874         }
 875
 876         seq_printf(m, "Current: %u\n", bpc);
 877         seq_printf(m, "Maximum: %u\n", connector->display_info.bpc);
 878         res = 0;
 879
 880 unlock:
 881         if (crtc)
 882                 drm_modeset_unlock(&crtc->mutex);
 883
 884         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 885         mutex_unlock(&dev->mode_config.mutex);
 886
 887         return res;
 888 }
 889
 890 /*
 891  * Example usage:
 892  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
 893  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 894  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
 895  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 896  */
 897 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
 898                                  size_t size, loff_t *pos)
 899 {
 900         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 901         char *wr_buf = NULL;
 902         uint32_t wr_buf_size = 42;
 903         int max_param_num = 1;
 904         long param;
 905         uint8_t param_nums = 0;
 906
 907         if (size == 0)
 908                 return -EINVAL;
 909
 910         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 911
 912         if (!wr_buf) {
 913                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
 914                 return -ENOSPC;
 915         }
 916
 917         if (parse_write_buffer_into_params(wr_buf, size,
 918                                            &param, buf,
 919                                            max_param_num,
 920                                            &param_nums)) {
 921                 kfree(wr_buf);
 922                 return -EINVAL;
 923         }
 924
 925         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
 926
 927         kfree(wr_buf);
 928         return 0;
 929 }
 930
 931 #ifdef CONFIG_DRM_AMD_DC_HDCP
 932 /*
 933  * Returns the HDCP capability of the Display (1.4 for now).
 934  *
 935  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 936  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 937  *
 938  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 939  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 940  */
 941 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 942 {
 943         struct drm_connector *connector = m->private;
 944         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 945         bool hdcp_cap, hdcp2_cap;
 946
 947         if (connector->status != connector_status_connected)
 948                 return -ENODEV;
 949
 950         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 951
 952         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 953         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 954
 955
 956         if (hdcp_cap)
 957                 seq_printf(m, "%s ", "HDCP1.4");
 958         if (hdcp2_cap)
 959                 seq_printf(m, "%s ", "HDCP2.2");
 960
 961         if (!hdcp_cap && !hdcp2_cap)
 962                 seq_printf(m, "%s ", "None");
 963
 964         seq_puts(m, "\n");
 965
 966         return 0;
 967 }
 968 #endif
 969
 970 /*
 971  * Returns whether the connected display is internal and not hotpluggable.
 972  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
 973  */
 974 static int internal_display_show(struct seq_file *m, void *data)
 975 {
 976         struct drm_connector *connector = m->private;
 977         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 978         struct dc_link *link = aconnector->dc_link;
 979
 980         seq_printf(m, "Internal: %u\n", link->is_internal_display);
 981
 982         return 0;
 983 }
 984
 985 /* function description
 986  *
 987  * generic SDP message access for testing
 988  *
 989  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
 990  *
 991  * SDP header
 992  * Hb0 : Secondary-Data Packet ID
 993  * Hb1 : Secondary-Data Packet type
 994  * Hb2 : Secondary-Data-packet-specific header, Byte 0
 995  * Hb3 : Secondary-Data-packet-specific header, Byte 1
 996  *
 997  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
 998  */
 999 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1000                                  size_t size, loff_t *pos)
1001 {
1002         int r;
1003         uint8_t data[36];
1004         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1005         struct dm_crtc_state *acrtc_state;
1006         uint32_t write_size = 36;
1007
1008         if (connector->base.status != connector_status_connected)
1009                 return -ENODEV;
1010
1011         if (size == 0)
1012                 return 0;
1013
1014         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1015
1016         r = copy_from_user(data, buf, write_size);
1017
1018         write_size -= r;
1019
1020         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1021
1022         return write_size;
1023 }
1024
1025 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
1026                                  size_t size, loff_t *pos)
1027 {
1028         int r;
1029         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1030
1031         if (size < sizeof(connector->debugfs_dpcd_address))
1032                 return -EINVAL;
1033
1034         r = copy_from_user(&connector->debugfs_dpcd_address,
1035                         buf, sizeof(connector->debugfs_dpcd_address));
1036
1037         return size - r;
1038 }
1039
1040 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
1041                                  size_t size, loff_t *pos)
1042 {
1043         int r;
1044         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1045
1046         if (size < sizeof(connector->debugfs_dpcd_size))
1047                 return -EINVAL;
1048
1049         r = copy_from_user(&connector->debugfs_dpcd_size,
1050                         buf, sizeof(connector->debugfs_dpcd_size));
1051
1052         if (connector->debugfs_dpcd_size > 256)
1053                 connector->debugfs_dpcd_size = 0;
1054
1055         return size - r;
1056 }
1057
1058 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
1059                                  size_t size, loff_t *pos)
1060 {
1061         int r;
1062         char *data;
1063         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1064         struct dc_link *link = connector->dc_link;
1065         uint32_t write_size = connector->debugfs_dpcd_size;
1066
1067         if (!write_size || size < write_size)
1068                 return -EINVAL;
1069
1070         data = kzalloc(write_size, GFP_KERNEL);
1071         if (!data)
1072                 return 0;
1073
1074         r = copy_from_user(data, buf, write_size);
1075
1076         dm_helpers_dp_write_dpcd(link->ctx, link,
1077                         connector->debugfs_dpcd_address, data, write_size - r);
1078         kfree(data);
1079         return write_size - r;
1080 }
1081
1082 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
1083                                  size_t size, loff_t *pos)
1084 {
1085         int r;
1086         char *data;
1087         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1088         struct dc_link *link = connector->dc_link;
1089         uint32_t read_size = connector->debugfs_dpcd_size;
1090
1091         if (!read_size || size < read_size)
1092                 return 0;
1093
1094         data = kzalloc(read_size, GFP_KERNEL);
1095         if (!data)
1096                 return 0;
1097
1098         dm_helpers_dp_read_dpcd(link->ctx, link,
1099                         connector->debugfs_dpcd_address, data, read_size);
1100
1101         r = copy_to_user(buf, data, read_size);
1102
1103         kfree(data);
1104         return read_size - r;
1105 }
1106
1107 /* function: Read link's DSC & FEC capabilities
1108  *
1109  *
1110  * Access it with the following command (you need to specify
1111  * connector like DP-1):
1112  *
1113  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1114  *
1115  */
1116 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1117 {
1118         struct drm_connector *connector = m->private;
1119         struct drm_modeset_acquire_ctx ctx;
1120         struct drm_device *dev = connector->dev;
1121         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1122         int ret = 0;
1123         bool try_again = false;
1124         bool is_fec_supported = false;
1125         bool is_dsc_supported = false;
1126         struct dpcd_caps dpcd_caps;
1127
1128         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1129         do {
1130                 try_again = false;
1131                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1132                 if (ret) {
1133                         if (ret == -EDEADLK) {
1134                                 ret = drm_modeset_backoff(&ctx);
1135                                 if (!ret) {
1136                                         try_again = true;
1137                                         continue;
1138                                 }
1139                         }
1140                         break;
1141                 }
1142                 if (connector->status != connector_status_connected) {
1143                         ret = -ENODEV;
1144                         break;
1145                 }
1146                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1147                 if (aconnector->port) {
1148                         /* aconnector sets dsc_aux during get_modes call
1149                          * if MST connector has it means it can either
1150                          * enable DSC on the sink device or on MST branch
1151                          * its connected to.
1152                          */
1153                         if (aconnector->dsc_aux) {
1154                                 is_fec_supported = true;
1155                                 is_dsc_supported = true;
1156                         }
1157                 } else {
1158                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1159                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1160                 }
1161         } while (try_again);
1162
1163         drm_modeset_drop_locks(&ctx);
1164         drm_modeset_acquire_fini(&ctx);
1165
1166         seq_printf(m, "FEC_Sink_Support: %s\n", yesno(is_fec_supported));
1167         seq_printf(m, "DSC_Sink_Support: %s\n", yesno(is_dsc_supported));
1168
1169         return ret;
1170 }
1171
1172 /* function: Trigger virtual HPD redetection on connector
1173  *
1174  * This function will perform link rediscovery, link disable
1175  * and enable, and dm connector state update.
1176  *
1177  * Retrigger HPD on an existing connector by echoing 1 into
1178  * its respectful "trigger_hotplug" debugfs entry:
1179  *
1180  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1181  *
1182  * This function can perform HPD unplug:
1183  *
1184  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1185  *
1186  */
1187 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1188                                                         size_t size, loff_t *pos)
1189 {
1190         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1191         struct drm_connector *connector = &aconnector->base;
1192         struct dc_link *link = NULL;
1193         struct drm_device *dev = connector->dev;
1194         enum dc_connection_type new_connection_type = dc_connection_none;
1195         char *wr_buf = NULL;
1196         uint32_t wr_buf_size = 42;
1197         int max_param_num = 1;
1198         long param[1] = {0};
1199         uint8_t param_nums = 0;
1200
1201         if (!aconnector || !aconnector->dc_link)
1202                 return -EINVAL;
1203
1204         if (size == 0)
1205                 return -EINVAL;
1206
1207         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1208
1209         if (!wr_buf) {
1210                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1211                 return -ENOSPC;
1212         }
1213
1214         if (parse_write_buffer_into_params(wr_buf, size,
1215                                                 (long *)param, buf,
1216                                                 max_param_num,
1217                                                 &param_nums)) {
1218                 kfree(wr_buf);
1219                 return -EINVAL;
1220         }
1221
1222         if (param_nums <= 0) {
1223                 DRM_DEBUG_DRIVER("user data not be read\n");
1224                 kfree(wr_buf);
1225                 return -EINVAL;
1226         }
1227
1228         if (param[0] == 1) {
1229                 mutex_lock(&aconnector->hpd_lock);
1230
1231                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) &&
1232                         new_connection_type != dc_connection_none)
1233                         goto unlock;
1234
1235                 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD))
1236                         goto unlock;
1237
1238                 amdgpu_dm_update_connector_after_detect(aconnector);
1239
1240                 drm_modeset_lock_all(dev);
1241                 dm_restore_drm_connector_state(dev, connector);
1242                 drm_modeset_unlock_all(dev);
1243
1244                 drm_kms_helper_hotplug_event(dev);
1245         } else if (param[0] == 0) {
1246                 if (!aconnector->dc_link)
1247                         goto unlock;
1248
1249                 link = aconnector->dc_link;
1250
1251                 if (link->local_sink) {
1252                         dc_sink_release(link->local_sink);
1253                         link->local_sink = NULL;
1254                 }
1255
1256                 link->dpcd_sink_count = 0;
1257                 link->type = dc_connection_none;
1258                 link->dongle_max_pix_clk = 0;
1259
1260                 amdgpu_dm_update_connector_after_detect(aconnector);
1261
1262                 drm_modeset_lock_all(dev);
1263                 dm_restore_drm_connector_state(dev, connector);
1264                 drm_modeset_unlock_all(dev);
1265
1266                 drm_kms_helper_hotplug_event(dev);
1267         }
1268
1269 unlock:
1270         mutex_unlock(&aconnector->hpd_lock);
1271
1272         kfree(wr_buf);
1273         return size;
1274 }
1275
1276 /* function: read DSC status on the connector
1277  *
1278  * The read function: dp_dsc_clock_en_read
1279  * returns current status of DSC clock on the connector.
1280  * The return is a boolean flag: 1 or 0.
1281  *
1282  * Access it with the following command (you need to specify
1283  * connector like DP-1):
1284  *
1285  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1286  *
1287  * Expected output:
1288  * 1 - means that DSC is currently enabled
1289  * 0 - means that DSC is disabled
1290  */
1291 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1292                                     size_t size, loff_t *pos)
1293 {
1294         char *rd_buf = NULL;
1295         char *rd_buf_ptr = NULL;
1296         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1297         struct display_stream_compressor *dsc;
1298         struct dcn_dsc_state dsc_state = {0};
1299         const uint32_t rd_buf_size = 10;
1300         struct pipe_ctx *pipe_ctx;
1301         ssize_t result = 0;
1302         int i, r, str_len = 30;
1303
1304         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1305
1306         if (!rd_buf)
1307                 return -ENOMEM;
1308
1309         rd_buf_ptr = rd_buf;
1310
1311         for (i = 0; i < MAX_PIPES; i++) {
1312                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1313                         if (pipe_ctx && pipe_ctx->stream &&
1314                             pipe_ctx->stream->link == aconnector->dc_link)
1315                                 break;
1316         }
1317
1318         if (!pipe_ctx)
1319                 return -ENXIO;
1320
1321         dsc = pipe_ctx->stream_res.dsc;
1322         if (dsc)
1323                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1324
1325         snprintf(rd_buf_ptr, str_len,
1326                 "%d\n",
1327                 dsc_state.dsc_clock_en);
1328         rd_buf_ptr += str_len;
1329
1330         while (size) {
1331                 if (*pos >= rd_buf_size)
1332                         break;
1333
1334                 r = put_user(*(rd_buf + result), buf);
1335                 if (r)
1336                         return r; /* r = -EFAULT */
1337
1338                 buf += 1;
1339                 size -= 1;
1340                 *pos += 1;
1341                 result += 1;
1342         }
1343
1344         kfree(rd_buf);
1345         return result;
1346 }
1347
1348 /* function: write force DSC on the connector
1349  *
1350  * The write function: dp_dsc_clock_en_write
1351  * enables to force DSC on the connector.
1352  * User can write to either force enable or force disable DSC
1353  * on the next modeset or set it to driver default
1354  *
1355  * Accepted inputs:
1356  * 0 - default DSC enablement policy
1357  * 1 - force enable DSC on the connector
1358  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1359  *
1360  * Writing DSC settings is done with the following command:
1361  * - To force enable DSC (you need to specify
1362  * connector like DP-1):
1363  *
1364  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1365  *
1366  * - To return to default state set the flag to zero and
1367  * let driver deal with DSC automatically
1368  * (you need to specify connector like DP-1):
1369  *
1370  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1371  *
1372  */
1373 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1374                                      size_t size, loff_t *pos)
1375 {
1376         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1377         struct drm_connector *connector = &aconnector->base;
1378         struct drm_device *dev = connector->dev;
1379         struct drm_crtc *crtc = NULL;
1380         struct dm_crtc_state *dm_crtc_state = NULL;
1381         struct pipe_ctx *pipe_ctx;
1382         int i;
1383         char *wr_buf = NULL;
1384         uint32_t wr_buf_size = 42;
1385         int max_param_num = 1;
1386         long param[1] = {0};
1387         uint8_t param_nums = 0;
1388
1389         if (size == 0)
1390                 return -EINVAL;
1391
1392         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1393
1394         if (!wr_buf) {
1395                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1396                 return -ENOSPC;
1397         }
1398
1399         if (parse_write_buffer_into_params(wr_buf, size,
1400                                             (long *)param, buf,
1401                                             max_param_num,
1402                                             &param_nums)) {
1403                 kfree(wr_buf);
1404                 return -EINVAL;
1405         }
1406
1407         if (param_nums <= 0) {
1408                 DRM_DEBUG_DRIVER("user data not be read\n");
1409                 kfree(wr_buf);
1410                 return -EINVAL;
1411         }
1412
1413         for (i = 0; i < MAX_PIPES; i++) {
1414                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1415                         if (pipe_ctx && pipe_ctx->stream &&
1416                             pipe_ctx->stream->link == aconnector->dc_link)
1417                                 break;
1418         }
1419
1420         if (!pipe_ctx || !pipe_ctx->stream)
1421                 goto done;
1422
1423         // Get CRTC state
1424         mutex_lock(&dev->mode_config.mutex);
1425         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1426
1427         if (connector->state == NULL)
1428                 goto unlock;
1429
1430         crtc = connector->state->crtc;
1431         if (crtc == NULL)
1432                 goto unlock;
1433
1434         drm_modeset_lock(&crtc->mutex, NULL);
1435         if (crtc->state == NULL)
1436                 goto unlock;
1437
1438         dm_crtc_state = to_dm_crtc_state(crtc->state);
1439         if (dm_crtc_state->stream == NULL)
1440                 goto unlock;
1441
1442         if (param[0] == 1)
1443                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1444         else if (param[0] == 2)
1445                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1446         else
1447                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1448
1449         dm_crtc_state->dsc_force_changed = true;
1450
1451 unlock:
1452         if (crtc)
1453                 drm_modeset_unlock(&crtc->mutex);
1454         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1455         mutex_unlock(&dev->mode_config.mutex);
1456
1457 done:
1458         kfree(wr_buf);
1459         return size;
1460 }
1461
1462 /* function: read DSC slice width parameter on the connector
1463  *
1464  * The read function: dp_dsc_slice_width_read
1465  * returns dsc slice width used in the current configuration
1466  * The return is an integer: 0 or other positive number
1467  *
1468  * Access the status with the following command:
1469  *
1470  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1471  *
1472  * 0 - means that DSC is disabled
1473  *
1474  * Any other number more than zero represents the
1475  * slice width currently used by DSC in pixels
1476  *
1477  */
1478 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1479                                     size_t size, loff_t *pos)
1480 {
1481         char *rd_buf = NULL;
1482         char *rd_buf_ptr = NULL;
1483         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1484         struct display_stream_compressor *dsc;
1485         struct dcn_dsc_state dsc_state = {0};
1486         const uint32_t rd_buf_size = 100;
1487         struct pipe_ctx *pipe_ctx;
1488         ssize_t result = 0;
1489         int i, r, str_len = 30;
1490
1491         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1492
1493         if (!rd_buf)
1494                 return -ENOMEM;
1495
1496         rd_buf_ptr = rd_buf;
1497
1498         for (i = 0; i < MAX_PIPES; i++) {
1499                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1500                         if (pipe_ctx && pipe_ctx->stream &&
1501                             pipe_ctx->stream->link == aconnector->dc_link)
1502                                 break;
1503         }
1504
1505         if (!pipe_ctx)
1506                 return -ENXIO;
1507
1508         dsc = pipe_ctx->stream_res.dsc;
1509         if (dsc)
1510                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1511
1512         snprintf(rd_buf_ptr, str_len,
1513                 "%d\n",
1514                 dsc_state.dsc_slice_width);
1515         rd_buf_ptr += str_len;
1516
1517         while (size) {
1518                 if (*pos >= rd_buf_size)
1519                         break;
1520
1521                 r = put_user(*(rd_buf + result), buf);
1522                 if (r)
1523                         return r; /* r = -EFAULT */
1524
1525                 buf += 1;
1526                 size -= 1;
1527                 *pos += 1;
1528                 result += 1;
1529         }
1530
1531         kfree(rd_buf);
1532         return result;
1533 }
1534
1535 /* function: write DSC slice width parameter
1536  *
1537  * The write function: dp_dsc_slice_width_write
1538  * overwrites automatically generated DSC configuration
1539  * of slice width.
1540  *
1541  * The user has to write the slice width divisible by the
1542  * picture width.
1543  *
1544  * Also the user has to write width in hexidecimal
1545  * rather than in decimal.
1546  *
1547  * Writing DSC settings is done with the following command:
1548  * - To force overwrite slice width: (example sets to 1920 pixels)
1549  *
1550  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1551  *
1552  *  - To stop overwriting and let driver find the optimal size,
1553  * set the width to zero:
1554  *
1555  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1556  *
1557  */
1558 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1559                                      size_t size, loff_t *pos)
1560 {
1561         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1562         struct pipe_ctx *pipe_ctx;
1563         struct drm_connector *connector = &aconnector->base;
1564         struct drm_device *dev = connector->dev;
1565         struct drm_crtc *crtc = NULL;
1566         struct dm_crtc_state *dm_crtc_state = NULL;
1567         int i;
1568         char *wr_buf = NULL;
1569         uint32_t wr_buf_size = 42;
1570         int max_param_num = 1;
1571         long param[1] = {0};
1572         uint8_t param_nums = 0;
1573
1574         if (size == 0)
1575                 return -EINVAL;
1576
1577         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1578
1579         if (!wr_buf) {
1580                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1581                 return -ENOSPC;
1582         }
1583
1584         if (parse_write_buffer_into_params(wr_buf, size,
1585                                             (long *)param, buf,
1586                                             max_param_num,
1587                                             &param_nums)) {
1588                 kfree(wr_buf);
1589                 return -EINVAL;
1590         }
1591
1592         if (param_nums <= 0) {
1593                 DRM_DEBUG_DRIVER("user data not be read\n");
1594                 kfree(wr_buf);
1595                 return -EINVAL;
1596         }
1597
1598         for (i = 0; i < MAX_PIPES; i++) {
1599                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1600                         if (pipe_ctx && pipe_ctx->stream &&
1601                             pipe_ctx->stream->link == aconnector->dc_link)
1602                                 break;
1603         }
1604
1605         if (!pipe_ctx || !pipe_ctx->stream)
1606                 goto done;
1607
1608         // Safely get CRTC state
1609         mutex_lock(&dev->mode_config.mutex);
1610         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1611
1612         if (connector->state == NULL)
1613                 goto unlock;
1614
1615         crtc = connector->state->crtc;
1616         if (crtc == NULL)
1617                 goto unlock;
1618
1619         drm_modeset_lock(&crtc->mutex, NULL);
1620         if (crtc->state == NULL)
1621                 goto unlock;
1622
1623         dm_crtc_state = to_dm_crtc_state(crtc->state);
1624         if (dm_crtc_state->stream == NULL)
1625                 goto unlock;
1626
1627         if (param[0] > 0)
1628                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1629                                         pipe_ctx->stream->timing.h_addressable,
1630                                         param[0]);
1631         else
1632                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1633
1634         dm_crtc_state->dsc_force_changed = true;
1635
1636 unlock:
1637         if (crtc)
1638                 drm_modeset_unlock(&crtc->mutex);
1639         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1640         mutex_unlock(&dev->mode_config.mutex);
1641
1642 done:
1643         kfree(wr_buf);
1644         return size;
1645 }
1646
1647 /* function: read DSC slice height parameter on the connector
1648  *
1649  * The read function: dp_dsc_slice_height_read
1650  * returns dsc slice height used in the current configuration
1651  * The return is an integer: 0 or other positive number
1652  *
1653  * Access the status with the following command:
1654  *
1655  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1656  *
1657  * 0 - means that DSC is disabled
1658  *
1659  * Any other number more than zero represents the
1660  * slice height currently used by DSC in pixels
1661  *
1662  */
1663 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1664                                     size_t size, loff_t *pos)
1665 {
1666         char *rd_buf = NULL;
1667         char *rd_buf_ptr = NULL;
1668         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1669         struct display_stream_compressor *dsc;
1670         struct dcn_dsc_state dsc_state = {0};
1671         const uint32_t rd_buf_size = 100;
1672         struct pipe_ctx *pipe_ctx;
1673         ssize_t result = 0;
1674         int i, r, str_len = 30;
1675
1676         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1677
1678         if (!rd_buf)
1679                 return -ENOMEM;
1680
1681         rd_buf_ptr = rd_buf;
1682
1683         for (i = 0; i < MAX_PIPES; i++) {
1684                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1685                         if (pipe_ctx && pipe_ctx->stream &&
1686                             pipe_ctx->stream->link == aconnector->dc_link)
1687                                 break;
1688         }
1689
1690         if (!pipe_ctx)
1691                 return -ENXIO;
1692
1693         dsc = pipe_ctx->stream_res.dsc;
1694         if (dsc)
1695                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1696
1697         snprintf(rd_buf_ptr, str_len,
1698                 "%d\n",
1699                 dsc_state.dsc_slice_height);
1700         rd_buf_ptr += str_len;
1701
1702         while (size) {
1703                 if (*pos >= rd_buf_size)
1704                         break;
1705
1706                 r = put_user(*(rd_buf + result), buf);
1707                 if (r)
1708                         return r; /* r = -EFAULT */
1709
1710                 buf += 1;
1711                 size -= 1;
1712                 *pos += 1;
1713                 result += 1;
1714         }
1715
1716         kfree(rd_buf);
1717         return result;
1718 }
1719
1720 /* function: write DSC slice height parameter
1721  *
1722  * The write function: dp_dsc_slice_height_write
1723  * overwrites automatically generated DSC configuration
1724  * of slice height.
1725  *
1726  * The user has to write the slice height divisible by the
1727  * picture height.
1728  *
1729  * Also the user has to write height in hexidecimal
1730  * rather than in decimal.
1731  *
1732  * Writing DSC settings is done with the following command:
1733  * - To force overwrite slice height (example sets to 128 pixels):
1734  *
1735  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1736  *
1737  *  - To stop overwriting and let driver find the optimal size,
1738  * set the height to zero:
1739  *
1740  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1741  *
1742  */
1743 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1744                                      size_t size, loff_t *pos)
1745 {
1746         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1747         struct drm_connector *connector = &aconnector->base;
1748         struct drm_device *dev = connector->dev;
1749         struct drm_crtc *crtc = NULL;
1750         struct dm_crtc_state *dm_crtc_state = NULL;
1751         struct pipe_ctx *pipe_ctx;
1752         int i;
1753         char *wr_buf = NULL;
1754         uint32_t wr_buf_size = 42;
1755         int max_param_num = 1;
1756         uint8_t param_nums = 0;
1757         long param[1] = {0};
1758
1759         if (size == 0)
1760                 return -EINVAL;
1761
1762         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1763
1764         if (!wr_buf) {
1765                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1766                 return -ENOSPC;
1767         }
1768
1769         if (parse_write_buffer_into_params(wr_buf, size,
1770                                             (long *)param, buf,
1771                                             max_param_num,
1772                                             &param_nums)) {
1773                 kfree(wr_buf);
1774                 return -EINVAL;
1775         }
1776
1777         if (param_nums <= 0) {
1778                 DRM_DEBUG_DRIVER("user data not be read\n");
1779                 kfree(wr_buf);
1780                 return -EINVAL;
1781         }
1782
1783         for (i = 0; i < MAX_PIPES; i++) {
1784                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1785                         if (pipe_ctx && pipe_ctx->stream &&
1786                             pipe_ctx->stream->link == aconnector->dc_link)
1787                                 break;
1788         }
1789
1790         if (!pipe_ctx || !pipe_ctx->stream)
1791                 goto done;
1792
1793         // Get CRTC state
1794         mutex_lock(&dev->mode_config.mutex);
1795         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1796
1797         if (connector->state == NULL)
1798                 goto unlock;
1799
1800         crtc = connector->state->crtc;
1801         if (crtc == NULL)
1802                 goto unlock;
1803
1804         drm_modeset_lock(&crtc->mutex, NULL);
1805         if (crtc->state == NULL)
1806                 goto unlock;
1807
1808         dm_crtc_state = to_dm_crtc_state(crtc->state);
1809         if (dm_crtc_state->stream == NULL)
1810                 goto unlock;
1811
1812         if (param[0] > 0)
1813                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1814                                         pipe_ctx->stream->timing.v_addressable,
1815                                         param[0]);
1816         else
1817                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1818
1819         dm_crtc_state->dsc_force_changed = true;
1820
1821 unlock:
1822         if (crtc)
1823                 drm_modeset_unlock(&crtc->mutex);
1824         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1825         mutex_unlock(&dev->mode_config.mutex);
1826
1827 done:
1828         kfree(wr_buf);
1829         return size;
1830 }
1831
1832 /* function: read DSC target rate on the connector in bits per pixel
1833  *
1834  * The read function: dp_dsc_bits_per_pixel_read
1835  * returns target rate of compression in bits per pixel
1836  * The return is an integer: 0 or other positive integer
1837  *
1838  * Access it with the following command:
1839  *
1840  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1841  *
1842  *  0 - means that DSC is disabled
1843  */
1844 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1845                                     size_t size, loff_t *pos)
1846 {
1847         char *rd_buf = NULL;
1848         char *rd_buf_ptr = NULL;
1849         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1850         struct display_stream_compressor *dsc;
1851         struct dcn_dsc_state dsc_state = {0};
1852         const uint32_t rd_buf_size = 100;
1853         struct pipe_ctx *pipe_ctx;
1854         ssize_t result = 0;
1855         int i, r, str_len = 30;
1856
1857         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1858
1859         if (!rd_buf)
1860                 return -ENOMEM;
1861
1862         rd_buf_ptr = rd_buf;
1863
1864         for (i = 0; i < MAX_PIPES; i++) {
1865                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1866                         if (pipe_ctx && pipe_ctx->stream &&
1867                             pipe_ctx->stream->link == aconnector->dc_link)
1868                                 break;
1869         }
1870
1871         if (!pipe_ctx)
1872                 return -ENXIO;
1873
1874         dsc = pipe_ctx->stream_res.dsc;
1875         if (dsc)
1876                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1877
1878         snprintf(rd_buf_ptr, str_len,
1879                 "%d\n",
1880                 dsc_state.dsc_bits_per_pixel);
1881         rd_buf_ptr += str_len;
1882
1883         while (size) {
1884                 if (*pos >= rd_buf_size)
1885                         break;
1886
1887                 r = put_user(*(rd_buf + result), buf);
1888                 if (r)
1889                         return r; /* r = -EFAULT */
1890
1891                 buf += 1;
1892                 size -= 1;
1893                 *pos += 1;
1894                 result += 1;
1895         }
1896
1897         kfree(rd_buf);
1898         return result;
1899 }
1900
1901 /* function: write DSC target rate in bits per pixel
1902  *
1903  * The write function: dp_dsc_bits_per_pixel_write
1904  * overwrites automatically generated DSC configuration
1905  * of DSC target bit rate.
1906  *
1907  * Also the user has to write bpp in hexidecimal
1908  * rather than in decimal.
1909  *
1910  * Writing DSC settings is done with the following command:
1911  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1912  *
1913  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1914  *
1915  *  - To stop overwriting and let driver find the optimal rate,
1916  * set the rate to zero:
1917  *
1918  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1919  *
1920  */
1921 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1922                                      size_t size, loff_t *pos)
1923 {
1924         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1925         struct drm_connector *connector = &aconnector->base;
1926         struct drm_device *dev = connector->dev;
1927         struct drm_crtc *crtc = NULL;
1928         struct dm_crtc_state *dm_crtc_state = NULL;
1929         struct pipe_ctx *pipe_ctx;
1930         int i;
1931         char *wr_buf = NULL;
1932         uint32_t wr_buf_size = 42;
1933         int max_param_num = 1;
1934         uint8_t param_nums = 0;
1935         long param[1] = {0};
1936
1937         if (size == 0)
1938                 return -EINVAL;
1939
1940         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1941
1942         if (!wr_buf) {
1943                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1944                 return -ENOSPC;
1945         }
1946
1947         if (parse_write_buffer_into_params(wr_buf, size,
1948                                             (long *)param, buf,
1949                                             max_param_num,
1950                                             &param_nums)) {
1951                 kfree(wr_buf);
1952                 return -EINVAL;
1953         }
1954
1955         if (param_nums <= 0) {
1956                 DRM_DEBUG_DRIVER("user data not be read\n");
1957                 kfree(wr_buf);
1958                 return -EINVAL;
1959         }
1960
1961         for (i = 0; i < MAX_PIPES; i++) {
1962                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1963                         if (pipe_ctx && pipe_ctx->stream &&
1964                             pipe_ctx->stream->link == aconnector->dc_link)
1965                                 break;
1966         }
1967
1968         if (!pipe_ctx || !pipe_ctx->stream)
1969                 goto done;
1970
1971         // Get CRTC state
1972         mutex_lock(&dev->mode_config.mutex);
1973         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1974
1975         if (connector->state == NULL)
1976                 goto unlock;
1977
1978         crtc = connector->state->crtc;
1979         if (crtc == NULL)
1980                 goto unlock;
1981
1982         drm_modeset_lock(&crtc->mutex, NULL);
1983         if (crtc->state == NULL)
1984                 goto unlock;
1985
1986         dm_crtc_state = to_dm_crtc_state(crtc->state);
1987         if (dm_crtc_state->stream == NULL)
1988                 goto unlock;
1989
1990         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
1991
1992         dm_crtc_state->dsc_force_changed = true;
1993
1994 unlock:
1995         if (crtc)
1996                 drm_modeset_unlock(&crtc->mutex);
1997         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1998         mutex_unlock(&dev->mode_config.mutex);
1999
2000 done:
2001         kfree(wr_buf);
2002         return size;
2003 }
2004
2005 /* function: read DSC picture width parameter on the connector
2006  *
2007  * The read function: dp_dsc_pic_width_read
2008  * returns dsc picture width used in the current configuration
2009  * It is the same as h_addressable of the current
2010  * display's timing
2011  * The return is an integer: 0 or other positive integer
2012  * If 0 then DSC is disabled.
2013  *
2014  * Access it with the following command:
2015  *
2016  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2017  *
2018  * 0 - means that DSC is disabled
2019  */
2020 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2021                                     size_t size, loff_t *pos)
2022 {
2023         char *rd_buf = NULL;
2024         char *rd_buf_ptr = NULL;
2025         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2026         struct display_stream_compressor *dsc;
2027         struct dcn_dsc_state dsc_state = {0};
2028         const uint32_t rd_buf_size = 100;
2029         struct pipe_ctx *pipe_ctx;
2030         ssize_t result = 0;
2031         int i, r, str_len = 30;
2032
2033         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2034
2035         if (!rd_buf)
2036                 return -ENOMEM;
2037
2038         rd_buf_ptr = rd_buf;
2039
2040         for (i = 0; i < MAX_PIPES; i++) {
2041                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2042                         if (pipe_ctx && pipe_ctx->stream &&
2043                             pipe_ctx->stream->link == aconnector->dc_link)
2044                                 break;
2045         }
2046
2047         if (!pipe_ctx)
2048                 return -ENXIO;
2049
2050         dsc = pipe_ctx->stream_res.dsc;
2051         if (dsc)
2052                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2053
2054         snprintf(rd_buf_ptr, str_len,
2055                 "%d\n",
2056                 dsc_state.dsc_pic_width);
2057         rd_buf_ptr += str_len;
2058
2059         while (size) {
2060                 if (*pos >= rd_buf_size)
2061                         break;
2062
2063                 r = put_user(*(rd_buf + result), buf);
2064                 if (r)
2065                         return r; /* r = -EFAULT */
2066
2067                 buf += 1;
2068                 size -= 1;
2069                 *pos += 1;
2070                 result += 1;
2071         }
2072
2073         kfree(rd_buf);
2074         return result;
2075 }
2076
2077 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2078                                     size_t size, loff_t *pos)
2079 {
2080         char *rd_buf = NULL;
2081         char *rd_buf_ptr = NULL;
2082         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2083         struct display_stream_compressor *dsc;
2084         struct dcn_dsc_state dsc_state = {0};
2085         const uint32_t rd_buf_size = 100;
2086         struct pipe_ctx *pipe_ctx;
2087         ssize_t result = 0;
2088         int i, r, str_len = 30;
2089
2090         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2091
2092         if (!rd_buf)
2093                 return -ENOMEM;
2094
2095         rd_buf_ptr = rd_buf;
2096
2097         for (i = 0; i < MAX_PIPES; i++) {
2098                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2099                         if (pipe_ctx && pipe_ctx->stream &&
2100                             pipe_ctx->stream->link == aconnector->dc_link)
2101                                 break;
2102         }
2103
2104         if (!pipe_ctx)
2105                 return -ENXIO;
2106
2107         dsc = pipe_ctx->stream_res.dsc;
2108         if (dsc)
2109                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2110
2111         snprintf(rd_buf_ptr, str_len,
2112                 "%d\n",
2113                 dsc_state.dsc_pic_height);
2114         rd_buf_ptr += str_len;
2115
2116         while (size) {
2117                 if (*pos >= rd_buf_size)
2118                         break;
2119
2120                 r = put_user(*(rd_buf + result), buf);
2121                 if (r)
2122                         return r; /* r = -EFAULT */
2123
2124                 buf += 1;
2125                 size -= 1;
2126                 *pos += 1;
2127                 result += 1;
2128         }
2129
2130         kfree(rd_buf);
2131         return result;
2132 }
2133
2134 /* function: read DSC chunk size parameter on the connector
2135  *
2136  * The read function: dp_dsc_chunk_size_read
2137  * returns dsc chunk size set in the current configuration
2138  * The value is calculated automatically by DSC code
2139  * and depends on slice parameters and bpp target rate
2140  * The return is an integer: 0 or other positive integer
2141  * If 0 then DSC is disabled.
2142  *
2143  * Access it with the following command:
2144  *
2145  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2146  *
2147  * 0 - means that DSC is disabled
2148  */
2149 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2150                                     size_t size, loff_t *pos)
2151 {
2152         char *rd_buf = NULL;
2153         char *rd_buf_ptr = NULL;
2154         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2155         struct display_stream_compressor *dsc;
2156         struct dcn_dsc_state dsc_state = {0};
2157         const uint32_t rd_buf_size = 100;
2158         struct pipe_ctx *pipe_ctx;
2159         ssize_t result = 0;
2160         int i, r, str_len = 30;
2161
2162         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2163
2164         if (!rd_buf)
2165                 return -ENOMEM;
2166
2167         rd_buf_ptr = rd_buf;
2168
2169         for (i = 0; i < MAX_PIPES; i++) {
2170                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2171                         if (pipe_ctx && pipe_ctx->stream &&
2172                             pipe_ctx->stream->link == aconnector->dc_link)
2173                                 break;
2174         }
2175
2176         if (!pipe_ctx)
2177                 return -ENXIO;
2178
2179         dsc = pipe_ctx->stream_res.dsc;
2180         if (dsc)
2181                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2182
2183         snprintf(rd_buf_ptr, str_len,
2184                 "%d\n",
2185                 dsc_state.dsc_chunk_size);
2186         rd_buf_ptr += str_len;
2187
2188         while (size) {
2189                 if (*pos >= rd_buf_size)
2190                         break;
2191
2192                 r = put_user(*(rd_buf + result), buf);
2193                 if (r)
2194                         return r; /* r = -EFAULT */
2195
2196                 buf += 1;
2197                 size -= 1;
2198                 *pos += 1;
2199                 result += 1;
2200         }
2201
2202         kfree(rd_buf);
2203         return result;
2204 }
2205
2206 /* function: read DSC slice bpg offset on the connector
2207  *
2208  * The read function: dp_dsc_slice_bpg_offset_read
2209  * returns dsc bpg slice offset set in the current configuration
2210  * The value is calculated automatically by DSC code
2211  * and depends on slice parameters and bpp target rate
2212  * The return is an integer: 0 or other positive integer
2213  * If 0 then DSC is disabled.
2214  *
2215  * Access it with the following command:
2216  *
2217  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2218  *
2219  * 0 - means that DSC is disabled
2220  */
2221 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2222                                     size_t size, loff_t *pos)
2223 {
2224         char *rd_buf = NULL;
2225         char *rd_buf_ptr = NULL;
2226         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2227         struct display_stream_compressor *dsc;
2228         struct dcn_dsc_state dsc_state = {0};
2229         const uint32_t rd_buf_size = 100;
2230         struct pipe_ctx *pipe_ctx;
2231         ssize_t result = 0;
2232         int i, r, str_len = 30;
2233
2234         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2235
2236         if (!rd_buf)
2237                 return -ENOMEM;
2238
2239         rd_buf_ptr = rd_buf;
2240
2241         for (i = 0; i < MAX_PIPES; i++) {
2242                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2243                         if (pipe_ctx && pipe_ctx->stream &&
2244                             pipe_ctx->stream->link == aconnector->dc_link)
2245                                 break;
2246         }
2247
2248         if (!pipe_ctx)
2249                 return -ENXIO;
2250
2251         dsc = pipe_ctx->stream_res.dsc;
2252         if (dsc)
2253                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2254
2255         snprintf(rd_buf_ptr, str_len,
2256                 "%d\n",
2257                 dsc_state.dsc_slice_bpg_offset);
2258         rd_buf_ptr += str_len;
2259
2260         while (size) {
2261                 if (*pos >= rd_buf_size)
2262                         break;
2263
2264                 r = put_user(*(rd_buf + result), buf);
2265                 if (r)
2266                         return r; /* r = -EFAULT */
2267
2268                 buf += 1;
2269                 size -= 1;
2270                 *pos += 1;
2271                 result += 1;
2272         }
2273
2274         kfree(rd_buf);
2275         return result;
2276 }
2277
2278
2279 /*
2280  * function description: Read max_requested_bpc property from the connector
2281  *
2282  * Access it with the following command:
2283  *
2284  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2285  *
2286  */
2287 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2288                 size_t size, loff_t *pos)
2289 {
2290         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2291         struct drm_connector *connector = &aconnector->base;
2292         struct drm_device *dev = connector->dev;
2293         struct dm_connector_state *state;
2294         ssize_t result = 0;
2295         char *rd_buf = NULL;
2296         char *rd_buf_ptr = NULL;
2297         const uint32_t rd_buf_size = 10;
2298         int r;
2299
2300         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2301
2302         if (!rd_buf)
2303                 return -ENOMEM;
2304
2305         mutex_lock(&dev->mode_config.mutex);
2306         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2307
2308         if (connector->state == NULL)
2309                 goto unlock;
2310
2311         state = to_dm_connector_state(connector->state);
2312
2313         rd_buf_ptr = rd_buf;
2314         snprintf(rd_buf_ptr, rd_buf_size,
2315                 "%u\n",
2316                 state->base.max_requested_bpc);
2317
2318         while (size) {
2319                 if (*pos >= rd_buf_size)
2320                         break;
2321
2322                 r = put_user(*(rd_buf + result), buf);
2323                 if (r) {
2324                         result = r; /* r = -EFAULT */
2325                         goto unlock;
2326                 }
2327                 buf += 1;
2328                 size -= 1;
2329                 *pos += 1;
2330                 result += 1;
2331         }
2332 unlock:
2333         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2334         mutex_unlock(&dev->mode_config.mutex);
2335         kfree(rd_buf);
2336         return result;
2337 }
2338
2339
2340 /*
2341  * function description: Set max_requested_bpc property on the connector
2342  *
2343  * This function will not force the input BPC on connector, it will only
2344  * change the max value. This is equivalent to setting max_bpc through
2345  * xrandr.
2346  *
2347  * The BPC value written must be >= 6 and <= 16. Values outside of this
2348  * range will result in errors.
2349  *
2350  * BPC values:
2351  *      0x6 - 6 BPC
2352  *      0x8 - 8 BPC
2353  *      0xa - 10 BPC
2354  *      0xc - 12 BPC
2355  *      0x10 - 16 BPC
2356  *
2357  * Write the max_bpc in the following way:
2358  *
2359  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2360  *
2361  */
2362 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2363                                      size_t size, loff_t *pos)
2364 {
2365         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2366         struct drm_connector *connector = &aconnector->base;
2367         struct dm_connector_state *state;
2368         struct drm_device *dev = connector->dev;
2369         char *wr_buf = NULL;
2370         uint32_t wr_buf_size = 42;
2371         int max_param_num = 1;
2372         long param[1] = {0};
2373         uint8_t param_nums = 0;
2374
2375         if (size == 0)
2376                 return -EINVAL;
2377
2378         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2379
2380         if (!wr_buf) {
2381                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2382                 return -ENOSPC;
2383         }
2384
2385         if (parse_write_buffer_into_params(wr_buf, size,
2386                                            (long *)param, buf,
2387                                            max_param_num,
2388                                            &param_nums)) {
2389                 kfree(wr_buf);
2390                 return -EINVAL;
2391         }
2392
2393         if (param_nums <= 0) {
2394                 DRM_DEBUG_DRIVER("user data not be read\n");
2395                 kfree(wr_buf);
2396                 return -EINVAL;
2397         }
2398
2399         if (param[0] < 6 || param[0] > 16) {
2400                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2401                 kfree(wr_buf);
2402                 return -EINVAL;
2403         }
2404
2405         mutex_lock(&dev->mode_config.mutex);
2406         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2407
2408         if (connector->state == NULL)
2409                 goto unlock;
2410
2411         state = to_dm_connector_state(connector->state);
2412         state->base.max_requested_bpc = param[0];
2413 unlock:
2414         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2415         mutex_unlock(&dev->mode_config.mutex);
2416
2417         kfree(wr_buf);
2418         return size;
2419 }
2420
2421 /*
2422  * Backlight at this moment.  Read only.
2423  * As written to display, taking ABM and backlight lut into account.
2424  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2425  *
2426  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2427  */
2428 static int current_backlight_show(struct seq_file *m, void *unused)
2429 {
2430         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2431         struct dc_link *link = aconnector->dc_link;
2432         unsigned int backlight;
2433
2434         backlight = dc_link_get_backlight_level(link);
2435         seq_printf(m, "0x%x\n", backlight);
2436
2437         return 0;
2438 }
2439
2440 /*
2441  * Backlight value that is being approached.  Read only.
2442  * As written to display, taking ABM and backlight lut into account.
2443  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2444  *
2445  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2446  */
2447 static int target_backlight_show(struct seq_file *m, void *unused)
2448 {
2449         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2450         struct dc_link *link = aconnector->dc_link;
2451         unsigned int backlight;
2452
2453         backlight = dc_link_get_target_backlight_pwm(link);
2454         seq_printf(m, "0x%x\n", backlight);
2455
2456         return 0;
2457 }
2458
2459 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2460 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2461 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2462 DEFINE_SHOW_ATTRIBUTE(output_bpc);
2463 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2464 #ifdef CONFIG_DRM_AMD_DC_HDCP
2465 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2466 #endif
2467 DEFINE_SHOW_ATTRIBUTE(internal_display);
2468
2469 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2470         .owner = THIS_MODULE,
2471         .read = dp_dsc_clock_en_read,
2472         .write = dp_dsc_clock_en_write,
2473         .llseek = default_llseek
2474 };
2475
2476 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2477         .owner = THIS_MODULE,
2478         .read = dp_dsc_slice_width_read,
2479         .write = dp_dsc_slice_width_write,
2480         .llseek = default_llseek
2481 };
2482
2483 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2484         .owner = THIS_MODULE,
2485         .read = dp_dsc_slice_height_read,
2486         .write = dp_dsc_slice_height_write,
2487         .llseek = default_llseek
2488 };
2489
2490 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2491         .owner = THIS_MODULE,
2492         .read = dp_dsc_bits_per_pixel_read,
2493         .write = dp_dsc_bits_per_pixel_write,
2494         .llseek = default_llseek
2495 };
2496
2497 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2498         .owner = THIS_MODULE,
2499         .read = dp_dsc_pic_width_read,
2500         .llseek = default_llseek
2501 };
2502
2503 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2504         .owner = THIS_MODULE,
2505         .read = dp_dsc_pic_height_read,
2506         .llseek = default_llseek
2507 };
2508
2509 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2510         .owner = THIS_MODULE,
2511         .read = dp_dsc_chunk_size_read,
2512         .llseek = default_llseek
2513 };
2514
2515 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2516         .owner = THIS_MODULE,
2517         .read = dp_dsc_slice_bpg_offset_read,
2518         .llseek = default_llseek
2519 };
2520
2521 static const struct file_operations trigger_hotplug_debugfs_fops = {
2522         .owner = THIS_MODULE,
2523         .write = trigger_hotplug,
2524         .llseek = default_llseek
2525 };
2526
2527 static const struct file_operations dp_link_settings_debugfs_fops = {
2528         .owner = THIS_MODULE,
2529         .read = dp_link_settings_read,
2530         .write = dp_link_settings_write,
2531         .llseek = default_llseek
2532 };
2533
2534 static const struct file_operations dp_phy_settings_debugfs_fop = {
2535         .owner = THIS_MODULE,
2536         .read = dp_phy_settings_read,
2537         .write = dp_phy_settings_write,
2538         .llseek = default_llseek
2539 };
2540
2541 static const struct file_operations dp_phy_test_pattern_fops = {
2542         .owner = THIS_MODULE,
2543         .write = dp_phy_test_pattern_debugfs_write,
2544         .llseek = default_llseek
2545 };
2546
2547 static const struct file_operations sdp_message_fops = {
2548         .owner = THIS_MODULE,
2549         .write = dp_sdp_message_debugfs_write,
2550         .llseek = default_llseek
2551 };
2552
2553 static const struct file_operations dp_dpcd_address_debugfs_fops = {
2554         .owner = THIS_MODULE,
2555         .write = dp_dpcd_address_write,
2556         .llseek = default_llseek
2557 };
2558
2559 static const struct file_operations dp_dpcd_size_debugfs_fops = {
2560         .owner = THIS_MODULE,
2561         .write = dp_dpcd_size_write,
2562         .llseek = default_llseek
2563 };
2564
2565 static const struct file_operations dp_dpcd_data_debugfs_fops = {
2566         .owner = THIS_MODULE,
2567         .read = dp_dpcd_data_read,
2568         .write = dp_dpcd_data_write,
2569         .llseek = default_llseek
2570 };
2571
2572 static const struct file_operations dp_max_bpc_debugfs_fops = {
2573         .owner = THIS_MODULE,
2574         .read = dp_max_bpc_read,
2575         .write = dp_max_bpc_write,
2576         .llseek = default_llseek
2577 };
2578
2579 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2580         .owner = THIS_MODULE,
2581         .write = dp_dsc_passthrough_set,
2582         .llseek = default_llseek
2583 };
2584
2585 static const struct {
2586         char *name;
2587         const struct file_operations *fops;
2588 } dp_debugfs_entries[] = {
2589                 {"link_settings", &dp_link_settings_debugfs_fops},
2590                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2591                 {"lttpr_status", &dp_lttpr_status_fops},
2592                 {"test_pattern", &dp_phy_test_pattern_fops},
2593 #ifdef CONFIG_DRM_AMD_DC_HDCP
2594                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2595 #endif
2596                 {"sdp_message", &sdp_message_fops},
2597                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
2598                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
2599                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
2600                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2601                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2602                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2603                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2604                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2605                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2606                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2607                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2608                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2609                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2610                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2611 };
2612
2613 #ifdef CONFIG_DRM_AMD_DC_HDCP
2614 static const struct {
2615         char *name;
2616         const struct file_operations *fops;
2617 } hdmi_debugfs_entries[] = {
2618                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2619 };
2620 #endif
2621 /*
2622  * Force YUV420 output if available from the given mode
2623  */
2624 static int force_yuv420_output_set(void *data, u64 val)
2625 {
2626         struct amdgpu_dm_connector *connector = data;
2627
2628         connector->force_yuv420_output = (bool)val;
2629
2630         return 0;
2631 }
2632
2633 /*
2634  * Check if YUV420 is forced when available from the given mode
2635  */
2636 static int force_yuv420_output_get(void *data, u64 *val)
2637 {
2638         struct amdgpu_dm_connector *connector = data;
2639
2640         *val = connector->force_yuv420_output;
2641
2642         return 0;
2643 }
2644
2645 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2646                          force_yuv420_output_set, "%llu\n");
2647
2648 /*
2649  *  Read PSR state
2650  */
2651 static int psr_get(void *data, u64 *val)
2652 {
2653         struct amdgpu_dm_connector *connector = data;
2654         struct dc_link *link = connector->dc_link;
2655         enum dc_psr_state state = PSR_STATE0;
2656
2657         dc_link_get_psr_state(link, &state);
2658
2659         *val = state;
2660
2661         return 0;
2662 }
2663
2664 /*
2665  * Set dmcub trace event IRQ enable or disable.
2666  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2667  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2668  */
2669 static int dmcub_trace_event_state_set(void *data, u64 val)
2670 {
2671         struct amdgpu_device *adev = data;
2672
2673         if (val == 1 || val == 0) {
2674                 dc_dmub_trace_event_control(adev->dm.dc, val);
2675                 adev->dm.dmcub_trace_event_en = (bool)val;
2676         } else
2677                 return 0;
2678
2679         return 0;
2680 }
2681
2682 /*
2683  * The interface doesn't need get function, so it will return the
2684  * value of zero
2685  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2686  */
2687 static int dmcub_trace_event_state_get(void *data, u64 *val)
2688 {
2689         struct amdgpu_device *adev = data;
2690
2691         *val = adev->dm.dmcub_trace_event_en;
2692         return 0;
2693 }
2694
2695 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2696                          dmcub_trace_event_state_set, "%llu\n");
2697
2698 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2699
2700 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2701 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2702
2703 static const struct {
2704         char *name;
2705         const struct file_operations *fops;
2706 } connector_debugfs_entries[] = {
2707                 {"force_yuv420_output", &force_yuv420_output_fops},
2708                 {"output_bpc", &output_bpc_fops},
2709                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
2710                 {"internal_display", &internal_display_fops}
2711 };
2712
2713 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
2714 {
2715         int i;
2716         struct dentry *dir = connector->base.debugfs_entry;
2717
2718         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2719             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2720                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
2721                         debugfs_create_file(dp_debugfs_entries[i].name,
2722                                             0644, dir, connector,
2723                                             dp_debugfs_entries[i].fops);
2724                 }
2725         }
2726         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2727                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
2728                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
2729                                     &current_backlight_fops);
2730                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
2731                                     &target_backlight_fops);
2732         }
2733
2734         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
2735                 debugfs_create_file(connector_debugfs_entries[i].name,
2736                                     0644, dir, connector,
2737                                     connector_debugfs_entries[i].fops);
2738         }
2739
2740         connector->debugfs_dpcd_address = 0;
2741         connector->debugfs_dpcd_size = 0;
2742
2743 #ifdef CONFIG_DRM_AMD_DC_HDCP
2744         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
2745                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
2746                         debugfs_create_file(hdmi_debugfs_entries[i].name,
2747                                             0644, dir, connector,
2748                                             hdmi_debugfs_entries[i].fops);
2749                 }
2750         }
2751 #endif
2752 }
2753
2754 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2755 /*
2756  * Set crc window coordinate x start
2757  */
2758 static int crc_win_x_start_set(void *data, u64 val)
2759 {
2760         struct drm_crtc *crtc = data;
2761         struct drm_device *drm_dev = crtc->dev;
2762         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2763
2764         spin_lock_irq(&drm_dev->event_lock);
2765         acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val;
2766         acrtc->dm_irq_params.crc_window.update_win = false;
2767         spin_unlock_irq(&drm_dev->event_lock);
2768
2769         return 0;
2770 }
2771
2772 /*
2773  * Get crc window coordinate x start
2774  */
2775 static int crc_win_x_start_get(void *data, u64 *val)
2776 {
2777         struct drm_crtc *crtc = data;
2778         struct drm_device *drm_dev = crtc->dev;
2779         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2780
2781         spin_lock_irq(&drm_dev->event_lock);
2782         *val = acrtc->dm_irq_params.crc_window.x_start;
2783         spin_unlock_irq(&drm_dev->event_lock);
2784
2785         return 0;
2786 }
2787
2788 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
2789                          crc_win_x_start_set, "%llu\n");
2790
2791
2792 /*
2793  * Set crc window coordinate y start
2794  */
2795 static int crc_win_y_start_set(void *data, u64 val)
2796 {
2797         struct drm_crtc *crtc = data;
2798         struct drm_device *drm_dev = crtc->dev;
2799         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2800
2801         spin_lock_irq(&drm_dev->event_lock);
2802         acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val;
2803         acrtc->dm_irq_params.crc_window.update_win = false;
2804         spin_unlock_irq(&drm_dev->event_lock);
2805
2806         return 0;
2807 }
2808
2809 /*
2810  * Get crc window coordinate y start
2811  */
2812 static int crc_win_y_start_get(void *data, u64 *val)
2813 {
2814         struct drm_crtc *crtc = data;
2815         struct drm_device *drm_dev = crtc->dev;
2816         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2817
2818         spin_lock_irq(&drm_dev->event_lock);
2819         *val = acrtc->dm_irq_params.crc_window.y_start;
2820         spin_unlock_irq(&drm_dev->event_lock);
2821
2822         return 0;
2823 }
2824
2825 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
2826                          crc_win_y_start_set, "%llu\n");
2827
2828 /*
2829  * Set crc window coordinate x end
2830  */
2831 static int crc_win_x_end_set(void *data, u64 val)
2832 {
2833         struct drm_crtc *crtc = data;
2834         struct drm_device *drm_dev = crtc->dev;
2835         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2836
2837         spin_lock_irq(&drm_dev->event_lock);
2838         acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val;
2839         acrtc->dm_irq_params.crc_window.update_win = false;
2840         spin_unlock_irq(&drm_dev->event_lock);
2841
2842         return 0;
2843 }
2844
2845 /*
2846  * Get crc window coordinate x end
2847  */
2848 static int crc_win_x_end_get(void *data, u64 *val)
2849 {
2850         struct drm_crtc *crtc = data;
2851         struct drm_device *drm_dev = crtc->dev;
2852         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2853
2854         spin_lock_irq(&drm_dev->event_lock);
2855         *val = acrtc->dm_irq_params.crc_window.x_end;
2856         spin_unlock_irq(&drm_dev->event_lock);
2857
2858         return 0;
2859 }
2860
2861 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
2862                          crc_win_x_end_set, "%llu\n");
2863
2864 /*
2865  * Set crc window coordinate y end
2866  */
2867 static int crc_win_y_end_set(void *data, u64 val)
2868 {
2869         struct drm_crtc *crtc = data;
2870         struct drm_device *drm_dev = crtc->dev;
2871         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2872
2873         spin_lock_irq(&drm_dev->event_lock);
2874         acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val;
2875         acrtc->dm_irq_params.crc_window.update_win = false;
2876         spin_unlock_irq(&drm_dev->event_lock);
2877
2878         return 0;
2879 }
2880
2881 /*
2882  * Get crc window coordinate y end
2883  */
2884 static int crc_win_y_end_get(void *data, u64 *val)
2885 {
2886         struct drm_crtc *crtc = data;
2887         struct drm_device *drm_dev = crtc->dev;
2888         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2889
2890         spin_lock_irq(&drm_dev->event_lock);
2891         *val = acrtc->dm_irq_params.crc_window.y_end;
2892         spin_unlock_irq(&drm_dev->event_lock);
2893
2894         return 0;
2895 }
2896
2897 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
2898                          crc_win_y_end_set, "%llu\n");
2899 /*
2900  * Trigger to commit crc window
2901  */
2902 static int crc_win_update_set(void *data, u64 val)
2903 {
2904         struct drm_crtc *new_crtc = data;
2905         struct drm_crtc *old_crtc = NULL;
2906         struct amdgpu_crtc *new_acrtc, *old_acrtc;
2907         struct amdgpu_device *adev = drm_to_adev(new_crtc->dev);
2908         struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
2909
2910         if (val) {
2911                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
2912                 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
2913                 if (crc_rd_wrk && crc_rd_wrk->crtc) {
2914                         old_crtc = crc_rd_wrk->crtc;
2915                         old_acrtc = to_amdgpu_crtc(old_crtc);
2916                 }
2917                 new_acrtc = to_amdgpu_crtc(new_crtc);
2918
2919                 if (old_crtc && old_crtc != new_crtc) {
2920                         old_acrtc->dm_irq_params.crc_window.activated = false;
2921                         old_acrtc->dm_irq_params.crc_window.update_win = false;
2922                         old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2923
2924                         new_acrtc->dm_irq_params.crc_window.activated = true;
2925                         new_acrtc->dm_irq_params.crc_window.update_win = true;
2926                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2927                         crc_rd_wrk->crtc = new_crtc;
2928                 } else {
2929                         new_acrtc->dm_irq_params.crc_window.activated = true;
2930                         new_acrtc->dm_irq_params.crc_window.update_win = true;
2931                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2932                         crc_rd_wrk->crtc = new_crtc;
2933                 }
2934                 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
2935                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
2936         }
2937
2938         return 0;
2939 }
2940
2941 /*
2942  * Get crc window update flag
2943  */
2944 static int crc_win_update_get(void *data, u64 *val)
2945 {
2946         *val = 0;
2947         return 0;
2948 }
2949
2950 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
2951                          crc_win_update_set, "%llu\n");
2952
2953 void crtc_debugfs_init(struct drm_crtc *crtc)
2954 {
2955         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
2956
2957         if (!dir)
2958                 return;
2959
2960         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
2961                                    &crc_win_x_start_fops);
2962         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
2963                                    &crc_win_y_start_fops);
2964         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
2965                                    &crc_win_x_end_fops);
2966         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
2967                                    &crc_win_y_end_fops);
2968         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
2969                                    &crc_win_update_fops);
2970
2971 }
2972 #endif
2973 /*
2974  * Writes DTN log state to the user supplied buffer.
2975  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
2976  */
2977 static ssize_t dtn_log_read(
2978         struct file *f,
2979         char __user *buf,
2980         size_t size,
2981         loff_t *pos)
2982 {
2983         struct amdgpu_device *adev = file_inode(f)->i_private;
2984         struct dc *dc = adev->dm.dc;
2985         struct dc_log_buffer_ctx log_ctx = { 0 };
2986         ssize_t result = 0;
2987
2988         if (!buf || !size)
2989                 return -EINVAL;
2990
2991         if (!dc->hwss.log_hw_state)
2992                 return 0;
2993
2994         dc->hwss.log_hw_state(dc, &log_ctx);
2995
2996         if (*pos < log_ctx.pos) {
2997                 size_t to_copy = log_ctx.pos - *pos;
2998
2999                 to_copy = min(to_copy, size);
3000
3001                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3002                         *pos += to_copy;
3003                         result = to_copy;
3004                 }
3005         }
3006
3007         kfree(log_ctx.buf);
3008
3009         return result;
3010 }
3011
3012 /*
3013  * Writes DTN log state to dmesg when triggered via a write.
3014  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3015  */
3016 static ssize_t dtn_log_write(
3017         struct file *f,
3018         const char __user *buf,
3019         size_t size,
3020         loff_t *pos)
3021 {
3022         struct amdgpu_device *adev = file_inode(f)->i_private;
3023         struct dc *dc = adev->dm.dc;
3024
3025         /* Write triggers log output via dmesg. */
3026         if (size == 0)
3027                 return 0;
3028
3029         if (dc->hwss.log_hw_state)
3030                 dc->hwss.log_hw_state(dc, NULL);
3031
3032         return size;
3033 }
3034
3035 static int mst_topo_show(struct seq_file *m, void *unused)
3036 {
3037         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3038         struct drm_device *dev = adev_to_drm(adev);
3039         struct drm_connector *connector;
3040         struct drm_connector_list_iter conn_iter;
3041         struct amdgpu_dm_connector *aconnector;
3042
3043         drm_connector_list_iter_begin(dev, &conn_iter);
3044         drm_for_each_connector_iter(connector, &conn_iter) {
3045                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3046                         continue;
3047
3048                 aconnector = to_amdgpu_dm_connector(connector);
3049
3050                 /* Ensure we're only dumping the topology of a root mst node */
3051                 if (!aconnector->mst_mgr.mst_state)
3052                         continue;
3053
3054                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3055                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3056         }
3057         drm_connector_list_iter_end(&conn_iter);
3058
3059         return 0;
3060 }
3061
3062 /*
3063  * Sets trigger hpd for MST topologies.
3064  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3065  * All topologies will be disconnected if val of 0 is set .
3066  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3067  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3068  */
3069 static int trigger_hpd_mst_set(void *data, u64 val)
3070 {
3071         struct amdgpu_device *adev = data;
3072         struct drm_device *dev = adev_to_drm(adev);
3073         struct drm_connector_list_iter iter;
3074         struct amdgpu_dm_connector *aconnector;
3075         struct drm_connector *connector;
3076         struct dc_link *link = NULL;
3077
3078         if (val == 1) {
3079                 drm_connector_list_iter_begin(dev, &iter);
3080                 drm_for_each_connector_iter(connector, &iter) {
3081                         aconnector = to_amdgpu_dm_connector(connector);
3082                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3083                             aconnector->mst_mgr.aux) {
3084                                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3085                                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3086                         }
3087                 }
3088         } else if (val == 0) {
3089                 drm_connector_list_iter_begin(dev, &iter);
3090                 drm_for_each_connector_iter(connector, &iter) {
3091                         aconnector = to_amdgpu_dm_connector(connector);
3092                         if (!aconnector->dc_link)
3093                                 continue;
3094
3095                         if (!aconnector->mst_port)
3096                                 continue;
3097
3098                         link = aconnector->dc_link;
3099                         dp_receiver_power_ctrl(link, false);
3100                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false);
3101                         link->mst_stream_alloc_table.stream_count = 0;
3102                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3103                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3104                 }
3105         } else {
3106                 return 0;
3107         }
3108         drm_kms_helper_hotplug_event(dev);
3109
3110         return 0;
3111 }
3112
3113 /*
3114  * The interface doesn't need get function, so it will return the
3115  * value of zero
3116  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3117  */
3118 static int trigger_hpd_mst_get(void *data, u64 *val)
3119 {
3120         *val = 0;
3121         return 0;
3122 }
3123
3124 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3125                          trigger_hpd_mst_set, "%llu\n");
3126
3127
3128 /*
3129  * Sets the force_timing_sync debug option from the given string.
3130  * All connected displays will be force synchronized immediately.
3131  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3132  */
3133 static int force_timing_sync_set(void *data, u64 val)
3134 {
3135         struct amdgpu_device *adev = data;
3136
3137         adev->dm.force_timing_sync = (bool)val;
3138
3139         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3140
3141         return 0;
3142 }
3143
3144 /*
3145  * Gets the force_timing_sync debug option value into the given buffer.
3146  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3147  */
3148 static int force_timing_sync_get(void *data, u64 *val)
3149 {
3150         struct amdgpu_device *adev = data;
3151
3152         *val = adev->dm.force_timing_sync;
3153
3154         return 0;
3155 }
3156
3157 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3158                          force_timing_sync_set, "%llu\n");
3159
3160
3161 /*
3162  * Disables all HPD and HPD RX interrupt handling in the
3163  * driver when set to 1. Default is 0.
3164  */
3165 static int disable_hpd_set(void *data, u64 val)
3166 {
3167         struct amdgpu_device *adev = data;
3168
3169         adev->dm.disable_hpd_irq = (bool)val;
3170
3171         return 0;
3172 }
3173
3174
3175 /*
3176  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3177  * 0 otherwise.
3178  */
3179 static int disable_hpd_get(void *data, u64 *val)
3180 {
3181         struct amdgpu_device *adev = data;
3182
3183         *val = adev->dm.disable_hpd_irq;
3184
3185         return 0;
3186 }
3187
3188 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3189                          disable_hpd_set, "%llu\n");
3190
3191 /*
3192  * Sets the DC visual confirm debug option from the given string.
3193  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3194  */
3195 static int visual_confirm_set(void *data, u64 val)
3196 {
3197         struct amdgpu_device *adev = data;
3198
3199         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3200
3201         return 0;
3202 }
3203
3204 /*
3205  * Reads the DC visual confirm debug option value into the given buffer.
3206  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3207  */
3208 static int visual_confirm_get(void *data, u64 *val)
3209 {
3210         struct amdgpu_device *adev = data;
3211
3212         *val = adev->dm.dc->debug.visual_confirm;
3213
3214         return 0;
3215 }
3216
3217 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3218 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3219                          visual_confirm_set, "%llu\n");
3220
3221 /*
3222  * Dumps the DCC_EN bit for each pipe.
3223  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3224  */
3225 static ssize_t dcc_en_bits_read(
3226         struct file *f,
3227         char __user *buf,
3228         size_t size,
3229         loff_t *pos)
3230 {
3231         struct amdgpu_device *adev = file_inode(f)->i_private;
3232         struct dc *dc = adev->dm.dc;
3233         char *rd_buf = NULL;
3234         const uint32_t rd_buf_size = 32;
3235         uint32_t result = 0;
3236         int offset = 0;
3237         int num_pipes = dc->res_pool->pipe_count;
3238         int *dcc_en_bits;
3239         int i, r;
3240
3241         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3242         if (!dcc_en_bits)
3243                 return -ENOMEM;
3244
3245         if (!dc->hwss.get_dcc_en_bits) {
3246                 kfree(dcc_en_bits);
3247                 return 0;
3248         }
3249
3250         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3251
3252         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3253         if (!rd_buf)
3254                 return -ENOMEM;
3255
3256         for (i = 0; i < num_pipes; i++)
3257                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3258                                    "%d  ", dcc_en_bits[i]);
3259         rd_buf[strlen(rd_buf)] = '\n';
3260
3261         kfree(dcc_en_bits);
3262
3263         while (size) {
3264                 if (*pos >= rd_buf_size)
3265                         break;
3266                 r = put_user(*(rd_buf + result), buf);
3267                 if (r)
3268                         return r; /* r = -EFAULT */
3269                 buf += 1;
3270                 size -= 1;
3271                 *pos += 1;
3272                 result += 1;
3273         }
3274
3275         kfree(rd_buf);
3276         return result;
3277 }
3278
3279 void dtn_debugfs_init(struct amdgpu_device *adev)
3280 {
3281         static const struct file_operations dtn_log_fops = {
3282                 .owner = THIS_MODULE,
3283                 .read = dtn_log_read,
3284                 .write = dtn_log_write,
3285                 .llseek = default_llseek
3286         };
3287         static const struct file_operations dcc_en_bits_fops = {
3288                 .owner = THIS_MODULE,
3289                 .read = dcc_en_bits_read,
3290                 .llseek = default_llseek
3291         };
3292
3293         struct drm_minor *minor = adev_to_drm(adev)->primary;
3294         struct dentry *root = minor->debugfs_root;
3295
3296         debugfs_create_file("amdgpu_mst_topology", 0444, root,
3297                             adev, &mst_topo_fops);
3298         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
3299                             &dtn_log_fops);
3300
3301         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
3302                                    &visual_confirm_fops);
3303
3304         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3305                                    adev, &dmub_tracebuffer_fops);
3306
3307         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3308                                    adev, &dmub_fw_state_fops);
3309
3310         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3311                                    adev, &force_timing_sync_ops);
3312
3313         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3314                                    adev, &dmcub_trace_event_state_fops);
3315
3316         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
3317                                    adev, &trigger_hpd_mst_ops);
3318
3319         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
3320                                    &dcc_en_bits_fops);
3321
3322         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
3323                                    &disable_hpd_ops);
3324
3325 }