2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
36 #include "ast_tables.h"
38 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
39 static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
40 static int ast_cursor_set(struct drm_crtc *crtc,
41 struct drm_file *file_priv,
45 static int ast_cursor_move(struct drm_crtc *crtc,
48 static inline void ast_load_palette_index(struct ast_private *ast,
49 u8 index, u8 red, u8 green,
52 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
53 ast_io_read8(ast, AST_IO_SEQ_PORT);
54 ast_io_write8(ast, AST_IO_DAC_DATA, red);
55 ast_io_read8(ast, AST_IO_SEQ_PORT);
56 ast_io_write8(ast, AST_IO_DAC_DATA, green);
57 ast_io_read8(ast, AST_IO_SEQ_PORT);
58 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
59 ast_io_read8(ast, AST_IO_SEQ_PORT);
62 static void ast_crtc_load_lut(struct drm_crtc *crtc)
64 struct ast_private *ast = crtc->dev->dev_private;
65 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
71 for (i = 0; i < 256; i++)
72 ast_load_palette_index(ast, i, ast_crtc->lut_r[i],
73 ast_crtc->lut_g[i], ast_crtc->lut_b[i]);
76 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,
77 struct drm_display_mode *adjusted_mode,
78 struct ast_vbios_mode_info *vbios_mode)
80 struct ast_private *ast = crtc->dev->dev_private;
81 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
84 struct ast_vbios_enhtable *best = NULL;
86 switch (crtc->primary->fb->bits_per_pixel) {
88 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
89 color_index = VGAModeIndex - 1;
92 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
93 color_index = HiCModeIndex;
97 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
98 color_index = TrueCModeIndex;
104 switch (crtc->mode.crtc_hdisplay) {
106 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
109 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
112 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
115 if (crtc->mode.crtc_vdisplay == 800)
116 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
118 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
121 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
124 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
127 if (crtc->mode.crtc_vdisplay == 900)
128 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
130 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
133 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
136 if (crtc->mode.crtc_vdisplay == 1080)
137 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
139 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
145 refresh_rate = drm_mode_vrefresh(mode);
146 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
148 struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
150 while (loop->refresh_rate != 0xff) {
152 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
153 (loop->flags & PVSync)) ||
154 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
155 (loop->flags & NVSync)) ||
156 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
157 (loop->flags & PHSync)) ||
158 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
159 (loop->flags & NHSync)))) {
163 if (loop->refresh_rate <= refresh_rate
164 && (!best || loop->refresh_rate > best->refresh_rate))
168 if (best || !check_sync)
173 vbios_mode->enh_table = best;
175 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
176 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
178 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
179 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
180 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
181 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
182 vbios_mode->enh_table->hfp;
183 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
184 vbios_mode->enh_table->hfp +
185 vbios_mode->enh_table->hsync);
187 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
188 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
189 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
190 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
191 vbios_mode->enh_table->vfp;
192 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
193 vbios_mode->enh_table->vfp +
194 vbios_mode->enh_table->vsync);
196 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
197 mode_id = vbios_mode->enh_table->mode_id;
199 if (ast->chip == AST1180) {
202 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
203 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
206 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
207 if (vbios_mode->enh_table->flags & NewModeInfo) {
208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel);
210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
212 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
223 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
224 struct ast_vbios_mode_info *vbios_mode)
226 struct ast_private *ast = crtc->dev->dev_private;
227 struct ast_vbios_stdtable *stdtable;
231 stdtable = vbios_mode->std_table;
233 jreg = stdtable->misc;
234 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
237 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
238 for (i = 0; i < 4; i++) {
239 jreg = stdtable->seq[i];
242 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
246 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
247 for (i = 0; i < 25; i++)
248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
251 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
252 for (i = 0; i < 20; i++) {
253 jreg = stdtable->ar[i];
254 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
255 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
257 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
258 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
260 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
264 for (i = 0; i < 9; i++)
265 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
268 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
269 struct ast_vbios_mode_info *vbios_mode)
271 struct ast_private *ast = crtc->dev->dev_private;
272 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
275 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
277 temp = (mode->crtc_htotal >> 3) - 5;
279 jregAC |= 0x01; /* HT D[8] */
280 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
282 temp = (mode->crtc_hdisplay >> 3) - 1;
284 jregAC |= 0x04; /* HDE D[8] */
285 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
287 temp = (mode->crtc_hblank_start >> 3) - 1;
289 jregAC |= 0x10; /* HBS D[8] */
290 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
292 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
294 jreg05 |= 0x80; /* HBE D[5] */
296 jregAD |= 0x01; /* HBE D[5] */
297 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
299 temp = (mode->crtc_hsync_start >> 3) - 1;
301 jregAC |= 0x40; /* HRS D[5] */
302 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
304 temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f;
306 jregAD |= 0x04; /* HRE D[5] */
307 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
309 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
310 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
313 temp = (mode->crtc_vtotal) - 2;
320 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
322 temp = (mode->crtc_vsync_start) - 1;
329 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
331 temp = (mode->crtc_vsync_end - 1) & 0x3f;
336 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
338 temp = mode->crtc_vdisplay - 1;
345 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
347 temp = mode->crtc_vblank_start - 1;
354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
356 temp = mode->crtc_vblank_end - 1;
359 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
361 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
363 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
365 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
368 static void ast_set_offset_reg(struct drm_crtc *crtc)
370 struct ast_private *ast = crtc->dev->dev_private;
374 offset = crtc->primary->fb->pitches[0] >> 3;
375 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
376 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
379 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode,
380 struct ast_vbios_mode_info *vbios_mode)
382 struct ast_private *ast = dev->dev_private;
383 struct ast_vbios_dclk_info *clk_info;
385 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
387 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
388 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
390 (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4));
393 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
394 struct ast_vbios_mode_info *vbios_mode)
396 struct ast_private *ast = crtc->dev->dev_private;
397 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
399 switch (crtc->primary->fb->bits_per_pixel) {
418 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
419 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
420 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
423 if (ast->chip == AST2300 || ast->chip == AST2400) {
424 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
425 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
426 } else if (ast->chip == AST2100 ||
427 ast->chip == AST1100 ||
428 ast->chip == AST2200 ||
429 ast->chip == AST2150) {
430 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
433 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
434 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
438 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode,
439 struct ast_vbios_mode_info *vbios_mode)
441 struct ast_private *ast = dev->dev_private;
444 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
446 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
447 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
448 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
451 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
452 struct ast_vbios_mode_info *vbios_mode)
454 switch (crtc->primary->fb->bits_per_pixel) {
463 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset)
465 struct ast_private *ast = crtc->dev->dev_private;
469 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
470 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
471 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
475 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
477 struct ast_private *ast = crtc->dev->dev_private;
479 if (ast->chip == AST1180)
483 case DRM_MODE_DPMS_ON:
484 case DRM_MODE_DPMS_STANDBY:
485 case DRM_MODE_DPMS_SUSPEND:
486 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
487 if (ast->tx_chip_type == AST_TX_DP501)
488 ast_set_dp501_video_output(crtc->dev, 1);
489 ast_crtc_load_lut(crtc);
491 case DRM_MODE_DPMS_OFF:
492 if (ast->tx_chip_type == AST_TX_DP501)
493 ast_set_dp501_video_output(crtc->dev, 0);
494 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
499 static bool ast_crtc_mode_fixup(struct drm_crtc *crtc,
500 const struct drm_display_mode *mode,
501 struct drm_display_mode *adjusted_mode)
506 /* ast is different - we will force move buffers out of VRAM */
507 static int ast_crtc_do_set_base(struct drm_crtc *crtc,
508 struct drm_framebuffer *fb,
509 int x, int y, int atomic)
511 struct ast_private *ast = crtc->dev->dev_private;
512 struct drm_gem_object *obj;
513 struct ast_framebuffer *ast_fb;
518 /* push the previous fb to system ram */
520 ast_fb = to_ast_framebuffer(fb);
522 bo = gem_to_ast_bo(obj);
523 ret = ast_bo_reserve(bo, false);
526 ast_bo_push_sysram(bo);
527 ast_bo_unreserve(bo);
530 ast_fb = to_ast_framebuffer(crtc->primary->fb);
532 bo = gem_to_ast_bo(obj);
534 ret = ast_bo_reserve(bo, false);
538 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
540 ast_bo_unreserve(bo);
544 if (&ast->fbdev->afb == ast_fb) {
545 /* if pushing console in kmap it */
546 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
548 DRM_ERROR("failed to kmap fbcon\n");
550 ast_bo_unreserve(bo);
552 ast_set_start_address_crt1(crtc, (u32)gpu_addr);
557 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
558 struct drm_framebuffer *old_fb)
560 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0);
563 static int ast_crtc_mode_set(struct drm_crtc *crtc,
564 struct drm_display_mode *mode,
565 struct drm_display_mode *adjusted_mode,
567 struct drm_framebuffer *old_fb)
569 struct drm_device *dev = crtc->dev;
570 struct ast_private *ast = crtc->dev->dev_private;
571 struct ast_vbios_mode_info vbios_mode;
573 if (ast->chip == AST1180) {
574 DRM_ERROR("AST 1180 modesetting not supported\n");
578 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode);
583 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
585 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode);
586 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode);
587 ast_set_offset_reg(crtc);
588 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode);
589 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode);
590 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode);
591 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode);
593 ast_crtc_mode_set_base(crtc, x, y, old_fb);
598 static void ast_crtc_disable(struct drm_crtc *crtc)
603 static void ast_crtc_prepare(struct drm_crtc *crtc)
608 static void ast_crtc_commit(struct drm_crtc *crtc)
610 struct ast_private *ast = crtc->dev->dev_private;
611 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
615 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
616 .dpms = ast_crtc_dpms,
617 .mode_fixup = ast_crtc_mode_fixup,
618 .mode_set = ast_crtc_mode_set,
619 .mode_set_base = ast_crtc_mode_set_base,
620 .disable = ast_crtc_disable,
621 .load_lut = ast_crtc_load_lut,
622 .prepare = ast_crtc_prepare,
623 .commit = ast_crtc_commit,
627 static void ast_crtc_reset(struct drm_crtc *crtc)
632 static void ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
633 u16 *blue, uint32_t start, uint32_t size)
635 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
636 int end = (start + size > 256) ? 256 : start + size, i;
638 /* userspace palettes are always correct as is */
639 for (i = start; i < end; i++) {
640 ast_crtc->lut_r[i] = red[i] >> 8;
641 ast_crtc->lut_g[i] = green[i] >> 8;
642 ast_crtc->lut_b[i] = blue[i] >> 8;
644 ast_crtc_load_lut(crtc);
648 static void ast_crtc_destroy(struct drm_crtc *crtc)
650 drm_crtc_cleanup(crtc);
654 static const struct drm_crtc_funcs ast_crtc_funcs = {
655 .cursor_set = ast_cursor_set,
656 .cursor_move = ast_cursor_move,
657 .reset = ast_crtc_reset,
658 .set_config = drm_crtc_helper_set_config,
659 .gamma_set = ast_crtc_gamma_set,
660 .destroy = ast_crtc_destroy,
663 static int ast_crtc_init(struct drm_device *dev)
665 struct ast_crtc *crtc;
668 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
672 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs);
673 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
674 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
676 for (i = 0; i < 256; i++) {
684 static void ast_encoder_destroy(struct drm_encoder *encoder)
686 drm_encoder_cleanup(encoder);
691 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector)
693 int enc_id = connector->encoder_ids[0];
694 /* pick the encoder ids */
696 return drm_encoder_find(connector->dev, enc_id);
701 static const struct drm_encoder_funcs ast_enc_funcs = {
702 .destroy = ast_encoder_destroy,
705 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode)
710 static bool ast_mode_fixup(struct drm_encoder *encoder,
711 const struct drm_display_mode *mode,
712 struct drm_display_mode *adjusted_mode)
717 static void ast_encoder_mode_set(struct drm_encoder *encoder,
718 struct drm_display_mode *mode,
719 struct drm_display_mode *adjusted_mode)
723 static void ast_encoder_prepare(struct drm_encoder *encoder)
728 static void ast_encoder_commit(struct drm_encoder *encoder)
734 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = {
735 .dpms = ast_encoder_dpms,
736 .mode_fixup = ast_mode_fixup,
737 .prepare = ast_encoder_prepare,
738 .commit = ast_encoder_commit,
739 .mode_set = ast_encoder_mode_set,
742 static int ast_encoder_init(struct drm_device *dev)
744 struct ast_encoder *ast_encoder;
746 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
750 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
751 DRM_MODE_ENCODER_DAC);
752 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs);
754 ast_encoder->base.possible_crtcs = 1;
758 static int ast_get_modes(struct drm_connector *connector)
760 struct ast_connector *ast_connector = to_ast_connector(connector);
761 struct ast_private *ast = connector->dev->dev_private;
765 if (ast->tx_chip_type == AST_TX_DP501) {
766 ast->dp501_maxclk = 0xff;
767 edid = kmalloc(128, GFP_KERNEL);
771 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
773 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
778 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
780 drm_mode_connector_update_edid_property(&ast_connector->base, edid);
781 ret = drm_add_edid_modes(connector, edid);
785 drm_mode_connector_update_edid_property(&ast_connector->base, NULL);
789 static int ast_mode_valid(struct drm_connector *connector,
790 struct drm_display_mode *mode)
792 struct ast_private *ast = connector->dev->dev_private;
793 int flags = MODE_NOMODE;
796 if (ast->support_wide_screen) {
797 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
799 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
801 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
803 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
805 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
808 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
809 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
812 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
813 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
821 switch (mode->hdisplay) {
823 if (mode->vdisplay == 480) flags = MODE_OK;
826 if (mode->vdisplay == 600) flags = MODE_OK;
829 if (mode->vdisplay == 768) flags = MODE_OK;
832 if (mode->vdisplay == 1024) flags = MODE_OK;
835 if (mode->vdisplay == 1200) flags = MODE_OK;
844 static void ast_connector_destroy(struct drm_connector *connector)
846 struct ast_connector *ast_connector = to_ast_connector(connector);
847 ast_i2c_destroy(ast_connector->i2c);
848 drm_connector_unregister(connector);
849 drm_connector_cleanup(connector);
853 static enum drm_connector_status
854 ast_connector_detect(struct drm_connector *connector, bool force)
856 return connector_status_connected;
859 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
860 .mode_valid = ast_mode_valid,
861 .get_modes = ast_get_modes,
862 .best_encoder = ast_best_single_encoder,
865 static const struct drm_connector_funcs ast_connector_funcs = {
866 .dpms = drm_helper_connector_dpms,
867 .detect = ast_connector_detect,
868 .fill_modes = drm_helper_probe_single_connector_modes,
869 .destroy = ast_connector_destroy,
872 static int ast_connector_init(struct drm_device *dev)
874 struct ast_connector *ast_connector;
875 struct drm_connector *connector;
876 struct drm_encoder *encoder;
878 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
882 connector = &ast_connector->base;
883 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
885 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
887 connector->interlace_allowed = 0;
888 connector->doublescan_allowed = 0;
890 drm_connector_register(connector);
892 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
894 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
895 drm_mode_connector_attach_encoder(connector, encoder);
897 ast_connector->i2c = ast_i2c_create(dev);
898 if (!ast_connector->i2c)
899 DRM_ERROR("failed to add ddc bus for connector\n");
904 /* allocate cursor cache and pin at start of VRAM */
905 static int ast_cursor_init(struct drm_device *dev)
907 struct ast_private *ast = dev->dev_private;
910 struct drm_gem_object *obj;
914 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM;
916 ret = ast_gem_create(dev, size, true, &obj);
919 bo = gem_to_ast_bo(obj);
920 ret = ast_bo_reserve(bo, false);
921 if (unlikely(ret != 0))
924 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
925 ast_bo_unreserve(bo);
929 /* kmap the object */
930 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap);
934 ast->cursor_cache = obj;
935 ast->cursor_cache_gpu_addr = gpu_addr;
936 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
942 static void ast_cursor_fini(struct drm_device *dev)
944 struct ast_private *ast = dev->dev_private;
945 ttm_bo_kunmap(&ast->cache_kmap);
946 drm_gem_object_unreference_unlocked(ast->cursor_cache);
949 int ast_mode_init(struct drm_device *dev)
951 ast_cursor_init(dev);
953 ast_encoder_init(dev);
954 ast_connector_init(dev);
958 void ast_mode_fini(struct drm_device *dev)
960 ast_cursor_fini(dev);
963 static int get_clock(void *i2c_priv)
965 struct ast_i2c_chan *i2c = i2c_priv;
966 struct ast_private *ast = i2c->dev->dev_private;
969 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4;
970 return val & 1 ? 1 : 0;
973 static int get_data(void *i2c_priv)
975 struct ast_i2c_chan *i2c = i2c_priv;
976 struct ast_private *ast = i2c->dev->dev_private;
979 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5;
980 return val & 1 ? 1 : 0;
983 static void set_clock(void *i2c_priv, int clock)
985 struct ast_i2c_chan *i2c = i2c_priv;
986 struct ast_private *ast = i2c->dev->dev_private;
990 for (i = 0; i < 0x10000; i++) {
991 ujcrb7 = ((clock & 0x01) ? 0 : 1);
992 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7);
993 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
999 static void set_data(void *i2c_priv, int data)
1001 struct ast_i2c_chan *i2c = i2c_priv;
1002 struct ast_private *ast = i2c->dev->dev_private;
1006 for (i = 0; i < 0x10000; i++) {
1007 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1008 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7);
1009 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1010 if (ujcrb7 == jtemp)
1015 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1017 struct ast_i2c_chan *i2c;
1020 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1024 i2c->adapter.owner = THIS_MODULE;
1025 i2c->adapter.class = I2C_CLASS_DDC;
1026 i2c->adapter.dev.parent = &dev->pdev->dev;
1028 i2c_set_adapdata(&i2c->adapter, i2c);
1029 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1031 i2c->adapter.algo_data = &i2c->bit;
1033 i2c->bit.udelay = 20;
1034 i2c->bit.timeout = 2;
1035 i2c->bit.data = i2c;
1036 i2c->bit.setsda = set_data;
1037 i2c->bit.setscl = set_clock;
1038 i2c->bit.getsda = get_data;
1039 i2c->bit.getscl = get_clock;
1040 ret = i2c_bit_add_bus(&i2c->adapter);
1042 DRM_ERROR("Failed to register bit i2c\n");
1052 static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1056 i2c_del_adapter(&i2c->adapter);
1060 static void ast_show_cursor(struct drm_crtc *crtc)
1062 struct ast_private *ast = crtc->dev->dev_private;
1066 /* enable ARGB cursor */
1068 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1071 static void ast_hide_cursor(struct drm_crtc *crtc)
1073 struct ast_private *ast = crtc->dev->dev_private;
1074 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
1077 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1082 } srcdata32[2], data32;
1088 s32 alpha_dst_delta, last_alpha_dst_delta;
1089 u8 *srcxor, *dstxor;
1091 u32 per_pixel_copy, two_pixel_copy;
1093 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1094 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1097 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1098 per_pixel_copy = width & 1;
1099 two_pixel_copy = width >> 1;
1101 for (j = 0; j < height; j++) {
1102 for (i = 0; i < two_pixel_copy; i++) {
1103 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1104 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1105 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1106 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1107 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
1108 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
1110 writel(data32.ul, dstxor);
1118 for (i = 0; i < per_pixel_copy; i++) {
1119 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1120 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1121 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1122 writew(data16.us, dstxor);
1123 csum += (u32)data16.us;
1128 dstxor += last_alpha_dst_delta;
1133 static int ast_cursor_set(struct drm_crtc *crtc,
1134 struct drm_file *file_priv,
1139 struct ast_private *ast = crtc->dev->dev_private;
1140 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1141 struct drm_gem_object *obj;
1146 struct ttm_bo_kmap_obj uobj_map;
1148 bool src_isiomem, dst_isiomem;
1150 ast_hide_cursor(crtc);
1154 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT)
1157 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
1159 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle);
1162 bo = gem_to_ast_bo(obj);
1164 ret = ast_bo_reserve(bo, false);
1168 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map);
1170 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem);
1171 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem);
1173 if (src_isiomem == true)
1174 DRM_ERROR("src cursor bo should be in main memory\n");
1175 if (dst_isiomem == false)
1176 DRM_ERROR("dst bo should be in VRAM\n");
1178 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1180 /* do data transfer to cursor cache */
1181 csum = copy_cursor_image(src, dst, width, height);
1183 /* write checksum + signature */
1184 ttm_bo_kunmap(&uobj_map);
1185 ast_bo_unreserve(bo);
1187 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1189 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1190 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1191 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1192 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1194 /* set pattern offset */
1195 gpu_addr = ast->cursor_cache_gpu_addr;
1196 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1198 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
1199 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
1200 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
1202 ast_crtc->cursor_width = width;
1203 ast_crtc->cursor_height = height;
1204 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
1205 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
1207 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
1209 ast_show_cursor(crtc);
1211 drm_gem_object_unreference_unlocked(obj);
1214 drm_gem_object_unreference_unlocked(obj);
1218 static int ast_cursor_move(struct drm_crtc *crtc,
1221 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1222 struct ast_private *ast = crtc->dev->dev_private;
1223 int x_offset, y_offset;
1226 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1227 writel(x, sig + AST_HWC_SIGNATURE_X);
1228 writel(y, sig + AST_HWC_SIGNATURE_Y);
1230 x_offset = ast_crtc->offset_x;
1231 y_offset = ast_crtc->offset_y;
1233 x_offset = (-x) + ast_crtc->offset_x;
1238 y_offset = (-y) + ast_crtc->offset_y;
1241 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1242 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1243 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1244 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1245 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1248 /* dummy write to fire HWC */
1249 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00);