drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55
  56 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  57 {
  58         if (HAS_LLC(dev_priv)) {
  59                 /*
  60                  * WaCompressedResourceDisplayNewHashMode:skl,kbl
  61                  * Display WA #0390: skl,kbl
  62                  *
  63                  * Must match Sampler, Pixel Back End, and Media. See
  64                  * WaCompressedResourceSamplerPbeMediaNewHashMode.
  65                  */
  66                 I915_WRITE(CHICKEN_PAR1_1,
  67                            I915_READ(CHICKEN_PAR1_1) |
  68                            SKL_DE_COMPRESSED_HASH_MODE);
  69         }
  70
  71         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
  72         I915_WRITE(CHICKEN_PAR1_1,
  73                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  74
  75         /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
  76         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  77                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  78
  79         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
  80         /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
  81         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  82                    DISP_FBC_WM_DIS |
  83                    DISP_FBC_MEMORY_WAKE);
  84
  85         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
  86         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  87                    ILK_DPFC_DISABLE_DUMMY0);
  88
  89         if (IS_SKYLAKE(dev_priv)) {
  90                 /* WaDisableDopClockGating */
  91                 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
  92                            & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  93         }
  94 }
  95
  96 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
  97 {
  98         gen9_init_clock_gating(dev_priv);
  99
 100         /* WaDisableSDEUnitClockGating:bxt */
 101         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 102                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 103
 104         /*
 105          * FIXME:
 106          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 107          */
 108         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 109                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 110
 111         /*
 112          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 113          * to stay fully on.
 114          */
 115         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 116                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 117 }
 118
 119 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 120 {
 121         gen9_init_clock_gating(dev_priv);
 122
 123         /*
 124          * WaDisablePWMClockGating:glk
 125          * Backlight PWM may stop in the asserted state, causing backlight
 126          * to stay fully on.
 127          */
 128         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 129                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 130
 131         /* WaDDIIOTimeout:glk */
 132         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
 133                 u32 val = I915_READ(CHICKEN_MISC_2);
 134                 val &= ~(GLK_CL0_PWR_DOWN |
 135                          GLK_CL1_PWR_DOWN |
 136                          GLK_CL2_PWR_DOWN);
 137                 I915_WRITE(CHICKEN_MISC_2, val);
 138         }
 139
 140 }
 141
 142 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 143 {
 144         u32 tmp;
 145
 146         tmp = I915_READ(CLKCFG);
 147
 148         switch (tmp & CLKCFG_FSB_MASK) {
 149         case CLKCFG_FSB_533:
 150                 dev_priv->fsb_freq = 533; /* 133*4 */
 151                 break;
 152         case CLKCFG_FSB_800:
 153                 dev_priv->fsb_freq = 800; /* 200*4 */
 154                 break;
 155         case CLKCFG_FSB_667:
 156                 dev_priv->fsb_freq =  667; /* 167*4 */
 157                 break;
 158         case CLKCFG_FSB_400:
 159                 dev_priv->fsb_freq = 400; /* 100*4 */
 160                 break;
 161         }
 162
 163         switch (tmp & CLKCFG_MEM_MASK) {
 164         case CLKCFG_MEM_533:
 165                 dev_priv->mem_freq = 533;
 166                 break;
 167         case CLKCFG_MEM_667:
 168                 dev_priv->mem_freq = 667;
 169                 break;
 170         case CLKCFG_MEM_800:
 171                 dev_priv->mem_freq = 800;
 172                 break;
 173         }
 174
 175         /* detect pineview DDR3 setting */
 176         tmp = I915_READ(CSHRDDR3CTL);
 177         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 178 }
 179
 180 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 181 {
 182         u16 ddrpll, csipll;
 183
 184         ddrpll = I915_READ16(DDRMPLL1);
 185         csipll = I915_READ16(CSIPLL0);
 186
 187         switch (ddrpll & 0xff) {
 188         case 0xc:
 189                 dev_priv->mem_freq = 800;
 190                 break;
 191         case 0x10:
 192                 dev_priv->mem_freq = 1066;
 193                 break;
 194         case 0x14:
 195                 dev_priv->mem_freq = 1333;
 196                 break;
 197         case 0x18:
 198                 dev_priv->mem_freq = 1600;
 199                 break;
 200         default:
 201                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 202                                  ddrpll & 0xff);
 203                 dev_priv->mem_freq = 0;
 204                 break;
 205         }
 206
 207         dev_priv->ips.r_t = dev_priv->mem_freq;
 208
 209         switch (csipll & 0x3ff) {
 210         case 0x00c:
 211                 dev_priv->fsb_freq = 3200;
 212                 break;
 213         case 0x00e:
 214                 dev_priv->fsb_freq = 3733;
 215                 break;
 216         case 0x010:
 217                 dev_priv->fsb_freq = 4266;
 218                 break;
 219         case 0x012:
 220                 dev_priv->fsb_freq = 4800;
 221                 break;
 222         case 0x014:
 223                 dev_priv->fsb_freq = 5333;
 224                 break;
 225         case 0x016:
 226                 dev_priv->fsb_freq = 5866;
 227                 break;
 228         case 0x018:
 229                 dev_priv->fsb_freq = 6400;
 230                 break;
 231         default:
 232                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 233                                  csipll & 0x3ff);
 234                 dev_priv->fsb_freq = 0;
 235                 break;
 236         }
 237
 238         if (dev_priv->fsb_freq == 3200) {
 239                 dev_priv->ips.c_m = 0;
 240         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 241                 dev_priv->ips.c_m = 1;
 242         } else {
 243                 dev_priv->ips.c_m = 2;
 244         }
 245 }
 246
 247 static const struct cxsr_latency cxsr_latency_table[] = {
 248         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 249         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 250         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 251         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 252         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 253
 254         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 255         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 256         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 257         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 258         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 259
 260         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 261         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 262         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 263         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 264         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 265
 266         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 267         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 268         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 269         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 270         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 271
 272         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 273         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 274         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 275         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 276         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 277
 278         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 279         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 280         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 281         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 282         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 283 };
 284
 285 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 286                                                          bool is_ddr3,
 287                                                          int fsb,
 288                                                          int mem)
 289 {
 290         const struct cxsr_latency *latency;
 291         int i;
 292
 293         if (fsb == 0 || mem == 0)
 294                 return NULL;
 295
 296         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 297                 latency = &cxsr_latency_table[i];
 298                 if (is_desktop == latency->is_desktop &&
 299                     is_ddr3 == latency->is_ddr3 &&
 300                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 301                         return latency;
 302         }
 303
 304         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 305
 306         return NULL;
 307 }
 308
 309 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 310 {
 311         u32 val;
 312
 313         mutex_lock(&dev_priv->pcu_lock);
 314
 315         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 316         if (enable)
 317                 val &= ~FORCE_DDR_HIGH_FREQ;
 318         else
 319                 val |= FORCE_DDR_HIGH_FREQ;
 320         val &= ~FORCE_DDR_LOW_FREQ;
 321         val |= FORCE_DDR_FREQ_REQ_ACK;
 322         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 323
 324         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 325                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 326                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 327
 328         mutex_unlock(&dev_priv->pcu_lock);
 329 }
 330
 331 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 332 {
 333         u32 val;
 334
 335         mutex_lock(&dev_priv->pcu_lock);
 336
 337         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 338         if (enable)
 339                 val |= DSP_MAXFIFO_PM5_ENABLE;
 340         else
 341                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 342         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 343
 344         mutex_unlock(&dev_priv->pcu_lock);
 345 }
 346
 347 #define FW_WM(value, plane) \
 348         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 349
 350 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 351 {
 352         bool was_enabled;
 353         u32 val;
 354
 355         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 356                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 357                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 358                 POSTING_READ(FW_BLC_SELF_VLV);
 359         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 360                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 361                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 362                 POSTING_READ(FW_BLC_SELF);
 363         } else if (IS_PINEVIEW(dev_priv)) {
 364                 val = I915_READ(DSPFW3);
 365                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 366                 if (enable)
 367                         val |= PINEVIEW_SELF_REFRESH_EN;
 368                 else
 369                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 370                 I915_WRITE(DSPFW3, val);
 371                 POSTING_READ(DSPFW3);
 372         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 373                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 374                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 375                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 376                 I915_WRITE(FW_BLC_SELF, val);
 377                 POSTING_READ(FW_BLC_SELF);
 378         } else if (IS_I915GM(dev_priv)) {
 379                 /*
 380                  * FIXME can't find a bit like this for 915G, and
 381                  * and yet it does have the related watermark in
 382                  * FW_BLC_SELF. What's going on?
 383                  */
 384                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 385                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 386                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 387                 I915_WRITE(INSTPM, val);
 388                 POSTING_READ(INSTPM);
 389         } else {
 390                 return false;
 391         }
 392
 393         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 394
 395         DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
 396                       enableddisabled(enable),
 397                       enableddisabled(was_enabled));
 398
 399         return was_enabled;
 400 }
 401
 402 /**
 403  * intel_set_memory_cxsr - Configure CxSR state
 404  * @dev_priv: i915 device
 405  * @enable: Allow vs. disallow CxSR
 406  *
 407  * Allow or disallow the system to enter a special CxSR
 408  * (C-state self refresh) state. What typically happens in CxSR mode
 409  * is that several display FIFOs may get combined into a single larger
 410  * FIFO for a particular plane (so called max FIFO mode) to allow the
 411  * system to defer memory fetches longer, and the memory will enter
 412  * self refresh.
 413  *
 414  * Note that enabling CxSR does not guarantee that the system enter
 415  * this special mode, nor does it guarantee that the system stays
 416  * in that mode once entered. So this just allows/disallows the system
 417  * to autonomously utilize the CxSR mode. Other factors such as core
 418  * C-states will affect when/if the system actually enters/exits the
 419  * CxSR mode.
 420  *
 421  * Note that on VLV/CHV this actually only controls the max FIFO mode,
 422  * and the system is free to enter/exit memory self refresh at any time
 423  * even when the use of CxSR has been disallowed.
 424  *
 425  * While the system is actually in the CxSR/max FIFO mode, some plane
 426  * control registers will not get latched on vblank. Thus in order to
 427  * guarantee the system will respond to changes in the plane registers
 428  * we must always disallow CxSR prior to making changes to those registers.
 429  * Unfortunately the system will re-evaluate the CxSR conditions at
 430  * frame start which happens after vblank start (which is when the plane
 431  * registers would get latched), so we can't proceed with the plane update
 432  * during the same frame where we disallowed CxSR.
 433  *
 434  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
 435  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
 436  * the hardware w.r.t. HPLL SR when writing to plane registers.
 437  * Disallowing just CxSR is sufficient.
 438  */
 439 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 440 {
 441         bool ret;
 442
 443         mutex_lock(&dev_priv->wm.wm_mutex);
 444         ret = _intel_set_memory_cxsr(dev_priv, enable);
 445         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 446                 dev_priv->wm.vlv.cxsr = enable;
 447         else if (IS_G4X(dev_priv))
 448                 dev_priv->wm.g4x.cxsr = enable;
 449         mutex_unlock(&dev_priv->wm.wm_mutex);
 450
 451         return ret;
 452 }
 453
 454 /*
 455  * Latency for FIFO fetches is dependent on several factors:
 456  *   - memory configuration (speed, channels)
 457  *   - chipset
 458  *   - current MCH state
 459  * It can be fairly high in some situations, so here we assume a fairly
 460  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 461  * set this value too high, the FIFO will fetch frequently to stay full)
 462  * and power consumption (set it too low to save power and we might see
 463  * FIFO underruns and display "flicker").
 464  *
 465  * A value of 5us seems to be a good balance; safe for very low end
 466  * platforms but not overly aggressive on lower latency configs.
 467  */
 468 static const int pessimal_latency_ns = 5000;
 469
 470 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 471         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 472
 473 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 474 {
 475         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 476         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 477         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 478         enum pipe pipe = crtc->pipe;
 479         int sprite0_start, sprite1_start;
 480
 481         switch (pipe) {
 482                 uint32_t dsparb, dsparb2, dsparb3;
 483         case PIPE_A:
 484                 dsparb = I915_READ(DSPARB);
 485                 dsparb2 = I915_READ(DSPARB2);
 486                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 487                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 488                 break;
 489         case PIPE_B:
 490                 dsparb = I915_READ(DSPARB);
 491                 dsparb2 = I915_READ(DSPARB2);
 492                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 493                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 494                 break;
 495         case PIPE_C:
 496                 dsparb2 = I915_READ(DSPARB2);
 497                 dsparb3 = I915_READ(DSPARB3);
 498                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 499                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 500                 break;
 501         default:
 502                 MISSING_CASE(pipe);
 503                 return;
 504         }
 505
 506         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 507         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 508         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 509         fifo_state->plane[PLANE_CURSOR] = 63;
 510 }
 511
 512 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 513                               enum i9xx_plane_id i9xx_plane)
 514 {
 515         uint32_t dsparb = I915_READ(DSPARB);
 516         int size;
 517
 518         size = dsparb & 0x7f;
 519         if (i9xx_plane == PLANE_B)
 520                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 521
 522         DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
 523                       dsparb, plane_name(i9xx_plane), size);
 524
 525         return size;
 526 }
 527
 528 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 529                               enum i9xx_plane_id i9xx_plane)
 530 {
 531         uint32_t dsparb = I915_READ(DSPARB);
 532         int size;
 533
 534         size = dsparb & 0x1ff;
 535         if (i9xx_plane == PLANE_B)
 536                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 537         size >>= 1; /* Convert to cachelines */
 538
 539         DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
 540                       dsparb, plane_name(i9xx_plane), size);
 541
 542         return size;
 543 }
 544
 545 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
 546                               enum i9xx_plane_id i9xx_plane)
 547 {
 548         uint32_t dsparb = I915_READ(DSPARB);
 549         int size;
 550
 551         size = dsparb & 0x7f;
 552         size >>= 2; /* Convert to cachelines */
 553
 554         DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
 555                       dsparb, plane_name(i9xx_plane), size);
 556
 557         return size;
 558 }
 559
 560 /* Pineview has different values for various configs */
 561 static const struct intel_watermark_params pineview_display_wm = {
 562         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 563         .max_wm = PINEVIEW_MAX_WM,
 564         .default_wm = PINEVIEW_DFT_WM,
 565         .guard_size = PINEVIEW_GUARD_WM,
 566         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 567 };
 568 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 569         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 570         .max_wm = PINEVIEW_MAX_WM,
 571         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 572         .guard_size = PINEVIEW_GUARD_WM,
 573         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 574 };
 575 static const struct intel_watermark_params pineview_cursor_wm = {
 576         .fifo_size = PINEVIEW_CURSOR_FIFO,
 577         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 578         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 579         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 580         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 581 };
 582 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 583         .fifo_size = PINEVIEW_CURSOR_FIFO,
 584         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 585         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 586         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 587         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 588 };
 589 static const struct intel_watermark_params i965_cursor_wm_info = {
 590         .fifo_size = I965_CURSOR_FIFO,
 591         .max_wm = I965_CURSOR_MAX_WM,
 592         .default_wm = I965_CURSOR_DFT_WM,
 593         .guard_size = 2,
 594         .cacheline_size = I915_FIFO_LINE_SIZE,
 595 };
 596 static const struct intel_watermark_params i945_wm_info = {
 597         .fifo_size = I945_FIFO_SIZE,
 598         .max_wm = I915_MAX_WM,
 599         .default_wm = 1,
 600         .guard_size = 2,
 601         .cacheline_size = I915_FIFO_LINE_SIZE,
 602 };
 603 static const struct intel_watermark_params i915_wm_info = {
 604         .fifo_size = I915_FIFO_SIZE,
 605         .max_wm = I915_MAX_WM,
 606         .default_wm = 1,
 607         .guard_size = 2,
 608         .cacheline_size = I915_FIFO_LINE_SIZE,
 609 };
 610 static const struct intel_watermark_params i830_a_wm_info = {
 611         .fifo_size = I855GM_FIFO_SIZE,
 612         .max_wm = I915_MAX_WM,
 613         .default_wm = 1,
 614         .guard_size = 2,
 615         .cacheline_size = I830_FIFO_LINE_SIZE,
 616 };
 617 static const struct intel_watermark_params i830_bc_wm_info = {
 618         .fifo_size = I855GM_FIFO_SIZE,
 619         .max_wm = I915_MAX_WM/2,
 620         .default_wm = 1,
 621         .guard_size = 2,
 622         .cacheline_size = I830_FIFO_LINE_SIZE,
 623 };
 624 static const struct intel_watermark_params i845_wm_info = {
 625         .fifo_size = I830_FIFO_SIZE,
 626         .max_wm = I915_MAX_WM,
 627         .default_wm = 1,
 628         .guard_size = 2,
 629         .cacheline_size = I830_FIFO_LINE_SIZE,
 630 };
 631
 632 /**
 633  * intel_wm_method1 - Method 1 / "small buffer" watermark formula
 634  * @pixel_rate: Pipe pixel rate in kHz
 635  * @cpp: Plane bytes per pixel
 636  * @latency: Memory wakeup latency in 0.1us units
 637  *
 638  * Compute the watermark using the method 1 or "small buffer"
 639  * formula. The caller may additonally add extra cachelines
 640  * to account for TLB misses and clock crossings.
 641  *
 642  * This method is concerned with the short term drain rate
 643  * of the FIFO, ie. it does not account for blanking periods
 644  * which would effectively reduce the average drain rate across
 645  * a longer period. The name "small" refers to the fact the
 646  * FIFO is relatively small compared to the amount of data
 647  * fetched.
 648  *
 649  * The FIFO level vs. time graph might look something like:
 650  *
 651  *   |\   |\
 652  *   | \  | \
 653  * __---__---__ (- plane active, _ blanking)
 654  * -> time
 655  *
 656  * or perhaps like this:
 657  *
 658  *   |\|\  |\|\
 659  * __----__----__ (- plane active, _ blanking)
 660  * -> time
 661  *
 662  * Returns:
 663  * The watermark in bytes
 664  */
 665 static unsigned int intel_wm_method1(unsigned int pixel_rate,
 666                                      unsigned int cpp,
 667                                      unsigned int latency)
 668 {
 669         uint64_t ret;
 670
 671         ret = (uint64_t) pixel_rate * cpp * latency;
 672         ret = DIV_ROUND_UP_ULL(ret, 10000);
 673
 674         return ret;
 675 }
 676
 677 /**
 678  * intel_wm_method2 - Method 2 / "large buffer" watermark formula
 679  * @pixel_rate: Pipe pixel rate in kHz
 680  * @htotal: Pipe horizontal total
 681  * @width: Plane width in pixels
 682  * @cpp: Plane bytes per pixel
 683  * @latency: Memory wakeup latency in 0.1us units
 684  *
 685  * Compute the watermark using the method 2 or "large buffer"
 686  * formula. The caller may additonally add extra cachelines
 687  * to account for TLB misses and clock crossings.
 688  *
 689  * This method is concerned with the long term drain rate
 690  * of the FIFO, ie. it does account for blanking periods
 691  * which effectively reduce the average drain rate across
 692  * a longer period. The name "large" refers to the fact the
 693  * FIFO is relatively large compared to the amount of data
 694  * fetched.
 695  *
 696  * The FIFO level vs. time graph might look something like:
 697  *
 698  *    |\___       |\___
 699  *    |    \___   |    \___
 700  *    |        \  |        \
 701  * __ --__--__--__--__--__--__ (- plane active, _ blanking)
 702  * -> time
 703  *
 704  * Returns:
 705  * The watermark in bytes
 706  */
 707 static unsigned int intel_wm_method2(unsigned int pixel_rate,
 708                                      unsigned int htotal,
 709                                      unsigned int width,
 710                                      unsigned int cpp,
 711                                      unsigned int latency)
 712 {
 713         unsigned int ret;
 714
 715         /*
 716          * FIXME remove once all users are computing
 717          * watermarks in the correct place.
 718          */
 719         if (WARN_ON_ONCE(htotal == 0))
 720                 htotal = 1;
 721
 722         ret = (latency * pixel_rate) / (htotal * 10000);
 723         ret = (ret + 1) * width * cpp;
 724
 725         return ret;
 726 }
 727
 728 /**
 729  * intel_calculate_wm - calculate watermark level
 730  * @pixel_rate: pixel clock
 731  * @wm: chip FIFO params
 732  * @fifo_size: size of the FIFO buffer
 733  * @cpp: bytes per pixel
 734  * @latency_ns: memory latency for the platform
 735  *
 736  * Calculate the watermark level (the level at which the display plane will
 737  * start fetching from memory again).  Each chip has a different display
 738  * FIFO size and allocation, so the caller needs to figure that out and pass
 739  * in the correct intel_watermark_params structure.
 740  *
 741  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 742  * on the pixel size.  When it reaches the watermark level, it'll start
 743  * fetching FIFO line sized based chunks from memory until the FIFO fills
 744  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 745  * will occur, and a display engine hang could result.
 746  */
 747 static unsigned int intel_calculate_wm(int pixel_rate,
 748                                        const struct intel_watermark_params *wm,
 749                                        int fifo_size, int cpp,
 750                                        unsigned int latency_ns)
 751 {
 752         int entries, wm_size;
 753
 754         /*
 755          * Note: we need to make sure we don't overflow for various clock &
 756          * latency values.
 757          * clocks go from a few thousand to several hundred thousand.
 758          * latency is usually a few thousand
 759          */
 760         entries = intel_wm_method1(pixel_rate, cpp,
 761                                    latency_ns / 100);
 762         entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 763                 wm->guard_size;
 764         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 765
 766         wm_size = fifo_size - entries;
 767         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 768
 769         /* Don't promote wm_size to unsigned... */
 770         if (wm_size > wm->max_wm)
 771                 wm_size = wm->max_wm;
 772         if (wm_size <= 0)
 773                 wm_size = wm->default_wm;
 774
 775         /*
 776          * Bspec seems to indicate that the value shouldn't be lower than
 777          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 778          * Lets go for 8 which is the burst size since certain platforms
 779          * already use a hardcoded 8 (which is what the spec says should be
 780          * done).
 781          */
 782         if (wm_size <= 8)
 783                 wm_size = 8;
 784
 785         return wm_size;
 786 }
 787
 788 static bool is_disabling(int old, int new, int threshold)
 789 {
 790         return old >= threshold && new < threshold;
 791 }
 792
 793 static bool is_enabling(int old, int new, int threshold)
 794 {
 795         return old < threshold && new >= threshold;
 796 }
 797
 798 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 799 {
 800         return dev_priv->wm.max_level + 1;
 801 }
 802
 803 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 804                                    const struct intel_plane_state *plane_state)
 805 {
 806         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 807
 808         /* FIXME check the 'enable' instead */
 809         if (!crtc_state->base.active)
 810                 return false;
 811
 812         /*
 813          * Treat cursor with fb as always visible since cursor updates
 814          * can happen faster than the vrefresh rate, and the current
 815          * watermark code doesn't handle that correctly. Cursor updates
 816          * which set/clear the fb or change the cursor size are going
 817          * to get throttled by intel_legacy_cursor_update() to work
 818          * around this problem with the watermark code.
 819          */
 820         if (plane->id == PLANE_CURSOR)
 821                 return plane_state->base.fb != NULL;
 822         else
 823                 return plane_state->base.visible;
 824 }
 825
 826 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 827 {
 828         struct intel_crtc *crtc, *enabled = NULL;
 829
 830         for_each_intel_crtc(&dev_priv->drm, crtc) {
 831                 if (intel_crtc_active(crtc)) {
 832                         if (enabled)
 833                                 return NULL;
 834                         enabled = crtc;
 835                 }
 836         }
 837
 838         return enabled;
 839 }
 840
 841 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 842 {
 843         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 844         struct intel_crtc *crtc;
 845         const struct cxsr_latency *latency;
 846         u32 reg;
 847         unsigned int wm;
 848
 849         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 850                                          dev_priv->is_ddr3,
 851                                          dev_priv->fsb_freq,
 852                                          dev_priv->mem_freq);
 853         if (!latency) {
 854                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 855                 intel_set_memory_cxsr(dev_priv, false);
 856                 return;
 857         }
 858
 859         crtc = single_enabled_crtc(dev_priv);
 860         if (crtc) {
 861                 const struct drm_display_mode *adjusted_mode =
 862                         &crtc->config->base.adjusted_mode;
 863                 const struct drm_framebuffer *fb =
 864                         crtc->base.primary->state->fb;
 865                 int cpp = fb->format->cpp[0];
 866                 int clock = adjusted_mode->crtc_clock;
 867
 868                 /* Display SR */
 869                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 870                                         pineview_display_wm.fifo_size,
 871                                         cpp, latency->display_sr);
 872                 reg = I915_READ(DSPFW1);
 873                 reg &= ~DSPFW_SR_MASK;
 874                 reg |= FW_WM(wm, SR);
 875                 I915_WRITE(DSPFW1, reg);
 876                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 877
 878                 /* cursor SR */
 879                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 880                                         pineview_display_wm.fifo_size,
 881                                         4, latency->cursor_sr);
 882                 reg = I915_READ(DSPFW3);
 883                 reg &= ~DSPFW_CURSOR_SR_MASK;
 884                 reg |= FW_WM(wm, CURSOR_SR);
 885                 I915_WRITE(DSPFW3, reg);
 886
 887                 /* Display HPLL off SR */
 888                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 889                                         pineview_display_hplloff_wm.fifo_size,
 890                                         cpp, latency->display_hpll_disable);
 891                 reg = I915_READ(DSPFW3);
 892                 reg &= ~DSPFW_HPLL_SR_MASK;
 893                 reg |= FW_WM(wm, HPLL_SR);
 894                 I915_WRITE(DSPFW3, reg);
 895
 896                 /* cursor HPLL off SR */
 897                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 898                                         pineview_display_hplloff_wm.fifo_size,
 899                                         4, latency->cursor_hpll_disable);
 900                 reg = I915_READ(DSPFW3);
 901                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 902                 reg |= FW_WM(wm, HPLL_CURSOR);
 903                 I915_WRITE(DSPFW3, reg);
 904                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 905
 906                 intel_set_memory_cxsr(dev_priv, true);
 907         } else {
 908                 intel_set_memory_cxsr(dev_priv, false);
 909         }
 910 }
 911
 912 /*
 913  * Documentation says:
 914  * "If the line size is small, the TLB fetches can get in the way of the
 915  *  data fetches, causing some lag in the pixel data return which is not
 916  *  accounted for in the above formulas. The following adjustment only
 917  *  needs to be applied if eight whole lines fit in the buffer at once.
 918  *  The WM is adjusted upwards by the difference between the FIFO size
 919  *  and the size of 8 whole lines. This adjustment is always performed
 920  *  in the actual pixel depth regardless of whether FBC is enabled or not."
 921  */
 922 static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
 923 {
 924         int tlb_miss = fifo_size * 64 - width * cpp * 8;
 925
 926         return max(0, tlb_miss);
 927 }
 928
 929 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 930                                 const struct g4x_wm_values *wm)
 931 {
 932         enum pipe pipe;
 933
 934         for_each_pipe(dev_priv, pipe)
 935                 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 936
 937         I915_WRITE(DSPFW1,
 938                    FW_WM(wm->sr.plane, SR) |
 939                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 940                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 941                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 942         I915_WRITE(DSPFW2,
 943                    (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 944                    FW_WM(wm->sr.fbc, FBC_SR) |
 945                    FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 946                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 947                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 948                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 949         I915_WRITE(DSPFW3,
 950                    (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 951                    FW_WM(wm->sr.cursor, CURSOR_SR) |
 952                    FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 953                    FW_WM(wm->hpll.plane, HPLL_SR));
 954
 955         POSTING_READ(DSPFW1);
 956 }
 957
 958 #define FW_WM_VLV(value, plane) \
 959         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 960
 961 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 962                                 const struct vlv_wm_values *wm)
 963 {
 964         enum pipe pipe;
 965
 966         for_each_pipe(dev_priv, pipe) {
 967                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 968
 969                 I915_WRITE(VLV_DDL(pipe),
 970                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 971                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 972                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
 973                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
 974         }
 975
 976         /*
 977          * Zero the (unused) WM1 watermarks, and also clear all the
 978          * high order bits so that there are no out of bounds values
 979          * present in the registers during the reprogramming.
 980          */
 981         I915_WRITE(DSPHOWM, 0);
 982         I915_WRITE(DSPHOWM1, 0);
 983         I915_WRITE(DSPFW4, 0);
 984         I915_WRITE(DSPFW5, 0);
 985         I915_WRITE(DSPFW6, 0);
 986
 987         I915_WRITE(DSPFW1,
 988                    FW_WM(wm->sr.plane, SR) |
 989                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 990                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 991                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 992         I915_WRITE(DSPFW2,
 993                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 994                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 995                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 996         I915_WRITE(DSPFW3,
 997                    FW_WM(wm->sr.cursor, CURSOR_SR));
 998
 999         if (IS_CHERRYVIEW(dev_priv)) {
1000                 I915_WRITE(DSPFW7_CHV,
1001                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1002                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1003                 I915_WRITE(DSPFW8_CHV,
1004                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1005                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1006                 I915_WRITE(DSPFW9_CHV,
1007                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1008                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1009                 I915_WRITE(DSPHOWM,
1010                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1011                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1012                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1013                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1014                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1015                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1016                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1017                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1018                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1019                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1020         } else {
1021                 I915_WRITE(DSPFW7,
1022                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1023                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1024                 I915_WRITE(DSPHOWM,
1025                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1026                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1027                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1028                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1029                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1030                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1031                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1032         }
1033
1034         POSTING_READ(DSPFW1);
1035 }
1036
1037 #undef FW_WM_VLV
1038
1039 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1040 {
1041         /* all latencies in usec */
1042         dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1043         dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1044         dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1045
1046         dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1047 }
1048
1049 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1050 {
1051         /*
1052          * DSPCNTR[13] supposedly controls whether the
1053          * primary plane can use the FIFO space otherwise
1054          * reserved for the sprite plane. It's not 100% clear
1055          * what the actual FIFO size is, but it looks like we
1056          * can happily set both primary and sprite watermarks
1057          * up to 127 cachelines. So that would seem to mean
1058          * that either DSPCNTR[13] doesn't do anything, or that
1059          * the total FIFO is >= 256 cachelines in size. Either
1060          * way, we don't seem to have to worry about this
1061          * repartitioning as the maximum watermark value the
1062          * register can hold for each plane is lower than the
1063          * minimum FIFO size.
1064          */
1065         switch (plane_id) {
1066         case PLANE_CURSOR:
1067                 return 63;
1068         case PLANE_PRIMARY:
1069                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1070         case PLANE_SPRITE0:
1071                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1072         default:
1073                 MISSING_CASE(plane_id);
1074                 return 0;
1075         }
1076 }
1077
1078 static int g4x_fbc_fifo_size(int level)
1079 {
1080         switch (level) {
1081         case G4X_WM_LEVEL_SR:
1082                 return 7;
1083         case G4X_WM_LEVEL_HPLL:
1084                 return 15;
1085         default:
1086                 MISSING_CASE(level);
1087                 return 0;
1088         }
1089 }
1090
1091 static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1092                                const struct intel_plane_state *plane_state,
1093                                int level)
1094 {
1095         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1096         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1097         const struct drm_display_mode *adjusted_mode =
1098                 &crtc_state->base.adjusted_mode;
1099         unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1100         unsigned int clock, htotal, cpp, width, wm;
1101
1102         if (latency == 0)
1103                 return USHRT_MAX;
1104
1105         if (!intel_wm_plane_visible(crtc_state, plane_state))
1106                 return 0;
1107
1108         /*
1109          * Not 100% sure which way ELK should go here as the
1110          * spec only says CL/CTG should assume 32bpp and BW
1111          * doesn't need to. But as these things followed the
1112          * mobile vs. desktop lines on gen3 as well, let's
1113          * assume ELK doesn't need this.
1114          *
1115          * The spec also fails to list such a restriction for
1116          * the HPLL watermark, which seems a little strange.
1117          * Let's use 32bpp for the HPLL watermark as well.
1118          */
1119         if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1120             level != G4X_WM_LEVEL_NORMAL)
1121                 cpp = 4;
1122         else
1123                 cpp = plane_state->base.fb->format->cpp[0];
1124
1125         clock = adjusted_mode->crtc_clock;
1126         htotal = adjusted_mode->crtc_htotal;
1127
1128         if (plane->id == PLANE_CURSOR)
1129                 width = plane_state->base.crtc_w;
1130         else
1131                 width = drm_rect_width(&plane_state->base.dst);
1132
1133         if (plane->id == PLANE_CURSOR) {
1134                 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1135         } else if (plane->id == PLANE_PRIMARY &&
1136                    level == G4X_WM_LEVEL_NORMAL) {
1137                 wm = intel_wm_method1(clock, cpp, latency);
1138         } else {
1139                 unsigned int small, large;
1140
1141                 small = intel_wm_method1(clock, cpp, latency);
1142                 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1143
1144                 wm = min(small, large);
1145         }
1146
1147         wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1148                               width, cpp);
1149
1150         wm = DIV_ROUND_UP(wm, 64) + 2;
1151
1152         return min_t(unsigned int, wm, USHRT_MAX);
1153 }
1154
1155 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1156                                  int level, enum plane_id plane_id, u16 value)
1157 {
1158         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1159         bool dirty = false;
1160
1161         for (; level < intel_wm_num_levels(dev_priv); level++) {
1162                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1163
1164                 dirty |= raw->plane[plane_id] != value;
1165                 raw->plane[plane_id] = value;
1166         }
1167
1168         return dirty;
1169 }
1170
1171 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1172                                int level, u16 value)
1173 {
1174         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1175         bool dirty = false;
1176
1177         /* NORMAL level doesn't have an FBC watermark */
1178         level = max(level, G4X_WM_LEVEL_SR);
1179
1180         for (; level < intel_wm_num_levels(dev_priv); level++) {
1181                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1182
1183                 dirty |= raw->fbc != value;
1184                 raw->fbc = value;
1185         }
1186
1187         return dirty;
1188 }
1189
1190 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1191                                    const struct intel_plane_state *pstate,
1192                                    uint32_t pri_val);
1193
1194 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1195                                      const struct intel_plane_state *plane_state)
1196 {
1197         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1198         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1199         enum plane_id plane_id = plane->id;
1200         bool dirty = false;
1201         int level;
1202
1203         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1204                 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1205                 if (plane_id == PLANE_PRIMARY)
1206                         dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1207                 goto out;
1208         }
1209
1210         for (level = 0; level < num_levels; level++) {
1211                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1212                 int wm, max_wm;
1213
1214                 wm = g4x_compute_wm(crtc_state, plane_state, level);
1215                 max_wm = g4x_plane_fifo_size(plane_id, level);
1216
1217                 if (wm > max_wm)
1218                         break;
1219
1220                 dirty |= raw->plane[plane_id] != wm;
1221                 raw->plane[plane_id] = wm;
1222
1223                 if (plane_id != PLANE_PRIMARY ||
1224                     level == G4X_WM_LEVEL_NORMAL)
1225                         continue;
1226
1227                 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1228                                         raw->plane[plane_id]);
1229                 max_wm = g4x_fbc_fifo_size(level);
1230
1231                 /*
1232                  * FBC wm is not mandatory as we
1233                  * can always just disable its use.
1234                  */
1235                 if (wm > max_wm)
1236                         wm = USHRT_MAX;
1237
1238                 dirty |= raw->fbc != wm;
1239                 raw->fbc = wm;
1240         }
1241
1242         /* mark watermarks as invalid */
1243         dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1244
1245         if (plane_id == PLANE_PRIMARY)
1246                 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1247
1248  out:
1249         if (dirty) {
1250                 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1251                               plane->base.name,
1252                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1253                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1254                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1255
1256                 if (plane_id == PLANE_PRIMARY)
1257                         DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1258                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1259                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1260         }
1261
1262         return dirty;
1263 }
1264
1265 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1266                                       enum plane_id plane_id, int level)
1267 {
1268         const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1269
1270         return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1271 }
1272
1273 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1274                                      int level)
1275 {
1276         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1277
1278         if (level > dev_priv->wm.max_level)
1279                 return false;
1280
1281         return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1282                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1283                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1284 }
1285
1286 /* mark all levels starting from 'level' as invalid */
1287 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1288                                struct g4x_wm_state *wm_state, int level)
1289 {
1290         if (level <= G4X_WM_LEVEL_NORMAL) {
1291                 enum plane_id plane_id;
1292
1293                 for_each_plane_id_on_crtc(crtc, plane_id)
1294                         wm_state->wm.plane[plane_id] = USHRT_MAX;
1295         }
1296
1297         if (level <= G4X_WM_LEVEL_SR) {
1298                 wm_state->cxsr = false;
1299                 wm_state->sr.cursor = USHRT_MAX;
1300                 wm_state->sr.plane = USHRT_MAX;
1301                 wm_state->sr.fbc = USHRT_MAX;
1302         }
1303
1304         if (level <= G4X_WM_LEVEL_HPLL) {
1305                 wm_state->hpll_en = false;
1306                 wm_state->hpll.cursor = USHRT_MAX;
1307                 wm_state->hpll.plane = USHRT_MAX;
1308                 wm_state->hpll.fbc = USHRT_MAX;
1309         }
1310 }
1311
1312 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1313 {
1314         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1315         struct intel_atomic_state *state =
1316                 to_intel_atomic_state(crtc_state->base.state);
1317         struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1318         int num_active_planes = hweight32(crtc_state->active_planes &
1319                                           ~BIT(PLANE_CURSOR));
1320         const struct g4x_pipe_wm *raw;
1321         const struct intel_plane_state *old_plane_state;
1322         const struct intel_plane_state *new_plane_state;
1323         struct intel_plane *plane;
1324         enum plane_id plane_id;
1325         int i, level;
1326         unsigned int dirty = 0;
1327
1328         for_each_oldnew_intel_plane_in_state(state, plane,
1329                                              old_plane_state,
1330                                              new_plane_state, i) {
1331                 if (new_plane_state->base.crtc != &crtc->base &&
1332                     old_plane_state->base.crtc != &crtc->base)
1333                         continue;
1334
1335                 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1336                         dirty |= BIT(plane->id);
1337         }
1338
1339         if (!dirty)
1340                 return 0;
1341
1342         level = G4X_WM_LEVEL_NORMAL;
1343         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1344                 goto out;
1345
1346         raw = &crtc_state->wm.g4x.raw[level];
1347         for_each_plane_id_on_crtc(crtc, plane_id)
1348                 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1349
1350         level = G4X_WM_LEVEL_SR;
1351
1352         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1353                 goto out;
1354
1355         raw = &crtc_state->wm.g4x.raw[level];
1356         wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1357         wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1358         wm_state->sr.fbc = raw->fbc;
1359
1360         wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1361
1362         level = G4X_WM_LEVEL_HPLL;
1363
1364         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1365                 goto out;
1366
1367         raw = &crtc_state->wm.g4x.raw[level];
1368         wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1369         wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1370         wm_state->hpll.fbc = raw->fbc;
1371
1372         wm_state->hpll_en = wm_state->cxsr;
1373
1374         level++;
1375
1376  out:
1377         if (level == G4X_WM_LEVEL_NORMAL)
1378                 return -EINVAL;
1379
1380         /* invalidate the higher levels */
1381         g4x_invalidate_wms(crtc, wm_state, level);
1382
1383         /*
1384          * Determine if the FBC watermark(s) can be used. IF
1385          * this isn't the case we prefer to disable the FBC
1386          ( watermark(s) rather than disable the SR/HPLL
1387          * level(s) entirely.
1388          */
1389         wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1390
1391         if (level >= G4X_WM_LEVEL_SR &&
1392             wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1393                 wm_state->fbc_en = false;
1394         else if (level >= G4X_WM_LEVEL_HPLL &&
1395                  wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1396                 wm_state->fbc_en = false;
1397
1398         return 0;
1399 }
1400
1401 static int g4x_compute_intermediate_wm(struct drm_device *dev,
1402                                        struct intel_crtc *crtc,
1403                                        struct intel_crtc_state *new_crtc_state)
1404 {
1405         struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1406         const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1407         struct intel_atomic_state *intel_state =
1408                 to_intel_atomic_state(new_crtc_state->base.state);
1409         const struct intel_crtc_state *old_crtc_state =
1410                 intel_atomic_get_old_crtc_state(intel_state, crtc);
1411         const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1412         enum plane_id plane_id;
1413
1414         if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
1415                 *intermediate = *optimal;
1416
1417                 intermediate->cxsr = false;
1418                 intermediate->hpll_en = false;
1419                 goto out;
1420         }
1421
1422         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1423                 !new_crtc_state->disable_cxsr;
1424         intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1425                 !new_crtc_state->disable_cxsr;
1426         intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1427
1428         for_each_plane_id_on_crtc(crtc, plane_id) {
1429                 intermediate->wm.plane[plane_id] =
1430                         max(optimal->wm.plane[plane_id],
1431                             active->wm.plane[plane_id]);
1432
1433                 WARN_ON(intermediate->wm.plane[plane_id] >
1434                         g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1435         }
1436
1437         intermediate->sr.plane = max(optimal->sr.plane,
1438                                      active->sr.plane);
1439         intermediate->sr.cursor = max(optimal->sr.cursor,
1440                                       active->sr.cursor);
1441         intermediate->sr.fbc = max(optimal->sr.fbc,
1442                                    active->sr.fbc);
1443
1444         intermediate->hpll.plane = max(optimal->hpll.plane,
1445                                        active->hpll.plane);
1446         intermediate->hpll.cursor = max(optimal->hpll.cursor,
1447                                         active->hpll.cursor);
1448         intermediate->hpll.fbc = max(optimal->hpll.fbc,
1449                                      active->hpll.fbc);
1450
1451         WARN_ON((intermediate->sr.plane >
1452                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1453                  intermediate->sr.cursor >
1454                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1455                 intermediate->cxsr);
1456         WARN_ON((intermediate->sr.plane >
1457                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1458                  intermediate->sr.cursor >
1459                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1460                 intermediate->hpll_en);
1461
1462         WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1463                 intermediate->fbc_en && intermediate->cxsr);
1464         WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1465                 intermediate->fbc_en && intermediate->hpll_en);
1466
1467 out:
1468         /*
1469          * If our intermediate WM are identical to the final WM, then we can
1470          * omit the post-vblank programming; only update if it's different.
1471          */
1472         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1473                 new_crtc_state->wm.need_postvbl_update = true;
1474
1475         return 0;
1476 }
1477
1478 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1479                          struct g4x_wm_values *wm)
1480 {
1481         struct intel_crtc *crtc;
1482         int num_active_crtcs = 0;
1483
1484         wm->cxsr = true;
1485         wm->hpll_en = true;
1486         wm->fbc_en = true;
1487
1488         for_each_intel_crtc(&dev_priv->drm, crtc) {
1489                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1490
1491                 if (!crtc->active)
1492                         continue;
1493
1494                 if (!wm_state->cxsr)
1495                         wm->cxsr = false;
1496                 if (!wm_state->hpll_en)
1497                         wm->hpll_en = false;
1498                 if (!wm_state->fbc_en)
1499                         wm->fbc_en = false;
1500
1501                 num_active_crtcs++;
1502         }
1503
1504         if (num_active_crtcs != 1) {
1505                 wm->cxsr = false;
1506                 wm->hpll_en = false;
1507                 wm->fbc_en = false;
1508         }
1509
1510         for_each_intel_crtc(&dev_priv->drm, crtc) {
1511                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1512                 enum pipe pipe = crtc->pipe;
1513
1514                 wm->pipe[pipe] = wm_state->wm;
1515                 if (crtc->active && wm->cxsr)
1516                         wm->sr = wm_state->sr;
1517                 if (crtc->active && wm->hpll_en)
1518                         wm->hpll = wm_state->hpll;
1519         }
1520 }
1521
1522 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1523 {
1524         struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1525         struct g4x_wm_values new_wm = {};
1526
1527         g4x_merge_wm(dev_priv, &new_wm);
1528
1529         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1530                 return;
1531
1532         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1533                 _intel_set_memory_cxsr(dev_priv, false);
1534
1535         g4x_write_wm_values(dev_priv, &new_wm);
1536
1537         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1538                 _intel_set_memory_cxsr(dev_priv, true);
1539
1540         *old_wm = new_wm;
1541 }
1542
1543 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1544                                    struct intel_crtc_state *crtc_state)
1545 {
1546         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1547         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1548
1549         mutex_lock(&dev_priv->wm.wm_mutex);
1550         crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1551         g4x_program_watermarks(dev_priv);
1552         mutex_unlock(&dev_priv->wm.wm_mutex);
1553 }
1554
1555 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1556                                     struct intel_crtc_state *crtc_state)
1557 {
1558         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1560
1561         if (!crtc_state->wm.need_postvbl_update)
1562                 return;
1563
1564         mutex_lock(&dev_priv->wm.wm_mutex);
1565         intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1566         g4x_program_watermarks(dev_priv);
1567         mutex_unlock(&dev_priv->wm.wm_mutex);
1568 }
1569
1570 /* latency must be in 0.1us units. */
1571 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1572                                    unsigned int htotal,
1573                                    unsigned int width,
1574                                    unsigned int cpp,
1575                                    unsigned int latency)
1576 {
1577         unsigned int ret;
1578
1579         ret = intel_wm_method2(pixel_rate, htotal,
1580                                width, cpp, latency);
1581         ret = DIV_ROUND_UP(ret, 64);
1582
1583         return ret;
1584 }
1585
1586 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1587 {
1588         /* all latencies in usec */
1589         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1590
1591         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1592
1593         if (IS_CHERRYVIEW(dev_priv)) {
1594                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1595                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1596
1597                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1598         }
1599 }
1600
1601 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1602                                      const struct intel_plane_state *plane_state,
1603                                      int level)
1604 {
1605         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1606         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1607         const struct drm_display_mode *adjusted_mode =
1608                 &crtc_state->base.adjusted_mode;
1609         unsigned int clock, htotal, cpp, width, wm;
1610
1611         if (dev_priv->wm.pri_latency[level] == 0)
1612                 return USHRT_MAX;
1613
1614         if (!intel_wm_plane_visible(crtc_state, plane_state))
1615                 return 0;
1616
1617         cpp = plane_state->base.fb->format->cpp[0];
1618         clock = adjusted_mode->crtc_clock;
1619         htotal = adjusted_mode->crtc_htotal;
1620         width = crtc_state->pipe_src_w;
1621
1622         if (plane->id == PLANE_CURSOR) {
1623                 /*
1624                  * FIXME the formula gives values that are
1625                  * too big for the cursor FIFO, and hence we
1626                  * would never be able to use cursors. For
1627                  * now just hardcode the watermark.
1628                  */
1629                 wm = 63;
1630         } else {
1631                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1632                                     dev_priv->wm.pri_latency[level] * 10);
1633         }
1634
1635         return min_t(unsigned int, wm, USHRT_MAX);
1636 }
1637
1638 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1639 {
1640         return (active_planes & (BIT(PLANE_SPRITE0) |
1641                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1642 }
1643
1644 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1645 {
1646         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1647         const struct g4x_pipe_wm *raw =
1648                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1649         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1650         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1651         int num_active_planes = hweight32(active_planes);
1652         const int fifo_size = 511;
1653         int fifo_extra, fifo_left = fifo_size;
1654         int sprite0_fifo_extra = 0;
1655         unsigned int total_rate;
1656         enum plane_id plane_id;
1657
1658         /*
1659          * When enabling sprite0 after sprite1 has already been enabled
1660          * we tend to get an underrun unless sprite0 already has some
1661          * FIFO space allcoated. Hence we always allocate at least one
1662          * cacheline for sprite0 whenever sprite1 is enabled.
1663          *
1664          * All other plane enable sequences appear immune to this problem.
1665          */
1666         if (vlv_need_sprite0_fifo_workaround(active_planes))
1667                 sprite0_fifo_extra = 1;
1668
1669         total_rate = raw->plane[PLANE_PRIMARY] +
1670                 raw->plane[PLANE_SPRITE0] +
1671                 raw->plane[PLANE_SPRITE1] +
1672                 sprite0_fifo_extra;
1673
1674         if (total_rate > fifo_size)
1675                 return -EINVAL;
1676
1677         if (total_rate == 0)
1678                 total_rate = 1;
1679
1680         for_each_plane_id_on_crtc(crtc, plane_id) {
1681                 unsigned int rate;
1682
1683                 if ((active_planes & BIT(plane_id)) == 0) {
1684                         fifo_state->plane[plane_id] = 0;
1685                         continue;
1686                 }
1687
1688                 rate = raw->plane[plane_id];
1689                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1690                 fifo_left -= fifo_state->plane[plane_id];
1691         }
1692
1693         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1694         fifo_left -= sprite0_fifo_extra;
1695
1696         fifo_state->plane[PLANE_CURSOR] = 63;
1697
1698         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1699
1700         /* spread the remainder evenly */
1701         for_each_plane_id_on_crtc(crtc, plane_id) {
1702                 int plane_extra;
1703
1704                 if (fifo_left == 0)
1705                         break;
1706
1707                 if ((active_planes & BIT(plane_id)) == 0)
1708                         continue;
1709
1710                 plane_extra = min(fifo_extra, fifo_left);
1711                 fifo_state->plane[plane_id] += plane_extra;
1712                 fifo_left -= plane_extra;
1713         }
1714
1715         WARN_ON(active_planes != 0 && fifo_left != 0);
1716
1717         /* give it all to the first plane if none are active */
1718         if (active_planes == 0) {
1719                 WARN_ON(fifo_left != fifo_size);
1720                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1721         }
1722
1723         return 0;
1724 }
1725
1726 /* mark all levels starting from 'level' as invalid */
1727 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1728                                struct vlv_wm_state *wm_state, int level)
1729 {
1730         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1731
1732         for (; level < intel_wm_num_levels(dev_priv); level++) {
1733                 enum plane_id plane_id;
1734
1735                 for_each_plane_id_on_crtc(crtc, plane_id)
1736                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1737
1738                 wm_state->sr[level].cursor = USHRT_MAX;
1739                 wm_state->sr[level].plane = USHRT_MAX;
1740         }
1741 }
1742
1743 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1744 {
1745         if (wm > fifo_size)
1746                 return USHRT_MAX;
1747         else
1748                 return fifo_size - wm;
1749 }
1750
1751 /*
1752  * Starting from 'level' set all higher
1753  * levels to 'value' in the "raw" watermarks.
1754  */
1755 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1756                                  int level, enum plane_id plane_id, u16 value)
1757 {
1758         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1759         int num_levels = intel_wm_num_levels(dev_priv);
1760         bool dirty = false;
1761
1762         for (; level < num_levels; level++) {
1763                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1764
1765                 dirty |= raw->plane[plane_id] != value;
1766                 raw->plane[plane_id] = value;
1767         }
1768
1769         return dirty;
1770 }
1771
1772 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1773                                      const struct intel_plane_state *plane_state)
1774 {
1775         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1776         enum plane_id plane_id = plane->id;
1777         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1778         int level;
1779         bool dirty = false;
1780
1781         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1782                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1783                 goto out;
1784         }
1785
1786         for (level = 0; level < num_levels; level++) {
1787                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1788                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1789                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1790
1791                 if (wm > max_wm)
1792                         break;
1793
1794                 dirty |= raw->plane[plane_id] != wm;
1795                 raw->plane[plane_id] = wm;
1796         }
1797
1798         /* mark all higher levels as invalid */
1799         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1800
1801 out:
1802         if (dirty)
1803                 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1804                               plane->base.name,
1805                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1806                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1807                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1808
1809         return dirty;
1810 }
1811
1812 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1813                                       enum plane_id plane_id, int level)
1814 {
1815         const struct g4x_pipe_wm *raw =
1816                 &crtc_state->wm.vlv.raw[level];
1817         const struct vlv_fifo_state *fifo_state =
1818                 &crtc_state->wm.vlv.fifo_state;
1819
1820         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1821 }
1822
1823 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1824 {
1825         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1826                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1827                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1828                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1829 }
1830
1831 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1832 {
1833         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1834         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1835         struct intel_atomic_state *state =
1836                 to_intel_atomic_state(crtc_state->base.state);
1837         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1838         const struct vlv_fifo_state *fifo_state =
1839                 &crtc_state->wm.vlv.fifo_state;
1840         int num_active_planes = hweight32(crtc_state->active_planes &
1841                                           ~BIT(PLANE_CURSOR));
1842         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1843         const struct intel_plane_state *old_plane_state;
1844         const struct intel_plane_state *new_plane_state;
1845         struct intel_plane *plane;
1846         enum plane_id plane_id;
1847         int level, ret, i;
1848         unsigned int dirty = 0;
1849
1850         for_each_oldnew_intel_plane_in_state(state, plane,
1851                                              old_plane_state,
1852                                              new_plane_state, i) {
1853                 if (new_plane_state->base.crtc != &crtc->base &&
1854                     old_plane_state->base.crtc != &crtc->base)
1855                         continue;
1856
1857                 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1858                         dirty |= BIT(plane->id);
1859         }
1860
1861         /*
1862          * DSPARB registers may have been reset due to the
1863          * power well being turned off. Make sure we restore
1864          * them to a consistent state even if no primary/sprite
1865          * planes are initially active.
1866          */
1867         if (needs_modeset)
1868                 crtc_state->fifo_changed = true;
1869
1870         if (!dirty)
1871                 return 0;
1872
1873         /* cursor changes don't warrant a FIFO recompute */
1874         if (dirty & ~BIT(PLANE_CURSOR)) {
1875                 const struct intel_crtc_state *old_crtc_state =
1876                         intel_atomic_get_old_crtc_state(state, crtc);
1877                 const struct vlv_fifo_state *old_fifo_state =
1878                         &old_crtc_state->wm.vlv.fifo_state;
1879
1880                 ret = vlv_compute_fifo(crtc_state);
1881                 if (ret)
1882                         return ret;
1883
1884                 if (needs_modeset ||
1885                     memcmp(old_fifo_state, fifo_state,
1886                            sizeof(*fifo_state)) != 0)
1887                         crtc_state->fifo_changed = true;
1888         }
1889
1890         /* initially allow all levels */
1891         wm_state->num_levels = intel_wm_num_levels(dev_priv);
1892         /*
1893          * Note that enabling cxsr with no primary/sprite planes
1894          * enabled can wedge the pipe. Hence we only allow cxsr
1895          * with exactly one enabled primary/sprite plane.
1896          */
1897         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1898
1899         for (level = 0; level < wm_state->num_levels; level++) {
1900                 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1901                 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1902
1903                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1904                         break;
1905
1906                 for_each_plane_id_on_crtc(crtc, plane_id) {
1907                         wm_state->wm[level].plane[plane_id] =
1908                                 vlv_invert_wm_value(raw->plane[plane_id],
1909                                                     fifo_state->plane[plane_id]);
1910                 }
1911
1912                 wm_state->sr[level].plane =
1913                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1914                                                  raw->plane[PLANE_SPRITE0],
1915                                                  raw->plane[PLANE_SPRITE1]),
1916                                             sr_fifo_size);
1917
1918                 wm_state->sr[level].cursor =
1919                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1920                                             63);
1921         }
1922
1923         if (level == 0)
1924                 return -EINVAL;
1925
1926         /* limit to only levels we can actually handle */
1927         wm_state->num_levels = level;
1928
1929         /* invalidate the higher levels */
1930         vlv_invalidate_wms(crtc, wm_state, level);
1931
1932         return 0;
1933 }
1934
1935 #define VLV_FIFO(plane, value) \
1936         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1937
1938 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1939                                    struct intel_crtc_state *crtc_state)
1940 {
1941         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1942         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1943         const struct vlv_fifo_state *fifo_state =
1944                 &crtc_state->wm.vlv.fifo_state;
1945         int sprite0_start, sprite1_start, fifo_size;
1946
1947         if (!crtc_state->fifo_changed)
1948                 return;
1949
1950         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1951         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1952         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1953
1954         WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1955         WARN_ON(fifo_size != 511);
1956
1957         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1958
1959         /*
1960          * uncore.lock serves a double purpose here. It allows us to
1961          * use the less expensive I915_{READ,WRITE}_FW() functions, and
1962          * it protects the DSPARB registers from getting clobbered by
1963          * parallel updates from multiple pipes.
1964          *
1965          * intel_pipe_update_start() has already disabled interrupts
1966          * for us, so a plain spin_lock() is sufficient here.
1967          */
1968         spin_lock(&dev_priv->uncore.lock);
1969
1970         switch (crtc->pipe) {
1971                 uint32_t dsparb, dsparb2, dsparb3;
1972         case PIPE_A:
1973                 dsparb = I915_READ_FW(DSPARB);
1974                 dsparb2 = I915_READ_FW(DSPARB2);
1975
1976                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1977                             VLV_FIFO(SPRITEB, 0xff));
1978                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1979                            VLV_FIFO(SPRITEB, sprite1_start));
1980
1981                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1982                              VLV_FIFO(SPRITEB_HI, 0x1));
1983                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1984                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1985
1986                 I915_WRITE_FW(DSPARB, dsparb);
1987                 I915_WRITE_FW(DSPARB2, dsparb2);
1988                 break;
1989         case PIPE_B:
1990                 dsparb = I915_READ_FW(DSPARB);
1991                 dsparb2 = I915_READ_FW(DSPARB2);
1992
1993                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1994                             VLV_FIFO(SPRITED, 0xff));
1995                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1996                            VLV_FIFO(SPRITED, sprite1_start));
1997
1998                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1999                              VLV_FIFO(SPRITED_HI, 0xff));
2000                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
2001                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
2002
2003                 I915_WRITE_FW(DSPARB, dsparb);
2004                 I915_WRITE_FW(DSPARB2, dsparb2);
2005                 break;
2006         case PIPE_C:
2007                 dsparb3 = I915_READ_FW(DSPARB3);
2008                 dsparb2 = I915_READ_FW(DSPARB2);
2009
2010                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2011                              VLV_FIFO(SPRITEF, 0xff));
2012                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2013                             VLV_FIFO(SPRITEF, sprite1_start));
2014
2015                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2016                              VLV_FIFO(SPRITEF_HI, 0xff));
2017                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2018                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2019
2020                 I915_WRITE_FW(DSPARB3, dsparb3);
2021                 I915_WRITE_FW(DSPARB2, dsparb2);
2022                 break;
2023         default:
2024                 break;
2025         }
2026
2027         POSTING_READ_FW(DSPARB);
2028
2029         spin_unlock(&dev_priv->uncore.lock);
2030 }
2031
2032 #undef VLV_FIFO
2033
2034 static int vlv_compute_intermediate_wm(struct drm_device *dev,
2035                                        struct intel_crtc *crtc,
2036                                        struct intel_crtc_state *new_crtc_state)
2037 {
2038         struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2039         const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2040         struct intel_atomic_state *intel_state =
2041                 to_intel_atomic_state(new_crtc_state->base.state);
2042         const struct intel_crtc_state *old_crtc_state =
2043                 intel_atomic_get_old_crtc_state(intel_state, crtc);
2044         const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
2045         int level;
2046
2047         if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
2048                 *intermediate = *optimal;
2049
2050                 intermediate->cxsr = false;
2051                 goto out;
2052         }
2053
2054         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2055         intermediate->cxsr = optimal->cxsr && active->cxsr &&
2056                 !new_crtc_state->disable_cxsr;
2057
2058         for (level = 0; level < intermediate->num_levels; level++) {
2059                 enum plane_id plane_id;
2060
2061                 for_each_plane_id_on_crtc(crtc, plane_id) {
2062                         intermediate->wm[level].plane[plane_id] =
2063                                 min(optimal->wm[level].plane[plane_id],
2064                                     active->wm[level].plane[plane_id]);
2065                 }
2066
2067                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2068                                                     active->sr[level].plane);
2069                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2070                                                      active->sr[level].cursor);
2071         }
2072
2073         vlv_invalidate_wms(crtc, intermediate, level);
2074
2075 out:
2076         /*
2077          * If our intermediate WM are identical to the final WM, then we can
2078          * omit the post-vblank programming; only update if it's different.
2079          */
2080         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2081                 new_crtc_state->wm.need_postvbl_update = true;
2082
2083         return 0;
2084 }
2085
2086 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2087                          struct vlv_wm_values *wm)
2088 {
2089         struct intel_crtc *crtc;
2090         int num_active_crtcs = 0;
2091
2092         wm->level = dev_priv->wm.max_level;
2093         wm->cxsr = true;
2094
2095         for_each_intel_crtc(&dev_priv->drm, crtc) {
2096                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2097
2098                 if (!crtc->active)
2099                         continue;
2100
2101                 if (!wm_state->cxsr)
2102                         wm->cxsr = false;
2103
2104                 num_active_crtcs++;
2105                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2106         }
2107
2108         if (num_active_crtcs != 1)
2109                 wm->cxsr = false;
2110
2111         if (num_active_crtcs > 1)
2112                 wm->level = VLV_WM_LEVEL_PM2;
2113
2114         for_each_intel_crtc(&dev_priv->drm, crtc) {
2115                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2116                 enum pipe pipe = crtc->pipe;
2117
2118                 wm->pipe[pipe] = wm_state->wm[wm->level];
2119                 if (crtc->active && wm->cxsr)
2120                         wm->sr = wm_state->sr[wm->level];
2121
2122                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2123                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2124                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2125                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2126         }
2127 }
2128
2129 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2130 {
2131         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2132         struct vlv_wm_values new_wm = {};
2133
2134         vlv_merge_wm(dev_priv, &new_wm);
2135
2136         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2137                 return;
2138
2139         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2140                 chv_set_memory_dvfs(dev_priv, false);
2141
2142         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2143                 chv_set_memory_pm5(dev_priv, false);
2144
2145         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2146                 _intel_set_memory_cxsr(dev_priv, false);
2147
2148         vlv_write_wm_values(dev_priv, &new_wm);
2149
2150         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2151                 _intel_set_memory_cxsr(dev_priv, true);
2152
2153         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2154                 chv_set_memory_pm5(dev_priv, true);
2155
2156         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2157                 chv_set_memory_dvfs(dev_priv, true);
2158
2159         *old_wm = new_wm;
2160 }
2161
2162 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2163                                    struct intel_crtc_state *crtc_state)
2164 {
2165         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2166         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2167
2168         mutex_lock(&dev_priv->wm.wm_mutex);
2169         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2170         vlv_program_watermarks(dev_priv);
2171         mutex_unlock(&dev_priv->wm.wm_mutex);
2172 }
2173
2174 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2175                                     struct intel_crtc_state *crtc_state)
2176 {
2177         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2179
2180         if (!crtc_state->wm.need_postvbl_update)
2181                 return;
2182
2183         mutex_lock(&dev_priv->wm.wm_mutex);
2184         intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2185         vlv_program_watermarks(dev_priv);
2186         mutex_unlock(&dev_priv->wm.wm_mutex);
2187 }
2188
2189 static void i965_update_wm(struct intel_crtc *unused_crtc)
2190 {
2191         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2192         struct intel_crtc *crtc;
2193         int srwm = 1;
2194         int cursor_sr = 16;
2195         bool cxsr_enabled;
2196
2197         /* Calc sr entries for one plane configs */
2198         crtc = single_enabled_crtc(dev_priv);
2199         if (crtc) {
2200                 /* self-refresh has much higher latency */
2201                 static const int sr_latency_ns = 12000;
2202                 const struct drm_display_mode *adjusted_mode =
2203                         &crtc->config->base.adjusted_mode;
2204                 const struct drm_framebuffer *fb =
2205                         crtc->base.primary->state->fb;
2206                 int clock = adjusted_mode->crtc_clock;
2207                 int htotal = adjusted_mode->crtc_htotal;
2208                 int hdisplay = crtc->config->pipe_src_w;
2209                 int cpp = fb->format->cpp[0];
2210                 int entries;
2211
2212                 entries = intel_wm_method2(clock, htotal,
2213                                            hdisplay, cpp, sr_latency_ns / 100);
2214                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2215                 srwm = I965_FIFO_SIZE - entries;
2216                 if (srwm < 0)
2217                         srwm = 1;
2218                 srwm &= 0x1ff;
2219                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2220                               entries, srwm);
2221
2222                 entries = intel_wm_method2(clock, htotal,
2223                                            crtc->base.cursor->state->crtc_w, 4,
2224                                            sr_latency_ns / 100);
2225                 entries = DIV_ROUND_UP(entries,
2226                                        i965_cursor_wm_info.cacheline_size) +
2227                         i965_cursor_wm_info.guard_size;
2228
2229                 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2230                 if (cursor_sr > i965_cursor_wm_info.max_wm)
2231                         cursor_sr = i965_cursor_wm_info.max_wm;
2232
2233                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2234                               "cursor %d\n", srwm, cursor_sr);
2235
2236                 cxsr_enabled = true;
2237         } else {
2238                 cxsr_enabled = false;
2239                 /* Turn off self refresh if both pipes are enabled */
2240                 intel_set_memory_cxsr(dev_priv, false);
2241         }
2242
2243         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2244                       srwm);
2245
2246         /* 965 has limitations... */
2247         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2248                    FW_WM(8, CURSORB) |
2249                    FW_WM(8, PLANEB) |
2250                    FW_WM(8, PLANEA));
2251         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2252                    FW_WM(8, PLANEC_OLD));
2253         /* update cursor SR watermark */
2254         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2255
2256         if (cxsr_enabled)
2257                 intel_set_memory_cxsr(dev_priv, true);
2258 }
2259
2260 #undef FW_WM
2261
2262 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2263 {
2264         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2265         const struct intel_watermark_params *wm_info;
2266         uint32_t fwater_lo;
2267         uint32_t fwater_hi;
2268         int cwm, srwm = 1;
2269         int fifo_size;
2270         int planea_wm, planeb_wm;
2271         struct intel_crtc *crtc, *enabled = NULL;
2272
2273         if (IS_I945GM(dev_priv))
2274                 wm_info = &i945_wm_info;
2275         else if (!IS_GEN2(dev_priv))
2276                 wm_info = &i915_wm_info;
2277         else
2278                 wm_info = &i830_a_wm_info;
2279
2280         fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
2281         crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
2282         if (intel_crtc_active(crtc)) {
2283                 const struct drm_display_mode *adjusted_mode =
2284                         &crtc->config->base.adjusted_mode;
2285                 const struct drm_framebuffer *fb =
2286                         crtc->base.primary->state->fb;
2287                 int cpp;
2288
2289                 if (IS_GEN2(dev_priv))
2290                         cpp = 4;
2291                 else
2292                         cpp = fb->format->cpp[0];
2293
2294                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2295                                                wm_info, fifo_size, cpp,
2296                                                pessimal_latency_ns);
2297                 enabled = crtc;
2298         } else {
2299                 planea_wm = fifo_size - wm_info->guard_size;
2300                 if (planea_wm > (long)wm_info->max_wm)
2301                         planea_wm = wm_info->max_wm;
2302         }
2303
2304         if (IS_GEN2(dev_priv))
2305                 wm_info = &i830_bc_wm_info;
2306
2307         fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
2308         crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
2309         if (intel_crtc_active(crtc)) {
2310                 const struct drm_display_mode *adjusted_mode =
2311                         &crtc->config->base.adjusted_mode;
2312                 const struct drm_framebuffer *fb =
2313                         crtc->base.primary->state->fb;
2314                 int cpp;
2315
2316                 if (IS_GEN2(dev_priv))
2317                         cpp = 4;
2318                 else
2319                         cpp = fb->format->cpp[0];
2320
2321                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2322                                                wm_info, fifo_size, cpp,
2323                                                pessimal_latency_ns);
2324                 if (enabled == NULL)
2325                         enabled = crtc;
2326                 else
2327                         enabled = NULL;
2328         } else {
2329                 planeb_wm = fifo_size - wm_info->guard_size;
2330                 if (planeb_wm > (long)wm_info->max_wm)
2331                         planeb_wm = wm_info->max_wm;
2332         }
2333
2334         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2335
2336         if (IS_I915GM(dev_priv) && enabled) {
2337                 struct drm_i915_gem_object *obj;
2338
2339                 obj = intel_fb_obj(enabled->base.primary->state->fb);
2340
2341                 /* self-refresh seems busted with untiled */
2342                 if (!i915_gem_object_is_tiled(obj))
2343                         enabled = NULL;
2344         }
2345
2346         /*
2347          * Overlay gets an aggressive default since video jitter is bad.
2348          */
2349         cwm = 2;
2350
2351         /* Play safe and disable self-refresh before adjusting watermarks. */
2352         intel_set_memory_cxsr(dev_priv, false);
2353
2354         /* Calc sr entries for one plane configs */
2355         if (HAS_FW_BLC(dev_priv) && enabled) {
2356                 /* self-refresh has much higher latency */
2357                 static const int sr_latency_ns = 6000;
2358                 const struct drm_display_mode *adjusted_mode =
2359                         &enabled->config->base.adjusted_mode;
2360                 const struct drm_framebuffer *fb =
2361                         enabled->base.primary->state->fb;
2362                 int clock = adjusted_mode->crtc_clock;
2363                 int htotal = adjusted_mode->crtc_htotal;
2364                 int hdisplay = enabled->config->pipe_src_w;
2365                 int cpp;
2366                 int entries;
2367
2368                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2369                         cpp = 4;
2370                 else
2371                         cpp = fb->format->cpp[0];
2372
2373                 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2374                                            sr_latency_ns / 100);
2375                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2376                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
2377                 srwm = wm_info->fifo_size - entries;
2378                 if (srwm < 0)
2379                         srwm = 1;
2380
2381                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2382                         I915_WRITE(FW_BLC_SELF,
2383                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2384                 else
2385                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2386         }
2387
2388         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2389                       planea_wm, planeb_wm, cwm, srwm);
2390
2391         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2392         fwater_hi = (cwm & 0x1f);
2393
2394         /* Set request length to 8 cachelines per fetch */
2395         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2396         fwater_hi = fwater_hi | (1 << 8);
2397
2398         I915_WRITE(FW_BLC, fwater_lo);
2399         I915_WRITE(FW_BLC2, fwater_hi);
2400
2401         if (enabled)
2402                 intel_set_memory_cxsr(dev_priv, true);
2403 }
2404
2405 static void i845_update_wm(struct intel_crtc *unused_crtc)
2406 {
2407         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2408         struct intel_crtc *crtc;
2409         const struct drm_display_mode *adjusted_mode;
2410         uint32_t fwater_lo;
2411         int planea_wm;
2412
2413         crtc = single_enabled_crtc(dev_priv);
2414         if (crtc == NULL)
2415                 return;
2416
2417         adjusted_mode = &crtc->config->base.adjusted_mode;
2418         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2419                                        &i845_wm_info,
2420                                        dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
2421                                        4, pessimal_latency_ns);
2422         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2423         fwater_lo |= (3<<8) | planea_wm;
2424
2425         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2426
2427         I915_WRITE(FW_BLC, fwater_lo);
2428 }
2429
2430 /* latency must be in 0.1us units. */
2431 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2432                                    unsigned int cpp,
2433                                    unsigned int latency)
2434 {
2435         unsigned int ret;
2436
2437         ret = intel_wm_method1(pixel_rate, cpp, latency);
2438         ret = DIV_ROUND_UP(ret, 64) + 2;
2439
2440         return ret;
2441 }
2442
2443 /* latency must be in 0.1us units. */
2444 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2445                                    unsigned int htotal,
2446                                    unsigned int width,
2447                                    unsigned int cpp,
2448                                    unsigned int latency)
2449 {
2450         unsigned int ret;
2451
2452         ret = intel_wm_method2(pixel_rate, htotal,
2453                                width, cpp, latency);
2454         ret = DIV_ROUND_UP(ret, 64) + 2;
2455
2456         return ret;
2457 }
2458
2459 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2460                            uint8_t cpp)
2461 {
2462         /*
2463          * Neither of these should be possible since this function shouldn't be
2464          * called if the CRTC is off or the plane is invisible.  But let's be
2465          * extra paranoid to avoid a potential divide-by-zero if we screw up
2466          * elsewhere in the driver.
2467          */
2468         if (WARN_ON(!cpp))
2469                 return 0;
2470         if (WARN_ON(!horiz_pixels))
2471                 return 0;
2472
2473         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2474 }
2475
2476 struct ilk_wm_maximums {
2477         uint16_t pri;
2478         uint16_t spr;
2479         uint16_t cur;
2480         uint16_t fbc;
2481 };
2482
2483 /*
2484  * For both WM_PIPE and WM_LP.
2485  * mem_value must be in 0.1us units.
2486  */
2487 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
2488                                    const struct intel_plane_state *pstate,
2489                                    uint32_t mem_value,
2490                                    bool is_lp)
2491 {
2492         uint32_t method1, method2;
2493         int cpp;
2494
2495         if (!intel_wm_plane_visible(cstate, pstate))
2496                 return 0;
2497
2498         cpp = pstate->base.fb->format->cpp[0];
2499
2500         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2501
2502         if (!is_lp)
2503                 return method1;
2504
2505         method2 = ilk_wm_method2(cstate->pixel_rate,
2506                                  cstate->base.adjusted_mode.crtc_htotal,
2507                                  drm_rect_width(&pstate->base.dst),
2508                                  cpp, mem_value);
2509
2510         return min(method1, method2);
2511 }
2512
2513 /*
2514  * For both WM_PIPE and WM_LP.
2515  * mem_value must be in 0.1us units.
2516  */
2517 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
2518                                    const struct intel_plane_state *pstate,
2519                                    uint32_t mem_value)
2520 {
2521         uint32_t method1, method2;
2522         int cpp;
2523
2524         if (!intel_wm_plane_visible(cstate, pstate))
2525                 return 0;
2526
2527         cpp = pstate->base.fb->format->cpp[0];
2528
2529         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2530         method2 = ilk_wm_method2(cstate->pixel_rate,
2531                                  cstate->base.adjusted_mode.crtc_htotal,
2532                                  drm_rect_width(&pstate->base.dst),
2533                                  cpp, mem_value);
2534         return min(method1, method2);
2535 }
2536
2537 /*
2538  * For both WM_PIPE and WM_LP.
2539  * mem_value must be in 0.1us units.
2540  */
2541 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
2542                                    const struct intel_plane_state *pstate,
2543                                    uint32_t mem_value)
2544 {
2545         int cpp;
2546
2547         if (!intel_wm_plane_visible(cstate, pstate))
2548                 return 0;
2549
2550         cpp = pstate->base.fb->format->cpp[0];
2551
2552         return ilk_wm_method2(cstate->pixel_rate,
2553                               cstate->base.adjusted_mode.crtc_htotal,
2554                               pstate->base.crtc_w, cpp, mem_value);
2555 }
2556
2557 /* Only for WM_LP. */
2558 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
2559                                    const struct intel_plane_state *pstate,
2560                                    uint32_t pri_val)
2561 {
2562         int cpp;
2563
2564         if (!intel_wm_plane_visible(cstate, pstate))
2565                 return 0;
2566
2567         cpp = pstate->base.fb->format->cpp[0];
2568
2569         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
2570 }
2571
2572 static unsigned int
2573 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2574 {
2575         if (INTEL_GEN(dev_priv) >= 8)
2576                 return 3072;
2577         else if (INTEL_GEN(dev_priv) >= 7)
2578                 return 768;
2579         else
2580                 return 512;
2581 }
2582
2583 static unsigned int
2584 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2585                      int level, bool is_sprite)
2586 {
2587         if (INTEL_GEN(dev_priv) >= 8)
2588                 /* BDW primary/sprite plane watermarks */
2589                 return level == 0 ? 255 : 2047;
2590         else if (INTEL_GEN(dev_priv) >= 7)
2591                 /* IVB/HSW primary/sprite plane watermarks */
2592                 return level == 0 ? 127 : 1023;
2593         else if (!is_sprite)
2594                 /* ILK/SNB primary plane watermarks */
2595                 return level == 0 ? 127 : 511;
2596         else
2597                 /* ILK/SNB sprite plane watermarks */
2598                 return level == 0 ? 63 : 255;
2599 }
2600
2601 static unsigned int
2602 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2603 {
2604         if (INTEL_GEN(dev_priv) >= 7)
2605                 return level == 0 ? 63 : 255;
2606         else
2607                 return level == 0 ? 31 : 63;
2608 }
2609
2610 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2611 {
2612         if (INTEL_GEN(dev_priv) >= 8)
2613                 return 31;
2614         else
2615                 return 15;
2616 }
2617
2618 /* Calculate the maximum primary/sprite plane watermark */
2619 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2620                                      int level,
2621                                      const struct intel_wm_config *config,
2622                                      enum intel_ddb_partitioning ddb_partitioning,
2623                                      bool is_sprite)
2624 {
2625         struct drm_i915_private *dev_priv = to_i915(dev);
2626         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2627
2628         /* if sprites aren't enabled, sprites get nothing */
2629         if (is_sprite && !config->sprites_enabled)
2630                 return 0;
2631
2632         /* HSW allows LP1+ watermarks even with multiple pipes */
2633         if (level == 0 || config->num_pipes_active > 1) {
2634                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2635
2636                 /*
2637                  * For some reason the non self refresh
2638                  * FIFO size is only half of the self
2639                  * refresh FIFO size on ILK/SNB.
2640                  */
2641                 if (INTEL_GEN(dev_priv) <= 6)
2642                         fifo_size /= 2;
2643         }
2644
2645         if (config->sprites_enabled) {
2646                 /* level 0 is always calculated with 1:1 split */
2647                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2648                         if (is_sprite)
2649                                 fifo_size *= 5;
2650                         fifo_size /= 6;
2651                 } else {
2652                         fifo_size /= 2;
2653                 }
2654         }
2655
2656         /* clamp to max that the registers can hold */
2657         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2658 }
2659
2660 /* Calculate the maximum cursor plane watermark */
2661 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2662                                       int level,
2663                                       const struct intel_wm_config *config)
2664 {
2665         /* HSW LP1+ watermarks w/ multiple pipes */
2666         if (level > 0 && config->num_pipes_active > 1)
2667                 return 64;
2668
2669         /* otherwise just report max that registers can hold */
2670         return ilk_cursor_wm_reg_max(to_i915(dev), level);
2671 }
2672
2673 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2674                                     int level,
2675                                     const struct intel_wm_config *config,
2676                                     enum intel_ddb_partitioning ddb_partitioning,
2677                                     struct ilk_wm_maximums *max)
2678 {
2679         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2680         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2681         max->cur = ilk_cursor_wm_max(dev, level, config);
2682         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
2683 }
2684
2685 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2686                                         int level,
2687                                         struct ilk_wm_maximums *max)
2688 {
2689         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2690         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2691         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2692         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2693 }
2694
2695 static bool ilk_validate_wm_level(int level,
2696                                   const struct ilk_wm_maximums *max,
2697                                   struct intel_wm_level *result)
2698 {
2699         bool ret;
2700
2701         /* already determined to be invalid? */
2702         if (!result->enable)
2703                 return false;
2704
2705         result->enable = result->pri_val <= max->pri &&
2706                          result->spr_val <= max->spr &&
2707                          result->cur_val <= max->cur;
2708
2709         ret = result->enable;
2710
2711         /*
2712          * HACK until we can pre-compute everything,
2713          * and thus fail gracefully if LP0 watermarks
2714          * are exceeded...
2715          */
2716         if (level == 0 && !result->enable) {
2717                 if (result->pri_val > max->pri)
2718                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2719                                       level, result->pri_val, max->pri);
2720                 if (result->spr_val > max->spr)
2721                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2722                                       level, result->spr_val, max->spr);
2723                 if (result->cur_val > max->cur)
2724                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2725                                       level, result->cur_val, max->cur);
2726
2727                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2728                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2729                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2730                 result->enable = true;
2731         }
2732
2733         return ret;
2734 }
2735
2736 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2737                                  const struct intel_crtc *intel_crtc,
2738                                  int level,
2739                                  struct intel_crtc_state *cstate,
2740                                  const struct intel_plane_state *pristate,
2741                                  const struct intel_plane_state *sprstate,
2742                                  const struct intel_plane_state *curstate,
2743                                  struct intel_wm_level *result)
2744 {
2745         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2746         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2747         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2748
2749         /* WM1+ latency values stored in 0.5us units */
2750         if (level > 0) {
2751                 pri_latency *= 5;
2752                 spr_latency *= 5;
2753                 cur_latency *= 5;
2754         }
2755
2756         if (pristate) {
2757                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2758                                                      pri_latency, level);
2759                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2760         }
2761
2762         if (sprstate)
2763                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2764
2765         if (curstate)
2766                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2767
2768         result->enable = true;
2769 }
2770
2771 static uint32_t
2772 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2773 {
2774         const struct intel_atomic_state *intel_state =
2775                 to_intel_atomic_state(cstate->base.state);
2776         const struct drm_display_mode *adjusted_mode =
2777                 &cstate->base.adjusted_mode;
2778         u32 linetime, ips_linetime;
2779
2780         if (!cstate->base.active)
2781                 return 0;
2782         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2783                 return 0;
2784         if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2785                 return 0;
2786
2787         /* The WM are computed with base on how long it takes to fill a single
2788          * row at the given clock rate, multiplied by 8.
2789          * */
2790         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2791                                      adjusted_mode->crtc_clock);
2792         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2793                                          intel_state->cdclk.logical.cdclk);
2794
2795         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2796                PIPE_WM_LINETIME_TIME(linetime);
2797 }
2798
2799 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2800                                   uint16_t wm[8])
2801 {
2802         if (INTEL_GEN(dev_priv) >= 9) {
2803                 uint32_t val;
2804                 int ret, i;
2805                 int level, max_level = ilk_wm_max_level(dev_priv);
2806
2807                 /* read the first set of memory latencies[0:3] */
2808                 val = 0; /* data0 to be programmed to 0 for first set */
2809                 mutex_lock(&dev_priv->pcu_lock);
2810                 ret = sandybridge_pcode_read(dev_priv,
2811                                              GEN9_PCODE_READ_MEM_LATENCY,
2812                                              &val);
2813                 mutex_unlock(&dev_priv->pcu_lock);
2814
2815                 if (ret) {
2816                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2817                         return;
2818                 }
2819
2820                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2821                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2822                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2823                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2824                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2825                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2826                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2827
2828                 /* read the second set of memory latencies[4:7] */
2829                 val = 1; /* data0 to be programmed to 1 for second set */
2830                 mutex_lock(&dev_priv->pcu_lock);
2831                 ret = sandybridge_pcode_read(dev_priv,
2832                                              GEN9_PCODE_READ_MEM_LATENCY,
2833                                              &val);
2834                 mutex_unlock(&dev_priv->pcu_lock);
2835                 if (ret) {
2836                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2837                         return;
2838                 }
2839
2840                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2841                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2842                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2843                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2844                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2845                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2846                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2847
2848                 /*
2849                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2850                  * need to be disabled. We make sure to sanitize the values out
2851                  * of the punit to satisfy this requirement.
2852                  */
2853                 for (level = 1; level <= max_level; level++) {
2854                         if (wm[level] == 0) {
2855                                 for (i = level + 1; i <= max_level; i++)
2856                                         wm[i] = 0;
2857                                 break;
2858                         }
2859                 }
2860
2861                 /*
2862                  * WaWmMemoryReadLatency:skl+,glk
2863                  *
2864                  * punit doesn't take into account the read latency so we need
2865                  * to add 2us to the various latency levels we retrieve from the
2866                  * punit when level 0 response data us 0us.
2867                  */
2868                 if (wm[0] == 0) {
2869                         wm[0] += 2;
2870                         for (level = 1; level <= max_level; level++) {
2871                                 if (wm[level] == 0)
2872                                         break;
2873                                 wm[level] += 2;
2874                         }
2875                 }
2876
2877         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2878                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2879
2880                 wm[0] = (sskpd >> 56) & 0xFF;
2881                 if (wm[0] == 0)
2882                         wm[0] = sskpd & 0xF;
2883                 wm[1] = (sskpd >> 4) & 0xFF;
2884                 wm[2] = (sskpd >> 12) & 0xFF;
2885                 wm[3] = (sskpd >> 20) & 0x1FF;
2886                 wm[4] = (sskpd >> 32) & 0x1FF;
2887         } else if (INTEL_GEN(dev_priv) >= 6) {
2888                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2889
2890                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2891                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2892                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2893                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2894         } else if (INTEL_GEN(dev_priv) >= 5) {
2895                 uint32_t mltr = I915_READ(MLTR_ILK);
2896
2897                 /* ILK primary LP0 latency is 700 ns */
2898                 wm[0] = 7;
2899                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2900                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2901         } else {
2902                 MISSING_CASE(INTEL_DEVID(dev_priv));
2903         }
2904 }
2905
2906 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2907                                        uint16_t wm[5])
2908 {
2909         /* ILK sprite LP0 latency is 1300 ns */
2910         if (IS_GEN5(dev_priv))
2911                 wm[0] = 13;
2912 }
2913
2914 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2915                                        uint16_t wm[5])
2916 {
2917         /* ILK cursor LP0 latency is 1300 ns */
2918         if (IS_GEN5(dev_priv))
2919                 wm[0] = 13;
2920 }
2921
2922 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2923 {
2924         /* how many WM levels are we expecting */
2925         if (INTEL_GEN(dev_priv) >= 9)
2926                 return 7;
2927         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2928                 return 4;
2929         else if (INTEL_GEN(dev_priv) >= 6)
2930                 return 3;
2931         else
2932                 return 2;
2933 }
2934
2935 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2936                                    const char *name,
2937                                    const uint16_t wm[8])
2938 {
2939         int level, max_level = ilk_wm_max_level(dev_priv);
2940
2941         for (level = 0; level <= max_level; level++) {
2942                 unsigned int latency = wm[level];
2943
2944                 if (latency == 0) {
2945                         DRM_ERROR("%s WM%d latency not provided\n",
2946                                   name, level);
2947                         continue;
2948                 }
2949
2950                 /*
2951                  * - latencies are in us on gen9.
2952                  * - before then, WM1+ latency values are in 0.5us units
2953                  */
2954                 if (INTEL_GEN(dev_priv) >= 9)
2955                         latency *= 10;
2956                 else if (level > 0)
2957                         latency *= 5;
2958
2959                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2960                               name, level, wm[level],
2961                               latency / 10, latency % 10);
2962         }
2963 }
2964
2965 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2966                                     uint16_t wm[5], uint16_t min)
2967 {
2968         int level, max_level = ilk_wm_max_level(dev_priv);
2969
2970         if (wm[0] >= min)
2971                 return false;
2972
2973         wm[0] = max(wm[0], min);
2974         for (level = 1; level <= max_level; level++)
2975                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2976
2977         return true;
2978 }
2979
2980 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2981 {
2982         bool changed;
2983
2984         /*
2985          * The BIOS provided WM memory latency values are often
2986          * inadequate for high resolution displays. Adjust them.
2987          */
2988         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2989                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2990                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2991
2992         if (!changed)
2993                 return;
2994
2995         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2996         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2997         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2998         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2999 }
3000
3001 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3002 {
3003         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
3004
3005         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3006                sizeof(dev_priv->wm.pri_latency));
3007         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3008                sizeof(dev_priv->wm.pri_latency));
3009
3010         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
3011         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3012
3013         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3014         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3015         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3016
3017         if (IS_GEN6(dev_priv))
3018                 snb_wm_latency_quirk(dev_priv);
3019 }
3020
3021 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3022 {
3023         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3024         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3025 }
3026
3027 static bool ilk_validate_pipe_wm(struct drm_device *dev,
3028                                  struct intel_pipe_wm *pipe_wm)
3029 {
3030         /* LP0 watermark maximums depend on this pipe alone */
3031         const struct intel_wm_config config = {
3032                 .num_pipes_active = 1,
3033                 .sprites_enabled = pipe_wm->sprites_enabled,
3034                 .sprites_scaled = pipe_wm->sprites_scaled,
3035         };
3036         struct ilk_wm_maximums max;
3037
3038         /* LP0 watermarks always use 1/2 DDB partitioning */
3039         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
3040
3041         /* At least LP0 must be valid */
3042         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3043                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3044                 return false;
3045         }
3046
3047         return true;
3048 }
3049
3050 /* Compute new watermarks for the pipe */
3051 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
3052 {
3053         struct drm_atomic_state *state = cstate->base.state;
3054         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3055         struct intel_pipe_wm *pipe_wm;
3056         struct drm_device *dev = state->dev;
3057         const struct drm_i915_private *dev_priv = to_i915(dev);
3058         struct drm_plane *plane;
3059         const struct drm_plane_state *plane_state;
3060         const struct intel_plane_state *pristate = NULL;
3061         const struct intel_plane_state *sprstate = NULL;
3062         const struct intel_plane_state *curstate = NULL;
3063         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3064         struct ilk_wm_maximums max;
3065
3066         pipe_wm = &cstate->wm.ilk.optimal;
3067
3068         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
3069                 const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
3070
3071                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3072                         pristate = ps;
3073                 else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
3074                         sprstate = ps;
3075                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
3076                         curstate = ps;
3077         }
3078
3079         pipe_wm->pipe_enabled = cstate->base.active;
3080         if (sprstate) {
3081                 pipe_wm->sprites_enabled = sprstate->base.visible;
3082                 pipe_wm->sprites_scaled = sprstate->base.visible &&
3083                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
3084                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
3085         }
3086
3087         usable_level = max_level;
3088
3089         /* ILK/SNB: LP2+ watermarks only w/o sprites */
3090         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3091                 usable_level = 1;
3092
3093         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3094         if (pipe_wm->sprites_scaled)
3095                 usable_level = 0;
3096
3097         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3098         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3099                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
3100
3101         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3102                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
3103
3104         if (!ilk_validate_pipe_wm(dev, pipe_wm))
3105                 return -EINVAL;
3106
3107         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3108
3109         for (level = 1; level <= usable_level; level++) {
3110                 struct intel_wm_level *wm = &pipe_wm->wm[level];
3111
3112                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
3113                                      pristate, sprstate, curstate, wm);
3114
3115                 /*
3116                  * Disable any watermark level that exceeds the
3117                  * register maximums since such watermarks are
3118                  * always invalid.
3119                  */
3120                 if (!ilk_validate_wm_level(level, &max, wm)) {
3121                         memset(wm, 0, sizeof(*wm));
3122                         break;
3123                 }
3124         }
3125
3126         return 0;
3127 }
3128
3129 /*
3130  * Build a set of 'intermediate' watermark values that satisfy both the old
3131  * state and the new state.  These can be programmed to the hardware
3132  * immediately.
3133  */
3134 static int ilk_compute_intermediate_wm(struct drm_device *dev,
3135                                        struct intel_crtc *intel_crtc,
3136                                        struct intel_crtc_state *newstate)
3137 {
3138         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3139         struct intel_atomic_state *intel_state =
3140                 to_intel_atomic_state(newstate->base.state);
3141         const struct intel_crtc_state *oldstate =
3142                 intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
3143         const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
3144         int level, max_level = ilk_wm_max_level(to_i915(dev));
3145
3146         /*
3147          * Start with the final, target watermarks, then combine with the
3148          * currently active watermarks to get values that are safe both before
3149          * and after the vblank.
3150          */
3151         *a = newstate->wm.ilk.optimal;
3152         if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base))
3153                 return 0;
3154
3155         a->pipe_enabled |= b->pipe_enabled;
3156         a->sprites_enabled |= b->sprites_enabled;
3157         a->sprites_scaled |= b->sprites_scaled;
3158
3159         for (level = 0; level <= max_level; level++) {
3160                 struct intel_wm_level *a_wm = &a->wm[level];
3161                 const struct intel_wm_level *b_wm = &b->wm[level];
3162
3163                 a_wm->enable &= b_wm->enable;
3164                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3165                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3166                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3167                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3168         }
3169
3170         /*
3171          * We need to make sure that these merged watermark values are
3172          * actually a valid configuration themselves.  If they're not,
3173          * there's no safe way to transition from the old state to
3174          * the new state, so we need to fail the atomic transaction.
3175          */
3176         if (!ilk_validate_pipe_wm(dev, a))
3177                 return -EINVAL;
3178
3179         /*
3180          * If our intermediate WM are identical to the final WM, then we can
3181          * omit the post-vblank programming; only update if it's different.
3182          */
3183         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3184                 newstate->wm.need_postvbl_update = true;
3185
3186         return 0;
3187 }
3188
3189 /*
3190  * Merge the watermarks from all active pipes for a specific level.
3191  */
3192 static void ilk_merge_wm_level(struct drm_device *dev,
3193                                int level,
3194                                struct intel_wm_level *ret_wm)
3195 {
3196         const struct intel_crtc *intel_crtc;
3197
3198         ret_wm->enable = true;
3199
3200         for_each_intel_crtc(dev, intel_crtc) {
3201                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3202                 const struct intel_wm_level *wm = &active->wm[level];
3203
3204                 if (!active->pipe_enabled)
3205                         continue;
3206
3207                 /*
3208                  * The watermark values may have been used in the past,
3209                  * so we must maintain them in the registers for some
3210                  * time even if the level is now disabled.
3211                  */
3212                 if (!wm->enable)
3213                         ret_wm->enable = false;
3214
3215                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3216                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3217                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3218                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3219         }
3220 }
3221
3222 /*
3223  * Merge all low power watermarks for all active pipes.
3224  */
3225 static void ilk_wm_merge(struct drm_device *dev,
3226                          const struct intel_wm_config *config,
3227                          const struct ilk_wm_maximums *max,
3228                          struct intel_pipe_wm *merged)
3229 {
3230         struct drm_i915_private *dev_priv = to_i915(dev);
3231         int level, max_level = ilk_wm_max_level(dev_priv);
3232         int last_enabled_level = max_level;
3233
3234         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3235         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3236             config->num_pipes_active > 1)
3237                 last_enabled_level = 0;
3238
3239         /* ILK: FBC WM must be disabled always */
3240         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3241
3242         /* merge each WM1+ level */
3243         for (level = 1; level <= max_level; level++) {
3244                 struct intel_wm_level *wm = &merged->wm[level];
3245
3246                 ilk_merge_wm_level(dev, level, wm);
3247
3248                 if (level > last_enabled_level)
3249                         wm->enable = false;
3250                 else if (!ilk_validate_wm_level(level, max, wm))
3251                         /* make sure all following levels get disabled */
3252                         last_enabled_level = level - 1;
3253
3254                 /*
3255                  * The spec says it is preferred to disable
3256                  * FBC WMs instead of disabling a WM level.
3257                  */
3258                 if (wm->fbc_val > max->fbc) {
3259                         if (wm->enable)
3260                                 merged->fbc_wm_enabled = false;
3261                         wm->fbc_val = 0;
3262                 }
3263         }
3264
3265         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3266         /*
3267          * FIXME this is racy. FBC might get enabled later.
3268          * What we should check here is whether FBC can be
3269          * enabled sometime later.
3270          */
3271         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
3272             intel_fbc_is_active(dev_priv)) {
3273                 for (level = 2; level <= max_level; level++) {
3274                         struct intel_wm_level *wm = &merged->wm[level];
3275
3276                         wm->enable = false;
3277                 }
3278         }
3279 }
3280
3281 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3282 {
3283         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3284         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3285 }
3286
3287 /* The value we need to program into the WM_LPx latency field */
3288 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
3289 {
3290         struct drm_i915_private *dev_priv = to_i915(dev);
3291
3292         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3293                 return 2 * level;
3294         else
3295                 return dev_priv->wm.pri_latency[level];
3296 }
3297
3298 static void ilk_compute_wm_results(struct drm_device *dev,
3299                                    const struct intel_pipe_wm *merged,
3300                                    enum intel_ddb_partitioning partitioning,
3301                                    struct ilk_wm_values *results)
3302 {
3303         struct drm_i915_private *dev_priv = to_i915(dev);
3304         struct intel_crtc *intel_crtc;
3305         int level, wm_lp;
3306
3307         results->enable_fbc_wm = merged->fbc_wm_enabled;
3308         results->partitioning = partitioning;
3309
3310         /* LP1+ register values */
3311         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3312                 const struct intel_wm_level *r;
3313
3314                 level = ilk_wm_lp_to_level(wm_lp, merged);
3315
3316                 r = &merged->wm[level];
3317
3318                 /*
3319                  * Maintain the watermark values even if the level is
3320                  * disabled. Doing otherwise could cause underruns.
3321                  */
3322                 results->wm_lp[wm_lp - 1] =
3323                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
3324                         (r->pri_val << WM1_LP_SR_SHIFT) |
3325                         r->cur_val;
3326
3327                 if (r->enable)
3328                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3329
3330                 if (INTEL_GEN(dev_priv) >= 8)
3331                         results->wm_lp[wm_lp - 1] |=
3332                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3333                 else
3334                         results->wm_lp[wm_lp - 1] |=
3335                                 r->fbc_val << WM1_LP_FBC_SHIFT;
3336
3337                 /*
3338                  * Always set WM1S_LP_EN when spr_val != 0, even if the
3339                  * level is disabled. Doing otherwise could cause underruns.
3340                  */
3341                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3342                         WARN_ON(wm_lp != 1);
3343                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3344                 } else
3345                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3346         }
3347
3348         /* LP0 register values */
3349         for_each_intel_crtc(dev, intel_crtc) {
3350                 enum pipe pipe = intel_crtc->pipe;
3351                 const struct intel_wm_level *r =
3352                         &intel_crtc->wm.active.ilk.wm[0];
3353
3354                 if (WARN_ON(!r->enable))
3355                         continue;
3356
3357                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
3358
3359                 results->wm_pipe[pipe] =
3360                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3361                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3362                         r->cur_val;
3363         }
3364 }
3365
3366 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3367  * case both are at the same level. Prefer r1 in case they're the same. */
3368 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
3369                                                   struct intel_pipe_wm *r1,
3370                                                   struct intel_pipe_wm *r2)
3371 {
3372         int level, max_level = ilk_wm_max_level(to_i915(dev));
3373         int level1 = 0, level2 = 0;
3374
3375         for (level = 1; level <= max_level; level++) {
3376                 if (r1->wm[level].enable)
3377                         level1 = level;
3378                 if (r2->wm[level].enable)
3379                         level2 = level;
3380         }
3381
3382         if (level1 == level2) {
3383                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3384                         return r2;
3385                 else
3386                         return r1;
3387         } else if (level1 > level2) {
3388                 return r1;
3389         } else {
3390                 return r2;
3391         }
3392 }
3393
3394 /* dirty bits used to track which watermarks need changes */
3395 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3396 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3397 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3398 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3399 #define WM_DIRTY_FBC (1 << 24)
3400 #define WM_DIRTY_DDB (1 << 25)
3401
3402 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3403                                          const struct ilk_wm_values *old,
3404                                          const struct ilk_wm_values *new)
3405 {
3406         unsigned int dirty = 0;
3407         enum pipe pipe;
3408         int wm_lp;
3409
3410         for_each_pipe(dev_priv, pipe) {
3411                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
3412                         dirty |= WM_DIRTY_LINETIME(pipe);
3413                         /* Must disable LP1+ watermarks too */
3414                         dirty |= WM_DIRTY_LP_ALL;
3415                 }
3416
3417                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3418                         dirty |= WM_DIRTY_PIPE(pipe);
3419                         /* Must disable LP1+ watermarks too */
3420                         dirty |= WM_DIRTY_LP_ALL;
3421                 }
3422         }
3423
3424         if (old->enable_fbc_wm != new->enable_fbc_wm) {
3425                 dirty |= WM_DIRTY_FBC;
3426                 /* Must disable LP1+ watermarks too */
3427                 dirty |= WM_DIRTY_LP_ALL;
3428         }
3429
3430         if (old->partitioning != new->partitioning) {
3431                 dirty |= WM_DIRTY_DDB;
3432                 /* Must disable LP1+ watermarks too */
3433                 dirty |= WM_DIRTY_LP_ALL;
3434         }
3435
3436         /* LP1+ watermarks already deemed dirty, no need to continue */
3437         if (dirty & WM_DIRTY_LP_ALL)
3438                 return dirty;
3439
3440         /* Find the lowest numbered LP1+ watermark in need of an update... */
3441         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3442                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3443                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3444                         break;
3445         }
3446
3447         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3448         for (; wm_lp <= 3; wm_lp++)
3449                 dirty |= WM_DIRTY_LP(wm_lp);
3450
3451         return dirty;
3452 }
3453
3454 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3455                                unsigned int dirty)
3456 {
3457         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3458         bool changed = false;
3459
3460         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3461                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3462                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3463                 changed = true;
3464         }
3465         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3466                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3467                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3468                 changed = true;
3469         }
3470         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3471                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3472                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3473                 changed = true;
3474         }
3475
3476         /*
3477          * Don't touch WM1S_LP_EN here.
3478          * Doing so could cause underruns.
3479          */
3480
3481         return changed;
3482 }
3483
3484 /*
3485  * The spec says we shouldn't write when we don't need, because every write
3486  * causes WMs to be re-evaluated, expending some power.
3487  */
3488 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3489                                 struct ilk_wm_values *results)
3490 {
3491         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3492         unsigned int dirty;
3493         uint32_t val;
3494
3495         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3496         if (!dirty)
3497                 return;
3498
3499         _ilk_disable_lp_wm(dev_priv, dirty);
3500
3501         if (dirty & WM_DIRTY_PIPE(PIPE_A))
3502                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3503         if (dirty & WM_DIRTY_PIPE(PIPE_B))
3504                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3505         if (dirty & WM_DIRTY_PIPE(PIPE_C))
3506                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3507
3508         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
3509                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
3510         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3511                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3512         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3513                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3514
3515         if (dirty & WM_DIRTY_DDB) {
3516                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3517                         val = I915_READ(WM_MISC);
3518                         if (results->partitioning == INTEL_DDB_PART_1_2)
3519                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3520                         else
3521                                 val |= WM_MISC_DATA_PARTITION_5_6;
3522                         I915_WRITE(WM_MISC, val);
3523                 } else {
3524                         val = I915_READ(DISP_ARB_CTL2);
3525                         if (results->partitioning == INTEL_DDB_PART_1_2)
3526                                 val &= ~DISP_DATA_PARTITION_5_6;
3527                         else
3528                                 val |= DISP_DATA_PARTITION_5_6;
3529                         I915_WRITE(DISP_ARB_CTL2, val);
3530                 }
3531         }
3532
3533         if (dirty & WM_DIRTY_FBC) {
3534                 val = I915_READ(DISP_ARB_CTL);
3535                 if (results->enable_fbc_wm)
3536                         val &= ~DISP_FBC_WM_DIS;
3537                 else
3538                         val |= DISP_FBC_WM_DIS;
3539                 I915_WRITE(DISP_ARB_CTL, val);
3540         }
3541
3542         if (dirty & WM_DIRTY_LP(1) &&
3543             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3544                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3545
3546         if (INTEL_GEN(dev_priv) >= 7) {
3547                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3548                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3549                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3550                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3551         }
3552
3553         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3554                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3555         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3556                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3557         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3558                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3559
3560         dev_priv->wm.hw = *results;
3561 }
3562
3563 bool ilk_disable_lp_wm(struct drm_device *dev)
3564 {
3565         struct drm_i915_private *dev_priv = to_i915(dev);
3566
3567         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3568 }
3569
3570 static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
3571 {
3572         u8 enabled_slices;
3573
3574         /* Slice 1 will always be enabled */
3575         enabled_slices = 1;
3576
3577         /* Gen prior to GEN11 have only one DBuf slice */
3578         if (INTEL_GEN(dev_priv) < 11)
3579                 return enabled_slices;
3580
3581         if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
3582                 enabled_slices++;
3583
3584         return enabled_slices;
3585 }
3586
3587 /*
3588  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3589  * so assume we'll always need it in order to avoid underruns.
3590  */
3591 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
3592 {
3593         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3594
3595         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
3596                 return true;
3597
3598         return false;
3599 }
3600
3601 static bool
3602 intel_has_sagv(struct drm_i915_private *dev_priv)
3603 {
3604         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
3605             IS_CANNONLAKE(dev_priv))
3606                 return true;
3607
3608         if (IS_SKYLAKE(dev_priv) &&
3609             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
3610                 return true;
3611
3612         return false;
3613 }
3614
3615 /*
3616  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3617  * depending on power and performance requirements. The display engine access
3618  * to system memory is blocked during the adjustment time. Because of the
3619  * blocking time, having this enabled can cause full system hangs and/or pipe
3620  * underruns if we don't meet all of the following requirements:
3621  *
3622  *  - <= 1 pipe enabled
3623  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3624  *  - We're not using an interlaced display configuration
3625  */
3626 int
3627 intel_enable_sagv(struct drm_i915_private *dev_priv)
3628 {
3629         int ret;
3630
3631         if (!intel_has_sagv(dev_priv))
3632                 return 0;
3633
3634         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3635                 return 0;
3636
3637         DRM_DEBUG_KMS("Enabling the SAGV\n");
3638         mutex_lock(&dev_priv->pcu_lock);
3639
3640         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3641                                       GEN9_SAGV_ENABLE);
3642
3643         /* We don't need to wait for the SAGV when enabling */
3644         mutex_unlock(&dev_priv->pcu_lock);
3645
3646         /*
3647          * Some skl systems, pre-release machines in particular,
3648          * don't actually have an SAGV.
3649          */
3650         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3651                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3652                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3653                 return 0;
3654         } else if (ret < 0) {
3655                 DRM_ERROR("Failed to enable the SAGV\n");
3656                 return ret;
3657         }
3658
3659         dev_priv->sagv_status = I915_SAGV_ENABLED;
3660         return 0;
3661 }
3662
3663 int
3664 intel_disable_sagv(struct drm_i915_private *dev_priv)
3665 {
3666         int ret;
3667
3668         if (!intel_has_sagv(dev_priv))
3669                 return 0;
3670
3671         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3672                 return 0;
3673
3674         DRM_DEBUG_KMS("Disabling the SAGV\n");
3675         mutex_lock(&dev_priv->pcu_lock);
3676
3677         /* bspec says to keep retrying for at least 1 ms */
3678         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3679                                 GEN9_SAGV_DISABLE,
3680                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3681                                 1);
3682         mutex_unlock(&dev_priv->pcu_lock);
3683
3684         /*
3685          * Some skl systems, pre-release machines in particular,
3686          * don't actually have an SAGV.
3687          */
3688         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3689                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3690                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3691                 return 0;
3692         } else if (ret < 0) {
3693                 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
3694                 return ret;
3695         }
3696
3697         dev_priv->sagv_status = I915_SAGV_DISABLED;
3698         return 0;
3699 }
3700
3701 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3702 {
3703         struct drm_device *dev = state->dev;
3704         struct drm_i915_private *dev_priv = to_i915(dev);
3705         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3706         struct intel_crtc *crtc;
3707         struct intel_plane *plane;
3708         struct intel_crtc_state *cstate;
3709         enum pipe pipe;
3710         int level, latency;
3711         int sagv_block_time_us;
3712
3713         if (!intel_has_sagv(dev_priv))
3714                 return false;
3715
3716         if (IS_GEN9(dev_priv))
3717                 sagv_block_time_us = 30;
3718         else if (IS_GEN10(dev_priv))
3719                 sagv_block_time_us = 20;
3720         else
3721                 sagv_block_time_us = 10;
3722
3723         /*
3724          * SKL+ workaround: bspec recommends we disable the SAGV when we have
3725          * more then one pipe enabled
3726          *
3727          * If there are no active CRTCs, no additional checks need be performed
3728          */
3729         if (hweight32(intel_state->active_crtcs) == 0)
3730                 return true;
3731         else if (hweight32(intel_state->active_crtcs) > 1)
3732                 return false;
3733
3734         /* Since we're now guaranteed to only have one active CRTC... */
3735         pipe = ffs(intel_state->active_crtcs) - 1;
3736         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3737         cstate = to_intel_crtc_state(crtc->base.state);
3738
3739         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3740                 return false;
3741
3742         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3743                 struct skl_plane_wm *wm =
3744                         &cstate->wm.skl.optimal.planes[plane->id];
3745
3746                 /* Skip this plane if it's not enabled */
3747                 if (!wm->wm[0].plane_en)
3748                         continue;
3749
3750                 /* Find the highest enabled wm level for this plane */
3751                 for (level = ilk_wm_max_level(dev_priv);
3752                      !wm->wm[level].plane_en; --level)
3753                      { }
3754
3755                 latency = dev_priv->wm.skl_latency[level];
3756
3757                 if (skl_needs_memory_bw_wa(intel_state) &&
3758                     plane->base.state->fb->modifier ==
3759                     I915_FORMAT_MOD_X_TILED)
3760                         latency += 15;
3761
3762                 /*
3763                  * If any of the planes on this pipe don't enable wm levels that
3764                  * incur memory latencies higher than sagv_block_time_us we
3765                  * can't enable the SAGV.
3766                  */
3767                 if (latency < sagv_block_time_us)
3768                         return false;
3769         }
3770
3771         return true;
3772 }
3773
3774 static unsigned int intel_get_ddb_size(struct drm_i915_private *dev_priv,
3775                                        const struct intel_crtc_state *cstate,
3776                                        const unsigned int total_data_rate,
3777                                        const int num_active,
3778                                        struct skl_ddb_allocation *ddb)
3779 {
3780         const struct drm_display_mode *adjusted_mode;
3781         u64 total_data_bw;
3782         u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3783
3784         WARN_ON(ddb_size == 0);
3785
3786         if (INTEL_GEN(dev_priv) < 11)
3787                 return ddb_size - 4; /* 4 blocks for bypass path allocation */
3788
3789         adjusted_mode = &cstate->base.adjusted_mode;
3790         total_data_bw = (u64)total_data_rate * drm_mode_vrefresh(adjusted_mode);
3791
3792         /*
3793          * 12GB/s is maximum BW supported by single DBuf slice.
3794          */
3795         if (total_data_bw >= GBps(12) || num_active > 1) {
3796                 ddb->enabled_slices = 2;
3797         } else {
3798                 ddb->enabled_slices = 1;
3799                 ddb_size /= 2;
3800         }
3801
3802         return ddb_size;
3803 }
3804
3805 static void
3806 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3807                                    const struct intel_crtc_state *cstate,
3808                                    const unsigned int total_data_rate,
3809                                    struct skl_ddb_allocation *ddb,
3810                                    struct skl_ddb_entry *alloc, /* out */
3811                                    int *num_active /* out */)
3812 {
3813         struct drm_atomic_state *state = cstate->base.state;
3814         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3815         struct drm_i915_private *dev_priv = to_i915(dev);
3816         struct drm_crtc *for_crtc = cstate->base.crtc;
3817         unsigned int pipe_size, ddb_size;
3818         int nth_active_pipe;
3819
3820         if (WARN_ON(!state) || !cstate->base.active) {
3821                 alloc->start = 0;
3822                 alloc->end = 0;
3823                 *num_active = hweight32(dev_priv->active_crtcs);
3824                 return;
3825         }
3826
3827         if (intel_state->active_pipe_changes)
3828                 *num_active = hweight32(intel_state->active_crtcs);
3829         else
3830                 *num_active = hweight32(dev_priv->active_crtcs);
3831
3832         ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,
3833                                       *num_active, ddb);
3834
3835         /*
3836          * If the state doesn't change the active CRTC's, then there's
3837          * no need to recalculate; the existing pipe allocation limits
3838          * should remain unchanged.  Note that we're safe from racing
3839          * commits since any racing commit that changes the active CRTC
3840          * list would need to grab _all_ crtc locks, including the one
3841          * we currently hold.
3842          */
3843         if (!intel_state->active_pipe_changes) {
3844                 /*
3845                  * alloc may be cleared by clear_intel_crtc_state,
3846                  * copy from old state to be sure
3847                  */
3848                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3849                 return;
3850         }
3851
3852         nth_active_pipe = hweight32(intel_state->active_crtcs &
3853                                     (drm_crtc_mask(for_crtc) - 1));
3854         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3855         alloc->start = nth_active_pipe * ddb_size / *num_active;
3856         alloc->end = alloc->start + pipe_size;
3857 }
3858
3859 static unsigned int skl_cursor_allocation(int num_active)
3860 {
3861         if (num_active == 1)
3862                 return 32;
3863
3864         return 8;
3865 }
3866
3867 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
3868                                        struct skl_ddb_entry *entry, u32 reg)
3869 {
3870         u16 mask;
3871
3872         if (INTEL_GEN(dev_priv) >= 11)
3873                 mask = ICL_DDB_ENTRY_MASK;
3874         else
3875                 mask = SKL_DDB_ENTRY_MASK;
3876         entry->start = reg & mask;
3877         entry->end = (reg >> DDB_ENTRY_END_SHIFT) & mask;
3878
3879         if (entry->end)
3880                 entry->end += 1;
3881 }
3882
3883 static void
3884 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
3885                            const enum pipe pipe,
3886                            const enum plane_id plane_id,
3887                            struct skl_ddb_allocation *ddb /* out */)
3888 {
3889         u32 val, val2 = 0;
3890         int fourcc, pixel_format;
3891
3892         /* Cursor doesn't support NV12/planar, so no extra calculation needed */
3893         if (plane_id == PLANE_CURSOR) {
3894                 val = I915_READ(CUR_BUF_CFG(pipe));
3895                 skl_ddb_entry_init_from_hw(dev_priv,
3896                                            &ddb->plane[pipe][plane_id], val);
3897                 return;
3898         }
3899
3900         val = I915_READ(PLANE_CTL(pipe, plane_id));
3901
3902         /* No DDB allocated for disabled planes */
3903         if (!(val & PLANE_CTL_ENABLE))
3904                 return;
3905
3906         pixel_format = val & PLANE_CTL_FORMAT_MASK;
3907         fourcc = skl_format_to_fourcc(pixel_format,
3908                                       val & PLANE_CTL_ORDER_RGBX,
3909                                       val & PLANE_CTL_ALPHA_MASK);
3910
3911         val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3912         val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
3913
3914         if (fourcc == DRM_FORMAT_NV12) {
3915                 skl_ddb_entry_init_from_hw(dev_priv,
3916                                            &ddb->plane[pipe][plane_id], val2);
3917                 skl_ddb_entry_init_from_hw(dev_priv,
3918                                            &ddb->uv_plane[pipe][plane_id], val);
3919         } else {
3920                 skl_ddb_entry_init_from_hw(dev_priv,
3921                                            &ddb->plane[pipe][plane_id], val);
3922         }
3923 }
3924
3925 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3926                           struct skl_ddb_allocation *ddb /* out */)
3927 {
3928         struct intel_crtc *crtc;
3929
3930         memset(ddb, 0, sizeof(*ddb));
3931
3932         ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
3933
3934         for_each_intel_crtc(&dev_priv->drm, crtc) {
3935                 enum intel_display_power_domain power_domain;
3936                 enum plane_id plane_id;
3937                 enum pipe pipe = crtc->pipe;
3938
3939                 power_domain = POWER_DOMAIN_PIPE(pipe);
3940                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3941                         continue;
3942
3943                 for_each_plane_id_on_crtc(crtc, plane_id)
3944                         skl_ddb_get_hw_plane_state(dev_priv, pipe,
3945                                                    plane_id, ddb);
3946
3947                 intel_display_power_put(dev_priv, power_domain);
3948         }
3949 }
3950
3951 /*
3952  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3953  * The bspec defines downscale amount as:
3954  *
3955  * """
3956  * Horizontal down scale amount = maximum[1, Horizontal source size /
3957  *                                           Horizontal destination size]
3958  * Vertical down scale amount = maximum[1, Vertical source size /
3959  *                                         Vertical destination size]
3960  * Total down scale amount = Horizontal down scale amount *
3961  *                           Vertical down scale amount
3962  * """
3963  *
3964  * Return value is provided in 16.16 fixed point form to retain fractional part.
3965  * Caller should take care of dividing & rounding off the value.
3966  */
3967 static uint_fixed_16_16_t
3968 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
3969                            const struct intel_plane_state *pstate)
3970 {
3971         struct intel_plane *plane = to_intel_plane(pstate->base.plane);
3972         uint32_t src_w, src_h, dst_w, dst_h;
3973         uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3974         uint_fixed_16_16_t downscale_h, downscale_w;
3975
3976         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
3977                 return u32_to_fixed16(0);
3978
3979         /* n.b., src is 16.16 fixed point, dst is whole integer */
3980         if (plane->id == PLANE_CURSOR) {
3981                 /*
3982                  * Cursors only support 0/180 degree rotation,
3983                  * hence no need to account for rotation here.
3984                  */
3985                 src_w = pstate->base.src_w >> 16;
3986                 src_h = pstate->base.src_h >> 16;
3987                 dst_w = pstate->base.crtc_w;
3988                 dst_h = pstate->base.crtc_h;
3989         } else {
3990                 /*
3991                  * Src coordinates are already rotated by 270 degrees for
3992                  * the 90/270 degree plane rotation cases (to match the
3993                  * GTT mapping), hence no need to account for rotation here.
3994                  */
3995                 src_w = drm_rect_width(&pstate->base.src) >> 16;
3996                 src_h = drm_rect_height(&pstate->base.src) >> 16;
3997                 dst_w = drm_rect_width(&pstate->base.dst);
3998                 dst_h = drm_rect_height(&pstate->base.dst);
3999         }
4000
4001         fp_w_ratio = div_fixed16(src_w, dst_w);
4002         fp_h_ratio = div_fixed16(src_h, dst_h);
4003         downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4004         downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4005
4006         return mul_fixed16(downscale_w, downscale_h);
4007 }
4008
4009 static uint_fixed_16_16_t
4010 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
4011 {
4012         uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
4013
4014         if (!crtc_state->base.enable)
4015                 return pipe_downscale;
4016
4017         if (crtc_state->pch_pfit.enabled) {
4018                 uint32_t src_w, src_h, dst_w, dst_h;
4019                 uint32_t pfit_size = crtc_state->pch_pfit.size;
4020                 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4021                 uint_fixed_16_16_t downscale_h, downscale_w;
4022
4023                 src_w = crtc_state->pipe_src_w;
4024                 src_h = crtc_state->pipe_src_h;
4025                 dst_w = pfit_size >> 16;
4026                 dst_h = pfit_size & 0xffff;
4027
4028                 if (!dst_w || !dst_h)
4029                         return pipe_downscale;
4030
4031                 fp_w_ratio = div_fixed16(src_w, dst_w);
4032                 fp_h_ratio = div_fixed16(src_h, dst_h);
4033                 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4034                 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4035
4036                 pipe_downscale = mul_fixed16(downscale_w, downscale_h);
4037         }
4038
4039         return pipe_downscale;
4040 }
4041
4042 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
4043                                   struct intel_crtc_state *cstate)
4044 {
4045         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4046         struct drm_crtc_state *crtc_state = &cstate->base;
4047         struct drm_atomic_state *state = crtc_state->state;
4048         struct drm_plane *plane;
4049         const struct drm_plane_state *pstate;
4050         struct intel_plane_state *intel_pstate;
4051         int crtc_clock, dotclk;
4052         uint32_t pipe_max_pixel_rate;
4053         uint_fixed_16_16_t pipe_downscale;
4054         uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
4055
4056         if (!cstate->base.enable)
4057                 return 0;
4058
4059         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
4060                 uint_fixed_16_16_t plane_downscale;
4061                 uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
4062                 int bpp;
4063
4064                 if (!intel_wm_plane_visible(cstate,
4065                                             to_intel_plane_state(pstate)))
4066                         continue;
4067
4068                 if (WARN_ON(!pstate->fb))
4069                         return -EINVAL;
4070
4071                 intel_pstate = to_intel_plane_state(pstate);
4072                 plane_downscale = skl_plane_downscale_amount(cstate,
4073                                                              intel_pstate);
4074                 bpp = pstate->fb->format->cpp[0] * 8;
4075                 if (bpp == 64)
4076                         plane_downscale = mul_fixed16(plane_downscale,
4077                                                       fp_9_div_8);
4078
4079                 max_downscale = max_fixed16(plane_downscale, max_downscale);
4080         }
4081         pipe_downscale = skl_pipe_downscale_amount(cstate);
4082
4083         pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
4084
4085         crtc_clock = crtc_state->adjusted_mode.crtc_clock;
4086         dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
4087
4088         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
4089                 dotclk *= 2;
4090
4091         pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
4092
4093         if (pipe_max_pixel_rate < crtc_clock) {
4094                 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
4095                 return -EINVAL;
4096         }
4097
4098         return 0;
4099 }
4100
4101 static unsigned int
4102 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
4103                              const struct drm_plane_state *pstate,
4104                              const int plane)
4105 {
4106         struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
4107         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
4108         uint32_t data_rate;
4109         uint32_t width = 0, height = 0;
4110         struct drm_framebuffer *fb;
4111         u32 format;
4112         uint_fixed_16_16_t down_scale_amount;
4113
4114         if (!intel_pstate->base.visible)
4115                 return 0;
4116
4117         fb = pstate->fb;
4118         format = fb->format->format;
4119
4120         if (intel_plane->id == PLANE_CURSOR)
4121                 return 0;
4122         if (plane == 1 && format != DRM_FORMAT_NV12)
4123                 return 0;
4124
4125         /*
4126          * Src coordinates are already rotated by 270 degrees for
4127          * the 90/270 degree plane rotation cases (to match the
4128          * GTT mapping), hence no need to account for rotation here.
4129          */
4130         width = drm_rect_width(&intel_pstate->base.src) >> 16;
4131         height = drm_rect_height(&intel_pstate->base.src) >> 16;
4132
4133         /* UV plane does 1/2 pixel sub-sampling */
4134         if (plane == 1 && format == DRM_FORMAT_NV12) {
4135                 width /= 2;
4136                 height /= 2;
4137         }
4138
4139         data_rate = width * height * fb->format->cpp[plane];
4140
4141         down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
4142
4143         return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4144 }
4145
4146 /*
4147  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4148  * a 8192x4096@32bpp framebuffer:
4149  *   3 * 4096 * 8192  * 4 < 2^32
4150  */
4151 static unsigned int
4152 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
4153                                  unsigned int *plane_data_rate,
4154                                  unsigned int *uv_plane_data_rate)
4155 {
4156         struct drm_crtc_state *cstate = &intel_cstate->base;
4157         struct drm_atomic_state *state = cstate->state;
4158         struct drm_plane *plane;
4159         const struct drm_plane_state *pstate;
4160         unsigned int total_data_rate = 0;
4161
4162         if (WARN_ON(!state))
4163                 return 0;
4164
4165         /* Calculate and cache data rate for each plane */
4166         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
4167                 enum plane_id plane_id = to_intel_plane(plane)->id;
4168                 unsigned int rate;
4169
4170                 /* packed/y */
4171                 rate = skl_plane_relative_data_rate(intel_cstate,
4172                                                     pstate, 0);
4173                 plane_data_rate[plane_id] = rate;
4174
4175                 total_data_rate += rate;
4176
4177                 /* uv-plane */
4178                 rate = skl_plane_relative_data_rate(intel_cstate,
4179                                                     pstate, 1);
4180                 uv_plane_data_rate[plane_id] = rate;
4181
4182                 total_data_rate += rate;
4183         }
4184
4185         return total_data_rate;
4186 }
4187
4188 static uint16_t
4189 skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
4190 {
4191         struct drm_framebuffer *fb = pstate->fb;
4192         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
4193         uint32_t src_w, src_h;
4194         uint32_t min_scanlines = 8;
4195         uint8_t plane_bpp;
4196
4197         if (WARN_ON(!fb))
4198                 return 0;
4199
4200         /* For packed formats, and uv-plane, return 0 */
4201         if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
4202                 return 0;
4203
4204         /* For Non Y-tile return 8-blocks */
4205         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
4206             fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
4207             fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
4208             fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
4209                 return 8;
4210
4211         /*
4212          * Src coordinates are already rotated by 270 degrees for
4213          * the 90/270 degree plane rotation cases (to match the
4214          * GTT mapping), hence no need to account for rotation here.
4215          */
4216         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
4217         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
4218
4219         /* Halve UV plane width and height for NV12 */
4220         if (plane == 1) {
4221                 src_w /= 2;
4222                 src_h /= 2;
4223         }
4224
4225         plane_bpp = fb->format->cpp[plane];
4226
4227         if (drm_rotation_90_or_270(pstate->rotation)) {
4228                 switch (plane_bpp) {
4229                 case 1:
4230                         min_scanlines = 32;
4231                         break;
4232                 case 2:
4233                         min_scanlines = 16;
4234                         break;
4235                 case 4:
4236                         min_scanlines = 8;
4237                         break;
4238                 case 8:
4239                         min_scanlines = 4;
4240                         break;
4241                 default:
4242                         WARN(1, "Unsupported pixel depth %u for rotation",
4243                              plane_bpp);
4244                         min_scanlines = 32;
4245                 }
4246         }
4247
4248         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
4249 }
4250
4251 static void
4252 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
4253                  uint16_t *minimum, uint16_t *uv_minimum)
4254 {
4255         const struct drm_plane_state *pstate;
4256         struct drm_plane *plane;
4257
4258         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
4259                 enum plane_id plane_id = to_intel_plane(plane)->id;
4260
4261                 if (plane_id == PLANE_CURSOR)
4262                         continue;
4263
4264                 if (!pstate->visible)
4265                         continue;
4266
4267                 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
4268                 uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
4269         }
4270
4271         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
4272 }
4273
4274 static int
4275 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
4276                       struct skl_ddb_allocation *ddb /* out */)
4277 {
4278         struct drm_atomic_state *state = cstate->base.state;
4279         struct drm_crtc *crtc = cstate->base.crtc;
4280         struct drm_device *dev = crtc->dev;
4281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4282         enum pipe pipe = intel_crtc->pipe;
4283         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
4284         uint16_t alloc_size, start;
4285         uint16_t minimum[I915_MAX_PLANES] = {};
4286         uint16_t uv_minimum[I915_MAX_PLANES] = {};
4287         unsigned int total_data_rate;
4288         enum plane_id plane_id;
4289         int num_active;
4290         unsigned int plane_data_rate[I915_MAX_PLANES] = {};
4291         unsigned int uv_plane_data_rate[I915_MAX_PLANES] = {};
4292         uint16_t total_min_blocks = 0;
4293
4294         /* Clear the partitioning for disabled planes. */
4295         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4296         memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
4297
4298         if (WARN_ON(!state))
4299                 return 0;
4300
4301         if (!cstate->base.active) {
4302                 alloc->start = alloc->end = 0;
4303                 return 0;
4304         }
4305
4306         total_data_rate = skl_get_total_relative_data_rate(cstate,
4307                                                            plane_data_rate,
4308                                                            uv_plane_data_rate);
4309         skl_ddb_get_pipe_allocation_limits(dev, cstate, total_data_rate, ddb,
4310                                            alloc, &num_active);
4311         alloc_size = skl_ddb_entry_size(alloc);
4312         if (alloc_size == 0)
4313                 return 0;
4314
4315         skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);
4316
4317         /*
4318          * 1. Allocate the mininum required blocks for each active plane
4319          * and allocate the cursor, it doesn't require extra allocation
4320          * proportional to the data rate.
4321          */
4322
4323         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4324                 total_min_blocks += minimum[plane_id];
4325                 total_min_blocks += uv_minimum[plane_id];
4326         }
4327
4328         if (total_min_blocks > alloc_size) {
4329                 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4330                 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks,
4331                                                         alloc_size);
4332                 return -EINVAL;
4333         }
4334
4335         alloc_size -= total_min_blocks;
4336         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
4337         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
4338
4339         /*
4340          * 2. Distribute the remaining space in proportion to the amount of
4341          * data each plane needs to fetch from memory.
4342          *
4343          * FIXME: we may not allocate every single block here.
4344          */
4345         if (total_data_rate == 0)
4346                 return 0;
4347
4348         start = alloc->start;
4349         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4350                 unsigned int data_rate, uv_data_rate;
4351                 uint16_t plane_blocks, uv_plane_blocks;
4352
4353                 if (plane_id == PLANE_CURSOR)
4354                         continue;
4355
4356                 data_rate = plane_data_rate[plane_id];
4357
4358                 /*
4359                  * allocation for (packed formats) or (uv-plane part of planar format):
4360                  * promote the expression to 64 bits to avoid overflowing, the
4361                  * result is < available as data_rate / total_data_rate < 1
4362                  */
4363                 plane_blocks = minimum[plane_id];
4364                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
4365                                         total_data_rate);
4366
4367                 /* Leave disabled planes at (0,0) */
4368                 if (data_rate) {
4369                         ddb->plane[pipe][plane_id].start = start;
4370                         ddb->plane[pipe][plane_id].end = start + plane_blocks;
4371                 }
4372
4373                 start += plane_blocks;
4374
4375                 /* Allocate DDB for UV plane for planar format/NV12 */
4376                 uv_data_rate = uv_plane_data_rate[plane_id];
4377
4378                 uv_plane_blocks = uv_minimum[plane_id];
4379                 uv_plane_blocks += div_u64((uint64_t)alloc_size * uv_data_rate,
4380                                            total_data_rate);
4381
4382                 if (uv_data_rate) {
4383                         ddb->uv_plane[pipe][plane_id].start = start;
4384                         ddb->uv_plane[pipe][plane_id].end =
4385                                 start + uv_plane_blocks;
4386                 }
4387
4388                 start += uv_plane_blocks;
4389         }
4390
4391         return 0;
4392 }
4393
4394 /*
4395  * The max latency should be 257 (max the punit can code is 255 and we add 2us
4396  * for the read latency) and cpp should always be <= 8, so that
4397  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4398  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4399 */
4400 static uint_fixed_16_16_t
4401 skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
4402                uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
4403 {
4404         uint32_t wm_intermediate_val;
4405         uint_fixed_16_16_t ret;
4406
4407         if (latency == 0)
4408                 return FP_16_16_MAX;
4409
4410         wm_intermediate_val = latency * pixel_rate * cpp;
4411         ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
4412
4413         if (INTEL_GEN(dev_priv) >= 10)
4414                 ret = add_fixed16_u32(ret, 1);
4415
4416         return ret;
4417 }
4418
4419 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
4420                         uint32_t pipe_htotal,
4421                         uint32_t latency,
4422                         uint_fixed_16_16_t plane_blocks_per_line)
4423 {
4424         uint32_t wm_intermediate_val;
4425         uint_fixed_16_16_t ret;
4426
4427         if (latency == 0)
4428                 return FP_16_16_MAX;
4429
4430         wm_intermediate_val = latency * pixel_rate;
4431         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4432                                            pipe_htotal * 1000);
4433         ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
4434         return ret;
4435 }
4436
4437 static uint_fixed_16_16_t
4438 intel_get_linetime_us(struct intel_crtc_state *cstate)
4439 {
4440         uint32_t pixel_rate;
4441         uint32_t crtc_htotal;
4442         uint_fixed_16_16_t linetime_us;
4443
4444         if (!cstate->base.active)
4445                 return u32_to_fixed16(0);
4446
4447         pixel_rate = cstate->pixel_rate;
4448
4449         if (WARN_ON(pixel_rate == 0))
4450                 return u32_to_fixed16(0);
4451
4452         crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
4453         linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
4454
4455         return linetime_us;
4456 }
4457
4458 static uint32_t
4459 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
4460                               const struct intel_plane_state *pstate)
4461 {
4462         uint64_t adjusted_pixel_rate;
4463         uint_fixed_16_16_t downscale_amount;
4464
4465         /* Shouldn't reach here on disabled planes... */
4466         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
4467                 return 0;
4468
4469         /*
4470          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4471          * with additional adjustments for plane-specific scaling.
4472          */
4473         adjusted_pixel_rate = cstate->pixel_rate;
4474         downscale_amount = skl_plane_downscale_amount(cstate, pstate);
4475
4476         return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4477                                             downscale_amount);
4478 }
4479
4480 static int
4481 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
4482                             struct intel_crtc_state *cstate,
4483                             const struct intel_plane_state *intel_pstate,
4484                             struct skl_wm_params *wp, int plane_id)
4485 {
4486         struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
4487         const struct drm_plane_state *pstate = &intel_pstate->base;
4488         const struct drm_framebuffer *fb = pstate->fb;
4489         uint32_t interm_pbpl;
4490         struct intel_atomic_state *state =
4491                 to_intel_atomic_state(cstate->base.state);
4492         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4493
4494         if (!intel_wm_plane_visible(cstate, intel_pstate))
4495                 return 0;
4496
4497         /* only NV12 format has two planes */
4498         if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
4499                 DRM_DEBUG_KMS("Non NV12 format have single plane\n");
4500                 return -EINVAL;
4501         }
4502
4503         wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
4504                       fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
4505                       fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4506                       fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4507         wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
4508         wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4509                          fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4510         wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
4511
4512         if (plane->id == PLANE_CURSOR) {
4513                 wp->width = intel_pstate->base.crtc_w;
4514         } else {
4515                 /*
4516                  * Src coordinates are already rotated by 270 degrees for
4517                  * the 90/270 degree plane rotation cases (to match the
4518                  * GTT mapping), hence no need to account for rotation here.
4519                  */
4520                 wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
4521         }
4522
4523         if (plane_id == 1 && wp->is_planar)
4524                 wp->width /= 2;
4525
4526         wp->cpp = fb->format->cpp[plane_id];
4527         wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
4528                                                              intel_pstate);
4529
4530         if (INTEL_GEN(dev_priv) >= 11 &&
4531             fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
4532                 wp->dbuf_block_size = 256;
4533         else
4534                 wp->dbuf_block_size = 512;
4535
4536         if (drm_rotation_90_or_270(pstate->rotation)) {
4537
4538                 switch (wp->cpp) {
4539                 case 1:
4540                         wp->y_min_scanlines = 16;
4541                         break;
4542                 case 2:
4543                         wp->y_min_scanlines = 8;
4544                         break;
4545                 case 4:
4546                         wp->y_min_scanlines = 4;
4547                         break;
4548                 default:
4549                         MISSING_CASE(wp->cpp);
4550                         return -EINVAL;
4551                 }
4552         } else {
4553                 wp->y_min_scanlines = 4;
4554         }
4555
4556         if (apply_memory_bw_wa)
4557                 wp->y_min_scanlines *= 2;
4558
4559         wp->plane_bytes_per_line = wp->width * wp->cpp;
4560         if (wp->y_tiled) {
4561                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
4562                                            wp->y_min_scanlines,
4563                                            wp->dbuf_block_size);
4564
4565                 if (INTEL_GEN(dev_priv) >= 10)
4566                         interm_pbpl++;
4567
4568                 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
4569                                                         wp->y_min_scanlines);
4570         } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
4571                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4572                                            wp->dbuf_block_size);
4573                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4574         } else {
4575                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4576                                            wp->dbuf_block_size) + 1;
4577                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4578         }
4579
4580         wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
4581                                              wp->plane_blocks_per_line);
4582         wp->linetime_us = fixed16_to_u32_round_up(
4583                                         intel_get_linetime_us(cstate));
4584
4585         return 0;
4586 }
4587
4588 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4589                                 struct intel_crtc_state *cstate,
4590                                 const struct intel_plane_state *intel_pstate,
4591                                 uint16_t ddb_allocation,
4592                                 int level,
4593                                 const struct skl_wm_params *wp,
4594                                 const struct skl_wm_level *result_prev,
4595                                 struct skl_wm_level *result /* out */)
4596 {
4597         const struct drm_plane_state *pstate = &intel_pstate->base;
4598         uint32_t latency = dev_priv->wm.skl_latency[level];
4599         uint_fixed_16_16_t method1, method2;
4600         uint_fixed_16_16_t selected_result;
4601         uint32_t res_blocks, res_lines;
4602         struct intel_atomic_state *state =
4603                 to_intel_atomic_state(cstate->base.state);
4604         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4605         uint32_t min_disp_buf_needed;
4606
4607         if (latency == 0 ||
4608             !intel_wm_plane_visible(cstate, intel_pstate)) {
4609                 result->plane_en = false;
4610                 return 0;
4611         }
4612
4613         /* Display WA #1141: kbl,cfl */
4614         if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
4615             IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
4616             dev_priv->ipc_enabled)
4617                 latency += 4;
4618
4619         if (apply_memory_bw_wa && wp->x_tiled)
4620                 latency += 15;
4621
4622         method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
4623                                  wp->cpp, latency, wp->dbuf_block_size);
4624         method2 = skl_wm_method2(wp->plane_pixel_rate,
4625                                  cstate->base.adjusted_mode.crtc_htotal,
4626                                  latency,
4627                                  wp->plane_blocks_per_line);
4628
4629         if (wp->y_tiled) {
4630                 selected_result = max_fixed16(method2, wp->y_tile_minimum);
4631         } else {
4632                 if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
4633                      wp->dbuf_block_size < 1) &&
4634                      (wp->plane_bytes_per_line / wp->dbuf_block_size < 1))
4635                         selected_result = method2;
4636                 else if (ddb_allocation >=
4637                          fixed16_to_u32_round_up(wp->plane_blocks_per_line))
4638                         selected_result = min_fixed16(method1, method2);
4639                 else if (latency >= wp->linetime_us)
4640                         selected_result = min_fixed16(method1, method2);
4641                 else
4642                         selected_result = method1;
4643         }
4644
4645         res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
4646         res_lines = div_round_up_fixed16(selected_result,
4647                                          wp->plane_blocks_per_line);
4648
4649         /* Display WA #1125: skl,bxt,kbl,glk */
4650         if (level == 0 && wp->rc_surface)
4651                 res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
4652
4653         /* Display WA #1126: skl,bxt,kbl,glk */
4654         if (level >= 1 && level <= 7) {
4655                 if (wp->y_tiled) {
4656                         res_blocks += fixed16_to_u32_round_up(
4657                                                         wp->y_tile_minimum);
4658                         res_lines += wp->y_min_scanlines;
4659                 } else {
4660                         res_blocks++;
4661                 }
4662
4663                 /*
4664                  * Make sure result blocks for higher latency levels are atleast
4665                  * as high as level below the current level.
4666                  * Assumption in DDB algorithm optimization for special cases.
4667                  * Also covers Display WA #1125 for RC.
4668                  */
4669                 if (result_prev->plane_res_b > res_blocks)
4670                         res_blocks = result_prev->plane_res_b;
4671         }
4672
4673         if (INTEL_GEN(dev_priv) >= 11) {
4674                 if (wp->y_tiled) {
4675                         uint32_t extra_lines;
4676                         uint_fixed_16_16_t fp_min_disp_buf_needed;
4677
4678                         if (res_lines % wp->y_min_scanlines == 0)
4679                                 extra_lines = wp->y_min_scanlines;
4680                         else
4681                                 extra_lines = wp->y_min_scanlines * 2 -
4682                                               res_lines % wp->y_min_scanlines;
4683
4684                         fp_min_disp_buf_needed = mul_u32_fixed16(res_lines +
4685                                                 extra_lines,
4686                                                 wp->plane_blocks_per_line);
4687                         min_disp_buf_needed = fixed16_to_u32_round_up(
4688                                                 fp_min_disp_buf_needed);
4689                 } else {
4690                         min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10);
4691                 }
4692         } else {
4693                 min_disp_buf_needed = res_blocks;
4694         }
4695
4696         if ((level > 0 && res_lines > 31) ||
4697             res_blocks >= ddb_allocation ||
4698             min_disp_buf_needed >= ddb_allocation) {
4699                 result->plane_en = false;
4700
4701                 /*
4702                  * If there are no valid level 0 watermarks, then we can't
4703                  * support this display configuration.
4704                  */
4705                 if (level) {
4706                         return 0;
4707                 } else {
4708                         struct drm_plane *plane = pstate->plane;
4709
4710                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4711                         DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4712                                       plane->base.id, plane->name,
4713                                       res_blocks, ddb_allocation, res_lines);
4714                         return -EINVAL;
4715                 }
4716         }
4717
4718         /*
4719          * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
4720          * disable wm level 1-7 on NV12 planes
4721          */
4722         if (wp->is_planar && level >= 1 &&
4723             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
4724              IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
4725                 result->plane_en = false;
4726                 return 0;
4727         }
4728
4729         /* The number of lines are ignored for the level 0 watermark. */
4730         result->plane_res_b = res_blocks;
4731         result->plane_res_l = res_lines;
4732         result->plane_en = true;
4733
4734         return 0;
4735 }
4736
4737 static int
4738 skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
4739                       struct skl_ddb_allocation *ddb,
4740                       struct intel_crtc_state *cstate,
4741                       const struct intel_plane_state *intel_pstate,
4742                       const struct skl_wm_params *wm_params,
4743                       struct skl_plane_wm *wm,
4744                       int plane_id)
4745 {
4746         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4747         struct drm_plane *plane = intel_pstate->base.plane;
4748         struct intel_plane *intel_plane = to_intel_plane(plane);
4749         uint16_t ddb_blocks;
4750         enum pipe pipe = intel_crtc->pipe;
4751         int level, max_level = ilk_wm_max_level(dev_priv);
4752         enum plane_id intel_plane_id = intel_plane->id;
4753         int ret;
4754
4755         if (WARN_ON(!intel_pstate->base.fb))
4756                 return -EINVAL;
4757
4758         ddb_blocks = plane_id ?
4759                      skl_ddb_entry_size(&ddb->uv_plane[pipe][intel_plane_id]) :
4760                      skl_ddb_entry_size(&ddb->plane[pipe][intel_plane_id]);
4761
4762         for (level = 0; level <= max_level; level++) {
4763                 struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] :
4764                                                           &wm->wm[level];
4765                 struct skl_wm_level *result_prev;
4766
4767                 if (level)
4768                         result_prev = plane_id ? &wm->uv_wm[level - 1] :
4769                                                   &wm->wm[level - 1];
4770                 else
4771                         result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0];
4772
4773                 ret = skl_compute_plane_wm(dev_priv,
4774                                            cstate,
4775                                            intel_pstate,
4776                                            ddb_blocks,
4777                                            level,
4778                                            wm_params,
4779                                            result_prev,
4780                                            result);
4781                 if (ret)
4782                         return ret;
4783         }
4784
4785         if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
4786                 wm->is_planar = true;
4787
4788         return 0;
4789 }
4790
4791 static uint32_t
4792 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
4793 {
4794         struct drm_atomic_state *state = cstate->base.state;
4795         struct drm_i915_private *dev_priv = to_i915(state->dev);
4796         uint_fixed_16_16_t linetime_us;
4797         uint32_t linetime_wm;
4798
4799         linetime_us = intel_get_linetime_us(cstate);
4800
4801         if (is_fixed16_zero(linetime_us))
4802                 return 0;
4803
4804         linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
4805
4806         /* Display WA #1135: bxt:ALL GLK:ALL */
4807         if ((IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) &&
4808             dev_priv->ipc_enabled)
4809                 linetime_wm /= 2;
4810
4811         return linetime_wm;
4812 }
4813
4814 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
4815                                       struct skl_wm_params *wp,
4816                                       struct skl_wm_level *wm_l0,
4817                                       uint16_t ddb_allocation,
4818                                       struct skl_wm_level *trans_wm /* out */)
4819 {
4820         struct drm_device *dev = cstate->base.crtc->dev;
4821         const struct drm_i915_private *dev_priv = to_i915(dev);
4822         uint16_t trans_min, trans_y_tile_min;
4823         const uint16_t trans_amount = 10; /* This is configurable amount */
4824         uint16_t trans_offset_b, res_blocks;
4825
4826         if (!cstate->base.active)
4827                 goto exit;
4828
4829         /* Transition WM are not recommended by HW team for GEN9 */
4830         if (INTEL_GEN(dev_priv) <= 9)
4831                 goto exit;
4832
4833         /* Transition WM don't make any sense if ipc is disabled */
4834         if (!dev_priv->ipc_enabled)
4835                 goto exit;
4836
4837         trans_min = 0;
4838         if (INTEL_GEN(dev_priv) >= 10)
4839                 trans_min = 4;
4840
4841         trans_offset_b = trans_min + trans_amount;
4842
4843         if (wp->y_tiled) {
4844                 trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
4845                                                         wp->y_tile_minimum);
4846                 res_blocks = max(wm_l0->plane_res_b, trans_y_tile_min) +
4847                                 trans_offset_b;
4848         } else {
4849                 res_blocks = wm_l0->plane_res_b + trans_offset_b;
4850
4851                 /* WA BUG:1938466 add one block for non y-tile planes */
4852                 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
4853                         res_blocks += 1;
4854
4855         }
4856
4857         res_blocks += 1;
4858
4859         if (res_blocks < ddb_allocation) {
4860                 trans_wm->plane_res_b = res_blocks;
4861                 trans_wm->plane_en = true;
4862                 return;
4863         }
4864
4865 exit:
4866         trans_wm->plane_en = false;
4867 }
4868
4869 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
4870                              struct skl_ddb_allocation *ddb,
4871                              struct skl_pipe_wm *pipe_wm)
4872 {
4873         struct drm_device *dev = cstate->base.crtc->dev;
4874         struct drm_crtc_state *crtc_state = &cstate->base;
4875         const struct drm_i915_private *dev_priv = to_i915(dev);
4876         struct drm_plane *plane;
4877         const struct drm_plane_state *pstate;
4878         struct skl_plane_wm *wm;
4879         int ret;
4880
4881         /*
4882          * We'll only calculate watermarks for planes that are actually
4883          * enabled, so make sure all other planes are set as disabled.
4884          */
4885         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
4886
4887         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
4888                 const struct intel_plane_state *intel_pstate =
4889                                                 to_intel_plane_state(pstate);
4890                 enum plane_id plane_id = to_intel_plane(plane)->id;
4891                 struct skl_wm_params wm_params;
4892                 enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
4893                 uint16_t ddb_blocks;
4894
4895                 wm = &pipe_wm->planes[plane_id];
4896                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
4897
4898                 ret = skl_compute_plane_wm_params(dev_priv, cstate,
4899                                                   intel_pstate, &wm_params, 0);
4900                 if (ret)
4901                         return ret;
4902
4903                 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4904                                             intel_pstate, &wm_params, wm, 0);
4905                 if (ret)
4906                         return ret;
4907
4908                 skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
4909                                           ddb_blocks, &wm->trans_wm);
4910
4911                 /* uv plane watermarks must also be validated for NV12/Planar */
4912                 if (wm_params.is_planar) {
4913                         memset(&wm_params, 0, sizeof(struct skl_wm_params));
4914                         wm->is_planar = true;
4915
4916                         ret = skl_compute_plane_wm_params(dev_priv, cstate,
4917                                                           intel_pstate,
4918                                                           &wm_params, 1);
4919                         if (ret)
4920                                 return ret;
4921
4922                         ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4923                                                     intel_pstate, &wm_params,
4924                                                     wm, 1);
4925                         if (ret)
4926                                 return ret;
4927                 }
4928         }
4929
4930         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
4931
4932         return 0;
4933 }
4934
4935 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
4936                                 i915_reg_t reg,
4937                                 const struct skl_ddb_entry *entry)
4938 {
4939         if (entry->end)
4940                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
4941         else
4942                 I915_WRITE(reg, 0);
4943 }
4944
4945 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
4946                                i915_reg_t reg,
4947                                const struct skl_wm_level *level)
4948 {
4949         uint32_t val = 0;
4950
4951         if (level->plane_en) {
4952                 val |= PLANE_WM_EN;
4953                 val |= level->plane_res_b;
4954                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
4955         }
4956
4957         I915_WRITE(reg, val);
4958 }
4959
4960 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
4961                                const struct skl_plane_wm *wm,
4962                                const struct skl_ddb_allocation *ddb,
4963                                enum plane_id plane_id)
4964 {
4965         struct drm_crtc *crtc = &intel_crtc->base;
4966         struct drm_device *dev = crtc->dev;
4967         struct drm_i915_private *dev_priv = to_i915(dev);
4968         int level, max_level = ilk_wm_max_level(dev_priv);
4969         enum pipe pipe = intel_crtc->pipe;
4970
4971         for (level = 0; level <= max_level; level++) {
4972                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
4973                                    &wm->wm[level]);
4974         }
4975         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
4976                            &wm->trans_wm);
4977
4978         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4979                             &ddb->plane[pipe][plane_id]);
4980         if (INTEL_GEN(dev_priv) >= 11)
4981                 return skl_ddb_entry_write(dev_priv,
4982                                            PLANE_BUF_CFG(pipe, plane_id),
4983                                            &ddb->plane[pipe][plane_id]);
4984         if (wm->is_planar) {
4985                 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4986                                     &ddb->uv_plane[pipe][plane_id]);
4987                 skl_ddb_entry_write(dev_priv,
4988                                     PLANE_NV12_BUF_CFG(pipe, plane_id),
4989                                     &ddb->plane[pipe][plane_id]);
4990         } else {
4991                 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4992                                     &ddb->plane[pipe][plane_id]);
4993                 I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
4994         }
4995 }
4996
4997 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
4998                                 const struct skl_plane_wm *wm,
4999                                 const struct skl_ddb_allocation *ddb)
5000 {
5001         struct drm_crtc *crtc = &intel_crtc->base;
5002         struct drm_device *dev = crtc->dev;
5003         struct drm_i915_private *dev_priv = to_i915(dev);
5004         int level, max_level = ilk_wm_max_level(dev_priv);
5005         enum pipe pipe = intel_crtc->pipe;
5006
5007         for (level = 0; level <= max_level; level++) {
5008                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5009                                    &wm->wm[level]);
5010         }
5011         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5012
5013         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
5014                             &ddb->plane[pipe][PLANE_CURSOR]);
5015 }
5016
5017 bool skl_wm_level_equals(const struct skl_wm_level *l1,
5018                          const struct skl_wm_level *l2)
5019 {
5020         if (l1->plane_en != l2->plane_en)
5021                 return false;
5022
5023         /* If both planes aren't enabled, the rest shouldn't matter */
5024         if (!l1->plane_en)
5025                 return true;
5026
5027         return (l1->plane_res_l == l2->plane_res_l &&
5028                 l1->plane_res_b == l2->plane_res_b);
5029 }
5030
5031 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
5032                                            const struct skl_ddb_entry *b)
5033 {
5034         return a->start < b->end && b->start < a->end;
5035 }
5036
5037 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
5038                                  const struct skl_ddb_entry **entries,
5039                                  const struct skl_ddb_entry *ddb,
5040                                  int ignore)
5041 {
5042         enum pipe pipe;
5043
5044         for_each_pipe(dev_priv, pipe) {
5045                 if (pipe != ignore && entries[pipe] &&
5046                     skl_ddb_entries_overlap(ddb, entries[pipe]))
5047                         return true;
5048         }
5049
5050         return false;
5051 }
5052
5053 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
5054                               const struct skl_pipe_wm *old_pipe_wm,
5055                               struct skl_pipe_wm *pipe_wm, /* out */
5056                               struct skl_ddb_allocation *ddb, /* out */
5057                               bool *changed /* out */)
5058 {
5059         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
5060         int ret;
5061
5062         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
5063         if (ret)
5064                 return ret;
5065
5066         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
5067                 *changed = false;
5068         else
5069                 *changed = true;
5070
5071         return 0;
5072 }
5073
5074 static uint32_t
5075 pipes_modified(struct drm_atomic_state *state)
5076 {
5077         struct drm_crtc *crtc;
5078         struct drm_crtc_state *cstate;
5079         uint32_t i, ret = 0;
5080
5081         for_each_new_crtc_in_state(state, crtc, cstate, i)
5082                 ret |= drm_crtc_mask(crtc);
5083
5084         return ret;
5085 }
5086
5087 static int
5088 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
5089 {
5090         struct drm_atomic_state *state = cstate->base.state;
5091         struct drm_device *dev = state->dev;
5092         struct drm_crtc *crtc = cstate->base.crtc;
5093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5094         struct drm_i915_private *dev_priv = to_i915(dev);
5095         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5096         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
5097         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
5098         struct drm_plane_state *plane_state;
5099         struct drm_plane *plane;
5100         enum pipe pipe = intel_crtc->pipe;
5101
5102         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
5103                 enum plane_id plane_id = to_intel_plane(plane)->id;
5104
5105                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
5106                                         &new_ddb->plane[pipe][plane_id]) &&
5107                     skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
5108                                         &new_ddb->uv_plane[pipe][plane_id]))
5109                         continue;
5110
5111                 plane_state = drm_atomic_get_plane_state(state, plane);
5112                 if (IS_ERR(plane_state))
5113                         return PTR_ERR(plane_state);
5114         }
5115
5116         return 0;
5117 }
5118
5119 static int
5120 skl_compute_ddb(struct drm_atomic_state *state)
5121 {
5122         const struct drm_i915_private *dev_priv = to_i915(state->dev);
5123         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5124         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
5125         struct intel_crtc *crtc;
5126         struct intel_crtc_state *cstate;
5127         int ret, i;
5128
5129         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
5130
5131         for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
5132                 ret = skl_allocate_pipe_ddb(cstate, ddb);
5133                 if (ret)
5134                         return ret;
5135
5136                 ret = skl_ddb_add_affected_planes(cstate);
5137                 if (ret)
5138                         return ret;
5139         }
5140
5141         return 0;
5142 }
5143
5144 static void
5145 skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
5146                       struct skl_ddb_values *src,
5147                       enum pipe pipe)
5148 {
5149         memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
5150                sizeof(dst->ddb.uv_plane[pipe]));
5151         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
5152                sizeof(dst->ddb.plane[pipe]));
5153         dst->ddb.enabled_slices = src->ddb.enabled_slices;
5154 }
5155
5156 static void
5157 skl_print_wm_changes(const struct drm_atomic_state *state)
5158 {
5159         const struct drm_device *dev = state->dev;
5160         const struct drm_i915_private *dev_priv = to_i915(dev);
5161         const struct intel_atomic_state *intel_state =
5162                 to_intel_atomic_state(state);
5163         const struct drm_crtc *crtc;
5164         const struct drm_crtc_state *cstate;
5165         const struct intel_plane *intel_plane;
5166         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
5167         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
5168         int i;
5169
5170         for_each_new_crtc_in_state(state, crtc, cstate, i) {
5171                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5172                 enum pipe pipe = intel_crtc->pipe;
5173
5174                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
5175                         enum plane_id plane_id = intel_plane->id;
5176                         const struct skl_ddb_entry *old, *new;
5177
5178                         old = &old_ddb->plane[pipe][plane_id];
5179                         new = &new_ddb->plane[pipe][plane_id];
5180
5181                         if (skl_ddb_entry_equal(old, new))
5182                                 continue;
5183
5184                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
5185                                          intel_plane->base.base.id,
5186                                          intel_plane->base.name,
5187                                          old->start, old->end,
5188                                          new->start, new->end);
5189                 }
5190         }
5191 }
5192
5193 static int
5194 skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
5195 {
5196         struct drm_device *dev = state->dev;
5197         const struct drm_i915_private *dev_priv = to_i915(dev);
5198         const struct drm_crtc *crtc;
5199         const struct drm_crtc_state *cstate;
5200         struct intel_crtc *intel_crtc;
5201         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5202         uint32_t realloc_pipes = pipes_modified(state);
5203         int ret, i;
5204
5205         /*
5206          * When we distrust bios wm we always need to recompute to set the
5207          * expected DDB allocations for each CRTC.
5208          */
5209         if (dev_priv->wm.distrust_bios_wm)
5210                 (*changed) = true;
5211
5212         /*
5213          * If this transaction isn't actually touching any CRTC's, don't
5214          * bother with watermark calculation.  Note that if we pass this
5215          * test, we're guaranteed to hold at least one CRTC state mutex,
5216          * which means we can safely use values like dev_priv->active_crtcs
5217          * since any racing commits that want to update them would need to
5218          * hold _all_ CRTC state mutexes.
5219          */
5220         for_each_new_crtc_in_state(state, crtc, cstate, i)
5221                 (*changed) = true;
5222
5223         if (!*changed)
5224                 return 0;
5225
5226         /*
5227          * If this is our first atomic update following hardware readout,
5228          * we can't trust the DDB that the BIOS programmed for us.  Let's
5229          * pretend that all pipes switched active status so that we'll
5230          * ensure a full DDB recompute.
5231          */
5232         if (dev_priv->wm.distrust_bios_wm) {
5233                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
5234                                        state->acquire_ctx);
5235                 if (ret)
5236                         return ret;
5237
5238                 intel_state->active_pipe_changes = ~0;
5239
5240                 /*
5241                  * We usually only initialize intel_state->active_crtcs if we
5242                  * we're doing a modeset; make sure this field is always
5243                  * initialized during the sanitization process that happens
5244                  * on the first commit too.
5245                  */
5246                 if (!intel_state->modeset)
5247                         intel_state->active_crtcs = dev_priv->active_crtcs;
5248         }
5249
5250         /*
5251          * If the modeset changes which CRTC's are active, we need to
5252          * recompute the DDB allocation for *all* active pipes, even
5253          * those that weren't otherwise being modified in any way by this
5254          * atomic commit.  Due to the shrinking of the per-pipe allocations
5255          * when new active CRTC's are added, it's possible for a pipe that
5256          * we were already using and aren't changing at all here to suddenly
5257          * become invalid if its DDB needs exceeds its new allocation.
5258          *
5259          * Note that if we wind up doing a full DDB recompute, we can't let
5260          * any other display updates race with this transaction, so we need
5261          * to grab the lock on *all* CRTC's.
5262          */
5263         if (intel_state->active_pipe_changes) {
5264                 realloc_pipes = ~0;
5265                 intel_state->wm_results.dirty_pipes = ~0;
5266         }
5267
5268         /*
5269          * We're not recomputing for the pipes not included in the commit, so
5270          * make sure we start with the current state.
5271          */
5272         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
5273                 struct intel_crtc_state *cstate;
5274
5275                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
5276                 if (IS_ERR(cstate))
5277                         return PTR_ERR(cstate);
5278         }
5279
5280         return 0;
5281 }
5282
5283 static int
5284 skl_compute_wm(struct drm_atomic_state *state)
5285 {
5286         struct drm_crtc *crtc;
5287         struct drm_crtc_state *cstate;
5288         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5289         struct skl_ddb_values *results = &intel_state->wm_results;
5290         struct skl_pipe_wm *pipe_wm;
5291         bool changed = false;
5292         int ret, i;
5293
5294         /* Clear all dirty flags */
5295         results->dirty_pipes = 0;
5296
5297         ret = skl_ddb_add_affected_pipes(state, &changed);
5298         if (ret || !changed)
5299                 return ret;
5300
5301         ret = skl_compute_ddb(state);
5302         if (ret)
5303                 return ret;
5304
5305         /*
5306          * Calculate WM's for all pipes that are part of this transaction.
5307          * Note that the DDB allocation above may have added more CRTC's that
5308          * weren't otherwise being modified (and set bits in dirty_pipes) if
5309          * pipe allocations had to change.
5310          *
5311          * FIXME:  Now that we're doing this in the atomic check phase, we
5312          * should allow skl_update_pipe_wm() to return failure in cases where
5313          * no suitable watermark values can be found.
5314          */
5315         for_each_new_crtc_in_state(state, crtc, cstate, i) {
5316                 struct intel_crtc_state *intel_cstate =
5317                         to_intel_crtc_state(cstate);
5318                 const struct skl_pipe_wm *old_pipe_wm =
5319                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
5320
5321                 pipe_wm = &intel_cstate->wm.skl.optimal;
5322                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
5323                                          &results->ddb, &changed);
5324                 if (ret)
5325                         return ret;
5326
5327                 if (changed)
5328                         results->dirty_pipes |= drm_crtc_mask(crtc);
5329
5330                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
5331                         /* This pipe's WM's did not change */
5332                         continue;
5333
5334                 intel_cstate->update_wm_pre = true;
5335         }
5336
5337         skl_print_wm_changes(state);
5338
5339         return 0;
5340 }
5341
5342 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
5343                                       struct intel_crtc_state *cstate)
5344 {
5345         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
5346         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5347         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
5348         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
5349         enum pipe pipe = crtc->pipe;
5350         enum plane_id plane_id;
5351
5352         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
5353                 return;
5354
5355         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
5356
5357         for_each_plane_id_on_crtc(crtc, plane_id) {
5358                 if (plane_id != PLANE_CURSOR)
5359                         skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
5360                                            ddb, plane_id);
5361                 else
5362                         skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
5363                                             ddb);
5364         }
5365 }
5366
5367 static void skl_initial_wm(struct intel_atomic_state *state,
5368                            struct intel_crtc_state *cstate)
5369 {
5370         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5371         struct drm_device *dev = intel_crtc->base.dev;
5372         struct drm_i915_private *dev_priv = to_i915(dev);
5373         struct skl_ddb_values *results = &state->wm_results;
5374         struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
5375         enum pipe pipe = intel_crtc->pipe;
5376
5377         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
5378                 return;
5379
5380         mutex_lock(&dev_priv->wm.wm_mutex);
5381
5382         if (cstate->base.active_changed)
5383                 skl_atomic_update_crtc_wm(state, cstate);
5384
5385         skl_copy_ddb_for_pipe(hw_vals, results, pipe);
5386
5387         mutex_unlock(&dev_priv->wm.wm_mutex);
5388 }
5389
5390 static void ilk_compute_wm_config(struct drm_device *dev,
5391                                   struct intel_wm_config *config)
5392 {
5393         struct intel_crtc *crtc;
5394
5395         /* Compute the currently _active_ config */
5396         for_each_intel_crtc(dev, crtc) {
5397                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5398
5399                 if (!wm->pipe_enabled)
5400                         continue;
5401
5402                 config->sprites_enabled |= wm->sprites_enabled;
5403                 config->sprites_scaled |= wm->sprites_scaled;
5404                 config->num_pipes_active++;
5405         }
5406 }
5407
5408 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
5409 {
5410         struct drm_device *dev = &dev_priv->drm;
5411         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
5412         struct ilk_wm_maximums max;
5413         struct intel_wm_config config = {};
5414         struct ilk_wm_values results = {};
5415         enum intel_ddb_partitioning partitioning;
5416
5417         ilk_compute_wm_config(dev, &config);
5418
5419         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
5420         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
5421
5422         /* 5/6 split only in single pipe config on IVB+ */
5423         if (INTEL_GEN(dev_priv) >= 7 &&
5424             config.num_pipes_active == 1 && config.sprites_enabled) {
5425                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
5426                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
5427
5428                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
5429         } else {
5430                 best_lp_wm = &lp_wm_1_2;
5431         }
5432
5433         partitioning = (best_lp_wm == &lp_wm_1_2) ?
5434                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
5435
5436         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
5437
5438         ilk_write_wm_values(dev_priv, &results);
5439 }
5440
5441 static void ilk_initial_watermarks(struct intel_atomic_state *state,
5442                                    struct intel_crtc_state *cstate)
5443 {
5444         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5445         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5446
5447         mutex_lock(&dev_priv->wm.wm_mutex);
5448         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
5449         ilk_program_watermarks(dev_priv);
5450         mutex_unlock(&dev_priv->wm.wm_mutex);
5451 }
5452
5453 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
5454                                     struct intel_crtc_state *cstate)
5455 {
5456         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5457         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5458
5459         mutex_lock(&dev_priv->wm.wm_mutex);
5460         if (cstate->wm.need_postvbl_update) {
5461                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
5462                 ilk_program_watermarks(dev_priv);
5463         }
5464         mutex_unlock(&dev_priv->wm.wm_mutex);
5465 }
5466
5467 static inline void skl_wm_level_from_reg_val(uint32_t val,
5468                                              struct skl_wm_level *level)
5469 {
5470         level->plane_en = val & PLANE_WM_EN;
5471         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5472         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5473                 PLANE_WM_LINES_MASK;
5474 }
5475
5476 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
5477                               struct skl_pipe_wm *out)
5478 {
5479         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5481         enum pipe pipe = intel_crtc->pipe;
5482         int level, max_level;
5483         enum plane_id plane_id;
5484         uint32_t val;
5485
5486         max_level = ilk_wm_max_level(dev_priv);
5487
5488         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
5489                 struct skl_plane_wm *wm = &out->planes[plane_id];
5490
5491                 for (level = 0; level <= max_level; level++) {
5492                         if (plane_id != PLANE_CURSOR)
5493                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
5494                         else
5495                                 val = I915_READ(CUR_WM(pipe, level));
5496
5497                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
5498                 }
5499
5500                 if (plane_id != PLANE_CURSOR)
5501                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5502                 else
5503                         val = I915_READ(CUR_WM_TRANS(pipe));
5504
5505                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5506         }
5507
5508         if (!intel_crtc->active)
5509                 return;
5510
5511         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
5512 }
5513
5514 void skl_wm_get_hw_state(struct drm_device *dev)
5515 {
5516         struct drm_i915_private *dev_priv = to_i915(dev);
5517         struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
5518         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
5519         struct drm_crtc *crtc;
5520         struct intel_crtc *intel_crtc;
5521         struct intel_crtc_state *cstate;
5522
5523         skl_ddb_get_hw_state(dev_priv, ddb);
5524         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5525                 intel_crtc = to_intel_crtc(crtc);
5526                 cstate = to_intel_crtc_state(crtc->state);
5527
5528                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
5529
5530                 if (intel_crtc->active)
5531                         hw->dirty_pipes |= drm_crtc_mask(crtc);
5532         }
5533
5534         if (dev_priv->active_crtcs) {
5535                 /* Fully recompute DDB on first atomic commit */
5536                 dev_priv->wm.distrust_bios_wm = true;
5537         } else {
5538                 /*
5539                  * Easy/common case; just sanitize DDB now if everything off
5540                  * Keep dbuf slice info intact
5541                  */
5542                 memset(ddb->plane, 0, sizeof(ddb->plane));
5543                 memset(ddb->uv_plane, 0, sizeof(ddb->uv_plane));
5544         }
5545 }
5546
5547 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
5548 {
5549         struct drm_device *dev = crtc->dev;
5550         struct drm_i915_private *dev_priv = to_i915(dev);
5551         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5553         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
5554         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
5555         enum pipe pipe = intel_crtc->pipe;
5556         static const i915_reg_t wm0_pipe_reg[] = {
5557                 [PIPE_A] = WM0_PIPEA_ILK,
5558                 [PIPE_B] = WM0_PIPEB_ILK,
5559                 [PIPE_C] = WM0_PIPEC_IVB,
5560         };
5561
5562         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
5563         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5564                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
5565
5566         memset(active, 0, sizeof(*active));
5567
5568         active->pipe_enabled = intel_crtc->active;
5569
5570         if (active->pipe_enabled) {
5571                 u32 tmp = hw->wm_pipe[pipe];
5572
5573                 /*
5574                  * For active pipes LP0 watermark is marked as
5575                  * enabled, and LP1+ watermaks as disabled since
5576                  * we can't really reverse compute them in case
5577                  * multiple pipes are active.
5578                  */
5579                 active->wm[0].enable = true;
5580                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
5581                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
5582                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
5583                 active->linetime = hw->wm_linetime[pipe];
5584         } else {
5585                 int level, max_level = ilk_wm_max_level(dev_priv);
5586
5587                 /*
5588                  * For inactive pipes, all watermark levels
5589                  * should be marked as enabled but zeroed,
5590                  * which is what we'd compute them to.
5591                  */
5592                 for (level = 0; level <= max_level; level++)
5593                         active->wm[level].enable = true;
5594         }
5595
5596         intel_crtc->wm.active.ilk = *active;
5597 }
5598
5599 #define _FW_WM(value, plane) \
5600         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5601 #define _FW_WM_VLV(value, plane) \
5602         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5603
5604 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
5605                                struct g4x_wm_values *wm)
5606 {
5607         uint32_t tmp;
5608
5609         tmp = I915_READ(DSPFW1);
5610         wm->sr.plane = _FW_WM(tmp, SR);
5611         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5612         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
5613         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
5614
5615         tmp = I915_READ(DSPFW2);
5616         wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
5617         wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5618         wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5619         wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
5620         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5621         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
5622
5623         tmp = I915_READ(DSPFW3);
5624         wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
5625         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5626         wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5627         wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5628 }
5629
5630 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
5631                                struct vlv_wm_values *wm)
5632 {
5633         enum pipe pipe;
5634         uint32_t tmp;
5635
5636         for_each_pipe(dev_priv, pipe) {
5637                 tmp = I915_READ(VLV_DDL(pipe));
5638
5639                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
5640                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5641                 wm->ddl[pipe].plane[PLANE_CURSOR] =
5642                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5643                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
5644                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5645                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
5646                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5647         }
5648
5649         tmp = I915_READ(DSPFW1);
5650         wm->sr.plane = _FW_WM(tmp, SR);
5651         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5652         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
5653         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
5654
5655         tmp = I915_READ(DSPFW2);
5656         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
5657         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5658         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
5659
5660         tmp = I915_READ(DSPFW3);
5661         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5662
5663         if (IS_CHERRYVIEW(dev_priv)) {
5664                 tmp = I915_READ(DSPFW7_CHV);
5665                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5666                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5667
5668                 tmp = I915_READ(DSPFW8_CHV);
5669                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
5670                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
5671
5672                 tmp = I915_READ(DSPFW9_CHV);
5673                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
5674                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
5675
5676                 tmp = I915_READ(DSPHOWM);
5677                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5678                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
5679                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
5680                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
5681                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5682                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5683                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5684                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5685                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5686                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5687         } else {
5688                 tmp = I915_READ(DSPFW7);
5689                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5690                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5691
5692                 tmp = I915_READ(DSPHOWM);
5693                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5694                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5695                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5696                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5697                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5698                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5699                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5700         }
5701 }
5702
5703 #undef _FW_WM
5704 #undef _FW_WM_VLV
5705
5706 void g4x_wm_get_hw_state(struct drm_device *dev)
5707 {
5708         struct drm_i915_private *dev_priv = to_i915(dev);
5709         struct g4x_wm_values *wm = &dev_priv->wm.g4x;
5710         struct intel_crtc *crtc;
5711
5712         g4x_read_wm_values(dev_priv, wm);
5713
5714         wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5715
5716         for_each_intel_crtc(dev, crtc) {
5717                 struct intel_crtc_state *crtc_state =
5718                         to_intel_crtc_state(crtc->base.state);
5719                 struct g4x_wm_state *active = &crtc->wm.active.g4x;
5720                 struct g4x_pipe_wm *raw;
5721                 enum pipe pipe = crtc->pipe;
5722                 enum plane_id plane_id;
5723                 int level, max_level;
5724
5725                 active->cxsr = wm->cxsr;
5726                 active->hpll_en = wm->hpll_en;
5727                 active->fbc_en = wm->fbc_en;
5728
5729                 active->sr = wm->sr;
5730                 active->hpll = wm->hpll;
5731
5732                 for_each_plane_id_on_crtc(crtc, plane_id) {
5733                         active->wm.plane[plane_id] =
5734                                 wm->pipe[pipe].plane[plane_id];
5735                 }
5736
5737                 if (wm->cxsr && wm->hpll_en)
5738                         max_level = G4X_WM_LEVEL_HPLL;
5739                 else if (wm->cxsr)
5740                         max_level = G4X_WM_LEVEL_SR;
5741                 else
5742                         max_level = G4X_WM_LEVEL_NORMAL;
5743
5744                 level = G4X_WM_LEVEL_NORMAL;
5745                 raw = &crtc_state->wm.g4x.raw[level];
5746                 for_each_plane_id_on_crtc(crtc, plane_id)
5747                         raw->plane[plane_id] = active->wm.plane[plane_id];
5748
5749                 if (++level > max_level)
5750                         goto out;
5751
5752                 raw = &crtc_state->wm.g4x.raw[level];
5753                 raw->plane[PLANE_PRIMARY] = active->sr.plane;
5754                 raw->plane[PLANE_CURSOR] = active->sr.cursor;
5755                 raw->plane[PLANE_SPRITE0] = 0;
5756                 raw->fbc = active->sr.fbc;
5757
5758                 if (++level > max_level)
5759                         goto out;
5760
5761                 raw = &crtc_state->wm.g4x.raw[level];
5762                 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
5763                 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
5764                 raw->plane[PLANE_SPRITE0] = 0;
5765                 raw->fbc = active->hpll.fbc;
5766
5767         out:
5768                 for_each_plane_id_on_crtc(crtc, plane_id)
5769                         g4x_raw_plane_wm_set(crtc_state, level,
5770                                              plane_id, USHRT_MAX);
5771                 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
5772
5773                 crtc_state->wm.g4x.optimal = *active;
5774                 crtc_state->wm.g4x.intermediate = *active;
5775
5776                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5777                               pipe_name(pipe),
5778                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5779                               wm->pipe[pipe].plane[PLANE_CURSOR],
5780                               wm->pipe[pipe].plane[PLANE_SPRITE0]);
5781         }
5782
5783         DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5784                       wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
5785         DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5786                       wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
5787         DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5788                       yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
5789 }
5790
5791 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
5792 {
5793         struct intel_plane *plane;
5794         struct intel_crtc *crtc;
5795
5796         mutex_lock(&dev_priv->wm.wm_mutex);
5797
5798         for_each_intel_plane(&dev_priv->drm, plane) {
5799                 struct intel_crtc *crtc =
5800                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5801                 struct intel_crtc_state *crtc_state =
5802                         to_intel_crtc_state(crtc->base.state);
5803                 struct intel_plane_state *plane_state =
5804                         to_intel_plane_state(plane->base.state);
5805                 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
5806                 enum plane_id plane_id = plane->id;
5807                 int level;
5808
5809                 if (plane_state->base.visible)
5810                         continue;
5811
5812                 for (level = 0; level < 3; level++) {
5813                         struct g4x_pipe_wm *raw =
5814                                 &crtc_state->wm.g4x.raw[level];
5815
5816                         raw->plane[plane_id] = 0;
5817                         wm_state->wm.plane[plane_id] = 0;
5818                 }
5819
5820                 if (plane_id == PLANE_PRIMARY) {
5821                         for (level = 0; level < 3; level++) {
5822                                 struct g4x_pipe_wm *raw =
5823                                         &crtc_state->wm.g4x.raw[level];
5824                                 raw->fbc = 0;
5825                         }
5826
5827                         wm_state->sr.fbc = 0;
5828                         wm_state->hpll.fbc = 0;
5829                         wm_state->fbc_en = false;
5830                 }
5831         }
5832
5833         for_each_intel_crtc(&dev_priv->drm, crtc) {
5834                 struct intel_crtc_state *crtc_state =
5835                         to_intel_crtc_state(crtc->base.state);
5836
5837                 crtc_state->wm.g4x.intermediate =
5838                         crtc_state->wm.g4x.optimal;
5839                 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
5840         }
5841
5842         g4x_program_watermarks(dev_priv);
5843
5844         mutex_unlock(&dev_priv->wm.wm_mutex);
5845 }
5846
5847 void vlv_wm_get_hw_state(struct drm_device *dev)
5848 {
5849         struct drm_i915_private *dev_priv = to_i915(dev);
5850         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
5851         struct intel_crtc *crtc;
5852         u32 val;
5853
5854         vlv_read_wm_values(dev_priv, wm);
5855
5856         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
5857         wm->level = VLV_WM_LEVEL_PM2;
5858
5859         if (IS_CHERRYVIEW(dev_priv)) {
5860                 mutex_lock(&dev_priv->pcu_lock);
5861
5862                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5863                 if (val & DSP_MAXFIFO_PM5_ENABLE)
5864                         wm->level = VLV_WM_LEVEL_PM5;
5865
5866                 /*
5867                  * If DDR DVFS is disabled in the BIOS, Punit
5868                  * will never ack the request. So if that happens
5869                  * assume we don't have to enable/disable DDR DVFS
5870                  * dynamically. To test that just set the REQ_ACK
5871                  * bit to poke the Punit, but don't change the
5872                  * HIGH/LOW bits so that we don't actually change
5873                  * the current state.
5874                  */
5875                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5876                 val |= FORCE_DDR_FREQ_REQ_ACK;
5877                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
5878
5879                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
5880                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
5881                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5882                                       "assuming DDR DVFS is disabled\n");
5883                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
5884                 } else {
5885                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5886                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
5887                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
5888                 }
5889
5890                 mutex_unlock(&dev_priv->pcu_lock);
5891         }
5892
5893         for_each_intel_crtc(dev, crtc) {
5894                 struct intel_crtc_state *crtc_state =
5895                         to_intel_crtc_state(crtc->base.state);
5896                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
5897                 const struct vlv_fifo_state *fifo_state =
5898                         &crtc_state->wm.vlv.fifo_state;
5899                 enum pipe pipe = crtc->pipe;
5900                 enum plane_id plane_id;
5901                 int level;
5902
5903                 vlv_get_fifo_size(crtc_state);
5904
5905                 active->num_levels = wm->level + 1;
5906                 active->cxsr = wm->cxsr;
5907
5908                 for (level = 0; level < active->num_levels; level++) {
5909                         struct g4x_pipe_wm *raw =
5910                                 &crtc_state->wm.vlv.raw[level];
5911
5912                         active->sr[level].plane = wm->sr.plane;
5913                         active->sr[level].cursor = wm->sr.cursor;
5914
5915                         for_each_plane_id_on_crtc(crtc, plane_id) {
5916                                 active->wm[level].plane[plane_id] =
5917                                         wm->pipe[pipe].plane[plane_id];
5918
5919                                 raw->plane[plane_id] =
5920                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
5921                                                             fifo_state->plane[plane_id]);
5922                         }
5923                 }
5924
5925                 for_each_plane_id_on_crtc(crtc, plane_id)
5926                         vlv_raw_plane_wm_set(crtc_state, level,
5927                                              plane_id, USHRT_MAX);
5928                 vlv_invalidate_wms(crtc, active, level);
5929
5930                 crtc_state->wm.vlv.optimal = *active;
5931                 crtc_state->wm.vlv.intermediate = *active;
5932
5933                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5934                               pipe_name(pipe),
5935                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5936                               wm->pipe[pipe].plane[PLANE_CURSOR],
5937                               wm->pipe[pipe].plane[PLANE_SPRITE0],
5938                               wm->pipe[pipe].plane[PLANE_SPRITE1]);
5939         }
5940
5941         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5942                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
5943 }
5944
5945 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
5946 {
5947         struct intel_plane *plane;
5948         struct intel_crtc *crtc;
5949
5950         mutex_lock(&dev_priv->wm.wm_mutex);
5951
5952         for_each_intel_plane(&dev_priv->drm, plane) {
5953                 struct intel_crtc *crtc =
5954                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5955                 struct intel_crtc_state *crtc_state =
5956                         to_intel_crtc_state(crtc->base.state);
5957                 struct intel_plane_state *plane_state =
5958                         to_intel_plane_state(plane->base.state);
5959                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
5960                 const struct vlv_fifo_state *fifo_state =
5961                         &crtc_state->wm.vlv.fifo_state;
5962                 enum plane_id plane_id = plane->id;
5963                 int level;
5964
5965                 if (plane_state->base.visible)
5966                         continue;
5967
5968                 for (level = 0; level < wm_state->num_levels; level++) {
5969                         struct g4x_pipe_wm *raw =
5970                                 &crtc_state->wm.vlv.raw[level];
5971
5972                         raw->plane[plane_id] = 0;
5973
5974                         wm_state->wm[level].plane[plane_id] =
5975                                 vlv_invert_wm_value(raw->plane[plane_id],
5976                                                     fifo_state->plane[plane_id]);
5977                 }
5978         }
5979
5980         for_each_intel_crtc(&dev_priv->drm, crtc) {
5981                 struct intel_crtc_state *crtc_state =
5982                         to_intel_crtc_state(crtc->base.state);
5983
5984                 crtc_state->wm.vlv.intermediate =
5985                         crtc_state->wm.vlv.optimal;
5986                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
5987         }
5988
5989         vlv_program_watermarks(dev_priv);
5990
5991         mutex_unlock(&dev_priv->wm.wm_mutex);
5992 }
5993
5994 /*
5995  * FIXME should probably kill this and improve
5996  * the real watermark readout/sanitation instead
5997  */
5998 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
5999 {
6000         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6001         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6002         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6003
6004         /*
6005          * Don't touch WM1S_LP_EN here.
6006          * Doing so could cause underruns.
6007          */
6008 }
6009
6010 void ilk_wm_get_hw_state(struct drm_device *dev)
6011 {
6012         struct drm_i915_private *dev_priv = to_i915(dev);
6013         struct ilk_wm_values *hw = &dev_priv->wm.hw;
6014         struct drm_crtc *crtc;
6015
6016         ilk_init_lp_watermarks(dev_priv);
6017
6018         for_each_crtc(dev, crtc)
6019                 ilk_pipe_wm_get_hw_state(crtc);
6020
6021         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
6022         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
6023         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
6024
6025         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
6026         if (INTEL_GEN(dev_priv) >= 7) {
6027                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
6028                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
6029         }
6030
6031         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6032                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
6033                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6034         else if (IS_IVYBRIDGE(dev_priv))
6035                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
6036                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6037
6038         hw->enable_fbc_wm =
6039                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
6040 }
6041
6042 /**
6043  * intel_update_watermarks - update FIFO watermark values based on current modes
6044  * @crtc: the #intel_crtc on which to compute the WM
6045  *
6046  * Calculate watermark values for the various WM regs based on current mode
6047  * and plane configuration.
6048  *
6049  * There are several cases to deal with here:
6050  *   - normal (i.e. non-self-refresh)
6051  *   - self-refresh (SR) mode
6052  *   - lines are large relative to FIFO size (buffer can hold up to 2)
6053  *   - lines are small relative to FIFO size (buffer can hold more than 2
6054  *     lines), so need to account for TLB latency
6055  *
6056  *   The normal calculation is:
6057  *     watermark = dotclock * bytes per pixel * latency
6058  *   where latency is platform & configuration dependent (we assume pessimal
6059  *   values here).
6060  *
6061  *   The SR calculation is:
6062  *     watermark = (trunc(latency/line time)+1) * surface width *
6063  *       bytes per pixel
6064  *   where
6065  *     line time = htotal / dotclock
6066  *     surface width = hdisplay for normal plane and 64 for cursor
6067  *   and latency is assumed to be high, as above.
6068  *
6069  * The final value programmed to the register should always be rounded up,
6070  * and include an extra 2 entries to account for clock crossings.
6071  *
6072  * We don't use the sprite, so we can ignore that.  And on Crestline we have
6073  * to set the non-SR watermarks to 8.
6074  */
6075 void intel_update_watermarks(struct intel_crtc *crtc)
6076 {
6077         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6078
6079         if (dev_priv->display.update_wm)
6080                 dev_priv->display.update_wm(crtc);
6081 }
6082
6083 void intel_enable_ipc(struct drm_i915_private *dev_priv)
6084 {
6085         u32 val;
6086
6087         /* Display WA #0477 WaDisableIPC: skl */
6088         if (IS_SKYLAKE(dev_priv)) {
6089                 dev_priv->ipc_enabled = false;
6090                 return;
6091         }
6092
6093         val = I915_READ(DISP_ARB_CTL2);
6094
6095         if (dev_priv->ipc_enabled)
6096                 val |= DISP_IPC_ENABLE;
6097         else
6098                 val &= ~DISP_IPC_ENABLE;
6099
6100         I915_WRITE(DISP_ARB_CTL2, val);
6101 }
6102
6103 void intel_init_ipc(struct drm_i915_private *dev_priv)
6104 {
6105         dev_priv->ipc_enabled = false;
6106         if (!HAS_IPC(dev_priv))
6107                 return;
6108
6109         dev_priv->ipc_enabled = true;
6110         intel_enable_ipc(dev_priv);
6111 }
6112
6113 /*
6114  * Lock protecting IPS related data structures
6115  */
6116 DEFINE_SPINLOCK(mchdev_lock);
6117
6118 /* Global for IPS driver to get at the current i915 device. Protected by
6119  * mchdev_lock. */
6120 static struct drm_i915_private *i915_mch_dev;
6121
6122 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
6123 {
6124         u16 rgvswctl;
6125
6126         lockdep_assert_held(&mchdev_lock);
6127
6128         rgvswctl = I915_READ16(MEMSWCTL);
6129         if (rgvswctl & MEMCTL_CMD_STS) {
6130                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6131                 return false; /* still busy with another command */
6132         }
6133
6134         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6135                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6136         I915_WRITE16(MEMSWCTL, rgvswctl);
6137         POSTING_READ16(MEMSWCTL);
6138
6139         rgvswctl |= MEMCTL_CMD_STS;
6140         I915_WRITE16(MEMSWCTL, rgvswctl);
6141
6142         return true;
6143 }
6144
6145 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
6146 {
6147         u32 rgvmodectl;
6148         u8 fmax, fmin, fstart, vstart;
6149
6150         spin_lock_irq(&mchdev_lock);
6151
6152         rgvmodectl = I915_READ(MEMMODECTL);
6153
6154         /* Enable temp reporting */
6155         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6156         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6157
6158         /* 100ms RC evaluation intervals */
6159         I915_WRITE(RCUPEI, 100000);
6160         I915_WRITE(RCDNEI, 100000);
6161
6162         /* Set max/min thresholds to 90ms and 80ms respectively */
6163         I915_WRITE(RCBMAXAVG, 90000);
6164         I915_WRITE(RCBMINAVG, 80000);
6165
6166         I915_WRITE(MEMIHYST, 1);
6167
6168         /* Set up min, max, and cur for interrupt handling */
6169         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6170         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6171         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6172                 MEMMODE_FSTART_SHIFT;
6173
6174         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
6175                 PXVFREQ_PX_SHIFT;
6176
6177         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
6178         dev_priv->ips.fstart = fstart;
6179
6180         dev_priv->ips.max_delay = fstart;
6181         dev_priv->ips.min_delay = fmin;
6182         dev_priv->ips.cur_delay = fstart;
6183
6184         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6185                          fmax, fmin, fstart);
6186
6187         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6188
6189         /*
6190          * Interrupts will be enabled in ironlake_irq_postinstall
6191          */
6192
6193         I915_WRITE(VIDSTART, vstart);
6194         POSTING_READ(VIDSTART);
6195
6196         rgvmodectl |= MEMMODE_SWMODE_EN;
6197         I915_WRITE(MEMMODECTL, rgvmodectl);
6198
6199         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6200                 DRM_ERROR("stuck trying to change perf mode\n");
6201         mdelay(1);
6202
6203         ironlake_set_drps(dev_priv, fstart);
6204
6205         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
6206                 I915_READ(DDREC) + I915_READ(CSIEC);
6207         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
6208         dev_priv->ips.last_count2 = I915_READ(GFXEC);
6209         dev_priv->ips.last_time2 = ktime_get_raw_ns();
6210
6211         spin_unlock_irq(&mchdev_lock);
6212 }
6213
6214 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
6215 {
6216         u16 rgvswctl;
6217
6218         spin_lock_irq(&mchdev_lock);
6219
6220         rgvswctl = I915_READ16(MEMSWCTL);
6221
6222         /* Ack interrupts, disable EFC interrupt */
6223         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6224         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6225         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6226         I915_WRITE(DEIIR, DE_PCU_EVENT);
6227         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6228
6229         /* Go back to the starting frequency */
6230         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
6231         mdelay(1);
6232         rgvswctl |= MEMCTL_CMD_STS;
6233         I915_WRITE(MEMSWCTL, rgvswctl);
6234         mdelay(1);
6235
6236         spin_unlock_irq(&mchdev_lock);
6237 }
6238
6239 /* There's a funny hw issue where the hw returns all 0 when reading from
6240  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
6241  * ourselves, instead of doing a rmw cycle (which might result in us clearing
6242  * all limits and the gpu stuck at whatever frequency it is at atm).
6243  */
6244 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
6245 {
6246         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6247         u32 limits;
6248
6249         /* Only set the down limit when we've reached the lowest level to avoid
6250          * getting more interrupts, otherwise leave this clear. This prevents a
6251          * race in the hw when coming out of rc6: There's a tiny window where
6252          * the hw runs at the minimal clock before selecting the desired
6253          * frequency, if the down threshold expires in that window we will not
6254          * receive a down interrupt. */
6255         if (INTEL_GEN(dev_priv) >= 9) {
6256                 limits = (rps->max_freq_softlimit) << 23;
6257                 if (val <= rps->min_freq_softlimit)
6258                         limits |= (rps->min_freq_softlimit) << 14;
6259         } else {
6260                 limits = rps->max_freq_softlimit << 24;
6261                 if (val <= rps->min_freq_softlimit)
6262                         limits |= rps->min_freq_softlimit << 16;
6263         }
6264
6265         return limits;
6266 }
6267
6268 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
6269 {
6270         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6271         int new_power;
6272         u32 threshold_up = 0, threshold_down = 0; /* in % */
6273         u32 ei_up = 0, ei_down = 0;
6274
6275         new_power = rps->power;
6276         switch (rps->power) {
6277         case LOW_POWER:
6278                 if (val > rps->efficient_freq + 1 &&
6279                     val > rps->cur_freq)
6280                         new_power = BETWEEN;
6281                 break;
6282
6283         case BETWEEN:
6284                 if (val <= rps->efficient_freq &&
6285                     val < rps->cur_freq)
6286                         new_power = LOW_POWER;
6287                 else if (val >= rps->rp0_freq &&
6288                          val > rps->cur_freq)
6289                         new_power = HIGH_POWER;
6290                 break;
6291
6292         case HIGH_POWER:
6293                 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
6294                     val < rps->cur_freq)
6295                         new_power = BETWEEN;
6296                 break;
6297         }
6298         /* Max/min bins are special */
6299         if (val <= rps->min_freq_softlimit)
6300                 new_power = LOW_POWER;
6301         if (val >= rps->max_freq_softlimit)
6302                 new_power = HIGH_POWER;
6303         if (new_power == rps->power)
6304                 return;
6305
6306         /* Note the units here are not exactly 1us, but 1280ns. */
6307         switch (new_power) {
6308         case LOW_POWER:
6309                 /* Upclock if more than 95% busy over 16ms */
6310                 ei_up = 16000;
6311                 threshold_up = 95;
6312
6313                 /* Downclock if less than 85% busy over 32ms */
6314                 ei_down = 32000;
6315                 threshold_down = 85;
6316                 break;
6317
6318         case BETWEEN:
6319                 /* Upclock if more than 90% busy over 13ms */
6320                 ei_up = 13000;
6321                 threshold_up = 90;
6322
6323                 /* Downclock if less than 75% busy over 32ms */
6324                 ei_down = 32000;
6325                 threshold_down = 75;
6326                 break;
6327
6328         case HIGH_POWER:
6329                 /* Upclock if more than 85% busy over 10ms */
6330                 ei_up = 10000;
6331                 threshold_up = 85;
6332
6333                 /* Downclock if less than 60% busy over 32ms */
6334                 ei_down = 32000;
6335                 threshold_down = 60;
6336                 break;
6337         }
6338
6339         /* When byt can survive without system hang with dynamic
6340          * sw freq adjustments, this restriction can be lifted.
6341          */
6342         if (IS_VALLEYVIEW(dev_priv))
6343                 goto skip_hw_write;
6344
6345         I915_WRITE(GEN6_RP_UP_EI,
6346                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
6347         I915_WRITE(GEN6_RP_UP_THRESHOLD,
6348                    GT_INTERVAL_FROM_US(dev_priv,
6349                                        ei_up * threshold_up / 100));
6350
6351         I915_WRITE(GEN6_RP_DOWN_EI,
6352                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
6353         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
6354                    GT_INTERVAL_FROM_US(dev_priv,
6355                                        ei_down * threshold_down / 100));
6356
6357         I915_WRITE(GEN6_RP_CONTROL,
6358                    GEN6_RP_MEDIA_TURBO |
6359                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6360                    GEN6_RP_MEDIA_IS_GFX |
6361                    GEN6_RP_ENABLE |
6362                    GEN6_RP_UP_BUSY_AVG |
6363                    GEN6_RP_DOWN_IDLE_AVG);
6364
6365 skip_hw_write:
6366         rps->power = new_power;
6367         rps->up_threshold = threshold_up;
6368         rps->down_threshold = threshold_down;
6369         rps->last_adj = 0;
6370 }
6371
6372 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
6373 {
6374         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6375         u32 mask = 0;
6376
6377         /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6378         if (val > rps->min_freq_softlimit)
6379                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
6380         if (val < rps->max_freq_softlimit)
6381                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
6382
6383         mask &= dev_priv->pm_rps_events;
6384
6385         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
6386 }
6387
6388 /* gen6_set_rps is called to update the frequency request, but should also be
6389  * called when the range (min_delay and max_delay) is modified so that we can
6390  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6391 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
6392 {
6393         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6394
6395         /* min/max delay may still have been modified so be sure to
6396          * write the limits value.
6397          */
6398         if (val != rps->cur_freq) {
6399                 gen6_set_rps_thresholds(dev_priv, val);
6400
6401                 if (INTEL_GEN(dev_priv) >= 9)
6402                         I915_WRITE(GEN6_RPNSWREQ,
6403                                    GEN9_FREQUENCY(val));
6404                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6405                         I915_WRITE(GEN6_RPNSWREQ,
6406                                    HSW_FREQUENCY(val));
6407                 else
6408                         I915_WRITE(GEN6_RPNSWREQ,
6409                                    GEN6_FREQUENCY(val) |
6410                                    GEN6_OFFSET(0) |
6411                                    GEN6_AGGRESSIVE_TURBO);
6412         }
6413
6414         /* Make sure we continue to get interrupts
6415          * until we hit the minimum or maximum frequencies.
6416          */
6417         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
6418         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6419
6420         rps->cur_freq = val;
6421         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6422
6423         return 0;
6424 }
6425
6426 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
6427 {
6428         int err;
6429
6430         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
6431                       "Odd GPU freq value\n"))
6432                 val &= ~1;
6433
6434         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6435
6436         if (val != dev_priv->gt_pm.rps.cur_freq) {
6437                 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
6438                 if (err)
6439                         return err;
6440
6441                 gen6_set_rps_thresholds(dev_priv, val);
6442         }
6443
6444         dev_priv->gt_pm.rps.cur_freq = val;
6445         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6446
6447         return 0;
6448 }
6449
6450 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6451  *
6452  * * If Gfx is Idle, then
6453  * 1. Forcewake Media well.
6454  * 2. Request idle freq.
6455  * 3. Release Forcewake of Media well.
6456 */
6457 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
6458 {
6459         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6460         u32 val = rps->idle_freq;
6461         int err;
6462
6463         if (rps->cur_freq <= val)
6464                 return;
6465
6466         /* The punit delays the write of the frequency and voltage until it
6467          * determines the GPU is awake. During normal usage we don't want to
6468          * waste power changing the frequency if the GPU is sleeping (rc6).
6469          * However, the GPU and driver is now idle and we do not want to delay
6470          * switching to minimum voltage (reducing power whilst idle) as we do
6471          * not expect to be woken in the near future and so must flush the
6472          * change by waking the device.
6473          *
6474          * We choose to take the media powerwell (either would do to trick the
6475          * punit into committing the voltage change) as that takes a lot less
6476          * power than the render powerwell.
6477          */
6478         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
6479         err = valleyview_set_rps(dev_priv, val);
6480         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
6481
6482         if (err)
6483                 DRM_ERROR("Failed to set RPS for idle\n");
6484 }
6485
6486 void gen6_rps_busy(struct drm_i915_private *dev_priv)
6487 {
6488         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6489
6490         mutex_lock(&dev_priv->pcu_lock);
6491         if (rps->enabled) {
6492                 u8 freq;
6493
6494                 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
6495                         gen6_rps_reset_ei(dev_priv);
6496                 I915_WRITE(GEN6_PMINTRMSK,
6497                            gen6_rps_pm_mask(dev_priv, rps->cur_freq));
6498
6499                 gen6_enable_rps_interrupts(dev_priv);
6500
6501                 /* Use the user's desired frequency as a guide, but for better
6502                  * performance, jump directly to RPe as our starting frequency.
6503                  */
6504                 freq = max(rps->cur_freq,
6505                            rps->efficient_freq);
6506
6507                 if (intel_set_rps(dev_priv,
6508                                   clamp(freq,
6509                                         rps->min_freq_softlimit,
6510                                         rps->max_freq_softlimit)))
6511                         DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6512         }
6513         mutex_unlock(&dev_priv->pcu_lock);
6514 }
6515
6516 void gen6_rps_idle(struct drm_i915_private *dev_priv)
6517 {
6518         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6519
6520         /* Flush our bottom-half so that it does not race with us
6521          * setting the idle frequency and so that it is bounded by
6522          * our rpm wakeref. And then disable the interrupts to stop any
6523          * futher RPS reclocking whilst we are asleep.
6524          */
6525         gen6_disable_rps_interrupts(dev_priv);
6526
6527         mutex_lock(&dev_priv->pcu_lock);
6528         if (rps->enabled) {
6529                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6530                         vlv_set_rps_idle(dev_priv);
6531                 else
6532                         gen6_set_rps(dev_priv, rps->idle_freq);
6533                 rps->last_adj = 0;
6534                 I915_WRITE(GEN6_PMINTRMSK,
6535                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
6536         }
6537         mutex_unlock(&dev_priv->pcu_lock);
6538 }
6539
6540 void gen6_rps_boost(struct i915_request *rq,
6541                     struct intel_rps_client *rps_client)
6542 {
6543         struct intel_rps *rps = &rq->i915->gt_pm.rps;
6544         unsigned long flags;
6545         bool boost;
6546
6547         /* This is intentionally racy! We peek at the state here, then
6548          * validate inside the RPS worker.
6549          */
6550         if (!rps->enabled)
6551                 return;
6552
6553         if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
6554                 return;
6555
6556         /* Serializes with i915_request_retire() */
6557         boost = false;
6558         spin_lock_irqsave(&rq->lock, flags);
6559         if (!rq->waitboost && !dma_fence_is_signaled_locked(&rq->fence)) {
6560                 boost = !atomic_fetch_inc(&rps->num_waiters);
6561                 rq->waitboost = true;
6562         }
6563         spin_unlock_irqrestore(&rq->lock, flags);
6564         if (!boost)
6565                 return;
6566
6567         if (READ_ONCE(rps->cur_freq) < rps->boost_freq)
6568                 schedule_work(&rps->work);
6569
6570         atomic_inc(rps_client ? &rps_client->boosts : &rps->boosts);
6571 }
6572
6573 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
6574 {
6575         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6576         int err;
6577
6578         lockdep_assert_held(&dev_priv->pcu_lock);
6579         GEM_BUG_ON(val > rps->max_freq);
6580         GEM_BUG_ON(val < rps->min_freq);
6581
6582         if (!rps->enabled) {
6583                 rps->cur_freq = val;
6584                 return 0;
6585         }
6586
6587         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6588                 err = valleyview_set_rps(dev_priv, val);
6589         else
6590                 err = gen6_set_rps(dev_priv, val);
6591
6592         return err;
6593 }
6594
6595 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
6596 {
6597         I915_WRITE(GEN6_RC_CONTROL, 0);
6598         I915_WRITE(GEN9_PG_ENABLE, 0);
6599 }
6600
6601 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
6602 {
6603         I915_WRITE(GEN6_RP_CONTROL, 0);
6604 }
6605
6606 static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
6607 {
6608         I915_WRITE(GEN6_RC_CONTROL, 0);
6609 }
6610
6611 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
6612 {
6613         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6614         I915_WRITE(GEN6_RP_CONTROL, 0);
6615 }
6616
6617 static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
6618 {
6619         I915_WRITE(GEN6_RC_CONTROL, 0);
6620 }
6621
6622 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
6623 {
6624         I915_WRITE(GEN6_RP_CONTROL, 0);
6625 }
6626
6627 static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
6628 {
6629         /* We're doing forcewake before Disabling RC6,
6630          * This what the BIOS expects when going into suspend */
6631         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6632
6633         I915_WRITE(GEN6_RC_CONTROL, 0);
6634
6635         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6636 }
6637
6638 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
6639 {
6640         I915_WRITE(GEN6_RP_CONTROL, 0);
6641 }
6642
6643 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
6644 {
6645         bool enable_rc6 = true;
6646         unsigned long rc6_ctx_base;
6647         u32 rc_ctl;
6648         int rc_sw_target;
6649
6650         rc_ctl = I915_READ(GEN6_RC_CONTROL);
6651         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
6652                        RC_SW_TARGET_STATE_SHIFT;
6653         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6654                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6655                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
6656                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
6657                          rc_sw_target);
6658
6659         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
6660                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6661                 enable_rc6 = false;
6662         }
6663
6664         /*
6665          * The exact context size is not known for BXT, so assume a page size
6666          * for this check.
6667          */
6668         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
6669         if (!((rc6_ctx_base >= dev_priv->dsm_reserved.start) &&
6670               (rc6_ctx_base + PAGE_SIZE < dev_priv->dsm_reserved.end))) {
6671                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6672                 enable_rc6 = false;
6673         }
6674
6675         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
6676               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
6677               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
6678               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
6679                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6680                 enable_rc6 = false;
6681         }
6682
6683         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
6684             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
6685             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
6686                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6687                 enable_rc6 = false;
6688         }
6689
6690         if (!I915_READ(GEN6_GFXPAUSE)) {
6691                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6692                 enable_rc6 = false;
6693         }
6694
6695         if (!I915_READ(GEN8_MISC_CTRL0)) {
6696                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6697                 enable_rc6 = false;
6698         }
6699
6700         return enable_rc6;
6701 }
6702
6703 static bool sanitize_rc6(struct drm_i915_private *i915)
6704 {
6705         struct intel_device_info *info = mkwrite_device_info(i915);
6706
6707         /* Powersaving is controlled by the host when inside a VM */
6708         if (intel_vgpu_active(i915))
6709                 info->has_rc6 = 0;
6710
6711         if (info->has_rc6 &&
6712             IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
6713                 DRM_INFO("RC6 disabled by BIOS\n");
6714                 info->has_rc6 = 0;
6715         }
6716
6717         /*
6718          * We assume that we do not have any deep rc6 levels if we don't have
6719          * have the previous rc6 level supported, i.e. we use HAS_RC6()
6720          * as the initial coarse check for rc6 in general, moving on to
6721          * progressively finer/deeper levels.
6722          */
6723         if (!info->has_rc6 && info->has_rc6p)
6724                 info->has_rc6p = 0;
6725
6726         return info->has_rc6;
6727 }
6728
6729 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
6730 {
6731         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6732
6733         /* All of these values are in units of 50MHz */
6734
6735         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6736         if (IS_GEN9_LP(dev_priv)) {
6737                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
6738                 rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
6739                 rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
6740                 rps->min_freq = (rp_state_cap >>  0) & 0xff;
6741         } else {
6742                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6743                 rps->rp0_freq = (rp_state_cap >>  0) & 0xff;
6744                 rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
6745                 rps->min_freq = (rp_state_cap >> 16) & 0xff;
6746         }
6747         /* hw_max = RP0 until we check for overclocking */
6748         rps->max_freq = rps->rp0_freq;
6749
6750         rps->efficient_freq = rps->rp1_freq;
6751         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
6752             IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
6753                 u32 ddcc_status = 0;
6754
6755                 if (sandybridge_pcode_read(dev_priv,
6756                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
6757                                            &ddcc_status) == 0)
6758                         rps->efficient_freq =
6759                                 clamp_t(u8,
6760                                         ((ddcc_status >> 8) & 0xff),
6761                                         rps->min_freq,
6762                                         rps->max_freq);
6763         }
6764
6765         if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
6766                 /* Store the frequency values in 16.66 MHZ units, which is
6767                  * the natural hardware unit for SKL
6768                  */
6769                 rps->rp0_freq *= GEN9_FREQ_SCALER;
6770                 rps->rp1_freq *= GEN9_FREQ_SCALER;
6771                 rps->min_freq *= GEN9_FREQ_SCALER;
6772                 rps->max_freq *= GEN9_FREQ_SCALER;
6773                 rps->efficient_freq *= GEN9_FREQ_SCALER;
6774         }
6775 }
6776
6777 static void reset_rps(struct drm_i915_private *dev_priv,
6778                       int (*set)(struct drm_i915_private *, u8))
6779 {
6780         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6781         u8 freq = rps->cur_freq;
6782
6783         /* force a reset */
6784         rps->power = -1;
6785         rps->cur_freq = -1;
6786
6787         if (set(dev_priv, freq))
6788                 DRM_ERROR("Failed to reset RPS to initial values\n");
6789 }
6790
6791 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6792 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
6793 {
6794         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6795
6796         /* Program defaults and thresholds for RPS */
6797         if (IS_GEN9(dev_priv))
6798                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6799                         GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));
6800
6801         /* 1 second timeout*/
6802         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
6803                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
6804
6805         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
6806
6807         /* Leaning on the below call to gen6_set_rps to program/setup the
6808          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6809          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6810         reset_rps(dev_priv, gen6_set_rps);
6811
6812         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6813 }
6814
6815 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
6816 {
6817         struct intel_engine_cs *engine;
6818         enum intel_engine_id id;
6819         u32 rc6_mode;
6820
6821         /* 1a: Software RC state - RC0 */
6822         I915_WRITE(GEN6_RC_STATE, 0);
6823
6824         /* 1b: Get forcewake during program sequence. Although the driver
6825          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6826         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6827
6828         /* 2a: Disable RC states. */
6829         I915_WRITE(GEN6_RC_CONTROL, 0);
6830
6831         /* 2b: Program RC6 thresholds.*/
6832         if (INTEL_GEN(dev_priv) >= 10) {
6833                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
6834                 I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
6835         } else if (IS_SKYLAKE(dev_priv)) {
6836                 /*
6837                  * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
6838                  * when CPG is enabled
6839                  */
6840                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
6841         } else {
6842                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
6843         }
6844
6845         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6846         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6847         for_each_engine(engine, dev_priv, id)
6848                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6849
6850         if (HAS_GUC(dev_priv))
6851                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
6852
6853         I915_WRITE(GEN6_RC_SLEEP, 0);
6854
6855         /*
6856          * 2c: Program Coarse Power Gating Policies.
6857          *
6858          * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
6859          * use instead is a more conservative estimate for the maximum time
6860          * it takes us to service a CS interrupt and submit a new ELSP - that
6861          * is the time which the GPU is idle waiting for the CPU to select the
6862          * next request to execute. If the idle hysteresis is less than that
6863          * interrupt service latency, the hardware will automatically gate
6864          * the power well and we will then incur the wake up cost on top of
6865          * the service latency. A similar guide from intel_pstate is that we
6866          * do not want the enable hysteresis to less than the wakeup latency.
6867          *
6868          * igt/gem_exec_nop/sequential provides a rough estimate for the
6869          * service latency, and puts it around 10us for Broadwell (and other
6870          * big core) and around 40us for Broxton (and other low power cores).
6871          * [Note that for legacy ringbuffer submission, this is less than 1us!]
6872          * However, the wakeup latency on Broxton is closer to 100us. To be
6873          * conservative, we have to factor in a context switch on top (due
6874          * to ksoftirqd).
6875          */
6876         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
6877         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
6878
6879         /* 3a: Enable RC6 */
6880         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
6881
6882         /* WaRsUseTimeoutMode:cnl (pre-prod) */
6883         if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))
6884                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6885         else
6886                 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
6887
6888         I915_WRITE(GEN6_RC_CONTROL,
6889                    GEN6_RC_CTL_HW_ENABLE |
6890                    GEN6_RC_CTL_RC6_ENABLE |
6891                    rc6_mode);
6892
6893         /*
6894          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6895          * WaRsDisableCoarsePowerGating:skl,cnl - Render/Media PG need to be disabled with RC6.
6896          */
6897         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
6898                 I915_WRITE(GEN9_PG_ENABLE, 0);
6899         else
6900                 I915_WRITE(GEN9_PG_ENABLE,
6901                            GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
6902
6903         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6904 }
6905
6906 static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
6907 {
6908         struct intel_engine_cs *engine;
6909         enum intel_engine_id id;
6910
6911         /* 1a: Software RC state - RC0 */
6912         I915_WRITE(GEN6_RC_STATE, 0);
6913
6914         /* 1b: Get forcewake during program sequence. Although the driver
6915          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6916         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6917
6918         /* 2a: Disable RC states. */
6919         I915_WRITE(GEN6_RC_CONTROL, 0);
6920
6921         /* 2b: Program RC6 thresholds.*/
6922         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6923         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6924         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6925         for_each_engine(engine, dev_priv, id)
6926                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6927         I915_WRITE(GEN6_RC_SLEEP, 0);
6928         I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
6929
6930         /* 3: Enable RC6 */
6931
6932         I915_WRITE(GEN6_RC_CONTROL,
6933                    GEN6_RC_CTL_HW_ENABLE |
6934                    GEN7_RC_CTL_TO_MODE |
6935                    GEN6_RC_CTL_RC6_ENABLE);
6936
6937         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6938 }
6939
6940 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6941 {
6942         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6943
6944         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6945
6946         /* 1 Program defaults and thresholds for RPS*/
6947         I915_WRITE(GEN6_RPNSWREQ,
6948                    HSW_FREQUENCY(rps->rp1_freq));
6949         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6950                    HSW_FREQUENCY(rps->rp1_freq));
6951         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6952         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
6953
6954         /* Docs recommend 900MHz, and 300 MHz respectively */
6955         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6956                    rps->max_freq_softlimit << 24 |
6957                    rps->min_freq_softlimit << 16);
6958
6959         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
6960         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6961         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
6962         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
6963
6964         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6965
6966         /* 2: Enable RPS */
6967         I915_WRITE(GEN6_RP_CONTROL,
6968                    GEN6_RP_MEDIA_TURBO |
6969                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6970                    GEN6_RP_MEDIA_IS_GFX |
6971                    GEN6_RP_ENABLE |
6972                    GEN6_RP_UP_BUSY_AVG |
6973                    GEN6_RP_DOWN_IDLE_AVG);
6974
6975         reset_rps(dev_priv, gen6_set_rps);
6976
6977         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6978 }
6979
6980 static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
6981 {
6982         struct intel_engine_cs *engine;
6983         enum intel_engine_id id;
6984         u32 rc6vids, rc6_mask;
6985         u32 gtfifodbg;
6986         int ret;
6987
6988         I915_WRITE(GEN6_RC_STATE, 0);
6989
6990         /* Clear the DBG now so we don't confuse earlier errors */
6991         gtfifodbg = I915_READ(GTFIFODBG);
6992         if (gtfifodbg) {
6993                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
6994                 I915_WRITE(GTFIFODBG, gtfifodbg);
6995         }
6996
6997         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6998
6999         /* disable the counters and set deterministic thresholds */
7000         I915_WRITE(GEN6_RC_CONTROL, 0);
7001
7002         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7003         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7004         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7005         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7006         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7007
7008         for_each_engine(engine, dev_priv, id)
7009                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7010
7011         I915_WRITE(GEN6_RC_SLEEP, 0);
7012         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7013         if (IS_IVYBRIDGE(dev_priv))
7014                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
7015         else
7016                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7017         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
7018         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7019
7020         /* We don't use those on Haswell */
7021         rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
7022         if (HAS_RC6p(dev_priv))
7023                 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
7024         if (HAS_RC6pp(dev_priv))
7025                 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
7026         I915_WRITE(GEN6_RC_CONTROL,
7027                    rc6_mask |
7028                    GEN6_RC_CTL_EI_MODE(1) |
7029                    GEN6_RC_CTL_HW_ENABLE);
7030
7031         rc6vids = 0;
7032         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
7033         if (IS_GEN6(dev_priv) && ret) {
7034                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
7035         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
7036                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
7037                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
7038                 rc6vids &= 0xffff00;
7039                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
7040                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
7041                 if (ret)
7042                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
7043         }
7044
7045         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7046 }
7047
7048 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
7049 {
7050         /* Here begins a magic sequence of register writes to enable
7051          * auto-downclocking.
7052          *
7053          * Perhaps there might be some value in exposing these to
7054          * userspace...
7055          */
7056         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7057
7058         /* Power down if completely idle for over 50ms */
7059         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
7060         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7061
7062         reset_rps(dev_priv, gen6_set_rps);
7063
7064         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7065 }
7066
7067 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7068 {
7069         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7070         const int min_freq = 15;
7071         const int scaling_factor = 180;
7072         unsigned int gpu_freq;
7073         unsigned int max_ia_freq, min_ring_freq;
7074         unsigned int max_gpu_freq, min_gpu_freq;
7075         struct cpufreq_policy *policy;
7076
7077         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
7078
7079         if (rps->max_freq <= rps->min_freq)
7080                 return;
7081
7082         policy = cpufreq_cpu_get(0);
7083         if (policy) {
7084                 max_ia_freq = policy->cpuinfo.max_freq;
7085                 cpufreq_cpu_put(policy);
7086         } else {
7087                 /*
7088                  * Default to measured freq if none found, PCU will ensure we
7089                  * don't go over
7090                  */
7091                 max_ia_freq = tsc_khz;
7092         }
7093
7094         /* Convert from kHz to MHz */
7095         max_ia_freq /= 1000;
7096
7097         min_ring_freq = I915_READ(DCLK) & 0xf;
7098         /* convert DDR frequency from units of 266.6MHz to bandwidth */
7099         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
7100
7101         min_gpu_freq = rps->min_freq;
7102         max_gpu_freq = rps->max_freq;
7103         if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7104                 /* Convert GT frequency to 50 HZ units */
7105                 min_gpu_freq /= GEN9_FREQ_SCALER;
7106                 max_gpu_freq /= GEN9_FREQ_SCALER;
7107         }
7108
7109         /*
7110          * For each potential GPU frequency, load a ring frequency we'd like
7111          * to use for memory access.  We do this by specifying the IA frequency
7112          * the PCU should use as a reference to determine the ring frequency.
7113          */
7114         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
7115                 const int diff = max_gpu_freq - gpu_freq;
7116                 unsigned int ia_freq = 0, ring_freq = 0;
7117
7118                 if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7119                         /*
7120                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
7121                          * No floor required for ring frequency on SKL.
7122                          */
7123                         ring_freq = gpu_freq;
7124                 } else if (INTEL_GEN(dev_priv) >= 8) {
7125                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
7126                         ring_freq = max(min_ring_freq, gpu_freq);
7127                 } else if (IS_HASWELL(dev_priv)) {
7128                         ring_freq = mult_frac(gpu_freq, 5, 4);
7129                         ring_freq = max(min_ring_freq, ring_freq);
7130                         /* leave ia_freq as the default, chosen by cpufreq */
7131                 } else {
7132                         /* On older processors, there is no separate ring
7133                          * clock domain, so in order to boost the bandwidth
7134                          * of the ring, we need to upclock the CPU (ia_freq).
7135                          *
7136                          * For GPU frequencies less than 750MHz,
7137                          * just use the lowest ring freq.
7138                          */
7139                         if (gpu_freq < min_freq)
7140                                 ia_freq = 800;
7141                         else
7142                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7143                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7144                 }
7145
7146                 sandybridge_pcode_write(dev_priv,
7147                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
7148                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
7149                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
7150                                         gpu_freq);
7151         }
7152 }
7153
7154 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
7155 {
7156         u32 val, rp0;
7157
7158         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
7159
7160         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
7161         case 8:
7162                 /* (2 * 4) config */
7163                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
7164                 break;
7165         case 12:
7166                 /* (2 * 6) config */
7167                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
7168                 break;
7169         case 16:
7170                 /* (2 * 8) config */
7171         default:
7172                 /* Setting (2 * 8) Min RP0 for any other combination */
7173                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
7174                 break;
7175         }
7176
7177         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
7178
7179         return rp0;
7180 }
7181
7182 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
7183 {
7184         u32 val, rpe;
7185
7186         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
7187         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
7188
7189         return rpe;
7190 }
7191
7192 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
7193 {
7194         u32 val, rp1;
7195
7196         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
7197         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
7198
7199         return rp1;
7200 }
7201
7202 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
7203 {
7204         u32 val, rpn;
7205
7206         val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
7207         rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
7208                        FB_GFX_FREQ_FUSE_MASK);
7209
7210         return rpn;
7211 }
7212
7213 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
7214 {
7215         u32 val, rp1;
7216
7217         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
7218
7219         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
7220
7221         return rp1;
7222 }
7223
7224 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
7225 {
7226         u32 val, rp0;
7227
7228         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
7229
7230         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
7231         /* Clamp to max */
7232         rp0 = min_t(u32, rp0, 0xea);
7233
7234         return rp0;
7235 }
7236
7237 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
7238 {
7239         u32 val, rpe;
7240
7241         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
7242         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
7243         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
7244         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
7245
7246         return rpe;
7247 }
7248
7249 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
7250 {
7251         u32 val;
7252
7253         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
7254         /*
7255          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
7256          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
7257          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
7258          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
7259          * to make sure it matches what Punit accepts.
7260          */
7261         return max_t(u32, val, 0xc0);
7262 }
7263
7264 /* Check that the pctx buffer wasn't move under us. */
7265 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
7266 {
7267         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7268
7269         WARN_ON(pctx_addr != dev_priv->dsm.start +
7270                              dev_priv->vlv_pctx->stolen->start);
7271 }
7272
7273
7274 /* Check that the pcbr address is not empty. */
7275 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
7276 {
7277         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7278
7279         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
7280 }
7281
7282 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
7283 {
7284         resource_size_t pctx_paddr, paddr;
7285         resource_size_t pctx_size = 32*1024;
7286         u32 pcbr;
7287
7288         pcbr = I915_READ(VLV_PCBR);
7289         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
7290                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7291                 paddr = dev_priv->dsm.end + 1 - pctx_size;
7292                 GEM_BUG_ON(paddr > U32_MAX);
7293
7294                 pctx_paddr = (paddr & (~4095));
7295                 I915_WRITE(VLV_PCBR, pctx_paddr);
7296         }
7297
7298         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7299 }
7300
7301 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
7302 {
7303         struct drm_i915_gem_object *pctx;
7304         resource_size_t pctx_paddr;
7305         resource_size_t pctx_size = 24*1024;
7306         u32 pcbr;
7307
7308         pcbr = I915_READ(VLV_PCBR);
7309         if (pcbr) {
7310                 /* BIOS set it up already, grab the pre-alloc'd space */
7311                 resource_size_t pcbr_offset;
7312
7313                 pcbr_offset = (pcbr & (~4095)) - dev_priv->dsm.start;
7314                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
7315                                                                       pcbr_offset,
7316                                                                       I915_GTT_OFFSET_NONE,
7317                                                                       pctx_size);
7318                 goto out;
7319         }
7320
7321         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7322
7323         /*
7324          * From the Gunit register HAS:
7325          * The Gfx driver is expected to program this register and ensure
7326          * proper allocation within Gfx stolen memory.  For example, this
7327          * register should be programmed such than the PCBR range does not
7328          * overlap with other ranges, such as the frame buffer, protected
7329          * memory, or any other relevant ranges.
7330          */
7331         pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
7332         if (!pctx) {
7333                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
7334                 goto out;
7335         }
7336
7337         GEM_BUG_ON(range_overflows_t(u64,
7338                                      dev_priv->dsm.start,
7339                                      pctx->stolen->start,
7340                                      U32_MAX));
7341         pctx_paddr = dev_priv->dsm.start + pctx->stolen->start;
7342         I915_WRITE(VLV_PCBR, pctx_paddr);
7343
7344 out:
7345         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7346         dev_priv->vlv_pctx = pctx;
7347 }
7348
7349 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
7350 {
7351         if (WARN_ON(!dev_priv->vlv_pctx))
7352                 return;
7353
7354         i915_gem_object_put(dev_priv->vlv_pctx);
7355         dev_priv->vlv_pctx = NULL;
7356 }
7357
7358 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
7359 {
7360         dev_priv->gt_pm.rps.gpll_ref_freq =
7361                 vlv_get_cck_clock(dev_priv, "GPLL ref",
7362                                   CCK_GPLL_CLOCK_CONTROL,
7363                                   dev_priv->czclk_freq);
7364
7365         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
7366                          dev_priv->gt_pm.rps.gpll_ref_freq);
7367 }
7368
7369 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
7370 {
7371         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7372         u32 val;
7373
7374         valleyview_setup_pctx(dev_priv);
7375
7376         vlv_init_gpll_ref_freq(dev_priv);
7377
7378         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7379         switch ((val >> 6) & 3) {
7380         case 0:
7381         case 1:
7382                 dev_priv->mem_freq = 800;
7383                 break;
7384         case 2:
7385                 dev_priv->mem_freq = 1066;
7386                 break;
7387         case 3:
7388                 dev_priv->mem_freq = 1333;
7389                 break;
7390         }
7391         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7392
7393         rps->max_freq = valleyview_rps_max_freq(dev_priv);
7394         rps->rp0_freq = rps->max_freq;
7395         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7396                          intel_gpu_freq(dev_priv, rps->max_freq),
7397                          rps->max_freq);
7398
7399         rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv);
7400         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7401                          intel_gpu_freq(dev_priv, rps->efficient_freq),
7402                          rps->efficient_freq);
7403
7404         rps->rp1_freq = valleyview_rps_guar_freq(dev_priv);
7405         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7406                          intel_gpu_freq(dev_priv, rps->rp1_freq),
7407                          rps->rp1_freq);
7408
7409         rps->min_freq = valleyview_rps_min_freq(dev_priv);
7410         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7411                          intel_gpu_freq(dev_priv, rps->min_freq),
7412                          rps->min_freq);
7413 }
7414
7415 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
7416 {
7417         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7418         u32 val;
7419
7420         cherryview_setup_pctx(dev_priv);
7421
7422         vlv_init_gpll_ref_freq(dev_priv);
7423
7424         mutex_lock(&dev_priv->sb_lock);
7425         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
7426         mutex_unlock(&dev_priv->sb_lock);
7427
7428         switch ((val >> 2) & 0x7) {
7429         case 3:
7430                 dev_priv->mem_freq = 2000;
7431                 break;
7432         default:
7433                 dev_priv->mem_freq = 1600;
7434                 break;
7435         }
7436         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7437
7438         rps->max_freq = cherryview_rps_max_freq(dev_priv);
7439         rps->rp0_freq = rps->max_freq;
7440         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7441                          intel_gpu_freq(dev_priv, rps->max_freq),
7442                          rps->max_freq);
7443
7444         rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv);
7445         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7446                          intel_gpu_freq(dev_priv, rps->efficient_freq),
7447                          rps->efficient_freq);
7448
7449         rps->rp1_freq = cherryview_rps_guar_freq(dev_priv);
7450         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7451                          intel_gpu_freq(dev_priv, rps->rp1_freq),
7452                          rps->rp1_freq);
7453
7454         rps->min_freq = cherryview_rps_min_freq(dev_priv);
7455         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7456                          intel_gpu_freq(dev_priv, rps->min_freq),
7457                          rps->min_freq);
7458
7459         WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
7460                    rps->min_freq) & 1,
7461                   "Odd GPU freq values\n");
7462 }
7463
7464 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7465 {
7466         valleyview_cleanup_pctx(dev_priv);
7467 }
7468
7469 static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
7470 {
7471         struct intel_engine_cs *engine;
7472         enum intel_engine_id id;
7473         u32 gtfifodbg, rc6_mode, pcbr;
7474
7475         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
7476                                              GT_FIFO_FREE_ENTRIES_CHV);
7477         if (gtfifodbg) {
7478                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7479                                  gtfifodbg);
7480                 I915_WRITE(GTFIFODBG, gtfifodbg);
7481         }
7482
7483         cherryview_check_pctx(dev_priv);
7484
7485         /* 1a & 1b: Get forcewake during program sequence. Although the driver
7486          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7487         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7488
7489         /*  Disable RC states. */
7490         I915_WRITE(GEN6_RC_CONTROL, 0);
7491
7492         /* 2a: Program RC6 thresholds.*/
7493         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7494         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7495         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7496
7497         for_each_engine(engine, dev_priv, id)
7498                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7499         I915_WRITE(GEN6_RC_SLEEP, 0);
7500
7501         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7502         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
7503
7504         /* Allows RC6 residency counter to work */
7505         I915_WRITE(VLV_COUNTER_CONTROL,
7506                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7507                                       VLV_MEDIA_RC6_COUNT_EN |
7508                                       VLV_RENDER_RC6_COUNT_EN));
7509
7510         /* For now we assume BIOS is allocating and populating the PCBR  */
7511         pcbr = I915_READ(VLV_PCBR);
7512
7513         /* 3: Enable RC6 */
7514         rc6_mode = 0;
7515         if (pcbr >> VLV_PCBR_ADDR_SHIFT)
7516                 rc6_mode = GEN7_RC_CTL_TO_MODE;
7517         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7518
7519         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7520 }
7521
7522 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
7523 {
7524         u32 val;
7525
7526         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7527
7528         /* 1: Program defaults and thresholds for RPS*/
7529         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7530         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7531         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7532         I915_WRITE(GEN6_RP_UP_EI, 66000);
7533         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7534
7535         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7536
7537         /* 2: Enable RPS */
7538         I915_WRITE(GEN6_RP_CONTROL,
7539                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7540                    GEN6_RP_MEDIA_IS_GFX |
7541                    GEN6_RP_ENABLE |
7542                    GEN6_RP_UP_BUSY_AVG |
7543                    GEN6_RP_DOWN_IDLE_AVG);
7544
7545         /* Setting Fixed Bias */
7546         val = VLV_OVERRIDE_EN |
7547                   VLV_SOC_TDP_EN |
7548                   CHV_BIAS_CPU_50_SOC_50;
7549         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7550
7551         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7552
7553         /* RPS code assumes GPLL is used */
7554         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7555
7556         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7557         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7558
7559         reset_rps(dev_priv, valleyview_set_rps);
7560
7561         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7562 }
7563
7564 static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
7565 {
7566         struct intel_engine_cs *engine;
7567         enum intel_engine_id id;
7568         u32 gtfifodbg;
7569
7570         valleyview_check_pctx(dev_priv);
7571
7572         gtfifodbg = I915_READ(GTFIFODBG);
7573         if (gtfifodbg) {
7574                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7575                                  gtfifodbg);
7576                 I915_WRITE(GTFIFODBG, gtfifodbg);
7577         }
7578
7579         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7580
7581         /*  Disable RC states. */
7582         I915_WRITE(GEN6_RC_CONTROL, 0);
7583
7584         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
7585         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7586         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7587
7588         for_each_engine(engine, dev_priv, id)
7589                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7590
7591         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
7592
7593         /* Allows RC6 residency counter to work */
7594         I915_WRITE(VLV_COUNTER_CONTROL,
7595                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7596                                       VLV_MEDIA_RC0_COUNT_EN |
7597                                       VLV_RENDER_RC0_COUNT_EN |
7598                                       VLV_MEDIA_RC6_COUNT_EN |
7599                                       VLV_RENDER_RC6_COUNT_EN));
7600
7601         I915_WRITE(GEN6_RC_CONTROL,
7602                    GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL);
7603
7604         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7605 }
7606
7607 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
7608 {
7609         u32 val;
7610
7611         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7612
7613         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7614         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7615         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7616         I915_WRITE(GEN6_RP_UP_EI, 66000);
7617         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7618
7619         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7620
7621         I915_WRITE(GEN6_RP_CONTROL,
7622                    GEN6_RP_MEDIA_TURBO |
7623                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7624                    GEN6_RP_MEDIA_IS_GFX |
7625                    GEN6_RP_ENABLE |
7626                    GEN6_RP_UP_BUSY_AVG |
7627                    GEN6_RP_DOWN_IDLE_CONT);
7628
7629         /* Setting Fixed Bias */
7630         val = VLV_OVERRIDE_EN |
7631                   VLV_SOC_TDP_EN |
7632                   VLV_BIAS_CPU_125_SOC_875;
7633         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7634
7635         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7636
7637         /* RPS code assumes GPLL is used */
7638         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7639
7640         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7641         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7642
7643         reset_rps(dev_priv, valleyview_set_rps);
7644
7645         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7646 }
7647
7648 static unsigned long intel_pxfreq(u32 vidfreq)
7649 {
7650         unsigned long freq;
7651         int div = (vidfreq & 0x3f0000) >> 16;
7652         int post = (vidfreq & 0x3000) >> 12;
7653         int pre = (vidfreq & 0x7);
7654
7655         if (!pre)
7656                 return 0;
7657
7658         freq = ((div * 133333) / ((1<<post) * pre));
7659
7660         return freq;
7661 }
7662
7663 static const struct cparams {
7664         u16 i;
7665         u16 t;
7666         u16 m;
7667         u16 c;
7668 } cparams[] = {
7669         { 1, 1333, 301, 28664 },
7670         { 1, 1066, 294, 24460 },
7671         { 1, 800, 294, 25192 },
7672         { 0, 1333, 276, 27605 },
7673         { 0, 1066, 276, 27605 },
7674         { 0, 800, 231, 23784 },
7675 };
7676
7677 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
7678 {
7679         u64 total_count, diff, ret;
7680         u32 count1, count2, count3, m = 0, c = 0;
7681         unsigned long now = jiffies_to_msecs(jiffies), diff1;
7682         int i;
7683
7684         lockdep_assert_held(&mchdev_lock);
7685
7686         diff1 = now - dev_priv->ips.last_time1;
7687
7688         /* Prevent division-by-zero if we are asking too fast.
7689          * Also, we don't get interesting results if we are polling
7690          * faster than once in 10ms, so just return the saved value
7691          * in such cases.
7692          */
7693         if (diff1 <= 10)
7694                 return dev_priv->ips.chipset_power;
7695
7696         count1 = I915_READ(DMIEC);
7697         count2 = I915_READ(DDREC);
7698         count3 = I915_READ(CSIEC);
7699
7700         total_count = count1 + count2 + count3;
7701
7702         /* FIXME: handle per-counter overflow */
7703         if (total_count < dev_priv->ips.last_count1) {
7704                 diff = ~0UL - dev_priv->ips.last_count1;
7705                 diff += total_count;
7706         } else {
7707                 diff = total_count - dev_priv->ips.last_count1;
7708         }
7709
7710         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
7711                 if (cparams[i].i == dev_priv->ips.c_m &&
7712                     cparams[i].t == dev_priv->ips.r_t) {
7713                         m = cparams[i].m;
7714                         c = cparams[i].c;
7715                         break;
7716                 }
7717         }
7718
7719         diff = div_u64(diff, diff1);
7720         ret = ((m * diff) + c);
7721         ret = div_u64(ret, 10);
7722
7723         dev_priv->ips.last_count1 = total_count;
7724         dev_priv->ips.last_time1 = now;
7725
7726         dev_priv->ips.chipset_power = ret;
7727
7728         return ret;
7729 }
7730
7731 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
7732 {
7733         unsigned long val;
7734
7735         if (!IS_GEN5(dev_priv))
7736                 return 0;
7737
7738         spin_lock_irq(&mchdev_lock);
7739
7740         val = __i915_chipset_val(dev_priv);
7741
7742         spin_unlock_irq(&mchdev_lock);
7743
7744         return val;
7745 }
7746
7747 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
7748 {
7749         unsigned long m, x, b;
7750         u32 tsfs;
7751
7752         tsfs = I915_READ(TSFS);
7753
7754         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
7755         x = I915_READ8(TR1);
7756
7757         b = tsfs & TSFS_INTR_MASK;
7758
7759         return ((m * x) / 127) - b;
7760 }
7761
7762 static int _pxvid_to_vd(u8 pxvid)
7763 {
7764         if (pxvid == 0)
7765                 return 0;
7766
7767         if (pxvid >= 8 && pxvid < 31)
7768                 pxvid = 31;
7769
7770         return (pxvid + 2) * 125;
7771 }
7772
7773 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7774 {
7775         const int vd = _pxvid_to_vd(pxvid);
7776         const int vm = vd - 1125;
7777
7778         if (INTEL_INFO(dev_priv)->is_mobile)
7779                 return vm > 0 ? vm : 0;
7780
7781         return vd;
7782 }
7783
7784 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
7785 {
7786         u64 now, diff, diffms;
7787         u32 count;
7788
7789         lockdep_assert_held(&mchdev_lock);
7790
7791         now = ktime_get_raw_ns();
7792         diffms = now - dev_priv->ips.last_time2;
7793         do_div(diffms, NSEC_PER_MSEC);
7794
7795         /* Don't divide by 0 */
7796         if (!diffms)
7797                 return;
7798
7799         count = I915_READ(GFXEC);
7800
7801         if (count < dev_priv->ips.last_count2) {
7802                 diff = ~0UL - dev_priv->ips.last_count2;
7803                 diff += count;
7804         } else {
7805                 diff = count - dev_priv->ips.last_count2;
7806         }
7807
7808         dev_priv->ips.last_count2 = count;
7809         dev_priv->ips.last_time2 = now;
7810
7811         /* More magic constants... */
7812         diff = diff * 1181;
7813         diff = div_u64(diff, diffms * 10);
7814         dev_priv->ips.gfx_power = diff;
7815 }
7816
7817 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
7818 {
7819         if (!IS_GEN5(dev_priv))
7820                 return;
7821
7822         spin_lock_irq(&mchdev_lock);
7823
7824         __i915_update_gfx_val(dev_priv);
7825
7826         spin_unlock_irq(&mchdev_lock);
7827 }
7828
7829 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
7830 {
7831         unsigned long t, corr, state1, corr2, state2;
7832         u32 pxvid, ext_v;
7833
7834         lockdep_assert_held(&mchdev_lock);
7835
7836         pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));
7837         pxvid = (pxvid >> 24) & 0x7f;
7838         ext_v = pvid_to_extvid(dev_priv, pxvid);
7839
7840         state1 = ext_v;
7841
7842         t = i915_mch_val(dev_priv);
7843
7844         /* Revel in the empirically derived constants */
7845
7846         /* Correction factor in 1/100000 units */
7847         if (t > 80)
7848                 corr = ((t * 2349) + 135940);
7849         else if (t >= 50)
7850                 corr = ((t * 964) + 29317);
7851         else /* < 50 */
7852                 corr = ((t * 301) + 1004);
7853
7854         corr = corr * ((150142 * state1) / 10000 - 78642);
7855         corr /= 100000;
7856         corr2 = (corr * dev_priv->ips.corr);
7857
7858         state2 = (corr2 * state1) / 10000;
7859         state2 /= 100; /* convert to mW */
7860
7861         __i915_update_gfx_val(dev_priv);
7862
7863         return dev_priv->ips.gfx_power + state2;
7864 }
7865
7866 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
7867 {
7868         unsigned long val;
7869
7870         if (!IS_GEN5(dev_priv))
7871                 return 0;
7872
7873         spin_lock_irq(&mchdev_lock);
7874
7875         val = __i915_gfx_val(dev_priv);
7876
7877         spin_unlock_irq(&mchdev_lock);
7878
7879         return val;
7880 }
7881
7882 /**
7883  * i915_read_mch_val - return value for IPS use
7884  *
7885  * Calculate and return a value for the IPS driver to use when deciding whether
7886  * we have thermal and power headroom to increase CPU or GPU power budget.
7887  */
7888 unsigned long i915_read_mch_val(void)
7889 {
7890         struct drm_i915_private *dev_priv;
7891         unsigned long chipset_val, graphics_val, ret = 0;
7892
7893         spin_lock_irq(&mchdev_lock);
7894         if (!i915_mch_dev)
7895                 goto out_unlock;
7896         dev_priv = i915_mch_dev;
7897
7898         chipset_val = __i915_chipset_val(dev_priv);
7899         graphics_val = __i915_gfx_val(dev_priv);
7900
7901         ret = chipset_val + graphics_val;
7902
7903 out_unlock:
7904         spin_unlock_irq(&mchdev_lock);
7905
7906         return ret;
7907 }
7908 EXPORT_SYMBOL_GPL(i915_read_mch_val);
7909
7910 /**
7911  * i915_gpu_raise - raise GPU frequency limit
7912  *
7913  * Raise the limit; IPS indicates we have thermal headroom.
7914  */
7915 bool i915_gpu_raise(void)
7916 {
7917         struct drm_i915_private *dev_priv;
7918         bool ret = true;
7919
7920         spin_lock_irq(&mchdev_lock);
7921         if (!i915_mch_dev) {
7922                 ret = false;
7923                 goto out_unlock;
7924         }
7925         dev_priv = i915_mch_dev;
7926
7927         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
7928                 dev_priv->ips.max_delay--;
7929
7930 out_unlock:
7931         spin_unlock_irq(&mchdev_lock);
7932
7933         return ret;
7934 }
7935 EXPORT_SYMBOL_GPL(i915_gpu_raise);
7936
7937 /**
7938  * i915_gpu_lower - lower GPU frequency limit
7939  *
7940  * IPS indicates we're close to a thermal limit, so throttle back the GPU
7941  * frequency maximum.
7942  */
7943 bool i915_gpu_lower(void)
7944 {
7945         struct drm_i915_private *dev_priv;
7946         bool ret = true;
7947
7948         spin_lock_irq(&mchdev_lock);
7949         if (!i915_mch_dev) {
7950                 ret = false;
7951                 goto out_unlock;
7952         }
7953         dev_priv = i915_mch_dev;
7954
7955         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
7956                 dev_priv->ips.max_delay++;
7957
7958 out_unlock:
7959         spin_unlock_irq(&mchdev_lock);
7960
7961         return ret;
7962 }
7963 EXPORT_SYMBOL_GPL(i915_gpu_lower);
7964
7965 /**
7966  * i915_gpu_busy - indicate GPU business to IPS
7967  *
7968  * Tell the IPS driver whether or not the GPU is busy.
7969  */
7970 bool i915_gpu_busy(void)
7971 {
7972         bool ret = false;
7973
7974         spin_lock_irq(&mchdev_lock);
7975         if (i915_mch_dev)
7976                 ret = i915_mch_dev->gt.awake;
7977         spin_unlock_irq(&mchdev_lock);
7978
7979         return ret;
7980 }
7981 EXPORT_SYMBOL_GPL(i915_gpu_busy);
7982
7983 /**
7984  * i915_gpu_turbo_disable - disable graphics turbo
7985  *
7986  * Disable graphics turbo by resetting the max frequency and setting the
7987  * current frequency to the default.
7988  */
7989 bool i915_gpu_turbo_disable(void)
7990 {
7991         struct drm_i915_private *dev_priv;
7992         bool ret = true;
7993
7994         spin_lock_irq(&mchdev_lock);
7995         if (!i915_mch_dev) {
7996                 ret = false;
7997                 goto out_unlock;
7998         }
7999         dev_priv = i915_mch_dev;
8000
8001         dev_priv->ips.max_delay = dev_priv->ips.fstart;
8002
8003         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
8004                 ret = false;
8005
8006 out_unlock:
8007         spin_unlock_irq(&mchdev_lock);
8008
8009         return ret;
8010 }
8011 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
8012
8013 /**
8014  * Tells the intel_ips driver that the i915 driver is now loaded, if
8015  * IPS got loaded first.
8016  *
8017  * This awkward dance is so that neither module has to depend on the
8018  * other in order for IPS to do the appropriate communication of
8019  * GPU turbo limits to i915.
8020  */
8021 static void
8022 ips_ping_for_i915_load(void)
8023 {
8024         void (*link)(void);
8025
8026         link = symbol_get(ips_link_to_i915_driver);
8027         if (link) {
8028                 link();
8029                 symbol_put(ips_link_to_i915_driver);
8030         }
8031 }
8032
8033 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
8034 {
8035         /* We only register the i915 ips part with intel-ips once everything is
8036          * set up, to avoid intel-ips sneaking in and reading bogus values. */
8037         spin_lock_irq(&mchdev_lock);
8038         i915_mch_dev = dev_priv;
8039         spin_unlock_irq(&mchdev_lock);
8040
8041         ips_ping_for_i915_load();
8042 }
8043
8044 void intel_gpu_ips_teardown(void)
8045 {
8046         spin_lock_irq(&mchdev_lock);
8047         i915_mch_dev = NULL;
8048         spin_unlock_irq(&mchdev_lock);
8049 }
8050
8051 static void intel_init_emon(struct drm_i915_private *dev_priv)
8052 {
8053         u32 lcfuse;
8054         u8 pxw[16];
8055         int i;
8056
8057         /* Disable to program */
8058         I915_WRITE(ECR, 0);
8059         POSTING_READ(ECR);
8060
8061         /* Program energy weights for various events */
8062         I915_WRITE(SDEW, 0x15040d00);
8063         I915_WRITE(CSIEW0, 0x007f0000);
8064         I915_WRITE(CSIEW1, 0x1e220004);
8065         I915_WRITE(CSIEW2, 0x04000004);
8066
8067         for (i = 0; i < 5; i++)
8068                 I915_WRITE(PEW(i), 0);
8069         for (i = 0; i < 3; i++)
8070                 I915_WRITE(DEW(i), 0);
8071
8072         /* Program P-state weights to account for frequency power adjustment */
8073         for (i = 0; i < 16; i++) {
8074                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
8075                 unsigned long freq = intel_pxfreq(pxvidfreq);
8076                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8077                         PXVFREQ_PX_SHIFT;
8078                 unsigned long val;
8079
8080                 val = vid * vid;
8081                 val *= (freq / 1000);
8082                 val *= 255;
8083                 val /= (127*127*900);
8084                 if (val > 0xff)
8085                         DRM_ERROR("bad pxval: %ld\n", val);
8086                 pxw[i] = val;
8087         }
8088         /* Render standby states get 0 weight */
8089         pxw[14] = 0;
8090         pxw[15] = 0;
8091
8092         for (i = 0; i < 4; i++) {
8093                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8094                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8095                 I915_WRITE(PXW(i), val);
8096         }
8097
8098         /* Adjust magic regs to magic values (more experimental results) */
8099         I915_WRITE(OGW0, 0);
8100         I915_WRITE(OGW1, 0);
8101         I915_WRITE(EG0, 0x00007f00);
8102         I915_WRITE(EG1, 0x0000000e);
8103         I915_WRITE(EG2, 0x000e0000);
8104         I915_WRITE(EG3, 0x68000300);
8105         I915_WRITE(EG4, 0x42000000);
8106         I915_WRITE(EG5, 0x00140031);
8107         I915_WRITE(EG6, 0);
8108         I915_WRITE(EG7, 0);
8109
8110         for (i = 0; i < 8; i++)
8111                 I915_WRITE(PXWL(i), 0);
8112
8113         /* Enable PMON + select events */
8114         I915_WRITE(ECR, 0x80000019);
8115
8116         lcfuse = I915_READ(LCFUSE02);
8117
8118         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
8119 }
8120
8121 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
8122 {
8123         struct intel_rps *rps = &dev_priv->gt_pm.rps;
8124
8125         /*
8126          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
8127          * requirement.
8128          */
8129         if (!sanitize_rc6(dev_priv)) {
8130                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
8131                 intel_runtime_pm_get(dev_priv);
8132         }
8133
8134         mutex_lock(&dev_priv->pcu_lock);
8135
8136         /* Initialize RPS limits (for userspace) */
8137         if (IS_CHERRYVIEW(dev_priv))
8138                 cherryview_init_gt_powersave(dev_priv);
8139         else if (IS_VALLEYVIEW(dev_priv))
8140                 valleyview_init_gt_powersave(dev_priv);
8141         else if (INTEL_GEN(dev_priv) >= 6)
8142                 gen6_init_rps_frequencies(dev_priv);
8143
8144         /* Derive initial user preferences/limits from the hardware limits */
8145         rps->idle_freq = rps->min_freq;
8146         rps->cur_freq = rps->idle_freq;
8147
8148         rps->max_freq_softlimit = rps->max_freq;
8149         rps->min_freq_softlimit = rps->min_freq;
8150
8151         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
8152                 rps->min_freq_softlimit =
8153                         max_t(int,
8154                               rps->efficient_freq,
8155                               intel_freq_opcode(dev_priv, 450));
8156
8157         /* After setting max-softlimit, find the overclock max freq */
8158         if (IS_GEN6(dev_priv) ||
8159             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
8160                 u32 params = 0;
8161
8162                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
8163                 if (params & BIT(31)) { /* OC supported */
8164                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
8165                                          (rps->max_freq & 0xff) * 50,
8166                                          (params & 0xff) * 50);
8167                         rps->max_freq = params & 0xff;
8168                 }
8169         }
8170
8171         /* Finally allow us to boost to max by default */
8172         rps->boost_freq = rps->max_freq;
8173
8174         mutex_unlock(&dev_priv->pcu_lock);
8175 }
8176
8177 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
8178 {
8179         if (IS_VALLEYVIEW(dev_priv))
8180                 valleyview_cleanup_gt_powersave(dev_priv);
8181
8182         if (!HAS_RC6(dev_priv))
8183                 intel_runtime_pm_put(dev_priv);
8184 }
8185
8186 /**
8187  * intel_suspend_gt_powersave - suspend PM work and helper threads
8188  * @dev_priv: i915 device
8189  *
8190  * We don't want to disable RC6 or other features here, we just want
8191  * to make sure any work we've queued has finished and won't bother
8192  * us while we're suspended.
8193  */
8194 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
8195 {
8196         if (INTEL_GEN(dev_priv) < 6)
8197                 return;
8198
8199         /* gen6_rps_idle() will be called later to disable interrupts */
8200 }
8201
8202 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
8203 {
8204         dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
8205         dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
8206         intel_disable_gt_powersave(dev_priv);
8207
8208         if (INTEL_GEN(dev_priv) >= 11)
8209                 gen11_reset_rps_interrupts(dev_priv);
8210         else
8211                 gen6_reset_rps_interrupts(dev_priv);
8212 }
8213
8214 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
8215 {
8216         lockdep_assert_held(&i915->pcu_lock);
8217
8218         if (!i915->gt_pm.llc_pstate.enabled)
8219                 return;
8220
8221         /* Currently there is no HW configuration to be done to disable. */
8222
8223         i915->gt_pm.llc_pstate.enabled = false;
8224 }
8225
8226 static void intel_disable_rc6(struct drm_i915_private *dev_priv)
8227 {
8228         lockdep_assert_held(&dev_priv->pcu_lock);
8229
8230         if (!dev_priv->gt_pm.rc6.enabled)
8231                 return;
8232
8233         if (INTEL_GEN(dev_priv) >= 9)
8234                 gen9_disable_rc6(dev_priv);
8235         else if (IS_CHERRYVIEW(dev_priv))
8236                 cherryview_disable_rc6(dev_priv);
8237         else if (IS_VALLEYVIEW(dev_priv))
8238                 valleyview_disable_rc6(dev_priv);
8239         else if (INTEL_GEN(dev_priv) >= 6)
8240                 gen6_disable_rc6(dev_priv);
8241
8242         dev_priv->gt_pm.rc6.enabled = false;
8243 }
8244
8245 static void intel_disable_rps(struct drm_i915_private *dev_priv)
8246 {
8247         lockdep_assert_held(&dev_priv->pcu_lock);
8248
8249         if (!dev_priv->gt_pm.rps.enabled)
8250                 return;
8251
8252         if (INTEL_GEN(dev_priv) >= 9)
8253                 gen9_disable_rps(dev_priv);
8254         else if (IS_CHERRYVIEW(dev_priv))
8255                 cherryview_disable_rps(dev_priv);
8256         else if (IS_VALLEYVIEW(dev_priv))
8257                 valleyview_disable_rps(dev_priv);
8258         else if (INTEL_GEN(dev_priv) >= 6)
8259                 gen6_disable_rps(dev_priv);
8260         else if (IS_IRONLAKE_M(dev_priv))
8261                 ironlake_disable_drps(dev_priv);
8262
8263         dev_priv->gt_pm.rps.enabled = false;
8264 }
8265
8266 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8267 {
8268         mutex_lock(&dev_priv->pcu_lock);
8269
8270         intel_disable_rc6(dev_priv);
8271         intel_disable_rps(dev_priv);
8272         if (HAS_LLC(dev_priv))
8273                 intel_disable_llc_pstate(dev_priv);
8274
8275         mutex_unlock(&dev_priv->pcu_lock);
8276 }
8277
8278 static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
8279 {
8280         lockdep_assert_held(&i915->pcu_lock);
8281
8282         if (i915->gt_pm.llc_pstate.enabled)
8283                 return;
8284
8285         gen6_update_ring_freq(i915);
8286
8287         i915->gt_pm.llc_pstate.enabled = true;
8288 }
8289
8290 static void intel_enable_rc6(struct drm_i915_private *dev_priv)
8291 {
8292         lockdep_assert_held(&dev_priv->pcu_lock);
8293
8294         if (dev_priv->gt_pm.rc6.enabled)
8295                 return;
8296
8297         if (IS_CHERRYVIEW(dev_priv))
8298                 cherryview_enable_rc6(dev_priv);
8299         else if (IS_VALLEYVIEW(dev_priv))
8300                 valleyview_enable_rc6(dev_priv);
8301         else if (INTEL_GEN(dev_priv) >= 9)
8302                 gen9_enable_rc6(dev_priv);
8303         else if (IS_BROADWELL(dev_priv))
8304                 gen8_enable_rc6(dev_priv);
8305         else if (INTEL_GEN(dev_priv) >= 6)
8306                 gen6_enable_rc6(dev_priv);
8307
8308         dev_priv->gt_pm.rc6.enabled = true;
8309 }
8310
8311 static void intel_enable_rps(struct drm_i915_private *dev_priv)
8312 {
8313         struct intel_rps *rps = &dev_priv->gt_pm.rps;
8314
8315         lockdep_assert_held(&dev_priv->pcu_lock);
8316
8317         if (rps->enabled)
8318                 return;
8319
8320         if (IS_CHERRYVIEW(dev_priv)) {
8321                 cherryview_enable_rps(dev_priv);
8322         } else if (IS_VALLEYVIEW(dev_priv)) {
8323                 valleyview_enable_rps(dev_priv);
8324         } else if (INTEL_GEN(dev_priv) >= 9) {
8325                 gen9_enable_rps(dev_priv);
8326         } else if (IS_BROADWELL(dev_priv)) {
8327                 gen8_enable_rps(dev_priv);
8328         } else if (INTEL_GEN(dev_priv) >= 6) {
8329                 gen6_enable_rps(dev_priv);
8330         } else if (IS_IRONLAKE_M(dev_priv)) {
8331                 ironlake_enable_drps(dev_priv);
8332                 intel_init_emon(dev_priv);
8333         }
8334
8335         WARN_ON(rps->max_freq < rps->min_freq);
8336         WARN_ON(rps->idle_freq > rps->max_freq);
8337
8338         WARN_ON(rps->efficient_freq < rps->min_freq);
8339         WARN_ON(rps->efficient_freq > rps->max_freq);
8340
8341         rps->enabled = true;
8342 }
8343
8344 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8345 {
8346         /* Powersaving is controlled by the host when inside a VM */
8347         if (intel_vgpu_active(dev_priv))
8348                 return;
8349
8350         mutex_lock(&dev_priv->pcu_lock);
8351
8352         if (HAS_RC6(dev_priv))
8353                 intel_enable_rc6(dev_priv);
8354         intel_enable_rps(dev_priv);
8355         if (HAS_LLC(dev_priv))
8356                 intel_enable_llc_pstate(dev_priv);
8357
8358         mutex_unlock(&dev_priv->pcu_lock);
8359 }
8360
8361 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
8362 {
8363         /*
8364          * On Ibex Peak and Cougar Point, we need to disable clock
8365          * gating for the panel power sequencer or it will fail to
8366          * start up when no ports are active.
8367          */
8368         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8369 }
8370
8371 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
8372 {
8373         enum pipe pipe;
8374
8375         for_each_pipe(dev_priv, pipe) {
8376                 I915_WRITE(DSPCNTR(pipe),
8377                            I915_READ(DSPCNTR(pipe)) |
8378                            DISPPLANE_TRICKLE_FEED_DISABLE);
8379
8380                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
8381                 POSTING_READ(DSPSURF(pipe));
8382         }
8383 }
8384
8385 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
8386 {
8387         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8388
8389         /*
8390          * Required for FBC
8391          * WaFbcDisableDpfcClockGating:ilk
8392          */
8393         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
8394                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
8395                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
8396
8397         I915_WRITE(PCH_3DCGDIS0,
8398                    MARIUNIT_CLOCK_GATE_DISABLE |
8399                    SVSMUNIT_CLOCK_GATE_DISABLE);
8400         I915_WRITE(PCH_3DCGDIS1,
8401                    VFMUNIT_CLOCK_GATE_DISABLE);
8402
8403         /*
8404          * According to the spec the following bits should be set in
8405          * order to enable memory self-refresh
8406          * The bit 22/21 of 0x42004
8407          * The bit 5 of 0x42020
8408          * The bit 15 of 0x45000
8409          */
8410         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8411                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8412                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8413         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
8414         I915_WRITE(DISP_ARB_CTL,
8415                    (I915_READ(DISP_ARB_CTL) |
8416                     DISP_FBC_WM_DIS));
8417
8418         /*
8419          * Based on the document from hardware guys the following bits
8420          * should be set unconditionally in order to enable FBC.
8421          * The bit 22 of 0x42000
8422          * The bit 22 of 0x42004
8423          * The bit 7,8,9 of 0x42020.
8424          */
8425         if (IS_IRONLAKE_M(dev_priv)) {
8426                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8427                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8428                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8429                            ILK_FBCQ_DIS);
8430                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8431                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8432                            ILK_DPARB_GATE);
8433         }
8434
8435         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8436
8437         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8438                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8439                    ILK_ELPIN_409_SELECT);
8440         I915_WRITE(_3D_CHICKEN2,
8441                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8442                    _3D_CHICKEN2_WM_READ_PIPELINED);
8443
8444         /* WaDisableRenderCachePipelinedFlush:ilk */
8445         I915_WRITE(CACHE_MODE_0,
8446                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8447
8448         /* WaDisable_RenderCache_OperationalFlush:ilk */
8449         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8450
8451         g4x_disable_trickle_feed(dev_priv);
8452
8453         ibx_init_clock_gating(dev_priv);
8454 }
8455
8456 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
8457 {
8458         int pipe;
8459         uint32_t val;
8460
8461         /*
8462          * On Ibex Peak and Cougar Point, we need to disable clock
8463          * gating for the panel power sequencer or it will fail to
8464          * start up when no ports are active.
8465          */
8466         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
8467                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
8468                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
8469         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8470                    DPLS_EDP_PPS_FIX_DIS);
8471         /* The below fixes the weird display corruption, a few pixels shifted
8472          * downward, on (only) LVDS of some HP laptops with IVY.
8473          */
8474         for_each_pipe(dev_priv, pipe) {
8475                 val = I915_READ(TRANS_CHICKEN2(pipe));
8476                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
8477                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8478                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
8479                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8480                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
8481                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
8482                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
8483                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
8484         }
8485         /* WADP0ClockGatingDisable */
8486         for_each_pipe(dev_priv, pipe) {
8487                 I915_WRITE(TRANS_CHICKEN1(pipe),
8488                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8489         }
8490 }
8491
8492 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
8493 {
8494         uint32_t tmp;
8495
8496         tmp = I915_READ(MCH_SSKPD);
8497         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
8498                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8499                               tmp);
8500 }
8501
8502 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
8503 {
8504         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8505
8506         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8507
8508         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8509                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8510                    ILK_ELPIN_409_SELECT);
8511
8512         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8513         I915_WRITE(_3D_CHICKEN,
8514                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8515
8516         /* WaDisable_RenderCache_OperationalFlush:snb */
8517         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8518
8519         /*
8520          * BSpec recoomends 8x4 when MSAA is used,
8521          * however in practice 16x4 seems fastest.
8522          *
8523          * Note that PS/WM thread counts depend on the WIZ hashing
8524          * disable bit, which we don't touch here, but it's good
8525          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8526          */
8527         I915_WRITE(GEN6_GT_MODE,
8528                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8529
8530         I915_WRITE(CACHE_MODE_0,
8531                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
8532
8533         I915_WRITE(GEN6_UCGCTL1,
8534                    I915_READ(GEN6_UCGCTL1) |
8535                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8536                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8537
8538         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8539          * gating disable must be set.  Failure to set it results in
8540          * flickering pixels due to Z write ordering failures after
8541          * some amount of runtime in the Mesa "fire" demo, and Unigine
8542          * Sanctuary and Tropics, and apparently anything else with
8543          * alpha test or pixel discard.
8544          *
8545          * According to the spec, bit 11 (RCCUNIT) must also be set,
8546          * but we didn't debug actual testcases to find it out.
8547          *
8548          * WaDisableRCCUnitClockGating:snb
8549          * WaDisableRCPBUnitClockGating:snb
8550          */
8551         I915_WRITE(GEN6_UCGCTL2,
8552                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8553                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8554
8555         /* WaStripsFansDisableFastClipPerformanceFix:snb */
8556         I915_WRITE(_3D_CHICKEN3,
8557                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
8558
8559         /*
8560          * Bspec says:
8561          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8562          * 3DSTATE_SF number of SF output attributes is more than 16."
8563          */
8564         I915_WRITE(_3D_CHICKEN3,
8565                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
8566
8567         /*
8568          * According to the spec the following bits should be
8569          * set in order to enable memory self-refresh and fbc:
8570          * The bit21 and bit22 of 0x42000
8571          * The bit21 and bit22 of 0x42004
8572          * The bit5 and bit7 of 0x42020
8573          * The bit14 of 0x70180
8574          * The bit14 of 0x71180
8575          *
8576          * WaFbcAsynchFlipDisableFbcQueue:snb
8577          */
8578         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8579                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8580                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8581         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8582                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8583                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8584         I915_WRITE(ILK_DSPCLK_GATE_D,
8585                    I915_READ(ILK_DSPCLK_GATE_D) |
8586                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
8587                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
8588
8589         g4x_disable_trickle_feed(dev_priv);
8590
8591         cpt_init_clock_gating(dev_priv);
8592
8593         gen6_check_mch_setup(dev_priv);
8594 }
8595
8596 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8597 {
8598         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8599
8600         /*
8601          * WaVSThreadDispatchOverride:ivb,vlv
8602          *
8603          * This actually overrides the dispatch
8604          * mode for all thread types.
8605          */
8606         reg &= ~GEN7_FF_SCHED_MASK;
8607         reg |= GEN7_FF_TS_SCHED_HW;
8608         reg |= GEN7_FF_VS_SCHED_HW;
8609         reg |= GEN7_FF_DS_SCHED_HW;
8610
8611         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8612 }
8613
8614 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
8615 {
8616         /*
8617          * TODO: this bit should only be enabled when really needed, then
8618          * disabled when not needed anymore in order to save power.
8619          */
8620         if (HAS_PCH_LPT_LP(dev_priv))
8621                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
8622                            I915_READ(SOUTH_DSPCLK_GATE_D) |
8623                            PCH_LP_PARTITION_LEVEL_DISABLE);
8624
8625         /* WADPOClockGatingDisable:hsw */
8626         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
8627                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
8628                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8629 }
8630
8631 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
8632 {
8633         if (HAS_PCH_LPT_LP(dev_priv)) {
8634                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
8635
8636                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8637                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8638         }
8639 }
8640
8641 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
8642                                    int general_prio_credits,
8643                                    int high_prio_credits)
8644 {
8645         u32 misccpctl;
8646         u32 val;
8647
8648         /* WaTempDisableDOPClkGating:bdw */
8649         misccpctl = I915_READ(GEN7_MISCCPCTL);
8650         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
8651
8652         val = I915_READ(GEN8_L3SQCREG1);
8653         val &= ~L3_PRIO_CREDITS_MASK;
8654         val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
8655         val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
8656         I915_WRITE(GEN8_L3SQCREG1, val);
8657
8658         /*
8659          * Wait at least 100 clocks before re-enabling clock gating.
8660          * See the definition of L3SQCREG1 in BSpec.
8661          */
8662         POSTING_READ(GEN8_L3SQCREG1);
8663         udelay(1);
8664         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
8665 }
8666
8667 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
8668 {
8669         /* This is not an Wa. Enable to reduce Sampler power */
8670         I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
8671                    I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
8672 }
8673
8674 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
8675 {
8676         if (!HAS_PCH_CNP(dev_priv))
8677                 return;
8678
8679         /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
8680         I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
8681                    CNP_PWM_CGE_GATING_DISABLE);
8682 }
8683
8684 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
8685 {
8686         u32 val;
8687         cnp_init_clock_gating(dev_priv);
8688
8689         /* This is not an Wa. Enable for better image quality */
8690         I915_WRITE(_3D_CHICKEN3,
8691                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
8692
8693         /* WaEnableChickenDCPR:cnl */
8694         I915_WRITE(GEN8_CHICKEN_DCPR_1,
8695                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
8696
8697         /* WaFbcWakeMemOn:cnl */
8698         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
8699                    DISP_FBC_MEMORY_WAKE);
8700
8701         val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
8702         /* ReadHitWriteOnlyDisable:cnl */
8703         val |= RCCUNIT_CLKGATE_DIS;
8704         /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
8705         if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
8706                 val |= SARBUNIT_CLKGATE_DIS;
8707         I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
8708
8709         /* Wa_2201832410:cnl */
8710         val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
8711         val |= GWUNIT_CLKGATE_DIS;
8712         I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
8713
8714         /* WaDisableVFclkgate:cnl */
8715         /* WaVFUnitClockGatingDisable:cnl */
8716         val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
8717         val |= VFUNIT_CLKGATE_DIS;
8718         I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
8719 }
8720
8721 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
8722 {
8723         cnp_init_clock_gating(dev_priv);
8724         gen9_init_clock_gating(dev_priv);
8725
8726         /* WaFbcNukeOnHostModify:cfl */
8727         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8728                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8729 }
8730
8731 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
8732 {
8733         gen9_init_clock_gating(dev_priv);
8734
8735         /* WaDisableSDEUnitClockGating:kbl */
8736         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8737                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8738                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8739
8740         /* WaDisableGamClockGating:kbl */
8741         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8742                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8743                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
8744
8745         /* WaFbcNukeOnHostModify:kbl */
8746         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8747                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8748 }
8749
8750 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
8751 {
8752         gen9_init_clock_gating(dev_priv);
8753
8754         /* WAC6entrylatency:skl */
8755         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
8756                    FBC_LLC_FULLY_OPEN);
8757
8758         /* WaFbcNukeOnHostModify:skl */
8759         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8760                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8761 }
8762
8763 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
8764 {
8765         /* The GTT cache must be disabled if the system is using 2M pages. */
8766         bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
8767                                                  I915_GTT_PAGE_SIZE_2M);
8768         enum pipe pipe;
8769
8770         /* WaSwitchSolVfFArbitrationPriority:bdw */
8771         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8772
8773         /* WaPsrDPAMaskVBlankInSRD:bdw */
8774         I915_WRITE(CHICKEN_PAR1_1,
8775                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
8776
8777         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8778         for_each_pipe(dev_priv, pipe) {
8779                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
8780                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
8781                            BDW_DPRS_MASK_VBLANK_SRD);
8782         }
8783
8784         /* WaVSRefCountFullforceMissDisable:bdw */
8785         /* WaDSRefCountFullforceMissDisable:bdw */
8786         I915_WRITE(GEN7_FF_THREAD_MODE,
8787                    I915_READ(GEN7_FF_THREAD_MODE) &
8788                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8789
8790         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8791                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8792
8793         /* WaDisableSDEUnitClockGating:bdw */
8794         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8795                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8796
8797         /* WaProgramL3SqcReg1Default:bdw */
8798         gen8_set_l3sqc_credits(dev_priv, 30, 2);
8799
8800         /* WaGttCachingOffByDefault:bdw */
8801         I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
8802
8803         /* WaKVMNotificationOnConfigChange:bdw */
8804         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
8805                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
8806
8807         lpt_init_clock_gating(dev_priv);
8808
8809         /* WaDisableDopClockGating:bdw
8810          *
8811          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8812          * clock gating.
8813          */
8814         I915_WRITE(GEN6_UCGCTL1,
8815                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
8816 }
8817
8818 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
8819 {
8820         /* L3 caching of data atomics doesn't work -- disable it. */
8821         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
8822         I915_WRITE(HSW_ROW_CHICKEN3,
8823                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
8824
8825         /* This is required by WaCatErrorRejectionIssue:hsw */
8826         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8827                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8828                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8829
8830         /* WaVSRefCountFullforceMissDisable:hsw */
8831         I915_WRITE(GEN7_FF_THREAD_MODE,
8832                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
8833
8834         /* WaDisable_RenderCache_OperationalFlush:hsw */
8835         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8836
8837         /* enable HiZ Raw Stall Optimization */
8838         I915_WRITE(CACHE_MODE_0_GEN7,
8839                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8840
8841         /* WaDisable4x2SubspanOptimization:hsw */
8842         I915_WRITE(CACHE_MODE_1,
8843                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8844
8845         /*
8846          * BSpec recommends 8x4 when MSAA is used,
8847          * however in practice 16x4 seems fastest.
8848          *
8849          * Note that PS/WM thread counts depend on the WIZ hashing
8850          * disable bit, which we don't touch here, but it's good
8851          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8852          */
8853         I915_WRITE(GEN7_GT_MODE,
8854                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8855
8856         /* WaSampleCChickenBitEnable:hsw */
8857         I915_WRITE(HALF_SLICE_CHICKEN3,
8858                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
8859
8860         /* WaSwitchSolVfFArbitrationPriority:hsw */
8861         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8862
8863         lpt_init_clock_gating(dev_priv);
8864 }
8865
8866 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
8867 {
8868         uint32_t snpcr;
8869
8870         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
8871
8872         /* WaDisableEarlyCull:ivb */
8873         I915_WRITE(_3D_CHICKEN3,
8874                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8875
8876         /* WaDisableBackToBackFlipFix:ivb */
8877         I915_WRITE(IVB_CHICKEN3,
8878                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8879                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8880
8881         /* WaDisablePSDDualDispatchEnable:ivb */
8882         if (IS_IVB_GT1(dev_priv))
8883                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8884                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8885
8886         /* WaDisable_RenderCache_OperationalFlush:ivb */
8887         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8888
8889         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8890         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8891                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8892
8893         /* WaApplyL3ControlAndL3ChickenMode:ivb */
8894         I915_WRITE(GEN7_L3CNTLREG1,
8895                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8896         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8897                    GEN7_WA_L3_CHICKEN_MODE);
8898         if (IS_IVB_GT1(dev_priv))
8899                 I915_WRITE(GEN7_ROW_CHICKEN2,
8900                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8901         else {
8902                 /* must write both registers */
8903                 I915_WRITE(GEN7_ROW_CHICKEN2,
8904                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8905                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
8906                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8907         }
8908
8909         /* WaForceL3Serialization:ivb */
8910         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8911                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8912
8913         /*
8914          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8915          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8916          */
8917         I915_WRITE(GEN6_UCGCTL2,
8918                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8919
8920         /* This is required by WaCatErrorRejectionIssue:ivb */
8921         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8922                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8923                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8924
8925         g4x_disable_trickle_feed(dev_priv);
8926
8927         gen7_setup_fixed_func_scheduler(dev_priv);
8928
8929         if (0) { /* causes HiZ corruption on ivb:gt1 */
8930                 /* enable HiZ Raw Stall Optimization */
8931                 I915_WRITE(CACHE_MODE_0_GEN7,
8932                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8933         }
8934
8935         /* WaDisable4x2SubspanOptimization:ivb */
8936         I915_WRITE(CACHE_MODE_1,
8937                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8938
8939         /*
8940          * BSpec recommends 8x4 when MSAA is used,
8941          * however in practice 16x4 seems fastest.
8942          *
8943          * Note that PS/WM thread counts depend on the WIZ hashing
8944          * disable bit, which we don't touch here, but it's good
8945          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8946          */
8947         I915_WRITE(GEN7_GT_MODE,
8948                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8949
8950         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
8951         snpcr &= ~GEN6_MBC_SNPCR_MASK;
8952         snpcr |= GEN6_MBC_SNPCR_MED;
8953         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
8954
8955         if (!HAS_PCH_NOP(dev_priv))
8956                 cpt_init_clock_gating(dev_priv);
8957
8958         gen6_check_mch_setup(dev_priv);
8959 }
8960
8961 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
8962 {
8963         /* WaDisableEarlyCull:vlv */
8964         I915_WRITE(_3D_CHICKEN3,
8965                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8966
8967         /* WaDisableBackToBackFlipFix:vlv */
8968         I915_WRITE(IVB_CHICKEN3,
8969                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8970                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8971
8972         /* WaPsdDispatchEnable:vlv */
8973         /* WaDisablePSDDualDispatchEnable:vlv */
8974         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8975                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
8976                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8977
8978         /* WaDisable_RenderCache_OperationalFlush:vlv */
8979         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8980
8981         /* WaForceL3Serialization:vlv */
8982         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8983                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8984
8985         /* WaDisableDopClockGating:vlv */
8986         I915_WRITE(GEN7_ROW_CHICKEN2,
8987                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8988
8989         /* This is required by WaCatErrorRejectionIssue:vlv */
8990         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8991                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8992                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8993
8994         gen7_setup_fixed_func_scheduler(dev_priv);
8995
8996         /*
8997          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8998          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8999          */
9000         I915_WRITE(GEN6_UCGCTL2,
9001                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
9002
9003         /* WaDisableL3Bank2xClockGate:vlv
9004          * Disabling L3 clock gating- MMIO 940c[25] = 1
9005          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
9006         I915_WRITE(GEN7_UCGCTL4,
9007                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
9008
9009         /*
9010          * BSpec says this must be set, even though
9011          * WaDisable4x2SubspanOptimization isn't listed for VLV.
9012          */
9013         I915_WRITE(CACHE_MODE_1,
9014                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
9015
9016         /*
9017          * BSpec recommends 8x4 when MSAA is used,
9018          * however in practice 16x4 seems fastest.
9019          *
9020          * Note that PS/WM thread counts depend on the WIZ hashing
9021          * disable bit, which we don't touch here, but it's good
9022          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
9023          */
9024         I915_WRITE(GEN7_GT_MODE,
9025                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
9026
9027         /*
9028          * WaIncreaseL3CreditsForVLVB0:vlv
9029          * This is the hardware default actually.
9030          */
9031         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
9032
9033         /*
9034          * WaDisableVLVClockGating_VBIIssue:vlv
9035          * Disable clock gating on th GCFG unit to prevent a delay
9036          * in the reporting of vblank events.
9037          */
9038         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
9039 }
9040
9041 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
9042 {
9043         /* WaVSRefCountFullforceMissDisable:chv */
9044         /* WaDSRefCountFullforceMissDisable:chv */
9045         I915_WRITE(GEN7_FF_THREAD_MODE,
9046                    I915_READ(GEN7_FF_THREAD_MODE) &
9047                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
9048
9049         /* WaDisableSemaphoreAndSyncFlipWait:chv */
9050         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
9051                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
9052
9053         /* WaDisableCSUnitClockGating:chv */
9054         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
9055                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
9056
9057         /* WaDisableSDEUnitClockGating:chv */
9058         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9059                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
9060
9061         /*
9062          * WaProgramL3SqcReg1Default:chv
9063          * See gfxspecs/Related Documents/Performance Guide/
9064          * LSQC Setting Recommendations.
9065          */
9066         gen8_set_l3sqc_credits(dev_priv, 38, 2);
9067
9068         /*
9069          * GTT cache may not work with big pages, so if those
9070          * are ever enabled GTT cache may need to be disabled.
9071          */
9072         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
9073 }
9074
9075 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
9076 {
9077         uint32_t dspclk_gate;
9078
9079         I915_WRITE(RENCLK_GATE_D1, 0);
9080         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
9081                    GS_UNIT_CLOCK_GATE_DISABLE |
9082                    CL_UNIT_CLOCK_GATE_DISABLE);
9083         I915_WRITE(RAMCLK_GATE_D, 0);
9084         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
9085                 OVRUNIT_CLOCK_GATE_DISABLE |
9086                 OVCUNIT_CLOCK_GATE_DISABLE;
9087         if (IS_GM45(dev_priv))
9088                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
9089         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
9090
9091         /* WaDisableRenderCachePipelinedFlush */
9092         I915_WRITE(CACHE_MODE_0,
9093                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
9094
9095         /* WaDisable_RenderCache_OperationalFlush:g4x */
9096         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9097
9098         g4x_disable_trickle_feed(dev_priv);
9099 }
9100
9101 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
9102 {
9103         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
9104         I915_WRITE(RENCLK_GATE_D2, 0);
9105         I915_WRITE(DSPCLK_GATE_D, 0);
9106         I915_WRITE(RAMCLK_GATE_D, 0);
9107         I915_WRITE16(DEUC, 0);
9108         I915_WRITE(MI_ARB_STATE,
9109                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9110
9111         /* WaDisable_RenderCache_OperationalFlush:gen4 */
9112         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9113 }
9114
9115 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
9116 {
9117         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
9118                    I965_RCC_CLOCK_GATE_DISABLE |
9119                    I965_RCPB_CLOCK_GATE_DISABLE |
9120                    I965_ISC_CLOCK_GATE_DISABLE |
9121                    I965_FBC_CLOCK_GATE_DISABLE);
9122         I915_WRITE(RENCLK_GATE_D2, 0);
9123         I915_WRITE(MI_ARB_STATE,
9124                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9125
9126         /* WaDisable_RenderCache_OperationalFlush:gen4 */
9127         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9128 }
9129
9130 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
9131 {
9132         u32 dstate = I915_READ(D_STATE);
9133
9134         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
9135                 DSTATE_DOT_CLOCK_GATING;
9136         I915_WRITE(D_STATE, dstate);
9137
9138         if (IS_PINEVIEW(dev_priv))
9139                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
9140
9141         /* IIR "flip pending" means done if this bit is set */
9142         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
9143
9144         /* interrupts should cause a wake up from C3 */
9145         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
9146
9147         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
9148         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
9149
9150         I915_WRITE(MI_ARB_STATE,
9151                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9152 }
9153
9154 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
9155 {
9156         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
9157
9158         /* interrupts should cause a wake up from C3 */
9159         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
9160                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
9161
9162         I915_WRITE(MEM_MODE,
9163                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
9164 }
9165
9166 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
9167 {
9168         I915_WRITE(MEM_MODE,
9169                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
9170                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
9171 }
9172
9173 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
9174 {
9175         dev_priv->display.init_clock_gating(dev_priv);
9176 }
9177
9178 void intel_suspend_hw(struct drm_i915_private *dev_priv)
9179 {
9180         if (HAS_PCH_LPT(dev_priv))
9181                 lpt_suspend_hw(dev_priv);
9182 }
9183
9184 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
9185 {
9186         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
9187 }
9188
9189 /**
9190  * intel_init_clock_gating_hooks - setup the clock gating hooks
9191  * @dev_priv: device private
9192  *
9193  * Setup the hooks that configure which clocks of a given platform can be
9194  * gated and also apply various GT and display specific workarounds for these
9195  * platforms. Note that some GT specific workarounds are applied separately
9196  * when GPU contexts or batchbuffers start their execution.
9197  */
9198 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
9199 {
9200         if (IS_ICELAKE(dev_priv))
9201                 dev_priv->display.init_clock_gating = icl_init_clock_gating;
9202         else if (IS_CANNONLAKE(dev_priv))
9203                 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
9204         else if (IS_COFFEELAKE(dev_priv))
9205                 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
9206         else if (IS_SKYLAKE(dev_priv))
9207                 dev_priv->display.init_clock_gating = skl_init_clock_gating;
9208         else if (IS_KABYLAKE(dev_priv))
9209                 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
9210         else if (IS_BROXTON(dev_priv))
9211                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
9212         else if (IS_GEMINILAKE(dev_priv))
9213                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
9214         else if (IS_BROADWELL(dev_priv))
9215                 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
9216         else if (IS_CHERRYVIEW(dev_priv))
9217                 dev_priv->display.init_clock_gating = chv_init_clock_gating;
9218         else if (IS_HASWELL(dev_priv))
9219                 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
9220         else if (IS_IVYBRIDGE(dev_priv))
9221                 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
9222         else if (IS_VALLEYVIEW(dev_priv))
9223                 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
9224         else if (IS_GEN6(dev_priv))
9225                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9226         else if (IS_GEN5(dev_priv))
9227                 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
9228         else if (IS_G4X(dev_priv))
9229                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9230         else if (IS_I965GM(dev_priv))
9231                 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
9232         else if (IS_I965G(dev_priv))
9233                 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
9234         else if (IS_GEN3(dev_priv))
9235                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9236         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
9237                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9238         else if (IS_GEN2(dev_priv))
9239                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9240         else {
9241                 MISSING_CASE(INTEL_DEVID(dev_priv));
9242                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
9243         }
9244 }
9245
9246 /* Set up chip specific power management-related functions */
9247 void intel_init_pm(struct drm_i915_private *dev_priv)
9248 {
9249         intel_fbc_init(dev_priv);
9250
9251         /* For cxsr */
9252         if (IS_PINEVIEW(dev_priv))
9253                 i915_pineview_get_mem_freq(dev_priv);
9254         else if (IS_GEN5(dev_priv))
9255                 i915_ironlake_get_mem_freq(dev_priv);
9256
9257         /* For FIFO watermark updates */
9258         if (INTEL_GEN(dev_priv) >= 9) {
9259                 skl_setup_wm_latency(dev_priv);
9260                 dev_priv->display.initial_watermarks = skl_initial_wm;
9261                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
9262                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
9263         } else if (HAS_PCH_SPLIT(dev_priv)) {
9264                 ilk_setup_wm_latency(dev_priv);
9265
9266                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
9267                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
9268                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
9269                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
9270                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
9271                         dev_priv->display.compute_intermediate_wm =
9272                                 ilk_compute_intermediate_wm;
9273                         dev_priv->display.initial_watermarks =
9274                                 ilk_initial_watermarks;
9275                         dev_priv->display.optimize_watermarks =
9276                                 ilk_optimize_watermarks;
9277                 } else {
9278                         DRM_DEBUG_KMS("Failed to read display plane latency. "
9279                                       "Disable CxSR\n");
9280                 }
9281         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9282                 vlv_setup_wm_latency(dev_priv);
9283                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
9284                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
9285                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
9286                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
9287                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
9288         } else if (IS_G4X(dev_priv)) {
9289                 g4x_setup_wm_latency(dev_priv);
9290                 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
9291                 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
9292                 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
9293                 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
9294         } else if (IS_PINEVIEW(dev_priv)) {
9295                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
9296                                             dev_priv->is_ddr3,
9297                                             dev_priv->fsb_freq,
9298                                             dev_priv->mem_freq)) {
9299                         DRM_INFO("failed to find known CxSR latency "
9300                                  "(found ddr%s fsb freq %d, mem freq %d), "
9301                                  "disabling CxSR\n",
9302                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9303                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9304                         /* Disable CxSR and never update its watermark again */
9305                         intel_set_memory_cxsr(dev_priv, false);
9306                         dev_priv->display.update_wm = NULL;
9307                 } else
9308                         dev_priv->display.update_wm = pineview_update_wm;
9309         } else if (IS_GEN4(dev_priv)) {
9310                 dev_priv->display.update_wm = i965_update_wm;
9311         } else if (IS_GEN3(dev_priv)) {
9312                 dev_priv->display.update_wm = i9xx_update_wm;
9313                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9314         } else if (IS_GEN2(dev_priv)) {
9315                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
9316                         dev_priv->display.update_wm = i845_update_wm;
9317                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9318                 } else {
9319                         dev_priv->display.update_wm = i9xx_update_wm;
9320                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9321                 }
9322         } else {
9323                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
9324         }
9325 }
9326
9327 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
9328 {
9329         uint32_t flags =
9330                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
9331
9332         switch (flags) {
9333         case GEN6_PCODE_SUCCESS:
9334                 return 0;
9335         case GEN6_PCODE_UNIMPLEMENTED_CMD:
9336                 return -ENODEV;
9337         case GEN6_PCODE_ILLEGAL_CMD:
9338                 return -ENXIO;
9339         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9340         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9341                 return -EOVERFLOW;
9342         case GEN6_PCODE_TIMEOUT:
9343                 return -ETIMEDOUT;
9344         default:
9345                 MISSING_CASE(flags);
9346                 return 0;
9347         }
9348 }
9349
9350 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
9351 {
9352         uint32_t flags =
9353                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
9354
9355         switch (flags) {
9356         case GEN6_PCODE_SUCCESS:
9357                 return 0;
9358         case GEN6_PCODE_ILLEGAL_CMD:
9359                 return -ENXIO;
9360         case GEN7_PCODE_TIMEOUT:
9361                 return -ETIMEDOUT;
9362         case GEN7_PCODE_ILLEGAL_DATA:
9363                 return -EINVAL;
9364         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9365                 return -EOVERFLOW;
9366         default:
9367                 MISSING_CASE(flags);
9368                 return 0;
9369         }
9370 }
9371
9372 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
9373 {
9374         int status;
9375
9376         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9377
9378         /* GEN6_PCODE_* are outside of the forcewake domain, we can
9379          * use te fw I915_READ variants to reduce the amount of work
9380          * required when reading/writing.
9381          */
9382
9383         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
9384                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
9385                                  mbox, __builtin_return_address(0));
9386                 return -EAGAIN;
9387         }
9388
9389         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
9390         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
9391         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
9392
9393         if (__intel_wait_for_register_fw(dev_priv,
9394                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
9395                                          500, 0, NULL)) {
9396                 DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
9397                           mbox, __builtin_return_address(0));
9398                 return -ETIMEDOUT;
9399         }
9400
9401         *val = I915_READ_FW(GEN6_PCODE_DATA);
9402         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
9403
9404         if (INTEL_GEN(dev_priv) > 6)
9405                 status = gen7_check_mailbox_status(dev_priv);
9406         else
9407                 status = gen6_check_mailbox_status(dev_priv);
9408
9409         if (status) {
9410                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
9411                                  mbox, __builtin_return_address(0), status);
9412                 return status;
9413         }
9414
9415         return 0;
9416 }
9417
9418 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
9419                                     u32 mbox, u32 val,
9420                                     int fast_timeout_us, int slow_timeout_ms)
9421 {
9422         int status;
9423
9424         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9425
9426         /* GEN6_PCODE_* are outside of the forcewake domain, we can
9427          * use te fw I915_READ variants to reduce the amount of work
9428          * required when reading/writing.
9429          */
9430
9431         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
9432                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
9433                                  val, mbox, __builtin_return_address(0));
9434                 return -EAGAIN;
9435         }
9436
9437         I915_WRITE_FW(GEN6_PCODE_DATA, val);
9438         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
9439         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
9440
9441         if (__intel_wait_for_register_fw(dev_priv,
9442                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
9443                                          fast_timeout_us, slow_timeout_ms,
9444                                          NULL)) {
9445                 DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
9446                           val, mbox, __builtin_return_address(0));
9447                 return -ETIMEDOUT;
9448         }
9449
9450         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
9451
9452         if (INTEL_GEN(dev_priv) > 6)
9453                 status = gen7_check_mailbox_status(dev_priv);
9454         else
9455                 status = gen6_check_mailbox_status(dev_priv);
9456
9457         if (status) {
9458                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
9459                                  val, mbox, __builtin_return_address(0), status);
9460                 return status;
9461         }
9462
9463         return 0;
9464 }
9465
9466 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
9467                                   u32 request, u32 reply_mask, u32 reply,
9468                                   u32 *status)
9469 {
9470         u32 val = request;
9471
9472         *status = sandybridge_pcode_read(dev_priv, mbox, &val);
9473
9474         return *status || ((val & reply_mask) == reply);
9475 }
9476
9477 /**
9478  * skl_pcode_request - send PCODE request until acknowledgment
9479  * @dev_priv: device private
9480  * @mbox: PCODE mailbox ID the request is targeted for
9481  * @request: request ID
9482  * @reply_mask: mask used to check for request acknowledgment
9483  * @reply: value used to check for request acknowledgment
9484  * @timeout_base_ms: timeout for polling with preemption enabled
9485  *
9486  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
9487  * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
9488  * The request is acknowledged once the PCODE reply dword equals @reply after
9489  * applying @reply_mask. Polling is first attempted with preemption enabled
9490  * for @timeout_base_ms and if this times out for another 50 ms with
9491  * preemption disabled.
9492  *
9493  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
9494  * other error as reported by PCODE.
9495  */
9496 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
9497                       u32 reply_mask, u32 reply, int timeout_base_ms)
9498 {
9499         u32 status;
9500         int ret;
9501
9502         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9503
9504 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9505                                    &status)
9506
9507         /*
9508          * Prime the PCODE by doing a request first. Normally it guarantees
9509          * that a subsequent request, at most @timeout_base_ms later, succeeds.
9510          * _wait_for() doesn't guarantee when its passed condition is evaluated
9511          * first, so send the first request explicitly.
9512          */
9513         if (COND) {
9514                 ret = 0;
9515                 goto out;
9516         }
9517         ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
9518         if (!ret)
9519                 goto out;
9520
9521         /*
9522          * The above can time out if the number of requests was low (2 in the
9523          * worst case) _and_ PCODE was busy for some reason even after a
9524          * (queued) request and @timeout_base_ms delay. As a workaround retry
9525          * the poll with preemption disabled to maximize the number of
9526          * requests. Increase the timeout from @timeout_base_ms to 50ms to
9527          * account for interrupts that could reduce the number of these
9528          * requests, and for any quirks of the PCODE firmware that delays
9529          * the request completion.
9530          */
9531         DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9532         WARN_ON_ONCE(timeout_base_ms > 3);
9533         preempt_disable();
9534         ret = wait_for_atomic(COND, 50);
9535         preempt_enable();
9536
9537 out:
9538         return ret ? ret : status;
9539 #undef COND
9540 }
9541
9542 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
9543 {
9544         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9545
9546         /*
9547          * N = val - 0xb7
9548          * Slow = Fast = GPLL ref * N
9549          */
9550         return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
9551 }
9552
9553 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
9554 {
9555         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9556
9557         return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
9558 }
9559
9560 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
9561 {
9562         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9563
9564         /*
9565          * N = val / 2
9566          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9567          */
9568         return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
9569 }
9570
9571 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
9572 {
9573         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9574
9575         /* CHV needs even values */
9576         return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
9577 }
9578
9579 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
9580 {
9581         if (INTEL_GEN(dev_priv) >= 9)
9582                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
9583                                          GEN9_FREQ_SCALER);
9584         else if (IS_CHERRYVIEW(dev_priv))
9585                 return chv_gpu_freq(dev_priv, val);
9586         else if (IS_VALLEYVIEW(dev_priv))
9587                 return byt_gpu_freq(dev_priv, val);
9588         else
9589                 return val * GT_FREQUENCY_MULTIPLIER;
9590 }
9591
9592 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9593 {
9594         if (INTEL_GEN(dev_priv) >= 9)
9595                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
9596                                          GT_FREQUENCY_MULTIPLIER);
9597         else if (IS_CHERRYVIEW(dev_priv))
9598                 return chv_freq_opcode(dev_priv, val);
9599         else if (IS_VALLEYVIEW(dev_priv))
9600                 return byt_freq_opcode(dev_priv, val);
9601         else
9602                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9603 }
9604
9605 void intel_pm_setup(struct drm_i915_private *dev_priv)
9606 {
9607         mutex_init(&dev_priv->pcu_lock);
9608
9609         atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
9610
9611         dev_priv->runtime_pm.suspended = false;
9612         atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
9613 }
9614
9615 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
9616                              const i915_reg_t reg)
9617 {
9618         u32 lower, upper, tmp;
9619         int loop = 2;
9620
9621         /*
9622          * The register accessed do not need forcewake. We borrow
9623          * uncore lock to prevent concurrent access to range reg.
9624          */
9625         lockdep_assert_held(&dev_priv->uncore.lock);
9626
9627         /*
9628          * vlv and chv residency counters are 40 bits in width.
9629          * With a control bit, we can choose between upper or lower
9630          * 32bit window into this counter.
9631          *
9632          * Although we always use the counter in high-range mode elsewhere,
9633          * userspace may attempt to read the value before rc6 is initialised,
9634          * before we have set the default VLV_COUNTER_CONTROL value. So always
9635          * set the high bit to be safe.
9636          */
9637         I915_WRITE_FW(VLV_COUNTER_CONTROL,
9638                       _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9639         upper = I915_READ_FW(reg);
9640         do {
9641                 tmp = upper;
9642
9643                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9644                               _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
9645                 lower = I915_READ_FW(reg);
9646
9647                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9648                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9649                 upper = I915_READ_FW(reg);
9650         } while (upper != tmp && --loop);
9651
9652         /*
9653          * Everywhere else we always use VLV_COUNTER_CONTROL with the
9654          * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9655          * now.
9656          */
9657
9658         return lower | (u64)upper << 8;
9659 }
9660
9661 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
9662                            const i915_reg_t reg)
9663 {
9664         u64 time_hw, prev_hw, overflow_hw;
9665         unsigned int fw_domains;
9666         unsigned long flags;
9667         unsigned int i;
9668         u32 mul, div;
9669
9670         if (!HAS_RC6(dev_priv))
9671                 return 0;
9672
9673         /*
9674          * Store previous hw counter values for counter wrap-around handling.
9675          *
9676          * There are only four interesting registers and they live next to each
9677          * other so we can use the relative address, compared to the smallest
9678          * one as the index into driver storage.
9679          */
9680         i = (i915_mmio_reg_offset(reg) -
9681              i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
9682         if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
9683                 return 0;
9684
9685         fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
9686
9687         spin_lock_irqsave(&dev_priv->uncore.lock, flags);
9688         intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
9689
9690         /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9691         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9692                 mul = 1000000;
9693                 div = dev_priv->czclk_freq;
9694                 overflow_hw = BIT_ULL(40);
9695                 time_hw = vlv_residency_raw(dev_priv, reg);
9696         } else {
9697                 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
9698                 if (IS_GEN9_LP(dev_priv)) {
9699                         mul = 10000;
9700                         div = 12;
9701                 } else {
9702                         mul = 1280;
9703                         div = 1;
9704                 }
9705
9706                 overflow_hw = BIT_ULL(32);
9707                 time_hw = I915_READ_FW(reg);
9708         }
9709
9710         /*
9711          * Counter wrap handling.
9712          *
9713          * But relying on a sufficient frequency of queries otherwise counters
9714          * can still wrap.
9715          */
9716         prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
9717         dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
9718
9719         /* RC6 delta from last sample. */
9720         if (time_hw >= prev_hw)
9721                 time_hw -= prev_hw;
9722         else
9723                 time_hw += overflow_hw - prev_hw;
9724
9725         /* Add delta to RC6 extended raw driver copy. */
9726         time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
9727         dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
9728
9729         intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
9730         spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
9731
9732         return mul_u64_u32_div(time_hw, mul, div);
9733 }
9734
9735 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
9736 {
9737         u32 cagf;
9738
9739         if (INTEL_GEN(dev_priv) >= 9)
9740                 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
9741         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
9742                 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
9743         else
9744                 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
9745
9746         return  cagf;
9747 }