drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 /* Primary plane formats for gen <= 3 */
  53 static const uint32_t i8xx_primary_formats[] = {
  54         DRM_FORMAT_C8,
  55         DRM_FORMAT_RGB565,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_XRGB8888,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t i965_primary_formats[] = {
  62         DRM_FORMAT_C8,
  63         DRM_FORMAT_RGB565,
  64         DRM_FORMAT_XRGB8888,
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68 };
  69
  70 static const uint64_t i9xx_format_modifiers[] = {
  71         I915_FORMAT_MOD_X_TILED,
  72         DRM_FORMAT_MOD_LINEAR,
  73         DRM_FORMAT_MOD_INVALID
  74 };
  75
  76 static const uint32_t skl_primary_formats[] = {
  77         DRM_FORMAT_C8,
  78         DRM_FORMAT_RGB565,
  79         DRM_FORMAT_XRGB8888,
  80         DRM_FORMAT_XBGR8888,
  81         DRM_FORMAT_ARGB8888,
  82         DRM_FORMAT_ABGR8888,
  83         DRM_FORMAT_XRGB2101010,
  84         DRM_FORMAT_XBGR2101010,
  85         DRM_FORMAT_YUYV,
  86         DRM_FORMAT_YVYU,
  87         DRM_FORMAT_UYVY,
  88         DRM_FORMAT_VYUY,
  89 };
  90
  91 static const uint32_t skl_pri_planar_formats[] = {
  92         DRM_FORMAT_C8,
  93         DRM_FORMAT_RGB565,
  94         DRM_FORMAT_XRGB8888,
  95         DRM_FORMAT_XBGR8888,
  96         DRM_FORMAT_ARGB8888,
  97         DRM_FORMAT_ABGR8888,
  98         DRM_FORMAT_XRGB2101010,
  99         DRM_FORMAT_XBGR2101010,
 100         DRM_FORMAT_YUYV,
 101         DRM_FORMAT_YVYU,
 102         DRM_FORMAT_UYVY,
 103         DRM_FORMAT_VYUY,
 104         DRM_FORMAT_NV12,
 105 };
 106
 107 static const uint64_t skl_format_modifiers_noccs[] = {
 108         I915_FORMAT_MOD_Yf_TILED,
 109         I915_FORMAT_MOD_Y_TILED,
 110         I915_FORMAT_MOD_X_TILED,
 111         DRM_FORMAT_MOD_LINEAR,
 112         DRM_FORMAT_MOD_INVALID
 113 };
 114
 115 static const uint64_t skl_format_modifiers_ccs[] = {
 116         I915_FORMAT_MOD_Yf_TILED_CCS,
 117         I915_FORMAT_MOD_Y_TILED_CCS,
 118         I915_FORMAT_MOD_Yf_TILED,
 119         I915_FORMAT_MOD_Y_TILED,
 120         I915_FORMAT_MOD_X_TILED,
 121         DRM_FORMAT_MOD_LINEAR,
 122         DRM_FORMAT_MOD_INVALID
 123 };
 124
 125 /* Cursor formats */
 126 static const uint32_t intel_cursor_formats[] = {
 127         DRM_FORMAT_ARGB8888,
 128 };
 129
 130 static const uint64_t cursor_format_modifiers[] = {
 131         DRM_FORMAT_MOD_LINEAR,
 132         DRM_FORMAT_MOD_INVALID
 133 };
 134
 135 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 136                                 struct intel_crtc_state *pipe_config);
 137 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 138                                    struct intel_crtc_state *pipe_config);
 139
 140 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 141                                   struct drm_i915_gem_object *obj,
 142                                   struct drm_mode_fb_cmd2 *mode_cmd);
 143 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 144 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 145 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 147                                          struct intel_link_m_n *m_n,
 148                                          struct intel_link_m_n *m2_n2);
 149 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 150 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 151 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 152 static void vlv_prepare_pll(struct intel_crtc *crtc,
 153                             const struct intel_crtc_state *pipe_config);
 154 static void chv_prepare_pll(struct intel_crtc *crtc,
 155                             const struct intel_crtc_state *pipe_config);
 156 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 157 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 158 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 159                                     struct intel_crtc_state *crtc_state);
 160 static void skylake_pfit_enable(struct intel_crtc *crtc);
 161 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 162 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 163 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 164                                          struct drm_modeset_acquire_ctx *ctx);
 165 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 166
 167 struct intel_limit {
 168         struct {
 169                 int min, max;
 170         } dot, vco, n, m, m1, m2, p, p1;
 171
 172         struct {
 173                 int dot_limit;
 174                 int p2_slow, p2_fast;
 175         } p2;
 176 };
 177
 178 /* returns HPLL frequency in kHz */
 179 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 180 {
 181         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 182
 183         /* Obtain SKU information */
 184         mutex_lock(&dev_priv->sb_lock);
 185         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 186                 CCK_FUSE_HPLL_FREQ_MASK;
 187         mutex_unlock(&dev_priv->sb_lock);
 188
 189         return vco_freq[hpll_freq] * 1000;
 190 }
 191
 192 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 193                       const char *name, u32 reg, int ref_freq)
 194 {
 195         u32 val;
 196         int divider;
 197
 198         mutex_lock(&dev_priv->sb_lock);
 199         val = vlv_cck_read(dev_priv, reg);
 200         mutex_unlock(&dev_priv->sb_lock);
 201
 202         divider = val & CCK_FREQUENCY_VALUES;
 203
 204         WARN((val & CCK_FREQUENCY_STATUS) !=
 205              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 206              "%s change in progress\n", name);
 207
 208         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 209 }
 210
 211 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 212                            const char *name, u32 reg)
 213 {
 214         if (dev_priv->hpll_freq == 0)
 215                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 216
 217         return vlv_get_cck_clock(dev_priv, name, reg,
 218                                  dev_priv->hpll_freq);
 219 }
 220
 221 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 222 {
 223         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 224                 return;
 225
 226         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 227                                                       CCK_CZ_CLOCK_CONTROL);
 228
 229         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 230 }
 231
 232 static inline u32 /* units of 100MHz */
 233 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 234                     const struct intel_crtc_state *pipe_config)
 235 {
 236         if (HAS_DDI(dev_priv))
 237                 return pipe_config->port_clock; /* SPLL */
 238         else
 239                 return dev_priv->fdi_pll_freq;
 240 }
 241
 242 static const struct intel_limit intel_limits_i8xx_dac = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 908000, .max = 1512000 },
 245         .n = { .min = 2, .max = 16 },
 246         .m = { .min = 96, .max = 140 },
 247         .m1 = { .min = 18, .max = 26 },
 248         .m2 = { .min = 6, .max = 16 },
 249         .p = { .min = 4, .max = 128 },
 250         .p1 = { .min = 2, .max = 33 },
 251         .p2 = { .dot_limit = 165000,
 252                 .p2_slow = 4, .p2_fast = 2 },
 253 };
 254
 255 static const struct intel_limit intel_limits_i8xx_dvo = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 908000, .max = 1512000 },
 258         .n = { .min = 2, .max = 16 },
 259         .m = { .min = 96, .max = 140 },
 260         .m1 = { .min = 18, .max = 26 },
 261         .m2 = { .min = 6, .max = 16 },
 262         .p = { .min = 4, .max = 128 },
 263         .p1 = { .min = 2, .max = 33 },
 264         .p2 = { .dot_limit = 165000,
 265                 .p2_slow = 4, .p2_fast = 4 },
 266 };
 267
 268 static const struct intel_limit intel_limits_i8xx_lvds = {
 269         .dot = { .min = 25000, .max = 350000 },
 270         .vco = { .min = 908000, .max = 1512000 },
 271         .n = { .min = 2, .max = 16 },
 272         .m = { .min = 96, .max = 140 },
 273         .m1 = { .min = 18, .max = 26 },
 274         .m2 = { .min = 6, .max = 16 },
 275         .p = { .min = 4, .max = 128 },
 276         .p1 = { .min = 1, .max = 6 },
 277         .p2 = { .dot_limit = 165000,
 278                 .p2_slow = 14, .p2_fast = 7 },
 279 };
 280
 281 static const struct intel_limit intel_limits_i9xx_sdvo = {
 282         .dot = { .min = 20000, .max = 400000 },
 283         .vco = { .min = 1400000, .max = 2800000 },
 284         .n = { .min = 1, .max = 6 },
 285         .m = { .min = 70, .max = 120 },
 286         .m1 = { .min = 8, .max = 18 },
 287         .m2 = { .min = 3, .max = 7 },
 288         .p = { .min = 5, .max = 80 },
 289         .p1 = { .min = 1, .max = 8 },
 290         .p2 = { .dot_limit = 200000,
 291                 .p2_slow = 10, .p2_fast = 5 },
 292 };
 293
 294 static const struct intel_limit intel_limits_i9xx_lvds = {
 295         .dot = { .min = 20000, .max = 400000 },
 296         .vco = { .min = 1400000, .max = 2800000 },
 297         .n = { .min = 1, .max = 6 },
 298         .m = { .min = 70, .max = 120 },
 299         .m1 = { .min = 8, .max = 18 },
 300         .m2 = { .min = 3, .max = 7 },
 301         .p = { .min = 7, .max = 98 },
 302         .p1 = { .min = 1, .max = 8 },
 303         .p2 = { .dot_limit = 112000,
 304                 .p2_slow = 14, .p2_fast = 7 },
 305 };
 306
 307
 308 static const struct intel_limit intel_limits_g4x_sdvo = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 1750000, .max = 3500000},
 311         .n = { .min = 1, .max = 4 },
 312         .m = { .min = 104, .max = 138 },
 313         .m1 = { .min = 17, .max = 23 },
 314         .m2 = { .min = 5, .max = 11 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 1, .max = 3},
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 10,
 319                 .p2_fast = 10
 320         },
 321 };
 322
 323 static const struct intel_limit intel_limits_g4x_hdmi = {
 324         .dot = { .min = 22000, .max = 400000 },
 325         .vco = { .min = 1750000, .max = 3500000},
 326         .n = { .min = 1, .max = 4 },
 327         .m = { .min = 104, .max = 138 },
 328         .m1 = { .min = 16, .max = 23 },
 329         .m2 = { .min = 5, .max = 11 },
 330         .p = { .min = 5, .max = 80 },
 331         .p1 = { .min = 1, .max = 8},
 332         .p2 = { .dot_limit = 165000,
 333                 .p2_slow = 10, .p2_fast = 5 },
 334 };
 335
 336 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 337         .dot = { .min = 20000, .max = 115000 },
 338         .vco = { .min = 1750000, .max = 3500000 },
 339         .n = { .min = 1, .max = 3 },
 340         .m = { .min = 104, .max = 138 },
 341         .m1 = { .min = 17, .max = 23 },
 342         .m2 = { .min = 5, .max = 11 },
 343         .p = { .min = 28, .max = 112 },
 344         .p1 = { .min = 2, .max = 8 },
 345         .p2 = { .dot_limit = 0,
 346                 .p2_slow = 14, .p2_fast = 14
 347         },
 348 };
 349
 350 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 351         .dot = { .min = 80000, .max = 224000 },
 352         .vco = { .min = 1750000, .max = 3500000 },
 353         .n = { .min = 1, .max = 3 },
 354         .m = { .min = 104, .max = 138 },
 355         .m1 = { .min = 17, .max = 23 },
 356         .m2 = { .min = 5, .max = 11 },
 357         .p = { .min = 14, .max = 42 },
 358         .p1 = { .min = 2, .max = 6 },
 359         .p2 = { .dot_limit = 0,
 360                 .p2_slow = 7, .p2_fast = 7
 361         },
 362 };
 363
 364 static const struct intel_limit intel_limits_pineview_sdvo = {
 365         .dot = { .min = 20000, .max = 400000},
 366         .vco = { .min = 1700000, .max = 3500000 },
 367         /* Pineview's Ncounter is a ring counter */
 368         .n = { .min = 3, .max = 6 },
 369         .m = { .min = 2, .max = 256 },
 370         /* Pineview only has one combined m divider, which we treat as m2. */
 371         .m1 = { .min = 0, .max = 0 },
 372         .m2 = { .min = 0, .max = 254 },
 373         .p = { .min = 5, .max = 80 },
 374         .p1 = { .min = 1, .max = 8 },
 375         .p2 = { .dot_limit = 200000,
 376                 .p2_slow = 10, .p2_fast = 5 },
 377 };
 378
 379 static const struct intel_limit intel_limits_pineview_lvds = {
 380         .dot = { .min = 20000, .max = 400000 },
 381         .vco = { .min = 1700000, .max = 3500000 },
 382         .n = { .min = 3, .max = 6 },
 383         .m = { .min = 2, .max = 256 },
 384         .m1 = { .min = 0, .max = 0 },
 385         .m2 = { .min = 0, .max = 254 },
 386         .p = { .min = 7, .max = 112 },
 387         .p1 = { .min = 1, .max = 8 },
 388         .p2 = { .dot_limit = 112000,
 389                 .p2_slow = 14, .p2_fast = 14 },
 390 };
 391
 392 /* Ironlake / Sandybridge
 393  *
 394  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 395  * the range value for them is (actual_value - 2).
 396  */
 397 static const struct intel_limit intel_limits_ironlake_dac = {
 398         .dot = { .min = 25000, .max = 350000 },
 399         .vco = { .min = 1760000, .max = 3510000 },
 400         .n = { .min = 1, .max = 5 },
 401         .m = { .min = 79, .max = 127 },
 402         .m1 = { .min = 12, .max = 22 },
 403         .m2 = { .min = 5, .max = 9 },
 404         .p = { .min = 5, .max = 80 },
 405         .p1 = { .min = 1, .max = 8 },
 406         .p2 = { .dot_limit = 225000,
 407                 .p2_slow = 10, .p2_fast = 5 },
 408 };
 409
 410 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 411         .dot = { .min = 25000, .max = 350000 },
 412         .vco = { .min = 1760000, .max = 3510000 },
 413         .n = { .min = 1, .max = 3 },
 414         .m = { .min = 79, .max = 118 },
 415         .m1 = { .min = 12, .max = 22 },
 416         .m2 = { .min = 5, .max = 9 },
 417         .p = { .min = 28, .max = 112 },
 418         .p1 = { .min = 2, .max = 8 },
 419         .p2 = { .dot_limit = 225000,
 420                 .p2_slow = 14, .p2_fast = 14 },
 421 };
 422
 423 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 424         .dot = { .min = 25000, .max = 350000 },
 425         .vco = { .min = 1760000, .max = 3510000 },
 426         .n = { .min = 1, .max = 3 },
 427         .m = { .min = 79, .max = 127 },
 428         .m1 = { .min = 12, .max = 22 },
 429         .m2 = { .min = 5, .max = 9 },
 430         .p = { .min = 14, .max = 56 },
 431         .p1 = { .min = 2, .max = 8 },
 432         .p2 = { .dot_limit = 225000,
 433                 .p2_slow = 7, .p2_fast = 7 },
 434 };
 435
 436 /* LVDS 100mhz refclk limits. */
 437 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 438         .dot = { .min = 25000, .max = 350000 },
 439         .vco = { .min = 1760000, .max = 3510000 },
 440         .n = { .min = 1, .max = 2 },
 441         .m = { .min = 79, .max = 126 },
 442         .m1 = { .min = 12, .max = 22 },
 443         .m2 = { .min = 5, .max = 9 },
 444         .p = { .min = 28, .max = 112 },
 445         .p1 = { .min = 2, .max = 8 },
 446         .p2 = { .dot_limit = 225000,
 447                 .p2_slow = 14, .p2_fast = 14 },
 448 };
 449
 450 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 451         .dot = { .min = 25000, .max = 350000 },
 452         .vco = { .min = 1760000, .max = 3510000 },
 453         .n = { .min = 1, .max = 3 },
 454         .m = { .min = 79, .max = 126 },
 455         .m1 = { .min = 12, .max = 22 },
 456         .m2 = { .min = 5, .max = 9 },
 457         .p = { .min = 14, .max = 42 },
 458         .p1 = { .min = 2, .max = 6 },
 459         .p2 = { .dot_limit = 225000,
 460                 .p2_slow = 7, .p2_fast = 7 },
 461 };
 462
 463 static const struct intel_limit intel_limits_vlv = {
 464          /*
 465           * These are the data rate limits (measured in fast clocks)
 466           * since those are the strictest limits we have. The fast
 467           * clock and actual rate limits are more relaxed, so checking
 468           * them would make no difference.
 469           */
 470         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 471         .vco = { .min = 4000000, .max = 6000000 },
 472         .n = { .min = 1, .max = 7 },
 473         .m1 = { .min = 2, .max = 3 },
 474         .m2 = { .min = 11, .max = 156 },
 475         .p1 = { .min = 2, .max = 3 },
 476         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 477 };
 478
 479 static const struct intel_limit intel_limits_chv = {
 480         /*
 481          * These are the data rate limits (measured in fast clocks)
 482          * since those are the strictest limits we have.  The fast
 483          * clock and actual rate limits are more relaxed, so checking
 484          * them would make no difference.
 485          */
 486         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 487         .vco = { .min = 4800000, .max = 6480000 },
 488         .n = { .min = 1, .max = 1 },
 489         .m1 = { .min = 2, .max = 2 },
 490         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 491         .p1 = { .min = 2, .max = 4 },
 492         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 493 };
 494
 495 static const struct intel_limit intel_limits_bxt = {
 496         /* FIXME: find real dot limits */
 497         .dot = { .min = 0, .max = INT_MAX },
 498         .vco = { .min = 4800000, .max = 6700000 },
 499         .n = { .min = 1, .max = 1 },
 500         .m1 = { .min = 2, .max = 2 },
 501         /* FIXME: find real m2 limits */
 502         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 503         .p1 = { .min = 2, .max = 4 },
 504         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 505 };
 506
 507 static void
 508 skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
 509 {
 510         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
 511                 return;
 512
 513         if (enable)
 514                 I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
 515         else
 516                 I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
 517 }
 518
 519 static void
 520 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
 521 {
 522         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
 523                 return;
 524
 525         if (enable)
 526                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 527                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 528         else
 529                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 530                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 531                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 532 }
 533
 534 static bool
 535 needs_modeset(const struct drm_crtc_state *state)
 536 {
 537         return drm_atomic_crtc_needs_modeset(state);
 538 }
 539
 540 /*
 541  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 542  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 543  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 544  * The helpers' return value is the rate of the clock that is fed to the
 545  * display engine's pipe which can be the above fast dot clock rate or a
 546  * divided-down version of it.
 547  */
 548 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 549 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 550 {
 551         clock->m = clock->m2 + 2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return 0;
 555         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 556         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 557
 558         return clock->dot;
 559 }
 560
 561 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 562 {
 563         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 564 }
 565
 566 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 567 {
 568         clock->m = i9xx_dpll_compute_m(clock);
 569         clock->p = clock->p1 * clock->p2;
 570         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 571                 return 0;
 572         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 573         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 574
 575         return clock->dot;
 576 }
 577
 578 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 579 {
 580         clock->m = clock->m1 * clock->m2;
 581         clock->p = clock->p1 * clock->p2;
 582         if (WARN_ON(clock->n == 0 || clock->p == 0))
 583                 return 0;
 584         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 585         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 586
 587         return clock->dot / 5;
 588 }
 589
 590 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 591 {
 592         clock->m = clock->m1 * clock->m2;
 593         clock->p = clock->p1 * clock->p2;
 594         if (WARN_ON(clock->n == 0 || clock->p == 0))
 595                 return 0;
 596         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 597                         clock->n << 22);
 598         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 599
 600         return clock->dot / 5;
 601 }
 602
 603 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 604
 605 /*
 606  * Returns whether the given set of divisors are valid for a given refclk with
 607  * the given connectors.
 608  */
 609 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 610                                const struct intel_limit *limit,
 611                                const struct dpll *clock)
 612 {
 613         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 614                 INTELPllInvalid("n out of range\n");
 615         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 616                 INTELPllInvalid("p1 out of range\n");
 617         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 618                 INTELPllInvalid("m2 out of range\n");
 619         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 620                 INTELPllInvalid("m1 out of range\n");
 621
 622         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 623             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 624                 if (clock->m1 <= clock->m2)
 625                         INTELPllInvalid("m1 <= m2\n");
 626
 627         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 628             !IS_GEN9_LP(dev_priv)) {
 629                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 630                         INTELPllInvalid("p out of range\n");
 631                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 632                         INTELPllInvalid("m out of range\n");
 633         }
 634
 635         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 636                 INTELPllInvalid("vco out of range\n");
 637         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 638          * connector, etc., rather than just a single range.
 639          */
 640         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 641                 INTELPllInvalid("dot out of range\n");
 642
 643         return true;
 644 }
 645
 646 static int
 647 i9xx_select_p2_div(const struct intel_limit *limit,
 648                    const struct intel_crtc_state *crtc_state,
 649                    int target)
 650 {
 651         struct drm_device *dev = crtc_state->base.crtc->dev;
 652
 653         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 654                 /*
 655                  * For LVDS just rely on its current settings for dual-channel.
 656                  * We haven't figured out how to reliably set up different
 657                  * single/dual channel state, if we even can.
 658                  */
 659                 if (intel_is_dual_link_lvds(dev))
 660                         return limit->p2.p2_fast;
 661                 else
 662                         return limit->p2.p2_slow;
 663         } else {
 664                 if (target < limit->p2.dot_limit)
 665                         return limit->p2.p2_slow;
 666                 else
 667                         return limit->p2.p2_fast;
 668         }
 669 }
 670
 671 /*
 672  * Returns a set of divisors for the desired target clock with the given
 673  * refclk, or FALSE.  The returned values represent the clock equation:
 674  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 675  *
 676  * Target and reference clocks are specified in kHz.
 677  *
 678  * If match_clock is provided, then best_clock P divider must match the P
 679  * divider from @match_clock used for LVDS downclocking.
 680  */
 681 static bool
 682 i9xx_find_best_dpll(const struct intel_limit *limit,
 683                     struct intel_crtc_state *crtc_state,
 684                     int target, int refclk, struct dpll *match_clock,
 685                     struct dpll *best_clock)
 686 {
 687         struct drm_device *dev = crtc_state->base.crtc->dev;
 688         struct dpll clock;
 689         int err = target;
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 694
 695         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 696              clock.m1++) {
 697                 for (clock.m2 = limit->m2.min;
 698                      clock.m2 <= limit->m2.max; clock.m2++) {
 699                         if (clock.m2 >= clock.m1)
 700                                 break;
 701                         for (clock.n = limit->n.min;
 702                              clock.n <= limit->n.max; clock.n++) {
 703                                 for (clock.p1 = limit->p1.min;
 704                                         clock.p1 <= limit->p1.max; clock.p1++) {
 705                                         int this_err;
 706
 707                                         i9xx_calc_dpll_params(refclk, &clock);
 708                                         if (!intel_PLL_is_valid(to_i915(dev),
 709                                                                 limit,
 710                                                                 &clock))
 711                                                 continue;
 712                                         if (match_clock &&
 713                                             clock.p != match_clock->p)
 714                                                 continue;
 715
 716                                         this_err = abs(clock.dot - target);
 717                                         if (this_err < err) {
 718                                                 *best_clock = clock;
 719                                                 err = this_err;
 720                                         }
 721                                 }
 722                         }
 723                 }
 724         }
 725
 726         return (err != target);
 727 }
 728
 729 /*
 730  * Returns a set of divisors for the desired target clock with the given
 731  * refclk, or FALSE.  The returned values represent the clock equation:
 732  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 733  *
 734  * Target and reference clocks are specified in kHz.
 735  *
 736  * If match_clock is provided, then best_clock P divider must match the P
 737  * divider from @match_clock used for LVDS downclocking.
 738  */
 739 static bool
 740 pnv_find_best_dpll(const struct intel_limit *limit,
 741                    struct intel_crtc_state *crtc_state,
 742                    int target, int refclk, struct dpll *match_clock,
 743                    struct dpll *best_clock)
 744 {
 745         struct drm_device *dev = crtc_state->base.crtc->dev;
 746         struct dpll clock;
 747         int err = target;
 748
 749         memset(best_clock, 0, sizeof(*best_clock));
 750
 751         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 752
 753         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 754              clock.m1++) {
 755                 for (clock.m2 = limit->m2.min;
 756                      clock.m2 <= limit->m2.max; clock.m2++) {
 757                         for (clock.n = limit->n.min;
 758                              clock.n <= limit->n.max; clock.n++) {
 759                                 for (clock.p1 = limit->p1.min;
 760                                         clock.p1 <= limit->p1.max; clock.p1++) {
 761                                         int this_err;
 762
 763                                         pnv_calc_dpll_params(refclk, &clock);
 764                                         if (!intel_PLL_is_valid(to_i915(dev),
 765                                                                 limit,
 766                                                                 &clock))
 767                                                 continue;
 768                                         if (match_clock &&
 769                                             clock.p != match_clock->p)
 770                                                 continue;
 771
 772                                         this_err = abs(clock.dot - target);
 773                                         if (this_err < err) {
 774                                                 *best_clock = clock;
 775                                                 err = this_err;
 776                                         }
 777                                 }
 778                         }
 779                 }
 780         }
 781
 782         return (err != target);
 783 }
 784
 785 /*
 786  * Returns a set of divisors for the desired target clock with the given
 787  * refclk, or FALSE.  The returned values represent the clock equation:
 788  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 789  *
 790  * Target and reference clocks are specified in kHz.
 791  *
 792  * If match_clock is provided, then best_clock P divider must match the P
 793  * divider from @match_clock used for LVDS downclocking.
 794  */
 795 static bool
 796 g4x_find_best_dpll(const struct intel_limit *limit,
 797                    struct intel_crtc_state *crtc_state,
 798                    int target, int refclk, struct dpll *match_clock,
 799                    struct dpll *best_clock)
 800 {
 801         struct drm_device *dev = crtc_state->base.crtc->dev;
 802         struct dpll clock;
 803         int max_n;
 804         bool found = false;
 805         /* approximately equals target * 0.00585 */
 806         int err_most = (target >> 8) + (target >> 9);
 807
 808         memset(best_clock, 0, sizeof(*best_clock));
 809
 810         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 811
 812         max_n = limit->n.max;
 813         /* based on hardware requirement, prefer smaller n to precision */
 814         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 815                 /* based on hardware requirement, prefere larger m1,m2 */
 816                 for (clock.m1 = limit->m1.max;
 817                      clock.m1 >= limit->m1.min; clock.m1--) {
 818                         for (clock.m2 = limit->m2.max;
 819                              clock.m2 >= limit->m2.min; clock.m2--) {
 820                                 for (clock.p1 = limit->p1.max;
 821                                      clock.p1 >= limit->p1.min; clock.p1--) {
 822                                         int this_err;
 823
 824                                         i9xx_calc_dpll_params(refclk, &clock);
 825                                         if (!intel_PLL_is_valid(to_i915(dev),
 826                                                                 limit,
 827                                                                 &clock))
 828                                                 continue;
 829
 830                                         this_err = abs(clock.dot - target);
 831                                         if (this_err < err_most) {
 832                                                 *best_clock = clock;
 833                                                 err_most = this_err;
 834                                                 max_n = clock.n;
 835                                                 found = true;
 836                                         }
 837                                 }
 838                         }
 839                 }
 840         }
 841         return found;
 842 }
 843
 844 /*
 845  * Check if the calculated PLL configuration is more optimal compared to the
 846  * best configuration and error found so far. Return the calculated error.
 847  */
 848 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 849                                const struct dpll *calculated_clock,
 850                                const struct dpll *best_clock,
 851                                unsigned int best_error_ppm,
 852                                unsigned int *error_ppm)
 853 {
 854         /*
 855          * For CHV ignore the error and consider only the P value.
 856          * Prefer a bigger P value based on HW requirements.
 857          */
 858         if (IS_CHERRYVIEW(to_i915(dev))) {
 859                 *error_ppm = 0;
 860
 861                 return calculated_clock->p > best_clock->p;
 862         }
 863
 864         if (WARN_ON_ONCE(!target_freq))
 865                 return false;
 866
 867         *error_ppm = div_u64(1000000ULL *
 868                                 abs(target_freq - calculated_clock->dot),
 869                              target_freq);
 870         /*
 871          * Prefer a better P value over a better (smaller) error if the error
 872          * is small. Ensure this preference for future configurations too by
 873          * setting the error to 0.
 874          */
 875         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 876                 *error_ppm = 0;
 877
 878                 return true;
 879         }
 880
 881         return *error_ppm + 10 < best_error_ppm;
 882 }
 883
 884 /*
 885  * Returns a set of divisors for the desired target clock with the given
 886  * refclk, or FALSE.  The returned values represent the clock equation:
 887  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 888  */
 889 static bool
 890 vlv_find_best_dpll(const struct intel_limit *limit,
 891                    struct intel_crtc_state *crtc_state,
 892                    int target, int refclk, struct dpll *match_clock,
 893                    struct dpll *best_clock)
 894 {
 895         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 896         struct drm_device *dev = crtc->base.dev;
 897         struct dpll clock;
 898         unsigned int bestppm = 1000000;
 899         /* min update 19.2 MHz */
 900         int max_n = min(limit->n.max, refclk / 19200);
 901         bool found = false;
 902
 903         target *= 5; /* fast clock */
 904
 905         memset(best_clock, 0, sizeof(*best_clock));
 906
 907         /* based on hardware requirement, prefer smaller n to precision */
 908         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 909                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 910                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 911                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 912                                 clock.p = clock.p1 * clock.p2;
 913                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 914                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 915                                         unsigned int ppm;
 916
 917                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 918                                                                      refclk * clock.m1);
 919
 920                                         vlv_calc_dpll_params(refclk, &clock);
 921
 922                                         if (!intel_PLL_is_valid(to_i915(dev),
 923                                                                 limit,
 924                                                                 &clock))
 925                                                 continue;
 926
 927                                         if (!vlv_PLL_is_optimal(dev, target,
 928                                                                 &clock,
 929                                                                 best_clock,
 930                                                                 bestppm, &ppm))
 931                                                 continue;
 932
 933                                         *best_clock = clock;
 934                                         bestppm = ppm;
 935                                         found = true;
 936                                 }
 937                         }
 938                 }
 939         }
 940
 941         return found;
 942 }
 943
 944 /*
 945  * Returns a set of divisors for the desired target clock with the given
 946  * refclk, or FALSE.  The returned values represent the clock equation:
 947  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 948  */
 949 static bool
 950 chv_find_best_dpll(const struct intel_limit *limit,
 951                    struct intel_crtc_state *crtc_state,
 952                    int target, int refclk, struct dpll *match_clock,
 953                    struct dpll *best_clock)
 954 {
 955         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 956         struct drm_device *dev = crtc->base.dev;
 957         unsigned int best_error_ppm;
 958         struct dpll clock;
 959         uint64_t m2;
 960         int found = false;
 961
 962         memset(best_clock, 0, sizeof(*best_clock));
 963         best_error_ppm = 1000000;
 964
 965         /*
 966          * Based on hardware doc, the n always set to 1, and m1 always
 967          * set to 2.  If requires to support 200Mhz refclk, we need to
 968          * revisit this because n may not 1 anymore.
 969          */
 970         clock.n = 1, clock.m1 = 2;
 971         target *= 5;    /* fast clock */
 972
 973         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 974                 for (clock.p2 = limit->p2.p2_fast;
 975                                 clock.p2 >= limit->p2.p2_slow;
 976                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 977                         unsigned int error_ppm;
 978
 979                         clock.p = clock.p1 * clock.p2;
 980
 981                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 982                                         clock.n) << 22, refclk * clock.m1);
 983
 984                         if (m2 > INT_MAX/clock.m1)
 985                                 continue;
 986
 987                         clock.m2 = m2;
 988
 989                         chv_calc_dpll_params(refclk, &clock);
 990
 991                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 992                                 continue;
 993
 994                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 995                                                 best_error_ppm, &error_ppm))
 996                                 continue;
 997
 998                         *best_clock = clock;
 999                         best_error_ppm = error_ppm;
1000                         found = true;
1001                 }
1002         }
1003
1004         return found;
1005 }
1006
1007 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1008                         struct dpll *best_clock)
1009 {
1010         int refclk = 100000;
1011         const struct intel_limit *limit = &intel_limits_bxt;
1012
1013         return chv_find_best_dpll(limit, crtc_state,
1014                                   target_clock, refclk, NULL, best_clock);
1015 }
1016
1017 bool intel_crtc_active(struct intel_crtc *crtc)
1018 {
1019         /* Be paranoid as we can arrive here with only partial
1020          * state retrieved from the hardware during setup.
1021          *
1022          * We can ditch the adjusted_mode.crtc_clock check as soon
1023          * as Haswell has gained clock readout/fastboot support.
1024          *
1025          * We can ditch the crtc->primary->fb check as soon as we can
1026          * properly reconstruct framebuffers.
1027          *
1028          * FIXME: The intel_crtc->active here should be switched to
1029          * crtc->state->active once we have proper CRTC states wired up
1030          * for atomic.
1031          */
1032         return crtc->active && crtc->base.primary->state->fb &&
1033                 crtc->config->base.adjusted_mode.crtc_clock;
1034 }
1035
1036 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1037                                              enum pipe pipe)
1038 {
1039         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1040
1041         return crtc->config->cpu_transcoder;
1042 }
1043
1044 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1045                                     enum pipe pipe)
1046 {
1047         i915_reg_t reg = PIPEDSL(pipe);
1048         u32 line1, line2;
1049         u32 line_mask;
1050
1051         if (IS_GEN2(dev_priv))
1052                 line_mask = DSL_LINEMASK_GEN2;
1053         else
1054                 line_mask = DSL_LINEMASK_GEN3;
1055
1056         line1 = I915_READ(reg) & line_mask;
1057         msleep(5);
1058         line2 = I915_READ(reg) & line_mask;
1059
1060         return line1 != line2;
1061 }
1062
1063 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1064 {
1065         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1066         enum pipe pipe = crtc->pipe;
1067
1068         /* Wait for the display line to settle/start moving */
1069         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1070                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1071                           pipe_name(pipe), onoff(state));
1072 }
1073
1074 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1075 {
1076         wait_for_pipe_scanline_moving(crtc, false);
1077 }
1078
1079 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1080 {
1081         wait_for_pipe_scanline_moving(crtc, true);
1082 }
1083
1084 static void
1085 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1086 {
1087         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1088         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1089
1090         if (INTEL_GEN(dev_priv) >= 4) {
1091                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1092                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1093
1094                 /* Wait for the Pipe State to go off */
1095                 if (intel_wait_for_register(dev_priv,
1096                                             reg, I965_PIPECONF_ACTIVE, 0,
1097                                             100))
1098                         WARN(1, "pipe_off wait timed out\n");
1099         } else {
1100                 intel_wait_for_pipe_scanline_stopped(crtc);
1101         }
1102 }
1103
1104 /* Only for pre-ILK configs */
1105 void assert_pll(struct drm_i915_private *dev_priv,
1106                 enum pipe pipe, bool state)
1107 {
1108         u32 val;
1109         bool cur_state;
1110
1111         val = I915_READ(DPLL(pipe));
1112         cur_state = !!(val & DPLL_VCO_ENABLE);
1113         I915_STATE_WARN(cur_state != state,
1114              "PLL state assertion failure (expected %s, current %s)\n",
1115                         onoff(state), onoff(cur_state));
1116 }
1117
1118 /* XXX: the dsi pll is shared between MIPI DSI ports */
1119 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1120 {
1121         u32 val;
1122         bool cur_state;
1123
1124         mutex_lock(&dev_priv->sb_lock);
1125         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1126         mutex_unlock(&dev_priv->sb_lock);
1127
1128         cur_state = val & DSI_PLL_VCO_EN;
1129         I915_STATE_WARN(cur_state != state,
1130              "DSI PLL state assertion failure (expected %s, current %s)\n",
1131                         onoff(state), onoff(cur_state));
1132 }
1133
1134 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1135                           enum pipe pipe, bool state)
1136 {
1137         bool cur_state;
1138         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1139                                                                       pipe);
1140
1141         if (HAS_DDI(dev_priv)) {
1142                 /* DDI does not have a specific FDI_TX register */
1143                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1144                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1145         } else {
1146                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1147                 cur_state = !!(val & FDI_TX_ENABLE);
1148         }
1149         I915_STATE_WARN(cur_state != state,
1150              "FDI TX state assertion failure (expected %s, current %s)\n",
1151                         onoff(state), onoff(cur_state));
1152 }
1153 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1154 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1155
1156 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1157                           enum pipe pipe, bool state)
1158 {
1159         u32 val;
1160         bool cur_state;
1161
1162         val = I915_READ(FDI_RX_CTL(pipe));
1163         cur_state = !!(val & FDI_RX_ENABLE);
1164         I915_STATE_WARN(cur_state != state,
1165              "FDI RX state assertion failure (expected %s, current %s)\n",
1166                         onoff(state), onoff(cur_state));
1167 }
1168 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1169 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1170
1171 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1172                                       enum pipe pipe)
1173 {
1174         u32 val;
1175
1176         /* ILK FDI PLL is always enabled */
1177         if (IS_GEN5(dev_priv))
1178                 return;
1179
1180         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1181         if (HAS_DDI(dev_priv))
1182                 return;
1183
1184         val = I915_READ(FDI_TX_CTL(pipe));
1185         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189                        enum pipe pipe, bool state)
1190 {
1191         u32 val;
1192         bool cur_state;
1193
1194         val = I915_READ(FDI_RX_CTL(pipe));
1195         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1196         I915_STATE_WARN(cur_state != state,
1197              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1198                         onoff(state), onoff(cur_state));
1199 }
1200
1201 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1202 {
1203         i915_reg_t pp_reg;
1204         u32 val;
1205         enum pipe panel_pipe = PIPE_A;
1206         bool locked = true;
1207
1208         if (WARN_ON(HAS_DDI(dev_priv)))
1209                 return;
1210
1211         if (HAS_PCH_SPLIT(dev_priv)) {
1212                 u32 port_sel;
1213
1214                 pp_reg = PP_CONTROL(0);
1215                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1216
1217                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1218                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1219                         panel_pipe = PIPE_B;
1220                 /* XXX: else fix for eDP */
1221         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1222                 /* presumably write lock depends on pipe, not port select */
1223                 pp_reg = PP_CONTROL(pipe);
1224                 panel_pipe = pipe;
1225         } else {
1226                 pp_reg = PP_CONTROL(0);
1227                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1228                         panel_pipe = PIPE_B;
1229         }
1230
1231         val = I915_READ(pp_reg);
1232         if (!(val & PANEL_POWER_ON) ||
1233             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1234                 locked = false;
1235
1236         I915_STATE_WARN(panel_pipe == pipe && locked,
1237              "panel assertion failure, pipe %c regs locked\n",
1238              pipe_name(pipe));
1239 }
1240
1241 void assert_pipe(struct drm_i915_private *dev_priv,
1242                  enum pipe pipe, bool state)
1243 {
1244         bool cur_state;
1245         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1246                                                                       pipe);
1247         enum intel_display_power_domain power_domain;
1248
1249         /* we keep both pipes enabled on 830 */
1250         if (IS_I830(dev_priv))
1251                 state = true;
1252
1253         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1254         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1255                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1256                 cur_state = !!(val & PIPECONF_ENABLE);
1257
1258                 intel_display_power_put(dev_priv, power_domain);
1259         } else {
1260                 cur_state = false;
1261         }
1262
1263         I915_STATE_WARN(cur_state != state,
1264              "pipe %c assertion failure (expected %s, current %s)\n",
1265                         pipe_name(pipe), onoff(state), onoff(cur_state));
1266 }
1267
1268 static void assert_plane(struct intel_plane *plane, bool state)
1269 {
1270         bool cur_state = plane->get_hw_state(plane);
1271
1272         I915_STATE_WARN(cur_state != state,
1273                         "%s assertion failure (expected %s, current %s)\n",
1274                         plane->base.name, onoff(state), onoff(cur_state));
1275 }
1276
1277 #define assert_plane_enabled(p) assert_plane(p, true)
1278 #define assert_plane_disabled(p) assert_plane(p, false)
1279
1280 static void assert_planes_disabled(struct intel_crtc *crtc)
1281 {
1282         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1283         struct intel_plane *plane;
1284
1285         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1286                 assert_plane_disabled(plane);
1287 }
1288
1289 static void assert_vblank_disabled(struct drm_crtc *crtc)
1290 {
1291         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1292                 drm_crtc_vblank_put(crtc);
1293 }
1294
1295 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1296                                     enum pipe pipe)
1297 {
1298         u32 val;
1299         bool enabled;
1300
1301         val = I915_READ(PCH_TRANSCONF(pipe));
1302         enabled = !!(val & TRANS_ENABLE);
1303         I915_STATE_WARN(enabled,
1304              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1305              pipe_name(pipe));
1306 }
1307
1308 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1309                             enum pipe pipe, u32 port_sel, u32 val)
1310 {
1311         if ((val & DP_PORT_EN) == 0)
1312                 return false;
1313
1314         if (HAS_PCH_CPT(dev_priv)) {
1315                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1316                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1317                         return false;
1318         } else if (IS_CHERRYVIEW(dev_priv)) {
1319                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1320                         return false;
1321         } else {
1322                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1323                         return false;
1324         }
1325         return true;
1326 }
1327
1328 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1329                               enum pipe pipe, u32 val)
1330 {
1331         if ((val & SDVO_ENABLE) == 0)
1332                 return false;
1333
1334         if (HAS_PCH_CPT(dev_priv)) {
1335                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1336                         return false;
1337         } else if (IS_CHERRYVIEW(dev_priv)) {
1338                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1339                         return false;
1340         } else {
1341                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1342                         return false;
1343         }
1344         return true;
1345 }
1346
1347 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1348                               enum pipe pipe, u32 val)
1349 {
1350         if ((val & LVDS_PORT_EN) == 0)
1351                 return false;
1352
1353         if (HAS_PCH_CPT(dev_priv)) {
1354                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1355                         return false;
1356         } else {
1357                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1358                         return false;
1359         }
1360         return true;
1361 }
1362
1363 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1364                               enum pipe pipe, u32 val)
1365 {
1366         if ((val & ADPA_DAC_ENABLE) == 0)
1367                 return false;
1368         if (HAS_PCH_CPT(dev_priv)) {
1369                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1370                         return false;
1371         } else {
1372                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1373                         return false;
1374         }
1375         return true;
1376 }
1377
1378 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1379                                    enum pipe pipe, i915_reg_t reg,
1380                                    u32 port_sel)
1381 {
1382         u32 val = I915_READ(reg);
1383         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1384              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1385              i915_mmio_reg_offset(reg), pipe_name(pipe));
1386
1387         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1388              && (val & DP_PIPEB_SELECT),
1389              "IBX PCH dp port still using transcoder B\n");
1390 }
1391
1392 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1393                                      enum pipe pipe, i915_reg_t reg)
1394 {
1395         u32 val = I915_READ(reg);
1396         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1397              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1398              i915_mmio_reg_offset(reg), pipe_name(pipe));
1399
1400         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1401              && (val & SDVO_PIPE_B_SELECT),
1402              "IBX PCH hdmi port still using transcoder B\n");
1403 }
1404
1405 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1406                                       enum pipe pipe)
1407 {
1408         u32 val;
1409
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1412         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1413
1414         val = I915_READ(PCH_ADPA);
1415         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1416              "PCH VGA enabled on transcoder %c, should be disabled\n",
1417              pipe_name(pipe));
1418
1419         val = I915_READ(PCH_LVDS);
1420         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1421              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1422              pipe_name(pipe));
1423
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1426         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1427 }
1428
1429 static void _vlv_enable_pll(struct intel_crtc *crtc,
1430                             const struct intel_crtc_state *pipe_config)
1431 {
1432         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1433         enum pipe pipe = crtc->pipe;
1434
1435         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1436         POSTING_READ(DPLL(pipe));
1437         udelay(150);
1438
1439         if (intel_wait_for_register(dev_priv,
1440                                     DPLL(pipe),
1441                                     DPLL_LOCK_VLV,
1442                                     DPLL_LOCK_VLV,
1443                                     1))
1444                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1445 }
1446
1447 static void vlv_enable_pll(struct intel_crtc *crtc,
1448                            const struct intel_crtc_state *pipe_config)
1449 {
1450         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1451         enum pipe pipe = crtc->pipe;
1452
1453         assert_pipe_disabled(dev_priv, pipe);
1454
1455         /* PLL is protected by panel, make sure we can write it */
1456         assert_panel_unlocked(dev_priv, pipe);
1457
1458         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1459                 _vlv_enable_pll(crtc, pipe_config);
1460
1461         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1462         POSTING_READ(DPLL_MD(pipe));
1463 }
1464
1465
1466 static void _chv_enable_pll(struct intel_crtc *crtc,
1467                             const struct intel_crtc_state *pipe_config)
1468 {
1469         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1470         enum pipe pipe = crtc->pipe;
1471         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1472         u32 tmp;
1473
1474         mutex_lock(&dev_priv->sb_lock);
1475
1476         /* Enable back the 10bit clock to display controller */
1477         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1478         tmp |= DPIO_DCLKP_EN;
1479         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1480
1481         mutex_unlock(&dev_priv->sb_lock);
1482
1483         /*
1484          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1485          */
1486         udelay(1);
1487
1488         /* Enable PLL */
1489         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1490
1491         /* Check PLL is locked */
1492         if (intel_wait_for_register(dev_priv,
1493                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1494                                     1))
1495                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1496 }
1497
1498 static void chv_enable_pll(struct intel_crtc *crtc,
1499                            const struct intel_crtc_state *pipe_config)
1500 {
1501         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1502         enum pipe pipe = crtc->pipe;
1503
1504         assert_pipe_disabled(dev_priv, pipe);
1505
1506         /* PLL is protected by panel, make sure we can write it */
1507         assert_panel_unlocked(dev_priv, pipe);
1508
1509         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1510                 _chv_enable_pll(crtc, pipe_config);
1511
1512         if (pipe != PIPE_A) {
1513                 /*
1514                  * WaPixelRepeatModeFixForC0:chv
1515                  *
1516                  * DPLLCMD is AWOL. Use chicken bits to propagate
1517                  * the value from DPLLBMD to either pipe B or C.
1518                  */
1519                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1520                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1521                 I915_WRITE(CBR4_VLV, 0);
1522                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1523
1524                 /*
1525                  * DPLLB VGA mode also seems to cause problems.
1526                  * We should always have it disabled.
1527                  */
1528                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1529         } else {
1530                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1531                 POSTING_READ(DPLL_MD(pipe));
1532         }
1533 }
1534
1535 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1536 {
1537         struct intel_crtc *crtc;
1538         int count = 0;
1539
1540         for_each_intel_crtc(&dev_priv->drm, crtc) {
1541                 count += crtc->base.state->active &&
1542                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1543         }
1544
1545         return count;
1546 }
1547
1548 static void i9xx_enable_pll(struct intel_crtc *crtc,
1549                             const struct intel_crtc_state *crtc_state)
1550 {
1551         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1552         i915_reg_t reg = DPLL(crtc->pipe);
1553         u32 dpll = crtc_state->dpll_hw_state.dpll;
1554         int i;
1555
1556         assert_pipe_disabled(dev_priv, crtc->pipe);
1557
1558         /* PLL is protected by panel, make sure we can write it */
1559         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1560                 assert_panel_unlocked(dev_priv, crtc->pipe);
1561
1562         /* Enable DVO 2x clock on both PLLs if necessary */
1563         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1564                 /*
1565                  * It appears to be important that we don't enable this
1566                  * for the current pipe before otherwise configuring the
1567                  * PLL. No idea how this should be handled if multiple
1568                  * DVO outputs are enabled simultaneosly.
1569                  */
1570                 dpll |= DPLL_DVO_2X_MODE;
1571                 I915_WRITE(DPLL(!crtc->pipe),
1572                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1573         }
1574
1575         /*
1576          * Apparently we need to have VGA mode enabled prior to changing
1577          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1578          * dividers, even though the register value does change.
1579          */
1580         I915_WRITE(reg, 0);
1581
1582         I915_WRITE(reg, dpll);
1583
1584         /* Wait for the clocks to stabilize. */
1585         POSTING_READ(reg);
1586         udelay(150);
1587
1588         if (INTEL_GEN(dev_priv) >= 4) {
1589                 I915_WRITE(DPLL_MD(crtc->pipe),
1590                            crtc_state->dpll_hw_state.dpll_md);
1591         } else {
1592                 /* The pixel multiplier can only be updated once the
1593                  * DPLL is enabled and the clocks are stable.
1594                  *
1595                  * So write it again.
1596                  */
1597                 I915_WRITE(reg, dpll);
1598         }
1599
1600         /* We do this three times for luck */
1601         for (i = 0; i < 3; i++) {
1602                 I915_WRITE(reg, dpll);
1603                 POSTING_READ(reg);
1604                 udelay(150); /* wait for warmup */
1605         }
1606 }
1607
1608 static void i9xx_disable_pll(struct intel_crtc *crtc)
1609 {
1610         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1611         enum pipe pipe = crtc->pipe;
1612
1613         /* Disable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev_priv) &&
1615             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1616             !intel_num_dvo_pipes(dev_priv)) {
1617                 I915_WRITE(DPLL(PIPE_B),
1618                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1619                 I915_WRITE(DPLL(PIPE_A),
1620                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1621         }
1622
1623         /* Don't disable pipe or pipe PLLs if needed */
1624         if (IS_I830(dev_priv))
1625                 return;
1626
1627         /* Make sure the pipe isn't still relying on us */
1628         assert_pipe_disabled(dev_priv, pipe);
1629
1630         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1631         POSTING_READ(DPLL(pipe));
1632 }
1633
1634 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1635 {
1636         u32 val;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         val = DPLL_INTEGRATED_REF_CLK_VLV |
1642                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1643         if (pipe != PIPE_A)
1644                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1645
1646         I915_WRITE(DPLL(pipe), val);
1647         POSTING_READ(DPLL(pipe));
1648 }
1649
1650 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1651 {
1652         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1653         u32 val;
1654
1655         /* Make sure the pipe isn't still relying on us */
1656         assert_pipe_disabled(dev_priv, pipe);
1657
1658         val = DPLL_SSC_REF_CLK_CHV |
1659                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1660         if (pipe != PIPE_A)
1661                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1662
1663         I915_WRITE(DPLL(pipe), val);
1664         POSTING_READ(DPLL(pipe));
1665
1666         mutex_lock(&dev_priv->sb_lock);
1667
1668         /* Disable 10bit clock to display controller */
1669         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1670         val &= ~DPIO_DCLKP_EN;
1671         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1672
1673         mutex_unlock(&dev_priv->sb_lock);
1674 }
1675
1676 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1677                          struct intel_digital_port *dport,
1678                          unsigned int expected_mask)
1679 {
1680         u32 port_mask;
1681         i915_reg_t dpll_reg;
1682
1683         switch (dport->base.port) {
1684         case PORT_B:
1685                 port_mask = DPLL_PORTB_READY_MASK;
1686                 dpll_reg = DPLL(0);
1687                 break;
1688         case PORT_C:
1689                 port_mask = DPLL_PORTC_READY_MASK;
1690                 dpll_reg = DPLL(0);
1691                 expected_mask <<= 4;
1692                 break;
1693         case PORT_D:
1694                 port_mask = DPLL_PORTD_READY_MASK;
1695                 dpll_reg = DPIO_PHY_STATUS;
1696                 break;
1697         default:
1698                 BUG();
1699         }
1700
1701         if (intel_wait_for_register(dev_priv,
1702                                     dpll_reg, port_mask, expected_mask,
1703                                     1000))
1704                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1705                      port_name(dport->base.port),
1706                      I915_READ(dpll_reg) & port_mask, expected_mask);
1707 }
1708
1709 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1710                                            enum pipe pipe)
1711 {
1712         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1713                                                                 pipe);
1714         i915_reg_t reg;
1715         uint32_t val, pipeconf_val;
1716
1717         /* Make sure PCH DPLL is enabled */
1718         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1719
1720         /* FDI must be feeding us bits for PCH ports */
1721         assert_fdi_tx_enabled(dev_priv, pipe);
1722         assert_fdi_rx_enabled(dev_priv, pipe);
1723
1724         if (HAS_PCH_CPT(dev_priv)) {
1725                 /* Workaround: Set the timing override bit before enabling the
1726                  * pch transcoder. */
1727                 reg = TRANS_CHICKEN2(pipe);
1728                 val = I915_READ(reg);
1729                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1730                 I915_WRITE(reg, val);
1731         }
1732
1733         reg = PCH_TRANSCONF(pipe);
1734         val = I915_READ(reg);
1735         pipeconf_val = I915_READ(PIPECONF(pipe));
1736
1737         if (HAS_PCH_IBX(dev_priv)) {
1738                 /*
1739                  * Make the BPC in transcoder be consistent with
1740                  * that in pipeconf reg. For HDMI we must use 8bpc
1741                  * here for both 8bpc and 12bpc.
1742                  */
1743                 val &= ~PIPECONF_BPC_MASK;
1744                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1745                         val |= PIPECONF_8BPC;
1746                 else
1747                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1748         }
1749
1750         val &= ~TRANS_INTERLACE_MASK;
1751         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1752                 if (HAS_PCH_IBX(dev_priv) &&
1753                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1754                         val |= TRANS_LEGACY_INTERLACED_ILK;
1755                 else
1756                         val |= TRANS_INTERLACED;
1757         else
1758                 val |= TRANS_PROGRESSIVE;
1759
1760         I915_WRITE(reg, val | TRANS_ENABLE);
1761         if (intel_wait_for_register(dev_priv,
1762                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1763                                     100))
1764                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1765 }
1766
1767 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1768                                       enum transcoder cpu_transcoder)
1769 {
1770         u32 val, pipeconf_val;
1771
1772         /* FDI must be feeding us bits for PCH ports */
1773         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1774         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1775
1776         /* Workaround: set timing override bit. */
1777         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1778         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1779         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1780
1781         val = TRANS_ENABLE;
1782         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1783
1784         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1785             PIPECONF_INTERLACED_ILK)
1786                 val |= TRANS_INTERLACED;
1787         else
1788                 val |= TRANS_PROGRESSIVE;
1789
1790         I915_WRITE(LPT_TRANSCONF, val);
1791         if (intel_wait_for_register(dev_priv,
1792                                     LPT_TRANSCONF,
1793                                     TRANS_STATE_ENABLE,
1794                                     TRANS_STATE_ENABLE,
1795                                     100))
1796                 DRM_ERROR("Failed to enable PCH transcoder\n");
1797 }
1798
1799 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1800                                             enum pipe pipe)
1801 {
1802         i915_reg_t reg;
1803         uint32_t val;
1804
1805         /* FDI relies on the transcoder */
1806         assert_fdi_tx_disabled(dev_priv, pipe);
1807         assert_fdi_rx_disabled(dev_priv, pipe);
1808
1809         /* Ports must be off as well */
1810         assert_pch_ports_disabled(dev_priv, pipe);
1811
1812         reg = PCH_TRANSCONF(pipe);
1813         val = I915_READ(reg);
1814         val &= ~TRANS_ENABLE;
1815         I915_WRITE(reg, val);
1816         /* wait for PCH transcoder off, transcoder state */
1817         if (intel_wait_for_register(dev_priv,
1818                                     reg, TRANS_STATE_ENABLE, 0,
1819                                     50))
1820                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1821
1822         if (HAS_PCH_CPT(dev_priv)) {
1823                 /* Workaround: Clear the timing override chicken bit again. */
1824                 reg = TRANS_CHICKEN2(pipe);
1825                 val = I915_READ(reg);
1826                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1827                 I915_WRITE(reg, val);
1828         }
1829 }
1830
1831 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1832 {
1833         u32 val;
1834
1835         val = I915_READ(LPT_TRANSCONF);
1836         val &= ~TRANS_ENABLE;
1837         I915_WRITE(LPT_TRANSCONF, val);
1838         /* wait for PCH transcoder off, transcoder state */
1839         if (intel_wait_for_register(dev_priv,
1840                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1841                                     50))
1842                 DRM_ERROR("Failed to disable PCH transcoder\n");
1843
1844         /* Workaround: clear timing override bit. */
1845         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1846         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1847         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1848 }
1849
1850 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1851 {
1852         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1853
1854         if (HAS_PCH_LPT(dev_priv))
1855                 return PIPE_A;
1856         else
1857                 return crtc->pipe;
1858 }
1859
1860 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1861 {
1862         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1863         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1864         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1865         enum pipe pipe = crtc->pipe;
1866         i915_reg_t reg;
1867         u32 val;
1868
1869         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1870
1871         assert_planes_disabled(crtc);
1872
1873         /*
1874          * A pipe without a PLL won't actually be able to drive bits from
1875          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1876          * need the check.
1877          */
1878         if (HAS_GMCH_DISPLAY(dev_priv)) {
1879                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1880                         assert_dsi_pll_enabled(dev_priv);
1881                 else
1882                         assert_pll_enabled(dev_priv, pipe);
1883         } else {
1884                 if (new_crtc_state->has_pch_encoder) {
1885                         /* if driving the PCH, we need FDI enabled */
1886                         assert_fdi_rx_pll_enabled(dev_priv,
1887                                                   intel_crtc_pch_transcoder(crtc));
1888                         assert_fdi_tx_pll_enabled(dev_priv,
1889                                                   (enum pipe) cpu_transcoder);
1890                 }
1891                 /* FIXME: assert CPU port conditions for SNB+ */
1892         }
1893
1894         reg = PIPECONF(cpu_transcoder);
1895         val = I915_READ(reg);
1896         if (val & PIPECONF_ENABLE) {
1897                 /* we keep both pipes enabled on 830 */
1898                 WARN_ON(!IS_I830(dev_priv));
1899                 return;
1900         }
1901
1902         I915_WRITE(reg, val | PIPECONF_ENABLE);
1903         POSTING_READ(reg);
1904
1905         /*
1906          * Until the pipe starts PIPEDSL reads will return a stale value,
1907          * which causes an apparent vblank timestamp jump when PIPEDSL
1908          * resets to its proper value. That also messes up the frame count
1909          * when it's derived from the timestamps. So let's wait for the
1910          * pipe to start properly before we call drm_crtc_vblank_on()
1911          */
1912         if (dev_priv->drm.max_vblank_count == 0)
1913                 intel_wait_for_pipe_scanline_moving(crtc);
1914 }
1915
1916 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1917 {
1918         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1919         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1920         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1921         enum pipe pipe = crtc->pipe;
1922         i915_reg_t reg;
1923         u32 val;
1924
1925         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1926
1927         /*
1928          * Make sure planes won't keep trying to pump pixels to us,
1929          * or we might hang the display.
1930          */
1931         assert_planes_disabled(crtc);
1932
1933         reg = PIPECONF(cpu_transcoder);
1934         val = I915_READ(reg);
1935         if ((val & PIPECONF_ENABLE) == 0)
1936                 return;
1937
1938         /*
1939          * Double wide has implications for planes
1940          * so best keep it disabled when not needed.
1941          */
1942         if (old_crtc_state->double_wide)
1943                 val &= ~PIPECONF_DOUBLE_WIDE;
1944
1945         /* Don't disable pipe or pipe PLLs if needed */
1946         if (!IS_I830(dev_priv))
1947                 val &= ~PIPECONF_ENABLE;
1948
1949         I915_WRITE(reg, val);
1950         if ((val & PIPECONF_ENABLE) == 0)
1951                 intel_wait_for_pipe_off(old_crtc_state);
1952 }
1953
1954 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1955 {
1956         return IS_GEN2(dev_priv) ? 2048 : 4096;
1957 }
1958
1959 static unsigned int
1960 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1961 {
1962         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1963         unsigned int cpp = fb->format->cpp[plane];
1964
1965         switch (fb->modifier) {
1966         case DRM_FORMAT_MOD_LINEAR:
1967                 return cpp;
1968         case I915_FORMAT_MOD_X_TILED:
1969                 if (IS_GEN2(dev_priv))
1970                         return 128;
1971                 else
1972                         return 512;
1973         case I915_FORMAT_MOD_Y_TILED_CCS:
1974                 if (plane == 1)
1975                         return 128;
1976                 /* fall through */
1977         case I915_FORMAT_MOD_Y_TILED:
1978                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1979                         return 128;
1980                 else
1981                         return 512;
1982         case I915_FORMAT_MOD_Yf_TILED_CCS:
1983                 if (plane == 1)
1984                         return 128;
1985                 /* fall through */
1986         case I915_FORMAT_MOD_Yf_TILED:
1987                 switch (cpp) {
1988                 case 1:
1989                         return 64;
1990                 case 2:
1991                 case 4:
1992                         return 128;
1993                 case 8:
1994                 case 16:
1995                         return 256;
1996                 default:
1997                         MISSING_CASE(cpp);
1998                         return cpp;
1999                 }
2000                 break;
2001         default:
2002                 MISSING_CASE(fb->modifier);
2003                 return cpp;
2004         }
2005 }
2006
2007 static unsigned int
2008 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2009 {
2010         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2011                 return 1;
2012         else
2013                 return intel_tile_size(to_i915(fb->dev)) /
2014                         intel_tile_width_bytes(fb, plane);
2015 }
2016
2017 /* Return the tile dimensions in pixel units */
2018 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2019                             unsigned int *tile_width,
2020                             unsigned int *tile_height)
2021 {
2022         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2023         unsigned int cpp = fb->format->cpp[plane];
2024
2025         *tile_width = tile_width_bytes / cpp;
2026         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2027 }
2028
2029 unsigned int
2030 intel_fb_align_height(const struct drm_framebuffer *fb,
2031                       int plane, unsigned int height)
2032 {
2033         unsigned int tile_height = intel_tile_height(fb, plane);
2034
2035         return ALIGN(height, tile_height);
2036 }
2037
2038 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2039 {
2040         unsigned int size = 0;
2041         int i;
2042
2043         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2044                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2045
2046         return size;
2047 }
2048
2049 static void
2050 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2051                         const struct drm_framebuffer *fb,
2052                         unsigned int rotation)
2053 {
2054         view->type = I915_GGTT_VIEW_NORMAL;
2055         if (drm_rotation_90_or_270(rotation)) {
2056                 view->type = I915_GGTT_VIEW_ROTATED;
2057                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2058         }
2059 }
2060
2061 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2062 {
2063         if (IS_I830(dev_priv))
2064                 return 16 * 1024;
2065         else if (IS_I85X(dev_priv))
2066                 return 256;
2067         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2068                 return 32;
2069         else
2070                 return 4 * 1024;
2071 }
2072
2073 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2074 {
2075         if (INTEL_GEN(dev_priv) >= 9)
2076                 return 256 * 1024;
2077         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2078                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2079                 return 128 * 1024;
2080         else if (INTEL_GEN(dev_priv) >= 4)
2081                 return 4 * 1024;
2082         else
2083                 return 0;
2084 }
2085
2086 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2087                                          int plane)
2088 {
2089         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2090
2091         /* AUX_DIST needs only 4K alignment */
2092         if (plane == 1)
2093                 return 4096;
2094
2095         switch (fb->modifier) {
2096         case DRM_FORMAT_MOD_LINEAR:
2097                 return intel_linear_alignment(dev_priv);
2098         case I915_FORMAT_MOD_X_TILED:
2099                 if (INTEL_GEN(dev_priv) >= 9)
2100                         return 256 * 1024;
2101                 return 0;
2102         case I915_FORMAT_MOD_Y_TILED_CCS:
2103         case I915_FORMAT_MOD_Yf_TILED_CCS:
2104         case I915_FORMAT_MOD_Y_TILED:
2105         case I915_FORMAT_MOD_Yf_TILED:
2106                 return 1 * 1024 * 1024;
2107         default:
2108                 MISSING_CASE(fb->modifier);
2109                 return 0;
2110         }
2111 }
2112
2113 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2114 {
2115         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2116         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2117
2118         return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2119 }
2120
2121 struct i915_vma *
2122 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2123                            unsigned int rotation,
2124                            bool uses_fence,
2125                            unsigned long *out_flags)
2126 {
2127         struct drm_device *dev = fb->dev;
2128         struct drm_i915_private *dev_priv = to_i915(dev);
2129         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2130         struct i915_ggtt_view view;
2131         struct i915_vma *vma;
2132         unsigned int pinctl;
2133         u32 alignment;
2134
2135         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137         alignment = intel_surf_alignment(fb, 0);
2138
2139         intel_fill_fb_ggtt_view(&view, fb, rotation);
2140
2141         /* Note that the w/a also requires 64 PTE of padding following the
2142          * bo. We currently fill all unused PTE with the shadow page and so
2143          * we should always have valid PTE following the scanout preventing
2144          * the VT-d warning.
2145          */
2146         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2147                 alignment = 256 * 1024;
2148
2149         /*
2150          * Global gtt pte registers are special registers which actually forward
2151          * writes to a chunk of system memory. Which means that there is no risk
2152          * that the register values disappear as soon as we call
2153          * intel_runtime_pm_put(), so it is correct to wrap only the
2154          * pin/unpin/fence and not more.
2155          */
2156         intel_runtime_pm_get(dev_priv);
2157
2158         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2159
2160         pinctl = 0;
2161
2162         /* Valleyview is definitely limited to scanning out the first
2163          * 512MiB. Lets presume this behaviour was inherited from the
2164          * g4x display engine and that all earlier gen are similarly
2165          * limited. Testing suggests that it is a little more
2166          * complicated than this. For example, Cherryview appears quite
2167          * happy to scanout from anywhere within its global aperture.
2168          */
2169         if (HAS_GMCH_DISPLAY(dev_priv))
2170                 pinctl |= PIN_MAPPABLE;
2171
2172         vma = i915_gem_object_pin_to_display_plane(obj,
2173                                                    alignment, &view, pinctl);
2174         if (IS_ERR(vma))
2175                 goto err;
2176
2177         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2178                 int ret;
2179
2180                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2181                  * fence, whereas 965+ only requires a fence if using
2182                  * framebuffer compression.  For simplicity, we always, when
2183                  * possible, install a fence as the cost is not that onerous.
2184                  *
2185                  * If we fail to fence the tiled scanout, then either the
2186                  * modeset will reject the change (which is highly unlikely as
2187                  * the affected systems, all but one, do not have unmappable
2188                  * space) or we will not be able to enable full powersaving
2189                  * techniques (also likely not to apply due to various limits
2190                  * FBC and the like impose on the size of the buffer, which
2191                  * presumably we violated anyway with this unmappable buffer).
2192                  * Anyway, it is presumably better to stumble onwards with
2193                  * something and try to run the system in a "less than optimal"
2194                  * mode that matches the user configuration.
2195                  */
2196                 ret = i915_vma_pin_fence(vma);
2197                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2198                         i915_gem_object_unpin_from_display_plane(vma);
2199                         vma = ERR_PTR(ret);
2200                         goto err;
2201                 }
2202
2203                 if (ret == 0 && vma->fence)
2204                         *out_flags |= PLANE_HAS_FENCE;
2205         }
2206
2207         i915_vma_get(vma);
2208 err:
2209         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2210
2211         intel_runtime_pm_put(dev_priv);
2212         return vma;
2213 }
2214
2215 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2216 {
2217         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2218
2219         if (flags & PLANE_HAS_FENCE)
2220                 i915_vma_unpin_fence(vma);
2221         i915_gem_object_unpin_from_display_plane(vma);
2222         i915_vma_put(vma);
2223 }
2224
2225 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2226                           unsigned int rotation)
2227 {
2228         if (drm_rotation_90_or_270(rotation))
2229                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2230         else
2231                 return fb->pitches[plane];
2232 }
2233
2234 /*
2235  * Convert the x/y offsets into a linear offset.
2236  * Only valid with 0/180 degree rotation, which is fine since linear
2237  * offset is only used with linear buffers on pre-hsw and tiled buffers
2238  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2239  */
2240 u32 intel_fb_xy_to_linear(int x, int y,
2241                           const struct intel_plane_state *state,
2242                           int plane)
2243 {
2244         const struct drm_framebuffer *fb = state->base.fb;
2245         unsigned int cpp = fb->format->cpp[plane];
2246         unsigned int pitch = fb->pitches[plane];
2247
2248         return y * pitch + x * cpp;
2249 }
2250
2251 /*
2252  * Add the x/y offsets derived from fb->offsets[] to the user
2253  * specified plane src x/y offsets. The resulting x/y offsets
2254  * specify the start of scanout from the beginning of the gtt mapping.
2255  */
2256 void intel_add_fb_offsets(int *x, int *y,
2257                           const struct intel_plane_state *state,
2258                           int plane)
2259
2260 {
2261         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2262         unsigned int rotation = state->base.rotation;
2263
2264         if (drm_rotation_90_or_270(rotation)) {
2265                 *x += intel_fb->rotated[plane].x;
2266                 *y += intel_fb->rotated[plane].y;
2267         } else {
2268                 *x += intel_fb->normal[plane].x;
2269                 *y += intel_fb->normal[plane].y;
2270         }
2271 }
2272
2273 static u32 __intel_adjust_tile_offset(int *x, int *y,
2274                                       unsigned int tile_width,
2275                                       unsigned int tile_height,
2276                                       unsigned int tile_size,
2277                                       unsigned int pitch_tiles,
2278                                       u32 old_offset,
2279                                       u32 new_offset)
2280 {
2281         unsigned int pitch_pixels = pitch_tiles * tile_width;
2282         unsigned int tiles;
2283
2284         WARN_ON(old_offset & (tile_size - 1));
2285         WARN_ON(new_offset & (tile_size - 1));
2286         WARN_ON(new_offset > old_offset);
2287
2288         tiles = (old_offset - new_offset) / tile_size;
2289
2290         *y += tiles / pitch_tiles * tile_height;
2291         *x += tiles % pitch_tiles * tile_width;
2292
2293         /* minimize x in case it got needlessly big */
2294         *y += *x / pitch_pixels * tile_height;
2295         *x %= pitch_pixels;
2296
2297         return new_offset;
2298 }
2299
2300 static u32 _intel_adjust_tile_offset(int *x, int *y,
2301                                      const struct drm_framebuffer *fb, int plane,
2302                                      unsigned int rotation,
2303                                      u32 old_offset, u32 new_offset)
2304 {
2305         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2306         unsigned int cpp = fb->format->cpp[plane];
2307         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2308
2309         WARN_ON(new_offset > old_offset);
2310
2311         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2312                 unsigned int tile_size, tile_width, tile_height;
2313                 unsigned int pitch_tiles;
2314
2315                 tile_size = intel_tile_size(dev_priv);
2316                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2317
2318                 if (drm_rotation_90_or_270(rotation)) {
2319                         pitch_tiles = pitch / tile_height;
2320                         swap(tile_width, tile_height);
2321                 } else {
2322                         pitch_tiles = pitch / (tile_width * cpp);
2323                 }
2324
2325                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2326                                            tile_size, pitch_tiles,
2327                                            old_offset, new_offset);
2328         } else {
2329                 old_offset += *y * pitch + *x * cpp;
2330
2331                 *y = (old_offset - new_offset) / pitch;
2332                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2333         }
2334
2335         return new_offset;
2336 }
2337
2338 /*
2339  * Adjust the tile offset by moving the difference into
2340  * the x/y offsets.
2341  */
2342 static u32 intel_adjust_tile_offset(int *x, int *y,
2343                                     const struct intel_plane_state *state, int plane,
2344                                     u32 old_offset, u32 new_offset)
2345 {
2346         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2347                                          state->base.rotation,
2348                                          old_offset, new_offset);
2349 }
2350
2351 /*
2352  * Computes the linear offset to the base tile and adjusts
2353  * x, y. bytes per pixel is assumed to be a power-of-two.
2354  *
2355  * In the 90/270 rotated case, x and y are assumed
2356  * to be already rotated to match the rotated GTT view, and
2357  * pitch is the tile_height aligned framebuffer height.
2358  *
2359  * This function is used when computing the derived information
2360  * under intel_framebuffer, so using any of that information
2361  * here is not allowed. Anything under drm_framebuffer can be
2362  * used. This is why the user has to pass in the pitch since it
2363  * is specified in the rotated orientation.
2364  */
2365 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2366                                       int *x, int *y,
2367                                       const struct drm_framebuffer *fb, int plane,
2368                                       unsigned int pitch,
2369                                       unsigned int rotation,
2370                                       u32 alignment)
2371 {
2372         uint64_t fb_modifier = fb->modifier;
2373         unsigned int cpp = fb->format->cpp[plane];
2374         u32 offset, offset_aligned;
2375
2376         if (alignment)
2377                 alignment--;
2378
2379         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2380                 unsigned int tile_size, tile_width, tile_height;
2381                 unsigned int tile_rows, tiles, pitch_tiles;
2382
2383                 tile_size = intel_tile_size(dev_priv);
2384                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2385
2386                 if (drm_rotation_90_or_270(rotation)) {
2387                         pitch_tiles = pitch / tile_height;
2388                         swap(tile_width, tile_height);
2389                 } else {
2390                         pitch_tiles = pitch / (tile_width * cpp);
2391                 }
2392
2393                 tile_rows = *y / tile_height;
2394                 *y %= tile_height;
2395
2396                 tiles = *x / tile_width;
2397                 *x %= tile_width;
2398
2399                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2400                 offset_aligned = offset & ~alignment;
2401
2402                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2403                                            tile_size, pitch_tiles,
2404                                            offset, offset_aligned);
2405         } else {
2406                 offset = *y * pitch + *x * cpp;
2407                 offset_aligned = offset & ~alignment;
2408
2409                 *y = (offset & alignment) / pitch;
2410                 *x = ((offset & alignment) - *y * pitch) / cpp;
2411         }
2412
2413         return offset_aligned;
2414 }
2415
2416 u32 intel_compute_tile_offset(int *x, int *y,
2417                               const struct intel_plane_state *state,
2418                               int plane)
2419 {
2420         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2421         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2422         const struct drm_framebuffer *fb = state->base.fb;
2423         unsigned int rotation = state->base.rotation;
2424         int pitch = intel_fb_pitch(fb, plane, rotation);
2425         u32 alignment;
2426
2427         if (intel_plane->id == PLANE_CURSOR)
2428                 alignment = intel_cursor_alignment(dev_priv);
2429         else
2430                 alignment = intel_surf_alignment(fb, plane);
2431
2432         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2433                                           rotation, alignment);
2434 }
2435
2436 /* Convert the fb->offset[] into x/y offsets */
2437 static int intel_fb_offset_to_xy(int *x, int *y,
2438                                  const struct drm_framebuffer *fb, int plane)
2439 {
2440         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2441
2442         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2443             fb->offsets[plane] % intel_tile_size(dev_priv))
2444                 return -EINVAL;
2445
2446         *x = 0;
2447         *y = 0;
2448
2449         _intel_adjust_tile_offset(x, y,
2450                                   fb, plane, DRM_MODE_ROTATE_0,
2451                                   fb->offsets[plane], 0);
2452
2453         return 0;
2454 }
2455
2456 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2457 {
2458         switch (fb_modifier) {
2459         case I915_FORMAT_MOD_X_TILED:
2460                 return I915_TILING_X;
2461         case I915_FORMAT_MOD_Y_TILED:
2462         case I915_FORMAT_MOD_Y_TILED_CCS:
2463                 return I915_TILING_Y;
2464         default:
2465                 return I915_TILING_NONE;
2466         }
2467 }
2468
2469 /*
2470  * From the Sky Lake PRM:
2471  * "The Color Control Surface (CCS) contains the compression status of
2472  *  the cache-line pairs. The compression state of the cache-line pair
2473  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2474  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2475  *  cache-line-pairs. CCS is always Y tiled."
2476  *
2477  * Since cache line pairs refers to horizontally adjacent cache lines,
2478  * each cache line in the CCS corresponds to an area of 32x16 cache
2479  * lines on the main surface. Since each pixel is 4 bytes, this gives
2480  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2481  * main surface.
2482  */
2483 static const struct drm_format_info ccs_formats[] = {
2484         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2485         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2486         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2487         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2488 };
2489
2490 static const struct drm_format_info *
2491 lookup_format_info(const struct drm_format_info formats[],
2492                    int num_formats, u32 format)
2493 {
2494         int i;
2495
2496         for (i = 0; i < num_formats; i++) {
2497                 if (formats[i].format == format)
2498                         return &formats[i];
2499         }
2500
2501         return NULL;
2502 }
2503
2504 static const struct drm_format_info *
2505 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2506 {
2507         switch (cmd->modifier[0]) {
2508         case I915_FORMAT_MOD_Y_TILED_CCS:
2509         case I915_FORMAT_MOD_Yf_TILED_CCS:
2510                 return lookup_format_info(ccs_formats,
2511                                           ARRAY_SIZE(ccs_formats),
2512                                           cmd->pixel_format);
2513         default:
2514                 return NULL;
2515         }
2516 }
2517
2518 static int
2519 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2520                    struct drm_framebuffer *fb)
2521 {
2522         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2523         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2524         u32 gtt_offset_rotated = 0;
2525         unsigned int max_size = 0;
2526         int i, num_planes = fb->format->num_planes;
2527         unsigned int tile_size = intel_tile_size(dev_priv);
2528
2529         for (i = 0; i < num_planes; i++) {
2530                 unsigned int width, height;
2531                 unsigned int cpp, size;
2532                 u32 offset;
2533                 int x, y;
2534                 int ret;
2535
2536                 cpp = fb->format->cpp[i];
2537                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2538                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2539
2540                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2541                 if (ret) {
2542                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2543                                       i, fb->offsets[i]);
2544                         return ret;
2545                 }
2546
2547                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2548                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2549                         int hsub = fb->format->hsub;
2550                         int vsub = fb->format->vsub;
2551                         int tile_width, tile_height;
2552                         int main_x, main_y;
2553                         int ccs_x, ccs_y;
2554
2555                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2556                         tile_width *= hsub;
2557                         tile_height *= vsub;
2558
2559                         ccs_x = (x * hsub) % tile_width;
2560                         ccs_y = (y * vsub) % tile_height;
2561                         main_x = intel_fb->normal[0].x % tile_width;
2562                         main_y = intel_fb->normal[0].y % tile_height;
2563
2564                         /*
2565                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2566                          * x/y offsets must match between CCS and the main surface.
2567                          */
2568                         if (main_x != ccs_x || main_y != ccs_y) {
2569                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2570                                               main_x, main_y,
2571                                               ccs_x, ccs_y,
2572                                               intel_fb->normal[0].x,
2573                                               intel_fb->normal[0].y,
2574                                               x, y);
2575                                 return -EINVAL;
2576                         }
2577                 }
2578
2579                 /*
2580                  * The fence (if used) is aligned to the start of the object
2581                  * so having the framebuffer wrap around across the edge of the
2582                  * fenced region doesn't really work. We have no API to configure
2583                  * the fence start offset within the object (nor could we probably
2584                  * on gen2/3). So it's just easier if we just require that the
2585                  * fb layout agrees with the fence layout. We already check that the
2586                  * fb stride matches the fence stride elsewhere.
2587                  */
2588                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2589                     (x + width) * cpp > fb->pitches[i]) {
2590                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2591                                       i, fb->offsets[i]);
2592                         return -EINVAL;
2593                 }
2594
2595                 /*
2596                  * First pixel of the framebuffer from
2597                  * the start of the normal gtt mapping.
2598                  */
2599                 intel_fb->normal[i].x = x;
2600                 intel_fb->normal[i].y = y;
2601
2602                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2603                                                     fb, i, fb->pitches[i],
2604                                                     DRM_MODE_ROTATE_0, tile_size);
2605                 offset /= tile_size;
2606
2607                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2608                         unsigned int tile_width, tile_height;
2609                         unsigned int pitch_tiles;
2610                         struct drm_rect r;
2611
2612                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2613
2614                         rot_info->plane[i].offset = offset;
2615                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2616                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2617                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2618
2619                         intel_fb->rotated[i].pitch =
2620                                 rot_info->plane[i].height * tile_height;
2621
2622                         /* how many tiles does this plane need */
2623                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2624                         /*
2625                          * If the plane isn't horizontally tile aligned,
2626                          * we need one more tile.
2627                          */
2628                         if (x != 0)
2629                                 size++;
2630
2631                         /* rotate the x/y offsets to match the GTT view */
2632                         r.x1 = x;
2633                         r.y1 = y;
2634                         r.x2 = x + width;
2635                         r.y2 = y + height;
2636                         drm_rect_rotate(&r,
2637                                         rot_info->plane[i].width * tile_width,
2638                                         rot_info->plane[i].height * tile_height,
2639                                         DRM_MODE_ROTATE_270);
2640                         x = r.x1;
2641                         y = r.y1;
2642
2643                         /* rotate the tile dimensions to match the GTT view */
2644                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2645                         swap(tile_width, tile_height);
2646
2647                         /*
2648                          * We only keep the x/y offsets, so push all of the
2649                          * gtt offset into the x/y offsets.
2650                          */
2651                         __intel_adjust_tile_offset(&x, &y,
2652                                                    tile_width, tile_height,
2653                                                    tile_size, pitch_tiles,
2654                                                    gtt_offset_rotated * tile_size, 0);
2655
2656                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2657
2658                         /*
2659                          * First pixel of the framebuffer from
2660                          * the start of the rotated gtt mapping.
2661                          */
2662                         intel_fb->rotated[i].x = x;
2663                         intel_fb->rotated[i].y = y;
2664                 } else {
2665                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2666                                             x * cpp, tile_size);
2667                 }
2668
2669                 /* how many tiles in total needed in the bo */
2670                 max_size = max(max_size, offset + size);
2671         }
2672
2673         if (max_size * tile_size > intel_fb->obj->base.size) {
2674                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2675                               max_size * tile_size, intel_fb->obj->base.size);
2676                 return -EINVAL;
2677         }
2678
2679         return 0;
2680 }
2681
2682 static int i9xx_format_to_fourcc(int format)
2683 {
2684         switch (format) {
2685         case DISPPLANE_8BPP:
2686                 return DRM_FORMAT_C8;
2687         case DISPPLANE_BGRX555:
2688                 return DRM_FORMAT_XRGB1555;
2689         case DISPPLANE_BGRX565:
2690                 return DRM_FORMAT_RGB565;
2691         default:
2692         case DISPPLANE_BGRX888:
2693                 return DRM_FORMAT_XRGB8888;
2694         case DISPPLANE_RGBX888:
2695                 return DRM_FORMAT_XBGR8888;
2696         case DISPPLANE_BGRX101010:
2697                 return DRM_FORMAT_XRGB2101010;
2698         case DISPPLANE_RGBX101010:
2699                 return DRM_FORMAT_XBGR2101010;
2700         }
2701 }
2702
2703 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2704 {
2705         switch (format) {
2706         case PLANE_CTL_FORMAT_RGB_565:
2707                 return DRM_FORMAT_RGB565;
2708         case PLANE_CTL_FORMAT_NV12:
2709                 return DRM_FORMAT_NV12;
2710         default:
2711         case PLANE_CTL_FORMAT_XRGB_8888:
2712                 if (rgb_order) {
2713                         if (alpha)
2714                                 return DRM_FORMAT_ABGR8888;
2715                         else
2716                                 return DRM_FORMAT_XBGR8888;
2717                 } else {
2718                         if (alpha)
2719                                 return DRM_FORMAT_ARGB8888;
2720                         else
2721                                 return DRM_FORMAT_XRGB8888;
2722                 }
2723         case PLANE_CTL_FORMAT_XRGB_2101010:
2724                 if (rgb_order)
2725                         return DRM_FORMAT_XBGR2101010;
2726                 else
2727                         return DRM_FORMAT_XRGB2101010;
2728         }
2729 }
2730
2731 static bool
2732 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2733                               struct intel_initial_plane_config *plane_config)
2734 {
2735         struct drm_device *dev = crtc->base.dev;
2736         struct drm_i915_private *dev_priv = to_i915(dev);
2737         struct drm_i915_gem_object *obj = NULL;
2738         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2739         struct drm_framebuffer *fb = &plane_config->fb->base;
2740         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2741         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2742                                     PAGE_SIZE);
2743
2744         size_aligned -= base_aligned;
2745
2746         if (plane_config->size == 0)
2747                 return false;
2748
2749         /* If the FB is too big, just don't use it since fbdev is not very
2750          * important and we should probably use that space with FBC or other
2751          * features. */
2752         if (size_aligned * 2 > dev_priv->stolen_usable_size)
2753                 return false;
2754
2755         mutex_lock(&dev->struct_mutex);
2756         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2757                                                              base_aligned,
2758                                                              base_aligned,
2759                                                              size_aligned);
2760         mutex_unlock(&dev->struct_mutex);
2761         if (!obj)
2762                 return false;
2763
2764         if (plane_config->tiling == I915_TILING_X)
2765                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2766
2767         mode_cmd.pixel_format = fb->format->format;
2768         mode_cmd.width = fb->width;
2769         mode_cmd.height = fb->height;
2770         mode_cmd.pitches[0] = fb->pitches[0];
2771         mode_cmd.modifier[0] = fb->modifier;
2772         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2773
2774         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2775                 DRM_DEBUG_KMS("intel fb init failed\n");
2776                 goto out_unref_obj;
2777         }
2778
2779
2780         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2781         return true;
2782
2783 out_unref_obj:
2784         i915_gem_object_put(obj);
2785         return false;
2786 }
2787
2788 static void
2789 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2790                         struct intel_plane_state *plane_state,
2791                         bool visible)
2792 {
2793         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2794
2795         plane_state->base.visible = visible;
2796
2797         /* FIXME pre-g4x don't work like this */
2798         if (visible) {
2799                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2800                 crtc_state->active_planes |= BIT(plane->id);
2801         } else {
2802                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2803                 crtc_state->active_planes &= ~BIT(plane->id);
2804         }
2805
2806         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2807                       crtc_state->base.crtc->name,
2808                       crtc_state->active_planes);
2809 }
2810
2811 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2812                                          struct intel_plane *plane)
2813 {
2814         struct intel_crtc_state *crtc_state =
2815                 to_intel_crtc_state(crtc->base.state);
2816         struct intel_plane_state *plane_state =
2817                 to_intel_plane_state(plane->base.state);
2818
2819         intel_set_plane_visible(crtc_state, plane_state, false);
2820
2821         if (plane->id == PLANE_PRIMARY)
2822                 intel_pre_disable_primary_noatomic(&crtc->base);
2823
2824         trace_intel_disable_plane(&plane->base, crtc);
2825         plane->disable_plane(plane, crtc);
2826 }
2827
2828 static void
2829 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2830                              struct intel_initial_plane_config *plane_config)
2831 {
2832         struct drm_device *dev = intel_crtc->base.dev;
2833         struct drm_i915_private *dev_priv = to_i915(dev);
2834         struct drm_crtc *c;
2835         struct drm_i915_gem_object *obj;
2836         struct drm_plane *primary = intel_crtc->base.primary;
2837         struct drm_plane_state *plane_state = primary->state;
2838         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2839         struct intel_plane *intel_plane = to_intel_plane(primary);
2840         struct intel_plane_state *intel_state =
2841                 to_intel_plane_state(plane_state);
2842         struct drm_framebuffer *fb;
2843
2844         if (!plane_config->fb)
2845                 return;
2846
2847         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2848                 fb = &plane_config->fb->base;
2849                 goto valid_fb;
2850         }
2851
2852         kfree(plane_config->fb);
2853
2854         /*
2855          * Failed to alloc the obj, check to see if we should share
2856          * an fb with another CRTC instead
2857          */
2858         for_each_crtc(dev, c) {
2859                 struct intel_plane_state *state;
2860
2861                 if (c == &intel_crtc->base)
2862                         continue;
2863
2864                 if (!to_intel_crtc(c)->active)
2865                         continue;
2866
2867                 state = to_intel_plane_state(c->primary->state);
2868                 if (!state->vma)
2869                         continue;
2870
2871                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2872                         fb = state->base.fb;
2873                         drm_framebuffer_get(fb);
2874                         goto valid_fb;
2875                 }
2876         }
2877
2878         /*
2879          * We've failed to reconstruct the BIOS FB.  Current display state
2880          * indicates that the primary plane is visible, but has a NULL FB,
2881          * which will lead to problems later if we don't fix it up.  The
2882          * simplest solution is to just disable the primary plane now and
2883          * pretend the BIOS never had it enabled.
2884          */
2885         intel_plane_disable_noatomic(intel_crtc, intel_plane);
2886
2887         return;
2888
2889 valid_fb:
2890         mutex_lock(&dev->struct_mutex);
2891         intel_state->vma =
2892                 intel_pin_and_fence_fb_obj(fb,
2893                                            primary->state->rotation,
2894                                            intel_plane_uses_fence(intel_state),
2895                                            &intel_state->flags);
2896         mutex_unlock(&dev->struct_mutex);
2897         if (IS_ERR(intel_state->vma)) {
2898                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2899                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2900
2901                 intel_state->vma = NULL;
2902                 drm_framebuffer_put(fb);
2903                 return;
2904         }
2905
2906         obj = intel_fb_obj(fb);
2907         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2908
2909         plane_state->src_x = 0;
2910         plane_state->src_y = 0;
2911         plane_state->src_w = fb->width << 16;
2912         plane_state->src_h = fb->height << 16;
2913
2914         plane_state->crtc_x = 0;
2915         plane_state->crtc_y = 0;
2916         plane_state->crtc_w = fb->width;
2917         plane_state->crtc_h = fb->height;
2918
2919         intel_state->base.src = drm_plane_state_src(plane_state);
2920         intel_state->base.dst = drm_plane_state_dest(plane_state);
2921
2922         if (i915_gem_object_is_tiled(obj))
2923                 dev_priv->preserve_bios_swizzle = true;
2924
2925         drm_framebuffer_get(fb);
2926         primary->fb = primary->state->fb = fb;
2927         primary->crtc = primary->state->crtc = &intel_crtc->base;
2928
2929         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2930                                 to_intel_plane_state(plane_state),
2931                                 true);
2932
2933         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2934                   &obj->frontbuffer_bits);
2935 }
2936
2937 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2938                                unsigned int rotation)
2939 {
2940         int cpp = fb->format->cpp[plane];
2941
2942         switch (fb->modifier) {
2943         case DRM_FORMAT_MOD_LINEAR:
2944         case I915_FORMAT_MOD_X_TILED:
2945                 switch (cpp) {
2946                 case 8:
2947                         return 4096;
2948                 case 4:
2949                 case 2:
2950                 case 1:
2951                         return 8192;
2952                 default:
2953                         MISSING_CASE(cpp);
2954                         break;
2955                 }
2956                 break;
2957         case I915_FORMAT_MOD_Y_TILED_CCS:
2958         case I915_FORMAT_MOD_Yf_TILED_CCS:
2959                 /* FIXME AUX plane? */
2960         case I915_FORMAT_MOD_Y_TILED:
2961         case I915_FORMAT_MOD_Yf_TILED:
2962                 switch (cpp) {
2963                 case 8:
2964                         return 2048;
2965                 case 4:
2966                         return 4096;
2967                 case 2:
2968                 case 1:
2969                         return 8192;
2970                 default:
2971                         MISSING_CASE(cpp);
2972                         break;
2973                 }
2974                 break;
2975         default:
2976                 MISSING_CASE(fb->modifier);
2977         }
2978
2979         return 2048;
2980 }
2981
2982 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2983                                            int main_x, int main_y, u32 main_offset)
2984 {
2985         const struct drm_framebuffer *fb = plane_state->base.fb;
2986         int hsub = fb->format->hsub;
2987         int vsub = fb->format->vsub;
2988         int aux_x = plane_state->aux.x;
2989         int aux_y = plane_state->aux.y;
2990         u32 aux_offset = plane_state->aux.offset;
2991         u32 alignment = intel_surf_alignment(fb, 1);
2992
2993         while (aux_offset >= main_offset && aux_y <= main_y) {
2994                 int x, y;
2995
2996                 if (aux_x == main_x && aux_y == main_y)
2997                         break;
2998
2999                 if (aux_offset == 0)
3000                         break;
3001
3002                 x = aux_x / hsub;
3003                 y = aux_y / vsub;
3004                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
3005                                                       aux_offset, aux_offset - alignment);
3006                 aux_x = x * hsub + aux_x % hsub;
3007                 aux_y = y * vsub + aux_y % vsub;
3008         }
3009
3010         if (aux_x != main_x || aux_y != main_y)
3011                 return false;
3012
3013         plane_state->aux.offset = aux_offset;
3014         plane_state->aux.x = aux_x;
3015         plane_state->aux.y = aux_y;
3016
3017         return true;
3018 }
3019
3020 static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
3021                                   struct intel_plane_state *plane_state)
3022 {
3023         struct drm_i915_private *dev_priv =
3024                 to_i915(plane_state->base.plane->dev);
3025         const struct drm_framebuffer *fb = plane_state->base.fb;
3026         unsigned int rotation = plane_state->base.rotation;
3027         int x = plane_state->base.src.x1 >> 16;
3028         int y = plane_state->base.src.y1 >> 16;
3029         int w = drm_rect_width(&plane_state->base.src) >> 16;
3030         int h = drm_rect_height(&plane_state->base.src) >> 16;
3031         int dst_x = plane_state->base.dst.x1;
3032         int pipe_src_w = crtc_state->pipe_src_w;
3033         int max_width = skl_max_plane_width(fb, 0, rotation);
3034         int max_height = 4096;
3035         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3036
3037         if (w > max_width || h > max_height) {
3038                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3039                               w, h, max_width, max_height);
3040                 return -EINVAL;
3041         }
3042
3043         /*
3044          * Display WA #1175: cnl,glk
3045          * Planes other than the cursor may cause FIFO underflow and display
3046          * corruption if starting less than 4 pixels from the right edge of
3047          * the screen.
3048          * Besides the above WA fix the similar problem, where planes other
3049          * than the cursor ending less than 4 pixels from the left edge of the
3050          * screen may cause FIFO underflow and display corruption.
3051          */
3052         if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
3053             (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
3054                 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
3055                               dst_x + w < 4 ? "end" : "start",
3056                               dst_x + w < 4 ? dst_x + w : dst_x,
3057                               4, pipe_src_w - 4);
3058                 return -ERANGE;
3059         }
3060
3061         intel_add_fb_offsets(&x, &y, plane_state, 0);
3062         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3063         alignment = intel_surf_alignment(fb, 0);
3064
3065         /*
3066          * AUX surface offset is specified as the distance from the
3067          * main surface offset, and it must be non-negative. Make
3068          * sure that is what we will get.
3069          */
3070         if (offset > aux_offset)
3071                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3072                                                   offset, aux_offset & ~(alignment - 1));
3073
3074         /*
3075          * When using an X-tiled surface, the plane blows up
3076          * if the x offset + width exceed the stride.
3077          *
3078          * TODO: linear and Y-tiled seem fine, Yf untested,
3079          */
3080         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3081                 int cpp = fb->format->cpp[0];
3082
3083                 while ((x + w) * cpp > fb->pitches[0]) {
3084                         if (offset == 0) {
3085                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3086                                 return -EINVAL;
3087                         }
3088
3089                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3090                                                           offset, offset - alignment);
3091                 }
3092         }
3093
3094         /*
3095          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3096          * they match with the main surface x/y offsets.
3097          */
3098         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3099             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3100                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3101                         if (offset == 0)
3102                                 break;
3103
3104                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3105                                                           offset, offset - alignment);
3106                 }
3107
3108                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3109                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3110                         return -EINVAL;
3111                 }
3112         }
3113
3114         plane_state->main.offset = offset;
3115         plane_state->main.x = x;
3116         plane_state->main.y = y;
3117
3118         return 0;
3119 }
3120
3121 static int
3122 skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
3123                        struct intel_plane_state *plane_state)
3124 {
3125         /* Display WA #1106 */
3126         if (plane_state->base.rotation !=
3127             (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90) &&
3128             plane_state->base.rotation != DRM_MODE_ROTATE_270)
3129                 return 0;
3130
3131         /*
3132          * src coordinates are rotated here.
3133          * We check height but report it as width
3134          */
3135         if (((drm_rect_height(&plane_state->base.src) >> 16) % 4) != 0) {
3136                 DRM_DEBUG_KMS("src width must be multiple "
3137                               "of 4 for rotated NV12\n");
3138                 return -EINVAL;
3139         }
3140
3141         return 0;
3142 }
3143
3144 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3145 {
3146         const struct drm_framebuffer *fb = plane_state->base.fb;
3147         unsigned int rotation = plane_state->base.rotation;
3148         int max_width = skl_max_plane_width(fb, 1, rotation);
3149         int max_height = 4096;
3150         int x = plane_state->base.src.x1 >> 17;
3151         int y = plane_state->base.src.y1 >> 17;
3152         int w = drm_rect_width(&plane_state->base.src) >> 17;
3153         int h = drm_rect_height(&plane_state->base.src) >> 17;
3154         u32 offset;
3155
3156         intel_add_fb_offsets(&x, &y, plane_state, 1);
3157         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3158
3159         /* FIXME not quite sure how/if these apply to the chroma plane */
3160         if (w > max_width || h > max_height) {
3161                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3162                               w, h, max_width, max_height);
3163                 return -EINVAL;
3164         }
3165
3166         plane_state->aux.offset = offset;
3167         plane_state->aux.x = x;
3168         plane_state->aux.y = y;
3169
3170         return 0;
3171 }
3172
3173 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3174 {
3175         const struct drm_framebuffer *fb = plane_state->base.fb;
3176         int src_x = plane_state->base.src.x1 >> 16;
3177         int src_y = plane_state->base.src.y1 >> 16;
3178         int hsub = fb->format->hsub;
3179         int vsub = fb->format->vsub;
3180         int x = src_x / hsub;
3181         int y = src_y / vsub;
3182         u32 offset;
3183
3184         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3185                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3186                               plane_state->base.rotation);
3187                 return -EINVAL;
3188         }
3189
3190         intel_add_fb_offsets(&x, &y, plane_state, 1);
3191         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3192
3193         plane_state->aux.offset = offset;
3194         plane_state->aux.x = x * hsub + src_x % hsub;
3195         plane_state->aux.y = y * vsub + src_y % vsub;
3196
3197         return 0;
3198 }
3199
3200 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
3201                             struct intel_plane_state *plane_state)
3202 {
3203         const struct drm_framebuffer *fb = plane_state->base.fb;
3204         unsigned int rotation = plane_state->base.rotation;
3205         int ret;
3206
3207         if (rotation & DRM_MODE_REFLECT_X &&
3208             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
3209                 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
3210                 return -EINVAL;
3211         }
3212
3213         if (!plane_state->base.visible)
3214                 return 0;
3215
3216         /* Rotate src coordinates to match rotated GTT view */
3217         if (drm_rotation_90_or_270(rotation))
3218                 drm_rect_rotate(&plane_state->base.src,
3219                                 fb->width << 16, fb->height << 16,
3220                                 DRM_MODE_ROTATE_270);
3221
3222         /*
3223          * Handle the AUX surface first since
3224          * the main surface setup depends on it.
3225          */
3226         if (fb->format->format == DRM_FORMAT_NV12) {
3227                 ret = skl_check_nv12_surface(crtc_state, plane_state);
3228                 if (ret)
3229                         return ret;
3230                 ret = skl_check_nv12_aux_surface(plane_state);
3231                 if (ret)
3232                         return ret;
3233         } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3234                    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3235                 ret = skl_check_ccs_aux_surface(plane_state);
3236                 if (ret)
3237                         return ret;
3238         } else {
3239                 plane_state->aux.offset = ~0xfff;
3240                 plane_state->aux.x = 0;
3241                 plane_state->aux.y = 0;
3242         }
3243
3244         ret = skl_check_main_surface(crtc_state, plane_state);
3245         if (ret)
3246                 return ret;
3247
3248         return 0;
3249 }
3250
3251 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3252                           const struct intel_plane_state *plane_state)
3253 {
3254         struct drm_i915_private *dev_priv =
3255                 to_i915(plane_state->base.plane->dev);
3256         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3257         const struct drm_framebuffer *fb = plane_state->base.fb;
3258         unsigned int rotation = plane_state->base.rotation;
3259         u32 dspcntr;
3260
3261         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3262
3263         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3264             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3265                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3266
3267         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3268                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3269
3270         if (INTEL_GEN(dev_priv) < 5)
3271                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3272
3273         switch (fb->format->format) {
3274         case DRM_FORMAT_C8:
3275                 dspcntr |= DISPPLANE_8BPP;
3276                 break;
3277         case DRM_FORMAT_XRGB1555:
3278                 dspcntr |= DISPPLANE_BGRX555;
3279                 break;
3280         case DRM_FORMAT_RGB565:
3281                 dspcntr |= DISPPLANE_BGRX565;
3282                 break;
3283         case DRM_FORMAT_XRGB8888:
3284                 dspcntr |= DISPPLANE_BGRX888;
3285                 break;
3286         case DRM_FORMAT_XBGR8888:
3287                 dspcntr |= DISPPLANE_RGBX888;
3288                 break;
3289         case DRM_FORMAT_XRGB2101010:
3290                 dspcntr |= DISPPLANE_BGRX101010;
3291                 break;
3292         case DRM_FORMAT_XBGR2101010:
3293                 dspcntr |= DISPPLANE_RGBX101010;
3294                 break;
3295         default:
3296                 MISSING_CASE(fb->format->format);
3297                 return 0;
3298         }
3299
3300         if (INTEL_GEN(dev_priv) >= 4 &&
3301             fb->modifier == I915_FORMAT_MOD_X_TILED)
3302                 dspcntr |= DISPPLANE_TILED;
3303
3304         if (rotation & DRM_MODE_ROTATE_180)
3305                 dspcntr |= DISPPLANE_ROTATE_180;
3306
3307         if (rotation & DRM_MODE_REFLECT_X)
3308                 dspcntr |= DISPPLANE_MIRROR;
3309
3310         return dspcntr;
3311 }
3312
3313 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3314 {
3315         struct drm_i915_private *dev_priv =
3316                 to_i915(plane_state->base.plane->dev);
3317         int src_x = plane_state->base.src.x1 >> 16;
3318         int src_y = plane_state->base.src.y1 >> 16;
3319         u32 offset;
3320
3321         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3322
3323         if (INTEL_GEN(dev_priv) >= 4)
3324                 offset = intel_compute_tile_offset(&src_x, &src_y,
3325                                                    plane_state, 0);
3326         else
3327                 offset = 0;
3328
3329         /* HSW/BDW do this automagically in hardware */
3330         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3331                 unsigned int rotation = plane_state->base.rotation;
3332                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3333                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3334
3335                 if (rotation & DRM_MODE_ROTATE_180) {
3336                         src_x += src_w - 1;
3337                         src_y += src_h - 1;
3338                 } else if (rotation & DRM_MODE_REFLECT_X) {
3339                         src_x += src_w - 1;
3340                 }
3341         }
3342
3343         plane_state->main.offset = offset;
3344         plane_state->main.x = src_x;
3345         plane_state->main.y = src_y;
3346
3347         return 0;
3348 }
3349
3350 static void i9xx_update_plane(struct intel_plane *plane,
3351                               const struct intel_crtc_state *crtc_state,
3352                               const struct intel_plane_state *plane_state)
3353 {
3354         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3355         const struct drm_framebuffer *fb = plane_state->base.fb;
3356         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3357         u32 linear_offset;
3358         u32 dspcntr = plane_state->ctl;
3359         i915_reg_t reg = DSPCNTR(i9xx_plane);
3360         int x = plane_state->main.x;
3361         int y = plane_state->main.y;
3362         unsigned long irqflags;
3363         u32 dspaddr_offset;
3364
3365         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3366
3367         if (INTEL_GEN(dev_priv) >= 4)
3368                 dspaddr_offset = plane_state->main.offset;
3369         else
3370                 dspaddr_offset = linear_offset;
3371
3372         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3373
3374         if (INTEL_GEN(dev_priv) < 4) {
3375                 /* pipesrc and dspsize control the size that is scaled from,
3376                  * which should always be the user's requested size.
3377                  */
3378                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3379                               ((crtc_state->pipe_src_h - 1) << 16) |
3380                               (crtc_state->pipe_src_w - 1));
3381                 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3382         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3383                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3384                               ((crtc_state->pipe_src_h - 1) << 16) |
3385                               (crtc_state->pipe_src_w - 1));
3386                 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3387                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3388         }
3389
3390         I915_WRITE_FW(reg, dspcntr);
3391
3392         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
3393         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3394                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3395                               intel_plane_ggtt_offset(plane_state) +
3396                               dspaddr_offset);
3397                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3398         } else if (INTEL_GEN(dev_priv) >= 4) {
3399                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3400                               intel_plane_ggtt_offset(plane_state) +
3401                               dspaddr_offset);
3402                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3403                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3404         } else {
3405                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3406                               intel_plane_ggtt_offset(plane_state) +
3407                               dspaddr_offset);
3408         }
3409         POSTING_READ_FW(reg);
3410
3411         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3412 }
3413
3414 static void i9xx_disable_plane(struct intel_plane *plane,
3415                                struct intel_crtc *crtc)
3416 {
3417         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3418         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3419         unsigned long irqflags;
3420
3421         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3422
3423         I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
3424         if (INTEL_GEN(dev_priv) >= 4)
3425                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3426         else
3427                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3428         POSTING_READ_FW(DSPCNTR(i9xx_plane));
3429
3430         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3431 }
3432
3433 static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
3434 {
3435         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3436         enum intel_display_power_domain power_domain;
3437         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3438         enum pipe pipe = plane->pipe;
3439         bool ret;
3440
3441         /*
3442          * Not 100% correct for planes that can move between pipes,
3443          * but that's only the case for gen2-4 which don't have any
3444          * display power wells.
3445          */
3446         power_domain = POWER_DOMAIN_PIPE(pipe);
3447         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3448                 return false;
3449
3450         ret = I915_READ(DSPCNTR(i9xx_plane)) & DISPLAY_PLANE_ENABLE;
3451
3452         intel_display_power_put(dev_priv, power_domain);
3453
3454         return ret;
3455 }
3456
3457 static u32
3458 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3459 {
3460         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3461                 return 64;
3462         else
3463                 return intel_tile_width_bytes(fb, plane);
3464 }
3465
3466 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3467 {
3468         struct drm_device *dev = intel_crtc->base.dev;
3469         struct drm_i915_private *dev_priv = to_i915(dev);
3470
3471         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3472         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3473         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3474 }
3475
3476 /*
3477  * This function detaches (aka. unbinds) unused scalers in hardware
3478  */
3479 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3480 {
3481         struct intel_crtc_scaler_state *scaler_state;
3482         int i;
3483
3484         scaler_state = &intel_crtc->config->scaler_state;
3485
3486         /* loop through and disable scalers that aren't in use */
3487         for (i = 0; i < intel_crtc->num_scalers; i++) {
3488                 if (!scaler_state->scalers[i].in_use)
3489                         skl_detach_scaler(intel_crtc, i);
3490         }
3491 }
3492
3493 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3494                      unsigned int rotation)
3495 {
3496         u32 stride;
3497
3498         if (plane >= fb->format->num_planes)
3499                 return 0;
3500
3501         stride = intel_fb_pitch(fb, plane, rotation);
3502
3503         /*
3504          * The stride is either expressed as a multiple of 64 bytes chunks for
3505          * linear buffers or in number of tiles for tiled buffers.
3506          */
3507         if (drm_rotation_90_or_270(rotation))
3508                 stride /= intel_tile_height(fb, plane);
3509         else
3510                 stride /= intel_fb_stride_alignment(fb, plane);
3511
3512         return stride;
3513 }
3514
3515 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3516 {
3517         switch (pixel_format) {
3518         case DRM_FORMAT_C8:
3519                 return PLANE_CTL_FORMAT_INDEXED;
3520         case DRM_FORMAT_RGB565:
3521                 return PLANE_CTL_FORMAT_RGB_565;
3522         case DRM_FORMAT_XBGR8888:
3523         case DRM_FORMAT_ABGR8888:
3524                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3525         case DRM_FORMAT_XRGB8888:
3526         case DRM_FORMAT_ARGB8888:
3527                 return PLANE_CTL_FORMAT_XRGB_8888;
3528         case DRM_FORMAT_XRGB2101010:
3529                 return PLANE_CTL_FORMAT_XRGB_2101010;
3530         case DRM_FORMAT_XBGR2101010:
3531                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3532         case DRM_FORMAT_YUYV:
3533                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3534         case DRM_FORMAT_YVYU:
3535                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3536         case DRM_FORMAT_UYVY:
3537                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3538         case DRM_FORMAT_VYUY:
3539                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3540         case DRM_FORMAT_NV12:
3541                 return PLANE_CTL_FORMAT_NV12;
3542         default:
3543                 MISSING_CASE(pixel_format);
3544         }
3545
3546         return 0;
3547 }
3548
3549 /*
3550  * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3551  * to be already pre-multiplied. We need to add a knob (or a different
3552  * DRM_FORMAT) for user-space to configure that.
3553  */
3554 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3555 {
3556         switch (pixel_format) {
3557         case DRM_FORMAT_ABGR8888:
3558         case DRM_FORMAT_ARGB8888:
3559                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3560         default:
3561                 return PLANE_CTL_ALPHA_DISABLE;
3562         }
3563 }
3564
3565 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3566 {
3567         switch (pixel_format) {
3568         case DRM_FORMAT_ABGR8888:
3569         case DRM_FORMAT_ARGB8888:
3570                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3571         default:
3572                 return PLANE_COLOR_ALPHA_DISABLE;
3573         }
3574 }
3575
3576 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3577 {
3578         switch (fb_modifier) {
3579         case DRM_FORMAT_MOD_LINEAR:
3580                 break;
3581         case I915_FORMAT_MOD_X_TILED:
3582                 return PLANE_CTL_TILED_X;
3583         case I915_FORMAT_MOD_Y_TILED:
3584                 return PLANE_CTL_TILED_Y;
3585         case I915_FORMAT_MOD_Y_TILED_CCS:
3586                 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3587         case I915_FORMAT_MOD_Yf_TILED:
3588                 return PLANE_CTL_TILED_YF;
3589         case I915_FORMAT_MOD_Yf_TILED_CCS:
3590                 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3591         default:
3592                 MISSING_CASE(fb_modifier);
3593         }
3594
3595         return 0;
3596 }
3597
3598 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3599 {
3600         switch (rotate) {
3601         case DRM_MODE_ROTATE_0:
3602                 break;
3603         /*
3604          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3605          * while i915 HW rotation is clockwise, thats why this swapping.
3606          */
3607         case DRM_MODE_ROTATE_90:
3608                 return PLANE_CTL_ROTATE_270;
3609         case DRM_MODE_ROTATE_180:
3610                 return PLANE_CTL_ROTATE_180;
3611         case DRM_MODE_ROTATE_270:
3612                 return PLANE_CTL_ROTATE_90;
3613         default:
3614                 MISSING_CASE(rotate);
3615         }
3616
3617         return 0;
3618 }
3619
3620 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3621 {
3622         switch (reflect) {
3623         case 0:
3624                 break;
3625         case DRM_MODE_REFLECT_X:
3626                 return PLANE_CTL_FLIP_HORIZONTAL;
3627         case DRM_MODE_REFLECT_Y:
3628         default:
3629                 MISSING_CASE(reflect);
3630         }
3631
3632         return 0;
3633 }
3634
3635 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3636                   const struct intel_plane_state *plane_state)
3637 {
3638         struct drm_i915_private *dev_priv =
3639                 to_i915(plane_state->base.plane->dev);
3640         const struct drm_framebuffer *fb = plane_state->base.fb;
3641         unsigned int rotation = plane_state->base.rotation;
3642         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3643         u32 plane_ctl;
3644
3645         plane_ctl = PLANE_CTL_ENABLE;
3646
3647         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3648                 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3649                 plane_ctl |=
3650                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3651                         PLANE_CTL_PIPE_CSC_ENABLE |
3652                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3653
3654                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3655                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3656
3657                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3658                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3659         }
3660
3661         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3662         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3663         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3664
3665         if (INTEL_GEN(dev_priv) >= 10)
3666                 plane_ctl |= cnl_plane_ctl_flip(rotation &
3667                                                 DRM_MODE_REFLECT_MASK);
3668
3669         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3670                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3671         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3672                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3673
3674         return plane_ctl;
3675 }
3676
3677 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3678                         const struct intel_plane_state *plane_state)
3679 {
3680         struct drm_i915_private *dev_priv =
3681                 to_i915(plane_state->base.plane->dev);
3682         const struct drm_framebuffer *fb = plane_state->base.fb;
3683         u32 plane_color_ctl = 0;
3684
3685         if (INTEL_GEN(dev_priv) < 11) {
3686                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3687                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3688         }
3689         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3690         plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3691
3692         if (intel_format_is_yuv(fb->format->format)) {
3693                 if (fb->format->format == DRM_FORMAT_NV12) {
3694                         plane_color_ctl |=
3695                                 PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3696                         goto out;
3697                 }
3698                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3699                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3700                 else
3701                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3702
3703                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3704                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3705         }
3706 out:
3707         return plane_color_ctl;
3708 }
3709
3710 static int
3711 __intel_display_resume(struct drm_device *dev,
3712                        struct drm_atomic_state *state,
3713                        struct drm_modeset_acquire_ctx *ctx)
3714 {
3715         struct drm_crtc_state *crtc_state;
3716         struct drm_crtc *crtc;
3717         int i, ret;
3718
3719         intel_modeset_setup_hw_state(dev, ctx);
3720         i915_redisable_vga(to_i915(dev));
3721
3722         if (!state)
3723                 return 0;
3724
3725         /*
3726          * We've duplicated the state, pointers to the old state are invalid.
3727          *
3728          * Don't attempt to use the old state until we commit the duplicated state.
3729          */
3730         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3731                 /*
3732                  * Force recalculation even if we restore
3733                  * current state. With fast modeset this may not result
3734                  * in a modeset when the state is compatible.
3735                  */
3736                 crtc_state->mode_changed = true;
3737         }
3738
3739         /* ignore any reset values/BIOS leftovers in the WM registers */
3740         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3741                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3742
3743         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3744
3745         WARN_ON(ret == -EDEADLK);
3746         return ret;
3747 }
3748
3749 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3750 {
3751         return intel_has_gpu_reset(dev_priv) &&
3752                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3753 }
3754
3755 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3756 {
3757         struct drm_device *dev = &dev_priv->drm;
3758         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3759         struct drm_atomic_state *state;
3760         int ret;
3761
3762         /* reset doesn't touch the display */
3763         if (!i915_modparams.force_reset_modeset_test &&
3764             !gpu_reset_clobbers_display(dev_priv))
3765                 return;
3766
3767         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3768         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3769         wake_up_all(&dev_priv->gpu_error.wait_queue);
3770
3771         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3772                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3773                 i915_gem_set_wedged(dev_priv);
3774         }
3775
3776         /*
3777          * Need mode_config.mutex so that we don't
3778          * trample ongoing ->detect() and whatnot.
3779          */
3780         mutex_lock(&dev->mode_config.mutex);
3781         drm_modeset_acquire_init(ctx, 0);
3782         while (1) {
3783                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3784                 if (ret != -EDEADLK)
3785                         break;
3786
3787                 drm_modeset_backoff(ctx);
3788         }
3789         /*
3790          * Disabling the crtcs gracefully seems nicer. Also the
3791          * g33 docs say we should at least disable all the planes.
3792          */
3793         state = drm_atomic_helper_duplicate_state(dev, ctx);
3794         if (IS_ERR(state)) {
3795                 ret = PTR_ERR(state);
3796                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3797                 return;
3798         }
3799
3800         ret = drm_atomic_helper_disable_all(dev, ctx);
3801         if (ret) {
3802                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3803                 drm_atomic_state_put(state);
3804                 return;
3805         }
3806
3807         dev_priv->modeset_restore_state = state;
3808         state->acquire_ctx = ctx;
3809 }
3810
3811 void intel_finish_reset(struct drm_i915_private *dev_priv)
3812 {
3813         struct drm_device *dev = &dev_priv->drm;
3814         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3815         struct drm_atomic_state *state;
3816         int ret;
3817
3818         /* reset doesn't touch the display */
3819         if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3820                 return;
3821
3822         state = fetch_and_zero(&dev_priv->modeset_restore_state);
3823         if (!state)
3824                 goto unlock;
3825
3826         /* reset doesn't touch the display */
3827         if (!gpu_reset_clobbers_display(dev_priv)) {
3828                 /* for testing only restore the display */
3829                 ret = __intel_display_resume(dev, state, ctx);
3830                 if (ret)
3831                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3832         } else {
3833                 /*
3834                  * The display has been reset as well,
3835                  * so need a full re-initialization.
3836                  */
3837                 intel_runtime_pm_disable_interrupts(dev_priv);
3838                 intel_runtime_pm_enable_interrupts(dev_priv);
3839
3840                 intel_pps_unlock_regs_wa(dev_priv);
3841                 intel_modeset_init_hw(dev);
3842                 intel_init_clock_gating(dev_priv);
3843
3844                 spin_lock_irq(&dev_priv->irq_lock);
3845                 if (dev_priv->display.hpd_irq_setup)
3846                         dev_priv->display.hpd_irq_setup(dev_priv);
3847                 spin_unlock_irq(&dev_priv->irq_lock);
3848
3849                 ret = __intel_display_resume(dev, state, ctx);
3850                 if (ret)
3851                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3852
3853                 intel_hpd_init(dev_priv);
3854         }
3855
3856         drm_atomic_state_put(state);
3857 unlock:
3858         drm_modeset_drop_locks(ctx);
3859         drm_modeset_acquire_fini(ctx);
3860         mutex_unlock(&dev->mode_config.mutex);
3861
3862         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3863 }
3864
3865 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3866                                      const struct intel_crtc_state *new_crtc_state)
3867 {
3868         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3869         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3870
3871         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3872         crtc->base.mode = new_crtc_state->base.mode;
3873
3874         /*
3875          * Update pipe size and adjust fitter if needed: the reason for this is
3876          * that in compute_mode_changes we check the native mode (not the pfit
3877          * mode) to see if we can flip rather than do a full mode set. In the
3878          * fastboot case, we'll flip, but if we don't update the pipesrc and
3879          * pfit state, we'll end up with a big fb scanned out into the wrong
3880          * sized surface.
3881          */
3882
3883         I915_WRITE(PIPESRC(crtc->pipe),
3884                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3885                    (new_crtc_state->pipe_src_h - 1));
3886
3887         /* on skylake this is done by detaching scalers */
3888         if (INTEL_GEN(dev_priv) >= 9) {
3889                 skl_detach_scalers(crtc);
3890
3891                 if (new_crtc_state->pch_pfit.enabled)
3892                         skylake_pfit_enable(crtc);
3893         } else if (HAS_PCH_SPLIT(dev_priv)) {
3894                 if (new_crtc_state->pch_pfit.enabled)
3895                         ironlake_pfit_enable(crtc);
3896                 else if (old_crtc_state->pch_pfit.enabled)
3897                         ironlake_pfit_disable(crtc, true);
3898         }
3899 }
3900
3901 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3902 {
3903         struct drm_device *dev = crtc->base.dev;
3904         struct drm_i915_private *dev_priv = to_i915(dev);
3905         int pipe = crtc->pipe;
3906         i915_reg_t reg;
3907         u32 temp;
3908
3909         /* enable normal train */
3910         reg = FDI_TX_CTL(pipe);
3911         temp = I915_READ(reg);
3912         if (IS_IVYBRIDGE(dev_priv)) {
3913                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3914                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3915         } else {
3916                 temp &= ~FDI_LINK_TRAIN_NONE;
3917                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3918         }
3919         I915_WRITE(reg, temp);
3920
3921         reg = FDI_RX_CTL(pipe);
3922         temp = I915_READ(reg);
3923         if (HAS_PCH_CPT(dev_priv)) {
3924                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3925                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3926         } else {
3927                 temp &= ~FDI_LINK_TRAIN_NONE;
3928                 temp |= FDI_LINK_TRAIN_NONE;
3929         }
3930         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3931
3932         /* wait one idle pattern time */
3933         POSTING_READ(reg);
3934         udelay(1000);
3935
3936         /* IVB wants error correction enabled */
3937         if (IS_IVYBRIDGE(dev_priv))
3938                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3939                            FDI_FE_ERRC_ENABLE);
3940 }
3941
3942 /* The FDI link training functions for ILK/Ibexpeak. */
3943 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3944                                     const struct intel_crtc_state *crtc_state)
3945 {
3946         struct drm_device *dev = crtc->base.dev;
3947         struct drm_i915_private *dev_priv = to_i915(dev);
3948         int pipe = crtc->pipe;
3949         i915_reg_t reg;
3950         u32 temp, tries;
3951
3952         /* FDI needs bits from pipe first */
3953         assert_pipe_enabled(dev_priv, pipe);
3954
3955         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3956            for train result */
3957         reg = FDI_RX_IMR(pipe);
3958         temp = I915_READ(reg);
3959         temp &= ~FDI_RX_SYMBOL_LOCK;
3960         temp &= ~FDI_RX_BIT_LOCK;
3961         I915_WRITE(reg, temp);
3962         I915_READ(reg);
3963         udelay(150);
3964
3965         /* enable CPU FDI TX and PCH FDI RX */
3966         reg = FDI_TX_CTL(pipe);
3967         temp = I915_READ(reg);
3968         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3969         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3970         temp &= ~FDI_LINK_TRAIN_NONE;
3971         temp |= FDI_LINK_TRAIN_PATTERN_1;
3972         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3973
3974         reg = FDI_RX_CTL(pipe);
3975         temp = I915_READ(reg);
3976         temp &= ~FDI_LINK_TRAIN_NONE;
3977         temp |= FDI_LINK_TRAIN_PATTERN_1;
3978         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3979
3980         POSTING_READ(reg);
3981         udelay(150);
3982
3983         /* Ironlake workaround, enable clock pointer after FDI enable*/
3984         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3985         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3986                    FDI_RX_PHASE_SYNC_POINTER_EN);
3987
3988         reg = FDI_RX_IIR(pipe);
3989         for (tries = 0; tries < 5; tries++) {
3990                 temp = I915_READ(reg);
3991                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3992
3993                 if ((temp & FDI_RX_BIT_LOCK)) {
3994                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3995                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3996                         break;
3997                 }
3998         }
3999         if (tries == 5)
4000                 DRM_ERROR("FDI train 1 fail!\n");
4001
4002         /* Train 2 */
4003         reg = FDI_TX_CTL(pipe);
4004         temp = I915_READ(reg);
4005         temp &= ~FDI_LINK_TRAIN_NONE;
4006         temp |= FDI_LINK_TRAIN_PATTERN_2;
4007         I915_WRITE(reg, temp);
4008
4009         reg = FDI_RX_CTL(pipe);
4010         temp = I915_READ(reg);
4011         temp &= ~FDI_LINK_TRAIN_NONE;
4012         temp |= FDI_LINK_TRAIN_PATTERN_2;
4013         I915_WRITE(reg, temp);
4014
4015         POSTING_READ(reg);
4016         udelay(150);
4017
4018         reg = FDI_RX_IIR(pipe);
4019         for (tries = 0; tries < 5; tries++) {
4020                 temp = I915_READ(reg);
4021                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4022
4023                 if (temp & FDI_RX_SYMBOL_LOCK) {
4024                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4025                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4026                         break;
4027                 }
4028         }
4029         if (tries == 5)
4030                 DRM_ERROR("FDI train 2 fail!\n");
4031
4032         DRM_DEBUG_KMS("FDI train done\n");
4033
4034 }
4035
4036 static const int snb_b_fdi_train_param[] = {
4037         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4038         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4039         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4040         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4041 };
4042
4043 /* The FDI link training functions for SNB/Cougarpoint. */
4044 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4045                                 const struct intel_crtc_state *crtc_state)
4046 {
4047         struct drm_device *dev = crtc->base.dev;
4048         struct drm_i915_private *dev_priv = to_i915(dev);
4049         int pipe = crtc->pipe;
4050         i915_reg_t reg;
4051         u32 temp, i, retry;
4052
4053         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4054            for train result */
4055         reg = FDI_RX_IMR(pipe);
4056         temp = I915_READ(reg);
4057         temp &= ~FDI_RX_SYMBOL_LOCK;
4058         temp &= ~FDI_RX_BIT_LOCK;
4059         I915_WRITE(reg, temp);
4060
4061         POSTING_READ(reg);
4062         udelay(150);
4063
4064         /* enable CPU FDI TX and PCH FDI RX */
4065         reg = FDI_TX_CTL(pipe);
4066         temp = I915_READ(reg);
4067         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4068         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4069         temp &= ~FDI_LINK_TRAIN_NONE;
4070         temp |= FDI_LINK_TRAIN_PATTERN_1;
4071         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4072         /* SNB-B */
4073         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4074         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4075
4076         I915_WRITE(FDI_RX_MISC(pipe),
4077                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4078
4079         reg = FDI_RX_CTL(pipe);
4080         temp = I915_READ(reg);
4081         if (HAS_PCH_CPT(dev_priv)) {
4082                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4083                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4084         } else {
4085                 temp &= ~FDI_LINK_TRAIN_NONE;
4086                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4087         }
4088         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4089
4090         POSTING_READ(reg);
4091         udelay(150);
4092
4093         for (i = 0; i < 4; i++) {
4094                 reg = FDI_TX_CTL(pipe);
4095                 temp = I915_READ(reg);
4096                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4097                 temp |= snb_b_fdi_train_param[i];
4098                 I915_WRITE(reg, temp);
4099
4100                 POSTING_READ(reg);
4101                 udelay(500);
4102
4103                 for (retry = 0; retry < 5; retry++) {
4104                         reg = FDI_RX_IIR(pipe);
4105                         temp = I915_READ(reg);
4106                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4107                         if (temp & FDI_RX_BIT_LOCK) {
4108                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4109                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4110                                 break;
4111                         }
4112                         udelay(50);
4113                 }
4114                 if (retry < 5)
4115                         break;
4116         }
4117         if (i == 4)
4118                 DRM_ERROR("FDI train 1 fail!\n");
4119
4120         /* Train 2 */
4121         reg = FDI_TX_CTL(pipe);
4122         temp = I915_READ(reg);
4123         temp &= ~FDI_LINK_TRAIN_NONE;
4124         temp |= FDI_LINK_TRAIN_PATTERN_2;
4125         if (IS_GEN6(dev_priv)) {
4126                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4127                 /* SNB-B */
4128                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4129         }
4130         I915_WRITE(reg, temp);
4131
4132         reg = FDI_RX_CTL(pipe);
4133         temp = I915_READ(reg);
4134         if (HAS_PCH_CPT(dev_priv)) {
4135                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4136                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4137         } else {
4138                 temp &= ~FDI_LINK_TRAIN_NONE;
4139                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4140         }
4141         I915_WRITE(reg, temp);
4142
4143         POSTING_READ(reg);
4144         udelay(150);
4145
4146         for (i = 0; i < 4; i++) {
4147                 reg = FDI_TX_CTL(pipe);
4148                 temp = I915_READ(reg);
4149                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4150                 temp |= snb_b_fdi_train_param[i];
4151                 I915_WRITE(reg, temp);
4152
4153                 POSTING_READ(reg);
4154                 udelay(500);
4155
4156                 for (retry = 0; retry < 5; retry++) {
4157                         reg = FDI_RX_IIR(pipe);
4158                         temp = I915_READ(reg);
4159                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4160                         if (temp & FDI_RX_SYMBOL_LOCK) {
4161                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4162                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4163                                 break;
4164                         }
4165                         udelay(50);
4166                 }
4167                 if (retry < 5)
4168                         break;
4169         }
4170         if (i == 4)
4171                 DRM_ERROR("FDI train 2 fail!\n");
4172
4173         DRM_DEBUG_KMS("FDI train done.\n");
4174 }
4175
4176 /* Manual link training for Ivy Bridge A0 parts */
4177 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4178                                       const struct intel_crtc_state *crtc_state)
4179 {
4180         struct drm_device *dev = crtc->base.dev;
4181         struct drm_i915_private *dev_priv = to_i915(dev);
4182         int pipe = crtc->pipe;
4183         i915_reg_t reg;
4184         u32 temp, i, j;
4185
4186         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4187            for train result */
4188         reg = FDI_RX_IMR(pipe);
4189         temp = I915_READ(reg);
4190         temp &= ~FDI_RX_SYMBOL_LOCK;
4191         temp &= ~FDI_RX_BIT_LOCK;
4192         I915_WRITE(reg, temp);
4193
4194         POSTING_READ(reg);
4195         udelay(150);
4196
4197         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4198                       I915_READ(FDI_RX_IIR(pipe)));
4199
4200         /* Try each vswing and preemphasis setting twice before moving on */
4201         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4202                 /* disable first in case we need to retry */
4203                 reg = FDI_TX_CTL(pipe);
4204                 temp = I915_READ(reg);
4205                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4206                 temp &= ~FDI_TX_ENABLE;
4207                 I915_WRITE(reg, temp);
4208
4209                 reg = FDI_RX_CTL(pipe);
4210                 temp = I915_READ(reg);
4211                 temp &= ~FDI_LINK_TRAIN_AUTO;
4212                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4213                 temp &= ~FDI_RX_ENABLE;
4214                 I915_WRITE(reg, temp);
4215
4216                 /* enable CPU FDI TX and PCH FDI RX */
4217                 reg = FDI_TX_CTL(pipe);
4218                 temp = I915_READ(reg);
4219                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4220                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4221                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4222                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4223                 temp |= snb_b_fdi_train_param[j/2];
4224                 temp |= FDI_COMPOSITE_SYNC;
4225                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4226
4227                 I915_WRITE(FDI_RX_MISC(pipe),
4228                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4229
4230                 reg = FDI_RX_CTL(pipe);
4231                 temp = I915_READ(reg);
4232                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4233                 temp |= FDI_COMPOSITE_SYNC;
4234                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4235
4236                 POSTING_READ(reg);
4237                 udelay(1); /* should be 0.5us */
4238
4239                 for (i = 0; i < 4; i++) {
4240                         reg = FDI_RX_IIR(pipe);
4241                         temp = I915_READ(reg);
4242                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4243
4244                         if (temp & FDI_RX_BIT_LOCK ||
4245                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4246                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4247                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4248                                               i);
4249                                 break;
4250                         }
4251                         udelay(1); /* should be 0.5us */
4252                 }
4253                 if (i == 4) {
4254                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4255                         continue;
4256                 }
4257
4258                 /* Train 2 */
4259                 reg = FDI_TX_CTL(pipe);
4260                 temp = I915_READ(reg);
4261                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4262                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4263                 I915_WRITE(reg, temp);
4264
4265                 reg = FDI_RX_CTL(pipe);
4266                 temp = I915_READ(reg);
4267                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4268                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4269                 I915_WRITE(reg, temp);
4270
4271                 POSTING_READ(reg);
4272                 udelay(2); /* should be 1.5us */
4273
4274                 for (i = 0; i < 4; i++) {
4275                         reg = FDI_RX_IIR(pipe);
4276                         temp = I915_READ(reg);
4277                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4278
4279                         if (temp & FDI_RX_SYMBOL_LOCK ||
4280                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4281                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4282                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4283                                               i);
4284                                 goto train_done;
4285                         }
4286                         udelay(2); /* should be 1.5us */
4287                 }
4288                 if (i == 4)
4289                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4290         }
4291
4292 train_done:
4293         DRM_DEBUG_KMS("FDI train done.\n");
4294 }
4295
4296 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4297 {
4298         struct drm_device *dev = intel_crtc->base.dev;
4299         struct drm_i915_private *dev_priv = to_i915(dev);
4300         int pipe = intel_crtc->pipe;
4301         i915_reg_t reg;
4302         u32 temp;
4303
4304         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4305         reg = FDI_RX_CTL(pipe);
4306         temp = I915_READ(reg);
4307         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4308         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4309         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4310         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4311
4312         POSTING_READ(reg);
4313         udelay(200);
4314
4315         /* Switch from Rawclk to PCDclk */
4316         temp = I915_READ(reg);
4317         I915_WRITE(reg, temp | FDI_PCDCLK);
4318
4319         POSTING_READ(reg);
4320         udelay(200);
4321
4322         /* Enable CPU FDI TX PLL, always on for Ironlake */
4323         reg = FDI_TX_CTL(pipe);
4324         temp = I915_READ(reg);
4325         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4326                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4327
4328                 POSTING_READ(reg);
4329                 udelay(100);
4330         }
4331 }
4332
4333 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4334 {
4335         struct drm_device *dev = intel_crtc->base.dev;
4336         struct drm_i915_private *dev_priv = to_i915(dev);
4337         int pipe = intel_crtc->pipe;
4338         i915_reg_t reg;
4339         u32 temp;
4340
4341         /* Switch from PCDclk to Rawclk */
4342         reg = FDI_RX_CTL(pipe);
4343         temp = I915_READ(reg);
4344         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4345
4346         /* Disable CPU FDI TX PLL */
4347         reg = FDI_TX_CTL(pipe);
4348         temp = I915_READ(reg);
4349         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4350
4351         POSTING_READ(reg);
4352         udelay(100);
4353
4354         reg = FDI_RX_CTL(pipe);
4355         temp = I915_READ(reg);
4356         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4357
4358         /* Wait for the clocks to turn off. */
4359         POSTING_READ(reg);
4360         udelay(100);
4361 }
4362
4363 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4364 {
4365         struct drm_device *dev = crtc->dev;
4366         struct drm_i915_private *dev_priv = to_i915(dev);
4367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4368         int pipe = intel_crtc->pipe;
4369         i915_reg_t reg;
4370         u32 temp;
4371
4372         /* disable CPU FDI tx and PCH FDI rx */
4373         reg = FDI_TX_CTL(pipe);
4374         temp = I915_READ(reg);
4375         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4376         POSTING_READ(reg);
4377
4378         reg = FDI_RX_CTL(pipe);
4379         temp = I915_READ(reg);
4380         temp &= ~(0x7 << 16);
4381         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4382         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4383
4384         POSTING_READ(reg);
4385         udelay(100);
4386
4387         /* Ironlake workaround, disable clock pointer after downing FDI */
4388         if (HAS_PCH_IBX(dev_priv))
4389                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4390
4391         /* still set train pattern 1 */
4392         reg = FDI_TX_CTL(pipe);
4393         temp = I915_READ(reg);
4394         temp &= ~FDI_LINK_TRAIN_NONE;
4395         temp |= FDI_LINK_TRAIN_PATTERN_1;
4396         I915_WRITE(reg, temp);
4397
4398         reg = FDI_RX_CTL(pipe);
4399         temp = I915_READ(reg);
4400         if (HAS_PCH_CPT(dev_priv)) {
4401                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4402                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4403         } else {
4404                 temp &= ~FDI_LINK_TRAIN_NONE;
4405                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4406         }
4407         /* BPC in FDI rx is consistent with that in PIPECONF */
4408         temp &= ~(0x07 << 16);
4409         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4410         I915_WRITE(reg, temp);
4411
4412         POSTING_READ(reg);
4413         udelay(100);
4414 }
4415
4416 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4417 {
4418         struct drm_crtc *crtc;
4419         bool cleanup_done;
4420
4421         drm_for_each_crtc(crtc, &dev_priv->drm) {
4422                 struct drm_crtc_commit *commit;
4423                 spin_lock(&crtc->commit_lock);
4424                 commit = list_first_entry_or_null(&crtc->commit_list,
4425                                                   struct drm_crtc_commit, commit_entry);
4426                 cleanup_done = commit ?
4427                         try_wait_for_completion(&commit->cleanup_done) : true;
4428                 spin_unlock(&crtc->commit_lock);
4429
4430                 if (cleanup_done)
4431                         continue;
4432
4433                 drm_crtc_wait_one_vblank(crtc);
4434
4435                 return true;
4436         }
4437
4438         return false;
4439 }
4440
4441 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4442 {
4443         u32 temp;
4444
4445         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4446
4447         mutex_lock(&dev_priv->sb_lock);
4448
4449         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4450         temp |= SBI_SSCCTL_DISABLE;
4451         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4452
4453         mutex_unlock(&dev_priv->sb_lock);
4454 }
4455
4456 /* Program iCLKIP clock to the desired frequency */
4457 static void lpt_program_iclkip(struct intel_crtc *crtc)
4458 {
4459         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4460         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4461         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4462         u32 temp;
4463
4464         lpt_disable_iclkip(dev_priv);
4465
4466         /* The iCLK virtual clock root frequency is in MHz,
4467          * but the adjusted_mode->crtc_clock in in KHz. To get the
4468          * divisors, it is necessary to divide one by another, so we
4469          * convert the virtual clock precision to KHz here for higher
4470          * precision.
4471          */
4472         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4473                 u32 iclk_virtual_root_freq = 172800 * 1000;
4474                 u32 iclk_pi_range = 64;
4475                 u32 desired_divisor;
4476
4477                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4478                                                     clock << auxdiv);
4479                 divsel = (desired_divisor / iclk_pi_range) - 2;
4480                 phaseinc = desired_divisor % iclk_pi_range;
4481
4482                 /*
4483                  * Near 20MHz is a corner case which is
4484                  * out of range for the 7-bit divisor
4485                  */
4486                 if (divsel <= 0x7f)
4487                         break;
4488         }
4489
4490         /* This should not happen with any sane values */
4491         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4492                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4493         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4494                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4495
4496         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4497                         clock,
4498                         auxdiv,
4499                         divsel,
4500                         phasedir,
4501                         phaseinc);
4502
4503         mutex_lock(&dev_priv->sb_lock);
4504
4505         /* Program SSCDIVINTPHASE6 */
4506         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4507         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4508         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4509         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4510         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4511         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4512         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4513         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4514
4515         /* Program SSCAUXDIV */
4516         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4517         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4518         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4519         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4520
4521         /* Enable modulator and associated divider */
4522         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4523         temp &= ~SBI_SSCCTL_DISABLE;
4524         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4525
4526         mutex_unlock(&dev_priv->sb_lock);
4527
4528         /* Wait for initialization time */
4529         udelay(24);
4530
4531         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4532 }
4533
4534 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4535 {
4536         u32 divsel, phaseinc, auxdiv;
4537         u32 iclk_virtual_root_freq = 172800 * 1000;
4538         u32 iclk_pi_range = 64;
4539         u32 desired_divisor;
4540         u32 temp;
4541
4542         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4543                 return 0;
4544
4545         mutex_lock(&dev_priv->sb_lock);
4546
4547         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4548         if (temp & SBI_SSCCTL_DISABLE) {
4549                 mutex_unlock(&dev_priv->sb_lock);
4550                 return 0;
4551         }
4552
4553         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4554         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4555                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4556         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4557                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4558
4559         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4560         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4561                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4562
4563         mutex_unlock(&dev_priv->sb_lock);
4564
4565         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4566
4567         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4568                                  desired_divisor << auxdiv);
4569 }
4570
4571 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4572                                                 enum pipe pch_transcoder)
4573 {
4574         struct drm_device *dev = crtc->base.dev;
4575         struct drm_i915_private *dev_priv = to_i915(dev);
4576         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4577
4578         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4579                    I915_READ(HTOTAL(cpu_transcoder)));
4580         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4581                    I915_READ(HBLANK(cpu_transcoder)));
4582         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4583                    I915_READ(HSYNC(cpu_transcoder)));
4584
4585         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4586                    I915_READ(VTOTAL(cpu_transcoder)));
4587         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4588                    I915_READ(VBLANK(cpu_transcoder)));
4589         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4590                    I915_READ(VSYNC(cpu_transcoder)));
4591         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4592                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4593 }
4594
4595 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4596 {
4597         struct drm_i915_private *dev_priv = to_i915(dev);
4598         uint32_t temp;
4599
4600         temp = I915_READ(SOUTH_CHICKEN1);
4601         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4602                 return;
4603
4604         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4605         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4606
4607         temp &= ~FDI_BC_BIFURCATION_SELECT;
4608         if (enable)
4609                 temp |= FDI_BC_BIFURCATION_SELECT;
4610
4611         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4612         I915_WRITE(SOUTH_CHICKEN1, temp);
4613         POSTING_READ(SOUTH_CHICKEN1);
4614 }
4615
4616 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4617 {
4618         struct drm_device *dev = intel_crtc->base.dev;
4619
4620         switch (intel_crtc->pipe) {
4621         case PIPE_A:
4622                 break;
4623         case PIPE_B:
4624                 if (intel_crtc->config->fdi_lanes > 2)
4625                         cpt_set_fdi_bc_bifurcation(dev, false);
4626                 else
4627                         cpt_set_fdi_bc_bifurcation(dev, true);
4628
4629                 break;
4630         case PIPE_C:
4631                 cpt_set_fdi_bc_bifurcation(dev, true);
4632
4633                 break;
4634         default:
4635                 BUG();
4636         }
4637 }
4638
4639 /* Return which DP Port should be selected for Transcoder DP control */
4640 static enum port
4641 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4642 {
4643         struct drm_device *dev = crtc->base.dev;
4644         struct intel_encoder *encoder;
4645
4646         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4647                 if (encoder->type == INTEL_OUTPUT_DP ||
4648                     encoder->type == INTEL_OUTPUT_EDP)
4649                         return encoder->port;
4650         }
4651
4652         return -1;
4653 }
4654
4655 /*
4656  * Enable PCH resources required for PCH ports:
4657  *   - PCH PLLs
4658  *   - FDI training & RX/TX
4659  *   - update transcoder timings
4660  *   - DP transcoding bits
4661  *   - transcoder
4662  */
4663 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4664 {
4665         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4666         struct drm_device *dev = crtc->base.dev;
4667         struct drm_i915_private *dev_priv = to_i915(dev);
4668         int pipe = crtc->pipe;
4669         u32 temp;
4670
4671         assert_pch_transcoder_disabled(dev_priv, pipe);
4672
4673         if (IS_IVYBRIDGE(dev_priv))
4674                 ivybridge_update_fdi_bc_bifurcation(crtc);
4675
4676         /* Write the TU size bits before fdi link training, so that error
4677          * detection works. */
4678         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4679                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4680
4681         /* For PCH output, training FDI link */
4682         dev_priv->display.fdi_link_train(crtc, crtc_state);
4683
4684         /* We need to program the right clock selection before writing the pixel
4685          * mutliplier into the DPLL. */
4686         if (HAS_PCH_CPT(dev_priv)) {
4687                 u32 sel;
4688
4689                 temp = I915_READ(PCH_DPLL_SEL);
4690                 temp |= TRANS_DPLL_ENABLE(pipe);
4691                 sel = TRANS_DPLLB_SEL(pipe);
4692                 if (crtc_state->shared_dpll ==
4693                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4694                         temp |= sel;
4695                 else
4696                         temp &= ~sel;
4697                 I915_WRITE(PCH_DPLL_SEL, temp);
4698         }
4699
4700         /* XXX: pch pll's can be enabled any time before we enable the PCH
4701          * transcoder, and we actually should do this to not upset any PCH
4702          * transcoder that already use the clock when we share it.
4703          *
4704          * Note that enable_shared_dpll tries to do the right thing, but
4705          * get_shared_dpll unconditionally resets the pll - we need that to have
4706          * the right LVDS enable sequence. */
4707         intel_enable_shared_dpll(crtc);
4708
4709         /* set transcoder timing, panel must allow it */
4710         assert_panel_unlocked(dev_priv, pipe);
4711         ironlake_pch_transcoder_set_timings(crtc, pipe);
4712
4713         intel_fdi_normal_train(crtc);
4714
4715         /* For PCH DP, enable TRANS_DP_CTL */
4716         if (HAS_PCH_CPT(dev_priv) &&
4717             intel_crtc_has_dp_encoder(crtc_state)) {
4718                 const struct drm_display_mode *adjusted_mode =
4719                         &crtc_state->base.adjusted_mode;
4720                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4721                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4722                 temp = I915_READ(reg);
4723                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4724                           TRANS_DP_SYNC_MASK |
4725                           TRANS_DP_BPC_MASK);
4726                 temp |= TRANS_DP_OUTPUT_ENABLE;
4727                 temp |= bpc << 9; /* same format but at 11:9 */
4728
4729                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4730                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4731                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4732                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4733
4734                 switch (intel_trans_dp_port_sel(crtc)) {
4735                 case PORT_B:
4736                         temp |= TRANS_DP_PORT_SEL_B;
4737                         break;
4738                 case PORT_C:
4739                         temp |= TRANS_DP_PORT_SEL_C;
4740                         break;
4741                 case PORT_D:
4742                         temp |= TRANS_DP_PORT_SEL_D;
4743                         break;
4744                 default:
4745                         BUG();
4746                 }
4747
4748                 I915_WRITE(reg, temp);
4749         }
4750
4751         ironlake_enable_pch_transcoder(dev_priv, pipe);
4752 }
4753
4754 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4755 {
4756         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4757         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4758         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4759
4760         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4761
4762         lpt_program_iclkip(crtc);
4763
4764         /* Set transcoder timing. */
4765         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4766
4767         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4768 }
4769
4770 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4771 {
4772         struct drm_i915_private *dev_priv = to_i915(dev);
4773         i915_reg_t dslreg = PIPEDSL(pipe);
4774         u32 temp;
4775
4776         temp = I915_READ(dslreg);
4777         udelay(500);
4778         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4779                 if (wait_for(I915_READ(dslreg) != temp, 5))
4780                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4781         }
4782 }
4783
4784 static int
4785 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4786                   unsigned int scaler_user, int *scaler_id,
4787                   int src_w, int src_h, int dst_w, int dst_h,
4788                   bool plane_scaler_check,
4789                   uint32_t pixel_format)
4790 {
4791         struct intel_crtc_scaler_state *scaler_state =
4792                 &crtc_state->scaler_state;
4793         struct intel_crtc *intel_crtc =
4794                 to_intel_crtc(crtc_state->base.crtc);
4795         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4796         const struct drm_display_mode *adjusted_mode =
4797                 &crtc_state->base.adjusted_mode;
4798         int need_scaling;
4799
4800         /*
4801          * Src coordinates are already rotated by 270 degrees for
4802          * the 90/270 degree plane rotation cases (to match the
4803          * GTT mapping), hence no need to account for rotation here.
4804          */
4805         need_scaling = src_w != dst_w || src_h != dst_h;
4806
4807         if (plane_scaler_check)
4808                 if (pixel_format == DRM_FORMAT_NV12)
4809                         need_scaling = true;
4810
4811         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4812                 need_scaling = true;
4813
4814         /*
4815          * Scaling/fitting not supported in IF-ID mode in GEN9+
4816          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4817          * Once NV12 is enabled, handle it here while allocating scaler
4818          * for NV12.
4819          */
4820         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4821             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4822                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4823                 return -EINVAL;
4824         }
4825
4826         /*
4827          * if plane is being disabled or scaler is no more required or force detach
4828          *  - free scaler binded to this plane/crtc
4829          *  - in order to do this, update crtc->scaler_usage
4830          *
4831          * Here scaler state in crtc_state is set free so that
4832          * scaler can be assigned to other user. Actual register
4833          * update to free the scaler is done in plane/panel-fit programming.
4834          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4835          */
4836         if (force_detach || !need_scaling) {
4837                 if (*scaler_id >= 0) {
4838                         scaler_state->scaler_users &= ~(1 << scaler_user);
4839                         scaler_state->scalers[*scaler_id].in_use = 0;
4840
4841                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4842                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4843                                 intel_crtc->pipe, scaler_user, *scaler_id,
4844                                 scaler_state->scaler_users);
4845                         *scaler_id = -1;
4846                 }
4847                 return 0;
4848         }
4849
4850         if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
4851             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
4852                 DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4853                 return -EINVAL;
4854         }
4855
4856         /* range checks */
4857         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4858             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4859             (IS_GEN11(dev_priv) &&
4860              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4861               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4862             (!IS_GEN11(dev_priv) &&
4863              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4864               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4865                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4866                         "size is out of scaler range\n",
4867                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4868                 return -EINVAL;
4869         }
4870
4871         /* mark this plane as a scaler user in crtc_state */
4872         scaler_state->scaler_users |= (1 << scaler_user);
4873         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4874                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4875                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4876                 scaler_state->scaler_users);
4877
4878         return 0;
4879 }
4880
4881 /**
4882  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4883  *
4884  * @state: crtc's scaler state
4885  *
4886  * Return
4887  *     0 - scaler_usage updated successfully
4888  *    error - requested scaling cannot be supported or other error condition
4889  */
4890 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4891 {
4892         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4893
4894         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4895                                  &state->scaler_state.scaler_id,
4896                                  state->pipe_src_w, state->pipe_src_h,
4897                                  adjusted_mode->crtc_hdisplay,
4898                                  adjusted_mode->crtc_vdisplay, false, 0);
4899 }
4900
4901 /**
4902  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4903  * @crtc_state: crtc's scaler state
4904  * @plane_state: atomic plane state to update
4905  *
4906  * Return
4907  *     0 - scaler_usage updated successfully
4908  *    error - requested scaling cannot be supported or other error condition
4909  */
4910 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4911                                    struct intel_plane_state *plane_state)
4912 {
4913
4914         struct intel_plane *intel_plane =
4915                 to_intel_plane(plane_state->base.plane);
4916         struct drm_framebuffer *fb = plane_state->base.fb;
4917         int ret;
4918
4919         bool force_detach = !fb || !plane_state->base.visible;
4920
4921         ret = skl_update_scaler(crtc_state, force_detach,
4922                                 drm_plane_index(&intel_plane->base),
4923                                 &plane_state->scaler_id,
4924                                 drm_rect_width(&plane_state->base.src) >> 16,
4925                                 drm_rect_height(&plane_state->base.src) >> 16,
4926                                 drm_rect_width(&plane_state->base.dst),
4927                                 drm_rect_height(&plane_state->base.dst),
4928                                 fb ? true : false, fb ? fb->format->format : 0);
4929
4930         if (ret || plane_state->scaler_id < 0)
4931                 return ret;
4932
4933         /* check colorkey */
4934         if (plane_state->ckey.flags) {
4935                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4936                               intel_plane->base.base.id,
4937                               intel_plane->base.name);
4938                 return -EINVAL;
4939         }
4940
4941         /* Check src format */
4942         switch (fb->format->format) {
4943         case DRM_FORMAT_RGB565:
4944         case DRM_FORMAT_XBGR8888:
4945         case DRM_FORMAT_XRGB8888:
4946         case DRM_FORMAT_ABGR8888:
4947         case DRM_FORMAT_ARGB8888:
4948         case DRM_FORMAT_XRGB2101010:
4949         case DRM_FORMAT_XBGR2101010:
4950         case DRM_FORMAT_YUYV:
4951         case DRM_FORMAT_YVYU:
4952         case DRM_FORMAT_UYVY:
4953         case DRM_FORMAT_VYUY:
4954         case DRM_FORMAT_NV12:
4955                 break;
4956         default:
4957                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4958                               intel_plane->base.base.id, intel_plane->base.name,
4959                               fb->base.id, fb->format->format);
4960                 return -EINVAL;
4961         }
4962
4963         return 0;
4964 }
4965
4966 static void skylake_scaler_disable(struct intel_crtc *crtc)
4967 {
4968         int i;
4969
4970         for (i = 0; i < crtc->num_scalers; i++)
4971                 skl_detach_scaler(crtc, i);
4972 }
4973
4974 static void skylake_pfit_enable(struct intel_crtc *crtc)
4975 {
4976         struct drm_device *dev = crtc->base.dev;
4977         struct drm_i915_private *dev_priv = to_i915(dev);
4978         int pipe = crtc->pipe;
4979         struct intel_crtc_scaler_state *scaler_state =
4980                 &crtc->config->scaler_state;
4981
4982         if (crtc->config->pch_pfit.enabled) {
4983                 int id;
4984
4985                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4986                         return;
4987
4988                 id = scaler_state->scaler_id;
4989                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4990                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4991                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4992                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4993         }
4994 }
4995
4996 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4997 {
4998         struct drm_device *dev = crtc->base.dev;
4999         struct drm_i915_private *dev_priv = to_i915(dev);
5000         int pipe = crtc->pipe;
5001
5002         if (crtc->config->pch_pfit.enabled) {
5003                 /* Force use of hard-coded filter coefficients
5004                  * as some pre-programmed values are broken,
5005                  * e.g. x201.
5006                  */
5007                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5008                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5009                                                  PF_PIPE_SEL_IVB(pipe));
5010                 else
5011                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5012                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
5013                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
5014         }
5015 }
5016
5017 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5018 {
5019         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5020         struct drm_device *dev = crtc->base.dev;
5021         struct drm_i915_private *dev_priv = to_i915(dev);
5022
5023         if (!crtc_state->ips_enabled)
5024                 return;
5025
5026         /*
5027          * We can only enable IPS after we enable a plane and wait for a vblank
5028          * This function is called from post_plane_update, which is run after
5029          * a vblank wait.
5030          */
5031         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5032
5033         if (IS_BROADWELL(dev_priv)) {
5034                 mutex_lock(&dev_priv->pcu_lock);
5035                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5036                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5037                 mutex_unlock(&dev_priv->pcu_lock);
5038                 /* Quoting Art Runyan: "its not safe to expect any particular
5039                  * value in IPS_CTL bit 31 after enabling IPS through the
5040                  * mailbox." Moreover, the mailbox may return a bogus state,
5041                  * so we need to just enable it and continue on.
5042                  */
5043         } else {
5044                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5045                 /* The bit only becomes 1 in the next vblank, so this wait here
5046                  * is essentially intel_wait_for_vblank. If we don't have this
5047                  * and don't wait for vblanks until the end of crtc_enable, then
5048                  * the HW state readout code will complain that the expected
5049                  * IPS_CTL value is not the one we read. */
5050                 if (intel_wait_for_register(dev_priv,
5051                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5052                                             50))
5053                         DRM_ERROR("Timed out waiting for IPS enable\n");
5054         }
5055 }
5056
5057 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5058 {
5059         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5060         struct drm_device *dev = crtc->base.dev;
5061         struct drm_i915_private *dev_priv = to_i915(dev);
5062
5063         if (!crtc_state->ips_enabled)
5064                 return;
5065
5066         if (IS_BROADWELL(dev_priv)) {
5067                 mutex_lock(&dev_priv->pcu_lock);
5068                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5069                 mutex_unlock(&dev_priv->pcu_lock);
5070                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
5071                 if (intel_wait_for_register(dev_priv,
5072                                             IPS_CTL, IPS_ENABLE, 0,
5073                                             42))
5074                         DRM_ERROR("Timed out waiting for IPS disable\n");
5075         } else {
5076                 I915_WRITE(IPS_CTL, 0);
5077                 POSTING_READ(IPS_CTL);
5078         }
5079
5080         /* We need to wait for a vblank before we can disable the plane. */
5081         intel_wait_for_vblank(dev_priv, crtc->pipe);
5082 }
5083
5084 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5085 {
5086         if (intel_crtc->overlay) {
5087                 struct drm_device *dev = intel_crtc->base.dev;
5088
5089                 mutex_lock(&dev->struct_mutex);
5090                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5091                 mutex_unlock(&dev->struct_mutex);
5092         }
5093
5094         /* Let userspace switch the overlay on again. In most cases userspace
5095          * has to recompute where to put it anyway.
5096          */
5097 }
5098
5099 /**
5100  * intel_post_enable_primary - Perform operations after enabling primary plane
5101  * @crtc: the CRTC whose primary plane was just enabled
5102  * @new_crtc_state: the enabling state
5103  *
5104  * Performs potentially sleeping operations that must be done after the primary
5105  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5106  * called due to an explicit primary plane update, or due to an implicit
5107  * re-enable that is caused when a sprite plane is updated to no longer
5108  * completely hide the primary plane.
5109  */
5110 static void
5111 intel_post_enable_primary(struct drm_crtc *crtc,
5112                           const struct intel_crtc_state *new_crtc_state)
5113 {
5114         struct drm_device *dev = crtc->dev;
5115         struct drm_i915_private *dev_priv = to_i915(dev);
5116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5117         int pipe = intel_crtc->pipe;
5118
5119         /*
5120          * Gen2 reports pipe underruns whenever all planes are disabled.
5121          * So don't enable underrun reporting before at least some planes
5122          * are enabled.
5123          * FIXME: Need to fix the logic to work when we turn off all planes
5124          * but leave the pipe running.
5125          */
5126         if (IS_GEN2(dev_priv))
5127                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5128
5129         /* Underruns don't always raise interrupts, so check manually. */
5130         intel_check_cpu_fifo_underruns(dev_priv);
5131         intel_check_pch_fifo_underruns(dev_priv);
5132 }
5133
5134 /* FIXME get rid of this and use pre_plane_update */
5135 static void
5136 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5137 {
5138         struct drm_device *dev = crtc->dev;
5139         struct drm_i915_private *dev_priv = to_i915(dev);
5140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5141         int pipe = intel_crtc->pipe;
5142
5143         /*
5144          * Gen2 reports pipe underruns whenever all planes are disabled.
5145          * So disable underrun reporting before all the planes get disabled.
5146          */
5147         if (IS_GEN2(dev_priv))
5148                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5149
5150         hsw_disable_ips(to_intel_crtc_state(crtc->state));
5151
5152         /*
5153          * Vblank time updates from the shadow to live plane control register
5154          * are blocked if the memory self-refresh mode is active at that
5155          * moment. So to make sure the plane gets truly disabled, disable
5156          * first the self-refresh mode. The self-refresh enable bit in turn
5157          * will be checked/applied by the HW only at the next frame start
5158          * event which is after the vblank start event, so we need to have a
5159          * wait-for-vblank between disabling the plane and the pipe.
5160          */
5161         if (HAS_GMCH_DISPLAY(dev_priv) &&
5162             intel_set_memory_cxsr(dev_priv, false))
5163                 intel_wait_for_vblank(dev_priv, pipe);
5164 }
5165
5166 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5167                                        const struct intel_crtc_state *new_crtc_state)
5168 {
5169         if (!old_crtc_state->ips_enabled)
5170                 return false;
5171
5172         if (needs_modeset(&new_crtc_state->base))
5173                 return true;
5174
5175         return !new_crtc_state->ips_enabled;
5176 }
5177
5178 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5179                                        const struct intel_crtc_state *new_crtc_state)
5180 {
5181         if (!new_crtc_state->ips_enabled)
5182                 return false;
5183
5184         if (needs_modeset(&new_crtc_state->base))
5185                 return true;
5186
5187         /*
5188          * We can't read out IPS on broadwell, assume the worst and
5189          * forcibly enable IPS on the first fastset.
5190          */
5191         if (new_crtc_state->update_pipe &&
5192             old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5193                 return true;
5194
5195         return !old_crtc_state->ips_enabled;
5196 }
5197
5198 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5199                           const struct intel_crtc_state *crtc_state)
5200 {
5201         if (!crtc_state->nv12_planes)
5202                 return false;
5203
5204         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
5205                 return false;
5206
5207         if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5208             IS_CANNONLAKE(dev_priv))
5209                 return true;
5210
5211         return false;
5212 }
5213
5214 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5215 {
5216         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5217         struct drm_device *dev = crtc->base.dev;
5218         struct drm_i915_private *dev_priv = to_i915(dev);
5219         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5220         struct intel_crtc_state *pipe_config =
5221                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5222                                                 crtc);
5223         struct drm_plane *primary = crtc->base.primary;
5224         struct drm_plane_state *old_primary_state =
5225                 drm_atomic_get_old_plane_state(old_state, primary);
5226
5227         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5228
5229         if (pipe_config->update_wm_post && pipe_config->base.active)
5230                 intel_update_watermarks(crtc);
5231
5232         if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5233                 hsw_enable_ips(pipe_config);
5234
5235         if (old_primary_state) {
5236                 struct drm_plane_state *new_primary_state =
5237                         drm_atomic_get_new_plane_state(old_state, primary);
5238
5239                 intel_fbc_post_update(crtc);
5240
5241                 if (new_primary_state->visible &&
5242                     (needs_modeset(&pipe_config->base) ||
5243                      !old_primary_state->visible))
5244                         intel_post_enable_primary(&crtc->base, pipe_config);
5245         }
5246
5247         /* Display WA 827 */
5248         if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5249             !needs_nv12_wa(dev_priv, pipe_config)) {
5250                 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5251                 skl_wa_528(dev_priv, crtc->pipe, false);
5252         }
5253 }
5254
5255 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5256                                    struct intel_crtc_state *pipe_config)
5257 {
5258         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5259         struct drm_device *dev = crtc->base.dev;
5260         struct drm_i915_private *dev_priv = to_i915(dev);
5261         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5262         struct drm_plane *primary = crtc->base.primary;
5263         struct drm_plane_state *old_primary_state =
5264                 drm_atomic_get_old_plane_state(old_state, primary);
5265         bool modeset = needs_modeset(&pipe_config->base);
5266         struct intel_atomic_state *old_intel_state =
5267                 to_intel_atomic_state(old_state);
5268
5269         if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5270                 hsw_disable_ips(old_crtc_state);
5271
5272         if (old_primary_state) {
5273                 struct intel_plane_state *new_primary_state =
5274                         intel_atomic_get_new_plane_state(old_intel_state,
5275                                                          to_intel_plane(primary));
5276
5277                 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5278                 /*
5279                  * Gen2 reports pipe underruns whenever all planes are disabled.
5280                  * So disable underrun reporting before all the planes get disabled.
5281                  */
5282                 if (IS_GEN2(dev_priv) && old_primary_state->visible &&
5283                     (modeset || !new_primary_state->base.visible))
5284                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5285         }
5286
5287         /* Display WA 827 */
5288         if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5289             needs_nv12_wa(dev_priv, pipe_config)) {
5290                 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5291                 skl_wa_528(dev_priv, crtc->pipe, true);
5292         }
5293
5294         /*
5295          * Vblank time updates from the shadow to live plane control register
5296          * are blocked if the memory self-refresh mode is active at that
5297          * moment. So to make sure the plane gets truly disabled, disable
5298          * first the self-refresh mode. The self-refresh enable bit in turn
5299          * will be checked/applied by the HW only at the next frame start
5300          * event which is after the vblank start event, so we need to have a
5301          * wait-for-vblank between disabling the plane and the pipe.
5302          */
5303         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5304             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5305                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5306
5307         /*
5308          * IVB workaround: must disable low power watermarks for at least
5309          * one frame before enabling scaling.  LP watermarks can be re-enabled
5310          * when scaling is disabled.
5311          *
5312          * WaCxSRDisabledForSpriteScaling:ivb
5313          */
5314         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5315                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5316
5317         /*
5318          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5319          * watermark programming here.
5320          */
5321         if (needs_modeset(&pipe_config->base))
5322                 return;
5323
5324         /*
5325          * For platforms that support atomic watermarks, program the
5326          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5327          * will be the intermediate values that are safe for both pre- and
5328          * post- vblank; when vblank happens, the 'active' values will be set
5329          * to the final 'target' values and we'll do this again to get the
5330          * optimal watermarks.  For gen9+ platforms, the values we program here
5331          * will be the final target values which will get automatically latched
5332          * at vblank time; no further programming will be necessary.
5333          *
5334          * If a platform hasn't been transitioned to atomic watermarks yet,
5335          * we'll continue to update watermarks the old way, if flags tell
5336          * us to.
5337          */
5338         if (dev_priv->display.initial_watermarks != NULL)
5339                 dev_priv->display.initial_watermarks(old_intel_state,
5340                                                      pipe_config);
5341         else if (pipe_config->update_wm_pre)
5342                 intel_update_watermarks(crtc);
5343 }
5344
5345 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5346 {
5347         struct drm_device *dev = crtc->dev;
5348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5349         struct drm_plane *p;
5350         int pipe = intel_crtc->pipe;
5351
5352         intel_crtc_dpms_overlay_disable(intel_crtc);
5353
5354         drm_for_each_plane_mask(p, dev, plane_mask)
5355                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5356
5357         /*
5358          * FIXME: Once we grow proper nuclear flip support out of this we need
5359          * to compute the mask of flip planes precisely. For the time being
5360          * consider this a flip to a NULL plane.
5361          */
5362         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5363 }
5364
5365 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5366                                           struct intel_crtc_state *crtc_state,
5367                                           struct drm_atomic_state *old_state)
5368 {
5369         struct drm_connector_state *conn_state;
5370         struct drm_connector *conn;
5371         int i;
5372
5373         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5374                 struct intel_encoder *encoder =
5375                         to_intel_encoder(conn_state->best_encoder);
5376
5377                 if (conn_state->crtc != crtc)
5378                         continue;
5379
5380                 if (encoder->pre_pll_enable)
5381                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5382         }
5383 }
5384
5385 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5386                                       struct intel_crtc_state *crtc_state,
5387                                       struct drm_atomic_state *old_state)
5388 {
5389         struct drm_connector_state *conn_state;
5390         struct drm_connector *conn;
5391         int i;
5392
5393         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5394                 struct intel_encoder *encoder =
5395                         to_intel_encoder(conn_state->best_encoder);
5396
5397                 if (conn_state->crtc != crtc)
5398                         continue;
5399
5400                 if (encoder->pre_enable)
5401                         encoder->pre_enable(encoder, crtc_state, conn_state);
5402         }
5403 }
5404
5405 static void intel_encoders_enable(struct drm_crtc *crtc,
5406                                   struct intel_crtc_state *crtc_state,
5407                                   struct drm_atomic_state *old_state)
5408 {
5409         struct drm_connector_state *conn_state;
5410         struct drm_connector *conn;
5411         int i;
5412
5413         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5414                 struct intel_encoder *encoder =
5415                         to_intel_encoder(conn_state->best_encoder);
5416
5417                 if (conn_state->crtc != crtc)
5418                         continue;
5419
5420                 encoder->enable(encoder, crtc_state, conn_state);
5421                 intel_opregion_notify_encoder(encoder, true);
5422         }
5423 }
5424
5425 static void intel_encoders_disable(struct drm_crtc *crtc,
5426                                    struct intel_crtc_state *old_crtc_state,
5427                                    struct drm_atomic_state *old_state)
5428 {
5429         struct drm_connector_state *old_conn_state;
5430         struct drm_connector *conn;
5431         int i;
5432
5433         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5434                 struct intel_encoder *encoder =
5435                         to_intel_encoder(old_conn_state->best_encoder);
5436
5437                 if (old_conn_state->crtc != crtc)
5438                         continue;
5439
5440                 intel_opregion_notify_encoder(encoder, false);
5441                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5442         }
5443 }
5444
5445 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5446                                         struct intel_crtc_state *old_crtc_state,
5447                                         struct drm_atomic_state *old_state)
5448 {
5449         struct drm_connector_state *old_conn_state;
5450         struct drm_connector *conn;
5451         int i;
5452
5453         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5454                 struct intel_encoder *encoder =
5455                         to_intel_encoder(old_conn_state->best_encoder);
5456
5457                 if (old_conn_state->crtc != crtc)
5458                         continue;
5459
5460                 if (encoder->post_disable)
5461                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5462         }
5463 }
5464
5465 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5466                                             struct intel_crtc_state *old_crtc_state,
5467                                             struct drm_atomic_state *old_state)
5468 {
5469         struct drm_connector_state *old_conn_state;
5470         struct drm_connector *conn;
5471         int i;
5472
5473         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5474                 struct intel_encoder *encoder =
5475                         to_intel_encoder(old_conn_state->best_encoder);
5476
5477                 if (old_conn_state->crtc != crtc)
5478                         continue;
5479
5480                 if (encoder->post_pll_disable)
5481                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5482         }
5483 }
5484
5485 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5486                                  struct drm_atomic_state *old_state)
5487 {
5488         struct drm_crtc *crtc = pipe_config->base.crtc;
5489         struct drm_device *dev = crtc->dev;
5490         struct drm_i915_private *dev_priv = to_i915(dev);
5491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5492         int pipe = intel_crtc->pipe;
5493         struct intel_atomic_state *old_intel_state =
5494                 to_intel_atomic_state(old_state);
5495
5496         if (WARN_ON(intel_crtc->active))
5497                 return;
5498
5499         /*
5500          * Sometimes spurious CPU pipe underruns happen during FDI
5501          * training, at least with VGA+HDMI cloning. Suppress them.
5502          *
5503          * On ILK we get an occasional spurious CPU pipe underruns
5504          * between eDP port A enable and vdd enable. Also PCH port
5505          * enable seems to result in the occasional CPU pipe underrun.
5506          *
5507          * Spurious PCH underruns also occur during PCH enabling.
5508          */
5509         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5510                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5511         if (intel_crtc->config->has_pch_encoder)
5512                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5513
5514         if (intel_crtc->config->has_pch_encoder)
5515                 intel_prepare_shared_dpll(intel_crtc);
5516
5517         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5518                 intel_dp_set_m_n(intel_crtc, M1_N1);
5519
5520         intel_set_pipe_timings(intel_crtc);
5521         intel_set_pipe_src_size(intel_crtc);
5522
5523         if (intel_crtc->config->has_pch_encoder) {
5524                 intel_cpu_transcoder_set_m_n(intel_crtc,
5525                                      &intel_crtc->config->fdi_m_n, NULL);
5526         }
5527
5528         ironlake_set_pipeconf(crtc);
5529
5530         intel_crtc->active = true;
5531
5532         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5533
5534         if (intel_crtc->config->has_pch_encoder) {
5535                 /* Note: FDI PLL enabling _must_ be done before we enable the
5536                  * cpu pipes, hence this is separate from all the other fdi/pch
5537                  * enabling. */
5538                 ironlake_fdi_pll_enable(intel_crtc);
5539         } else {
5540                 assert_fdi_tx_disabled(dev_priv, pipe);
5541                 assert_fdi_rx_disabled(dev_priv, pipe);
5542         }
5543
5544         ironlake_pfit_enable(intel_crtc);
5545
5546         /*
5547          * On ILK+ LUT must be loaded before the pipe is running but with
5548          * clocks enabled
5549          */
5550         intel_color_load_luts(&pipe_config->base);
5551
5552         if (dev_priv->display.initial_watermarks != NULL)
5553                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5554         intel_enable_pipe(pipe_config);
5555
5556         if (intel_crtc->config->has_pch_encoder)
5557                 ironlake_pch_enable(pipe_config);
5558
5559         assert_vblank_disabled(crtc);
5560         drm_crtc_vblank_on(crtc);
5561
5562         intel_encoders_enable(crtc, pipe_config, old_state);
5563
5564         if (HAS_PCH_CPT(dev_priv))
5565                 cpt_verify_modeset(dev, intel_crtc->pipe);
5566
5567         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5568         if (intel_crtc->config->has_pch_encoder)
5569                 intel_wait_for_vblank(dev_priv, pipe);
5570         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5571         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5572 }
5573
5574 /* IPS only exists on ULT machines and is tied to pipe A. */
5575 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5576 {
5577         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5578 }
5579
5580 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5581                                             enum pipe pipe, bool apply)
5582 {
5583         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5584         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5585
5586         if (apply)
5587                 val |= mask;
5588         else
5589                 val &= ~mask;
5590
5591         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5592 }
5593
5594 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5595 {
5596         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5597         enum pipe pipe = crtc->pipe;
5598         uint32_t val;
5599
5600         val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
5601
5602         /* Program B credit equally to all pipes */
5603         val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5604
5605         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5606 }
5607
5608 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5609                                 struct drm_atomic_state *old_state)
5610 {
5611         struct drm_crtc *crtc = pipe_config->base.crtc;
5612         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5614         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5615         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5616         struct intel_atomic_state *old_intel_state =
5617                 to_intel_atomic_state(old_state);
5618         bool psl_clkgate_wa;
5619
5620         if (WARN_ON(intel_crtc->active))
5621                 return;
5622
5623         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5624
5625         if (intel_crtc->config->shared_dpll)
5626                 intel_enable_shared_dpll(intel_crtc);
5627
5628         if (INTEL_GEN(dev_priv) >= 11)
5629                 icl_map_plls_to_ports(crtc, pipe_config, old_state);
5630
5631         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5632                 intel_dp_set_m_n(intel_crtc, M1_N1);
5633
5634         if (!transcoder_is_dsi(cpu_transcoder))
5635                 intel_set_pipe_timings(intel_crtc);
5636
5637         intel_set_pipe_src_size(intel_crtc);
5638
5639         if (cpu_transcoder != TRANSCODER_EDP &&
5640             !transcoder_is_dsi(cpu_transcoder)) {
5641                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5642                            intel_crtc->config->pixel_multiplier - 1);
5643         }
5644
5645         if (intel_crtc->config->has_pch_encoder) {
5646                 intel_cpu_transcoder_set_m_n(intel_crtc,
5647                                      &intel_crtc->config->fdi_m_n, NULL);
5648         }
5649
5650         if (!transcoder_is_dsi(cpu_transcoder))
5651                 haswell_set_pipeconf(crtc);
5652
5653         haswell_set_pipemisc(crtc);
5654
5655         intel_color_set_csc(&pipe_config->base);
5656
5657         intel_crtc->active = true;
5658
5659         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5660
5661         if (!transcoder_is_dsi(cpu_transcoder))
5662                 intel_ddi_enable_pipe_clock(pipe_config);
5663
5664         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5665         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5666                          intel_crtc->config->pch_pfit.enabled;
5667         if (psl_clkgate_wa)
5668                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5669
5670         if (INTEL_GEN(dev_priv) >= 9)
5671                 skylake_pfit_enable(intel_crtc);
5672         else
5673                 ironlake_pfit_enable(intel_crtc);
5674
5675         /*
5676          * On ILK+ LUT must be loaded before the pipe is running but with
5677          * clocks enabled
5678          */
5679         intel_color_load_luts(&pipe_config->base);
5680
5681         intel_ddi_set_pipe_settings(pipe_config);
5682         if (!transcoder_is_dsi(cpu_transcoder))
5683                 intel_ddi_enable_transcoder_func(pipe_config);
5684
5685         if (dev_priv->display.initial_watermarks != NULL)
5686                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5687
5688         if (INTEL_GEN(dev_priv) >= 11)
5689                 icl_pipe_mbus_enable(intel_crtc);
5690
5691         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5692         if (!transcoder_is_dsi(cpu_transcoder))
5693                 intel_enable_pipe(pipe_config);
5694
5695         if (intel_crtc->config->has_pch_encoder)
5696                 lpt_pch_enable(pipe_config);
5697
5698         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5699                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5700
5701         assert_vblank_disabled(crtc);
5702         drm_crtc_vblank_on(crtc);
5703
5704         intel_encoders_enable(crtc, pipe_config, old_state);
5705
5706         if (psl_clkgate_wa) {
5707                 intel_wait_for_vblank(dev_priv, pipe);
5708                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5709         }
5710
5711         /* If we change the relative order between pipe/planes enabling, we need
5712          * to change the workaround. */
5713         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5714         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5715                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5716                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5717         }
5718 }
5719
5720 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5721 {
5722         struct drm_device *dev = crtc->base.dev;
5723         struct drm_i915_private *dev_priv = to_i915(dev);
5724         int pipe = crtc->pipe;
5725
5726         /* To avoid upsetting the power well on haswell only disable the pfit if
5727          * it's in use. The hw state code will make sure we get this right. */
5728         if (force || crtc->config->pch_pfit.enabled) {
5729                 I915_WRITE(PF_CTL(pipe), 0);
5730                 I915_WRITE(PF_WIN_POS(pipe), 0);
5731                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5732         }
5733 }
5734
5735 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5736                                   struct drm_atomic_state *old_state)
5737 {
5738         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5739         struct drm_device *dev = crtc->dev;
5740         struct drm_i915_private *dev_priv = to_i915(dev);
5741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5742         int pipe = intel_crtc->pipe;
5743
5744         /*
5745          * Sometimes spurious CPU pipe underruns happen when the
5746          * pipe is already disabled, but FDI RX/TX is still enabled.
5747          * Happens at least with VGA+HDMI cloning. Suppress them.
5748          */
5749         if (intel_crtc->config->has_pch_encoder) {
5750                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5751                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5752         }
5753
5754         intel_encoders_disable(crtc, old_crtc_state, old_state);
5755
5756         drm_crtc_vblank_off(crtc);
5757         assert_vblank_disabled(crtc);
5758
5759         intel_disable_pipe(old_crtc_state);
5760
5761         ironlake_pfit_disable(intel_crtc, false);
5762
5763         if (intel_crtc->config->has_pch_encoder)
5764                 ironlake_fdi_disable(crtc);
5765
5766         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5767
5768         if (intel_crtc->config->has_pch_encoder) {
5769                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5770
5771                 if (HAS_PCH_CPT(dev_priv)) {
5772                         i915_reg_t reg;
5773                         u32 temp;
5774
5775                         /* disable TRANS_DP_CTL */
5776                         reg = TRANS_DP_CTL(pipe);
5777                         temp = I915_READ(reg);
5778                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5779                                   TRANS_DP_PORT_SEL_MASK);
5780                         temp |= TRANS_DP_PORT_SEL_NONE;
5781                         I915_WRITE(reg, temp);
5782
5783                         /* disable DPLL_SEL */
5784                         temp = I915_READ(PCH_DPLL_SEL);
5785                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5786                         I915_WRITE(PCH_DPLL_SEL, temp);
5787                 }
5788
5789                 ironlake_fdi_pll_disable(intel_crtc);
5790         }
5791
5792         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5793         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5794 }
5795
5796 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5797                                  struct drm_atomic_state *old_state)
5798 {
5799         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5800         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5802         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5803
5804         intel_encoders_disable(crtc, old_crtc_state, old_state);
5805
5806         drm_crtc_vblank_off(crtc);
5807         assert_vblank_disabled(crtc);
5808
5809         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5810         if (!transcoder_is_dsi(cpu_transcoder))
5811                 intel_disable_pipe(old_crtc_state);
5812
5813         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5814                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5815
5816         if (!transcoder_is_dsi(cpu_transcoder))
5817                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5818
5819         if (INTEL_GEN(dev_priv) >= 9)
5820                 skylake_scaler_disable(intel_crtc);
5821         else
5822                 ironlake_pfit_disable(intel_crtc, false);
5823
5824         if (!transcoder_is_dsi(cpu_transcoder))
5825                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5826
5827         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5828
5829         if (INTEL_GEN(dev_priv) >= 11)
5830                 icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
5831 }
5832
5833 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5834 {
5835         struct drm_device *dev = crtc->base.dev;
5836         struct drm_i915_private *dev_priv = to_i915(dev);
5837         struct intel_crtc_state *pipe_config = crtc->config;
5838
5839         if (!pipe_config->gmch_pfit.control)
5840                 return;
5841
5842         /*
5843          * The panel fitter should only be adjusted whilst the pipe is disabled,
5844          * according to register description and PRM.
5845          */
5846         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5847         assert_pipe_disabled(dev_priv, crtc->pipe);
5848
5849         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5850         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5851
5852         /* Border color in case we don't scale up to the full screen. Black by
5853          * default, change to something else for debugging. */
5854         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5855 }
5856
5857 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5858 {
5859         switch (port) {
5860         case PORT_A:
5861                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5862         case PORT_B:
5863                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5864         case PORT_C:
5865                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5866         case PORT_D:
5867                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5868         case PORT_E:
5869                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5870         case PORT_F:
5871                 return POWER_DOMAIN_PORT_DDI_F_LANES;
5872         default:
5873                 MISSING_CASE(port);
5874                 return POWER_DOMAIN_PORT_OTHER;
5875         }
5876 }
5877
5878 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5879                                   struct intel_crtc_state *crtc_state)
5880 {
5881         struct drm_device *dev = crtc->dev;
5882         struct drm_i915_private *dev_priv = to_i915(dev);
5883         struct drm_encoder *encoder;
5884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5885         enum pipe pipe = intel_crtc->pipe;
5886         u64 mask;
5887         enum transcoder transcoder = crtc_state->cpu_transcoder;
5888
5889         if (!crtc_state->base.active)
5890                 return 0;
5891
5892         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
5893         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
5894         if (crtc_state->pch_pfit.enabled ||
5895             crtc_state->pch_pfit.force_thru)
5896                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5897
5898         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5899                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5900
5901                 mask |= BIT_ULL(intel_encoder->power_domain);
5902         }
5903
5904         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5905                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
5906
5907         if (crtc_state->shared_dpll)
5908                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5909
5910         return mask;
5911 }
5912
5913 static u64
5914 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5915                                struct intel_crtc_state *crtc_state)
5916 {
5917         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5919         enum intel_display_power_domain domain;
5920         u64 domains, new_domains, old_domains;
5921
5922         old_domains = intel_crtc->enabled_power_domains;
5923         intel_crtc->enabled_power_domains = new_domains =
5924                 get_crtc_power_domains(crtc, crtc_state);
5925
5926         domains = new_domains & ~old_domains;
5927
5928         for_each_power_domain(domain, domains)
5929                 intel_display_power_get(dev_priv, domain);
5930
5931         return old_domains & ~new_domains;
5932 }
5933
5934 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5935                                       u64 domains)
5936 {
5937         enum intel_display_power_domain domain;
5938
5939         for_each_power_domain(domain, domains)
5940                 intel_display_power_put(dev_priv, domain);
5941 }
5942
5943 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5944                                    struct drm_atomic_state *old_state)
5945 {
5946         struct intel_atomic_state *old_intel_state =
5947                 to_intel_atomic_state(old_state);
5948         struct drm_crtc *crtc = pipe_config->base.crtc;
5949         struct drm_device *dev = crtc->dev;
5950         struct drm_i915_private *dev_priv = to_i915(dev);
5951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5952         int pipe = intel_crtc->pipe;
5953
5954         if (WARN_ON(intel_crtc->active))
5955                 return;
5956
5957         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5958                 intel_dp_set_m_n(intel_crtc, M1_N1);
5959
5960         intel_set_pipe_timings(intel_crtc);
5961         intel_set_pipe_src_size(intel_crtc);
5962
5963         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5964                 struct drm_i915_private *dev_priv = to_i915(dev);
5965
5966                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5967                 I915_WRITE(CHV_CANVAS(pipe), 0);
5968         }
5969
5970         i9xx_set_pipeconf(intel_crtc);
5971
5972         intel_crtc->active = true;
5973
5974         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5975
5976         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5977
5978         if (IS_CHERRYVIEW(dev_priv)) {
5979                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5980                 chv_enable_pll(intel_crtc, intel_crtc->config);
5981         } else {
5982                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5983                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5984         }
5985
5986         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5987
5988         i9xx_pfit_enable(intel_crtc);
5989
5990         intel_color_load_luts(&pipe_config->base);
5991
5992         dev_priv->display.initial_watermarks(old_intel_state,
5993                                              pipe_config);
5994         intel_enable_pipe(pipe_config);
5995
5996         assert_vblank_disabled(crtc);
5997         drm_crtc_vblank_on(crtc);
5998
5999         intel_encoders_enable(crtc, pipe_config, old_state);
6000 }
6001
6002 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6003 {
6004         struct drm_device *dev = crtc->base.dev;
6005         struct drm_i915_private *dev_priv = to_i915(dev);
6006
6007         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6008         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6009 }
6010
6011 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6012                              struct drm_atomic_state *old_state)
6013 {
6014         struct intel_atomic_state *old_intel_state =
6015                 to_intel_atomic_state(old_state);
6016         struct drm_crtc *crtc = pipe_config->base.crtc;
6017         struct drm_device *dev = crtc->dev;
6018         struct drm_i915_private *dev_priv = to_i915(dev);
6019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6020         enum pipe pipe = intel_crtc->pipe;
6021
6022         if (WARN_ON(intel_crtc->active))
6023                 return;
6024
6025         i9xx_set_pll_dividers(intel_crtc);
6026
6027         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6028                 intel_dp_set_m_n(intel_crtc, M1_N1);
6029
6030         intel_set_pipe_timings(intel_crtc);
6031         intel_set_pipe_src_size(intel_crtc);
6032
6033         i9xx_set_pipeconf(intel_crtc);
6034
6035         intel_crtc->active = true;
6036
6037         if (!IS_GEN2(dev_priv))
6038                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6039
6040         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6041
6042         i9xx_enable_pll(intel_crtc, pipe_config);
6043
6044         i9xx_pfit_enable(intel_crtc);
6045
6046         intel_color_load_luts(&pipe_config->base);
6047
6048         if (dev_priv->display.initial_watermarks != NULL)
6049                 dev_priv->display.initial_watermarks(old_intel_state,
6050                                                      intel_crtc->config);
6051         else
6052                 intel_update_watermarks(intel_crtc);
6053         intel_enable_pipe(pipe_config);
6054
6055         assert_vblank_disabled(crtc);
6056         drm_crtc_vblank_on(crtc);
6057
6058         intel_encoders_enable(crtc, pipe_config, old_state);
6059 }
6060
6061 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6062 {
6063         struct drm_device *dev = crtc->base.dev;
6064         struct drm_i915_private *dev_priv = to_i915(dev);
6065
6066         if (!crtc->config->gmch_pfit.control)
6067                 return;
6068
6069         assert_pipe_disabled(dev_priv, crtc->pipe);
6070
6071         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6072                          I915_READ(PFIT_CONTROL));
6073         I915_WRITE(PFIT_CONTROL, 0);
6074 }
6075
6076 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6077                               struct drm_atomic_state *old_state)
6078 {
6079         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6080         struct drm_device *dev = crtc->dev;
6081         struct drm_i915_private *dev_priv = to_i915(dev);
6082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6083         int pipe = intel_crtc->pipe;
6084
6085         /*
6086          * On gen2 planes are double buffered but the pipe isn't, so we must
6087          * wait for planes to fully turn off before disabling the pipe.
6088          */
6089         if (IS_GEN2(dev_priv))
6090                 intel_wait_for_vblank(dev_priv, pipe);
6091
6092         intel_encoders_disable(crtc, old_crtc_state, old_state);
6093
6094         drm_crtc_vblank_off(crtc);
6095         assert_vblank_disabled(crtc);
6096
6097         intel_disable_pipe(old_crtc_state);
6098
6099         i9xx_pfit_disable(intel_crtc);
6100
6101         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6102
6103         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6104                 if (IS_CHERRYVIEW(dev_priv))
6105                         chv_disable_pll(dev_priv, pipe);
6106                 else if (IS_VALLEYVIEW(dev_priv))
6107                         vlv_disable_pll(dev_priv, pipe);
6108                 else
6109                         i9xx_disable_pll(intel_crtc);
6110         }
6111
6112         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6113
6114         if (!IS_GEN2(dev_priv))
6115                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6116
6117         if (!dev_priv->display.initial_watermarks)
6118                 intel_update_watermarks(intel_crtc);
6119
6120         /* clock the pipe down to 640x480@60 to potentially save power */
6121         if (IS_I830(dev_priv))
6122                 i830_enable_pipe(dev_priv, pipe);
6123 }
6124
6125 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6126                                         struct drm_modeset_acquire_ctx *ctx)
6127 {
6128         struct intel_encoder *encoder;
6129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6130         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6131         enum intel_display_power_domain domain;
6132         struct intel_plane *plane;
6133         u64 domains;
6134         struct drm_atomic_state *state;
6135         struct intel_crtc_state *crtc_state;
6136         int ret;
6137
6138         if (!intel_crtc->active)
6139                 return;
6140
6141         for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6142                 const struct intel_plane_state *plane_state =
6143                         to_intel_plane_state(plane->base.state);
6144
6145                 if (plane_state->base.visible)
6146                         intel_plane_disable_noatomic(intel_crtc, plane);
6147         }
6148
6149         state = drm_atomic_state_alloc(crtc->dev);
6150         if (!state) {
6151                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6152                               crtc->base.id, crtc->name);
6153                 return;
6154         }
6155
6156         state->acquire_ctx = ctx;
6157
6158         /* Everything's already locked, -EDEADLK can't happen. */
6159         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6160         ret = drm_atomic_add_affected_connectors(state, crtc);
6161
6162         WARN_ON(IS_ERR(crtc_state) || ret);
6163
6164         dev_priv->display.crtc_disable(crtc_state, state);
6165
6166         drm_atomic_state_put(state);
6167
6168         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6169                       crtc->base.id, crtc->name);
6170
6171         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6172         crtc->state->active = false;
6173         intel_crtc->active = false;
6174         crtc->enabled = false;
6175         crtc->state->connector_mask = 0;
6176         crtc->state->encoder_mask = 0;
6177
6178         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6179                 encoder->base.crtc = NULL;
6180
6181         intel_fbc_disable(intel_crtc);
6182         intel_update_watermarks(intel_crtc);
6183         intel_disable_shared_dpll(intel_crtc);
6184
6185         domains = intel_crtc->enabled_power_domains;
6186         for_each_power_domain(domain, domains)
6187                 intel_display_power_put(dev_priv, domain);
6188         intel_crtc->enabled_power_domains = 0;
6189
6190         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6191         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6192         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6193 }
6194
6195 /*
6196  * turn all crtc's off, but do not adjust state
6197  * This has to be paired with a call to intel_modeset_setup_hw_state.
6198  */
6199 int intel_display_suspend(struct drm_device *dev)
6200 {
6201         struct drm_i915_private *dev_priv = to_i915(dev);
6202         struct drm_atomic_state *state;
6203         int ret;
6204
6205         state = drm_atomic_helper_suspend(dev);
6206         ret = PTR_ERR_OR_ZERO(state);
6207         if (ret)
6208                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6209         else
6210                 dev_priv->modeset_restore_state = state;
6211         return ret;
6212 }
6213
6214 void intel_encoder_destroy(struct drm_encoder *encoder)
6215 {
6216         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6217
6218         drm_encoder_cleanup(encoder);
6219         kfree(intel_encoder);
6220 }
6221
6222 /* Cross check the actual hw state with our own modeset state tracking (and it's
6223  * internal consistency). */
6224 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6225                                          struct drm_connector_state *conn_state)
6226 {
6227         struct intel_connector *connector = to_intel_connector(conn_state->connector);
6228
6229         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6230                       connector->base.base.id,
6231                       connector->base.name);
6232
6233         if (connector->get_hw_state(connector)) {
6234                 struct intel_encoder *encoder = connector->encoder;
6235
6236                 I915_STATE_WARN(!crtc_state,
6237                          "connector enabled without attached crtc\n");
6238
6239                 if (!crtc_state)
6240                         return;
6241
6242                 I915_STATE_WARN(!crtc_state->active,
6243                       "connector is active, but attached crtc isn't\n");
6244
6245                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6246                         return;
6247
6248                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6249                         "atomic encoder doesn't match attached encoder\n");
6250
6251                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6252                         "attached encoder crtc differs from connector crtc\n");
6253         } else {
6254                 I915_STATE_WARN(crtc_state && crtc_state->active,
6255                         "attached crtc is active, but connector isn't\n");
6256                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6257                         "best encoder set without crtc!\n");
6258         }
6259 }
6260
6261 int intel_connector_init(struct intel_connector *connector)
6262 {
6263         struct intel_digital_connector_state *conn_state;
6264
6265         /*
6266          * Allocate enough memory to hold intel_digital_connector_state,
6267          * This might be a few bytes too many, but for connectors that don't
6268          * need it we'll free the state and allocate a smaller one on the first
6269          * succesful commit anyway.
6270          */
6271         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6272         if (!conn_state)
6273                 return -ENOMEM;
6274
6275         __drm_atomic_helper_connector_reset(&connector->base,
6276                                             &conn_state->base);
6277
6278         return 0;
6279 }
6280
6281 struct intel_connector *intel_connector_alloc(void)
6282 {
6283         struct intel_connector *connector;
6284
6285         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6286         if (!connector)
6287                 return NULL;
6288
6289         if (intel_connector_init(connector) < 0) {
6290                 kfree(connector);
6291                 return NULL;
6292         }
6293
6294         return connector;
6295 }
6296
6297 /*
6298  * Free the bits allocated by intel_connector_alloc.
6299  * This should only be used after intel_connector_alloc has returned
6300  * successfully, and before drm_connector_init returns successfully.
6301  * Otherwise the destroy callbacks for the connector and the state should
6302  * take care of proper cleanup/free
6303  */
6304 void intel_connector_free(struct intel_connector *connector)
6305 {
6306         kfree(to_intel_digital_connector_state(connector->base.state));
6307         kfree(connector);
6308 }
6309
6310 /* Simple connector->get_hw_state implementation for encoders that support only
6311  * one connector and no cloning and hence the encoder state determines the state
6312  * of the connector. */
6313 bool intel_connector_get_hw_state(struct intel_connector *connector)
6314 {
6315         enum pipe pipe = 0;
6316         struct intel_encoder *encoder = connector->encoder;
6317
6318         return encoder->get_hw_state(encoder, &pipe);
6319 }
6320
6321 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6322 {
6323         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6324                 return crtc_state->fdi_lanes;
6325
6326         return 0;
6327 }
6328
6329 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6330                                      struct intel_crtc_state *pipe_config)
6331 {
6332         struct drm_i915_private *dev_priv = to_i915(dev);
6333         struct drm_atomic_state *state = pipe_config->base.state;
6334         struct intel_crtc *other_crtc;
6335         struct intel_crtc_state *other_crtc_state;
6336
6337         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6338                       pipe_name(pipe), pipe_config->fdi_lanes);
6339         if (pipe_config->fdi_lanes > 4) {
6340                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6341                               pipe_name(pipe), pipe_config->fdi_lanes);
6342                 return -EINVAL;
6343         }
6344
6345         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6346                 if (pipe_config->fdi_lanes > 2) {
6347                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6348                                       pipe_config->fdi_lanes);
6349                         return -EINVAL;
6350                 } else {
6351                         return 0;
6352                 }
6353         }
6354
6355         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6356                 return 0;
6357
6358         /* Ivybridge 3 pipe is really complicated */
6359         switch (pipe) {
6360         case PIPE_A:
6361                 return 0;
6362         case PIPE_B:
6363                 if (pipe_config->fdi_lanes <= 2)
6364                         return 0;
6365
6366                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6367                 other_crtc_state =
6368                         intel_atomic_get_crtc_state(state, other_crtc);
6369                 if (IS_ERR(other_crtc_state))
6370                         return PTR_ERR(other_crtc_state);
6371
6372                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6373                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6374                                       pipe_name(pipe), pipe_config->fdi_lanes);
6375                         return -EINVAL;
6376                 }
6377                 return 0;
6378         case PIPE_C:
6379                 if (pipe_config->fdi_lanes > 2) {
6380                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6381                                       pipe_name(pipe), pipe_config->fdi_lanes);
6382                         return -EINVAL;
6383                 }
6384
6385                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6386                 other_crtc_state =
6387                         intel_atomic_get_crtc_state(state, other_crtc);
6388                 if (IS_ERR(other_crtc_state))
6389                         return PTR_ERR(other_crtc_state);
6390
6391                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6392                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6393                         return -EINVAL;
6394                 }
6395                 return 0;
6396         default:
6397                 BUG();
6398         }
6399 }
6400
6401 #define RETRY 1
6402 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6403                                        struct intel_crtc_state *pipe_config)
6404 {
6405         struct drm_device *dev = intel_crtc->base.dev;
6406         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6407         int lane, link_bw, fdi_dotclock, ret;
6408         bool needs_recompute = false;
6409
6410 retry:
6411         /* FDI is a binary signal running at ~2.7GHz, encoding
6412          * each output octet as 10 bits. The actual frequency
6413          * is stored as a divider into a 100MHz clock, and the
6414          * mode pixel clock is stored in units of 1KHz.
6415          * Hence the bw of each lane in terms of the mode signal
6416          * is:
6417          */
6418         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6419
6420         fdi_dotclock = adjusted_mode->crtc_clock;
6421
6422         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6423                                            pipe_config->pipe_bpp);
6424
6425         pipe_config->fdi_lanes = lane;
6426
6427         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6428                                link_bw, &pipe_config->fdi_m_n, false);
6429
6430         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6431         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6432                 pipe_config->pipe_bpp -= 2*3;
6433                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6434                               pipe_config->pipe_bpp);
6435                 needs_recompute = true;
6436                 pipe_config->bw_constrained = true;
6437
6438                 goto retry;
6439         }
6440
6441         if (needs_recompute)
6442                 return RETRY;
6443
6444         return ret;
6445 }
6446
6447 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6448 {
6449         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6450         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6451
6452         /* IPS only exists on ULT machines and is tied to pipe A. */
6453         if (!hsw_crtc_supports_ips(crtc))
6454                 return false;
6455
6456         if (!i915_modparams.enable_ips)
6457                 return false;
6458
6459         if (crtc_state->pipe_bpp > 24)
6460                 return false;
6461
6462         /*
6463          * We compare against max which means we must take
6464          * the increased cdclk requirement into account when
6465          * calculating the new cdclk.
6466          *
6467          * Should measure whether using a lower cdclk w/o IPS
6468          */
6469         if (IS_BROADWELL(dev_priv) &&
6470             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6471                 return false;
6472
6473         return true;
6474 }
6475
6476 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6477 {
6478         struct drm_i915_private *dev_priv =
6479                 to_i915(crtc_state->base.crtc->dev);
6480         struct intel_atomic_state *intel_state =
6481                 to_intel_atomic_state(crtc_state->base.state);
6482
6483         if (!hsw_crtc_state_ips_capable(crtc_state))
6484                 return false;
6485
6486         if (crtc_state->ips_force_disable)
6487                 return false;
6488
6489         /* IPS should be fine as long as at least one plane is enabled. */
6490         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6491                 return false;
6492
6493         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6494         if (IS_BROADWELL(dev_priv) &&
6495             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6496                 return false;
6497
6498         return true;
6499 }
6500
6501 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6502 {
6503         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6504
6505         /* GDG double wide on either pipe, otherwise pipe A only */
6506         return INTEL_GEN(dev_priv) < 4 &&
6507                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6508 }
6509
6510 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6511 {
6512         uint32_t pixel_rate;
6513
6514         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6515
6516         /*
6517          * We only use IF-ID interlacing. If we ever use
6518          * PF-ID we'll need to adjust the pixel_rate here.
6519          */
6520
6521         if (pipe_config->pch_pfit.enabled) {
6522                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6523                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6524
6525                 pipe_w = pipe_config->pipe_src_w;
6526                 pipe_h = pipe_config->pipe_src_h;
6527
6528                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6529                 pfit_h = pfit_size & 0xFFFF;
6530                 if (pipe_w < pfit_w)
6531                         pipe_w = pfit_w;
6532                 if (pipe_h < pfit_h)
6533                         pipe_h = pfit_h;
6534
6535                 if (WARN_ON(!pfit_w || !pfit_h))
6536                         return pixel_rate;
6537
6538                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6539                                      pfit_w * pfit_h);
6540         }
6541
6542         return pixel_rate;
6543 }
6544
6545 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6546 {
6547         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6548
6549         if (HAS_GMCH_DISPLAY(dev_priv))
6550                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6551                 crtc_state->pixel_rate =
6552                         crtc_state->base.adjusted_mode.crtc_clock;
6553         else
6554                 crtc_state->pixel_rate =
6555                         ilk_pipe_pixel_rate(crtc_state);
6556 }
6557
6558 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6559                                      struct intel_crtc_state *pipe_config)
6560 {
6561         struct drm_device *dev = crtc->base.dev;
6562         struct drm_i915_private *dev_priv = to_i915(dev);
6563         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6564         int clock_limit = dev_priv->max_dotclk_freq;
6565
6566         if (INTEL_GEN(dev_priv) < 4) {
6567                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6568
6569                 /*
6570                  * Enable double wide mode when the dot clock
6571                  * is > 90% of the (display) core speed.
6572                  */
6573                 if (intel_crtc_supports_double_wide(crtc) &&
6574                     adjusted_mode->crtc_clock > clock_limit) {
6575                         clock_limit = dev_priv->max_dotclk_freq;
6576                         pipe_config->double_wide = true;
6577                 }
6578         }
6579
6580         if (adjusted_mode->crtc_clock > clock_limit) {
6581                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6582                               adjusted_mode->crtc_clock, clock_limit,
6583                               yesno(pipe_config->double_wide));
6584                 return -EINVAL;
6585         }
6586
6587         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6588                 /*
6589                  * There is only one pipe CSC unit per pipe, and we need that
6590                  * for output conversion from RGB->YCBCR. So if CTM is already
6591                  * applied we can't support YCBCR420 output.
6592                  */
6593                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6594                 return -EINVAL;
6595         }
6596
6597         /*
6598          * Pipe horizontal size must be even in:
6599          * - DVO ganged mode
6600          * - LVDS dual channel mode
6601          * - Double wide pipe
6602          */
6603         if (pipe_config->pipe_src_w & 1) {
6604                 if (pipe_config->double_wide) {
6605                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6606                         return -EINVAL;
6607                 }
6608
6609                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6610                     intel_is_dual_link_lvds(dev)) {
6611                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6612                         return -EINVAL;
6613                 }
6614         }
6615
6616         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6617          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6618          */
6619         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6620                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6621                 return -EINVAL;
6622
6623         intel_crtc_compute_pixel_rate(pipe_config);
6624
6625         if (pipe_config->has_pch_encoder)
6626                 return ironlake_fdi_compute_config(crtc, pipe_config);
6627
6628         return 0;
6629 }
6630
6631 static void
6632 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6633 {
6634         while (*num > DATA_LINK_M_N_MASK ||
6635                *den > DATA_LINK_M_N_MASK) {
6636                 *num >>= 1;
6637                 *den >>= 1;
6638         }
6639 }
6640
6641 static void compute_m_n(unsigned int m, unsigned int n,
6642                         uint32_t *ret_m, uint32_t *ret_n,
6643                         bool reduce_m_n)
6644 {
6645         /*
6646          * Reduce M/N as much as possible without loss in precision. Several DP
6647          * dongles in particular seem to be fussy about too large *link* M/N
6648          * values. The passed in values are more likely to have the least
6649          * significant bits zero than M after rounding below, so do this first.
6650          */
6651         if (reduce_m_n) {
6652                 while ((m & 1) == 0 && (n & 1) == 0) {
6653                         m >>= 1;
6654                         n >>= 1;
6655                 }
6656         }
6657
6658         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6659         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6660         intel_reduce_m_n_ratio(ret_m, ret_n);
6661 }
6662
6663 void
6664 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6665                        int pixel_clock, int link_clock,
6666                        struct intel_link_m_n *m_n,
6667                        bool reduce_m_n)
6668 {
6669         m_n->tu = 64;
6670
6671         compute_m_n(bits_per_pixel * pixel_clock,
6672                     link_clock * nlanes * 8,
6673                     &m_n->gmch_m, &m_n->gmch_n,
6674                     reduce_m_n);
6675
6676         compute_m_n(pixel_clock, link_clock,
6677                     &m_n->link_m, &m_n->link_n,
6678                     reduce_m_n);
6679 }
6680
6681 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6682 {
6683         if (i915_modparams.panel_use_ssc >= 0)
6684                 return i915_modparams.panel_use_ssc != 0;
6685         return dev_priv->vbt.lvds_use_ssc
6686                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6687 }
6688
6689 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6690 {
6691         return (1 << dpll->n) << 16 | dpll->m2;
6692 }
6693
6694 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6695 {
6696         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6697 }
6698
6699 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6700                                      struct intel_crtc_state *crtc_state,
6701                                      struct dpll *reduced_clock)
6702 {
6703         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6704         u32 fp, fp2 = 0;
6705
6706         if (IS_PINEVIEW(dev_priv)) {
6707                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6708                 if (reduced_clock)
6709                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6710         } else {
6711                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6712                 if (reduced_clock)
6713                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6714         }
6715
6716         crtc_state->dpll_hw_state.fp0 = fp;
6717
6718         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6719             reduced_clock) {
6720                 crtc_state->dpll_hw_state.fp1 = fp2;
6721         } else {
6722                 crtc_state->dpll_hw_state.fp1 = fp;
6723         }
6724 }
6725
6726 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6727                 pipe)
6728 {
6729         u32 reg_val;
6730
6731         /*
6732          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6733          * and set it to a reasonable value instead.
6734          */
6735         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6736         reg_val &= 0xffffff00;
6737         reg_val |= 0x00000030;
6738         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6739
6740         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6741         reg_val &= 0x00ffffff;
6742         reg_val |= 0x8c000000;
6743         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6744
6745         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6746         reg_val &= 0xffffff00;
6747         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6748
6749         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6750         reg_val &= 0x00ffffff;
6751         reg_val |= 0xb0000000;
6752         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6753 }
6754
6755 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6756                                          struct intel_link_m_n *m_n)
6757 {
6758         struct drm_device *dev = crtc->base.dev;
6759         struct drm_i915_private *dev_priv = to_i915(dev);
6760         int pipe = crtc->pipe;
6761
6762         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6763         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6764         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6765         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6766 }
6767
6768 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6769                                          struct intel_link_m_n *m_n,
6770                                          struct intel_link_m_n *m2_n2)
6771 {
6772         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6773         int pipe = crtc->pipe;
6774         enum transcoder transcoder = crtc->config->cpu_transcoder;
6775
6776         if (INTEL_GEN(dev_priv) >= 5) {
6777                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6778                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6779                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6780                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6781                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6782                  * for gen < 8) and if DRRS is supported (to make sure the
6783                  * registers are not unnecessarily accessed).
6784                  */
6785                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6786                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6787                         I915_WRITE(PIPE_DATA_M2(transcoder),
6788                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6789                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6790                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6791                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6792                 }
6793         } else {
6794                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6795                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6796                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6797                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6798         }
6799 }
6800
6801 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6802 {
6803         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6804
6805         if (m_n == M1_N1) {
6806                 dp_m_n = &crtc->config->dp_m_n;
6807                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6808         } else if (m_n == M2_N2) {
6809
6810                 /*
6811                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6812                  * needs to be programmed into M1_N1.
6813                  */
6814                 dp_m_n = &crtc->config->dp_m2_n2;
6815         } else {
6816                 DRM_ERROR("Unsupported divider value\n");
6817                 return;
6818         }
6819
6820         if (crtc->config->has_pch_encoder)
6821                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6822         else
6823                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6824 }
6825
6826 static void vlv_compute_dpll(struct intel_crtc *crtc,
6827                              struct intel_crtc_state *pipe_config)
6828 {
6829         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6830                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6831         if (crtc->pipe != PIPE_A)
6832                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6833
6834         /* DPLL not used with DSI, but still need the rest set up */
6835         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6836                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6837                         DPLL_EXT_BUFFER_ENABLE_VLV;
6838
6839         pipe_config->dpll_hw_state.dpll_md =
6840                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6841 }
6842
6843 static void chv_compute_dpll(struct intel_crtc *crtc,
6844                              struct intel_crtc_state *pipe_config)
6845 {
6846         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6847                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6848         if (crtc->pipe != PIPE_A)
6849                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6850
6851         /* DPLL not used with DSI, but still need the rest set up */
6852         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6853                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6854
6855         pipe_config->dpll_hw_state.dpll_md =
6856                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6857 }
6858
6859 static void vlv_prepare_pll(struct intel_crtc *crtc,
6860                             const struct intel_crtc_state *pipe_config)
6861 {
6862         struct drm_device *dev = crtc->base.dev;
6863         struct drm_i915_private *dev_priv = to_i915(dev);
6864         enum pipe pipe = crtc->pipe;
6865         u32 mdiv;
6866         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6867         u32 coreclk, reg_val;
6868
6869         /* Enable Refclk */
6870         I915_WRITE(DPLL(pipe),
6871                    pipe_config->dpll_hw_state.dpll &
6872                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6873
6874         /* No need to actually set up the DPLL with DSI */
6875         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6876                 return;
6877
6878         mutex_lock(&dev_priv->sb_lock);
6879
6880         bestn = pipe_config->dpll.n;
6881         bestm1 = pipe_config->dpll.m1;
6882         bestm2 = pipe_config->dpll.m2;
6883         bestp1 = pipe_config->dpll.p1;
6884         bestp2 = pipe_config->dpll.p2;
6885
6886         /* See eDP HDMI DPIO driver vbios notes doc */
6887
6888         /* PLL B needs special handling */
6889         if (pipe == PIPE_B)
6890                 vlv_pllb_recal_opamp(dev_priv, pipe);
6891
6892         /* Set up Tx target for periodic Rcomp update */
6893         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6894
6895         /* Disable target IRef on PLL */
6896         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6897         reg_val &= 0x00ffffff;
6898         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6899
6900         /* Disable fast lock */
6901         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6902
6903         /* Set idtafcrecal before PLL is enabled */
6904         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6905         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6906         mdiv |= ((bestn << DPIO_N_SHIFT));
6907         mdiv |= (1 << DPIO_K_SHIFT);
6908
6909         /*
6910          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6911          * but we don't support that).
6912          * Note: don't use the DAC post divider as it seems unstable.
6913          */
6914         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6915         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6916
6917         mdiv |= DPIO_ENABLE_CALIBRATION;
6918         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6919
6920         /* Set HBR and RBR LPF coefficients */
6921         if (pipe_config->port_clock == 162000 ||
6922             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6923             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6924                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6925                                  0x009f0003);
6926         else
6927                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6928                                  0x00d0000f);
6929
6930         if (intel_crtc_has_dp_encoder(pipe_config)) {
6931                 /* Use SSC source */
6932                 if (pipe == PIPE_A)
6933                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6934                                          0x0df40000);
6935                 else
6936                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6937                                          0x0df70000);
6938         } else { /* HDMI or VGA */
6939                 /* Use bend source */
6940                 if (pipe == PIPE_A)
6941                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6942                                          0x0df70000);
6943                 else
6944                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6945                                          0x0df40000);
6946         }
6947
6948         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6949         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6950         if (intel_crtc_has_dp_encoder(crtc->config))
6951                 coreclk |= 0x01000000;
6952         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6953
6954         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6955         mutex_unlock(&dev_priv->sb_lock);
6956 }
6957
6958 static void chv_prepare_pll(struct intel_crtc *crtc,
6959                             const struct intel_crtc_state *pipe_config)
6960 {
6961         struct drm_device *dev = crtc->base.dev;
6962         struct drm_i915_private *dev_priv = to_i915(dev);
6963         enum pipe pipe = crtc->pipe;
6964         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6965         u32 loopfilter, tribuf_calcntr;
6966         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6967         u32 dpio_val;
6968         int vco;
6969
6970         /* Enable Refclk and SSC */
6971         I915_WRITE(DPLL(pipe),
6972                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6973
6974         /* No need to actually set up the DPLL with DSI */
6975         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6976                 return;
6977
6978         bestn = pipe_config->dpll.n;
6979         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6980         bestm1 = pipe_config->dpll.m1;
6981         bestm2 = pipe_config->dpll.m2 >> 22;
6982         bestp1 = pipe_config->dpll.p1;
6983         bestp2 = pipe_config->dpll.p2;
6984         vco = pipe_config->dpll.vco;
6985         dpio_val = 0;
6986         loopfilter = 0;
6987
6988         mutex_lock(&dev_priv->sb_lock);
6989
6990         /* p1 and p2 divider */
6991         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6992                         5 << DPIO_CHV_S1_DIV_SHIFT |
6993                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6994                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6995                         1 << DPIO_CHV_K_DIV_SHIFT);
6996
6997         /* Feedback post-divider - m2 */
6998         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6999
7000         /* Feedback refclk divider - n and m1 */
7001         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7002                         DPIO_CHV_M1_DIV_BY_2 |
7003                         1 << DPIO_CHV_N_DIV_SHIFT);
7004
7005         /* M2 fraction division */
7006         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7007
7008         /* M2 fraction division enable */
7009         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7010         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7011         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7012         if (bestm2_frac)
7013                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7014         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7015
7016         /* Program digital lock detect threshold */
7017         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7018         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7019                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7020         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7021         if (!bestm2_frac)
7022                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7023         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7024
7025         /* Loop filter */
7026         if (vco == 5400000) {
7027                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7028                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7029                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7030                 tribuf_calcntr = 0x9;
7031         } else if (vco <= 6200000) {
7032                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7033                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7034                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7035                 tribuf_calcntr = 0x9;
7036         } else if (vco <= 6480000) {
7037                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7038                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7039                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7040                 tribuf_calcntr = 0x8;
7041         } else {
7042                 /* Not supported. Apply the same limits as in the max case */
7043                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7044                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7045                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7046                 tribuf_calcntr = 0;
7047         }
7048         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7049
7050         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7051         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7052         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7053         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7054
7055         /* AFC Recal */
7056         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7057                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7058                         DPIO_AFC_RECAL);
7059
7060         mutex_unlock(&dev_priv->sb_lock);
7061 }
7062
7063 /**
7064  * vlv_force_pll_on - forcibly enable just the PLL
7065  * @dev_priv: i915 private structure
7066  * @pipe: pipe PLL to enable
7067  * @dpll: PLL configuration
7068  *
7069  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7070  * in cases where we need the PLL enabled even when @pipe is not going to
7071  * be enabled.
7072  */
7073 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7074                      const struct dpll *dpll)
7075 {
7076         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7077         struct intel_crtc_state *pipe_config;
7078
7079         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7080         if (!pipe_config)
7081                 return -ENOMEM;
7082
7083         pipe_config->base.crtc = &crtc->base;
7084         pipe_config->pixel_multiplier = 1;
7085         pipe_config->dpll = *dpll;
7086
7087         if (IS_CHERRYVIEW(dev_priv)) {
7088                 chv_compute_dpll(crtc, pipe_config);
7089                 chv_prepare_pll(crtc, pipe_config);
7090                 chv_enable_pll(crtc, pipe_config);
7091         } else {
7092                 vlv_compute_dpll(crtc, pipe_config);
7093                 vlv_prepare_pll(crtc, pipe_config);
7094                 vlv_enable_pll(crtc, pipe_config);
7095         }
7096
7097         kfree(pipe_config);
7098
7099         return 0;
7100 }
7101
7102 /**
7103  * vlv_force_pll_off - forcibly disable just the PLL
7104  * @dev_priv: i915 private structure
7105  * @pipe: pipe PLL to disable
7106  *
7107  * Disable the PLL for @pipe. To be used in cases where we need
7108  * the PLL enabled even when @pipe is not going to be enabled.
7109  */
7110 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7111 {
7112         if (IS_CHERRYVIEW(dev_priv))
7113                 chv_disable_pll(dev_priv, pipe);
7114         else
7115                 vlv_disable_pll(dev_priv, pipe);
7116 }
7117
7118 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7119                               struct intel_crtc_state *crtc_state,
7120                               struct dpll *reduced_clock)
7121 {
7122         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7123         u32 dpll;
7124         struct dpll *clock = &crtc_state->dpll;
7125
7126         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7127
7128         dpll = DPLL_VGA_MODE_DIS;
7129
7130         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7131                 dpll |= DPLLB_MODE_LVDS;
7132         else
7133                 dpll |= DPLLB_MODE_DAC_SERIAL;
7134
7135         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7136             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7137                 dpll |= (crtc_state->pixel_multiplier - 1)
7138                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7139         }
7140
7141         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7142             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7143                 dpll |= DPLL_SDVO_HIGH_SPEED;
7144
7145         if (intel_crtc_has_dp_encoder(crtc_state))
7146                 dpll |= DPLL_SDVO_HIGH_SPEED;
7147
7148         /* compute bitmask from p1 value */
7149         if (IS_PINEVIEW(dev_priv))
7150                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7151         else {
7152                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7153                 if (IS_G4X(dev_priv) && reduced_clock)
7154                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7155         }
7156         switch (clock->p2) {
7157         case 5:
7158                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7159                 break;
7160         case 7:
7161                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7162                 break;
7163         case 10:
7164                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7165                 break;
7166         case 14:
7167                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7168                 break;
7169         }
7170         if (INTEL_GEN(dev_priv) >= 4)
7171                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7172
7173         if (crtc_state->sdvo_tv_clock)
7174                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7175         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7176                  intel_panel_use_ssc(dev_priv))
7177                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7178         else
7179                 dpll |= PLL_REF_INPUT_DREFCLK;
7180
7181         dpll |= DPLL_VCO_ENABLE;
7182         crtc_state->dpll_hw_state.dpll = dpll;
7183
7184         if (INTEL_GEN(dev_priv) >= 4) {
7185                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7186                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7187                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7188         }
7189 }
7190
7191 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7192                               struct intel_crtc_state *crtc_state,
7193                               struct dpll *reduced_clock)
7194 {
7195         struct drm_device *dev = crtc->base.dev;
7196         struct drm_i915_private *dev_priv = to_i915(dev);
7197         u32 dpll;
7198         struct dpll *clock = &crtc_state->dpll;
7199
7200         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7201
7202         dpll = DPLL_VGA_MODE_DIS;
7203
7204         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7205                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7206         } else {
7207                 if (clock->p1 == 2)
7208                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7209                 else
7210                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7211                 if (clock->p2 == 4)
7212                         dpll |= PLL_P2_DIVIDE_BY_4;
7213         }
7214
7215         if (!IS_I830(dev_priv) &&
7216             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7217                 dpll |= DPLL_DVO_2X_MODE;
7218
7219         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7220             intel_panel_use_ssc(dev_priv))
7221                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7222         else
7223                 dpll |= PLL_REF_INPUT_DREFCLK;
7224
7225         dpll |= DPLL_VCO_ENABLE;
7226         crtc_state->dpll_hw_state.dpll = dpll;
7227 }
7228
7229 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7230 {
7231         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7232         enum pipe pipe = intel_crtc->pipe;
7233         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7234         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7235         uint32_t crtc_vtotal, crtc_vblank_end;
7236         int vsyncshift = 0;
7237
7238         /* We need to be careful not to changed the adjusted mode, for otherwise
7239          * the hw state checker will get angry at the mismatch. */
7240         crtc_vtotal = adjusted_mode->crtc_vtotal;
7241         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7242
7243         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7244                 /* the chip adds 2 halflines automatically */
7245                 crtc_vtotal -= 1;
7246                 crtc_vblank_end -= 1;
7247
7248                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7249                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7250                 else
7251                         vsyncshift = adjusted_mode->crtc_hsync_start -
7252                                 adjusted_mode->crtc_htotal / 2;
7253                 if (vsyncshift < 0)
7254                         vsyncshift += adjusted_mode->crtc_htotal;
7255         }
7256
7257         if (INTEL_GEN(dev_priv) > 3)
7258                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7259
7260         I915_WRITE(HTOTAL(cpu_transcoder),
7261                    (adjusted_mode->crtc_hdisplay - 1) |
7262                    ((adjusted_mode->crtc_htotal - 1) << 16));
7263         I915_WRITE(HBLANK(cpu_transcoder),
7264                    (adjusted_mode->crtc_hblank_start - 1) |
7265                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7266         I915_WRITE(HSYNC(cpu_transcoder),
7267                    (adjusted_mode->crtc_hsync_start - 1) |
7268                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7269
7270         I915_WRITE(VTOTAL(cpu_transcoder),
7271                    (adjusted_mode->crtc_vdisplay - 1) |
7272                    ((crtc_vtotal - 1) << 16));
7273         I915_WRITE(VBLANK(cpu_transcoder),
7274                    (adjusted_mode->crtc_vblank_start - 1) |
7275                    ((crtc_vblank_end - 1) << 16));
7276         I915_WRITE(VSYNC(cpu_transcoder),
7277                    (adjusted_mode->crtc_vsync_start - 1) |
7278                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7279
7280         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7281          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7282          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7283          * bits. */
7284         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7285             (pipe == PIPE_B || pipe == PIPE_C))
7286                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7287
7288 }
7289
7290 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7291 {
7292         struct drm_device *dev = intel_crtc->base.dev;
7293         struct drm_i915_private *dev_priv = to_i915(dev);
7294         enum pipe pipe = intel_crtc->pipe;
7295
7296         /* pipesrc controls the size that is scaled from, which should
7297          * always be the user's requested size.
7298          */
7299         I915_WRITE(PIPESRC(pipe),
7300                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7301                    (intel_crtc->config->pipe_src_h - 1));
7302 }
7303
7304 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7305                                    struct intel_crtc_state *pipe_config)
7306 {
7307         struct drm_device *dev = crtc->base.dev;
7308         struct drm_i915_private *dev_priv = to_i915(dev);
7309         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7310         uint32_t tmp;
7311
7312         tmp = I915_READ(HTOTAL(cpu_transcoder));
7313         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7314         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7315         tmp = I915_READ(HBLANK(cpu_transcoder));
7316         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7317         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7318         tmp = I915_READ(HSYNC(cpu_transcoder));
7319         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7320         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7321
7322         tmp = I915_READ(VTOTAL(cpu_transcoder));
7323         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7324         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7325         tmp = I915_READ(VBLANK(cpu_transcoder));
7326         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7327         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7328         tmp = I915_READ(VSYNC(cpu_transcoder));
7329         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7330         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7331
7332         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7333                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7334                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7335                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7336         }
7337 }
7338
7339 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7340                                     struct intel_crtc_state *pipe_config)
7341 {
7342         struct drm_device *dev = crtc->base.dev;
7343         struct drm_i915_private *dev_priv = to_i915(dev);
7344         u32 tmp;
7345
7346         tmp = I915_READ(PIPESRC(crtc->pipe));
7347         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7348         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7349
7350         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7351         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7352 }
7353
7354 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7355                                  struct intel_crtc_state *pipe_config)
7356 {
7357         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7358         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7359         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7360         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7361
7362         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7363         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7364         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7365         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7366
7367         mode->flags = pipe_config->base.adjusted_mode.flags;
7368         mode->type = DRM_MODE_TYPE_DRIVER;
7369
7370         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7371
7372         mode->hsync = drm_mode_hsync(mode);
7373         mode->vrefresh = drm_mode_vrefresh(mode);
7374         drm_mode_set_name(mode);
7375 }
7376
7377 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7378 {
7379         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7380         uint32_t pipeconf;
7381
7382         pipeconf = 0;
7383
7384         /* we keep both pipes enabled on 830 */
7385         if (IS_I830(dev_priv))
7386                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7387
7388         if (intel_crtc->config->double_wide)
7389                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7390
7391         /* only g4x and later have fancy bpc/dither controls */
7392         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7393             IS_CHERRYVIEW(dev_priv)) {
7394                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7395                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7396                         pipeconf |= PIPECONF_DITHER_EN |
7397                                     PIPECONF_DITHER_TYPE_SP;
7398
7399                 switch (intel_crtc->config->pipe_bpp) {
7400                 case 18:
7401                         pipeconf |= PIPECONF_6BPC;
7402                         break;
7403                 case 24:
7404                         pipeconf |= PIPECONF_8BPC;
7405                         break;
7406                 case 30:
7407                         pipeconf |= PIPECONF_10BPC;
7408                         break;
7409                 default:
7410                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7411                         BUG();
7412                 }
7413         }
7414
7415         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7416                 if (INTEL_GEN(dev_priv) < 4 ||
7417                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7418                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7419                 else
7420                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7421         } else
7422                 pipeconf |= PIPECONF_PROGRESSIVE;
7423
7424         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7425              intel_crtc->config->limited_color_range)
7426                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7427
7428         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7429         POSTING_READ(PIPECONF(intel_crtc->pipe));
7430 }
7431
7432 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7433                                    struct intel_crtc_state *crtc_state)
7434 {
7435         struct drm_device *dev = crtc->base.dev;
7436         struct drm_i915_private *dev_priv = to_i915(dev);
7437         const struct intel_limit *limit;
7438         int refclk = 48000;
7439
7440         memset(&crtc_state->dpll_hw_state, 0,
7441                sizeof(crtc_state->dpll_hw_state));
7442
7443         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7444                 if (intel_panel_use_ssc(dev_priv)) {
7445                         refclk = dev_priv->vbt.lvds_ssc_freq;
7446                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7447                 }
7448
7449                 limit = &intel_limits_i8xx_lvds;
7450         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7451                 limit = &intel_limits_i8xx_dvo;
7452         } else {
7453                 limit = &intel_limits_i8xx_dac;
7454         }
7455
7456         if (!crtc_state->clock_set &&
7457             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7458                                  refclk, NULL, &crtc_state->dpll)) {
7459                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7460                 return -EINVAL;
7461         }
7462
7463         i8xx_compute_dpll(crtc, crtc_state, NULL);
7464
7465         return 0;
7466 }
7467
7468 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7469                                   struct intel_crtc_state *crtc_state)
7470 {
7471         struct drm_device *dev = crtc->base.dev;
7472         struct drm_i915_private *dev_priv = to_i915(dev);
7473         const struct intel_limit *limit;
7474         int refclk = 96000;
7475
7476         memset(&crtc_state->dpll_hw_state, 0,
7477                sizeof(crtc_state->dpll_hw_state));
7478
7479         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7480                 if (intel_panel_use_ssc(dev_priv)) {
7481                         refclk = dev_priv->vbt.lvds_ssc_freq;
7482                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7483                 }
7484
7485                 if (intel_is_dual_link_lvds(dev))
7486                         limit = &intel_limits_g4x_dual_channel_lvds;
7487                 else
7488                         limit = &intel_limits_g4x_single_channel_lvds;
7489         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7490                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7491                 limit = &intel_limits_g4x_hdmi;
7492         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7493                 limit = &intel_limits_g4x_sdvo;
7494         } else {
7495                 /* The option is for other outputs */
7496                 limit = &intel_limits_i9xx_sdvo;
7497         }
7498
7499         if (!crtc_state->clock_set &&
7500             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7501                                 refclk, NULL, &crtc_state->dpll)) {
7502                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7503                 return -EINVAL;
7504         }
7505
7506         i9xx_compute_dpll(crtc, crtc_state, NULL);
7507
7508         return 0;
7509 }
7510
7511 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7512                                   struct intel_crtc_state *crtc_state)
7513 {
7514         struct drm_device *dev = crtc->base.dev;
7515         struct drm_i915_private *dev_priv = to_i915(dev);
7516         const struct intel_limit *limit;
7517         int refclk = 96000;
7518
7519         memset(&crtc_state->dpll_hw_state, 0,
7520                sizeof(crtc_state->dpll_hw_state));
7521
7522         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7523                 if (intel_panel_use_ssc(dev_priv)) {
7524                         refclk = dev_priv->vbt.lvds_ssc_freq;
7525                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7526                 }
7527
7528                 limit = &intel_limits_pineview_lvds;
7529         } else {
7530                 limit = &intel_limits_pineview_sdvo;
7531         }
7532
7533         if (!crtc_state->clock_set &&
7534             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7535                                 refclk, NULL, &crtc_state->dpll)) {
7536                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7537                 return -EINVAL;
7538         }
7539
7540         i9xx_compute_dpll(crtc, crtc_state, NULL);
7541
7542         return 0;
7543 }
7544
7545 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7546                                    struct intel_crtc_state *crtc_state)
7547 {
7548         struct drm_device *dev = crtc->base.dev;
7549         struct drm_i915_private *dev_priv = to_i915(dev);
7550         const struct intel_limit *limit;
7551         int refclk = 96000;
7552
7553         memset(&crtc_state->dpll_hw_state, 0,
7554                sizeof(crtc_state->dpll_hw_state));
7555
7556         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7557                 if (intel_panel_use_ssc(dev_priv)) {
7558                         refclk = dev_priv->vbt.lvds_ssc_freq;
7559                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7560                 }
7561
7562                 limit = &intel_limits_i9xx_lvds;
7563         } else {
7564                 limit = &intel_limits_i9xx_sdvo;
7565         }
7566
7567         if (!crtc_state->clock_set &&
7568             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7569                                  refclk, NULL, &crtc_state->dpll)) {
7570                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7571                 return -EINVAL;
7572         }
7573
7574         i9xx_compute_dpll(crtc, crtc_state, NULL);
7575
7576         return 0;
7577 }
7578
7579 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7580                                   struct intel_crtc_state *crtc_state)
7581 {
7582         int refclk = 100000;
7583         const struct intel_limit *limit = &intel_limits_chv;
7584
7585         memset(&crtc_state->dpll_hw_state, 0,
7586                sizeof(crtc_state->dpll_hw_state));
7587
7588         if (!crtc_state->clock_set &&
7589             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7590                                 refclk, NULL, &crtc_state->dpll)) {
7591                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7592                 return -EINVAL;
7593         }
7594
7595         chv_compute_dpll(crtc, crtc_state);
7596
7597         return 0;
7598 }
7599
7600 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7601                                   struct intel_crtc_state *crtc_state)
7602 {
7603         int refclk = 100000;
7604         const struct intel_limit *limit = &intel_limits_vlv;
7605
7606         memset(&crtc_state->dpll_hw_state, 0,
7607                sizeof(crtc_state->dpll_hw_state));
7608
7609         if (!crtc_state->clock_set &&
7610             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7611                                 refclk, NULL, &crtc_state->dpll)) {
7612                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7613                 return -EINVAL;
7614         }
7615
7616         vlv_compute_dpll(crtc, crtc_state);
7617
7618         return 0;
7619 }
7620
7621 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7622                                  struct intel_crtc_state *pipe_config)
7623 {
7624         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7625         uint32_t tmp;
7626
7627         if (INTEL_GEN(dev_priv) <= 3 &&
7628             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7629                 return;
7630
7631         tmp = I915_READ(PFIT_CONTROL);
7632         if (!(tmp & PFIT_ENABLE))
7633                 return;
7634
7635         /* Check whether the pfit is attached to our pipe. */
7636         if (INTEL_GEN(dev_priv) < 4) {
7637                 if (crtc->pipe != PIPE_B)
7638                         return;
7639         } else {
7640                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7641                         return;
7642         }
7643
7644         pipe_config->gmch_pfit.control = tmp;
7645         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7646 }
7647
7648 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7649                                struct intel_crtc_state *pipe_config)
7650 {
7651         struct drm_device *dev = crtc->base.dev;
7652         struct drm_i915_private *dev_priv = to_i915(dev);
7653         int pipe = pipe_config->cpu_transcoder;
7654         struct dpll clock;
7655         u32 mdiv;
7656         int refclk = 100000;
7657
7658         /* In case of DSI, DPLL will not be used */
7659         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7660                 return;
7661
7662         mutex_lock(&dev_priv->sb_lock);
7663         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7664         mutex_unlock(&dev_priv->sb_lock);
7665
7666         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7667         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7668         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7669         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7670         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7671
7672         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7673 }
7674
7675 static void
7676 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7677                               struct intel_initial_plane_config *plane_config)
7678 {
7679         struct drm_device *dev = crtc->base.dev;
7680         struct drm_i915_private *dev_priv = to_i915(dev);
7681         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7682         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7683         enum pipe pipe = crtc->pipe;
7684         u32 val, base, offset;
7685         int fourcc, pixel_format;
7686         unsigned int aligned_height;
7687         struct drm_framebuffer *fb;
7688         struct intel_framebuffer *intel_fb;
7689
7690         if (!plane->get_hw_state(plane))
7691                 return;
7692
7693         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7694         if (!intel_fb) {
7695                 DRM_DEBUG_KMS("failed to alloc fb\n");
7696                 return;
7697         }
7698
7699         fb = &intel_fb->base;
7700
7701         fb->dev = dev;
7702
7703         val = I915_READ(DSPCNTR(i9xx_plane));
7704
7705         if (INTEL_GEN(dev_priv) >= 4) {
7706                 if (val & DISPPLANE_TILED) {
7707                         plane_config->tiling = I915_TILING_X;
7708                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7709                 }
7710         }
7711
7712         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7713         fourcc = i9xx_format_to_fourcc(pixel_format);
7714         fb->format = drm_format_info(fourcc);
7715
7716         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7717                 offset = I915_READ(DSPOFFSET(i9xx_plane));
7718                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7719         } else if (INTEL_GEN(dev_priv) >= 4) {
7720                 if (plane_config->tiling)
7721                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
7722                 else
7723                         offset = I915_READ(DSPLINOFF(i9xx_plane));
7724                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7725         } else {
7726                 base = I915_READ(DSPADDR(i9xx_plane));
7727         }
7728         plane_config->base = base;
7729
7730         val = I915_READ(PIPESRC(pipe));
7731         fb->width = ((val >> 16) & 0xfff) + 1;
7732         fb->height = ((val >> 0) & 0xfff) + 1;
7733
7734         val = I915_READ(DSPSTRIDE(i9xx_plane));
7735         fb->pitches[0] = val & 0xffffffc0;
7736
7737         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7738
7739         plane_config->size = fb->pitches[0] * aligned_height;
7740
7741         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7742                       crtc->base.name, plane->base.name, fb->width, fb->height,
7743                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7744                       plane_config->size);
7745
7746         plane_config->fb = intel_fb;
7747 }
7748
7749 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7750                                struct intel_crtc_state *pipe_config)
7751 {
7752         struct drm_device *dev = crtc->base.dev;
7753         struct drm_i915_private *dev_priv = to_i915(dev);
7754         int pipe = pipe_config->cpu_transcoder;
7755         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7756         struct dpll clock;
7757         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7758         int refclk = 100000;
7759
7760         /* In case of DSI, DPLL will not be used */
7761         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7762                 return;
7763
7764         mutex_lock(&dev_priv->sb_lock);
7765         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7766         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7767         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7768         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7769         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7770         mutex_unlock(&dev_priv->sb_lock);
7771
7772         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7773         clock.m2 = (pll_dw0 & 0xff) << 22;
7774         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7775                 clock.m2 |= pll_dw2 & 0x3fffff;
7776         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7777         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7778         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7779
7780         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7781 }
7782
7783 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7784                                  struct intel_crtc_state *pipe_config)
7785 {
7786         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7787         enum intel_display_power_domain power_domain;
7788         uint32_t tmp;
7789         bool ret;
7790
7791         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7792         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7793                 return false;
7794
7795         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7796         pipe_config->shared_dpll = NULL;
7797
7798         ret = false;
7799
7800         tmp = I915_READ(PIPECONF(crtc->pipe));
7801         if (!(tmp & PIPECONF_ENABLE))
7802                 goto out;
7803
7804         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7805             IS_CHERRYVIEW(dev_priv)) {
7806                 switch (tmp & PIPECONF_BPC_MASK) {
7807                 case PIPECONF_6BPC:
7808                         pipe_config->pipe_bpp = 18;
7809                         break;
7810                 case PIPECONF_8BPC:
7811                         pipe_config->pipe_bpp = 24;
7812                         break;
7813                 case PIPECONF_10BPC:
7814                         pipe_config->pipe_bpp = 30;
7815                         break;
7816                 default:
7817                         break;
7818                 }
7819         }
7820
7821         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7822             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7823                 pipe_config->limited_color_range = true;
7824
7825         if (INTEL_GEN(dev_priv) < 4)
7826                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7827
7828         intel_get_pipe_timings(crtc, pipe_config);
7829         intel_get_pipe_src_size(crtc, pipe_config);
7830
7831         i9xx_get_pfit_config(crtc, pipe_config);
7832
7833         if (INTEL_GEN(dev_priv) >= 4) {
7834                 /* No way to read it out on pipes B and C */
7835                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7836                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7837                 else
7838                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7839                 pipe_config->pixel_multiplier =
7840                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7841                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7842                 pipe_config->dpll_hw_state.dpll_md = tmp;
7843         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7844                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7845                 tmp = I915_READ(DPLL(crtc->pipe));
7846                 pipe_config->pixel_multiplier =
7847                         ((tmp & SDVO_MULTIPLIER_MASK)
7848                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7849         } else {
7850                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7851                  * port and will be fixed up in the encoder->get_config
7852                  * function. */
7853                 pipe_config->pixel_multiplier = 1;
7854         }
7855         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7856         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7857                 /*
7858                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7859                  * on 830. Filter it out here so that we don't
7860                  * report errors due to that.
7861                  */
7862                 if (IS_I830(dev_priv))
7863                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7864
7865                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7866                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7867         } else {
7868                 /* Mask out read-only status bits. */
7869                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7870                                                      DPLL_PORTC_READY_MASK |
7871                                                      DPLL_PORTB_READY_MASK);
7872         }
7873
7874         if (IS_CHERRYVIEW(dev_priv))
7875                 chv_crtc_clock_get(crtc, pipe_config);
7876         else if (IS_VALLEYVIEW(dev_priv))
7877                 vlv_crtc_clock_get(crtc, pipe_config);
7878         else
7879                 i9xx_crtc_clock_get(crtc, pipe_config);
7880
7881         /*
7882          * Normally the dotclock is filled in by the encoder .get_config()
7883          * but in case the pipe is enabled w/o any ports we need a sane
7884          * default.
7885          */
7886         pipe_config->base.adjusted_mode.crtc_clock =
7887                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7888
7889         ret = true;
7890
7891 out:
7892         intel_display_power_put(dev_priv, power_domain);
7893
7894         return ret;
7895 }
7896
7897 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7898 {
7899         struct intel_encoder *encoder;
7900         int i;
7901         u32 val, final;
7902         bool has_lvds = false;
7903         bool has_cpu_edp = false;
7904         bool has_panel = false;
7905         bool has_ck505 = false;
7906         bool can_ssc = false;
7907         bool using_ssc_source = false;
7908
7909         /* We need to take the global config into account */
7910         for_each_intel_encoder(&dev_priv->drm, encoder) {
7911                 switch (encoder->type) {
7912                 case INTEL_OUTPUT_LVDS:
7913                         has_panel = true;
7914                         has_lvds = true;
7915                         break;
7916                 case INTEL_OUTPUT_EDP:
7917                         has_panel = true;
7918                         if (encoder->port == PORT_A)
7919                                 has_cpu_edp = true;
7920                         break;
7921                 default:
7922                         break;
7923                 }
7924         }
7925
7926         if (HAS_PCH_IBX(dev_priv)) {
7927                 has_ck505 = dev_priv->vbt.display_clock_mode;
7928                 can_ssc = has_ck505;
7929         } else {
7930                 has_ck505 = false;
7931                 can_ssc = true;
7932         }
7933
7934         /* Check if any DPLLs are using the SSC source */
7935         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7936                 u32 temp = I915_READ(PCH_DPLL(i));
7937
7938                 if (!(temp & DPLL_VCO_ENABLE))
7939                         continue;
7940
7941                 if ((temp & PLL_REF_INPUT_MASK) ==
7942                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7943                         using_ssc_source = true;
7944                         break;
7945                 }
7946         }
7947
7948         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7949                       has_panel, has_lvds, has_ck505, using_ssc_source);
7950
7951         /* Ironlake: try to setup display ref clock before DPLL
7952          * enabling. This is only under driver's control after
7953          * PCH B stepping, previous chipset stepping should be
7954          * ignoring this setting.
7955          */
7956         val = I915_READ(PCH_DREF_CONTROL);
7957
7958         /* As we must carefully and slowly disable/enable each source in turn,
7959          * compute the final state we want first and check if we need to
7960          * make any changes at all.
7961          */
7962         final = val;
7963         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7964         if (has_ck505)
7965                 final |= DREF_NONSPREAD_CK505_ENABLE;
7966         else
7967                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7968
7969         final &= ~DREF_SSC_SOURCE_MASK;
7970         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7971         final &= ~DREF_SSC1_ENABLE;
7972
7973         if (has_panel) {
7974                 final |= DREF_SSC_SOURCE_ENABLE;
7975
7976                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7977                         final |= DREF_SSC1_ENABLE;
7978
7979                 if (has_cpu_edp) {
7980                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7981                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7982                         else
7983                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7984                 } else
7985                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7986         } else if (using_ssc_source) {
7987                 final |= DREF_SSC_SOURCE_ENABLE;
7988                 final |= DREF_SSC1_ENABLE;
7989         }
7990
7991         if (final == val)
7992                 return;
7993
7994         /* Always enable nonspread source */
7995         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7996
7997         if (has_ck505)
7998                 val |= DREF_NONSPREAD_CK505_ENABLE;
7999         else
8000                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8001
8002         if (has_panel) {
8003                 val &= ~DREF_SSC_SOURCE_MASK;
8004                 val |= DREF_SSC_SOURCE_ENABLE;
8005
8006                 /* SSC must be turned on before enabling the CPU output  */
8007                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8008                         DRM_DEBUG_KMS("Using SSC on panel\n");
8009                         val |= DREF_SSC1_ENABLE;
8010                 } else
8011                         val &= ~DREF_SSC1_ENABLE;
8012
8013                 /* Get SSC going before enabling the outputs */
8014                 I915_WRITE(PCH_DREF_CONTROL, val);
8015                 POSTING_READ(PCH_DREF_CONTROL);
8016                 udelay(200);
8017
8018                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8019
8020                 /* Enable CPU source on CPU attached eDP */
8021                 if (has_cpu_edp) {
8022                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8023                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8024                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8025                         } else
8026                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8027                 } else
8028                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8029
8030                 I915_WRITE(PCH_DREF_CONTROL, val);
8031                 POSTING_READ(PCH_DREF_CONTROL);
8032                 udelay(200);
8033         } else {
8034                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8035
8036                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8037
8038                 /* Turn off CPU output */
8039                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8040
8041                 I915_WRITE(PCH_DREF_CONTROL, val);
8042                 POSTING_READ(PCH_DREF_CONTROL);
8043                 udelay(200);
8044
8045                 if (!using_ssc_source) {
8046                         DRM_DEBUG_KMS("Disabling SSC source\n");
8047
8048                         /* Turn off the SSC source */
8049                         val &= ~DREF_SSC_SOURCE_MASK;
8050                         val |= DREF_SSC_SOURCE_DISABLE;
8051
8052                         /* Turn off SSC1 */
8053                         val &= ~DREF_SSC1_ENABLE;
8054
8055                         I915_WRITE(PCH_DREF_CONTROL, val);
8056                         POSTING_READ(PCH_DREF_CONTROL);
8057                         udelay(200);
8058                 }
8059         }
8060
8061         BUG_ON(val != final);
8062 }
8063
8064 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8065 {
8066         uint32_t tmp;
8067
8068         tmp = I915_READ(SOUTH_CHICKEN2);
8069         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8070         I915_WRITE(SOUTH_CHICKEN2, tmp);
8071
8072         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8073                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8074                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8075
8076         tmp = I915_READ(SOUTH_CHICKEN2);
8077         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8078         I915_WRITE(SOUTH_CHICKEN2, tmp);
8079
8080         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8081                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8082                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8083 }
8084
8085 /* WaMPhyProgramming:hsw */
8086 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8087 {
8088         uint32_t tmp;
8089
8090         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8091         tmp &= ~(0xFF << 24);
8092         tmp |= (0x12 << 24);
8093         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8094
8095         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8096         tmp |= (1 << 11);
8097         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8098
8099         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8100         tmp |= (1 << 11);
8101         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8102
8103         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8104         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8105         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8106
8107         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8108         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8109         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8110
8111         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8112         tmp &= ~(7 << 13);
8113         tmp |= (5 << 13);
8114         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8115
8116         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8117         tmp &= ~(7 << 13);
8118         tmp |= (5 << 13);
8119         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8120
8121         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8122         tmp &= ~0xFF;
8123         tmp |= 0x1C;
8124         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8125
8126         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8127         tmp &= ~0xFF;
8128         tmp |= 0x1C;
8129         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8130
8131         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8132         tmp &= ~(0xFF << 16);
8133         tmp |= (0x1C << 16);
8134         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8135
8136         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8137         tmp &= ~(0xFF << 16);
8138         tmp |= (0x1C << 16);
8139         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8140
8141         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8142         tmp |= (1 << 27);
8143         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8144
8145         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8146         tmp |= (1 << 27);
8147         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8148
8149         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8150         tmp &= ~(0xF << 28);
8151         tmp |= (4 << 28);
8152         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8153
8154         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8155         tmp &= ~(0xF << 28);
8156         tmp |= (4 << 28);
8157         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8158 }
8159
8160 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8161  * Programming" based on the parameters passed:
8162  * - Sequence to enable CLKOUT_DP
8163  * - Sequence to enable CLKOUT_DP without spread
8164  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8165  */
8166 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8167                                  bool with_spread, bool with_fdi)
8168 {
8169         uint32_t reg, tmp;
8170
8171         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8172                 with_spread = true;
8173         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8174             with_fdi, "LP PCH doesn't have FDI\n"))
8175                 with_fdi = false;
8176
8177         mutex_lock(&dev_priv->sb_lock);
8178
8179         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8180         tmp &= ~SBI_SSCCTL_DISABLE;
8181         tmp |= SBI_SSCCTL_PATHALT;
8182         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8183
8184         udelay(24);
8185
8186         if (with_spread) {
8187                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8188                 tmp &= ~SBI_SSCCTL_PATHALT;
8189                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8190
8191                 if (with_fdi) {
8192                         lpt_reset_fdi_mphy(dev_priv);
8193                         lpt_program_fdi_mphy(dev_priv);
8194                 }
8195         }
8196
8197         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8198         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8199         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8200         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8201
8202         mutex_unlock(&dev_priv->sb_lock);
8203 }
8204
8205 /* Sequence to disable CLKOUT_DP */
8206 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8207 {
8208         uint32_t reg, tmp;
8209
8210         mutex_lock(&dev_priv->sb_lock);
8211
8212         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8213         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8214         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8215         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8216
8217         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8218         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8219                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8220                         tmp |= SBI_SSCCTL_PATHALT;
8221                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8222                         udelay(32);
8223                 }
8224                 tmp |= SBI_SSCCTL_DISABLE;
8225                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8226         }
8227
8228         mutex_unlock(&dev_priv->sb_lock);
8229 }
8230
8231 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8232
8233 static const uint16_t sscdivintphase[] = {
8234         [BEND_IDX( 50)] = 0x3B23,
8235         [BEND_IDX( 45)] = 0x3B23,
8236         [BEND_IDX( 40)] = 0x3C23,
8237         [BEND_IDX( 35)] = 0x3C23,
8238         [BEND_IDX( 30)] = 0x3D23,
8239         [BEND_IDX( 25)] = 0x3D23,
8240         [BEND_IDX( 20)] = 0x3E23,
8241         [BEND_IDX( 15)] = 0x3E23,
8242         [BEND_IDX( 10)] = 0x3F23,
8243         [BEND_IDX(  5)] = 0x3F23,
8244         [BEND_IDX(  0)] = 0x0025,
8245         [BEND_IDX( -5)] = 0x0025,
8246         [BEND_IDX(-10)] = 0x0125,
8247         [BEND_IDX(-15)] = 0x0125,
8248         [BEND_IDX(-20)] = 0x0225,
8249         [BEND_IDX(-25)] = 0x0225,
8250         [BEND_IDX(-30)] = 0x0325,
8251         [BEND_IDX(-35)] = 0x0325,
8252         [BEND_IDX(-40)] = 0x0425,
8253         [BEND_IDX(-45)] = 0x0425,
8254         [BEND_IDX(-50)] = 0x0525,
8255 };
8256
8257 /*
8258  * Bend CLKOUT_DP
8259  * steps -50 to 50 inclusive, in steps of 5
8260  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8261  * change in clock period = -(steps / 10) * 5.787 ps
8262  */
8263 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8264 {
8265         uint32_t tmp;
8266         int idx = BEND_IDX(steps);
8267
8268         if (WARN_ON(steps % 5 != 0))
8269                 return;
8270
8271         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8272                 return;
8273
8274         mutex_lock(&dev_priv->sb_lock);
8275
8276         if (steps % 10 != 0)
8277                 tmp = 0xAAAAAAAB;
8278         else
8279                 tmp = 0x00000000;
8280         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8281
8282         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8283         tmp &= 0xffff0000;
8284         tmp |= sscdivintphase[idx];
8285         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8286
8287         mutex_unlock(&dev_priv->sb_lock);
8288 }
8289
8290 #undef BEND_IDX
8291
8292 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8293 {
8294         struct intel_encoder *encoder;
8295         bool has_vga = false;
8296
8297         for_each_intel_encoder(&dev_priv->drm, encoder) {
8298                 switch (encoder->type) {
8299                 case INTEL_OUTPUT_ANALOG:
8300                         has_vga = true;
8301                         break;
8302                 default:
8303                         break;
8304                 }
8305         }
8306
8307         if (has_vga) {
8308                 lpt_bend_clkout_dp(dev_priv, 0);
8309                 lpt_enable_clkout_dp(dev_priv, true, true);
8310         } else {
8311                 lpt_disable_clkout_dp(dev_priv);
8312         }
8313 }
8314
8315 /*
8316  * Initialize reference clocks when the driver loads
8317  */
8318 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8319 {
8320         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8321                 ironlake_init_pch_refclk(dev_priv);
8322         else if (HAS_PCH_LPT(dev_priv))
8323                 lpt_init_pch_refclk(dev_priv);
8324 }
8325
8326 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8327 {
8328         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8330         int pipe = intel_crtc->pipe;
8331         uint32_t val;
8332
8333         val = 0;
8334
8335         switch (intel_crtc->config->pipe_bpp) {
8336         case 18:
8337                 val |= PIPECONF_6BPC;
8338                 break;
8339         case 24:
8340                 val |= PIPECONF_8BPC;
8341                 break;
8342         case 30:
8343                 val |= PIPECONF_10BPC;
8344                 break;
8345         case 36:
8346                 val |= PIPECONF_12BPC;
8347                 break;
8348         default:
8349                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8350                 BUG();
8351         }
8352
8353         if (intel_crtc->config->dither)
8354                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8355
8356         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8357                 val |= PIPECONF_INTERLACED_ILK;
8358         else
8359                 val |= PIPECONF_PROGRESSIVE;
8360
8361         if (intel_crtc->config->limited_color_range)
8362                 val |= PIPECONF_COLOR_RANGE_SELECT;
8363
8364         I915_WRITE(PIPECONF(pipe), val);
8365         POSTING_READ(PIPECONF(pipe));
8366 }
8367
8368 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8369 {
8370         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8372         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8373         u32 val = 0;
8374
8375         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8376                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8377
8378         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8379                 val |= PIPECONF_INTERLACED_ILK;
8380         else
8381                 val |= PIPECONF_PROGRESSIVE;
8382
8383         I915_WRITE(PIPECONF(cpu_transcoder), val);
8384         POSTING_READ(PIPECONF(cpu_transcoder));
8385 }
8386
8387 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8388 {
8389         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8391         struct intel_crtc_state *config = intel_crtc->config;
8392
8393         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8394                 u32 val = 0;
8395
8396                 switch (intel_crtc->config->pipe_bpp) {
8397                 case 18:
8398                         val |= PIPEMISC_DITHER_6_BPC;
8399                         break;
8400                 case 24:
8401                         val |= PIPEMISC_DITHER_8_BPC;
8402                         break;
8403                 case 30:
8404                         val |= PIPEMISC_DITHER_10_BPC;
8405                         break;
8406                 case 36:
8407                         val |= PIPEMISC_DITHER_12_BPC;
8408                         break;
8409                 default:
8410                         /* Case prevented by pipe_config_set_bpp. */
8411                         BUG();
8412                 }
8413
8414                 if (intel_crtc->config->dither)
8415                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8416
8417                 if (config->ycbcr420) {
8418                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8419                                 PIPEMISC_YUV420_ENABLE |
8420                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8421                 }
8422
8423                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8424         }
8425 }
8426
8427 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8428 {
8429         /*
8430          * Account for spread spectrum to avoid
8431          * oversubscribing the link. Max center spread
8432          * is 2.5%; use 5% for safety's sake.
8433          */
8434         u32 bps = target_clock * bpp * 21 / 20;
8435         return DIV_ROUND_UP(bps, link_bw * 8);
8436 }
8437
8438 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8439 {
8440         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8441 }
8442
8443 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8444                                   struct intel_crtc_state *crtc_state,
8445                                   struct dpll *reduced_clock)
8446 {
8447         struct drm_crtc *crtc = &intel_crtc->base;
8448         struct drm_device *dev = crtc->dev;
8449         struct drm_i915_private *dev_priv = to_i915(dev);
8450         u32 dpll, fp, fp2;
8451         int factor;
8452
8453         /* Enable autotuning of the PLL clock (if permissible) */
8454         factor = 21;
8455         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8456                 if ((intel_panel_use_ssc(dev_priv) &&
8457                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8458                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8459                         factor = 25;
8460         } else if (crtc_state->sdvo_tv_clock)
8461                 factor = 20;
8462
8463         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8464
8465         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8466                 fp |= FP_CB_TUNE;
8467
8468         if (reduced_clock) {
8469                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8470
8471                 if (reduced_clock->m < factor * reduced_clock->n)
8472                         fp2 |= FP_CB_TUNE;
8473         } else {
8474                 fp2 = fp;
8475         }
8476
8477         dpll = 0;
8478
8479         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8480                 dpll |= DPLLB_MODE_LVDS;
8481         else
8482                 dpll |= DPLLB_MODE_DAC_SERIAL;
8483
8484         dpll |= (crtc_state->pixel_multiplier - 1)
8485                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8486
8487         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8488             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8489                 dpll |= DPLL_SDVO_HIGH_SPEED;
8490
8491         if (intel_crtc_has_dp_encoder(crtc_state))
8492                 dpll |= DPLL_SDVO_HIGH_SPEED;
8493
8494         /*
8495          * The high speed IO clock is only really required for
8496          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8497          * possible to share the DPLL between CRT and HDMI. Enabling
8498          * the clock needlessly does no real harm, except use up a
8499          * bit of power potentially.
8500          *
8501          * We'll limit this to IVB with 3 pipes, since it has only two
8502          * DPLLs and so DPLL sharing is the only way to get three pipes
8503          * driving PCH ports at the same time. On SNB we could do this,
8504          * and potentially avoid enabling the second DPLL, but it's not
8505          * clear if it''s a win or loss power wise. No point in doing
8506          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8507          */
8508         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8509             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8510                 dpll |= DPLL_SDVO_HIGH_SPEED;
8511
8512         /* compute bitmask from p1 value */
8513         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8514         /* also FPA1 */
8515         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8516
8517         switch (crtc_state->dpll.p2) {
8518         case 5:
8519                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8520                 break;
8521         case 7:
8522                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8523                 break;
8524         case 10:
8525                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8526                 break;
8527         case 14:
8528                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8529                 break;
8530         }
8531
8532         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8533             intel_panel_use_ssc(dev_priv))
8534                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8535         else
8536                 dpll |= PLL_REF_INPUT_DREFCLK;
8537
8538         dpll |= DPLL_VCO_ENABLE;
8539
8540         crtc_state->dpll_hw_state.dpll = dpll;
8541         crtc_state->dpll_hw_state.fp0 = fp;
8542         crtc_state->dpll_hw_state.fp1 = fp2;
8543 }
8544
8545 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8546                                        struct intel_crtc_state *crtc_state)
8547 {
8548         struct drm_device *dev = crtc->base.dev;
8549         struct drm_i915_private *dev_priv = to_i915(dev);
8550         const struct intel_limit *limit;
8551         int refclk = 120000;
8552
8553         memset(&crtc_state->dpll_hw_state, 0,
8554                sizeof(crtc_state->dpll_hw_state));
8555
8556         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8557         if (!crtc_state->has_pch_encoder)
8558                 return 0;
8559
8560         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8561                 if (intel_panel_use_ssc(dev_priv)) {
8562                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8563                                       dev_priv->vbt.lvds_ssc_freq);
8564                         refclk = dev_priv->vbt.lvds_ssc_freq;
8565                 }
8566
8567                 if (intel_is_dual_link_lvds(dev)) {
8568                         if (refclk == 100000)
8569                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8570                         else
8571                                 limit = &intel_limits_ironlake_dual_lvds;
8572                 } else {
8573                         if (refclk == 100000)
8574                                 limit = &intel_limits_ironlake_single_lvds_100m;
8575                         else
8576                                 limit = &intel_limits_ironlake_single_lvds;
8577                 }
8578         } else {
8579                 limit = &intel_limits_ironlake_dac;
8580         }
8581
8582         if (!crtc_state->clock_set &&
8583             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8584                                 refclk, NULL, &crtc_state->dpll)) {
8585                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8586                 return -EINVAL;
8587         }
8588
8589         ironlake_compute_dpll(crtc, crtc_state, NULL);
8590
8591         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8592                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8593                                  pipe_name(crtc->pipe));
8594                 return -EINVAL;
8595         }
8596
8597         return 0;
8598 }
8599
8600 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8601                                          struct intel_link_m_n *m_n)
8602 {
8603         struct drm_device *dev = crtc->base.dev;
8604         struct drm_i915_private *dev_priv = to_i915(dev);
8605         enum pipe pipe = crtc->pipe;
8606
8607         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8608         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8609         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8610                 & ~TU_SIZE_MASK;
8611         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8612         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8613                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8614 }
8615
8616 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8617                                          enum transcoder transcoder,
8618                                          struct intel_link_m_n *m_n,
8619                                          struct intel_link_m_n *m2_n2)
8620 {
8621         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8622         enum pipe pipe = crtc->pipe;
8623
8624         if (INTEL_GEN(dev_priv) >= 5) {
8625                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8626                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8627                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8628                         & ~TU_SIZE_MASK;
8629                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8630                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8631                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8632                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8633                  * gen < 8) and if DRRS is supported (to make sure the
8634                  * registers are not unnecessarily read).
8635                  */
8636                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8637                         crtc->config->has_drrs) {
8638                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8639                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8640                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8641                                         & ~TU_SIZE_MASK;
8642                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8643                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8644                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8645                 }
8646         } else {
8647                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8648                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8649                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8650                         & ~TU_SIZE_MASK;
8651                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8652                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8653                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8654         }
8655 }
8656
8657 void intel_dp_get_m_n(struct intel_crtc *crtc,
8658                       struct intel_crtc_state *pipe_config)
8659 {
8660         if (pipe_config->has_pch_encoder)
8661                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8662         else
8663                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8664                                              &pipe_config->dp_m_n,
8665                                              &pipe_config->dp_m2_n2);
8666 }
8667
8668 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8669                                         struct intel_crtc_state *pipe_config)
8670 {
8671         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8672                                      &pipe_config->fdi_m_n, NULL);
8673 }
8674
8675 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8676                                     struct intel_crtc_state *pipe_config)
8677 {
8678         struct drm_device *dev = crtc->base.dev;
8679         struct drm_i915_private *dev_priv = to_i915(dev);
8680         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8681         uint32_t ps_ctrl = 0;
8682         int id = -1;
8683         int i;
8684
8685         /* find scaler attached to this pipe */
8686         for (i = 0; i < crtc->num_scalers; i++) {
8687                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8688                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8689                         id = i;
8690                         pipe_config->pch_pfit.enabled = true;
8691                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8692                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8693                         break;
8694                 }
8695         }
8696
8697         scaler_state->scaler_id = id;
8698         if (id >= 0) {
8699                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8700         } else {
8701                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8702         }
8703 }
8704
8705 static void
8706 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8707                                  struct intel_initial_plane_config *plane_config)
8708 {
8709         struct drm_device *dev = crtc->base.dev;
8710         struct drm_i915_private *dev_priv = to_i915(dev);
8711         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8712         enum plane_id plane_id = plane->id;
8713         enum pipe pipe = crtc->pipe;
8714         u32 val, base, offset, stride_mult, tiling, alpha;
8715         int fourcc, pixel_format;
8716         unsigned int aligned_height;
8717         struct drm_framebuffer *fb;
8718         struct intel_framebuffer *intel_fb;
8719
8720         if (!plane->get_hw_state(plane))
8721                 return;
8722
8723         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8724         if (!intel_fb) {
8725                 DRM_DEBUG_KMS("failed to alloc fb\n");
8726                 return;
8727         }
8728
8729         fb = &intel_fb->base;
8730
8731         fb->dev = dev;
8732
8733         val = I915_READ(PLANE_CTL(pipe, plane_id));
8734
8735         if (INTEL_GEN(dev_priv) >= 11)
8736                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8737         else
8738                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8739
8740         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8741                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
8742                 alpha &= PLANE_COLOR_ALPHA_MASK;
8743         } else {
8744                 alpha = val & PLANE_CTL_ALPHA_MASK;
8745         }
8746
8747         fourcc = skl_format_to_fourcc(pixel_format,
8748                                       val & PLANE_CTL_ORDER_RGBX, alpha);
8749         fb->format = drm_format_info(fourcc);
8750
8751         tiling = val & PLANE_CTL_TILED_MASK;
8752         switch (tiling) {
8753         case PLANE_CTL_TILED_LINEAR:
8754                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8755                 break;
8756         case PLANE_CTL_TILED_X:
8757                 plane_config->tiling = I915_TILING_X;
8758                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8759                 break;
8760         case PLANE_CTL_TILED_Y:
8761                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8762                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8763                 else
8764                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8765                 break;
8766         case PLANE_CTL_TILED_YF:
8767                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8768                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8769                 else
8770                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8771                 break;
8772         default:
8773                 MISSING_CASE(tiling);
8774                 goto error;
8775         }
8776
8777         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8778         plane_config->base = base;
8779
8780         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
8781
8782         val = I915_READ(PLANE_SIZE(pipe, plane_id));
8783         fb->height = ((val >> 16) & 0xfff) + 1;
8784         fb->width = ((val >> 0) & 0x1fff) + 1;
8785
8786         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
8787         stride_mult = intel_fb_stride_alignment(fb, 0);
8788         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8789
8790         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8791
8792         plane_config->size = fb->pitches[0] * aligned_height;
8793
8794         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8795                       crtc->base.name, plane->base.name, fb->width, fb->height,
8796                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8797                       plane_config->size);
8798
8799         plane_config->fb = intel_fb;
8800         return;
8801
8802 error:
8803         kfree(intel_fb);
8804 }
8805
8806 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8807                                      struct intel_crtc_state *pipe_config)
8808 {
8809         struct drm_device *dev = crtc->base.dev;
8810         struct drm_i915_private *dev_priv = to_i915(dev);
8811         uint32_t tmp;
8812
8813         tmp = I915_READ(PF_CTL(crtc->pipe));
8814
8815         if (tmp & PF_ENABLE) {
8816                 pipe_config->pch_pfit.enabled = true;
8817                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8818                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8819
8820                 /* We currently do not free assignements of panel fitters on
8821                  * ivb/hsw (since we don't use the higher upscaling modes which
8822                  * differentiates them) so just WARN about this case for now. */
8823                 if (IS_GEN7(dev_priv)) {
8824                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8825                                 PF_PIPE_SEL_IVB(crtc->pipe));
8826                 }
8827         }
8828 }
8829
8830 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8831                                      struct intel_crtc_state *pipe_config)
8832 {
8833         struct drm_device *dev = crtc->base.dev;
8834         struct drm_i915_private *dev_priv = to_i915(dev);
8835         enum intel_display_power_domain power_domain;
8836         uint32_t tmp;
8837         bool ret;
8838
8839         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8840         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8841                 return false;
8842
8843         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8844         pipe_config->shared_dpll = NULL;
8845
8846         ret = false;
8847         tmp = I915_READ(PIPECONF(crtc->pipe));
8848         if (!(tmp & PIPECONF_ENABLE))
8849                 goto out;
8850
8851         switch (tmp & PIPECONF_BPC_MASK) {
8852         case PIPECONF_6BPC:
8853                 pipe_config->pipe_bpp = 18;
8854                 break;
8855         case PIPECONF_8BPC:
8856                 pipe_config->pipe_bpp = 24;
8857                 break;
8858         case PIPECONF_10BPC:
8859                 pipe_config->pipe_bpp = 30;
8860                 break;
8861         case PIPECONF_12BPC:
8862                 pipe_config->pipe_bpp = 36;
8863                 break;
8864         default:
8865                 break;
8866         }
8867
8868         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8869                 pipe_config->limited_color_range = true;
8870
8871         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8872                 struct intel_shared_dpll *pll;
8873                 enum intel_dpll_id pll_id;
8874
8875                 pipe_config->has_pch_encoder = true;
8876
8877                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8878                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8879                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8880
8881                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8882
8883                 if (HAS_PCH_IBX(dev_priv)) {
8884                         /*
8885                          * The pipe->pch transcoder and pch transcoder->pll
8886                          * mapping is fixed.
8887                          */
8888                         pll_id = (enum intel_dpll_id) crtc->pipe;
8889                 } else {
8890                         tmp = I915_READ(PCH_DPLL_SEL);
8891                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8892                                 pll_id = DPLL_ID_PCH_PLL_B;
8893                         else
8894                                 pll_id= DPLL_ID_PCH_PLL_A;
8895                 }
8896
8897                 pipe_config->shared_dpll =
8898                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8899                 pll = pipe_config->shared_dpll;
8900
8901                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
8902                                                 &pipe_config->dpll_hw_state));
8903
8904                 tmp = pipe_config->dpll_hw_state.dpll;
8905                 pipe_config->pixel_multiplier =
8906                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8907                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8908
8909                 ironlake_pch_clock_get(crtc, pipe_config);
8910         } else {
8911                 pipe_config->pixel_multiplier = 1;
8912         }
8913
8914         intel_get_pipe_timings(crtc, pipe_config);
8915         intel_get_pipe_src_size(crtc, pipe_config);
8916
8917         ironlake_get_pfit_config(crtc, pipe_config);
8918
8919         ret = true;
8920
8921 out:
8922         intel_display_power_put(dev_priv, power_domain);
8923
8924         return ret;
8925 }
8926
8927 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8928 {
8929         struct drm_device *dev = &dev_priv->drm;
8930         struct intel_crtc *crtc;
8931
8932         for_each_intel_crtc(dev, crtc)
8933                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8934                      pipe_name(crtc->pipe));
8935
8936         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8937                         "Display power well on\n");
8938         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8939         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8940         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8941         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8942         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8943              "CPU PWM1 enabled\n");
8944         if (IS_HASWELL(dev_priv))
8945                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8946                      "CPU PWM2 enabled\n");
8947         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8948              "PCH PWM1 enabled\n");
8949         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8950              "Utility pin enabled\n");
8951         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8952
8953         /*
8954          * In theory we can still leave IRQs enabled, as long as only the HPD
8955          * interrupts remain enabled. We used to check for that, but since it's
8956          * gen-specific and since we only disable LCPLL after we fully disable
8957          * the interrupts, the check below should be enough.
8958          */
8959         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8960 }
8961
8962 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8963 {
8964         if (IS_HASWELL(dev_priv))
8965                 return I915_READ(D_COMP_HSW);
8966         else
8967                 return I915_READ(D_COMP_BDW);
8968 }
8969
8970 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8971 {
8972         if (IS_HASWELL(dev_priv)) {
8973                 mutex_lock(&dev_priv->pcu_lock);
8974                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8975                                             val))
8976                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8977                 mutex_unlock(&dev_priv->pcu_lock);
8978         } else {
8979                 I915_WRITE(D_COMP_BDW, val);
8980                 POSTING_READ(D_COMP_BDW);
8981         }
8982 }
8983
8984 /*
8985  * This function implements pieces of two sequences from BSpec:
8986  * - Sequence for display software to disable LCPLL
8987  * - Sequence for display software to allow package C8+
8988  * The steps implemented here are just the steps that actually touch the LCPLL
8989  * register. Callers should take care of disabling all the display engine
8990  * functions, doing the mode unset, fixing interrupts, etc.
8991  */
8992 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8993                               bool switch_to_fclk, bool allow_power_down)
8994 {
8995         uint32_t val;
8996
8997         assert_can_disable_lcpll(dev_priv);
8998
8999         val = I915_READ(LCPLL_CTL);
9000
9001         if (switch_to_fclk) {
9002                 val |= LCPLL_CD_SOURCE_FCLK;
9003                 I915_WRITE(LCPLL_CTL, val);
9004
9005                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9006                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9007                         DRM_ERROR("Switching to FCLK failed\n");
9008
9009                 val = I915_READ(LCPLL_CTL);
9010         }
9011
9012         val |= LCPLL_PLL_DISABLE;
9013         I915_WRITE(LCPLL_CTL, val);
9014         POSTING_READ(LCPLL_CTL);
9015
9016         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9017                 DRM_ERROR("LCPLL still locked\n");
9018
9019         val = hsw_read_dcomp(dev_priv);
9020         val |= D_COMP_COMP_DISABLE;
9021         hsw_write_dcomp(dev_priv, val);
9022         ndelay(100);
9023
9024         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9025                      1))
9026                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9027
9028         if (allow_power_down) {
9029                 val = I915_READ(LCPLL_CTL);
9030                 val |= LCPLL_POWER_DOWN_ALLOW;
9031                 I915_WRITE(LCPLL_CTL, val);
9032                 POSTING_READ(LCPLL_CTL);
9033         }
9034 }
9035
9036 /*
9037  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9038  * source.
9039  */
9040 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9041 {
9042         uint32_t val;
9043
9044         val = I915_READ(LCPLL_CTL);
9045
9046         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9047                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9048                 return;
9049
9050         /*
9051          * Make sure we're not on PC8 state before disabling PC8, otherwise
9052          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9053          */
9054         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9055
9056         if (val & LCPLL_POWER_DOWN_ALLOW) {
9057                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9058                 I915_WRITE(LCPLL_CTL, val);
9059                 POSTING_READ(LCPLL_CTL);
9060         }
9061
9062         val = hsw_read_dcomp(dev_priv);
9063         val |= D_COMP_COMP_FORCE;
9064         val &= ~D_COMP_COMP_DISABLE;
9065         hsw_write_dcomp(dev_priv, val);
9066
9067         val = I915_READ(LCPLL_CTL);
9068         val &= ~LCPLL_PLL_DISABLE;
9069         I915_WRITE(LCPLL_CTL, val);
9070
9071         if (intel_wait_for_register(dev_priv,
9072                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9073                                     5))
9074                 DRM_ERROR("LCPLL not locked yet\n");
9075
9076         if (val & LCPLL_CD_SOURCE_FCLK) {
9077                 val = I915_READ(LCPLL_CTL);
9078                 val &= ~LCPLL_CD_SOURCE_FCLK;
9079                 I915_WRITE(LCPLL_CTL, val);
9080
9081                 if (wait_for_us((I915_READ(LCPLL_CTL) &
9082                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9083                         DRM_ERROR("Switching back to LCPLL failed\n");
9084         }
9085
9086         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9087
9088         intel_update_cdclk(dev_priv);
9089         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9090 }
9091
9092 /*
9093  * Package states C8 and deeper are really deep PC states that can only be
9094  * reached when all the devices on the system allow it, so even if the graphics
9095  * device allows PC8+, it doesn't mean the system will actually get to these
9096  * states. Our driver only allows PC8+ when going into runtime PM.
9097  *
9098  * The requirements for PC8+ are that all the outputs are disabled, the power
9099  * well is disabled and most interrupts are disabled, and these are also
9100  * requirements for runtime PM. When these conditions are met, we manually do
9101  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9102  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9103  * hang the machine.
9104  *
9105  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9106  * the state of some registers, so when we come back from PC8+ we need to
9107  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9108  * need to take care of the registers kept by RC6. Notice that this happens even
9109  * if we don't put the device in PCI D3 state (which is what currently happens
9110  * because of the runtime PM support).
9111  *
9112  * For more, read "Display Sequences for Package C8" on the hardware
9113  * documentation.
9114  */
9115 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9116 {
9117         uint32_t val;
9118
9119         DRM_DEBUG_KMS("Enabling package C8+\n");
9120
9121         if (HAS_PCH_LPT_LP(dev_priv)) {
9122                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9123                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9124                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9125         }
9126
9127         lpt_disable_clkout_dp(dev_priv);
9128         hsw_disable_lcpll(dev_priv, true, true);
9129 }
9130
9131 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9132 {
9133         uint32_t val;
9134
9135         DRM_DEBUG_KMS("Disabling package C8+\n");
9136
9137         hsw_restore_lcpll(dev_priv);
9138         lpt_init_pch_refclk(dev_priv);
9139
9140         if (HAS_PCH_LPT_LP(dev_priv)) {
9141                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9142                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9143                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9144         }
9145 }
9146
9147 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9148                                       struct intel_crtc_state *crtc_state)
9149 {
9150         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9151                 struct intel_encoder *encoder =
9152                         intel_ddi_get_crtc_new_encoder(crtc_state);
9153
9154                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9155                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9156                                          pipe_name(crtc->pipe));
9157                         return -EINVAL;
9158                 }
9159         }
9160
9161         return 0;
9162 }
9163
9164 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9165                                    enum port port,
9166                                    struct intel_crtc_state *pipe_config)
9167 {
9168         enum intel_dpll_id id;
9169         u32 temp;
9170
9171         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9172         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9173
9174         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9175                 return;
9176
9177         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9178 }
9179
9180 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9181                                 enum port port,
9182                                 struct intel_crtc_state *pipe_config)
9183 {
9184         enum intel_dpll_id id;
9185
9186         switch (port) {
9187         case PORT_A:
9188                 id = DPLL_ID_SKL_DPLL0;
9189                 break;
9190         case PORT_B:
9191                 id = DPLL_ID_SKL_DPLL1;
9192                 break;
9193         case PORT_C:
9194                 id = DPLL_ID_SKL_DPLL2;
9195                 break;
9196         default:
9197                 DRM_ERROR("Incorrect port type\n");
9198                 return;
9199         }
9200
9201         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9202 }
9203
9204 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9205                                 enum port port,
9206                                 struct intel_crtc_state *pipe_config)
9207 {
9208         enum intel_dpll_id id;
9209         u32 temp;
9210
9211         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9212         id = temp >> (port * 3 + 1);
9213
9214         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9215                 return;
9216
9217         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9218 }
9219
9220 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9221                                 enum port port,
9222                                 struct intel_crtc_state *pipe_config)
9223 {
9224         enum intel_dpll_id id;
9225         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9226
9227         switch (ddi_pll_sel) {
9228         case PORT_CLK_SEL_WRPLL1:
9229                 id = DPLL_ID_WRPLL1;
9230                 break;
9231         case PORT_CLK_SEL_WRPLL2:
9232                 id = DPLL_ID_WRPLL2;
9233                 break;
9234         case PORT_CLK_SEL_SPLL:
9235                 id = DPLL_ID_SPLL;
9236                 break;
9237         case PORT_CLK_SEL_LCPLL_810:
9238                 id = DPLL_ID_LCPLL_810;
9239                 break;
9240         case PORT_CLK_SEL_LCPLL_1350:
9241                 id = DPLL_ID_LCPLL_1350;
9242                 break;
9243         case PORT_CLK_SEL_LCPLL_2700:
9244                 id = DPLL_ID_LCPLL_2700;
9245                 break;
9246         default:
9247                 MISSING_CASE(ddi_pll_sel);
9248                 /* fall through */
9249         case PORT_CLK_SEL_NONE:
9250                 return;
9251         }
9252
9253         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9254 }
9255
9256 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9257                                      struct intel_crtc_state *pipe_config,
9258                                      u64 *power_domain_mask)
9259 {
9260         struct drm_device *dev = crtc->base.dev;
9261         struct drm_i915_private *dev_priv = to_i915(dev);
9262         enum intel_display_power_domain power_domain;
9263         u32 tmp;
9264
9265         /*
9266          * The pipe->transcoder mapping is fixed with the exception of the eDP
9267          * transcoder handled below.
9268          */
9269         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9270
9271         /*
9272          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9273          * consistency and less surprising code; it's in always on power).
9274          */
9275         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9276         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9277                 enum pipe trans_edp_pipe;
9278                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9279                 default:
9280                         WARN(1, "unknown pipe linked to edp transcoder\n");
9281                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9282                 case TRANS_DDI_EDP_INPUT_A_ON:
9283                         trans_edp_pipe = PIPE_A;
9284                         break;
9285                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9286                         trans_edp_pipe = PIPE_B;
9287                         break;
9288                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9289                         trans_edp_pipe = PIPE_C;
9290                         break;
9291                 }
9292
9293                 if (trans_edp_pipe == crtc->pipe)
9294                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9295         }
9296
9297         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9298         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9299                 return false;
9300         *power_domain_mask |= BIT_ULL(power_domain);
9301
9302         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9303
9304         return tmp & PIPECONF_ENABLE;
9305 }
9306
9307 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9308                                          struct intel_crtc_state *pipe_config,
9309                                          u64 *power_domain_mask)
9310 {
9311         struct drm_device *dev = crtc->base.dev;
9312         struct drm_i915_private *dev_priv = to_i915(dev);
9313         enum intel_display_power_domain power_domain;
9314         enum port port;
9315         enum transcoder cpu_transcoder;
9316         u32 tmp;
9317
9318         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9319                 if (port == PORT_A)
9320                         cpu_transcoder = TRANSCODER_DSI_A;
9321                 else
9322                         cpu_transcoder = TRANSCODER_DSI_C;
9323
9324                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9325                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9326                         continue;
9327                 *power_domain_mask |= BIT_ULL(power_domain);
9328
9329                 /*
9330                  * The PLL needs to be enabled with a valid divider
9331                  * configuration, otherwise accessing DSI registers will hang
9332                  * the machine. See BSpec North Display Engine
9333                  * registers/MIPI[BXT]. We can break out here early, since we
9334                  * need the same DSI PLL to be enabled for both DSI ports.
9335                  */
9336                 if (!intel_dsi_pll_is_enabled(dev_priv))
9337                         break;
9338
9339                 /* XXX: this works for video mode only */
9340                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9341                 if (!(tmp & DPI_ENABLE))
9342                         continue;
9343
9344                 tmp = I915_READ(MIPI_CTRL(port));
9345                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9346                         continue;
9347
9348                 pipe_config->cpu_transcoder = cpu_transcoder;
9349                 break;
9350         }
9351
9352         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9353 }
9354
9355 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9356                                        struct intel_crtc_state *pipe_config)
9357 {
9358         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9359         struct intel_shared_dpll *pll;
9360         enum port port;
9361         uint32_t tmp;
9362
9363         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9364
9365         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9366
9367         if (IS_CANNONLAKE(dev_priv))
9368                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9369         else if (IS_GEN9_BC(dev_priv))
9370                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9371         else if (IS_GEN9_LP(dev_priv))
9372                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9373         else
9374                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9375
9376         pll = pipe_config->shared_dpll;
9377         if (pll) {
9378                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9379                                                 &pipe_config->dpll_hw_state));
9380         }
9381
9382         /*
9383          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9384          * DDI E. So just check whether this pipe is wired to DDI E and whether
9385          * the PCH transcoder is on.
9386          */
9387         if (INTEL_GEN(dev_priv) < 9 &&
9388             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9389                 pipe_config->has_pch_encoder = true;
9390
9391                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9392                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9393                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9394
9395                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9396         }
9397 }
9398
9399 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9400                                     struct intel_crtc_state *pipe_config)
9401 {
9402         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9403         enum intel_display_power_domain power_domain;
9404         u64 power_domain_mask;
9405         bool active;
9406
9407         intel_crtc_init_scalers(crtc, pipe_config);
9408
9409         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9410         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9411                 return false;
9412         power_domain_mask = BIT_ULL(power_domain);
9413
9414         pipe_config->shared_dpll = NULL;
9415
9416         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9417
9418         if (IS_GEN9_LP(dev_priv) &&
9419             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9420                 WARN_ON(active);
9421                 active = true;
9422         }
9423
9424         if (!active)
9425                 goto out;
9426
9427         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9428                 haswell_get_ddi_port_state(crtc, pipe_config);
9429                 intel_get_pipe_timings(crtc, pipe_config);
9430         }
9431
9432         intel_get_pipe_src_size(crtc, pipe_config);
9433
9434         pipe_config->gamma_mode =
9435                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9436
9437         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9438                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9439                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9440
9441                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9442                         bool blend_mode_420 = tmp &
9443                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9444
9445                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9446                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9447                             pipe_config->ycbcr420 != blend_mode_420)
9448                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9449                 } else if (clrspace_yuv) {
9450                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9451                 }
9452         }
9453
9454         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9455         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9456                 power_domain_mask |= BIT_ULL(power_domain);
9457                 if (INTEL_GEN(dev_priv) >= 9)
9458                         skylake_get_pfit_config(crtc, pipe_config);
9459                 else
9460                         ironlake_get_pfit_config(crtc, pipe_config);
9461         }
9462
9463         if (hsw_crtc_supports_ips(crtc)) {
9464                 if (IS_HASWELL(dev_priv))
9465                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9466                 else {
9467                         /*
9468                          * We cannot readout IPS state on broadwell, set to
9469                          * true so we can set it to a defined state on first
9470                          * commit.
9471                          */
9472                         pipe_config->ips_enabled = true;
9473                 }
9474         }
9475
9476         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9477             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9478                 pipe_config->pixel_multiplier =
9479                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9480         } else {
9481                 pipe_config->pixel_multiplier = 1;
9482         }
9483
9484 out:
9485         for_each_power_domain(power_domain, power_domain_mask)
9486                 intel_display_power_put(dev_priv, power_domain);
9487
9488         return active;
9489 }
9490
9491 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9492 {
9493         struct drm_i915_private *dev_priv =
9494                 to_i915(plane_state->base.plane->dev);
9495         const struct drm_framebuffer *fb = plane_state->base.fb;
9496         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9497         u32 base;
9498
9499         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9500                 base = obj->phys_handle->busaddr;
9501         else
9502                 base = intel_plane_ggtt_offset(plane_state);
9503
9504         base += plane_state->main.offset;
9505
9506         /* ILK+ do this automagically */
9507         if (HAS_GMCH_DISPLAY(dev_priv) &&
9508             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9509                 base += (plane_state->base.crtc_h *
9510                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9511
9512         return base;
9513 }
9514
9515 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9516 {
9517         int x = plane_state->base.crtc_x;
9518         int y = plane_state->base.crtc_y;
9519         u32 pos = 0;
9520
9521         if (x < 0) {
9522                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9523                 x = -x;
9524         }
9525         pos |= x << CURSOR_X_SHIFT;
9526
9527         if (y < 0) {
9528                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9529                 y = -y;
9530         }
9531         pos |= y << CURSOR_Y_SHIFT;
9532
9533         return pos;
9534 }
9535
9536 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9537 {
9538         const struct drm_mode_config *config =
9539                 &plane_state->base.plane->dev->mode_config;
9540         int width = plane_state->base.crtc_w;
9541         int height = plane_state->base.crtc_h;
9542
9543         return width > 0 && width <= config->cursor_width &&
9544                 height > 0 && height <= config->cursor_height;
9545 }
9546
9547 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9548                               struct intel_plane_state *plane_state)
9549 {
9550         const struct drm_framebuffer *fb = plane_state->base.fb;
9551         int src_x, src_y;
9552         u32 offset;
9553         int ret;
9554
9555         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9556                                                   &crtc_state->base,
9557                                                   DRM_PLANE_HELPER_NO_SCALING,
9558                                                   DRM_PLANE_HELPER_NO_SCALING,
9559                                                   true, true);
9560         if (ret)
9561                 return ret;
9562
9563         if (!fb)
9564                 return 0;
9565
9566         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9567                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9568                 return -EINVAL;
9569         }
9570
9571         src_x = plane_state->base.src_x >> 16;
9572         src_y = plane_state->base.src_y >> 16;
9573
9574         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9575         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9576
9577         if (src_x != 0 || src_y != 0) {
9578                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9579                 return -EINVAL;
9580         }
9581
9582         plane_state->main.offset = offset;
9583
9584         return 0;
9585 }
9586
9587 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9588                            const struct intel_plane_state *plane_state)
9589 {
9590         const struct drm_framebuffer *fb = plane_state->base.fb;
9591
9592         return CURSOR_ENABLE |
9593                 CURSOR_GAMMA_ENABLE |
9594                 CURSOR_FORMAT_ARGB |
9595                 CURSOR_STRIDE(fb->pitches[0]);
9596 }
9597
9598 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9599 {
9600         int width = plane_state->base.crtc_w;
9601
9602         /*
9603          * 845g/865g are only limited by the width of their cursors,
9604          * the height is arbitrary up to the precision of the register.
9605          */
9606         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9607 }
9608
9609 static int i845_check_cursor(struct intel_plane *plane,
9610                              struct intel_crtc_state *crtc_state,
9611                              struct intel_plane_state *plane_state)
9612 {
9613         const struct drm_framebuffer *fb = plane_state->base.fb;
9614         int ret;
9615
9616         ret = intel_check_cursor(crtc_state, plane_state);
9617         if (ret)
9618                 return ret;
9619
9620         /* if we want to turn off the cursor ignore width and height */
9621         if (!fb)
9622                 return 0;
9623
9624         /* Check for which cursor types we support */
9625         if (!i845_cursor_size_ok(plane_state)) {
9626                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9627                           plane_state->base.crtc_w,
9628                           plane_state->base.crtc_h);
9629                 return -EINVAL;
9630         }
9631
9632         switch (fb->pitches[0]) {
9633         case 256:
9634         case 512:
9635         case 1024:
9636         case 2048:
9637                 break;
9638         default:
9639                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9640                               fb->pitches[0]);
9641                 return -EINVAL;
9642         }
9643
9644         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9645
9646         return 0;
9647 }
9648
9649 static void i845_update_cursor(struct intel_plane *plane,
9650                                const struct intel_crtc_state *crtc_state,
9651                                const struct intel_plane_state *plane_state)
9652 {
9653         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9654         u32 cntl = 0, base = 0, pos = 0, size = 0;
9655         unsigned long irqflags;
9656
9657         if (plane_state && plane_state->base.visible) {
9658                 unsigned int width = plane_state->base.crtc_w;
9659                 unsigned int height = plane_state->base.crtc_h;
9660
9661                 cntl = plane_state->ctl;
9662                 size = (height << 12) | width;
9663
9664                 base = intel_cursor_base(plane_state);
9665                 pos = intel_cursor_position(plane_state);
9666         }
9667
9668         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9669
9670         /* On these chipsets we can only modify the base/size/stride
9671          * whilst the cursor is disabled.
9672          */
9673         if (plane->cursor.base != base ||
9674             plane->cursor.size != size ||
9675             plane->cursor.cntl != cntl) {
9676                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9677                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9678                 I915_WRITE_FW(CURSIZE, size);
9679                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9680                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9681
9682                 plane->cursor.base = base;
9683                 plane->cursor.size = size;
9684                 plane->cursor.cntl = cntl;
9685         } else {
9686                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9687         }
9688
9689         POSTING_READ_FW(CURCNTR(PIPE_A));
9690
9691         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9692 }
9693
9694 static void i845_disable_cursor(struct intel_plane *plane,
9695                                 struct intel_crtc *crtc)
9696 {
9697         i845_update_cursor(plane, NULL, NULL);
9698 }
9699
9700 static bool i845_cursor_get_hw_state(struct intel_plane *plane)
9701 {
9702         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9703         enum intel_display_power_domain power_domain;
9704         bool ret;
9705
9706         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9707         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9708                 return false;
9709
9710         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9711
9712         intel_display_power_put(dev_priv, power_domain);
9713
9714         return ret;
9715 }
9716
9717 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9718                            const struct intel_plane_state *plane_state)
9719 {
9720         struct drm_i915_private *dev_priv =
9721                 to_i915(plane_state->base.plane->dev);
9722         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9723         u32 cntl;
9724
9725         cntl = MCURSOR_GAMMA_ENABLE;
9726
9727         if (HAS_DDI(dev_priv))
9728                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9729
9730         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9731                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9732
9733         switch (plane_state->base.crtc_w) {
9734         case 64:
9735                 cntl |= CURSOR_MODE_64_ARGB_AX;
9736                 break;
9737         case 128:
9738                 cntl |= CURSOR_MODE_128_ARGB_AX;
9739                 break;
9740         case 256:
9741                 cntl |= CURSOR_MODE_256_ARGB_AX;
9742                 break;
9743         default:
9744                 MISSING_CASE(plane_state->base.crtc_w);
9745                 return 0;
9746         }
9747
9748         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9749                 cntl |= CURSOR_ROTATE_180;
9750
9751         return cntl;
9752 }
9753
9754 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9755 {
9756         struct drm_i915_private *dev_priv =
9757                 to_i915(plane_state->base.plane->dev);
9758         int width = plane_state->base.crtc_w;
9759         int height = plane_state->base.crtc_h;
9760
9761         if (!intel_cursor_size_ok(plane_state))
9762                 return false;
9763
9764         /* Cursor width is limited to a few power-of-two sizes */
9765         switch (width) {
9766         case 256:
9767         case 128:
9768         case 64:
9769                 break;
9770         default:
9771                 return false;
9772         }
9773
9774         /*
9775          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9776          * height from 8 lines up to the cursor width, when the
9777          * cursor is not rotated. Everything else requires square
9778          * cursors.
9779          */
9780         if (HAS_CUR_FBC(dev_priv) &&
9781             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9782                 if (height < 8 || height > width)
9783                         return false;
9784         } else {
9785                 if (height != width)
9786                         return false;
9787         }
9788
9789         return true;
9790 }
9791
9792 static int i9xx_check_cursor(struct intel_plane *plane,
9793                              struct intel_crtc_state *crtc_state,
9794                              struct intel_plane_state *plane_state)
9795 {
9796         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9797         const struct drm_framebuffer *fb = plane_state->base.fb;
9798         enum pipe pipe = plane->pipe;
9799         int ret;
9800
9801         ret = intel_check_cursor(crtc_state, plane_state);
9802         if (ret)
9803                 return ret;
9804
9805         /* if we want to turn off the cursor ignore width and height */
9806         if (!fb)
9807                 return 0;
9808
9809         /* Check for which cursor types we support */
9810         if (!i9xx_cursor_size_ok(plane_state)) {
9811                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9812                           plane_state->base.crtc_w,
9813                           plane_state->base.crtc_h);
9814                 return -EINVAL;
9815         }
9816
9817         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9818                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9819                               fb->pitches[0], plane_state->base.crtc_w);
9820                 return -EINVAL;
9821         }
9822
9823         /*
9824          * There's something wrong with the cursor on CHV pipe C.
9825          * If it straddles the left edge of the screen then
9826          * moving it away from the edge or disabling it often
9827          * results in a pipe underrun, and often that can lead to
9828          * dead pipe (constant underrun reported, and it scans
9829          * out just a solid color). To recover from that, the
9830          * display power well must be turned off and on again.
9831          * Refuse the put the cursor into that compromised position.
9832          */
9833         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9834             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9835                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9836                 return -EINVAL;
9837         }
9838
9839         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9840
9841         return 0;
9842 }
9843
9844 static void i9xx_update_cursor(struct intel_plane *plane,
9845                                const struct intel_crtc_state *crtc_state,
9846                                const struct intel_plane_state *plane_state)
9847 {
9848         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9849         enum pipe pipe = plane->pipe;
9850         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9851         unsigned long irqflags;
9852
9853         if (plane_state && plane_state->base.visible) {
9854                 cntl = plane_state->ctl;
9855
9856                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9857                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9858
9859                 base = intel_cursor_base(plane_state);
9860                 pos = intel_cursor_position(plane_state);
9861         }
9862
9863         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9864
9865         /*
9866          * On some platforms writing CURCNTR first will also
9867          * cause CURPOS to be armed by the CURBASE write.
9868          * Without the CURCNTR write the CURPOS write would
9869          * arm itself. Thus we always start the full update
9870          * with a CURCNTR write.
9871          *
9872          * On other platforms CURPOS always requires the
9873          * CURBASE write to arm the update. Additonally
9874          * a write to any of the cursor register will cancel
9875          * an already armed cursor update. Thus leaving out
9876          * the CURBASE write after CURPOS could lead to a
9877          * cursor that doesn't appear to move, or even change
9878          * shape. Thus we always write CURBASE.
9879          *
9880          * CURCNTR and CUR_FBC_CTL are always
9881          * armed by the CURBASE write only.
9882          */
9883         if (plane->cursor.base != base ||
9884             plane->cursor.size != fbc_ctl ||
9885             plane->cursor.cntl != cntl) {
9886                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9887                 if (HAS_CUR_FBC(dev_priv))
9888                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9889                 I915_WRITE_FW(CURPOS(pipe), pos);
9890                 I915_WRITE_FW(CURBASE(pipe), base);
9891
9892                 plane->cursor.base = base;
9893                 plane->cursor.size = fbc_ctl;
9894                 plane->cursor.cntl = cntl;
9895         } else {
9896                 I915_WRITE_FW(CURPOS(pipe), pos);
9897                 I915_WRITE_FW(CURBASE(pipe), base);
9898         }
9899
9900         POSTING_READ_FW(CURBASE(pipe));
9901
9902         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9903 }
9904
9905 static void i9xx_disable_cursor(struct intel_plane *plane,
9906                                 struct intel_crtc *crtc)
9907 {
9908         i9xx_update_cursor(plane, NULL, NULL);
9909 }
9910
9911 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
9912 {
9913         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9914         enum intel_display_power_domain power_domain;
9915         enum pipe pipe = plane->pipe;
9916         bool ret;
9917
9918         /*
9919          * Not 100% correct for planes that can move between pipes,
9920          * but that's only the case for gen2-3 which don't have any
9921          * display power wells.
9922          */
9923         power_domain = POWER_DOMAIN_PIPE(pipe);
9924         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9925                 return false;
9926
9927         ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
9928
9929         intel_display_power_put(dev_priv, power_domain);
9930
9931         return ret;
9932 }
9933
9934 /* VESA 640x480x72Hz mode to set on the pipe */
9935 static const struct drm_display_mode load_detect_mode = {
9936         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9937                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9938 };
9939
9940 struct drm_framebuffer *
9941 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9942                          struct drm_mode_fb_cmd2 *mode_cmd)
9943 {
9944         struct intel_framebuffer *intel_fb;
9945         int ret;
9946
9947         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9948         if (!intel_fb)
9949                 return ERR_PTR(-ENOMEM);
9950
9951         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9952         if (ret)
9953                 goto err;
9954
9955         return &intel_fb->base;
9956
9957 err:
9958         kfree(intel_fb);
9959         return ERR_PTR(ret);
9960 }
9961
9962 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
9963                                         struct drm_crtc *crtc)
9964 {
9965         struct drm_plane *plane;
9966         struct drm_plane_state *plane_state;
9967         int ret, i;
9968
9969         ret = drm_atomic_add_affected_planes(state, crtc);
9970         if (ret)
9971                 return ret;
9972
9973         for_each_new_plane_in_state(state, plane, plane_state, i) {
9974                 if (plane_state->crtc != crtc)
9975                         continue;
9976
9977                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
9978                 if (ret)
9979                         return ret;
9980
9981                 drm_atomic_set_fb_for_plane(plane_state, NULL);
9982         }
9983
9984         return 0;
9985 }
9986
9987 int intel_get_load_detect_pipe(struct drm_connector *connector,
9988                                const struct drm_display_mode *mode,
9989                                struct intel_load_detect_pipe *old,
9990                                struct drm_modeset_acquire_ctx *ctx)
9991 {
9992         struct intel_crtc *intel_crtc;
9993         struct intel_encoder *intel_encoder =
9994                 intel_attached_encoder(connector);
9995         struct drm_crtc *possible_crtc;
9996         struct drm_encoder *encoder = &intel_encoder->base;
9997         struct drm_crtc *crtc = NULL;
9998         struct drm_device *dev = encoder->dev;
9999         struct drm_i915_private *dev_priv = to_i915(dev);
10000         struct drm_mode_config *config = &dev->mode_config;
10001         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10002         struct drm_connector_state *connector_state;
10003         struct intel_crtc_state *crtc_state;
10004         int ret, i = -1;
10005
10006         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10007                       connector->base.id, connector->name,
10008                       encoder->base.id, encoder->name);
10009
10010         old->restore_state = NULL;
10011
10012         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10013
10014         /*
10015          * Algorithm gets a little messy:
10016          *
10017          *   - if the connector already has an assigned crtc, use it (but make
10018          *     sure it's on first)
10019          *
10020          *   - try to find the first unused crtc that can drive this connector,
10021          *     and use that if we find one
10022          */
10023
10024         /* See if we already have a CRTC for this connector */
10025         if (connector->state->crtc) {
10026                 crtc = connector->state->crtc;
10027
10028                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10029                 if (ret)
10030                         goto fail;
10031
10032                 /* Make sure the crtc and connector are running */
10033                 goto found;
10034         }
10035
10036         /* Find an unused one (if possible) */
10037         for_each_crtc(dev, possible_crtc) {
10038                 i++;
10039                 if (!(encoder->possible_crtcs & (1 << i)))
10040                         continue;
10041
10042                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10043                 if (ret)
10044                         goto fail;
10045
10046                 if (possible_crtc->state->enable) {
10047                         drm_modeset_unlock(&possible_crtc->mutex);
10048                         continue;
10049                 }
10050
10051                 crtc = possible_crtc;
10052                 break;
10053         }
10054
10055         /*
10056          * If we didn't find an unused CRTC, don't use any.
10057          */
10058         if (!crtc) {
10059                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10060                 ret = -ENODEV;
10061                 goto fail;
10062         }
10063
10064 found:
10065         intel_crtc = to_intel_crtc(crtc);
10066
10067         state = drm_atomic_state_alloc(dev);
10068         restore_state = drm_atomic_state_alloc(dev);
10069         if (!state || !restore_state) {
10070                 ret = -ENOMEM;
10071                 goto fail;
10072         }
10073
10074         state->acquire_ctx = ctx;
10075         restore_state->acquire_ctx = ctx;
10076
10077         connector_state = drm_atomic_get_connector_state(state, connector);
10078         if (IS_ERR(connector_state)) {
10079                 ret = PTR_ERR(connector_state);
10080                 goto fail;
10081         }
10082
10083         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10084         if (ret)
10085                 goto fail;
10086
10087         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10088         if (IS_ERR(crtc_state)) {
10089                 ret = PTR_ERR(crtc_state);
10090                 goto fail;
10091         }
10092
10093         crtc_state->base.active = crtc_state->base.enable = true;
10094
10095         if (!mode)
10096                 mode = &load_detect_mode;
10097
10098         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10099         if (ret)
10100                 goto fail;
10101
10102         ret = intel_modeset_disable_planes(state, crtc);
10103         if (ret)
10104                 goto fail;
10105
10106         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10107         if (!ret)
10108                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10109         if (!ret)
10110                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10111         if (ret) {
10112                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10113                 goto fail;
10114         }
10115
10116         ret = drm_atomic_commit(state);
10117         if (ret) {
10118                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10119                 goto fail;
10120         }
10121
10122         old->restore_state = restore_state;
10123         drm_atomic_state_put(state);
10124
10125         /* let the connector get through one full cycle before testing */
10126         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10127         return true;
10128
10129 fail:
10130         if (state) {
10131                 drm_atomic_state_put(state);
10132                 state = NULL;
10133         }
10134         if (restore_state) {
10135                 drm_atomic_state_put(restore_state);
10136                 restore_state = NULL;
10137         }
10138
10139         if (ret == -EDEADLK)
10140                 return ret;
10141
10142         return false;
10143 }
10144
10145 void intel_release_load_detect_pipe(struct drm_connector *connector,
10146                                     struct intel_load_detect_pipe *old,
10147                                     struct drm_modeset_acquire_ctx *ctx)
10148 {
10149         struct intel_encoder *intel_encoder =
10150                 intel_attached_encoder(connector);
10151         struct drm_encoder *encoder = &intel_encoder->base;
10152         struct drm_atomic_state *state = old->restore_state;
10153         int ret;
10154
10155         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10156                       connector->base.id, connector->name,
10157                       encoder->base.id, encoder->name);
10158
10159         if (!state)
10160                 return;
10161
10162         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10163         if (ret)
10164                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10165         drm_atomic_state_put(state);
10166 }
10167
10168 static int i9xx_pll_refclk(struct drm_device *dev,
10169                            const struct intel_crtc_state *pipe_config)
10170 {
10171         struct drm_i915_private *dev_priv = to_i915(dev);
10172         u32 dpll = pipe_config->dpll_hw_state.dpll;
10173
10174         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10175                 return dev_priv->vbt.lvds_ssc_freq;
10176         else if (HAS_PCH_SPLIT(dev_priv))
10177                 return 120000;
10178         else if (!IS_GEN2(dev_priv))
10179                 return 96000;
10180         else
10181                 return 48000;
10182 }
10183
10184 /* Returns the clock of the currently programmed mode of the given pipe. */
10185 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10186                                 struct intel_crtc_state *pipe_config)
10187 {
10188         struct drm_device *dev = crtc->base.dev;
10189         struct drm_i915_private *dev_priv = to_i915(dev);
10190         int pipe = pipe_config->cpu_transcoder;
10191         u32 dpll = pipe_config->dpll_hw_state.dpll;
10192         u32 fp;
10193         struct dpll clock;
10194         int port_clock;
10195         int refclk = i9xx_pll_refclk(dev, pipe_config);
10196
10197         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10198                 fp = pipe_config->dpll_hw_state.fp0;
10199         else
10200                 fp = pipe_config->dpll_hw_state.fp1;
10201
10202         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10203         if (IS_PINEVIEW(dev_priv)) {
10204                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10205                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10206         } else {
10207                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10208                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10209         }
10210
10211         if (!IS_GEN2(dev_priv)) {
10212                 if (IS_PINEVIEW(dev_priv))
10213                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10214                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10215                 else
10216                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10217                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10218
10219                 switch (dpll & DPLL_MODE_MASK) {
10220                 case DPLLB_MODE_DAC_SERIAL:
10221                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10222                                 5 : 10;
10223                         break;
10224                 case DPLLB_MODE_LVDS:
10225                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10226                                 7 : 14;
10227                         break;
10228                 default:
10229                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10230                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10231                         return;
10232                 }
10233
10234                 if (IS_PINEVIEW(dev_priv))
10235                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10236                 else
10237                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10238         } else {
10239                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10240                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10241
10242                 if (is_lvds) {
10243                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10244                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10245
10246                         if (lvds & LVDS_CLKB_POWER_UP)
10247                                 clock.p2 = 7;
10248                         else
10249                                 clock.p2 = 14;
10250                 } else {
10251                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10252                                 clock.p1 = 2;
10253                         else {
10254                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10255                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10256                         }
10257                         if (dpll & PLL_P2_DIVIDE_BY_4)
10258                                 clock.p2 = 4;
10259                         else
10260                                 clock.p2 = 2;
10261                 }
10262
10263                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10264         }
10265
10266         /*
10267          * This value includes pixel_multiplier. We will use
10268          * port_clock to compute adjusted_mode.crtc_clock in the
10269          * encoder's get_config() function.
10270          */
10271         pipe_config->port_clock = port_clock;
10272 }
10273
10274 int intel_dotclock_calculate(int link_freq,
10275                              const struct intel_link_m_n *m_n)
10276 {
10277         /*
10278          * The calculation for the data clock is:
10279          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10280          * But we want to avoid losing precison if possible, so:
10281          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10282          *
10283          * and the link clock is simpler:
10284          * link_clock = (m * link_clock) / n
10285          */
10286
10287         if (!m_n->link_n)
10288                 return 0;
10289
10290         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10291 }
10292
10293 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10294                                    struct intel_crtc_state *pipe_config)
10295 {
10296         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10297
10298         /* read out port_clock from the DPLL */
10299         i9xx_crtc_clock_get(crtc, pipe_config);
10300
10301         /*
10302          * In case there is an active pipe without active ports,
10303          * we may need some idea for the dotclock anyway.
10304          * Calculate one based on the FDI configuration.
10305          */
10306         pipe_config->base.adjusted_mode.crtc_clock =
10307                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10308                                          &pipe_config->fdi_m_n);
10309 }
10310
10311 /* Returns the currently programmed mode of the given encoder. */
10312 struct drm_display_mode *
10313 intel_encoder_current_mode(struct intel_encoder *encoder)
10314 {
10315         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10316         struct intel_crtc_state *crtc_state;
10317         struct drm_display_mode *mode;
10318         struct intel_crtc *crtc;
10319         enum pipe pipe;
10320
10321         if (!encoder->get_hw_state(encoder, &pipe))
10322                 return NULL;
10323
10324         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10325
10326         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10327         if (!mode)
10328                 return NULL;
10329
10330         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10331         if (!crtc_state) {
10332                 kfree(mode);
10333                 return NULL;
10334         }
10335
10336         crtc_state->base.crtc = &crtc->base;
10337
10338         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10339                 kfree(crtc_state);
10340                 kfree(mode);
10341                 return NULL;
10342         }
10343
10344         encoder->get_config(encoder, crtc_state);
10345
10346         intel_mode_from_pipe_config(mode, crtc_state);
10347
10348         kfree(crtc_state);
10349
10350         return mode;
10351 }
10352
10353 static void intel_crtc_destroy(struct drm_crtc *crtc)
10354 {
10355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10356
10357         drm_crtc_cleanup(crtc);
10358         kfree(intel_crtc);
10359 }
10360
10361 /**
10362  * intel_wm_need_update - Check whether watermarks need updating
10363  * @plane: drm plane
10364  * @state: new plane state
10365  *
10366  * Check current plane state versus the new one to determine whether
10367  * watermarks need to be recalculated.
10368  *
10369  * Returns true or false.
10370  */
10371 static bool intel_wm_need_update(struct drm_plane *plane,
10372                                  struct drm_plane_state *state)
10373 {
10374         struct intel_plane_state *new = to_intel_plane_state(state);
10375         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10376
10377         /* Update watermarks on tiling or size changes. */
10378         if (new->base.visible != cur->base.visible)
10379                 return true;
10380
10381         if (!cur->base.fb || !new->base.fb)
10382                 return false;
10383
10384         if (cur->base.fb->modifier != new->base.fb->modifier ||
10385             cur->base.rotation != new->base.rotation ||
10386             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10387             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10388             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10389             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10390                 return true;
10391
10392         return false;
10393 }
10394
10395 static bool needs_scaling(const struct intel_plane_state *state)
10396 {
10397         int src_w = drm_rect_width(&state->base.src) >> 16;
10398         int src_h = drm_rect_height(&state->base.src) >> 16;
10399         int dst_w = drm_rect_width(&state->base.dst);
10400         int dst_h = drm_rect_height(&state->base.dst);
10401
10402         return (src_w != dst_w || src_h != dst_h);
10403 }
10404
10405 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10406                                     struct drm_crtc_state *crtc_state,
10407                                     const struct intel_plane_state *old_plane_state,
10408                                     struct drm_plane_state *plane_state)
10409 {
10410         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10411         struct drm_crtc *crtc = crtc_state->crtc;
10412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10413         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10414         struct drm_device *dev = crtc->dev;
10415         struct drm_i915_private *dev_priv = to_i915(dev);
10416         bool mode_changed = needs_modeset(crtc_state);
10417         bool was_crtc_enabled = old_crtc_state->base.active;
10418         bool is_crtc_enabled = crtc_state->active;
10419         bool turn_off, turn_on, visible, was_visible;
10420         struct drm_framebuffer *fb = plane_state->fb;
10421         int ret;
10422
10423         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10424                 ret = skl_update_scaler_plane(
10425                         to_intel_crtc_state(crtc_state),
10426                         to_intel_plane_state(plane_state));
10427                 if (ret)
10428                         return ret;
10429         }
10430
10431         was_visible = old_plane_state->base.visible;
10432         visible = plane_state->visible;
10433
10434         if (!was_crtc_enabled && WARN_ON(was_visible))
10435                 was_visible = false;
10436
10437         /*
10438          * Visibility is calculated as if the crtc was on, but
10439          * after scaler setup everything depends on it being off
10440          * when the crtc isn't active.
10441          *
10442          * FIXME this is wrong for watermarks. Watermarks should also
10443          * be computed as if the pipe would be active. Perhaps move
10444          * per-plane wm computation to the .check_plane() hook, and
10445          * only combine the results from all planes in the current place?
10446          */
10447         if (!is_crtc_enabled) {
10448                 plane_state->visible = visible = false;
10449                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10450         }
10451
10452         if (!was_visible && !visible)
10453                 return 0;
10454
10455         if (fb != old_plane_state->base.fb)
10456                 pipe_config->fb_changed = true;
10457
10458         turn_off = was_visible && (!visible || mode_changed);
10459         turn_on = visible && (!was_visible || mode_changed);
10460
10461         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10462                          intel_crtc->base.base.id, intel_crtc->base.name,
10463                          plane->base.base.id, plane->base.name,
10464                          fb ? fb->base.id : -1);
10465
10466         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10467                          plane->base.base.id, plane->base.name,
10468                          was_visible, visible,
10469                          turn_off, turn_on, mode_changed);
10470
10471         if (turn_on) {
10472                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10473                         pipe_config->update_wm_pre = true;
10474
10475                 /* must disable cxsr around plane enable/disable */
10476                 if (plane->id != PLANE_CURSOR)
10477                         pipe_config->disable_cxsr = true;
10478         } else if (turn_off) {
10479                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10480                         pipe_config->update_wm_post = true;
10481
10482                 /* must disable cxsr around plane enable/disable */
10483                 if (plane->id != PLANE_CURSOR)
10484                         pipe_config->disable_cxsr = true;
10485         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10486                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10487                         /* FIXME bollocks */
10488                         pipe_config->update_wm_pre = true;
10489                         pipe_config->update_wm_post = true;
10490                 }
10491         }
10492
10493         if (visible || was_visible)
10494                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10495
10496         /*
10497          * WaCxSRDisabledForSpriteScaling:ivb
10498          *
10499          * cstate->update_wm was already set above, so this flag will
10500          * take effect when we commit and program watermarks.
10501          */
10502         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10503             needs_scaling(to_intel_plane_state(plane_state)) &&
10504             !needs_scaling(old_plane_state))
10505                 pipe_config->disable_lp_wm = true;
10506
10507         return 0;
10508 }
10509
10510 static bool encoders_cloneable(const struct intel_encoder *a,
10511                                const struct intel_encoder *b)
10512 {
10513         /* masks could be asymmetric, so check both ways */
10514         return a == b || (a->cloneable & (1 << b->type) &&
10515                           b->cloneable & (1 << a->type));
10516 }
10517
10518 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10519                                          struct intel_crtc *crtc,
10520                                          struct intel_encoder *encoder)
10521 {
10522         struct intel_encoder *source_encoder;
10523         struct drm_connector *connector;
10524         struct drm_connector_state *connector_state;
10525         int i;
10526
10527         for_each_new_connector_in_state(state, connector, connector_state, i) {
10528                 if (connector_state->crtc != &crtc->base)
10529                         continue;
10530
10531                 source_encoder =
10532                         to_intel_encoder(connector_state->best_encoder);
10533                 if (!encoders_cloneable(encoder, source_encoder))
10534                         return false;
10535         }
10536
10537         return true;
10538 }
10539
10540 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10541                                    struct drm_crtc_state *crtc_state)
10542 {
10543         struct drm_device *dev = crtc->dev;
10544         struct drm_i915_private *dev_priv = to_i915(dev);
10545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10546         struct intel_crtc_state *pipe_config =
10547                 to_intel_crtc_state(crtc_state);
10548         struct drm_atomic_state *state = crtc_state->state;
10549         int ret;
10550         bool mode_changed = needs_modeset(crtc_state);
10551
10552         if (mode_changed && !crtc_state->active)
10553                 pipe_config->update_wm_post = true;
10554
10555         if (mode_changed && crtc_state->enable &&
10556             dev_priv->display.crtc_compute_clock &&
10557             !WARN_ON(pipe_config->shared_dpll)) {
10558                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10559                                                            pipe_config);
10560                 if (ret)
10561                         return ret;
10562         }
10563
10564         if (crtc_state->color_mgmt_changed) {
10565                 ret = intel_color_check(crtc, crtc_state);
10566                 if (ret)
10567                         return ret;
10568
10569                 /*
10570                  * Changing color management on Intel hardware is
10571                  * handled as part of planes update.
10572                  */
10573                 crtc_state->planes_changed = true;
10574         }
10575
10576         ret = 0;
10577         if (dev_priv->display.compute_pipe_wm) {
10578                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10579                 if (ret) {
10580                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10581                         return ret;
10582                 }
10583         }
10584
10585         if (dev_priv->display.compute_intermediate_wm &&
10586             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10587                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10588                         return 0;
10589
10590                 /*
10591                  * Calculate 'intermediate' watermarks that satisfy both the
10592                  * old state and the new state.  We can program these
10593                  * immediately.
10594                  */
10595                 ret = dev_priv->display.compute_intermediate_wm(dev,
10596                                                                 intel_crtc,
10597                                                                 pipe_config);
10598                 if (ret) {
10599                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10600                         return ret;
10601                 }
10602         } else if (dev_priv->display.compute_intermediate_wm) {
10603                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10604                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10605         }
10606
10607         if (INTEL_GEN(dev_priv) >= 9) {
10608                 if (mode_changed)
10609                         ret = skl_update_scaler_crtc(pipe_config);
10610
10611                 if (!ret)
10612                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10613                                                             pipe_config);
10614                 if (!ret)
10615                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10616                                                          pipe_config);
10617         }
10618
10619         if (HAS_IPS(dev_priv))
10620                 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
10621
10622         return ret;
10623 }
10624
10625 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10626         .atomic_begin = intel_begin_crtc_commit,
10627         .atomic_flush = intel_finish_crtc_commit,
10628         .atomic_check = intel_crtc_atomic_check,
10629 };
10630
10631 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10632 {
10633         struct intel_connector *connector;
10634         struct drm_connector_list_iter conn_iter;
10635
10636         drm_connector_list_iter_begin(dev, &conn_iter);
10637         for_each_intel_connector_iter(connector, &conn_iter) {
10638                 if (connector->base.state->crtc)
10639                         drm_connector_unreference(&connector->base);
10640
10641                 if (connector->base.encoder) {
10642                         connector->base.state->best_encoder =
10643                                 connector->base.encoder;
10644                         connector->base.state->crtc =
10645                                 connector->base.encoder->crtc;
10646
10647                         drm_connector_reference(&connector->base);
10648                 } else {
10649                         connector->base.state->best_encoder = NULL;
10650                         connector->base.state->crtc = NULL;
10651                 }
10652         }
10653         drm_connector_list_iter_end(&conn_iter);
10654 }
10655
10656 static void
10657 connected_sink_compute_bpp(struct intel_connector *connector,
10658                            struct intel_crtc_state *pipe_config)
10659 {
10660         const struct drm_display_info *info = &connector->base.display_info;
10661         int bpp = pipe_config->pipe_bpp;
10662
10663         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10664                       connector->base.base.id,
10665                       connector->base.name);
10666
10667         /* Don't use an invalid EDID bpc value */
10668         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10669                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10670                               bpp, info->bpc * 3);
10671                 pipe_config->pipe_bpp = info->bpc * 3;
10672         }
10673
10674         /* Clamp bpp to 8 on screens without EDID 1.4 */
10675         if (info->bpc == 0 && bpp > 24) {
10676                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10677                               bpp);
10678                 pipe_config->pipe_bpp = 24;
10679         }
10680 }
10681
10682 static int
10683 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10684                           struct intel_crtc_state *pipe_config)
10685 {
10686         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10687         struct drm_atomic_state *state;
10688         struct drm_connector *connector;
10689         struct drm_connector_state *connector_state;
10690         int bpp, i;
10691
10692         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10693             IS_CHERRYVIEW(dev_priv)))
10694                 bpp = 10*3;
10695         else if (INTEL_GEN(dev_priv) >= 5)
10696                 bpp = 12*3;
10697         else
10698                 bpp = 8*3;
10699
10700
10701         pipe_config->pipe_bpp = bpp;
10702
10703         state = pipe_config->base.state;
10704
10705         /* Clamp display bpp to EDID value */
10706         for_each_new_connector_in_state(state, connector, connector_state, i) {
10707                 if (connector_state->crtc != &crtc->base)
10708                         continue;
10709
10710                 connected_sink_compute_bpp(to_intel_connector(connector),
10711                                            pipe_config);
10712         }
10713
10714         return bpp;
10715 }
10716
10717 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10718 {
10719         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10720                         "type: 0x%x flags: 0x%x\n",
10721                 mode->crtc_clock,
10722                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10723                 mode->crtc_hsync_end, mode->crtc_htotal,
10724                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10725                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10726 }
10727
10728 static inline void
10729 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10730                       unsigned int lane_count, struct intel_link_m_n *m_n)
10731 {
10732         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10733                       id, lane_count,
10734                       m_n->gmch_m, m_n->gmch_n,
10735                       m_n->link_m, m_n->link_n, m_n->tu);
10736 }
10737
10738 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10739
10740 static const char * const output_type_str[] = {
10741         OUTPUT_TYPE(UNUSED),
10742         OUTPUT_TYPE(ANALOG),
10743         OUTPUT_TYPE(DVO),
10744         OUTPUT_TYPE(SDVO),
10745         OUTPUT_TYPE(LVDS),
10746         OUTPUT_TYPE(TVOUT),
10747         OUTPUT_TYPE(HDMI),
10748         OUTPUT_TYPE(DP),
10749         OUTPUT_TYPE(EDP),
10750         OUTPUT_TYPE(DSI),
10751         OUTPUT_TYPE(DDI),
10752         OUTPUT_TYPE(DP_MST),
10753 };
10754
10755 #undef OUTPUT_TYPE
10756
10757 static void snprintf_output_types(char *buf, size_t len,
10758                                   unsigned int output_types)
10759 {
10760         char *str = buf;
10761         int i;
10762
10763         str[0] = '\0';
10764
10765         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10766                 int r;
10767
10768                 if ((output_types & BIT(i)) == 0)
10769                         continue;
10770
10771                 r = snprintf(str, len, "%s%s",
10772                              str != buf ? "," : "", output_type_str[i]);
10773                 if (r >= len)
10774                         break;
10775                 str += r;
10776                 len -= r;
10777
10778                 output_types &= ~BIT(i);
10779         }
10780
10781         WARN_ON_ONCE(output_types != 0);
10782 }
10783
10784 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10785                                    struct intel_crtc_state *pipe_config,
10786                                    const char *context)
10787 {
10788         struct drm_device *dev = crtc->base.dev;
10789         struct drm_i915_private *dev_priv = to_i915(dev);
10790         struct drm_plane *plane;
10791         struct intel_plane *intel_plane;
10792         struct intel_plane_state *state;
10793         struct drm_framebuffer *fb;
10794         char buf[64];
10795
10796         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10797                       crtc->base.base.id, crtc->base.name, context);
10798
10799         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10800         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10801                       buf, pipe_config->output_types);
10802
10803         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10804                       transcoder_name(pipe_config->cpu_transcoder),
10805                       pipe_config->pipe_bpp, pipe_config->dither);
10806
10807         if (pipe_config->has_pch_encoder)
10808                 intel_dump_m_n_config(pipe_config, "fdi",
10809                                       pipe_config->fdi_lanes,
10810                                       &pipe_config->fdi_m_n);
10811
10812         if (pipe_config->ycbcr420)
10813                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10814
10815         if (intel_crtc_has_dp_encoder(pipe_config)) {
10816                 intel_dump_m_n_config(pipe_config, "dp m_n",
10817                                 pipe_config->lane_count, &pipe_config->dp_m_n);
10818                 if (pipe_config->has_drrs)
10819                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
10820                                               pipe_config->lane_count,
10821                                               &pipe_config->dp_m2_n2);
10822         }
10823
10824         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10825                       pipe_config->has_audio, pipe_config->has_infoframe);
10826
10827         DRM_DEBUG_KMS("requested mode:\n");
10828         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10829         DRM_DEBUG_KMS("adjusted mode:\n");
10830         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10831         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10832         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10833                       pipe_config->port_clock,
10834                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10835                       pipe_config->pixel_rate);
10836
10837         if (INTEL_GEN(dev_priv) >= 9)
10838                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10839                               crtc->num_scalers,
10840                               pipe_config->scaler_state.scaler_users,
10841                               pipe_config->scaler_state.scaler_id);
10842
10843         if (HAS_GMCH_DISPLAY(dev_priv))
10844                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10845                               pipe_config->gmch_pfit.control,
10846                               pipe_config->gmch_pfit.pgm_ratios,
10847                               pipe_config->gmch_pfit.lvds_border_bits);
10848         else
10849                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10850                               pipe_config->pch_pfit.pos,
10851                               pipe_config->pch_pfit.size,
10852                               enableddisabled(pipe_config->pch_pfit.enabled));
10853
10854         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10855                       pipe_config->ips_enabled, pipe_config->double_wide);
10856
10857         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10858
10859         DRM_DEBUG_KMS("planes on this crtc\n");
10860         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10861                 struct drm_format_name_buf format_name;
10862                 intel_plane = to_intel_plane(plane);
10863                 if (intel_plane->pipe != crtc->pipe)
10864                         continue;
10865
10866                 state = to_intel_plane_state(plane->state);
10867                 fb = state->base.fb;
10868                 if (!fb) {
10869                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10870                                       plane->base.id, plane->name, state->scaler_id);
10871                         continue;
10872                 }
10873
10874                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10875                               plane->base.id, plane->name,
10876                               fb->base.id, fb->width, fb->height,
10877                               drm_get_format_name(fb->format->format, &format_name));
10878                 if (INTEL_GEN(dev_priv) >= 9)
10879                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10880                                       state->scaler_id,
10881                                       state->base.src.x1 >> 16,
10882                                       state->base.src.y1 >> 16,
10883                                       drm_rect_width(&state->base.src) >> 16,
10884                                       drm_rect_height(&state->base.src) >> 16,
10885                                       state->base.dst.x1, state->base.dst.y1,
10886                                       drm_rect_width(&state->base.dst),
10887                                       drm_rect_height(&state->base.dst));
10888         }
10889 }
10890
10891 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10892 {
10893         struct drm_device *dev = state->dev;
10894         struct drm_connector *connector;
10895         struct drm_connector_list_iter conn_iter;
10896         unsigned int used_ports = 0;
10897         unsigned int used_mst_ports = 0;
10898         bool ret = true;
10899
10900         /*
10901          * Walk the connector list instead of the encoder
10902          * list to detect the problem on ddi platforms
10903          * where there's just one encoder per digital port.
10904          */
10905         drm_connector_list_iter_begin(dev, &conn_iter);
10906         drm_for_each_connector_iter(connector, &conn_iter) {
10907                 struct drm_connector_state *connector_state;
10908                 struct intel_encoder *encoder;
10909
10910                 connector_state = drm_atomic_get_new_connector_state(state, connector);
10911                 if (!connector_state)
10912                         connector_state = connector->state;
10913
10914                 if (!connector_state->best_encoder)
10915                         continue;
10916
10917                 encoder = to_intel_encoder(connector_state->best_encoder);
10918
10919                 WARN_ON(!connector_state->crtc);
10920
10921                 switch (encoder->type) {
10922                         unsigned int port_mask;
10923                 case INTEL_OUTPUT_DDI:
10924                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
10925                                 break;
10926                 case INTEL_OUTPUT_DP:
10927                 case INTEL_OUTPUT_HDMI:
10928                 case INTEL_OUTPUT_EDP:
10929                         port_mask = 1 << encoder->port;
10930
10931                         /* the same port mustn't appear more than once */
10932                         if (used_ports & port_mask)
10933                                 ret = false;
10934
10935                         used_ports |= port_mask;
10936                         break;
10937                 case INTEL_OUTPUT_DP_MST:
10938                         used_mst_ports |=
10939                                 1 << encoder->port;
10940                         break;
10941                 default:
10942                         break;
10943                 }
10944         }
10945         drm_connector_list_iter_end(&conn_iter);
10946
10947         /* can't mix MST and SST/HDMI on the same port */
10948         if (used_ports & used_mst_ports)
10949                 return false;
10950
10951         return ret;
10952 }
10953
10954 static void
10955 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10956 {
10957         struct drm_i915_private *dev_priv =
10958                 to_i915(crtc_state->base.crtc->dev);
10959         struct intel_crtc_scaler_state scaler_state;
10960         struct intel_dpll_hw_state dpll_hw_state;
10961         struct intel_shared_dpll *shared_dpll;
10962         struct intel_crtc_wm_state wm_state;
10963         bool force_thru, ips_force_disable;
10964
10965         /* FIXME: before the switch to atomic started, a new pipe_config was
10966          * kzalloc'd. Code that depends on any field being zero should be
10967          * fixed, so that the crtc_state can be safely duplicated. For now,
10968          * only fields that are know to not cause problems are preserved. */
10969
10970         scaler_state = crtc_state->scaler_state;
10971         shared_dpll = crtc_state->shared_dpll;
10972         dpll_hw_state = crtc_state->dpll_hw_state;
10973         force_thru = crtc_state->pch_pfit.force_thru;
10974         ips_force_disable = crtc_state->ips_force_disable;
10975         if (IS_G4X(dev_priv) ||
10976             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10977                 wm_state = crtc_state->wm;
10978
10979         /* Keep base drm_crtc_state intact, only clear our extended struct */
10980         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10981         memset(&crtc_state->base + 1, 0,
10982                sizeof(*crtc_state) - sizeof(crtc_state->base));
10983
10984         crtc_state->scaler_state = scaler_state;
10985         crtc_state->shared_dpll = shared_dpll;
10986         crtc_state->dpll_hw_state = dpll_hw_state;
10987         crtc_state->pch_pfit.force_thru = force_thru;
10988         crtc_state->ips_force_disable = ips_force_disable;
10989         if (IS_G4X(dev_priv) ||
10990             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10991                 crtc_state->wm = wm_state;
10992 }
10993
10994 static int
10995 intel_modeset_pipe_config(struct drm_crtc *crtc,
10996                           struct intel_crtc_state *pipe_config)
10997 {
10998         struct drm_atomic_state *state = pipe_config->base.state;
10999         struct intel_encoder *encoder;
11000         struct drm_connector *connector;
11001         struct drm_connector_state *connector_state;
11002         int base_bpp, ret = -EINVAL;
11003         int i;
11004         bool retry = true;
11005
11006         clear_intel_crtc_state(pipe_config);
11007
11008         pipe_config->cpu_transcoder =
11009                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11010
11011         /*
11012          * Sanitize sync polarity flags based on requested ones. If neither
11013          * positive or negative polarity is requested, treat this as meaning
11014          * negative polarity.
11015          */
11016         if (!(pipe_config->base.adjusted_mode.flags &
11017               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11018                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11019
11020         if (!(pipe_config->base.adjusted_mode.flags &
11021               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11022                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11023
11024         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11025                                              pipe_config);
11026         if (base_bpp < 0)
11027                 goto fail;
11028
11029         /*
11030          * Determine the real pipe dimensions. Note that stereo modes can
11031          * increase the actual pipe size due to the frame doubling and
11032          * insertion of additional space for blanks between the frame. This
11033          * is stored in the crtc timings. We use the requested mode to do this
11034          * computation to clearly distinguish it from the adjusted mode, which
11035          * can be changed by the connectors in the below retry loop.
11036          */
11037         drm_mode_get_hv_timing(&pipe_config->base.mode,
11038                                &pipe_config->pipe_src_w,
11039                                &pipe_config->pipe_src_h);
11040
11041         for_each_new_connector_in_state(state, connector, connector_state, i) {
11042                 if (connector_state->crtc != crtc)
11043                         continue;
11044
11045                 encoder = to_intel_encoder(connector_state->best_encoder);
11046
11047                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11048                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11049                         goto fail;
11050                 }
11051
11052                 /*
11053                  * Determine output_types before calling the .compute_config()
11054                  * hooks so that the hooks can use this information safely.
11055                  */
11056                 if (encoder->compute_output_type)
11057                         pipe_config->output_types |=
11058                                 BIT(encoder->compute_output_type(encoder, pipe_config,
11059                                                                  connector_state));
11060                 else
11061                         pipe_config->output_types |= BIT(encoder->type);
11062         }
11063
11064 encoder_retry:
11065         /* Ensure the port clock defaults are reset when retrying. */
11066         pipe_config->port_clock = 0;
11067         pipe_config->pixel_multiplier = 1;
11068
11069         /* Fill in default crtc timings, allow encoders to overwrite them. */
11070         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11071                               CRTC_STEREO_DOUBLE);
11072
11073         /* Pass our mode to the connectors and the CRTC to give them a chance to
11074          * adjust it according to limitations or connector properties, and also
11075          * a chance to reject the mode entirely.
11076          */
11077         for_each_new_connector_in_state(state, connector, connector_state, i) {
11078                 if (connector_state->crtc != crtc)
11079                         continue;
11080
11081                 encoder = to_intel_encoder(connector_state->best_encoder);
11082
11083                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11084                         DRM_DEBUG_KMS("Encoder config failure\n");
11085                         goto fail;
11086                 }
11087         }
11088
11089         /* Set default port clock if not overwritten by the encoder. Needs to be
11090          * done afterwards in case the encoder adjusts the mode. */
11091         if (!pipe_config->port_clock)
11092                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11093                         * pipe_config->pixel_multiplier;
11094
11095         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11096         if (ret < 0) {
11097                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11098                 goto fail;
11099         }
11100
11101         if (ret == RETRY) {
11102                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11103                         ret = -EINVAL;
11104                         goto fail;
11105                 }
11106
11107                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11108                 retry = false;
11109                 goto encoder_retry;
11110         }
11111
11112         /* Dithering seems to not pass-through bits correctly when it should, so
11113          * only enable it on 6bpc panels and when its not a compliance
11114          * test requesting 6bpc video pattern.
11115          */
11116         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11117                 !pipe_config->dither_force_disable;
11118         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11119                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11120
11121 fail:
11122         return ret;
11123 }
11124
11125 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11126 {
11127         int diff;
11128
11129         if (clock1 == clock2)
11130                 return true;
11131
11132         if (!clock1 || !clock2)
11133                 return false;
11134
11135         diff = abs(clock1 - clock2);
11136
11137         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11138                 return true;
11139
11140         return false;
11141 }
11142
11143 static bool
11144 intel_compare_m_n(unsigned int m, unsigned int n,
11145                   unsigned int m2, unsigned int n2,
11146                   bool exact)
11147 {
11148         if (m == m2 && n == n2)
11149                 return true;
11150
11151         if (exact || !m || !n || !m2 || !n2)
11152                 return false;
11153
11154         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11155
11156         if (n > n2) {
11157                 while (n > n2) {
11158                         m2 <<= 1;
11159                         n2 <<= 1;
11160                 }
11161         } else if (n < n2) {
11162                 while (n < n2) {
11163                         m <<= 1;
11164                         n <<= 1;
11165                 }
11166         }
11167
11168         if (n != n2)
11169                 return false;
11170
11171         return intel_fuzzy_clock_check(m, m2);
11172 }
11173
11174 static bool
11175 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11176                        struct intel_link_m_n *m2_n2,
11177                        bool adjust)
11178 {
11179         if (m_n->tu == m2_n2->tu &&
11180             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11181                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11182             intel_compare_m_n(m_n->link_m, m_n->link_n,
11183                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11184                 if (adjust)
11185                         *m2_n2 = *m_n;
11186
11187                 return true;
11188         }
11189
11190         return false;
11191 }
11192
11193 static void __printf(3, 4)
11194 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11195 {
11196         struct va_format vaf;
11197         va_list args;
11198
11199         va_start(args, format);
11200         vaf.fmt = format;
11201         vaf.va = &args;
11202
11203         if (adjust)
11204                 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11205         else
11206                 drm_err("mismatch in %s %pV", name, &vaf);
11207
11208         va_end(args);
11209 }
11210
11211 static bool
11212 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11213                           struct intel_crtc_state *current_config,
11214                           struct intel_crtc_state *pipe_config,
11215                           bool adjust)
11216 {
11217         bool ret = true;
11218         bool fixup_inherited = adjust &&
11219                 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11220                 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11221
11222 #define PIPE_CONF_CHECK_X(name) do { \
11223         if (current_config->name != pipe_config->name) { \
11224                 pipe_config_err(adjust, __stringify(name), \
11225                           "(expected 0x%08x, found 0x%08x)\n", \
11226                           current_config->name, \
11227                           pipe_config->name); \
11228                 ret = false; \
11229         } \
11230 } while (0)
11231
11232 #define PIPE_CONF_CHECK_I(name) do { \
11233         if (current_config->name != pipe_config->name) { \
11234                 pipe_config_err(adjust, __stringify(name), \
11235                           "(expected %i, found %i)\n", \
11236                           current_config->name, \
11237                           pipe_config->name); \
11238                 ret = false; \
11239         } \
11240 } while (0)
11241
11242 #define PIPE_CONF_CHECK_BOOL(name) do { \
11243         if (current_config->name != pipe_config->name) { \
11244                 pipe_config_err(adjust, __stringify(name), \
11245                           "(expected %s, found %s)\n", \
11246                           yesno(current_config->name), \
11247                           yesno(pipe_config->name)); \
11248                 ret = false; \
11249         } \
11250 } while (0)
11251
11252 /*
11253  * Checks state where we only read out the enabling, but not the entire
11254  * state itself (like full infoframes or ELD for audio). These states
11255  * require a full modeset on bootup to fix up.
11256  */
11257 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
11258         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11259                 PIPE_CONF_CHECK_BOOL(name); \
11260         } else { \
11261                 pipe_config_err(adjust, __stringify(name), \
11262                           "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11263                           yesno(current_config->name), \
11264                           yesno(pipe_config->name)); \
11265                 ret = false; \
11266         } \
11267 } while (0)
11268
11269 #define PIPE_CONF_CHECK_P(name) do { \
11270         if (current_config->name != pipe_config->name) { \
11271                 pipe_config_err(adjust, __stringify(name), \
11272                           "(expected %p, found %p)\n", \
11273                           current_config->name, \
11274                           pipe_config->name); \
11275                 ret = false; \
11276         } \
11277 } while (0)
11278
11279 #define PIPE_CONF_CHECK_M_N(name) do { \
11280         if (!intel_compare_link_m_n(&current_config->name, \
11281                                     &pipe_config->name,\
11282                                     adjust)) { \
11283                 pipe_config_err(adjust, __stringify(name), \
11284                           "(expected tu %i gmch %i/%i link %i/%i, " \
11285                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11286                           current_config->name.tu, \
11287                           current_config->name.gmch_m, \
11288                           current_config->name.gmch_n, \
11289                           current_config->name.link_m, \
11290                           current_config->name.link_n, \
11291                           pipe_config->name.tu, \
11292                           pipe_config->name.gmch_m, \
11293                           pipe_config->name.gmch_n, \
11294                           pipe_config->name.link_m, \
11295                           pipe_config->name.link_n); \
11296                 ret = false; \
11297         } \
11298 } while (0)
11299
11300 /* This is required for BDW+ where there is only one set of registers for
11301  * switching between high and low RR.
11302  * This macro can be used whenever a comparison has to be made between one
11303  * hw state and multiple sw state variables.
11304  */
11305 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
11306         if (!intel_compare_link_m_n(&current_config->name, \
11307                                     &pipe_config->name, adjust) && \
11308             !intel_compare_link_m_n(&current_config->alt_name, \
11309                                     &pipe_config->name, adjust)) { \
11310                 pipe_config_err(adjust, __stringify(name), \
11311                           "(expected tu %i gmch %i/%i link %i/%i, " \
11312                           "or tu %i gmch %i/%i link %i/%i, " \
11313                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11314                           current_config->name.tu, \
11315                           current_config->name.gmch_m, \
11316                           current_config->name.gmch_n, \
11317                           current_config->name.link_m, \
11318                           current_config->name.link_n, \
11319                           current_config->alt_name.tu, \
11320                           current_config->alt_name.gmch_m, \
11321                           current_config->alt_name.gmch_n, \
11322                           current_config->alt_name.link_m, \
11323                           current_config->alt_name.link_n, \
11324                           pipe_config->name.tu, \
11325                           pipe_config->name.gmch_m, \
11326                           pipe_config->name.gmch_n, \
11327                           pipe_config->name.link_m, \
11328                           pipe_config->name.link_n); \
11329                 ret = false; \
11330         } \
11331 } while (0)
11332
11333 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
11334         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11335                 pipe_config_err(adjust, __stringify(name), \
11336                           "(%x) (expected %i, found %i)\n", \
11337                           (mask), \
11338                           current_config->name & (mask), \
11339                           pipe_config->name & (mask)); \
11340                 ret = false; \
11341         } \
11342 } while (0)
11343
11344 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
11345         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11346                 pipe_config_err(adjust, __stringify(name), \
11347                           "(expected %i, found %i)\n", \
11348                           current_config->name, \
11349                           pipe_config->name); \
11350                 ret = false; \
11351         } \
11352 } while (0)
11353
11354 #define PIPE_CONF_QUIRK(quirk)  \
11355         ((current_config->quirks | pipe_config->quirks) & (quirk))
11356
11357         PIPE_CONF_CHECK_I(cpu_transcoder);
11358
11359         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11360         PIPE_CONF_CHECK_I(fdi_lanes);
11361         PIPE_CONF_CHECK_M_N(fdi_m_n);
11362
11363         PIPE_CONF_CHECK_I(lane_count);
11364         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11365
11366         if (INTEL_GEN(dev_priv) < 8) {
11367                 PIPE_CONF_CHECK_M_N(dp_m_n);
11368
11369                 if (current_config->has_drrs)
11370                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11371         } else
11372                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11373
11374         PIPE_CONF_CHECK_X(output_types);
11375
11376         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11377         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11378         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11379         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11380         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11381         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11382
11383         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11384         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11385         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11386         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11387         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11388         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11389
11390         PIPE_CONF_CHECK_I(pixel_multiplier);
11391         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11392         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11393             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11394                 PIPE_CONF_CHECK_BOOL(limited_color_range);
11395
11396         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11397         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11398         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11399         PIPE_CONF_CHECK_BOOL(ycbcr420);
11400
11401         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11402
11403         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11404                               DRM_MODE_FLAG_INTERLACE);
11405
11406         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11407                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11408                                       DRM_MODE_FLAG_PHSYNC);
11409                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11410                                       DRM_MODE_FLAG_NHSYNC);
11411                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11412                                       DRM_MODE_FLAG_PVSYNC);
11413                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11414                                       DRM_MODE_FLAG_NVSYNC);
11415         }
11416
11417         PIPE_CONF_CHECK_X(gmch_pfit.control);
11418         /* pfit ratios are autocomputed by the hw on gen4+ */
11419         if (INTEL_GEN(dev_priv) < 4)
11420                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11421         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11422
11423         if (!adjust) {
11424                 PIPE_CONF_CHECK_I(pipe_src_w);
11425                 PIPE_CONF_CHECK_I(pipe_src_h);
11426
11427                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11428                 if (current_config->pch_pfit.enabled) {
11429                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11430                         PIPE_CONF_CHECK_X(pch_pfit.size);
11431                 }
11432
11433                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11434                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11435         }
11436
11437         PIPE_CONF_CHECK_BOOL(double_wide);
11438
11439         PIPE_CONF_CHECK_P(shared_dpll);
11440         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11441         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11442         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11443         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11444         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11445         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11446         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11447         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11448         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11449         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11450         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11451         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11452         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11453         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11454         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11455         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11456         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11457         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11458         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11459         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11460         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11461         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
11462         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
11463         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
11464         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
11465         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
11466         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
11467         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
11468         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
11469         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
11470         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
11471
11472         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11473         PIPE_CONF_CHECK_X(dsi_pll.div);
11474
11475         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11476                 PIPE_CONF_CHECK_I(pipe_bpp);
11477
11478         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11479         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11480
11481         PIPE_CONF_CHECK_I(min_voltage_level);
11482
11483 #undef PIPE_CONF_CHECK_X
11484 #undef PIPE_CONF_CHECK_I
11485 #undef PIPE_CONF_CHECK_BOOL
11486 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11487 #undef PIPE_CONF_CHECK_P
11488 #undef PIPE_CONF_CHECK_FLAGS
11489 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11490 #undef PIPE_CONF_QUIRK
11491
11492         return ret;
11493 }
11494
11495 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11496                                            const struct intel_crtc_state *pipe_config)
11497 {
11498         if (pipe_config->has_pch_encoder) {
11499                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11500                                                             &pipe_config->fdi_m_n);
11501                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11502
11503                 /*
11504                  * FDI already provided one idea for the dotclock.
11505                  * Yell if the encoder disagrees.
11506                  */
11507                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11508                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11509                      fdi_dotclock, dotclock);
11510         }
11511 }
11512
11513 static void verify_wm_state(struct drm_crtc *crtc,
11514                             struct drm_crtc_state *new_state)
11515 {
11516         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11517         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11518         struct skl_pipe_wm hw_wm, *sw_wm;
11519         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11520         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11522         const enum pipe pipe = intel_crtc->pipe;
11523         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11524
11525         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11526                 return;
11527
11528         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11529         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11530
11531         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11532         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11533
11534         if (INTEL_GEN(dev_priv) >= 11)
11535                 if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
11536                         DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
11537                                   sw_ddb->enabled_slices,
11538                                   hw_ddb.enabled_slices);
11539         /* planes */
11540         for_each_universal_plane(dev_priv, pipe, plane) {
11541                 hw_plane_wm = &hw_wm.planes[plane];
11542                 sw_plane_wm = &sw_wm->planes[plane];
11543
11544                 /* Watermarks */
11545                 for (level = 0; level <= max_level; level++) {
11546                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11547                                                 &sw_plane_wm->wm[level]))
11548                                 continue;
11549
11550                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11551                                   pipe_name(pipe), plane + 1, level,
11552                                   sw_plane_wm->wm[level].plane_en,
11553                                   sw_plane_wm->wm[level].plane_res_b,
11554                                   sw_plane_wm->wm[level].plane_res_l,
11555                                   hw_plane_wm->wm[level].plane_en,
11556                                   hw_plane_wm->wm[level].plane_res_b,
11557                                   hw_plane_wm->wm[level].plane_res_l);
11558                 }
11559
11560                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11561                                          &sw_plane_wm->trans_wm)) {
11562                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11563                                   pipe_name(pipe), plane + 1,
11564                                   sw_plane_wm->trans_wm.plane_en,
11565                                   sw_plane_wm->trans_wm.plane_res_b,
11566                                   sw_plane_wm->trans_wm.plane_res_l,
11567                                   hw_plane_wm->trans_wm.plane_en,
11568                                   hw_plane_wm->trans_wm.plane_res_b,
11569                                   hw_plane_wm->trans_wm.plane_res_l);
11570                 }
11571
11572                 /* DDB */
11573                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11574                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11575
11576                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11577                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11578                                   pipe_name(pipe), plane + 1,
11579                                   sw_ddb_entry->start, sw_ddb_entry->end,
11580                                   hw_ddb_entry->start, hw_ddb_entry->end);
11581                 }
11582         }
11583
11584         /*
11585          * cursor
11586          * If the cursor plane isn't active, we may not have updated it's ddb
11587          * allocation. In that case since the ddb allocation will be updated
11588          * once the plane becomes visible, we can skip this check
11589          */
11590         if (1) {
11591                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11592                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11593
11594                 /* Watermarks */
11595                 for (level = 0; level <= max_level; level++) {
11596                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11597                                                 &sw_plane_wm->wm[level]))
11598                                 continue;
11599
11600                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11601                                   pipe_name(pipe), level,
11602                                   sw_plane_wm->wm[level].plane_en,
11603                                   sw_plane_wm->wm[level].plane_res_b,
11604                                   sw_plane_wm->wm[level].plane_res_l,
11605                                   hw_plane_wm->wm[level].plane_en,
11606                                   hw_plane_wm->wm[level].plane_res_b,
11607                                   hw_plane_wm->wm[level].plane_res_l);
11608                 }
11609
11610                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11611                                          &sw_plane_wm->trans_wm)) {
11612                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11613                                   pipe_name(pipe),
11614                                   sw_plane_wm->trans_wm.plane_en,
11615                                   sw_plane_wm->trans_wm.plane_res_b,
11616                                   sw_plane_wm->trans_wm.plane_res_l,
11617                                   hw_plane_wm->trans_wm.plane_en,
11618                                   hw_plane_wm->trans_wm.plane_res_b,
11619                                   hw_plane_wm->trans_wm.plane_res_l);
11620                 }
11621
11622                 /* DDB */
11623                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11624                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11625
11626                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11627                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11628                                   pipe_name(pipe),
11629                                   sw_ddb_entry->start, sw_ddb_entry->end,
11630                                   hw_ddb_entry->start, hw_ddb_entry->end);
11631                 }
11632         }
11633 }
11634
11635 static void
11636 verify_connector_state(struct drm_device *dev,
11637                        struct drm_atomic_state *state,
11638                        struct drm_crtc *crtc)
11639 {
11640         struct drm_connector *connector;
11641         struct drm_connector_state *new_conn_state;
11642         int i;
11643
11644         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11645                 struct drm_encoder *encoder = connector->encoder;
11646                 struct drm_crtc_state *crtc_state = NULL;
11647
11648                 if (new_conn_state->crtc != crtc)
11649                         continue;
11650
11651                 if (crtc)
11652                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11653
11654                 intel_connector_verify_state(crtc_state, new_conn_state);
11655
11656                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11657                      "connector's atomic encoder doesn't match legacy encoder\n");
11658         }
11659 }
11660
11661 static void
11662 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11663 {
11664         struct intel_encoder *encoder;
11665         struct drm_connector *connector;
11666         struct drm_connector_state *old_conn_state, *new_conn_state;
11667         int i;
11668
11669         for_each_intel_encoder(dev, encoder) {
11670                 bool enabled = false, found = false;
11671                 enum pipe pipe;
11672
11673                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11674                               encoder->base.base.id,
11675                               encoder->base.name);
11676
11677                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11678                                                    new_conn_state, i) {
11679                         if (old_conn_state->best_encoder == &encoder->base)
11680                                 found = true;
11681
11682                         if (new_conn_state->best_encoder != &encoder->base)
11683                                 continue;
11684                         found = enabled = true;
11685
11686                         I915_STATE_WARN(new_conn_state->crtc !=
11687                                         encoder->base.crtc,
11688                              "connector's crtc doesn't match encoder crtc\n");
11689                 }
11690
11691                 if (!found)
11692                         continue;
11693
11694                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11695                      "encoder's enabled state mismatch "
11696                      "(expected %i, found %i)\n",
11697                      !!encoder->base.crtc, enabled);
11698
11699                 if (!encoder->base.crtc) {
11700                         bool active;
11701
11702                         active = encoder->get_hw_state(encoder, &pipe);
11703                         I915_STATE_WARN(active,
11704                              "encoder detached but still enabled on pipe %c.\n",
11705                              pipe_name(pipe));
11706                 }
11707         }
11708 }
11709
11710 static void
11711 verify_crtc_state(struct drm_crtc *crtc,
11712                   struct drm_crtc_state *old_crtc_state,
11713                   struct drm_crtc_state *new_crtc_state)
11714 {
11715         struct drm_device *dev = crtc->dev;
11716         struct drm_i915_private *dev_priv = to_i915(dev);
11717         struct intel_encoder *encoder;
11718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11719         struct intel_crtc_state *pipe_config, *sw_config;
11720         struct drm_atomic_state *old_state;
11721         bool active;
11722
11723         old_state = old_crtc_state->state;
11724         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11725         pipe_config = to_intel_crtc_state(old_crtc_state);
11726         memset(pipe_config, 0, sizeof(*pipe_config));
11727         pipe_config->base.crtc = crtc;
11728         pipe_config->base.state = old_state;
11729
11730         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11731
11732         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11733
11734         /* we keep both pipes enabled on 830 */
11735         if (IS_I830(dev_priv))
11736                 active = new_crtc_state->active;
11737
11738         I915_STATE_WARN(new_crtc_state->active != active,
11739              "crtc active state doesn't match with hw state "
11740              "(expected %i, found %i)\n", new_crtc_state->active, active);
11741
11742         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11743              "transitional active state does not match atomic hw state "
11744              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11745
11746         for_each_encoder_on_crtc(dev, crtc, encoder) {
11747                 enum pipe pipe;
11748
11749                 active = encoder->get_hw_state(encoder, &pipe);
11750                 I915_STATE_WARN(active != new_crtc_state->active,
11751                         "[ENCODER:%i] active %i with crtc active %i\n",
11752                         encoder->base.base.id, active, new_crtc_state->active);
11753
11754                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11755                                 "Encoder connected to wrong pipe %c\n",
11756                                 pipe_name(pipe));
11757
11758                 if (active)
11759                         encoder->get_config(encoder, pipe_config);
11760         }
11761
11762         intel_crtc_compute_pixel_rate(pipe_config);
11763
11764         if (!new_crtc_state->active)
11765                 return;
11766
11767         intel_pipe_config_sanity_check(dev_priv, pipe_config);
11768
11769         sw_config = to_intel_crtc_state(new_crtc_state);
11770         if (!intel_pipe_config_compare(dev_priv, sw_config,
11771                                        pipe_config, false)) {
11772                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11773                 intel_dump_pipe_config(intel_crtc, pipe_config,
11774                                        "[hw state]");
11775                 intel_dump_pipe_config(intel_crtc, sw_config,
11776                                        "[sw state]");
11777         }
11778 }
11779
11780 static void
11781 intel_verify_planes(struct intel_atomic_state *state)
11782 {
11783         struct intel_plane *plane;
11784         const struct intel_plane_state *plane_state;
11785         int i;
11786
11787         for_each_new_intel_plane_in_state(state, plane,
11788                                           plane_state, i)
11789                 assert_plane(plane, plane_state->base.visible);
11790 }
11791
11792 static void
11793 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11794                          struct intel_shared_dpll *pll,
11795                          struct drm_crtc *crtc,
11796                          struct drm_crtc_state *new_state)
11797 {
11798         struct intel_dpll_hw_state dpll_hw_state;
11799         unsigned crtc_mask;
11800         bool active;
11801
11802         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11803
11804         DRM_DEBUG_KMS("%s\n", pll->info->name);
11805
11806         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
11807
11808         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
11809                 I915_STATE_WARN(!pll->on && pll->active_mask,
11810                      "pll in active use but not on in sw tracking\n");
11811                 I915_STATE_WARN(pll->on && !pll->active_mask,
11812                      "pll is on but not used by any active crtc\n");
11813                 I915_STATE_WARN(pll->on != active,
11814                      "pll on state mismatch (expected %i, found %i)\n",
11815                      pll->on, active);
11816         }
11817
11818         if (!crtc) {
11819                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11820                                 "more active pll users than references: %x vs %x\n",
11821                                 pll->active_mask, pll->state.crtc_mask);
11822
11823                 return;
11824         }
11825
11826         crtc_mask = 1 << drm_crtc_index(crtc);
11827
11828         if (new_state->active)
11829                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11830                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11831                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11832         else
11833                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11834                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11835                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11836
11837         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11838                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11839                         crtc_mask, pll->state.crtc_mask);
11840
11841         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11842                                           &dpll_hw_state,
11843                                           sizeof(dpll_hw_state)),
11844                         "pll hw state mismatch\n");
11845 }
11846
11847 static void
11848 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11849                          struct drm_crtc_state *old_crtc_state,
11850                          struct drm_crtc_state *new_crtc_state)
11851 {
11852         struct drm_i915_private *dev_priv = to_i915(dev);
11853         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11854         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11855
11856         if (new_state->shared_dpll)
11857                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11858
11859         if (old_state->shared_dpll &&
11860             old_state->shared_dpll != new_state->shared_dpll) {
11861                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11862                 struct intel_shared_dpll *pll = old_state->shared_dpll;
11863
11864                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11865                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11866                                 pipe_name(drm_crtc_index(crtc)));
11867                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11868                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11869                                 pipe_name(drm_crtc_index(crtc)));
11870         }
11871 }
11872
11873 static void
11874 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11875                           struct drm_atomic_state *state,
11876                           struct drm_crtc_state *old_state,
11877                           struct drm_crtc_state *new_state)
11878 {
11879         if (!needs_modeset(new_state) &&
11880             !to_intel_crtc_state(new_state)->update_pipe)
11881                 return;
11882
11883         verify_wm_state(crtc, new_state);
11884         verify_connector_state(crtc->dev, state, crtc);
11885         verify_crtc_state(crtc, old_state, new_state);
11886         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11887 }
11888
11889 static void
11890 verify_disabled_dpll_state(struct drm_device *dev)
11891 {
11892         struct drm_i915_private *dev_priv = to_i915(dev);
11893         int i;
11894
11895         for (i = 0; i < dev_priv->num_shared_dpll; i++)
11896                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11897 }
11898
11899 static void
11900 intel_modeset_verify_disabled(struct drm_device *dev,
11901                               struct drm_atomic_state *state)
11902 {
11903         verify_encoder_state(dev, state);
11904         verify_connector_state(dev, state, NULL);
11905         verify_disabled_dpll_state(dev);
11906 }
11907
11908 static void update_scanline_offset(struct intel_crtc *crtc)
11909 {
11910         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11911
11912         /*
11913          * The scanline counter increments at the leading edge of hsync.
11914          *
11915          * On most platforms it starts counting from vtotal-1 on the
11916          * first active line. That means the scanline counter value is
11917          * always one less than what we would expect. Ie. just after
11918          * start of vblank, which also occurs at start of hsync (on the
11919          * last active line), the scanline counter will read vblank_start-1.
11920          *
11921          * On gen2 the scanline counter starts counting from 1 instead
11922          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11923          * to keep the value positive), instead of adding one.
11924          *
11925          * On HSW+ the behaviour of the scanline counter depends on the output
11926          * type. For DP ports it behaves like most other platforms, but on HDMI
11927          * there's an extra 1 line difference. So we need to add two instead of
11928          * one to the value.
11929          *
11930          * On VLV/CHV DSI the scanline counter would appear to increment
11931          * approx. 1/3 of a scanline before start of vblank. Unfortunately
11932          * that means we can't tell whether we're in vblank or not while
11933          * we're on that particular line. We must still set scanline_offset
11934          * to 1 so that the vblank timestamps come out correct when we query
11935          * the scanline counter from within the vblank interrupt handler.
11936          * However if queried just before the start of vblank we'll get an
11937          * answer that's slightly in the future.
11938          */
11939         if (IS_GEN2(dev_priv)) {
11940                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11941                 int vtotal;
11942
11943                 vtotal = adjusted_mode->crtc_vtotal;
11944                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11945                         vtotal /= 2;
11946
11947                 crtc->scanline_offset = vtotal - 1;
11948         } else if (HAS_DDI(dev_priv) &&
11949                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11950                 crtc->scanline_offset = 2;
11951         } else
11952                 crtc->scanline_offset = 1;
11953 }
11954
11955 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11956 {
11957         struct drm_device *dev = state->dev;
11958         struct drm_i915_private *dev_priv = to_i915(dev);
11959         struct drm_crtc *crtc;
11960         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11961         int i;
11962
11963         if (!dev_priv->display.crtc_compute_clock)
11964                 return;
11965
11966         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11967                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11968                 struct intel_shared_dpll *old_dpll =
11969                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
11970
11971                 if (!needs_modeset(new_crtc_state))
11972                         continue;
11973
11974                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11975
11976                 if (!old_dpll)
11977                         continue;
11978
11979                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11980         }
11981 }
11982
11983 /*
11984  * This implements the workaround described in the "notes" section of the mode
11985  * set sequence documentation. When going from no pipes or single pipe to
11986  * multiple pipes, and planes are enabled after the pipe, we need to wait at
11987  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11988  */
11989 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11990 {
11991         struct drm_crtc_state *crtc_state;
11992         struct intel_crtc *intel_crtc;
11993         struct drm_crtc *crtc;
11994         struct intel_crtc_state *first_crtc_state = NULL;
11995         struct intel_crtc_state *other_crtc_state = NULL;
11996         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11997         int i;
11998
11999         /* look at all crtc's that are going to be enabled in during modeset */
12000         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12001                 intel_crtc = to_intel_crtc(crtc);
12002
12003                 if (!crtc_state->active || !needs_modeset(crtc_state))
12004                         continue;
12005
12006                 if (first_crtc_state) {
12007                         other_crtc_state = to_intel_crtc_state(crtc_state);
12008                         break;
12009                 } else {
12010                         first_crtc_state = to_intel_crtc_state(crtc_state);
12011                         first_pipe = intel_crtc->pipe;
12012                 }
12013         }
12014
12015         /* No workaround needed? */
12016         if (!first_crtc_state)
12017                 return 0;
12018
12019         /* w/a possibly needed, check how many crtc's are already enabled. */
12020         for_each_intel_crtc(state->dev, intel_crtc) {
12021                 struct intel_crtc_state *pipe_config;
12022
12023                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12024                 if (IS_ERR(pipe_config))
12025                         return PTR_ERR(pipe_config);
12026
12027                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12028
12029                 if (!pipe_config->base.active ||
12030                     needs_modeset(&pipe_config->base))
12031                         continue;
12032
12033                 /* 2 or more enabled crtcs means no need for w/a */
12034                 if (enabled_pipe != INVALID_PIPE)
12035                         return 0;
12036
12037                 enabled_pipe = intel_crtc->pipe;
12038         }
12039
12040         if (enabled_pipe != INVALID_PIPE)
12041                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12042         else if (other_crtc_state)
12043                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12044
12045         return 0;
12046 }
12047
12048 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12049 {
12050         struct drm_crtc *crtc;
12051
12052         /* Add all pipes to the state */
12053         for_each_crtc(state->dev, crtc) {
12054                 struct drm_crtc_state *crtc_state;
12055
12056                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12057                 if (IS_ERR(crtc_state))
12058                         return PTR_ERR(crtc_state);
12059         }
12060
12061         return 0;
12062 }
12063
12064 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12065 {
12066         struct drm_crtc *crtc;
12067
12068         /*
12069          * Add all pipes to the state, and force
12070          * a modeset on all the active ones.
12071          */
12072         for_each_crtc(state->dev, crtc) {
12073                 struct drm_crtc_state *crtc_state;
12074                 int ret;
12075
12076                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12077                 if (IS_ERR(crtc_state))
12078                         return PTR_ERR(crtc_state);
12079
12080                 if (!crtc_state->active || needs_modeset(crtc_state))
12081                         continue;
12082
12083                 crtc_state->mode_changed = true;
12084
12085                 ret = drm_atomic_add_affected_connectors(state, crtc);
12086                 if (ret)
12087                         return ret;
12088
12089                 ret = drm_atomic_add_affected_planes(state, crtc);
12090                 if (ret)
12091                         return ret;
12092         }
12093
12094         return 0;
12095 }
12096
12097 static int intel_modeset_checks(struct drm_atomic_state *state)
12098 {
12099         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12100         struct drm_i915_private *dev_priv = to_i915(state->dev);
12101         struct drm_crtc *crtc;
12102         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12103         int ret = 0, i;
12104
12105         if (!check_digital_port_conflicts(state)) {
12106                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12107                 return -EINVAL;
12108         }
12109
12110         intel_state->modeset = true;
12111         intel_state->active_crtcs = dev_priv->active_crtcs;
12112         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12113         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12114
12115         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12116                 if (new_crtc_state->active)
12117                         intel_state->active_crtcs |= 1 << i;
12118                 else
12119                         intel_state->active_crtcs &= ~(1 << i);
12120
12121                 if (old_crtc_state->active != new_crtc_state->active)
12122                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12123         }
12124
12125         /*
12126          * See if the config requires any additional preparation, e.g.
12127          * to adjust global state with pipes off.  We need to do this
12128          * here so we can get the modeset_pipe updated config for the new
12129          * mode set on this crtc.  For other crtcs we need to use the
12130          * adjusted_mode bits in the crtc directly.
12131          */
12132         if (dev_priv->display.modeset_calc_cdclk) {
12133                 ret = dev_priv->display.modeset_calc_cdclk(state);
12134                 if (ret < 0)
12135                         return ret;
12136
12137                 /*
12138                  * Writes to dev_priv->cdclk.logical must protected by
12139                  * holding all the crtc locks, even if we don't end up
12140                  * touching the hardware
12141                  */
12142                 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12143                                         &intel_state->cdclk.logical)) {
12144                         ret = intel_lock_all_pipes(state);
12145                         if (ret < 0)
12146                                 return ret;
12147                 }
12148
12149                 /* All pipes must be switched off while we change the cdclk. */
12150                 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12151                                               &intel_state->cdclk.actual)) {
12152                         ret = intel_modeset_all_pipes(state);
12153                         if (ret < 0)
12154                                 return ret;
12155                 }
12156
12157                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12158                               intel_state->cdclk.logical.cdclk,
12159                               intel_state->cdclk.actual.cdclk);
12160                 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12161                               intel_state->cdclk.logical.voltage_level,
12162                               intel_state->cdclk.actual.voltage_level);
12163         } else {
12164                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12165         }
12166
12167         intel_modeset_clear_plls(state);
12168
12169         if (IS_HASWELL(dev_priv))
12170                 return haswell_mode_set_planes_workaround(state);
12171
12172         return 0;
12173 }
12174
12175 /*
12176  * Handle calculation of various watermark data at the end of the atomic check
12177  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12178  * handlers to ensure that all derived state has been updated.
12179  */
12180 static int calc_watermark_data(struct drm_atomic_state *state)
12181 {
12182         struct drm_device *dev = state->dev;
12183         struct drm_i915_private *dev_priv = to_i915(dev);
12184
12185         /* Is there platform-specific watermark information to calculate? */
12186         if (dev_priv->display.compute_global_watermarks)
12187                 return dev_priv->display.compute_global_watermarks(state);
12188
12189         return 0;
12190 }
12191
12192 /**
12193  * intel_atomic_check - validate state object
12194  * @dev: drm device
12195  * @state: state to validate
12196  */
12197 static int intel_atomic_check(struct drm_device *dev,
12198                               struct drm_atomic_state *state)
12199 {
12200         struct drm_i915_private *dev_priv = to_i915(dev);
12201         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12202         struct drm_crtc *crtc;
12203         struct drm_crtc_state *old_crtc_state, *crtc_state;
12204         int ret, i;
12205         bool any_ms = false;
12206
12207         /* Catch I915_MODE_FLAG_INHERITED */
12208         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
12209                                       crtc_state, i) {
12210                 if (crtc_state->mode.private_flags !=
12211                     old_crtc_state->mode.private_flags)
12212                         crtc_state->mode_changed = true;
12213         }
12214
12215         ret = drm_atomic_helper_check_modeset(dev, state);
12216         if (ret)
12217                 return ret;
12218
12219         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12220                 struct intel_crtc_state *pipe_config =
12221                         to_intel_crtc_state(crtc_state);
12222
12223                 if (!needs_modeset(crtc_state))
12224                         continue;
12225
12226                 if (!crtc_state->enable) {
12227                         any_ms = true;
12228                         continue;
12229                 }
12230
12231                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12232                 if (ret) {
12233                         intel_dump_pipe_config(to_intel_crtc(crtc),
12234                                                pipe_config, "[failed]");
12235                         return ret;
12236                 }
12237
12238                 if (i915_modparams.fastboot &&
12239                     intel_pipe_config_compare(dev_priv,
12240                                         to_intel_crtc_state(old_crtc_state),
12241                                         pipe_config, true)) {
12242                         crtc_state->mode_changed = false;
12243                         pipe_config->update_pipe = true;
12244                 }
12245
12246                 if (needs_modeset(crtc_state))
12247                         any_ms = true;
12248
12249                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12250                                        needs_modeset(crtc_state) ?
12251                                        "[modeset]" : "[fastset]");
12252         }
12253
12254         if (any_ms) {
12255                 ret = intel_modeset_checks(state);
12256
12257                 if (ret)
12258                         return ret;
12259         } else {
12260                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12261         }
12262
12263         ret = drm_atomic_helper_check_planes(dev, state);
12264         if (ret)
12265                 return ret;
12266
12267         intel_fbc_choose_crtc(dev_priv, intel_state);
12268         return calc_watermark_data(state);
12269 }
12270
12271 static int intel_atomic_prepare_commit(struct drm_device *dev,
12272                                        struct drm_atomic_state *state)
12273 {
12274         return drm_atomic_helper_prepare_planes(dev, state);
12275 }
12276
12277 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12278 {
12279         struct drm_device *dev = crtc->base.dev;
12280
12281         if (!dev->max_vblank_count)
12282                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
12283
12284         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12285 }
12286
12287 static void intel_update_crtc(struct drm_crtc *crtc,
12288                               struct drm_atomic_state *state,
12289                               struct drm_crtc_state *old_crtc_state,
12290                               struct drm_crtc_state *new_crtc_state)
12291 {
12292         struct drm_device *dev = crtc->dev;
12293         struct drm_i915_private *dev_priv = to_i915(dev);
12294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12295         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12296         bool modeset = needs_modeset(new_crtc_state);
12297         struct intel_plane_state *new_plane_state =
12298                 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
12299                                                  to_intel_plane(crtc->primary));
12300
12301         if (modeset) {
12302                 update_scanline_offset(intel_crtc);
12303                 dev_priv->display.crtc_enable(pipe_config, state);
12304
12305                 /* vblanks work again, re-enable pipe CRC. */
12306                 intel_crtc_enable_pipe_crc(intel_crtc);
12307         } else {
12308                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12309                                        pipe_config);
12310         }
12311
12312         if (new_plane_state)
12313                 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
12314
12315         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12316 }
12317
12318 static void intel_update_crtcs(struct drm_atomic_state *state)
12319 {
12320         struct drm_crtc *crtc;
12321         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12322         int i;
12323
12324         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12325                 if (!new_crtc_state->active)
12326                         continue;
12327
12328                 intel_update_crtc(crtc, state, old_crtc_state,
12329                                   new_crtc_state);
12330         }
12331 }
12332
12333 static void skl_update_crtcs(struct drm_atomic_state *state)
12334 {
12335         struct drm_i915_private *dev_priv = to_i915(state->dev);
12336         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12337         struct drm_crtc *crtc;
12338         struct intel_crtc *intel_crtc;
12339         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12340         struct intel_crtc_state *cstate;
12341         unsigned int updated = 0;
12342         bool progress;
12343         enum pipe pipe;
12344         int i;
12345         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
12346         u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
12347
12348         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12349
12350         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12351                 /* ignore allocations for crtc's that have been turned off. */
12352                 if (new_crtc_state->active)
12353                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12354
12355         /* If 2nd DBuf slice required, enable it here */
12356         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
12357                 icl_dbuf_slices_update(dev_priv, required_slices);
12358
12359         /*
12360          * Whenever the number of active pipes changes, we need to make sure we
12361          * update the pipes in the right order so that their ddb allocations
12362          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12363          * cause pipe underruns and other bad stuff.
12364          */
12365         do {
12366                 progress = false;
12367
12368                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12369                         bool vbl_wait = false;
12370                         unsigned int cmask = drm_crtc_mask(crtc);
12371
12372                         intel_crtc = to_intel_crtc(crtc);
12373                         cstate = to_intel_crtc_state(new_crtc_state);
12374                         pipe = intel_crtc->pipe;
12375
12376                         if (updated & cmask || !cstate->base.active)
12377                                 continue;
12378
12379                         if (skl_ddb_allocation_overlaps(dev_priv,
12380                                                         entries,
12381                                                         &cstate->wm.skl.ddb,
12382                                                         i))
12383                                 continue;
12384
12385                         updated |= cmask;
12386                         entries[i] = &cstate->wm.skl.ddb;
12387
12388                         /*
12389                          * If this is an already active pipe, it's DDB changed,
12390                          * and this isn't the last pipe that needs updating
12391                          * then we need to wait for a vblank to pass for the
12392                          * new ddb allocation to take effect.
12393                          */
12394                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12395                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12396                             !new_crtc_state->active_changed &&
12397                             intel_state->wm_results.dirty_pipes != updated)
12398                                 vbl_wait = true;
12399
12400                         intel_update_crtc(crtc, state, old_crtc_state,
12401                                           new_crtc_state);
12402
12403                         if (vbl_wait)
12404                                 intel_wait_for_vblank(dev_priv, pipe);
12405
12406                         progress = true;
12407                 }
12408         } while (progress);
12409
12410         /* If 2nd DBuf slice is no more required disable it */
12411         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
12412                 icl_dbuf_slices_update(dev_priv, required_slices);
12413 }
12414
12415 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12416 {
12417         struct intel_atomic_state *state, *next;
12418         struct llist_node *freed;
12419
12420         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12421         llist_for_each_entry_safe(state, next, freed, freed)
12422                 drm_atomic_state_put(&state->base);
12423 }
12424
12425 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12426 {
12427         struct drm_i915_private *dev_priv =
12428                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12429
12430         intel_atomic_helper_free_state(dev_priv);
12431 }
12432
12433 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12434 {
12435         struct wait_queue_entry wait_fence, wait_reset;
12436         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12437
12438         init_wait_entry(&wait_fence, 0);
12439         init_wait_entry(&wait_reset, 0);
12440         for (;;) {
12441                 prepare_to_wait(&intel_state->commit_ready.wait,
12442                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12443                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12444                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12445
12446
12447                 if (i915_sw_fence_done(&intel_state->commit_ready)
12448                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12449                         break;
12450
12451                 schedule();
12452         }
12453         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12454         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12455 }
12456
12457 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12458 {
12459         struct drm_device *dev = state->dev;
12460         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12461         struct drm_i915_private *dev_priv = to_i915(dev);
12462         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12463         struct drm_crtc *crtc;
12464         struct intel_crtc_state *intel_cstate;
12465         u64 put_domains[I915_MAX_PIPES] = {};
12466         int i;
12467
12468         intel_atomic_commit_fence_wait(intel_state);
12469
12470         drm_atomic_helper_wait_for_dependencies(state);
12471
12472         if (intel_state->modeset)
12473                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12474
12475         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12476                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12477
12478                 if (needs_modeset(new_crtc_state) ||
12479                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12480
12481                         put_domains[to_intel_crtc(crtc)->pipe] =
12482                                 modeset_get_crtc_power_domains(crtc,
12483                                         to_intel_crtc_state(new_crtc_state));
12484                 }
12485
12486                 if (!needs_modeset(new_crtc_state))
12487                         continue;
12488
12489                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12490                                        to_intel_crtc_state(new_crtc_state));
12491
12492                 if (old_crtc_state->active) {
12493                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12494
12495                         /*
12496                          * We need to disable pipe CRC before disabling the pipe,
12497                          * or we race against vblank off.
12498                          */
12499                         intel_crtc_disable_pipe_crc(intel_crtc);
12500
12501                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12502                         intel_crtc->active = false;
12503                         intel_fbc_disable(intel_crtc);
12504                         intel_disable_shared_dpll(intel_crtc);
12505
12506                         /*
12507                          * Underruns don't always raise
12508                          * interrupts, so check manually.
12509                          */
12510                         intel_check_cpu_fifo_underruns(dev_priv);
12511                         intel_check_pch_fifo_underruns(dev_priv);
12512
12513                         if (!new_crtc_state->active) {
12514                                 /*
12515                                  * Make sure we don't call initial_watermarks
12516                                  * for ILK-style watermark updates.
12517                                  *
12518                                  * No clue what this is supposed to achieve.
12519                                  */
12520                                 if (INTEL_GEN(dev_priv) >= 9)
12521                                         dev_priv->display.initial_watermarks(intel_state,
12522                                                                              to_intel_crtc_state(new_crtc_state));
12523                         }
12524                 }
12525         }
12526
12527         /* FIXME: Eventually get rid of our intel_crtc->config pointer */
12528         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
12529                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
12530
12531         if (intel_state->modeset) {
12532                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12533
12534                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12535
12536                 /*
12537                  * SKL workaround: bspec recommends we disable the SAGV when we
12538                  * have more then one pipe enabled
12539                  */
12540                 if (!intel_can_enable_sagv(state))
12541                         intel_disable_sagv(dev_priv);
12542
12543                 intel_modeset_verify_disabled(dev, state);
12544         }
12545
12546         /* Complete the events for pipes that have now been disabled */
12547         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12548                 bool modeset = needs_modeset(new_crtc_state);
12549
12550                 /* Complete events for now disable pipes here. */
12551                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12552                         spin_lock_irq(&dev->event_lock);
12553                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12554                         spin_unlock_irq(&dev->event_lock);
12555
12556                         new_crtc_state->event = NULL;
12557                 }
12558         }
12559
12560         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12561         dev_priv->display.update_crtcs(state);
12562
12563         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12564          * already, but still need the state for the delayed optimization. To
12565          * fix this:
12566          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12567          * - schedule that vblank worker _before_ calling hw_done
12568          * - at the start of commit_tail, cancel it _synchrously
12569          * - switch over to the vblank wait helper in the core after that since
12570          *   we don't need out special handling any more.
12571          */
12572         drm_atomic_helper_wait_for_flip_done(dev, state);
12573
12574         /*
12575          * Now that the vblank has passed, we can go ahead and program the
12576          * optimal watermarks on platforms that need two-step watermark
12577          * programming.
12578          *
12579          * TODO: Move this (and other cleanup) to an async worker eventually.
12580          */
12581         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12582                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12583
12584                 if (dev_priv->display.optimize_watermarks)
12585                         dev_priv->display.optimize_watermarks(intel_state,
12586                                                               intel_cstate);
12587         }
12588
12589         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12590                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12591
12592                 if (put_domains[i])
12593                         modeset_put_power_domains(dev_priv, put_domains[i]);
12594
12595                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12596         }
12597
12598         if (intel_state->modeset)
12599                 intel_verify_planes(intel_state);
12600
12601         if (intel_state->modeset && intel_can_enable_sagv(state))
12602                 intel_enable_sagv(dev_priv);
12603
12604         drm_atomic_helper_commit_hw_done(state);
12605
12606         if (intel_state->modeset) {
12607                 /* As one of the primary mmio accessors, KMS has a high
12608                  * likelihood of triggering bugs in unclaimed access. After we
12609                  * finish modesetting, see if an error has been flagged, and if
12610                  * so enable debugging for the next modeset - and hope we catch
12611                  * the culprit.
12612                  */
12613                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12614                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12615         }
12616
12617         drm_atomic_helper_cleanup_planes(dev, state);
12618
12619         drm_atomic_helper_commit_cleanup_done(state);
12620
12621         drm_atomic_state_put(state);
12622
12623         intel_atomic_helper_free_state(dev_priv);
12624 }
12625
12626 static void intel_atomic_commit_work(struct work_struct *work)
12627 {
12628         struct drm_atomic_state *state =
12629                 container_of(work, struct drm_atomic_state, commit_work);
12630
12631         intel_atomic_commit_tail(state);
12632 }
12633
12634 static int __i915_sw_fence_call
12635 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12636                           enum i915_sw_fence_notify notify)
12637 {
12638         struct intel_atomic_state *state =
12639                 container_of(fence, struct intel_atomic_state, commit_ready);
12640
12641         switch (notify) {
12642         case FENCE_COMPLETE:
12643                 /* we do blocking waits in the worker, nothing to do here */
12644                 break;
12645         case FENCE_FREE:
12646                 {
12647                         struct intel_atomic_helper *helper =
12648                                 &to_i915(state->base.dev)->atomic_helper;
12649
12650                         if (llist_add(&state->freed, &helper->free_list))
12651                                 schedule_work(&helper->free_work);
12652                         break;
12653                 }
12654         }
12655
12656         return NOTIFY_DONE;
12657 }
12658
12659 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12660 {
12661         struct drm_plane_state *old_plane_state, *new_plane_state;
12662         struct drm_plane *plane;
12663         int i;
12664
12665         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12666                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12667                                   intel_fb_obj(new_plane_state->fb),
12668                                   to_intel_plane(plane)->frontbuffer_bit);
12669 }
12670
12671 /**
12672  * intel_atomic_commit - commit validated state object
12673  * @dev: DRM device
12674  * @state: the top-level driver state object
12675  * @nonblock: nonblocking commit
12676  *
12677  * This function commits a top-level state object that has been validated
12678  * with drm_atomic_helper_check().
12679  *
12680  * RETURNS
12681  * Zero for success or -errno.
12682  */
12683 static int intel_atomic_commit(struct drm_device *dev,
12684                                struct drm_atomic_state *state,
12685                                bool nonblock)
12686 {
12687         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12688         struct drm_i915_private *dev_priv = to_i915(dev);
12689         int ret = 0;
12690
12691         drm_atomic_state_get(state);
12692         i915_sw_fence_init(&intel_state->commit_ready,
12693                            intel_atomic_commit_ready);
12694
12695         /*
12696          * The intel_legacy_cursor_update() fast path takes care
12697          * of avoiding the vblank waits for simple cursor
12698          * movement and flips. For cursor on/off and size changes,
12699          * we want to perform the vblank waits so that watermark
12700          * updates happen during the correct frames. Gen9+ have
12701          * double buffered watermarks and so shouldn't need this.
12702          *
12703          * Unset state->legacy_cursor_update before the call to
12704          * drm_atomic_helper_setup_commit() because otherwise
12705          * drm_atomic_helper_wait_for_flip_done() is a noop and
12706          * we get FIFO underruns because we didn't wait
12707          * for vblank.
12708          *
12709          * FIXME doing watermarks and fb cleanup from a vblank worker
12710          * (assuming we had any) would solve these problems.
12711          */
12712         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12713                 struct intel_crtc_state *new_crtc_state;
12714                 struct intel_crtc *crtc;
12715                 int i;
12716
12717                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12718                         if (new_crtc_state->wm.need_postvbl_update ||
12719                             new_crtc_state->update_wm_post)
12720                                 state->legacy_cursor_update = false;
12721         }
12722
12723         ret = intel_atomic_prepare_commit(dev, state);
12724         if (ret) {
12725                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12726                 i915_sw_fence_commit(&intel_state->commit_ready);
12727                 return ret;
12728         }
12729
12730         ret = drm_atomic_helper_setup_commit(state, nonblock);
12731         if (!ret)
12732                 ret = drm_atomic_helper_swap_state(state, true);
12733
12734         if (ret) {
12735                 i915_sw_fence_commit(&intel_state->commit_ready);
12736
12737                 drm_atomic_helper_cleanup_planes(dev, state);
12738                 return ret;
12739         }
12740         dev_priv->wm.distrust_bios_wm = false;
12741         intel_shared_dpll_swap_state(state);
12742         intel_atomic_track_fbs(state);
12743
12744         if (intel_state->modeset) {
12745                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12746                        sizeof(intel_state->min_cdclk));
12747                 memcpy(dev_priv->min_voltage_level,
12748                        intel_state->min_voltage_level,
12749                        sizeof(intel_state->min_voltage_level));
12750                 dev_priv->active_crtcs = intel_state->active_crtcs;
12751                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12752                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12753         }
12754
12755         drm_atomic_state_get(state);
12756         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12757
12758         i915_sw_fence_commit(&intel_state->commit_ready);
12759         if (nonblock && intel_state->modeset) {
12760                 queue_work(dev_priv->modeset_wq, &state->commit_work);
12761         } else if (nonblock) {
12762                 queue_work(system_unbound_wq, &state->commit_work);
12763         } else {
12764                 if (intel_state->modeset)
12765                         flush_workqueue(dev_priv->modeset_wq);
12766                 intel_atomic_commit_tail(state);
12767         }
12768
12769         return 0;
12770 }
12771
12772 static const struct drm_crtc_funcs intel_crtc_funcs = {
12773         .gamma_set = drm_atomic_helper_legacy_gamma_set,
12774         .set_config = drm_atomic_helper_set_config,
12775         .destroy = intel_crtc_destroy,
12776         .page_flip = drm_atomic_helper_page_flip,
12777         .atomic_duplicate_state = intel_crtc_duplicate_state,
12778         .atomic_destroy_state = intel_crtc_destroy_state,
12779         .set_crc_source = intel_crtc_set_crc_source,
12780 };
12781
12782 struct wait_rps_boost {
12783         struct wait_queue_entry wait;
12784
12785         struct drm_crtc *crtc;
12786         struct i915_request *request;
12787 };
12788
12789 static int do_rps_boost(struct wait_queue_entry *_wait,
12790                         unsigned mode, int sync, void *key)
12791 {
12792         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12793         struct i915_request *rq = wait->request;
12794
12795         /*
12796          * If we missed the vblank, but the request is already running it
12797          * is reasonable to assume that it will complete before the next
12798          * vblank without our intervention, so leave RPS alone.
12799          */
12800         if (!i915_request_started(rq))
12801                 gen6_rps_boost(rq, NULL);
12802         i915_request_put(rq);
12803
12804         drm_crtc_vblank_put(wait->crtc);
12805
12806         list_del(&wait->wait.entry);
12807         kfree(wait);
12808         return 1;
12809 }
12810
12811 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12812                                        struct dma_fence *fence)
12813 {
12814         struct wait_rps_boost *wait;
12815
12816         if (!dma_fence_is_i915(fence))
12817                 return;
12818
12819         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12820                 return;
12821
12822         if (drm_crtc_vblank_get(crtc))
12823                 return;
12824
12825         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12826         if (!wait) {
12827                 drm_crtc_vblank_put(crtc);
12828                 return;
12829         }
12830
12831         wait->request = to_request(dma_fence_get(fence));
12832         wait->crtc = crtc;
12833
12834         wait->wait.func = do_rps_boost;
12835         wait->wait.flags = 0;
12836
12837         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12838 }
12839
12840 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
12841 {
12842         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12843         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12844         struct drm_framebuffer *fb = plane_state->base.fb;
12845         struct i915_vma *vma;
12846
12847         if (plane->id == PLANE_CURSOR &&
12848             INTEL_INFO(dev_priv)->cursor_needs_physical) {
12849                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12850                 const int align = intel_cursor_alignment(dev_priv);
12851
12852                 return i915_gem_object_attach_phys(obj, align);
12853         }
12854
12855         vma = intel_pin_and_fence_fb_obj(fb,
12856                                          plane_state->base.rotation,
12857                                          intel_plane_uses_fence(plane_state),
12858                                          &plane_state->flags);
12859         if (IS_ERR(vma))
12860                 return PTR_ERR(vma);
12861
12862         plane_state->vma = vma;
12863
12864         return 0;
12865 }
12866
12867 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
12868 {
12869         struct i915_vma *vma;
12870
12871         vma = fetch_and_zero(&old_plane_state->vma);
12872         if (vma)
12873                 intel_unpin_fb_vma(vma, old_plane_state->flags);
12874 }
12875
12876 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
12877 {
12878         struct i915_sched_attr attr = {
12879                 .priority = I915_PRIORITY_DISPLAY,
12880         };
12881
12882         i915_gem_object_wait_priority(obj, 0, &attr);
12883 }
12884
12885 /**
12886  * intel_prepare_plane_fb - Prepare fb for usage on plane
12887  * @plane: drm plane to prepare for
12888  * @new_state: the plane state being prepared
12889  *
12890  * Prepares a framebuffer for usage on a display plane.  Generally this
12891  * involves pinning the underlying object and updating the frontbuffer tracking
12892  * bits.  Some older platforms need special physical address handling for
12893  * cursor planes.
12894  *
12895  * Must be called with struct_mutex held.
12896  *
12897  * Returns 0 on success, negative error code on failure.
12898  */
12899 int
12900 intel_prepare_plane_fb(struct drm_plane *plane,
12901                        struct drm_plane_state *new_state)
12902 {
12903         struct intel_atomic_state *intel_state =
12904                 to_intel_atomic_state(new_state->state);
12905         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12906         struct drm_framebuffer *fb = new_state->fb;
12907         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12908         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12909         int ret;
12910
12911         if (old_obj) {
12912                 struct drm_crtc_state *crtc_state =
12913                         drm_atomic_get_new_crtc_state(new_state->state,
12914                                                       plane->state->crtc);
12915
12916                 /* Big Hammer, we also need to ensure that any pending
12917                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12918                  * current scanout is retired before unpinning the old
12919                  * framebuffer. Note that we rely on userspace rendering
12920                  * into the buffer attached to the pipe they are waiting
12921                  * on. If not, userspace generates a GPU hang with IPEHR
12922                  * point to the MI_WAIT_FOR_EVENT.
12923                  *
12924                  * This should only fail upon a hung GPU, in which case we
12925                  * can safely continue.
12926                  */
12927                 if (needs_modeset(crtc_state)) {
12928                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12929                                                               old_obj->resv, NULL,
12930                                                               false, 0,
12931                                                               GFP_KERNEL);
12932                         if (ret < 0)
12933                                 return ret;
12934                 }
12935         }
12936
12937         if (new_state->fence) { /* explicit fencing */
12938                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12939                                                     new_state->fence,
12940                                                     I915_FENCE_TIMEOUT,
12941                                                     GFP_KERNEL);
12942                 if (ret < 0)
12943                         return ret;
12944         }
12945
12946         if (!obj)
12947                 return 0;
12948
12949         ret = i915_gem_object_pin_pages(obj);
12950         if (ret)
12951                 return ret;
12952
12953         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12954         if (ret) {
12955                 i915_gem_object_unpin_pages(obj);
12956                 return ret;
12957         }
12958
12959         ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
12960
12961         fb_obj_bump_render_priority(obj);
12962
12963         mutex_unlock(&dev_priv->drm.struct_mutex);
12964         i915_gem_object_unpin_pages(obj);
12965         if (ret)
12966                 return ret;
12967
12968         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
12969
12970         if (!new_state->fence) { /* implicit fencing */
12971                 struct dma_fence *fence;
12972
12973                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12974                                                       obj->resv, NULL,
12975                                                       false, I915_FENCE_TIMEOUT,
12976                                                       GFP_KERNEL);
12977                 if (ret < 0)
12978                         return ret;
12979
12980                 fence = reservation_object_get_excl_rcu(obj->resv);
12981                 if (fence) {
12982                         add_rps_boost_after_vblank(new_state->crtc, fence);
12983                         dma_fence_put(fence);
12984                 }
12985         } else {
12986                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12987         }
12988
12989         return 0;
12990 }
12991
12992 /**
12993  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12994  * @plane: drm plane to clean up for
12995  * @old_state: the state from the previous modeset
12996  *
12997  * Cleans up a framebuffer that has just been removed from a plane.
12998  *
12999  * Must be called with struct_mutex held.
13000  */
13001 void
13002 intel_cleanup_plane_fb(struct drm_plane *plane,
13003                        struct drm_plane_state *old_state)
13004 {
13005         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13006
13007         /* Should only be called after a successful intel_prepare_plane_fb()! */
13008         mutex_lock(&dev_priv->drm.struct_mutex);
13009         intel_plane_unpin_fb(to_intel_plane_state(old_state));
13010         mutex_unlock(&dev_priv->drm.struct_mutex);
13011 }
13012
13013 int
13014 skl_max_scale(struct intel_crtc *intel_crtc,
13015               struct intel_crtc_state *crtc_state,
13016               uint32_t pixel_format)
13017 {
13018         struct drm_i915_private *dev_priv;
13019         int max_scale, mult;
13020         int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
13021
13022         if (!intel_crtc || !crtc_state->base.enable)
13023                 return DRM_PLANE_HELPER_NO_SCALING;
13024
13025         dev_priv = to_i915(intel_crtc->base.dev);
13026
13027         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13028         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13029
13030         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
13031                 max_dotclk *= 2;
13032
13033         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13034                 return DRM_PLANE_HELPER_NO_SCALING;
13035
13036         /*
13037          * skl max scale is lower of:
13038          *    close to 3 but not 3, -1 is for that purpose
13039          *            or
13040          *    cdclk/crtc_clock
13041          */
13042         mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
13043         tmpclk1 = (1 << 16) * mult - 1;
13044         tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
13045         max_scale = min(tmpclk1, tmpclk2);
13046
13047         return max_scale;
13048 }
13049
13050 static int
13051 intel_check_primary_plane(struct intel_plane *plane,
13052                           struct intel_crtc_state *crtc_state,
13053                           struct intel_plane_state *state)
13054 {
13055         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13056         struct drm_crtc *crtc = state->base.crtc;
13057         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13058         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13059         bool can_position = false;
13060         int ret;
13061         uint32_t pixel_format = 0;
13062
13063         if (INTEL_GEN(dev_priv) >= 9) {
13064                 /* use scaler when colorkey is not required */
13065                 if (!state->ckey.flags) {
13066                         min_scale = 1;
13067                         if (state->base.fb)
13068                                 pixel_format = state->base.fb->format->format;
13069                         max_scale = skl_max_scale(to_intel_crtc(crtc),
13070                                                   crtc_state, pixel_format);
13071                 }
13072                 can_position = true;
13073         }
13074
13075         ret = drm_atomic_helper_check_plane_state(&state->base,
13076                                                   &crtc_state->base,
13077                                                   min_scale, max_scale,
13078                                                   can_position, true);
13079         if (ret)
13080                 return ret;
13081
13082         if (!state->base.fb)
13083                 return 0;
13084
13085         if (INTEL_GEN(dev_priv) >= 9) {
13086                 ret = skl_check_plane_surface(crtc_state, state);
13087                 if (ret)
13088                         return ret;
13089
13090                 state->ctl = skl_plane_ctl(crtc_state, state);
13091         } else {
13092                 ret = i9xx_check_plane_surface(state);
13093                 if (ret)
13094                         return ret;
13095
13096                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13097         }
13098
13099         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
13100                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
13101
13102         return 0;
13103 }
13104
13105 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13106                                     struct drm_crtc_state *old_crtc_state)
13107 {
13108         struct drm_device *dev = crtc->dev;
13109         struct drm_i915_private *dev_priv = to_i915(dev);
13110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13111         struct intel_crtc_state *old_intel_cstate =
13112                 to_intel_crtc_state(old_crtc_state);
13113         struct intel_atomic_state *old_intel_state =
13114                 to_intel_atomic_state(old_crtc_state->state);
13115         struct intel_crtc_state *intel_cstate =
13116                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13117         bool modeset = needs_modeset(&intel_cstate->base);
13118
13119         if (!modeset &&
13120             (intel_cstate->base.color_mgmt_changed ||
13121              intel_cstate->update_pipe)) {
13122                 intel_color_set_csc(&intel_cstate->base);
13123                 intel_color_load_luts(&intel_cstate->base);
13124         }
13125
13126         /* Perform vblank evasion around commit operation */
13127         intel_pipe_update_start(intel_cstate);
13128
13129         if (modeset)
13130                 goto out;
13131
13132         if (intel_cstate->update_pipe)
13133                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
13134         else if (INTEL_GEN(dev_priv) >= 9)
13135                 skl_detach_scalers(intel_crtc);
13136
13137 out:
13138         if (dev_priv->display.atomic_update_watermarks)
13139                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13140                                                            intel_cstate);
13141 }
13142
13143 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13144                                   struct intel_crtc_state *crtc_state)
13145 {
13146         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13147
13148         if (!IS_GEN2(dev_priv))
13149                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13150
13151         if (crtc_state->has_pch_encoder) {
13152                 enum pipe pch_transcoder =
13153                         intel_crtc_pch_transcoder(crtc);
13154
13155                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
13156         }
13157 }
13158
13159 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13160                                      struct drm_crtc_state *old_crtc_state)
13161 {
13162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13163         struct intel_atomic_state *old_intel_state =
13164                 to_intel_atomic_state(old_crtc_state->state);
13165         struct intel_crtc_state *new_crtc_state =
13166                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13167
13168         intel_pipe_update_end(new_crtc_state);
13169
13170         if (new_crtc_state->update_pipe &&
13171             !needs_modeset(&new_crtc_state->base) &&
13172             old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
13173                 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
13174 }
13175
13176 /**
13177  * intel_plane_destroy - destroy a plane
13178  * @plane: plane to destroy
13179  *
13180  * Common destruction function for all types of planes (primary, cursor,
13181  * sprite).
13182  */
13183 void intel_plane_destroy(struct drm_plane *plane)
13184 {
13185         drm_plane_cleanup(plane);
13186         kfree(to_intel_plane(plane));
13187 }
13188
13189 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
13190 {
13191         switch (format) {
13192         case DRM_FORMAT_C8:
13193         case DRM_FORMAT_RGB565:
13194         case DRM_FORMAT_XRGB1555:
13195         case DRM_FORMAT_XRGB8888:
13196                 return modifier == DRM_FORMAT_MOD_LINEAR ||
13197                         modifier == I915_FORMAT_MOD_X_TILED;
13198         default:
13199                 return false;
13200         }
13201 }
13202
13203 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
13204 {
13205         switch (format) {
13206         case DRM_FORMAT_C8:
13207         case DRM_FORMAT_RGB565:
13208         case DRM_FORMAT_XRGB8888:
13209         case DRM_FORMAT_XBGR8888:
13210         case DRM_FORMAT_XRGB2101010:
13211         case DRM_FORMAT_XBGR2101010:
13212                 return modifier == DRM_FORMAT_MOD_LINEAR ||
13213                         modifier == I915_FORMAT_MOD_X_TILED;
13214         default:
13215                 return false;
13216         }
13217 }
13218
13219 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13220 {
13221         switch (format) {
13222         case DRM_FORMAT_XRGB8888:
13223         case DRM_FORMAT_XBGR8888:
13224         case DRM_FORMAT_ARGB8888:
13225         case DRM_FORMAT_ABGR8888:
13226                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13227                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13228                         return true;
13229                 /* fall through */
13230         case DRM_FORMAT_RGB565:
13231         case DRM_FORMAT_XRGB2101010:
13232         case DRM_FORMAT_XBGR2101010:
13233         case DRM_FORMAT_YUYV:
13234         case DRM_FORMAT_YVYU:
13235         case DRM_FORMAT_UYVY:
13236         case DRM_FORMAT_VYUY:
13237         case DRM_FORMAT_NV12:
13238                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13239                         return true;
13240                 /* fall through */
13241         case DRM_FORMAT_C8:
13242                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13243                     modifier == I915_FORMAT_MOD_X_TILED ||
13244                     modifier == I915_FORMAT_MOD_Y_TILED)
13245                         return true;
13246                 /* fall through */
13247         default:
13248                 return false;
13249         }
13250 }
13251
13252 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13253                                                      uint32_t format,
13254                                                      uint64_t modifier)
13255 {
13256         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13257
13258         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13259                 return false;
13260
13261         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13262             modifier != DRM_FORMAT_MOD_LINEAR)
13263                 return false;
13264
13265         if (INTEL_GEN(dev_priv) >= 9)
13266                 return skl_mod_supported(format, modifier);
13267         else if (INTEL_GEN(dev_priv) >= 4)
13268                 return i965_mod_supported(format, modifier);
13269         else
13270                 return i8xx_mod_supported(format, modifier);
13271 }
13272
13273 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13274                                                     uint32_t format,
13275                                                     uint64_t modifier)
13276 {
13277         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13278                 return false;
13279
13280         return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13281 }
13282
13283 static struct drm_plane_funcs intel_plane_funcs = {
13284         .update_plane = drm_atomic_helper_update_plane,
13285         .disable_plane = drm_atomic_helper_disable_plane,
13286         .destroy = intel_plane_destroy,
13287         .atomic_get_property = intel_plane_atomic_get_property,
13288         .atomic_set_property = intel_plane_atomic_set_property,
13289         .atomic_duplicate_state = intel_plane_duplicate_state,
13290         .atomic_destroy_state = intel_plane_destroy_state,
13291         .format_mod_supported = intel_primary_plane_format_mod_supported,
13292 };
13293
13294 static int
13295 intel_legacy_cursor_update(struct drm_plane *plane,
13296                            struct drm_crtc *crtc,
13297                            struct drm_framebuffer *fb,
13298                            int crtc_x, int crtc_y,
13299                            unsigned int crtc_w, unsigned int crtc_h,
13300                            uint32_t src_x, uint32_t src_y,
13301                            uint32_t src_w, uint32_t src_h,
13302                            struct drm_modeset_acquire_ctx *ctx)
13303 {
13304         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13305         int ret;
13306         struct drm_plane_state *old_plane_state, *new_plane_state;
13307         struct intel_plane *intel_plane = to_intel_plane(plane);
13308         struct drm_framebuffer *old_fb;
13309         struct drm_crtc_state *crtc_state = crtc->state;
13310
13311         /*
13312          * When crtc is inactive or there is a modeset pending,
13313          * wait for it to complete in the slowpath
13314          */
13315         if (!crtc_state->active || needs_modeset(crtc_state) ||
13316             to_intel_crtc_state(crtc_state)->update_pipe)
13317                 goto slow;
13318
13319         old_plane_state = plane->state;
13320         /*
13321          * Don't do an async update if there is an outstanding commit modifying
13322          * the plane.  This prevents our async update's changes from getting
13323          * overridden by a previous synchronous update's state.
13324          */
13325         if (old_plane_state->commit &&
13326             !try_wait_for_completion(&old_plane_state->commit->hw_done))
13327                 goto slow;
13328
13329         /*
13330          * If any parameters change that may affect watermarks,
13331          * take the slowpath. Only changing fb or position should be
13332          * in the fastpath.
13333          */
13334         if (old_plane_state->crtc != crtc ||
13335             old_plane_state->src_w != src_w ||
13336             old_plane_state->src_h != src_h ||
13337             old_plane_state->crtc_w != crtc_w ||
13338             old_plane_state->crtc_h != crtc_h ||
13339             !old_plane_state->fb != !fb)
13340                 goto slow;
13341
13342         new_plane_state = intel_plane_duplicate_state(plane);
13343         if (!new_plane_state)
13344                 return -ENOMEM;
13345
13346         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13347
13348         new_plane_state->src_x = src_x;
13349         new_plane_state->src_y = src_y;
13350         new_plane_state->src_w = src_w;
13351         new_plane_state->src_h = src_h;
13352         new_plane_state->crtc_x = crtc_x;
13353         new_plane_state->crtc_y = crtc_y;
13354         new_plane_state->crtc_w = crtc_w;
13355         new_plane_state->crtc_h = crtc_h;
13356
13357         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13358                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13359                                                   to_intel_plane_state(plane->state),
13360                                                   to_intel_plane_state(new_plane_state));
13361         if (ret)
13362                 goto out_free;
13363
13364         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13365         if (ret)
13366                 goto out_free;
13367
13368         ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
13369         if (ret)
13370                 goto out_unlock;
13371
13372         intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
13373
13374         old_fb = old_plane_state->fb;
13375         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13376                           intel_plane->frontbuffer_bit);
13377
13378         /* Swap plane state */
13379         plane->state = new_plane_state;
13380
13381         if (plane->state->visible) {
13382                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13383                 intel_plane->update_plane(intel_plane,
13384                                           to_intel_crtc_state(crtc->state),
13385                                           to_intel_plane_state(plane->state));
13386         } else {
13387                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13388                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13389         }
13390
13391         intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
13392
13393 out_unlock:
13394         mutex_unlock(&dev_priv->drm.struct_mutex);
13395 out_free:
13396         if (ret)
13397                 intel_plane_destroy_state(plane, new_plane_state);
13398         else
13399                 intel_plane_destroy_state(plane, old_plane_state);
13400         return ret;
13401
13402 slow:
13403         return drm_atomic_helper_update_plane(plane, crtc, fb,
13404                                               crtc_x, crtc_y, crtc_w, crtc_h,
13405                                               src_x, src_y, src_w, src_h, ctx);
13406 }
13407
13408 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13409         .update_plane = intel_legacy_cursor_update,
13410         .disable_plane = drm_atomic_helper_disable_plane,
13411         .destroy = intel_plane_destroy,
13412         .atomic_get_property = intel_plane_atomic_get_property,
13413         .atomic_set_property = intel_plane_atomic_set_property,
13414         .atomic_duplicate_state = intel_plane_duplicate_state,
13415         .atomic_destroy_state = intel_plane_destroy_state,
13416         .format_mod_supported = intel_cursor_plane_format_mod_supported,
13417 };
13418
13419 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13420                                enum i9xx_plane_id i9xx_plane)
13421 {
13422         if (!HAS_FBC(dev_priv))
13423                 return false;
13424
13425         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13426                 return i9xx_plane == PLANE_A; /* tied to pipe A */
13427         else if (IS_IVYBRIDGE(dev_priv))
13428                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13429                         i9xx_plane == PLANE_C;
13430         else if (INTEL_GEN(dev_priv) >= 4)
13431                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13432         else
13433                 return i9xx_plane == PLANE_A;
13434 }
13435
13436 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13437                               enum pipe pipe, enum plane_id plane_id)
13438 {
13439         if (!HAS_FBC(dev_priv))
13440                 return false;
13441
13442         return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13443 }
13444
13445 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
13446                           enum pipe pipe, enum plane_id plane_id)
13447 {
13448         if (plane_id == PLANE_PRIMARY) {
13449                 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13450                         return false;
13451                 else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
13452                          !IS_GEMINILAKE(dev_priv))
13453                         return false;
13454         } else if (plane_id >= PLANE_SPRITE0) {
13455                 if (plane_id == PLANE_CURSOR)
13456                         return false;
13457                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
13458                         if (plane_id != PLANE_SPRITE0)
13459                                 return false;
13460                 } else {
13461                         if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
13462                             IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13463                                 return false;
13464                 }
13465         }
13466         return true;
13467 }
13468
13469 static struct intel_plane *
13470 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13471 {
13472         struct intel_plane *primary = NULL;
13473         struct intel_plane_state *state = NULL;
13474         const uint32_t *intel_primary_formats;
13475         unsigned int supported_rotations;
13476         unsigned int num_formats;
13477         const uint64_t *modifiers;
13478         int ret;
13479
13480         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13481         if (!primary) {
13482                 ret = -ENOMEM;
13483                 goto fail;
13484         }
13485
13486         state = intel_create_plane_state(&primary->base);
13487         if (!state) {
13488                 ret = -ENOMEM;
13489                 goto fail;
13490         }
13491
13492         primary->base.state = &state->base;
13493
13494         primary->can_scale = false;
13495         primary->max_downscale = 1;
13496         if (INTEL_GEN(dev_priv) >= 9) {
13497                 primary->can_scale = true;
13498                 state->scaler_id = -1;
13499         }
13500         primary->pipe = pipe;
13501         /*
13502          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13503          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13504          */
13505         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13506                 primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
13507         else
13508                 primary->i9xx_plane = (enum i9xx_plane_id) pipe;
13509         primary->id = PLANE_PRIMARY;
13510         primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13511
13512         if (INTEL_GEN(dev_priv) >= 9)
13513                 primary->has_fbc = skl_plane_has_fbc(dev_priv,
13514                                                      primary->pipe,
13515                                                      primary->id);
13516         else
13517                 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13518                                                       primary->i9xx_plane);
13519
13520         if (primary->has_fbc) {
13521                 struct intel_fbc *fbc = &dev_priv->fbc;
13522
13523                 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13524         }
13525
13526         primary->check_plane = intel_check_primary_plane;
13527
13528         if (INTEL_GEN(dev_priv) >= 9) {
13529                 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
13530                         intel_primary_formats = skl_pri_planar_formats;
13531                         num_formats = ARRAY_SIZE(skl_pri_planar_formats);
13532                 } else {
13533                         intel_primary_formats = skl_primary_formats;
13534                         num_formats = ARRAY_SIZE(skl_primary_formats);
13535                 }
13536
13537                 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
13538                         modifiers = skl_format_modifiers_ccs;
13539                 else
13540                         modifiers = skl_format_modifiers_noccs;
13541
13542                 primary->update_plane = skl_update_plane;
13543                 primary->disable_plane = skl_disable_plane;
13544                 primary->get_hw_state = skl_plane_get_hw_state;
13545         } else if (INTEL_GEN(dev_priv) >= 4) {
13546                 intel_primary_formats = i965_primary_formats;
13547                 num_formats = ARRAY_SIZE(i965_primary_formats);
13548                 modifiers = i9xx_format_modifiers;
13549
13550                 primary->update_plane = i9xx_update_plane;
13551                 primary->disable_plane = i9xx_disable_plane;
13552                 primary->get_hw_state = i9xx_plane_get_hw_state;
13553         } else {
13554                 intel_primary_formats = i8xx_primary_formats;
13555                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13556                 modifiers = i9xx_format_modifiers;
13557
13558                 primary->update_plane = i9xx_update_plane;
13559                 primary->disable_plane = i9xx_disable_plane;
13560                 primary->get_hw_state = i9xx_plane_get_hw_state;
13561         }
13562
13563         if (INTEL_GEN(dev_priv) >= 9)
13564                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13565                                                0, &intel_plane_funcs,
13566                                                intel_primary_formats, num_formats,
13567                                                modifiers,
13568                                                DRM_PLANE_TYPE_PRIMARY,
13569                                                "plane 1%c", pipe_name(pipe));
13570         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13571                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13572                                                0, &intel_plane_funcs,
13573                                                intel_primary_formats, num_formats,
13574                                                modifiers,
13575                                                DRM_PLANE_TYPE_PRIMARY,
13576                                                "primary %c", pipe_name(pipe));
13577         else
13578                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13579                                                0, &intel_plane_funcs,
13580                                                intel_primary_formats, num_formats,
13581                                                modifiers,
13582                                                DRM_PLANE_TYPE_PRIMARY,
13583                                                "plane %c",
13584                                                plane_name(primary->i9xx_plane));
13585         if (ret)
13586                 goto fail;
13587
13588         if (INTEL_GEN(dev_priv) >= 10) {
13589                 supported_rotations =
13590                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13591                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13592                         DRM_MODE_REFLECT_X;
13593         } else if (INTEL_GEN(dev_priv) >= 9) {
13594                 supported_rotations =
13595                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13596                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13597         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13598                 supported_rotations =
13599                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13600                         DRM_MODE_REFLECT_X;
13601         } else if (INTEL_GEN(dev_priv) >= 4) {
13602                 supported_rotations =
13603                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13604         } else {
13605                 supported_rotations = DRM_MODE_ROTATE_0;
13606         }
13607
13608         if (INTEL_GEN(dev_priv) >= 4)
13609                 drm_plane_create_rotation_property(&primary->base,
13610                                                    DRM_MODE_ROTATE_0,
13611                                                    supported_rotations);
13612
13613         if (INTEL_GEN(dev_priv) >= 9)
13614                 drm_plane_create_color_properties(&primary->base,
13615                                                   BIT(DRM_COLOR_YCBCR_BT601) |
13616                                                   BIT(DRM_COLOR_YCBCR_BT709),
13617                                                   BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13618                                                   BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13619                                                   DRM_COLOR_YCBCR_BT709,
13620                                                   DRM_COLOR_YCBCR_LIMITED_RANGE);
13621
13622         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13623
13624         return primary;
13625
13626 fail:
13627         kfree(state);
13628         kfree(primary);
13629
13630         return ERR_PTR(ret);
13631 }
13632
13633 static struct intel_plane *
13634 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13635                           enum pipe pipe)
13636 {
13637         struct intel_plane *cursor = NULL;
13638         struct intel_plane_state *state = NULL;
13639         int ret;
13640
13641         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13642         if (!cursor) {
13643                 ret = -ENOMEM;
13644                 goto fail;
13645         }
13646
13647         state = intel_create_plane_state(&cursor->base);
13648         if (!state) {
13649                 ret = -ENOMEM;
13650                 goto fail;
13651         }
13652
13653         cursor->base.state = &state->base;
13654
13655         cursor->can_scale = false;
13656         cursor->max_downscale = 1;
13657         cursor->pipe = pipe;
13658         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
13659         cursor->id = PLANE_CURSOR;
13660         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
13661
13662         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13663                 cursor->update_plane = i845_update_cursor;
13664                 cursor->disable_plane = i845_disable_cursor;
13665                 cursor->get_hw_state = i845_cursor_get_hw_state;
13666                 cursor->check_plane = i845_check_cursor;
13667         } else {
13668                 cursor->update_plane = i9xx_update_cursor;
13669                 cursor->disable_plane = i9xx_disable_cursor;
13670                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
13671                 cursor->check_plane = i9xx_check_cursor;
13672         }
13673
13674         cursor->cursor.base = ~0;
13675         cursor->cursor.cntl = ~0;
13676
13677         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13678                 cursor->cursor.size = ~0;
13679
13680         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13681                                        0, &intel_cursor_plane_funcs,
13682                                        intel_cursor_formats,
13683                                        ARRAY_SIZE(intel_cursor_formats),
13684                                        cursor_format_modifiers,
13685                                        DRM_PLANE_TYPE_CURSOR,
13686                                        "cursor %c", pipe_name(pipe));
13687         if (ret)
13688                 goto fail;
13689
13690         if (INTEL_GEN(dev_priv) >= 4)
13691                 drm_plane_create_rotation_property(&cursor->base,
13692                                                    DRM_MODE_ROTATE_0,
13693                                                    DRM_MODE_ROTATE_0 |
13694                                                    DRM_MODE_ROTATE_180);
13695
13696         if (INTEL_GEN(dev_priv) >= 9)
13697                 state->scaler_id = -1;
13698
13699         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13700
13701         return cursor;
13702
13703 fail:
13704         kfree(state);
13705         kfree(cursor);
13706
13707         return ERR_PTR(ret);
13708 }
13709
13710 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13711                                     struct intel_crtc_state *crtc_state)
13712 {
13713         struct intel_crtc_scaler_state *scaler_state =
13714                 &crtc_state->scaler_state;
13715         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13716         int i;
13717
13718         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13719         if (!crtc->num_scalers)
13720                 return;
13721
13722         for (i = 0; i < crtc->num_scalers; i++) {
13723                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13724
13725                 scaler->in_use = 0;
13726                 scaler->mode = PS_SCALER_MODE_DYN;
13727         }
13728
13729         scaler_state->scaler_id = -1;
13730 }
13731
13732 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13733 {
13734         struct intel_crtc *intel_crtc;
13735         struct intel_crtc_state *crtc_state = NULL;
13736         struct intel_plane *primary = NULL;
13737         struct intel_plane *cursor = NULL;
13738         int sprite, ret;
13739
13740         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13741         if (!intel_crtc)
13742                 return -ENOMEM;
13743
13744         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13745         if (!crtc_state) {
13746                 ret = -ENOMEM;
13747                 goto fail;
13748         }
13749         intel_crtc->config = crtc_state;
13750         intel_crtc->base.state = &crtc_state->base;
13751         crtc_state->base.crtc = &intel_crtc->base;
13752
13753         primary = intel_primary_plane_create(dev_priv, pipe);
13754         if (IS_ERR(primary)) {
13755                 ret = PTR_ERR(primary);
13756                 goto fail;
13757         }
13758         intel_crtc->plane_ids_mask |= BIT(primary->id);
13759
13760         for_each_sprite(dev_priv, pipe, sprite) {
13761                 struct intel_plane *plane;
13762
13763                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13764                 if (IS_ERR(plane)) {
13765                         ret = PTR_ERR(plane);
13766                         goto fail;
13767                 }
13768                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13769         }
13770
13771         cursor = intel_cursor_plane_create(dev_priv, pipe);
13772         if (IS_ERR(cursor)) {
13773                 ret = PTR_ERR(cursor);
13774                 goto fail;
13775         }
13776         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13777
13778         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13779                                         &primary->base, &cursor->base,
13780                                         &intel_crtc_funcs,
13781                                         "pipe %c", pipe_name(pipe));
13782         if (ret)
13783                 goto fail;
13784
13785         intel_crtc->pipe = pipe;
13786
13787         /* initialize shared scalers */
13788         intel_crtc_init_scalers(intel_crtc, crtc_state);
13789
13790         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
13791                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
13792         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
13793
13794         if (INTEL_GEN(dev_priv) < 9) {
13795                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
13796
13797                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13798                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
13799                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
13800         }
13801
13802         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13803
13804         intel_color_init(&intel_crtc->base);
13805
13806         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13807
13808         return 0;
13809
13810 fail:
13811         /*
13812          * drm_mode_config_cleanup() will free up any
13813          * crtcs/planes already initialized.
13814          */
13815         kfree(crtc_state);
13816         kfree(intel_crtc);
13817
13818         return ret;
13819 }
13820
13821 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13822 {
13823         struct drm_device *dev = connector->base.dev;
13824
13825         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13826
13827         if (!connector->base.state->crtc)
13828                 return INVALID_PIPE;
13829
13830         return to_intel_crtc(connector->base.state->crtc)->pipe;
13831 }
13832
13833 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
13834                                       struct drm_file *file)
13835 {
13836         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13837         struct drm_crtc *drmmode_crtc;
13838         struct intel_crtc *crtc;
13839
13840         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13841         if (!drmmode_crtc)
13842                 return -ENOENT;
13843
13844         crtc = to_intel_crtc(drmmode_crtc);
13845         pipe_from_crtc_id->pipe = crtc->pipe;
13846
13847         return 0;
13848 }
13849
13850 static int intel_encoder_clones(struct intel_encoder *encoder)
13851 {
13852         struct drm_device *dev = encoder->base.dev;
13853         struct intel_encoder *source_encoder;
13854         int index_mask = 0;
13855         int entry = 0;
13856
13857         for_each_intel_encoder(dev, source_encoder) {
13858                 if (encoders_cloneable(encoder, source_encoder))
13859                         index_mask |= (1 << entry);
13860
13861                 entry++;
13862         }
13863
13864         return index_mask;
13865 }
13866
13867 static bool has_edp_a(struct drm_i915_private *dev_priv)
13868 {
13869         if (!IS_MOBILE(dev_priv))
13870                 return false;
13871
13872         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13873                 return false;
13874
13875         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13876                 return false;
13877
13878         return true;
13879 }
13880
13881 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13882 {
13883         if (INTEL_GEN(dev_priv) >= 9)
13884                 return false;
13885
13886         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13887                 return false;
13888
13889         if (IS_CHERRYVIEW(dev_priv))
13890                 return false;
13891
13892         if (HAS_PCH_LPT_H(dev_priv) &&
13893             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13894                 return false;
13895
13896         /* DDI E can't be used if DDI A requires 4 lanes */
13897         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13898                 return false;
13899
13900         if (!dev_priv->vbt.int_crt_support)
13901                 return false;
13902
13903         return true;
13904 }
13905
13906 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13907 {
13908         int pps_num;
13909         int pps_idx;
13910
13911         if (HAS_DDI(dev_priv))
13912                 return;
13913         /*
13914          * This w/a is needed at least on CPT/PPT, but to be sure apply it
13915          * everywhere where registers can be write protected.
13916          */
13917         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13918                 pps_num = 2;
13919         else
13920                 pps_num = 1;
13921
13922         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13923                 u32 val = I915_READ(PP_CONTROL(pps_idx));
13924
13925                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13926                 I915_WRITE(PP_CONTROL(pps_idx), val);
13927         }
13928 }
13929
13930 static void intel_pps_init(struct drm_i915_private *dev_priv)
13931 {
13932         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13933                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13934         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13935                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13936         else
13937                 dev_priv->pps_mmio_base = PPS_BASE;
13938
13939         intel_pps_unlock_regs_wa(dev_priv);
13940 }
13941
13942 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13943 {
13944         struct intel_encoder *encoder;
13945         bool dpd_is_edp = false;
13946
13947         intel_pps_init(dev_priv);
13948
13949         /*
13950          * intel_edp_init_connector() depends on this completing first, to
13951          * prevent the registeration of both eDP and LVDS and the incorrect
13952          * sharing of the PPS.
13953          */
13954         intel_lvds_init(dev_priv);
13955
13956         if (intel_crt_present(dev_priv))
13957                 intel_crt_init(dev_priv);
13958
13959         if (IS_GEN9_LP(dev_priv)) {
13960                 /*
13961                  * FIXME: Broxton doesn't support port detection via the
13962                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13963                  * detect the ports.
13964                  */
13965                 intel_ddi_init(dev_priv, PORT_A);
13966                 intel_ddi_init(dev_priv, PORT_B);
13967                 intel_ddi_init(dev_priv, PORT_C);
13968
13969                 intel_dsi_init(dev_priv);
13970         } else if (HAS_DDI(dev_priv)) {
13971                 int found;
13972
13973                 /*
13974                  * Haswell uses DDI functions to detect digital outputs.
13975                  * On SKL pre-D0 the strap isn't connected, so we assume
13976                  * it's there.
13977                  */
13978                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13979                 /* WaIgnoreDDIAStrap: skl */
13980                 if (found || IS_GEN9_BC(dev_priv))
13981                         intel_ddi_init(dev_priv, PORT_A);
13982
13983                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
13984                  * register */
13985                 found = I915_READ(SFUSE_STRAP);
13986
13987                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13988                         intel_ddi_init(dev_priv, PORT_B);
13989                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13990                         intel_ddi_init(dev_priv, PORT_C);
13991                 if (found & SFUSE_STRAP_DDID_DETECTED)
13992                         intel_ddi_init(dev_priv, PORT_D);
13993                 if (found & SFUSE_STRAP_DDIF_DETECTED)
13994                         intel_ddi_init(dev_priv, PORT_F);
13995                 /*
13996                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13997                  */
13998                 if (IS_GEN9_BC(dev_priv) &&
13999                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14000                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14001                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14002                         intel_ddi_init(dev_priv, PORT_E);
14003
14004         } else if (HAS_PCH_SPLIT(dev_priv)) {
14005                 int found;
14006                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14007
14008                 if (has_edp_a(dev_priv))
14009                         intel_dp_init(dev_priv, DP_A, PORT_A);
14010
14011                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14012                         /* PCH SDVOB multiplex with HDMIB */
14013                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14014                         if (!found)
14015                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14016                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14017                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14018                 }
14019
14020                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14021                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14022
14023                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14024                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14025
14026                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14027                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14028
14029                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14030                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14031         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14032                 bool has_edp, has_port;
14033
14034                 /*
14035                  * The DP_DETECTED bit is the latched state of the DDC
14036                  * SDA pin at boot. However since eDP doesn't require DDC
14037                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14038                  * eDP ports may have been muxed to an alternate function.
14039                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14040                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14041                  * detect eDP ports.
14042                  *
14043                  * Sadly the straps seem to be missing sometimes even for HDMI
14044                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14045                  * and VBT for the presence of the port. Additionally we can't
14046                  * trust the port type the VBT declares as we've seen at least
14047                  * HDMI ports that the VBT claim are DP or eDP.
14048                  */
14049                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14050                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14051                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14052                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14053                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14054                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14055
14056                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14057                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14058                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14059                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14060                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14061                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14062
14063                 if (IS_CHERRYVIEW(dev_priv)) {
14064                         /*
14065                          * eDP not supported on port D,
14066                          * so no need to worry about it
14067                          */
14068                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14069                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14070                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14071                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14072                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14073                 }
14074
14075                 intel_dsi_init(dev_priv);
14076         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14077                 bool found = false;
14078
14079                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14080                         DRM_DEBUG_KMS("probing SDVOB\n");
14081                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14082                         if (!found && IS_G4X(dev_priv)) {
14083                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14084                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14085                         }
14086
14087                         if (!found && IS_G4X(dev_priv))
14088                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14089                 }
14090
14091                 /* Before G4X SDVOC doesn't have its own detect register */
14092
14093                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14094                         DRM_DEBUG_KMS("probing SDVOC\n");
14095                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14096                 }
14097
14098                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14099
14100                         if (IS_G4X(dev_priv)) {
14101                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14102                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14103                         }
14104                         if (IS_G4X(dev_priv))
14105                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14106                 }
14107
14108                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14109                         intel_dp_init(dev_priv, DP_D, PORT_D);
14110         } else if (IS_GEN2(dev_priv))
14111                 intel_dvo_init(dev_priv);
14112
14113         if (SUPPORTS_TV(dev_priv))
14114                 intel_tv_init(dev_priv);
14115
14116         intel_psr_init(dev_priv);
14117
14118         for_each_intel_encoder(&dev_priv->drm, encoder) {
14119                 encoder->base.possible_crtcs = encoder->crtc_mask;
14120                 encoder->base.possible_clones =
14121                         intel_encoder_clones(encoder);
14122         }
14123
14124         intel_init_pch_refclk(dev_priv);
14125
14126         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14127 }
14128
14129 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14130 {
14131         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14132
14133         drm_framebuffer_cleanup(fb);
14134
14135         i915_gem_object_lock(intel_fb->obj);
14136         WARN_ON(!intel_fb->obj->framebuffer_references--);
14137         i915_gem_object_unlock(intel_fb->obj);
14138
14139         i915_gem_object_put(intel_fb->obj);
14140
14141         kfree(intel_fb);
14142 }
14143
14144 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14145                                                 struct drm_file *file,
14146                                                 unsigned int *handle)
14147 {
14148         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14149         struct drm_i915_gem_object *obj = intel_fb->obj;
14150
14151         if (obj->userptr.mm) {
14152                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14153                 return -EINVAL;
14154         }
14155
14156         return drm_gem_handle_create(file, &obj->base, handle);
14157 }
14158
14159 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14160                                         struct drm_file *file,
14161                                         unsigned flags, unsigned color,
14162                                         struct drm_clip_rect *clips,
14163                                         unsigned num_clips)
14164 {
14165         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14166
14167         i915_gem_object_flush_if_display(obj);
14168         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14169
14170         return 0;
14171 }
14172
14173 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14174         .destroy = intel_user_framebuffer_destroy,
14175         .create_handle = intel_user_framebuffer_create_handle,
14176         .dirty = intel_user_framebuffer_dirty,
14177 };
14178
14179 static
14180 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14181                          uint64_t fb_modifier, uint32_t pixel_format)
14182 {
14183         u32 gen = INTEL_GEN(dev_priv);
14184
14185         if (gen >= 9) {
14186                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14187
14188                 /* "The stride in bytes must not exceed the of the size of 8K
14189                  *  pixels and 32K bytes."
14190                  */
14191                 return min(8192 * cpp, 32768);
14192         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14193                 return 32*1024;
14194         } else if (gen >= 4) {
14195                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14196                         return 16*1024;
14197                 else
14198                         return 32*1024;
14199         } else if (gen >= 3) {
14200                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14201                         return 8*1024;
14202                 else
14203                         return 16*1024;
14204         } else {
14205                 /* XXX DSPC is limited to 4k tiled */
14206                 return 8*1024;
14207         }
14208 }
14209
14210 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14211                                   struct drm_i915_gem_object *obj,
14212                                   struct drm_mode_fb_cmd2 *mode_cmd)
14213 {
14214         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14215         struct drm_framebuffer *fb = &intel_fb->base;
14216         struct drm_format_name_buf format_name;
14217         u32 pitch_limit;
14218         unsigned int tiling, stride;
14219         int ret = -EINVAL;
14220         int i;
14221
14222         i915_gem_object_lock(obj);
14223         obj->framebuffer_references++;
14224         tiling = i915_gem_object_get_tiling(obj);
14225         stride = i915_gem_object_get_stride(obj);
14226         i915_gem_object_unlock(obj);
14227
14228         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14229                 /*
14230                  * If there's a fence, enforce that
14231                  * the fb modifier and tiling mode match.
14232                  */
14233                 if (tiling != I915_TILING_NONE &&
14234                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14235                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14236                         goto err;
14237                 }
14238         } else {
14239                 if (tiling == I915_TILING_X) {
14240                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14241                 } else if (tiling == I915_TILING_Y) {
14242                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14243                         goto err;
14244                 }
14245         }
14246
14247         /* Passed in modifier sanity checking. */
14248         switch (mode_cmd->modifier[0]) {
14249         case I915_FORMAT_MOD_Y_TILED_CCS:
14250         case I915_FORMAT_MOD_Yf_TILED_CCS:
14251                 switch (mode_cmd->pixel_format) {
14252                 case DRM_FORMAT_XBGR8888:
14253                 case DRM_FORMAT_ABGR8888:
14254                 case DRM_FORMAT_XRGB8888:
14255                 case DRM_FORMAT_ARGB8888:
14256                         break;
14257                 default:
14258                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
14259                         goto err;
14260                 }
14261                 /* fall through */
14262         case I915_FORMAT_MOD_Y_TILED:
14263         case I915_FORMAT_MOD_Yf_TILED:
14264                 if (INTEL_GEN(dev_priv) < 9) {
14265                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14266                                       mode_cmd->modifier[0]);
14267                         goto err;
14268                 }
14269         case DRM_FORMAT_MOD_LINEAR:
14270         case I915_FORMAT_MOD_X_TILED:
14271                 break;
14272         default:
14273                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14274                               mode_cmd->modifier[0]);
14275                 goto err;
14276         }
14277
14278         /*
14279          * gen2/3 display engine uses the fence if present,
14280          * so the tiling mode must match the fb modifier exactly.
14281          */
14282         if (INTEL_GEN(dev_priv) < 4 &&
14283             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14284                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14285                 goto err;
14286         }
14287
14288         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14289                                            mode_cmd->pixel_format);
14290         if (mode_cmd->pitches[0] > pitch_limit) {
14291                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14292                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14293                               "tiled" : "linear",
14294                               mode_cmd->pitches[0], pitch_limit);
14295                 goto err;
14296         }
14297
14298         /*
14299          * If there's a fence, enforce that
14300          * the fb pitch and fence stride match.
14301          */
14302         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14303                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14304                               mode_cmd->pitches[0], stride);
14305                 goto err;
14306         }
14307
14308         /* Reject formats not supported by any plane early. */
14309         switch (mode_cmd->pixel_format) {
14310         case DRM_FORMAT_C8:
14311         case DRM_FORMAT_RGB565:
14312         case DRM_FORMAT_XRGB8888:
14313         case DRM_FORMAT_ARGB8888:
14314                 break;
14315         case DRM_FORMAT_XRGB1555:
14316                 if (INTEL_GEN(dev_priv) > 3) {
14317                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14318                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14319                         goto err;
14320                 }
14321                 break;
14322         case DRM_FORMAT_ABGR8888:
14323                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14324                     INTEL_GEN(dev_priv) < 9) {
14325                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14326                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14327                         goto err;
14328                 }
14329                 break;
14330         case DRM_FORMAT_XBGR8888:
14331         case DRM_FORMAT_XRGB2101010:
14332         case DRM_FORMAT_XBGR2101010:
14333                 if (INTEL_GEN(dev_priv) < 4) {
14334                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14335                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14336                         goto err;
14337                 }
14338                 break;
14339         case DRM_FORMAT_ABGR2101010:
14340                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14341                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14342                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14343                         goto err;
14344                 }
14345                 break;
14346         case DRM_FORMAT_YUYV:
14347         case DRM_FORMAT_UYVY:
14348         case DRM_FORMAT_YVYU:
14349         case DRM_FORMAT_VYUY:
14350                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14351                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14352                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14353                         goto err;
14354                 }
14355                 break;
14356         case DRM_FORMAT_NV12:
14357                 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
14358                     mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
14359                         DRM_DEBUG_KMS("RC not to be enabled with NV12\n");
14360                         goto err;
14361                 }
14362                 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
14363                     IS_BROXTON(dev_priv)) {
14364                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14365                                       drm_get_format_name(mode_cmd->pixel_format,
14366                                                           &format_name));
14367                         goto err;
14368                 }
14369                 break;
14370         default:
14371                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14372                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14373                 goto err;
14374         }
14375
14376         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14377         if (mode_cmd->offsets[0] != 0)
14378                 goto err;
14379
14380         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14381
14382         if (fb->format->format == DRM_FORMAT_NV12 &&
14383             (fb->width < SKL_MIN_YUV_420_SRC_W ||
14384              fb->height < SKL_MIN_YUV_420_SRC_H ||
14385              (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14386                 DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14387                 return -EINVAL;
14388         }
14389
14390         for (i = 0; i < fb->format->num_planes; i++) {
14391                 u32 stride_alignment;
14392
14393                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14394                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14395                         goto err;
14396                 }
14397
14398                 stride_alignment = intel_fb_stride_alignment(fb, i);
14399
14400                 /*
14401                  * Display WA #0531: skl,bxt,kbl,glk
14402                  *
14403                  * Render decompression and plane width > 3840
14404                  * combined with horizontal panning requires the
14405                  * plane stride to be a multiple of 4. We'll just
14406                  * require the entire fb to accommodate that to avoid
14407                  * potential runtime errors at plane configuration time.
14408                  */
14409                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14410                     (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14411                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14412                         stride_alignment *= 4;
14413
14414                 if (fb->pitches[i] & (stride_alignment - 1)) {
14415                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14416                                       i, fb->pitches[i], stride_alignment);
14417                         goto err;
14418                 }
14419         }
14420
14421         intel_fb->obj = obj;
14422
14423         ret = intel_fill_fb_info(dev_priv, fb);
14424         if (ret)
14425                 goto err;
14426
14427         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14428         if (ret) {
14429                 DRM_ERROR("framebuffer init failed %d\n", ret);
14430                 goto err;
14431         }
14432
14433         return 0;
14434
14435 err:
14436         i915_gem_object_lock(obj);
14437         obj->framebuffer_references--;
14438         i915_gem_object_unlock(obj);
14439         return ret;
14440 }
14441
14442 static struct drm_framebuffer *
14443 intel_user_framebuffer_create(struct drm_device *dev,
14444                               struct drm_file *filp,
14445                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14446 {
14447         struct drm_framebuffer *fb;
14448         struct drm_i915_gem_object *obj;
14449         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14450
14451         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14452         if (!obj)
14453                 return ERR_PTR(-ENOENT);
14454
14455         fb = intel_framebuffer_create(obj, &mode_cmd);
14456         if (IS_ERR(fb))
14457                 i915_gem_object_put(obj);
14458
14459         return fb;
14460 }
14461
14462 static void intel_atomic_state_free(struct drm_atomic_state *state)
14463 {
14464         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14465
14466         drm_atomic_state_default_release(state);
14467
14468         i915_sw_fence_fini(&intel_state->commit_ready);
14469
14470         kfree(state);
14471 }
14472
14473 static enum drm_mode_status
14474 intel_mode_valid(struct drm_device *dev,
14475                  const struct drm_display_mode *mode)
14476 {
14477         if (mode->vscan > 1)
14478                 return MODE_NO_VSCAN;
14479
14480         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
14481                 return MODE_NO_DBLESCAN;
14482
14483         if (mode->flags & DRM_MODE_FLAG_HSKEW)
14484                 return MODE_H_ILLEGAL;
14485
14486         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14487                            DRM_MODE_FLAG_NCSYNC |
14488                            DRM_MODE_FLAG_PCSYNC))
14489                 return MODE_HSYNC;
14490
14491         if (mode->flags & (DRM_MODE_FLAG_BCAST |
14492                            DRM_MODE_FLAG_PIXMUX |
14493                            DRM_MODE_FLAG_CLKDIV2))
14494                 return MODE_BAD;
14495
14496         return MODE_OK;
14497 }
14498
14499 static const struct drm_mode_config_funcs intel_mode_funcs = {
14500         .fb_create = intel_user_framebuffer_create,
14501         .get_format_info = intel_get_format_info,
14502         .output_poll_changed = intel_fbdev_output_poll_changed,
14503         .mode_valid = intel_mode_valid,
14504         .atomic_check = intel_atomic_check,
14505         .atomic_commit = intel_atomic_commit,
14506         .atomic_state_alloc = intel_atomic_state_alloc,
14507         .atomic_state_clear = intel_atomic_state_clear,
14508         .atomic_state_free = intel_atomic_state_free,
14509 };
14510
14511 /**
14512  * intel_init_display_hooks - initialize the display modesetting hooks
14513  * @dev_priv: device private
14514  */
14515 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14516 {
14517         intel_init_cdclk_hooks(dev_priv);
14518
14519         if (INTEL_GEN(dev_priv) >= 9) {
14520                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14521                 dev_priv->display.get_initial_plane_config =
14522                         skylake_get_initial_plane_config;
14523                 dev_priv->display.crtc_compute_clock =
14524                         haswell_crtc_compute_clock;
14525                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14526                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14527         } else if (HAS_DDI(dev_priv)) {
14528                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14529                 dev_priv->display.get_initial_plane_config =
14530                         i9xx_get_initial_plane_config;
14531                 dev_priv->display.crtc_compute_clock =
14532                         haswell_crtc_compute_clock;
14533                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14534                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14535         } else if (HAS_PCH_SPLIT(dev_priv)) {
14536                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14537                 dev_priv->display.get_initial_plane_config =
14538                         i9xx_get_initial_plane_config;
14539                 dev_priv->display.crtc_compute_clock =
14540                         ironlake_crtc_compute_clock;
14541                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14542                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14543         } else if (IS_CHERRYVIEW(dev_priv)) {
14544                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14545                 dev_priv->display.get_initial_plane_config =
14546                         i9xx_get_initial_plane_config;
14547                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14548                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14549                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14550         } else if (IS_VALLEYVIEW(dev_priv)) {
14551                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14552                 dev_priv->display.get_initial_plane_config =
14553                         i9xx_get_initial_plane_config;
14554                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14555                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14556                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14557         } else if (IS_G4X(dev_priv)) {
14558                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14559                 dev_priv->display.get_initial_plane_config =
14560                         i9xx_get_initial_plane_config;
14561                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14562                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14563                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14564         } else if (IS_PINEVIEW(dev_priv)) {
14565                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14566                 dev_priv->display.get_initial_plane_config =
14567                         i9xx_get_initial_plane_config;
14568                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14569                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14570                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14571         } else if (!IS_GEN2(dev_priv)) {
14572                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14573                 dev_priv->display.get_initial_plane_config =
14574                         i9xx_get_initial_plane_config;
14575                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14576                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14577                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14578         } else {
14579                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14580                 dev_priv->display.get_initial_plane_config =
14581                         i9xx_get_initial_plane_config;
14582                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14583                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14584                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14585         }
14586
14587         if (IS_GEN5(dev_priv)) {
14588                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14589         } else if (IS_GEN6(dev_priv)) {
14590                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14591         } else if (IS_IVYBRIDGE(dev_priv)) {
14592                 /* FIXME: detect B0+ stepping and use auto training */
14593                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14594         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14595                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14596         }
14597
14598         if (INTEL_GEN(dev_priv) >= 9)
14599                 dev_priv->display.update_crtcs = skl_update_crtcs;
14600         else
14601                 dev_priv->display.update_crtcs = intel_update_crtcs;
14602 }
14603
14604 /*
14605  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14606  */
14607 static void quirk_ssc_force_disable(struct drm_device *dev)
14608 {
14609         struct drm_i915_private *dev_priv = to_i915(dev);
14610         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14611         DRM_INFO("applying lvds SSC disable quirk\n");
14612 }
14613
14614 /*
14615  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14616  * brightness value
14617  */
14618 static void quirk_invert_brightness(struct drm_device *dev)
14619 {
14620         struct drm_i915_private *dev_priv = to_i915(dev);
14621         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14622         DRM_INFO("applying inverted panel brightness quirk\n");
14623 }
14624
14625 /* Some VBT's incorrectly indicate no backlight is present */
14626 static void quirk_backlight_present(struct drm_device *dev)
14627 {
14628         struct drm_i915_private *dev_priv = to_i915(dev);
14629         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14630         DRM_INFO("applying backlight present quirk\n");
14631 }
14632
14633 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14634  * which is 300 ms greater than eDP spec T12 min.
14635  */
14636 static void quirk_increase_t12_delay(struct drm_device *dev)
14637 {
14638         struct drm_i915_private *dev_priv = to_i915(dev);
14639
14640         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14641         DRM_INFO("Applying T12 delay quirk\n");
14642 }
14643
14644 struct intel_quirk {
14645         int device;
14646         int subsystem_vendor;
14647         int subsystem_device;
14648         void (*hook)(struct drm_device *dev);
14649 };
14650
14651 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14652 struct intel_dmi_quirk {
14653         void (*hook)(struct drm_device *dev);
14654         const struct dmi_system_id (*dmi_id_list)[];
14655 };
14656
14657 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14658 {
14659         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14660         return 1;
14661 }
14662
14663 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14664         {
14665                 .dmi_id_list = &(const struct dmi_system_id[]) {
14666                         {
14667                                 .callback = intel_dmi_reverse_brightness,
14668                                 .ident = "NCR Corporation",
14669                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14670                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14671                                 },
14672                         },
14673                         { }  /* terminating entry */
14674                 },
14675                 .hook = quirk_invert_brightness,
14676         },
14677 };
14678
14679 static struct intel_quirk intel_quirks[] = {
14680         /* Lenovo U160 cannot use SSC on LVDS */
14681         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14682
14683         /* Sony Vaio Y cannot use SSC on LVDS */
14684         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14685
14686         /* Acer Aspire 5734Z must invert backlight brightness */
14687         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14688
14689         /* Acer/eMachines G725 */
14690         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14691
14692         /* Acer/eMachines e725 */
14693         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14694
14695         /* Acer/Packard Bell NCL20 */
14696         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14697
14698         /* Acer Aspire 4736Z */
14699         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14700
14701         /* Acer Aspire 5336 */
14702         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14703
14704         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14705         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14706
14707         /* Acer C720 Chromebook (Core i3 4005U) */
14708         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14709
14710         /* Apple Macbook 2,1 (Core 2 T7400) */
14711         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14712
14713         /* Apple Macbook 4,1 */
14714         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14715
14716         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14717         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14718
14719         /* HP Chromebook 14 (Celeron 2955U) */
14720         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14721
14722         /* Dell Chromebook 11 */
14723         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14724
14725         /* Dell Chromebook 11 (2015 version) */
14726         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14727
14728         /* Toshiba Satellite P50-C-18C */
14729         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14730 };
14731
14732 static void intel_init_quirks(struct drm_device *dev)
14733 {
14734         struct pci_dev *d = dev->pdev;
14735         int i;
14736
14737         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14738                 struct intel_quirk *q = &intel_quirks[i];
14739
14740                 if (d->device == q->device &&
14741                     (d->subsystem_vendor == q->subsystem_vendor ||
14742                      q->subsystem_vendor == PCI_ANY_ID) &&
14743                     (d->subsystem_device == q->subsystem_device ||
14744                      q->subsystem_device == PCI_ANY_ID))
14745                         q->hook(dev);
14746         }
14747         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14748                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14749                         intel_dmi_quirks[i].hook(dev);
14750         }
14751 }
14752
14753 /* Disable the VGA plane that we never use */
14754 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14755 {
14756         struct pci_dev *pdev = dev_priv->drm.pdev;
14757         u8 sr1;
14758         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14759
14760         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14761         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14762         outb(SR01, VGA_SR_INDEX);
14763         sr1 = inb(VGA_SR_DATA);
14764         outb(sr1 | 1<<5, VGA_SR_DATA);
14765         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14766         udelay(300);
14767
14768         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14769         POSTING_READ(vga_reg);
14770 }
14771
14772 void intel_modeset_init_hw(struct drm_device *dev)
14773 {
14774         struct drm_i915_private *dev_priv = to_i915(dev);
14775
14776         intel_update_cdclk(dev_priv);
14777         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
14778         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14779 }
14780
14781 /*
14782  * Calculate what we think the watermarks should be for the state we've read
14783  * out of the hardware and then immediately program those watermarks so that
14784  * we ensure the hardware settings match our internal state.
14785  *
14786  * We can calculate what we think WM's should be by creating a duplicate of the
14787  * current state (which was constructed during hardware readout) and running it
14788  * through the atomic check code to calculate new watermark values in the
14789  * state object.
14790  */
14791 static void sanitize_watermarks(struct drm_device *dev)
14792 {
14793         struct drm_i915_private *dev_priv = to_i915(dev);
14794         struct drm_atomic_state *state;
14795         struct intel_atomic_state *intel_state;
14796         struct drm_crtc *crtc;
14797         struct drm_crtc_state *cstate;
14798         struct drm_modeset_acquire_ctx ctx;
14799         int ret;
14800         int i;
14801
14802         /* Only supported on platforms that use atomic watermark design */
14803         if (!dev_priv->display.optimize_watermarks)
14804                 return;
14805
14806         /*
14807          * We need to hold connection_mutex before calling duplicate_state so
14808          * that the connector loop is protected.
14809          */
14810         drm_modeset_acquire_init(&ctx, 0);
14811 retry:
14812         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14813         if (ret == -EDEADLK) {
14814                 drm_modeset_backoff(&ctx);
14815                 goto retry;
14816         } else if (WARN_ON(ret)) {
14817                 goto fail;
14818         }
14819
14820         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14821         if (WARN_ON(IS_ERR(state)))
14822                 goto fail;
14823
14824         intel_state = to_intel_atomic_state(state);
14825
14826         /*
14827          * Hardware readout is the only time we don't want to calculate
14828          * intermediate watermarks (since we don't trust the current
14829          * watermarks).
14830          */
14831         if (!HAS_GMCH_DISPLAY(dev_priv))
14832                 intel_state->skip_intermediate_wm = true;
14833
14834         ret = intel_atomic_check(dev, state);
14835         if (ret) {
14836                 /*
14837                  * If we fail here, it means that the hardware appears to be
14838                  * programmed in a way that shouldn't be possible, given our
14839                  * understanding of watermark requirements.  This might mean a
14840                  * mistake in the hardware readout code or a mistake in the
14841                  * watermark calculations for a given platform.  Raise a WARN
14842                  * so that this is noticeable.
14843                  *
14844                  * If this actually happens, we'll have to just leave the
14845                  * BIOS-programmed watermarks untouched and hope for the best.
14846                  */
14847                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14848                 goto put_state;
14849         }
14850
14851         /* Write calculated watermark values back */
14852         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14853                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14854
14855                 cs->wm.need_postvbl_update = true;
14856                 dev_priv->display.optimize_watermarks(intel_state, cs);
14857
14858                 to_intel_crtc_state(crtc->state)->wm = cs->wm;
14859         }
14860
14861 put_state:
14862         drm_atomic_state_put(state);
14863 fail:
14864         drm_modeset_drop_locks(&ctx);
14865         drm_modeset_acquire_fini(&ctx);
14866 }
14867
14868 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14869 {
14870         if (IS_GEN5(dev_priv)) {
14871                 u32 fdi_pll_clk =
14872                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14873
14874                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14875         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
14876                 dev_priv->fdi_pll_freq = 270000;
14877         } else {
14878                 return;
14879         }
14880
14881         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
14882 }
14883
14884 int intel_modeset_init(struct drm_device *dev)
14885 {
14886         struct drm_i915_private *dev_priv = to_i915(dev);
14887         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14888         enum pipe pipe;
14889         struct intel_crtc *crtc;
14890
14891         dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
14892
14893         drm_mode_config_init(dev);
14894
14895         dev->mode_config.min_width = 0;
14896         dev->mode_config.min_height = 0;
14897
14898         dev->mode_config.preferred_depth = 24;
14899         dev->mode_config.prefer_shadow = 1;
14900
14901         dev->mode_config.allow_fb_modifiers = true;
14902
14903         dev->mode_config.funcs = &intel_mode_funcs;
14904
14905         init_llist_head(&dev_priv->atomic_helper.free_list);
14906         INIT_WORK(&dev_priv->atomic_helper.free_work,
14907                   intel_atomic_helper_free_state_worker);
14908
14909         intel_init_quirks(dev);
14910
14911         intel_init_pm(dev_priv);
14912
14913         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14914                 return 0;
14915
14916         /*
14917          * There may be no VBT; and if the BIOS enabled SSC we can
14918          * just keep using it to avoid unnecessary flicker.  Whereas if the
14919          * BIOS isn't using it, don't assume it will work even if the VBT
14920          * indicates as much.
14921          */
14922         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14923                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14924                                             DREF_SSC1_ENABLE);
14925
14926                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14927                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14928                                      bios_lvds_use_ssc ? "en" : "dis",
14929                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14930                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14931                 }
14932         }
14933
14934         if (IS_GEN2(dev_priv)) {
14935                 dev->mode_config.max_width = 2048;
14936                 dev->mode_config.max_height = 2048;
14937         } else if (IS_GEN3(dev_priv)) {
14938                 dev->mode_config.max_width = 4096;
14939                 dev->mode_config.max_height = 4096;
14940         } else {
14941                 dev->mode_config.max_width = 8192;
14942                 dev->mode_config.max_height = 8192;
14943         }
14944
14945         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14946                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14947                 dev->mode_config.cursor_height = 1023;
14948         } else if (IS_GEN2(dev_priv)) {
14949                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14950                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14951         } else {
14952                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14953                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14954         }
14955
14956         dev->mode_config.fb_base = ggtt->gmadr.start;
14957
14958         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14959                       INTEL_INFO(dev_priv)->num_pipes,
14960                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14961
14962         for_each_pipe(dev_priv, pipe) {
14963                 int ret;
14964
14965                 ret = intel_crtc_init(dev_priv, pipe);
14966                 if (ret) {
14967                         drm_mode_config_cleanup(dev);
14968                         return ret;
14969                 }
14970         }
14971
14972         intel_shared_dpll_init(dev);
14973         intel_update_fdi_pll_freq(dev_priv);
14974
14975         intel_update_czclk(dev_priv);
14976         intel_modeset_init_hw(dev);
14977
14978         if (dev_priv->max_cdclk_freq == 0)
14979                 intel_update_max_cdclk(dev_priv);
14980
14981         /* Just disable it once at startup */
14982         i915_disable_vga(dev_priv);
14983         intel_setup_outputs(dev_priv);
14984
14985         drm_modeset_lock_all(dev);
14986         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14987         drm_modeset_unlock_all(dev);
14988
14989         for_each_intel_crtc(dev, crtc) {
14990                 struct intel_initial_plane_config plane_config = {};
14991
14992                 if (!crtc->active)
14993                         continue;
14994
14995                 /*
14996                  * Note that reserving the BIOS fb up front prevents us
14997                  * from stuffing other stolen allocations like the ring
14998                  * on top.  This prevents some ugliness at boot time, and
14999                  * can even allow for smooth boot transitions if the BIOS
15000                  * fb is large enough for the active pipe configuration.
15001                  */
15002                 dev_priv->display.get_initial_plane_config(crtc,
15003                                                            &plane_config);
15004
15005                 /*
15006                  * If the fb is shared between multiple heads, we'll
15007                  * just get the first one.
15008                  */
15009                 intel_find_initial_plane_obj(crtc, &plane_config);
15010         }
15011
15012         /*
15013          * Make sure hardware watermarks really match the state we read out.
15014          * Note that we need to do this after reconstructing the BIOS fb's
15015          * since the watermark calculation done here will use pstate->fb.
15016          */
15017         if (!HAS_GMCH_DISPLAY(dev_priv))
15018                 sanitize_watermarks(dev);
15019
15020         return 0;
15021 }
15022
15023 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15024 {
15025         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15026         /* 640x480@60Hz, ~25175 kHz */
15027         struct dpll clock = {
15028                 .m1 = 18,
15029                 .m2 = 7,
15030                 .p1 = 13,
15031                 .p2 = 4,
15032                 .n = 2,
15033         };
15034         u32 dpll, fp;
15035         int i;
15036
15037         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15038
15039         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15040                       pipe_name(pipe), clock.vco, clock.dot);
15041
15042         fp = i9xx_dpll_compute_fp(&clock);
15043         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15044                 DPLL_VGA_MODE_DIS |
15045                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15046                 PLL_P2_DIVIDE_BY_4 |
15047                 PLL_REF_INPUT_DREFCLK |
15048                 DPLL_VCO_ENABLE;
15049
15050         I915_WRITE(FP0(pipe), fp);
15051         I915_WRITE(FP1(pipe), fp);
15052
15053         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15054         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15055         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15056         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15057         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15058         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15059         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15060
15061         /*
15062          * Apparently we need to have VGA mode enabled prior to changing
15063          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15064          * dividers, even though the register value does change.
15065          */
15066         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15067         I915_WRITE(DPLL(pipe), dpll);
15068
15069         /* Wait for the clocks to stabilize. */
15070         POSTING_READ(DPLL(pipe));
15071         udelay(150);
15072
15073         /* The pixel multiplier can only be updated once the
15074          * DPLL is enabled and the clocks are stable.
15075          *
15076          * So write it again.
15077          */
15078         I915_WRITE(DPLL(pipe), dpll);
15079
15080         /* We do this three times for luck */
15081         for (i = 0; i < 3 ; i++) {
15082                 I915_WRITE(DPLL(pipe), dpll);
15083                 POSTING_READ(DPLL(pipe));
15084                 udelay(150); /* wait for warmup */
15085         }
15086
15087         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15088         POSTING_READ(PIPECONF(pipe));
15089
15090         intel_wait_for_pipe_scanline_moving(crtc);
15091 }
15092
15093 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15094 {
15095         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15096
15097         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15098                       pipe_name(pipe));
15099
15100         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15101         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15102         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15103         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
15104         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
15105
15106         I915_WRITE(PIPECONF(pipe), 0);
15107         POSTING_READ(PIPECONF(pipe));
15108
15109         intel_wait_for_pipe_scanline_stopped(crtc);
15110
15111         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15112         POSTING_READ(DPLL(pipe));
15113 }
15114
15115 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
15116                                    struct intel_plane *plane)
15117 {
15118         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15119         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
15120         u32 val = I915_READ(DSPCNTR(i9xx_plane));
15121
15122         return (val & DISPLAY_PLANE_ENABLE) == 0 ||
15123                 (val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
15124 }
15125
15126 static void
15127 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15128 {
15129         struct intel_crtc *crtc;
15130
15131         if (INTEL_GEN(dev_priv) >= 4)
15132                 return;
15133
15134         for_each_intel_crtc(&dev_priv->drm, crtc) {
15135                 struct intel_plane *plane =
15136                         to_intel_plane(crtc->base.primary);
15137
15138                 if (intel_plane_mapping_ok(crtc, plane))
15139                         continue;
15140
15141                 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
15142                               plane->base.name);
15143                 intel_plane_disable_noatomic(crtc, plane);
15144         }
15145 }
15146
15147 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15148 {
15149         struct drm_device *dev = crtc->base.dev;
15150         struct intel_encoder *encoder;
15151
15152         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15153                 return true;
15154
15155         return false;
15156 }
15157
15158 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15159 {
15160         struct drm_device *dev = encoder->base.dev;
15161         struct intel_connector *connector;
15162
15163         for_each_connector_on_encoder(dev, &encoder->base, connector)
15164                 return connector;
15165
15166         return NULL;
15167 }
15168
15169 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15170                               enum pipe pch_transcoder)
15171 {
15172         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15173                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15174 }
15175
15176 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15177                                 struct drm_modeset_acquire_ctx *ctx)
15178 {
15179         struct drm_device *dev = crtc->base.dev;
15180         struct drm_i915_private *dev_priv = to_i915(dev);
15181         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15182
15183         /* Clear any frame start delays used for debugging left by the BIOS */
15184         if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15185                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15186
15187                 I915_WRITE(reg,
15188                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15189         }
15190
15191         /* restore vblank interrupts to correct state */
15192         drm_crtc_vblank_reset(&crtc->base);
15193         if (crtc->active) {
15194                 struct intel_plane *plane;
15195
15196                 drm_crtc_vblank_on(&crtc->base);
15197
15198                 /* Disable everything but the primary plane */
15199                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15200                         const struct intel_plane_state *plane_state =
15201                                 to_intel_plane_state(plane->base.state);
15202
15203                         if (plane_state->base.visible &&
15204                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15205                                 intel_plane_disable_noatomic(crtc, plane);
15206                 }
15207         }
15208
15209         /* Adjust the state of the output pipe according to whether we
15210          * have active connectors/encoders. */
15211         if (crtc->active && !intel_crtc_has_encoders(crtc))
15212                 intel_crtc_disable_noatomic(&crtc->base, ctx);
15213
15214         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15215                 /*
15216                  * We start out with underrun reporting disabled to avoid races.
15217                  * For correct bookkeeping mark this on active crtcs.
15218                  *
15219                  * Also on gmch platforms we dont have any hardware bits to
15220                  * disable the underrun reporting. Which means we need to start
15221                  * out with underrun reporting disabled also on inactive pipes,
15222                  * since otherwise we'll complain about the garbage we read when
15223                  * e.g. coming up after runtime pm.
15224                  *
15225                  * No protection against concurrent access is required - at
15226                  * worst a fifo underrun happens which also sets this to false.
15227                  */
15228                 crtc->cpu_fifo_underrun_disabled = true;
15229                 /*
15230                  * We track the PCH trancoder underrun reporting state
15231                  * within the crtc. With crtc for pipe A housing the underrun
15232                  * reporting state for PCH transcoder A, crtc for pipe B housing
15233                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15234                  * and marking underrun reporting as disabled for the non-existing
15235                  * PCH transcoders B and C would prevent enabling the south
15236                  * error interrupt (see cpt_can_enable_serr_int()).
15237                  */
15238                 if (has_pch_trancoder(dev_priv, crtc->pipe))
15239                         crtc->pch_fifo_underrun_disabled = true;
15240         }
15241 }
15242
15243 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15244 {
15245         struct intel_connector *connector;
15246
15247         /* We need to check both for a crtc link (meaning that the
15248          * encoder is active and trying to read from a pipe) and the
15249          * pipe itself being active. */
15250         bool has_active_crtc = encoder->base.crtc &&
15251                 to_intel_crtc(encoder->base.crtc)->active;
15252
15253         connector = intel_encoder_find_connector(encoder);
15254         if (connector && !has_active_crtc) {
15255                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15256                               encoder->base.base.id,
15257                               encoder->base.name);
15258
15259                 /* Connector is active, but has no active pipe. This is
15260                  * fallout from our resume register restoring. Disable
15261                  * the encoder manually again. */
15262                 if (encoder->base.crtc) {
15263                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15264
15265                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15266                                       encoder->base.base.id,
15267                                       encoder->base.name);
15268                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15269                         if (encoder->post_disable)
15270                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15271                 }
15272                 encoder->base.crtc = NULL;
15273
15274                 /* Inconsistent output/port/pipe state happens presumably due to
15275                  * a bug in one of the get_hw_state functions. Or someplace else
15276                  * in our code, like the register restore mess on resume. Clamp
15277                  * things to off as a safer default. */
15278
15279                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15280                 connector->base.encoder = NULL;
15281         }
15282 }
15283
15284 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15285 {
15286         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15287
15288         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15289                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15290                 i915_disable_vga(dev_priv);
15291         }
15292 }
15293
15294 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15295 {
15296         /* This function can be called both from intel_modeset_setup_hw_state or
15297          * at a very early point in our resume sequence, where the power well
15298          * structures are not yet restored. Since this function is at a very
15299          * paranoid "someone might have enabled VGA while we were not looking"
15300          * level, just check if the power well is enabled instead of trying to
15301          * follow the "don't touch the power well if we don't need it" policy
15302          * the rest of the driver uses. */
15303         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15304                 return;
15305
15306         i915_redisable_vga_power_on(dev_priv);
15307
15308         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15309 }
15310
15311 /* FIXME read out full plane state for all planes */
15312 static void readout_plane_state(struct intel_crtc *crtc)
15313 {
15314         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15315         struct intel_crtc_state *crtc_state =
15316                 to_intel_crtc_state(crtc->base.state);
15317         struct intel_plane *plane;
15318
15319         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
15320                 struct intel_plane_state *plane_state =
15321                         to_intel_plane_state(plane->base.state);
15322                 bool visible = plane->get_hw_state(plane);
15323
15324                 intel_set_plane_visible(crtc_state, plane_state, visible);
15325         }
15326 }
15327
15328 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15329 {
15330         struct drm_i915_private *dev_priv = to_i915(dev);
15331         enum pipe pipe;
15332         struct intel_crtc *crtc;
15333         struct intel_encoder *encoder;
15334         struct intel_connector *connector;
15335         struct drm_connector_list_iter conn_iter;
15336         int i;
15337
15338         dev_priv->active_crtcs = 0;
15339
15340         for_each_intel_crtc(dev, crtc) {
15341                 struct intel_crtc_state *crtc_state =
15342                         to_intel_crtc_state(crtc->base.state);
15343
15344                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15345                 memset(crtc_state, 0, sizeof(*crtc_state));
15346                 crtc_state->base.crtc = &crtc->base;
15347
15348                 crtc_state->base.active = crtc_state->base.enable =
15349                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15350
15351                 crtc->base.enabled = crtc_state->base.enable;
15352                 crtc->active = crtc_state->base.active;
15353
15354                 if (crtc_state->base.active)
15355                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15356
15357                 readout_plane_state(crtc);
15358
15359                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15360                               crtc->base.base.id, crtc->base.name,
15361                               enableddisabled(crtc_state->base.active));
15362         }
15363
15364         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15365                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15366
15367                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
15368                                                         &pll->state.hw_state);
15369                 pll->state.crtc_mask = 0;
15370                 for_each_intel_crtc(dev, crtc) {
15371                         struct intel_crtc_state *crtc_state =
15372                                 to_intel_crtc_state(crtc->base.state);
15373
15374                         if (crtc_state->base.active &&
15375                             crtc_state->shared_dpll == pll)
15376                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15377                 }
15378                 pll->active_mask = pll->state.crtc_mask;
15379
15380                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15381                               pll->info->name, pll->state.crtc_mask, pll->on);
15382         }
15383
15384         for_each_intel_encoder(dev, encoder) {
15385                 pipe = 0;
15386
15387                 if (encoder->get_hw_state(encoder, &pipe)) {
15388                         struct intel_crtc_state *crtc_state;
15389
15390                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15391                         crtc_state = to_intel_crtc_state(crtc->base.state);
15392
15393                         encoder->base.crtc = &crtc->base;
15394                         encoder->get_config(encoder, crtc_state);
15395                 } else {
15396                         encoder->base.crtc = NULL;
15397                 }
15398
15399                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15400                               encoder->base.base.id, encoder->base.name,
15401                               enableddisabled(encoder->base.crtc),
15402                               pipe_name(pipe));
15403         }
15404
15405         drm_connector_list_iter_begin(dev, &conn_iter);
15406         for_each_intel_connector_iter(connector, &conn_iter) {
15407                 if (connector->get_hw_state(connector)) {
15408                         connector->base.dpms = DRM_MODE_DPMS_ON;
15409
15410                         encoder = connector->encoder;
15411                         connector->base.encoder = &encoder->base;
15412
15413                         if (encoder->base.crtc &&
15414                             encoder->base.crtc->state->active) {
15415                                 /*
15416                                  * This has to be done during hardware readout
15417                                  * because anything calling .crtc_disable may
15418                                  * rely on the connector_mask being accurate.
15419                                  */
15420                                 encoder->base.crtc->state->connector_mask |=
15421                                         1 << drm_connector_index(&connector->base);
15422                                 encoder->base.crtc->state->encoder_mask |=
15423                                         1 << drm_encoder_index(&encoder->base);
15424                         }
15425
15426                 } else {
15427                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15428                         connector->base.encoder = NULL;
15429                 }
15430                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15431                               connector->base.base.id, connector->base.name,
15432                               enableddisabled(connector->base.encoder));
15433         }
15434         drm_connector_list_iter_end(&conn_iter);
15435
15436         for_each_intel_crtc(dev, crtc) {
15437                 struct intel_crtc_state *crtc_state =
15438                         to_intel_crtc_state(crtc->base.state);
15439                 int min_cdclk = 0;
15440
15441                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15442                 if (crtc_state->base.active) {
15443                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15444                         crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
15445                         crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
15446                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15447                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15448
15449                         /*
15450                          * The initial mode needs to be set in order to keep
15451                          * the atomic core happy. It wants a valid mode if the
15452                          * crtc's enabled, so we do the above call.
15453                          *
15454                          * But we don't set all the derived state fully, hence
15455                          * set a flag to indicate that a full recalculation is
15456                          * needed on the next commit.
15457                          */
15458                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15459
15460                         intel_crtc_compute_pixel_rate(crtc_state);
15461
15462                         if (dev_priv->display.modeset_calc_cdclk) {
15463                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15464                                 if (WARN_ON(min_cdclk < 0))
15465                                         min_cdclk = 0;
15466                         }
15467
15468                         drm_calc_timestamping_constants(&crtc->base,
15469                                                         &crtc_state->base.adjusted_mode);
15470                         update_scanline_offset(crtc);
15471                 }
15472
15473                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15474                 dev_priv->min_voltage_level[crtc->pipe] =
15475                         crtc_state->min_voltage_level;
15476
15477                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15478         }
15479 }
15480
15481 static void
15482 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15483 {
15484         struct intel_encoder *encoder;
15485
15486         for_each_intel_encoder(&dev_priv->drm, encoder) {
15487                 u64 get_domains;
15488                 enum intel_display_power_domain domain;
15489
15490                 if (!encoder->get_power_domains)
15491                         continue;
15492
15493                 get_domains = encoder->get_power_domains(encoder);
15494                 for_each_power_domain(domain, get_domains)
15495                         intel_display_power_get(dev_priv, domain);
15496         }
15497 }
15498
15499 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15500 {
15501         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15502         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15503                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15504                            DARBF_GATING_DIS);
15505
15506         if (IS_HASWELL(dev_priv)) {
15507                 /*
15508                  * WaRsPkgCStateDisplayPMReq:hsw
15509                  * System hang if this isn't done before disabling all planes!
15510                  */
15511                 I915_WRITE(CHICKEN_PAR1_1,
15512                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15513         }
15514 }
15515
15516 /* Scan out the current hw modeset state,
15517  * and sanitizes it to the current state
15518  */
15519 static void
15520 intel_modeset_setup_hw_state(struct drm_device *dev,
15521                              struct drm_modeset_acquire_ctx *ctx)
15522 {
15523         struct drm_i915_private *dev_priv = to_i915(dev);
15524         enum pipe pipe;
15525         struct intel_crtc *crtc;
15526         struct intel_encoder *encoder;
15527         int i;
15528
15529         intel_early_display_was(dev_priv);
15530         intel_modeset_readout_hw_state(dev);
15531
15532         /* HW state is read out, now we need to sanitize this mess. */
15533         get_encoder_power_domains(dev_priv);
15534
15535         intel_sanitize_plane_mapping(dev_priv);
15536
15537         for_each_intel_encoder(dev, encoder) {
15538                 intel_sanitize_encoder(encoder);
15539         }
15540
15541         for_each_pipe(dev_priv, pipe) {
15542                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15543
15544                 intel_sanitize_crtc(crtc, ctx);
15545                 intel_dump_pipe_config(crtc, crtc->config,
15546                                        "[setup_hw_state]");
15547         }
15548
15549         intel_modeset_update_connector_atomic_state(dev);
15550
15551         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15552                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15553
15554                 if (!pll->on || pll->active_mask)
15555                         continue;
15556
15557                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
15558                               pll->info->name);
15559
15560                 pll->info->funcs->disable(dev_priv, pll);
15561                 pll->on = false;
15562         }
15563
15564         if (IS_G4X(dev_priv)) {
15565                 g4x_wm_get_hw_state(dev);
15566                 g4x_wm_sanitize(dev_priv);
15567         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15568                 vlv_wm_get_hw_state(dev);
15569                 vlv_wm_sanitize(dev_priv);
15570         } else if (INTEL_GEN(dev_priv) >= 9) {
15571                 skl_wm_get_hw_state(dev);
15572         } else if (HAS_PCH_SPLIT(dev_priv)) {
15573                 ilk_wm_get_hw_state(dev);
15574         }
15575
15576         for_each_intel_crtc(dev, crtc) {
15577                 u64 put_domains;
15578
15579                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15580                 if (WARN_ON(put_domains))
15581                         modeset_put_power_domains(dev_priv, put_domains);
15582         }
15583         intel_display_set_init_power(dev_priv, false);
15584
15585         intel_power_domains_verify_state(dev_priv);
15586
15587         intel_fbc_init_pipe_state(dev_priv);
15588 }
15589
15590 void intel_display_resume(struct drm_device *dev)
15591 {
15592         struct drm_i915_private *dev_priv = to_i915(dev);
15593         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15594         struct drm_modeset_acquire_ctx ctx;
15595         int ret;
15596
15597         dev_priv->modeset_restore_state = NULL;
15598         if (state)
15599                 state->acquire_ctx = &ctx;
15600
15601         drm_modeset_acquire_init(&ctx, 0);
15602
15603         while (1) {
15604                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15605                 if (ret != -EDEADLK)
15606                         break;
15607
15608                 drm_modeset_backoff(&ctx);
15609         }
15610
15611         if (!ret)
15612                 ret = __intel_display_resume(dev, state, &ctx);
15613
15614         intel_enable_ipc(dev_priv);
15615         drm_modeset_drop_locks(&ctx);
15616         drm_modeset_acquire_fini(&ctx);
15617
15618         if (ret)
15619                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15620         if (state)
15621                 drm_atomic_state_put(state);
15622 }
15623
15624 int intel_connector_register(struct drm_connector *connector)
15625 {
15626         struct intel_connector *intel_connector = to_intel_connector(connector);
15627         int ret;
15628
15629         ret = intel_backlight_device_register(intel_connector);
15630         if (ret)
15631                 goto err;
15632
15633         return 0;
15634
15635 err:
15636         return ret;
15637 }
15638
15639 void intel_connector_unregister(struct drm_connector *connector)
15640 {
15641         struct intel_connector *intel_connector = to_intel_connector(connector);
15642
15643         intel_backlight_device_unregister(intel_connector);
15644         intel_panel_destroy_backlight(connector);
15645 }
15646
15647 static void intel_hpd_poll_fini(struct drm_device *dev)
15648 {
15649         struct intel_connector *connector;
15650         struct drm_connector_list_iter conn_iter;
15651
15652         /* Kill all the work that may have been queued by hpd. */
15653         drm_connector_list_iter_begin(dev, &conn_iter);
15654         for_each_intel_connector_iter(connector, &conn_iter) {
15655                 if (connector->modeset_retry_work.func)
15656                         cancel_work_sync(&connector->modeset_retry_work);
15657                 if (connector->hdcp_shim) {
15658                         cancel_delayed_work_sync(&connector->hdcp_check_work);
15659                         cancel_work_sync(&connector->hdcp_prop_work);
15660                 }
15661         }
15662         drm_connector_list_iter_end(&conn_iter);
15663 }
15664
15665 void intel_modeset_cleanup(struct drm_device *dev)
15666 {
15667         struct drm_i915_private *dev_priv = to_i915(dev);
15668
15669         flush_work(&dev_priv->atomic_helper.free_work);
15670         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15671
15672         intel_disable_gt_powersave(dev_priv);
15673
15674         /*
15675          * Interrupts and polling as the first thing to avoid creating havoc.
15676          * Too much stuff here (turning of connectors, ...) would
15677          * experience fancy races otherwise.
15678          */
15679         intel_irq_uninstall(dev_priv);
15680
15681         /*
15682          * Due to the hpd irq storm handling the hotplug work can re-arm the
15683          * poll handlers. Hence disable polling after hpd handling is shut down.
15684          */
15685         intel_hpd_poll_fini(dev);
15686
15687         /* poll work can call into fbdev, hence clean that up afterwards */
15688         intel_fbdev_fini(dev_priv);
15689
15690         intel_unregister_dsm_handler();
15691
15692         intel_fbc_global_disable(dev_priv);
15693
15694         /* flush any delayed tasks or pending work */
15695         flush_scheduled_work();
15696
15697         drm_mode_config_cleanup(dev);
15698
15699         intel_cleanup_overlay(dev_priv);
15700
15701         intel_cleanup_gt_powersave(dev_priv);
15702
15703         intel_teardown_gmbus(dev_priv);
15704
15705         destroy_workqueue(dev_priv->modeset_wq);
15706 }
15707
15708 void intel_connector_attach_encoder(struct intel_connector *connector,
15709                                     struct intel_encoder *encoder)
15710 {
15711         connector->encoder = encoder;
15712         drm_mode_connector_attach_encoder(&connector->base,
15713                                           &encoder->base);
15714 }
15715
15716 /*
15717  * set vga decode state - true == enable VGA decode
15718  */
15719 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15720 {
15721         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15722         u16 gmch_ctrl;
15723
15724         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15725                 DRM_ERROR("failed to read control word\n");
15726                 return -EIO;
15727         }
15728
15729         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15730                 return 0;
15731
15732         if (state)
15733                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15734         else
15735                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15736
15737         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15738                 DRM_ERROR("failed to write control word\n");
15739                 return -EIO;
15740         }
15741
15742         return 0;
15743 }
15744
15745 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15746
15747 struct intel_display_error_state {
15748
15749         u32 power_well_driver;
15750
15751         int num_transcoders;
15752
15753         struct intel_cursor_error_state {
15754                 u32 control;
15755                 u32 position;
15756                 u32 base;
15757                 u32 size;
15758         } cursor[I915_MAX_PIPES];
15759
15760         struct intel_pipe_error_state {
15761                 bool power_domain_on;
15762                 u32 source;
15763                 u32 stat;
15764         } pipe[I915_MAX_PIPES];
15765
15766         struct intel_plane_error_state {
15767                 u32 control;
15768                 u32 stride;
15769                 u32 size;
15770                 u32 pos;
15771                 u32 addr;
15772                 u32 surface;
15773                 u32 tile_offset;
15774         } plane[I915_MAX_PIPES];
15775
15776         struct intel_transcoder_error_state {
15777                 bool power_domain_on;
15778                 enum transcoder cpu_transcoder;
15779
15780                 u32 conf;
15781
15782                 u32 htotal;
15783                 u32 hblank;
15784                 u32 hsync;
15785                 u32 vtotal;
15786                 u32 vblank;
15787                 u32 vsync;
15788         } transcoder[4];
15789 };
15790
15791 struct intel_display_error_state *
15792 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15793 {
15794         struct intel_display_error_state *error;
15795         int transcoders[] = {
15796                 TRANSCODER_A,
15797                 TRANSCODER_B,
15798                 TRANSCODER_C,
15799                 TRANSCODER_EDP,
15800         };
15801         int i;
15802
15803         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15804                 return NULL;
15805
15806         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15807         if (error == NULL)
15808                 return NULL;
15809
15810         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15811                 error->power_well_driver =
15812                         I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15813
15814         for_each_pipe(dev_priv, i) {
15815                 error->pipe[i].power_domain_on =
15816                         __intel_display_power_is_enabled(dev_priv,
15817                                                          POWER_DOMAIN_PIPE(i));
15818                 if (!error->pipe[i].power_domain_on)
15819                         continue;
15820
15821                 error->cursor[i].control = I915_READ(CURCNTR(i));
15822                 error->cursor[i].position = I915_READ(CURPOS(i));
15823                 error->cursor[i].base = I915_READ(CURBASE(i));
15824
15825                 error->plane[i].control = I915_READ(DSPCNTR(i));
15826                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15827                 if (INTEL_GEN(dev_priv) <= 3) {
15828                         error->plane[i].size = I915_READ(DSPSIZE(i));
15829                         error->plane[i].pos = I915_READ(DSPPOS(i));
15830                 }
15831                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15832                         error->plane[i].addr = I915_READ(DSPADDR(i));
15833                 if (INTEL_GEN(dev_priv) >= 4) {
15834                         error->plane[i].surface = I915_READ(DSPSURF(i));
15835                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15836                 }
15837
15838                 error->pipe[i].source = I915_READ(PIPESRC(i));
15839
15840                 if (HAS_GMCH_DISPLAY(dev_priv))
15841                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15842         }
15843
15844         /* Note: this does not include DSI transcoders. */
15845         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15846         if (HAS_DDI(dev_priv))
15847                 error->num_transcoders++; /* Account for eDP. */
15848
15849         for (i = 0; i < error->num_transcoders; i++) {
15850                 enum transcoder cpu_transcoder = transcoders[i];
15851
15852                 error->transcoder[i].power_domain_on =
15853                         __intel_display_power_is_enabled(dev_priv,
15854                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15855                 if (!error->transcoder[i].power_domain_on)
15856                         continue;
15857
15858                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15859
15860                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15861                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15862                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15863                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15864                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15865                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15866                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15867         }
15868
15869         return error;
15870 }
15871
15872 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15873
15874 void
15875 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15876                                 struct intel_display_error_state *error)
15877 {
15878         struct drm_i915_private *dev_priv = m->i915;
15879         int i;
15880
15881         if (!error)
15882                 return;
15883
15884         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15885         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15886                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15887                            error->power_well_driver);
15888         for_each_pipe(dev_priv, i) {
15889                 err_printf(m, "Pipe [%d]:\n", i);
15890                 err_printf(m, "  Power: %s\n",
15891                            onoff(error->pipe[i].power_domain_on));
15892                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15893                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15894
15895                 err_printf(m, "Plane [%d]:\n", i);
15896                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15897                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15898                 if (INTEL_GEN(dev_priv) <= 3) {
15899                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15900                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15901                 }
15902                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15903                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15904                 if (INTEL_GEN(dev_priv) >= 4) {
15905                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15906                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15907                 }
15908
15909                 err_printf(m, "Cursor [%d]:\n", i);
15910                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15911                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15912                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15913         }
15914
15915         for (i = 0; i < error->num_transcoders; i++) {
15916                 err_printf(m, "CPU transcoder: %s\n",
15917                            transcoder_name(error->transcoder[i].cpu_transcoder));
15918                 err_printf(m, "  Power: %s\n",
15919                            onoff(error->transcoder[i].power_domain_on));
15920                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15921                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15922                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15923                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15924                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15925                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15926                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15927         }
15928 }
15929
15930 #endif