drivers/usb/dwc2/hcd_intr.c

   1 /*
   2  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the interrupt handlers for Host mode
  39  */
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/io.h>
  46 #include <linux/slab.h>
  47 #include <linux/usb.h>
  48
  49 #include <linux/usb/hcd.h>
  50 #include <linux/usb/ch11.h>
  51
  52 #include "core.h"
  53 #include "hcd.h"
  54
  55 /* This function is for debug only */
  56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  57 {
  58         u16 curr_frame_number = hsotg->frame_number;
  59         u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
  60
  61         if (expected != curr_frame_number)
  62                 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
  63                               expected, curr_frame_number);
  64
  65 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  66         if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  67                 if (expected != curr_frame_number) {
  68                         hsotg->frame_num_array[hsotg->frame_num_idx] =
  69                                         curr_frame_number;
  70                         hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  71                                         hsotg->last_frame_num;
  72                         hsotg->frame_num_idx++;
  73                 }
  74         } else if (!hsotg->dumped_frame_num_array) {
  75                 int i;
  76
  77                 dev_info(hsotg->dev, "Frame     Last Frame\n");
  78                 dev_info(hsotg->dev, "-----     ----------\n");
  79                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  80                         dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  81                                  hsotg->frame_num_array[i],
  82                                  hsotg->last_frame_num_array[i]);
  83                 }
  84                 hsotg->dumped_frame_num_array = 1;
  85         }
  86 #endif
  87         hsotg->last_frame_num = curr_frame_number;
  88 }
  89
  90 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  91                                     struct dwc2_host_chan *chan,
  92                                     struct dwc2_qtd *qtd)
  93 {
  94         struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
  95         struct urb *usb_urb;
  96
  97         if (!chan->qh)
  98                 return;
  99
 100         if (chan->qh->dev_speed == USB_SPEED_HIGH)
 101                 return;
 102
 103         if (!qtd->urb)
 104                 return;
 105
 106         usb_urb = qtd->urb->priv;
 107         if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
 108                 return;
 109
 110         /*
 111          * The root hub doesn't really have a TT, but Linux thinks it
 112          * does because how could you have a "high speed hub" that
 113          * directly talks directly to low speed devices without a TT?
 114          * It's all lies.  Lies, I tell you.
 115          */
 116         if (usb_urb->dev->tt->hub == root_hub)
 117                 return;
 118
 119         if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 120                 chan->qh->tt_buffer_dirty = 1;
 121                 if (usb_hub_clear_tt_buffer(usb_urb))
 122                         /* Clear failed; let's hope things work anyway */
 123                         chan->qh->tt_buffer_dirty = 0;
 124         }
 125 }
 126
 127 /*
 128  * Handles the start-of-frame interrupt in host mode. Non-periodic
 129  * transactions may be queued to the DWC_otg controller for the current
 130  * (micro)frame. Periodic transactions may be queued to the controller
 131  * for the next (micro)frame.
 132  */
 133 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 134 {
 135         struct list_head *qh_entry;
 136         struct dwc2_qh *qh;
 137         enum dwc2_transaction_type tr_type;
 138
 139         /* Clear interrupt */
 140         dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 141
 142 #ifdef DEBUG_SOF
 143         dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 144 #endif
 145
 146         hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
 147
 148         dwc2_track_missed_sofs(hsotg);
 149
 150         /* Determine whether any periodic QHs should be executed */
 151         qh_entry = hsotg->periodic_sched_inactive.next;
 152         while (qh_entry != &hsotg->periodic_sched_inactive) {
 153                 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 154                 qh_entry = qh_entry->next;
 155                 if (dwc2_frame_num_le(qh->next_active_frame,
 156                                       hsotg->frame_number)) {
 157                         dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
 158                                       qh, hsotg->frame_number,
 159                                       qh->next_active_frame);
 160
 161                         /*
 162                          * Move QH to the ready list to be executed next
 163                          * (micro)frame
 164                          */
 165                         list_move_tail(&qh->qh_list_entry,
 166                                        &hsotg->periodic_sched_ready);
 167                 }
 168         }
 169         tr_type = dwc2_hcd_select_transactions(hsotg);
 170         if (tr_type != DWC2_TRANSACTION_NONE)
 171                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 172 }
 173
 174 /*
 175  * Handles the Rx FIFO Level Interrupt, which indicates that there is
 176  * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 177  * memory if the DWC_otg controller is operating in Slave mode.
 178  */
 179 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 180 {
 181         u32 grxsts, chnum, bcnt, dpid, pktsts;
 182         struct dwc2_host_chan *chan;
 183
 184         if (dbg_perio())
 185                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 186
 187         grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
 188         chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
 189         chan = hsotg->hc_ptr_array[chnum];
 190         if (!chan) {
 191                 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 192                 return;
 193         }
 194
 195         bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
 196         dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
 197         pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
 198
 199         /* Packet Status */
 200         if (dbg_perio()) {
 201                 dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 202                 dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 203                 dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 204                          chan->data_pid_start);
 205                 dev_vdbg(hsotg->dev, "    PStatus = %d\n", pktsts);
 206         }
 207
 208         switch (pktsts) {
 209         case GRXSTS_PKTSTS_HCHIN:
 210                 /* Read the data into the host buffer */
 211                 if (bcnt > 0) {
 212                         dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 213
 214                         /* Update the HC fields for the next packet received */
 215                         chan->xfer_count += bcnt;
 216                         chan->xfer_buf += bcnt;
 217                 }
 218                 break;
 219         case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 220         case GRXSTS_PKTSTS_DATATOGGLEERR:
 221         case GRXSTS_PKTSTS_HCHHALTED:
 222                 /* Handled in interrupt, just ignore data */
 223                 break;
 224         default:
 225                 dev_err(hsotg->dev,
 226                         "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 227                 break;
 228         }
 229 }
 230
 231 /*
 232  * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 233  * data packets may be written to the FIFO for OUT transfers. More requests
 234  * may be written to the non-periodic request queue for IN transfers. This
 235  * interrupt is enabled only in Slave mode.
 236  */
 237 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 238 {
 239         dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 240         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 241 }
 242
 243 /*
 244  * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 245  * packets may be written to the FIFO for OUT transfers. More requests may be
 246  * written to the periodic request queue for IN transfers. This interrupt is
 247  * enabled only in Slave mode.
 248  */
 249 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 250 {
 251         if (dbg_perio())
 252                 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 253         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 254 }
 255
 256 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 257                               u32 *hprt0_modify)
 258 {
 259         struct dwc2_core_params *params = &hsotg->params;
 260         int do_reset = 0;
 261         u32 usbcfg;
 262         u32 prtspd;
 263         u32 hcfg;
 264         u32 fslspclksel;
 265         u32 hfir;
 266
 267         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 268
 269         /* Every time when port enables calculate HFIR.FrInterval */
 270         hfir = dwc2_readl(hsotg->regs + HFIR);
 271         hfir &= ~HFIR_FRINT_MASK;
 272         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 273                 HFIR_FRINT_MASK;
 274         dwc2_writel(hfir, hsotg->regs + HFIR);
 275
 276         /* Check if we need to adjust the PHY clock speed for low power */
 277         if (!params->host_support_fs_ls_low_power) {
 278                 /* Port has been enabled, set the reset change flag */
 279                 hsotg->flags.b.port_reset_change = 1;
 280                 return;
 281         }
 282
 283         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 284         prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 285
 286         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 287                 /* Low power */
 288                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 289                         /* Set PHY low power clock select for FS/LS devices */
 290                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 291                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 292                         do_reset = 1;
 293                 }
 294
 295                 hcfg = dwc2_readl(hsotg->regs + HCFG);
 296                 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
 297                               HCFG_FSLSPCLKSEL_SHIFT;
 298
 299                 if (prtspd == HPRT0_SPD_LOW_SPEED &&
 300                     params->host_ls_low_power_phy_clk) {
 301                         /* 6 MHZ */
 302                         dev_vdbg(hsotg->dev,
 303                                  "FS_PHY programming HCFG to 6 MHz\n");
 304                         if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
 305                                 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
 306                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 307                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 308                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 309                                 do_reset = 1;
 310                         }
 311                 } else {
 312                         /* 48 MHZ */
 313                         dev_vdbg(hsotg->dev,
 314                                  "FS_PHY programming HCFG to 48 MHz\n");
 315                         if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
 316                                 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
 317                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 318                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 319                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 320                                 do_reset = 1;
 321                         }
 322                 }
 323         } else {
 324                 /* Not low power */
 325                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 326                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 327                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 328                         do_reset = 1;
 329                 }
 330         }
 331
 332         if (do_reset) {
 333                 *hprt0_modify |= HPRT0_RST;
 334                 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0);
 335                 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 336                                    msecs_to_jiffies(60));
 337         } else {
 338                 /* Port has been enabled, set the reset change flag */
 339                 hsotg->flags.b.port_reset_change = 1;
 340         }
 341 }
 342
 343 /*
 344  * There are multiple conditions that can cause a port interrupt. This function
 345  * determines which interrupt conditions have occurred and handles them
 346  * appropriately.
 347  */
 348 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 349 {
 350         u32 hprt0;
 351         u32 hprt0_modify;
 352
 353         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 354
 355         hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 356         hprt0_modify = hprt0;
 357
 358         /*
 359          * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 360          * GINTSTS
 361          */
 362         hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 363                           HPRT0_OVRCURRCHG);
 364
 365         /*
 366          * Port Connect Detected
 367          * Set flag and clear if detected
 368          */
 369         if (hprt0 & HPRT0_CONNDET) {
 370                 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0);
 371
 372                 dev_vdbg(hsotg->dev,
 373                          "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 374                          hprt0);
 375                 dwc2_hcd_connect(hsotg);
 376
 377                 /*
 378                  * The Hub driver asserts a reset when it sees port connect
 379                  * status change flag
 380                  */
 381         }
 382
 383         /*
 384          * Port Enable Changed
 385          * Clear if detected - Set internal flag if disabled
 386          */
 387         if (hprt0 & HPRT0_ENACHG) {
 388                 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0);
 389                 dev_vdbg(hsotg->dev,
 390                          "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 391                          hprt0, !!(hprt0 & HPRT0_ENA));
 392                 if (hprt0 & HPRT0_ENA) {
 393                         hsotg->new_connection = true;
 394                         dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 395                 } else {
 396                         hsotg->flags.b.port_enable_change = 1;
 397                         if (hsotg->params.dma_desc_fs_enable) {
 398                                 u32 hcfg;
 399
 400                                 hsotg->params.dma_desc_enable = false;
 401                                 hsotg->new_connection = false;
 402                                 hcfg = dwc2_readl(hsotg->regs + HCFG);
 403                                 hcfg &= ~HCFG_DESCDMA;
 404                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 405                         }
 406                 }
 407         }
 408
 409         /* Overcurrent Change Interrupt */
 410         if (hprt0 & HPRT0_OVRCURRCHG) {
 411                 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG,
 412                             hsotg->regs + HPRT0);
 413                 dev_vdbg(hsotg->dev,
 414                          "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 415                          hprt0);
 416                 hsotg->flags.b.port_over_current_change = 1;
 417         }
 418 }
 419
 420 /*
 421  * Gets the actual length of a transfer after the transfer halts. halt_status
 422  * holds the reason for the halt.
 423  *
 424  * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 425  * is set to 1 upon return if less than the requested number of bytes were
 426  * transferred. short_read may also be NULL on entry, in which case it remains
 427  * unchanged.
 428  */
 429 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 430                                        struct dwc2_host_chan *chan, int chnum,
 431                                        struct dwc2_qtd *qtd,
 432                                        enum dwc2_halt_status halt_status,
 433                                        int *short_read)
 434 {
 435         u32 hctsiz, count, length;
 436
 437         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 438
 439         if (halt_status == DWC2_HC_XFER_COMPLETE) {
 440                 if (chan->ep_is_in) {
 441                         count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
 442                                 TSIZ_XFERSIZE_SHIFT;
 443                         length = chan->xfer_len - count;
 444                         if (short_read)
 445                                 *short_read = (count != 0);
 446                 } else if (chan->qh->do_split) {
 447                         length = qtd->ssplit_out_xfer_count;
 448                 } else {
 449                         length = chan->xfer_len;
 450                 }
 451         } else {
 452                 /*
 453                  * Must use the hctsiz.pktcnt field to determine how much data
 454                  * has been transferred. This field reflects the number of
 455                  * packets that have been transferred via the USB. This is
 456                  * always an integral number of packets if the transfer was
 457                  * halted before its normal completion. (Can't use the
 458                  * hctsiz.xfersize field because that reflects the number of
 459                  * bytes transferred via the AHB, not the USB).
 460                  */
 461                 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
 462                 length = (chan->start_pkt_count - count) * chan->max_packet;
 463         }
 464
 465         return length;
 466 }
 467
 468 /**
 469  * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 470  * Complete interrupt on the host channel. Updates the actual_length field
 471  * of the URB based on the number of bytes transferred via the host channel.
 472  * Sets the URB status if the data transfer is finished.
 473  *
 474  * Return: 1 if the data transfer specified by the URB is completely finished,
 475  * 0 otherwise
 476  */
 477 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 478                                  struct dwc2_host_chan *chan, int chnum,
 479                                  struct dwc2_hcd_urb *urb,
 480                                  struct dwc2_qtd *qtd)
 481 {
 482         u32 hctsiz;
 483         int xfer_done = 0;
 484         int short_read = 0;
 485         int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 486                                                       DWC2_HC_XFER_COMPLETE,
 487                                                       &short_read);
 488
 489         if (urb->actual_length + xfer_length > urb->length) {
 490                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 491                 xfer_length = urb->length - urb->actual_length;
 492         }
 493
 494         dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 495                  urb->actual_length, xfer_length);
 496         urb->actual_length += xfer_length;
 497
 498         if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 499             (urb->flags & URB_SEND_ZERO_PACKET) &&
 500             urb->actual_length >= urb->length &&
 501             !(urb->length % chan->max_packet)) {
 502                 xfer_done = 0;
 503         } else if (short_read || urb->actual_length >= urb->length) {
 504                 xfer_done = 1;
 505                 urb->status = 0;
 506         }
 507
 508         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 509         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 510                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 511         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 512         dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 513                  (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
 514         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 515         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 516         dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 517                  xfer_done);
 518
 519         return xfer_done;
 520 }
 521
 522 /*
 523  * Save the starting data toggle for the next transfer. The data toggle is
 524  * saved in the QH for non-control transfers and it's saved in the QTD for
 525  * control transfers.
 526  */
 527 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 528                                struct dwc2_host_chan *chan, int chnum,
 529                                struct dwc2_qtd *qtd)
 530 {
 531         u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 532         u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 533
 534         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 535                 if (WARN(!chan || !chan->qh,
 536                          "chan->qh must be specified for non-control eps\n"))
 537                         return;
 538
 539                 if (pid == TSIZ_SC_MC_PID_DATA0)
 540                         chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 541                 else
 542                         chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 543         } else {
 544                 if (WARN(!qtd,
 545                          "qtd must be specified for control eps\n"))
 546                         return;
 547
 548                 if (pid == TSIZ_SC_MC_PID_DATA0)
 549                         qtd->data_toggle = DWC2_HC_PID_DATA0;
 550                 else
 551                         qtd->data_toggle = DWC2_HC_PID_DATA1;
 552         }
 553 }
 554
 555 /**
 556  * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 557  * the transfer is stopped for any reason. The fields of the current entry in
 558  * the frame descriptor array are set based on the transfer state and the input
 559  * halt_status. Completes the Isochronous URB if all the URB frames have been
 560  * completed.
 561  *
 562  * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 563  * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 564  */
 565 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 566                 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 567                 int chnum, struct dwc2_qtd *qtd,
 568                 enum dwc2_halt_status halt_status)
 569 {
 570         struct dwc2_hcd_iso_packet_desc *frame_desc;
 571         struct dwc2_hcd_urb *urb = qtd->urb;
 572
 573         if (!urb)
 574                 return DWC2_HC_XFER_NO_HALT_STATUS;
 575
 576         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 577
 578         switch (halt_status) {
 579         case DWC2_HC_XFER_COMPLETE:
 580                 frame_desc->status = 0;
 581                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 582                                         chan, chnum, qtd, halt_status, NULL);
 583                 break;
 584         case DWC2_HC_XFER_FRAME_OVERRUN:
 585                 urb->error_count++;
 586                 if (chan->ep_is_in)
 587                         frame_desc->status = -ENOSR;
 588                 else
 589                         frame_desc->status = -ECOMM;
 590                 frame_desc->actual_length = 0;
 591                 break;
 592         case DWC2_HC_XFER_BABBLE_ERR:
 593                 urb->error_count++;
 594                 frame_desc->status = -EOVERFLOW;
 595                 /* Don't need to update actual_length in this case */
 596                 break;
 597         case DWC2_HC_XFER_XACT_ERR:
 598                 urb->error_count++;
 599                 frame_desc->status = -EPROTO;
 600                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 601                                         chan, chnum, qtd, halt_status, NULL);
 602
 603                 /* Skip whole frame */
 604                 if (chan->qh->do_split &&
 605                     chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 606                     hsotg->params.host_dma) {
 607                         qtd->complete_split = 0;
 608                         qtd->isoc_split_offset = 0;
 609                 }
 610
 611                 break;
 612         default:
 613                 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 614                         halt_status);
 615                 break;
 616         }
 617
 618         if (++qtd->isoc_frame_index == urb->packet_count) {
 619                 /*
 620                  * urb->status is not used for isoc transfers. The individual
 621                  * frame_desc statuses are used instead.
 622                  */
 623                 dwc2_host_complete(hsotg, qtd, 0);
 624                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
 625         } else {
 626                 halt_status = DWC2_HC_XFER_COMPLETE;
 627         }
 628
 629         return halt_status;
 630 }
 631
 632 /*
 633  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 634  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 635  * still linked to the QH, the QH is added to the end of the inactive
 636  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 637  * schedule if no more QTDs are linked to the QH.
 638  */
 639 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 640                                int free_qtd)
 641 {
 642         int continue_split = 0;
 643         struct dwc2_qtd *qtd;
 644
 645         if (dbg_qh(qh))
 646                 dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 647                          hsotg, qh, free_qtd);
 648
 649         if (list_empty(&qh->qtd_list)) {
 650                 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 651                 goto no_qtd;
 652         }
 653
 654         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 655
 656         if (qtd->complete_split)
 657                 continue_split = 1;
 658         else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 659                  qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 660                 continue_split = 1;
 661
 662         if (free_qtd) {
 663                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 664                 continue_split = 0;
 665         }
 666
 667 no_qtd:
 668         qh->channel = NULL;
 669         dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 670 }
 671
 672 /**
 673  * dwc2_release_channel() - Releases a host channel for use by other transfers
 674  *
 675  * @hsotg:       The HCD state structure
 676  * @chan:        The host channel to release
 677  * @qtd:         The QTD associated with the host channel. This QTD may be
 678  *               freed if the transfer is complete or an error has occurred.
 679  * @halt_status: Reason the channel is being released. This status
 680  *               determines the actions taken by this function.
 681  *
 682  * Also attempts to select and queue more transactions since at least one host
 683  * channel is available.
 684  */
 685 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 686                                  struct dwc2_host_chan *chan,
 687                                  struct dwc2_qtd *qtd,
 688                                  enum dwc2_halt_status halt_status)
 689 {
 690         enum dwc2_transaction_type tr_type;
 691         u32 haintmsk;
 692         int free_qtd = 0;
 693
 694         if (dbg_hc(chan))
 695                 dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 696                          __func__, chan->hc_num, halt_status);
 697
 698         switch (halt_status) {
 699         case DWC2_HC_XFER_URB_COMPLETE:
 700                 free_qtd = 1;
 701                 break;
 702         case DWC2_HC_XFER_AHB_ERR:
 703         case DWC2_HC_XFER_STALL:
 704         case DWC2_HC_XFER_BABBLE_ERR:
 705                 free_qtd = 1;
 706                 break;
 707         case DWC2_HC_XFER_XACT_ERR:
 708                 if (qtd && qtd->error_count >= 3) {
 709                         dev_vdbg(hsotg->dev,
 710                                  "  Complete URB with transaction error\n");
 711                         free_qtd = 1;
 712                         dwc2_host_complete(hsotg, qtd, -EPROTO);
 713                 }
 714                 break;
 715         case DWC2_HC_XFER_URB_DEQUEUE:
 716                 /*
 717                  * The QTD has already been removed and the QH has been
 718                  * deactivated. Don't want to do anything except release the
 719                  * host channel and try to queue more transfers.
 720                  */
 721                 goto cleanup;
 722         case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 723                 dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 724                 free_qtd = 1;
 725                 dwc2_host_complete(hsotg, qtd, -EIO);
 726                 break;
 727         case DWC2_HC_XFER_NO_HALT_STATUS:
 728         default:
 729                 break;
 730         }
 731
 732         dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 733
 734 cleanup:
 735         /*
 736          * Release the host channel for use by other transfers. The cleanup
 737          * function clears the channel interrupt enables and conditions, so
 738          * there's no need to clear the Channel Halted interrupt separately.
 739          */
 740         if (!list_empty(&chan->hc_list_entry))
 741                 list_del(&chan->hc_list_entry);
 742         dwc2_hc_cleanup(hsotg, chan);
 743         list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 744
 745         if (hsotg->params.uframe_sched) {
 746                 hsotg->available_host_channels++;
 747         } else {
 748                 switch (chan->ep_type) {
 749                 case USB_ENDPOINT_XFER_CONTROL:
 750                 case USB_ENDPOINT_XFER_BULK:
 751                         hsotg->non_periodic_channels--;
 752                         break;
 753                 default:
 754                         /*
 755                          * Don't release reservations for periodic channels
 756                          * here. That's done when a periodic transfer is
 757                          * descheduled (i.e. when the QH is removed from the
 758                          * periodic schedule).
 759                          */
 760                         break;
 761                 }
 762         }
 763
 764         haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
 765         haintmsk &= ~(1 << chan->hc_num);
 766         dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
 767
 768         /* Try to queue more transfers now that there's a free channel */
 769         tr_type = dwc2_hcd_select_transactions(hsotg);
 770         if (tr_type != DWC2_TRANSACTION_NONE)
 771                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 772 }
 773
 774 /*
 775  * Halts a host channel. If the channel cannot be halted immediately because
 776  * the request queue is full, this function ensures that the FIFO empty
 777  * interrupt for the appropriate queue is enabled so that the halt request can
 778  * be queued when there is space in the request queue.
 779  *
 780  * This function may also be called in DMA mode. In that case, the channel is
 781  * simply released since the core always halts the channel automatically in
 782  * DMA mode.
 783  */
 784 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 785                               struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 786                               enum dwc2_halt_status halt_status)
 787 {
 788         if (dbg_hc(chan))
 789                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 790
 791         if (hsotg->params.host_dma) {
 792                 if (dbg_hc(chan))
 793                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 794                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 795                 return;
 796         }
 797
 798         /* Slave mode processing */
 799         dwc2_hc_halt(hsotg, chan, halt_status);
 800
 801         if (chan->halt_on_queue) {
 802                 u32 gintmsk;
 803
 804                 dev_vdbg(hsotg->dev, "Halt on queue\n");
 805                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 806                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 807                         dev_vdbg(hsotg->dev, "control/bulk\n");
 808                         /*
 809                          * Make sure the Non-periodic Tx FIFO empty interrupt
 810                          * is enabled so that the non-periodic schedule will
 811                          * be processed
 812                          */
 813                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 814                         gintmsk |= GINTSTS_NPTXFEMP;
 815                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 816                 } else {
 817                         dev_vdbg(hsotg->dev, "isoc/intr\n");
 818                         /*
 819                          * Move the QH from the periodic queued schedule to
 820                          * the periodic assigned schedule. This allows the
 821                          * halt to be queued when the periodic schedule is
 822                          * processed.
 823                          */
 824                         list_move_tail(&chan->qh->qh_list_entry,
 825                                        &hsotg->periodic_sched_assigned);
 826
 827                         /*
 828                          * Make sure the Periodic Tx FIFO Empty interrupt is
 829                          * enabled so that the periodic schedule will be
 830                          * processed
 831                          */
 832                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 833                         gintmsk |= GINTSTS_PTXFEMP;
 834                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 835                 }
 836         }
 837 }
 838
 839 /*
 840  * Performs common cleanup for non-periodic transfers after a Transfer
 841  * Complete interrupt. This function should be called after any endpoint type
 842  * specific handling is finished to release the host channel.
 843  */
 844 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 845                                             struct dwc2_host_chan *chan,
 846                                             int chnum, struct dwc2_qtd *qtd,
 847                                             enum dwc2_halt_status halt_status)
 848 {
 849         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 850
 851         qtd->error_count = 0;
 852
 853         if (chan->hcint & HCINTMSK_NYET) {
 854                 /*
 855                  * Got a NYET on the last transaction of the transfer. This
 856                  * means that the endpoint should be in the PING state at the
 857                  * beginning of the next transfer.
 858                  */
 859                 dev_vdbg(hsotg->dev, "got NYET\n");
 860                 chan->qh->ping_state = 1;
 861         }
 862
 863         /*
 864          * Always halt and release the host channel to make it available for
 865          * more transfers. There may still be more phases for a control
 866          * transfer or more data packets for a bulk transfer at this point,
 867          * but the host channel is still halted. A channel will be reassigned
 868          * to the transfer when the non-periodic schedule is processed after
 869          * the channel is released. This allows transactions to be queued
 870          * properly via dwc2_hcd_queue_transactions, which also enables the
 871          * Tx FIFO Empty interrupt if necessary.
 872          */
 873         if (chan->ep_is_in) {
 874                 /*
 875                  * IN transfers in Slave mode require an explicit disable to
 876                  * halt the channel. (In DMA mode, this call simply releases
 877                  * the channel.)
 878                  */
 879                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 880         } else {
 881                 /*
 882                  * The channel is automatically disabled by the core for OUT
 883                  * transfers in Slave mode
 884                  */
 885                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 886         }
 887 }
 888
 889 /*
 890  * Performs common cleanup for periodic transfers after a Transfer Complete
 891  * interrupt. This function should be called after any endpoint type specific
 892  * handling is finished to release the host channel.
 893  */
 894 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 895                                         struct dwc2_host_chan *chan, int chnum,
 896                                         struct dwc2_qtd *qtd,
 897                                         enum dwc2_halt_status halt_status)
 898 {
 899         u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 900
 901         qtd->error_count = 0;
 902
 903         if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 904                 /* Core halts channel in these cases */
 905                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 906         else
 907                 /* Flush any outstanding requests from the Tx queue */
 908                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 909 }
 910
 911 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 912                                        struct dwc2_host_chan *chan, int chnum,
 913                                        struct dwc2_qtd *qtd)
 914 {
 915         struct dwc2_hcd_iso_packet_desc *frame_desc;
 916         u32 len;
 917         u32 hctsiz;
 918         u32 pid;
 919
 920         if (!qtd->urb)
 921                 return 0;
 922
 923         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 924         len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 925                                           DWC2_HC_XFER_COMPLETE, NULL);
 926         if (!len) {
 927                 qtd->complete_split = 0;
 928                 qtd->isoc_split_offset = 0;
 929                 return 0;
 930         }
 931
 932         frame_desc->actual_length += len;
 933
 934         qtd->isoc_split_offset += len;
 935
 936         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 937         pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 938
 939         if (frame_desc->actual_length >= frame_desc->length || pid == 0) {
 940                 frame_desc->status = 0;
 941                 qtd->isoc_frame_index++;
 942                 qtd->complete_split = 0;
 943                 qtd->isoc_split_offset = 0;
 944         }
 945
 946         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 947                 dwc2_host_complete(hsotg, qtd, 0);
 948                 dwc2_release_channel(hsotg, chan, qtd,
 949                                      DWC2_HC_XFER_URB_COMPLETE);
 950         } else {
 951                 dwc2_release_channel(hsotg, chan, qtd,
 952                                      DWC2_HC_XFER_NO_HALT_STATUS);
 953         }
 954
 955         return 1;       /* Indicates that channel released */
 956 }
 957
 958 /*
 959  * Handles a host channel Transfer Complete interrupt. This handler may be
 960  * called in either DMA mode or Slave mode.
 961  */
 962 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 963                                   struct dwc2_host_chan *chan, int chnum,
 964                                   struct dwc2_qtd *qtd)
 965 {
 966         struct dwc2_hcd_urb *urb = qtd->urb;
 967         enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 968         int pipe_type;
 969         int urb_xfer_done;
 970
 971         if (dbg_hc(chan))
 972                 dev_vdbg(hsotg->dev,
 973                          "--Host Channel %d Interrupt: Transfer Complete--\n",
 974                          chnum);
 975
 976         if (!urb)
 977                 goto handle_xfercomp_done;
 978
 979         pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
 980
 981         if (hsotg->params.dma_desc_enable) {
 982                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
 983                 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
 984                         /* Do not disable the interrupt, just clear it */
 985                         return;
 986                 goto handle_xfercomp_done;
 987         }
 988
 989         /* Handle xfer complete on CSPLIT */
 990         if (chan->qh->do_split) {
 991                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 992                     hsotg->params.host_dma) {
 993                         if (qtd->complete_split &&
 994                             dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
 995                                                         qtd))
 996                                 goto handle_xfercomp_done;
 997                 } else {
 998                         qtd->complete_split = 0;
 999                 }
1000         }
1001
1002         /* Update the QTD and URB states */
1003         switch (pipe_type) {
1004         case USB_ENDPOINT_XFER_CONTROL:
1005                 switch (qtd->control_phase) {
1006                 case DWC2_CONTROL_SETUP:
1007                         if (urb->length > 0)
1008                                 qtd->control_phase = DWC2_CONTROL_DATA;
1009                         else
1010                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1011                         dev_vdbg(hsotg->dev,
1012                                  "  Control setup transaction done\n");
1013                         halt_status = DWC2_HC_XFER_COMPLETE;
1014                         break;
1015                 case DWC2_CONTROL_DATA:
1016                         urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1017                                                               chnum, urb, qtd);
1018                         if (urb_xfer_done) {
1019                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1020                                 dev_vdbg(hsotg->dev,
1021                                          "  Control data transfer done\n");
1022                         } else {
1023                                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1024                                                           qtd);
1025                         }
1026                         halt_status = DWC2_HC_XFER_COMPLETE;
1027                         break;
1028                 case DWC2_CONTROL_STATUS:
1029                         dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1030                         if (urb->status == -EINPROGRESS)
1031                                 urb->status = 0;
1032                         dwc2_host_complete(hsotg, qtd, urb->status);
1033                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1034                         break;
1035                 }
1036
1037                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1038                                                 halt_status);
1039                 break;
1040         case USB_ENDPOINT_XFER_BULK:
1041                 dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1042                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1043                                                       qtd);
1044                 if (urb_xfer_done) {
1045                         dwc2_host_complete(hsotg, qtd, urb->status);
1046                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1047                 } else {
1048                         halt_status = DWC2_HC_XFER_COMPLETE;
1049                 }
1050
1051                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1052                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1053                                                 halt_status);
1054                 break;
1055         case USB_ENDPOINT_XFER_INT:
1056                 dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1057                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1058                                                       qtd);
1059
1060                 /*
1061                  * Interrupt URB is done on the first transfer complete
1062                  * interrupt
1063                  */
1064                 if (urb_xfer_done) {
1065                         dwc2_host_complete(hsotg, qtd, urb->status);
1066                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1067                 } else {
1068                         halt_status = DWC2_HC_XFER_COMPLETE;
1069                 }
1070
1071                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1072                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1073                                             halt_status);
1074                 break;
1075         case USB_ENDPOINT_XFER_ISOC:
1076                 if (dbg_perio())
1077                         dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1078                 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1079                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1080                                                         chnum, qtd,
1081                                                         DWC2_HC_XFER_COMPLETE);
1082                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1083                                             halt_status);
1084                 break;
1085         }
1086
1087 handle_xfercomp_done:
1088         disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1089 }
1090
1091 /*
1092  * Handles a host channel STALL interrupt. This handler may be called in
1093  * either DMA mode or Slave mode.
1094  */
1095 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1096                                struct dwc2_host_chan *chan, int chnum,
1097                                struct dwc2_qtd *qtd)
1098 {
1099         struct dwc2_hcd_urb *urb = qtd->urb;
1100         int pipe_type;
1101
1102         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1103                 chnum);
1104
1105         if (hsotg->params.dma_desc_enable) {
1106                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1107                                             DWC2_HC_XFER_STALL);
1108                 goto handle_stall_done;
1109         }
1110
1111         if (!urb)
1112                 goto handle_stall_halt;
1113
1114         pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1115
1116         if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1117                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1118
1119         if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1120             pipe_type == USB_ENDPOINT_XFER_INT) {
1121                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1122                 /*
1123                  * USB protocol requires resetting the data toggle for bulk
1124                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1125                  * setup command is issued to the endpoint. Anticipate the
1126                  * CLEAR_FEATURE command since a STALL has occurred and reset
1127                  * the data toggle now.
1128                  */
1129                 chan->qh->data_toggle = 0;
1130         }
1131
1132 handle_stall_halt:
1133         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1134
1135 handle_stall_done:
1136         disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1137 }
1138
1139 /*
1140  * Updates the state of the URB when a transfer has been stopped due to an
1141  * abnormal condition before the transfer completes. Modifies the
1142  * actual_length field of the URB to reflect the number of bytes that have
1143  * actually been transferred via the host channel.
1144  */
1145 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1146                                       struct dwc2_host_chan *chan, int chnum,
1147                                       struct dwc2_hcd_urb *urb,
1148                                       struct dwc2_qtd *qtd,
1149                                       enum dwc2_halt_status halt_status)
1150 {
1151         u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1152                                                       qtd, halt_status, NULL);
1153         u32 hctsiz;
1154
1155         if (urb->actual_length + xfer_length > urb->length) {
1156                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1157                 xfer_length = urb->length - urb->actual_length;
1158         }
1159
1160         urb->actual_length += xfer_length;
1161
1162         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1163         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1164                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1165         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1166                  chan->start_pkt_count);
1167         dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1168                  (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1169         dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1170         dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1171                  xfer_length);
1172         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1173                  urb->actual_length);
1174         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1175                  urb->length);
1176 }
1177
1178 /*
1179  * Handles a host channel NAK interrupt. This handler may be called in either
1180  * DMA mode or Slave mode.
1181  */
1182 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1183                              struct dwc2_host_chan *chan, int chnum,
1184                              struct dwc2_qtd *qtd)
1185 {
1186         if (!qtd) {
1187                 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1188                 return;
1189         }
1190
1191         if (!qtd->urb) {
1192                 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1193                 return;
1194         }
1195
1196         if (dbg_hc(chan))
1197                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1198                          chnum);
1199
1200         /*
1201          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1202          * interrupt. Re-start the SSPLIT transfer.
1203          */
1204         if (chan->do_split) {
1205                 if (chan->complete_split)
1206                         qtd->error_count = 0;
1207                 qtd->complete_split = 0;
1208                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1209                 goto handle_nak_done;
1210         }
1211
1212         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1213         case USB_ENDPOINT_XFER_CONTROL:
1214         case USB_ENDPOINT_XFER_BULK:
1215                 if (hsotg->params.host_dma && chan->ep_is_in) {
1216                         /*
1217                          * NAK interrupts are enabled on bulk/control IN
1218                          * transfers in DMA mode for the sole purpose of
1219                          * resetting the error count after a transaction error
1220                          * occurs. The core will continue transferring data.
1221                          */
1222                         qtd->error_count = 0;
1223                         break;
1224                 }
1225
1226                 /*
1227                  * NAK interrupts normally occur during OUT transfers in DMA
1228                  * or Slave mode. For IN transfers, more requests will be
1229                  * queued as request queue space is available.
1230                  */
1231                 qtd->error_count = 0;
1232
1233                 if (!chan->qh->ping_state) {
1234                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1235                                                   qtd, DWC2_HC_XFER_NAK);
1236                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1237
1238                         if (chan->speed == USB_SPEED_HIGH)
1239                                 chan->qh->ping_state = 1;
1240                 }
1241
1242                 /*
1243                  * Halt the channel so the transfer can be re-started from
1244                  * the appropriate point or the PING protocol will
1245                  * start/continue
1246                  */
1247                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1248                 break;
1249         case USB_ENDPOINT_XFER_INT:
1250                 qtd->error_count = 0;
1251                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1252                 break;
1253         case USB_ENDPOINT_XFER_ISOC:
1254                 /* Should never get called for isochronous transfers */
1255                 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1256                 break;
1257         }
1258
1259 handle_nak_done:
1260         disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1261 }
1262
1263 /*
1264  * Handles a host channel ACK interrupt. This interrupt is enabled when
1265  * performing the PING protocol in Slave mode, when errors occur during
1266  * either Slave mode or DMA mode, and during Start Split transactions.
1267  */
1268 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1269                              struct dwc2_host_chan *chan, int chnum,
1270                              struct dwc2_qtd *qtd)
1271 {
1272         struct dwc2_hcd_iso_packet_desc *frame_desc;
1273
1274         if (dbg_hc(chan))
1275                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1276                          chnum);
1277
1278         if (chan->do_split) {
1279                 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1280                 if (!chan->ep_is_in &&
1281                     chan->data_pid_start != DWC2_HC_PID_SETUP)
1282                         qtd->ssplit_out_xfer_count = chan->xfer_len;
1283
1284                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1285                         qtd->complete_split = 1;
1286                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1287                 } else {
1288                         /* ISOC OUT */
1289                         switch (chan->xact_pos) {
1290                         case DWC2_HCSPLT_XACTPOS_ALL:
1291                                 break;
1292                         case DWC2_HCSPLT_XACTPOS_END:
1293                                 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1294                                 qtd->isoc_split_offset = 0;
1295                                 break;
1296                         case DWC2_HCSPLT_XACTPOS_BEGIN:
1297                         case DWC2_HCSPLT_XACTPOS_MID:
1298                                 /*
1299                                  * For BEGIN or MID, calculate the length for
1300                                  * the next microframe to determine the correct
1301                                  * SSPLIT token, either MID or END
1302                                  */
1303                                 frame_desc = &qtd->urb->iso_descs[
1304                                                 qtd->isoc_frame_index];
1305                                 qtd->isoc_split_offset += 188;
1306
1307                                 if (frame_desc->length - qtd->isoc_split_offset
1308                                                         <= 188)
1309                                         qtd->isoc_split_pos =
1310                                                         DWC2_HCSPLT_XACTPOS_END;
1311                                 else
1312                                         qtd->isoc_split_pos =
1313                                                         DWC2_HCSPLT_XACTPOS_MID;
1314                                 break;
1315                         }
1316                 }
1317         } else {
1318                 qtd->error_count = 0;
1319
1320                 if (chan->qh->ping_state) {
1321                         chan->qh->ping_state = 0;
1322                         /*
1323                          * Halt the channel so the transfer can be re-started
1324                          * from the appropriate point. This only happens in
1325                          * Slave mode. In DMA mode, the ping_state is cleared
1326                          * when the transfer is started because the core
1327                          * automatically executes the PING, then the transfer.
1328                          */
1329                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1330                 }
1331         }
1332
1333         /*
1334          * If the ACK occurred when _not_ in the PING state, let the channel
1335          * continue transferring data after clearing the error count
1336          */
1337         disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1338 }
1339
1340 /*
1341  * Handles a host channel NYET interrupt. This interrupt should only occur on
1342  * Bulk and Control OUT endpoints and for complete split transactions. If a
1343  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1344  * handled in the xfercomp interrupt handler, not here. This handler may be
1345  * called in either DMA mode or Slave mode.
1346  */
1347 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1348                               struct dwc2_host_chan *chan, int chnum,
1349                               struct dwc2_qtd *qtd)
1350 {
1351         if (dbg_hc(chan))
1352                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1353                          chnum);
1354
1355         /*
1356          * NYET on CSPLIT
1357          * re-do the CSPLIT immediately on non-periodic
1358          */
1359         if (chan->do_split && chan->complete_split) {
1360                 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1361                     hsotg->params.host_dma) {
1362                         qtd->complete_split = 0;
1363                         qtd->isoc_split_offset = 0;
1364                         qtd->isoc_frame_index++;
1365                         if (qtd->urb &&
1366                             qtd->isoc_frame_index == qtd->urb->packet_count) {
1367                                 dwc2_host_complete(hsotg, qtd, 0);
1368                                 dwc2_release_channel(hsotg, chan, qtd,
1369                                                      DWC2_HC_XFER_URB_COMPLETE);
1370                         } else {
1371                                 dwc2_release_channel(hsotg, chan, qtd,
1372                                                 DWC2_HC_XFER_NO_HALT_STATUS);
1373                         }
1374                         goto handle_nyet_done;
1375                 }
1376
1377                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1378                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1379                         struct dwc2_qh *qh = chan->qh;
1380                         bool past_end;
1381
1382                         if (!hsotg->params.uframe_sched) {
1383                                 int frnum = dwc2_hcd_get_frame_number(hsotg);
1384
1385                                 /* Don't have num_hs_transfers; simple logic */
1386                                 past_end = dwc2_full_frame_num(frnum) !=
1387                                      dwc2_full_frame_num(qh->next_active_frame);
1388                         } else {
1389                                 int end_frnum;
1390
1391                                 /*
1392                                  * Figure out the end frame based on
1393                                  * schedule.
1394                                  *
1395                                  * We don't want to go on trying again
1396                                  * and again forever. Let's stop when
1397                                  * we've done all the transfers that
1398                                  * were scheduled.
1399                                  *
1400                                  * We're going to be comparing
1401                                  * start_active_frame and
1402                                  * next_active_frame, both of which
1403                                  * are 1 before the time the packet
1404                                  * goes on the wire, so that cancels
1405                                  * out. Basically if had 1 transfer
1406                                  * and we saw 1 NYET then we're done.
1407                                  * We're getting a NYET here so if
1408                                  * next >= (start + num_transfers)
1409                                  * we're done. The complexity is that
1410                                  * for all but ISOC_OUT we skip one
1411                                  * slot.
1412                                  */
1413                                 end_frnum = dwc2_frame_num_inc(
1414                                         qh->start_active_frame,
1415                                         qh->num_hs_transfers);
1416
1417                                 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
1418                                     qh->ep_is_in)
1419                                         end_frnum =
1420                                                dwc2_frame_num_inc(end_frnum, 1);
1421
1422                                 past_end = dwc2_frame_num_le(
1423                                         end_frnum, qh->next_active_frame);
1424                         }
1425
1426                         if (past_end) {
1427                                 /* Treat this as a transaction error. */
1428 #if 0
1429                                 /*
1430                                  * Todo: Fix system performance so this can
1431                                  * be treated as an error. Right now complete
1432                                  * splits cannot be scheduled precisely enough
1433                                  * due to other system activity, so this error
1434                                  * occurs regularly in Slave mode.
1435                                  */
1436                                 qtd->error_count++;
1437 #endif
1438                                 qtd->complete_split = 0;
1439                                 dwc2_halt_channel(hsotg, chan, qtd,
1440                                                   DWC2_HC_XFER_XACT_ERR);
1441                                 /* Todo: add support for isoc release */
1442                                 goto handle_nyet_done;
1443                         }
1444                 }
1445
1446                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1447                 goto handle_nyet_done;
1448         }
1449
1450         chan->qh->ping_state = 1;
1451         qtd->error_count = 0;
1452
1453         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1454                                   DWC2_HC_XFER_NYET);
1455         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1456
1457         /*
1458          * Halt the channel and re-start the transfer so the PING protocol
1459          * will start
1460          */
1461         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1462
1463 handle_nyet_done:
1464         disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1465 }
1466
1467 /*
1468  * Handles a host channel babble interrupt. This handler may be called in
1469  * either DMA mode or Slave mode.
1470  */
1471 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1472                                 struct dwc2_host_chan *chan, int chnum,
1473                                 struct dwc2_qtd *qtd)
1474 {
1475         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1476                 chnum);
1477
1478         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1479
1480         if (hsotg->params.dma_desc_enable) {
1481                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1482                                             DWC2_HC_XFER_BABBLE_ERR);
1483                 goto disable_int;
1484         }
1485
1486         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1487                 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1488                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1489         } else {
1490                 enum dwc2_halt_status halt_status;
1491
1492                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1493                                                 qtd, DWC2_HC_XFER_BABBLE_ERR);
1494                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1495         }
1496
1497 disable_int:
1498         disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1499 }
1500
1501 /*
1502  * Handles a host channel AHB error interrupt. This handler is only called in
1503  * DMA mode.
1504  */
1505 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1506                                 struct dwc2_host_chan *chan, int chnum,
1507                                 struct dwc2_qtd *qtd)
1508 {
1509         struct dwc2_hcd_urb *urb = qtd->urb;
1510         char *pipetype, *speed;
1511         u32 hcchar;
1512         u32 hcsplt;
1513         u32 hctsiz;
1514         u32 hc_dma;
1515
1516         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1517                 chnum);
1518
1519         if (!urb)
1520                 goto handle_ahberr_halt;
1521
1522         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1523
1524         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1525         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1526         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1527         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1528
1529         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1530         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1531         dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1532         dev_err(hsotg->dev, "  Device address: %d\n",
1533                 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1534         dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1535                 dwc2_hcd_get_ep_num(&urb->pipe_info),
1536                 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1537
1538         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1539         case USB_ENDPOINT_XFER_CONTROL:
1540                 pipetype = "CONTROL";
1541                 break;
1542         case USB_ENDPOINT_XFER_BULK:
1543                 pipetype = "BULK";
1544                 break;
1545         case USB_ENDPOINT_XFER_INT:
1546                 pipetype = "INTERRUPT";
1547                 break;
1548         case USB_ENDPOINT_XFER_ISOC:
1549                 pipetype = "ISOCHRONOUS";
1550                 break;
1551         default:
1552                 pipetype = "UNKNOWN";
1553                 break;
1554         }
1555
1556         dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1557
1558         switch (chan->speed) {
1559         case USB_SPEED_HIGH:
1560                 speed = "HIGH";
1561                 break;
1562         case USB_SPEED_FULL:
1563                 speed = "FULL";
1564                 break;
1565         case USB_SPEED_LOW:
1566                 speed = "LOW";
1567                 break;
1568         default:
1569                 speed = "UNKNOWN";
1570                 break;
1571         }
1572
1573         dev_err(hsotg->dev, "  Speed: %s\n", speed);
1574
1575         dev_err(hsotg->dev, "  Max packet size: %d\n",
1576                 dwc2_hcd_get_mps(&urb->pipe_info));
1577         dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1578         dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1579                 urb->buf, (unsigned long)urb->dma);
1580         dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1581                 urb->setup_packet, (unsigned long)urb->setup_dma);
1582         dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1583
1584         /* Core halts the channel for Descriptor DMA mode */
1585         if (hsotg->params.dma_desc_enable) {
1586                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1587                                             DWC2_HC_XFER_AHB_ERR);
1588                 goto handle_ahberr_done;
1589         }
1590
1591         dwc2_host_complete(hsotg, qtd, -EIO);
1592
1593 handle_ahberr_halt:
1594         /*
1595          * Force a channel halt. Don't call dwc2_halt_channel because that won't
1596          * write to the HCCHARn register in DMA mode to force the halt.
1597          */
1598         dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1599
1600 handle_ahberr_done:
1601         disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1602 }
1603
1604 /*
1605  * Handles a host channel transaction error interrupt. This handler may be
1606  * called in either DMA mode or Slave mode.
1607  */
1608 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1609                                  struct dwc2_host_chan *chan, int chnum,
1610                                  struct dwc2_qtd *qtd)
1611 {
1612         dev_dbg(hsotg->dev,
1613                 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1614
1615         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1616
1617         if (hsotg->params.dma_desc_enable) {
1618                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1619                                             DWC2_HC_XFER_XACT_ERR);
1620                 goto handle_xacterr_done;
1621         }
1622
1623         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1624         case USB_ENDPOINT_XFER_CONTROL:
1625         case USB_ENDPOINT_XFER_BULK:
1626                 qtd->error_count++;
1627                 if (!chan->qh->ping_state) {
1628                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1629                                                   qtd, DWC2_HC_XFER_XACT_ERR);
1630                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1631                         if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1632                                 chan->qh->ping_state = 1;
1633                 }
1634
1635                 /*
1636                  * Halt the channel so the transfer can be re-started from
1637                  * the appropriate point or the PING protocol will start
1638                  */
1639                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1640                 break;
1641         case USB_ENDPOINT_XFER_INT:
1642                 qtd->error_count++;
1643                 if (chan->do_split && chan->complete_split)
1644                         qtd->complete_split = 0;
1645                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1646                 break;
1647         case USB_ENDPOINT_XFER_ISOC:
1648                 {
1649                         enum dwc2_halt_status halt_status;
1650
1651                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1652                                          chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1653                         dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1654                 }
1655                 break;
1656         }
1657
1658 handle_xacterr_done:
1659         disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1660 }
1661
1662 /*
1663  * Handles a host channel frame overrun interrupt. This handler may be called
1664  * in either DMA mode or Slave mode.
1665  */
1666 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1667                                   struct dwc2_host_chan *chan, int chnum,
1668                                   struct dwc2_qtd *qtd)
1669 {
1670         enum dwc2_halt_status halt_status;
1671
1672         if (dbg_hc(chan))
1673                 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1674                         chnum);
1675
1676         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1677
1678         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1679         case USB_ENDPOINT_XFER_CONTROL:
1680         case USB_ENDPOINT_XFER_BULK:
1681                 break;
1682         case USB_ENDPOINT_XFER_INT:
1683                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1684                 break;
1685         case USB_ENDPOINT_XFER_ISOC:
1686                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1687                                         qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1688                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1689                 break;
1690         }
1691
1692         disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1693 }
1694
1695 /*
1696  * Handles a host channel data toggle error interrupt. This handler may be
1697  * called in either DMA mode or Slave mode.
1698  */
1699 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1700                                     struct dwc2_host_chan *chan, int chnum,
1701                                     struct dwc2_qtd *qtd)
1702 {
1703         dev_dbg(hsotg->dev,
1704                 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1705
1706         if (chan->ep_is_in)
1707                 qtd->error_count = 0;
1708         else
1709                 dev_err(hsotg->dev,
1710                         "Data Toggle Error on OUT transfer, channel %d\n",
1711                         chnum);
1712
1713         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1714         disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1715 }
1716
1717 /*
1718  * For debug only. It checks that a valid halt status is set and that
1719  * HCCHARn.chdis is clear. If there's a problem, corrective action is
1720  * taken and a warning is issued.
1721  *
1722  * Return: true if halt status is ok, false otherwise
1723  */
1724 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1725                                 struct dwc2_host_chan *chan, int chnum,
1726                                 struct dwc2_qtd *qtd)
1727 {
1728 #ifdef DEBUG
1729         u32 hcchar;
1730         u32 hctsiz;
1731         u32 hcintmsk;
1732         u32 hcsplt;
1733
1734         if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1735                 /*
1736                  * This code is here only as a check. This condition should
1737                  * never happen. Ignore the halt if it does occur.
1738                  */
1739                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1740                 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1741                 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1742                 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1743                 dev_dbg(hsotg->dev,
1744                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1745                          __func__);
1746                 dev_dbg(hsotg->dev,
1747                         "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1748                         chnum, hcchar, hctsiz);
1749                 dev_dbg(hsotg->dev,
1750                         "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1751                         chan->hcint, hcintmsk, hcsplt);
1752                 if (qtd)
1753                         dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1754                                 qtd->complete_split);
1755                 dev_warn(hsotg->dev,
1756                          "%s: no halt status, channel %d, ignoring interrupt\n",
1757                          __func__, chnum);
1758                 return false;
1759         }
1760
1761         /*
1762          * This code is here only as a check. hcchar.chdis should never be set
1763          * when the halt interrupt occurs. Halt the channel again if it does
1764          * occur.
1765          */
1766         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1767         if (hcchar & HCCHAR_CHDIS) {
1768                 dev_warn(hsotg->dev,
1769                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1770                          __func__, hcchar);
1771                 chan->halt_pending = 0;
1772                 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1773                 return false;
1774         }
1775 #endif
1776
1777         return true;
1778 }
1779
1780 /*
1781  * Handles a host Channel Halted interrupt in DMA mode. This handler
1782  * determines the reason the channel halted and proceeds accordingly.
1783  */
1784 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1785                                     struct dwc2_host_chan *chan, int chnum,
1786                                     struct dwc2_qtd *qtd)
1787 {
1788         u32 hcintmsk;
1789         int out_nak_enh = 0;
1790
1791         if (dbg_hc(chan))
1792                 dev_vdbg(hsotg->dev,
1793                          "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1794                          chnum);
1795
1796         /*
1797          * For core with OUT NAK enhancement, the flow for high-speed
1798          * CONTROL/BULK OUT is handled a little differently
1799          */
1800         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1801                 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1802                     (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1803                      chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1804                         out_nak_enh = 1;
1805                 }
1806         }
1807
1808         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1809             (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1810              !hsotg->params.dma_desc_enable)) {
1811                 if (hsotg->params.dma_desc_enable)
1812                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1813                                                     chan->halt_status);
1814                 else
1815                         /*
1816                          * Just release the channel. A dequeue can happen on a
1817                          * transfer timeout. In the case of an AHB Error, the
1818                          * channel was forced to halt because there's no way to
1819                          * gracefully recover.
1820                          */
1821                         dwc2_release_channel(hsotg, chan, qtd,
1822                                              chan->halt_status);
1823                 return;
1824         }
1825
1826         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1827
1828         if (chan->hcint & HCINTMSK_XFERCOMPL) {
1829                 /*
1830                  * Todo: This is here because of a possible hardware bug. Spec
1831                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1832                  * interrupt w/ACK bit set should occur, but I only see the
1833                  * XFERCOMP bit, even with it masked out. This is a workaround
1834                  * for that behavior. Should fix this when hardware is fixed.
1835                  */
1836                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1837                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1838                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1839         } else if (chan->hcint & HCINTMSK_STALL) {
1840                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1841         } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1842                    !hsotg->params.dma_desc_enable) {
1843                 if (out_nak_enh) {
1844                         if (chan->hcint &
1845                             (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1846                                 dev_vdbg(hsotg->dev,
1847                                          "XactErr with NYET/NAK/ACK\n");
1848                                 qtd->error_count = 0;
1849                         } else {
1850                                 dev_vdbg(hsotg->dev,
1851                                          "XactErr without NYET/NAK/ACK\n");
1852                         }
1853                 }
1854
1855                 /*
1856                  * Must handle xacterr before nak or ack. Could get a xacterr
1857                  * at the same time as either of these on a BULK/CONTROL OUT
1858                  * that started with a PING. The xacterr takes precedence.
1859                  */
1860                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1861         } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1862                    hsotg->params.dma_desc_enable) {
1863                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1864         } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1865                    hsotg->params.dma_desc_enable) {
1866                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1867         } else if (chan->hcint & HCINTMSK_BBLERR) {
1868                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1869         } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1870                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1871         } else if (!out_nak_enh) {
1872                 if (chan->hcint & HCINTMSK_NYET) {
1873                         /*
1874                          * Must handle nyet before nak or ack. Could get a nyet
1875                          * at the same time as either of those on a BULK/CONTROL
1876                          * OUT that started with a PING. The nyet takes
1877                          * precedence.
1878                          */
1879                         dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1880                 } else if ((chan->hcint & HCINTMSK_NAK) &&
1881                            !(hcintmsk & HCINTMSK_NAK)) {
1882                         /*
1883                          * If nak is not masked, it's because a non-split IN
1884                          * transfer is in an error state. In that case, the nak
1885                          * is handled by the nak interrupt handler, not here.
1886                          * Handle nak here for BULK/CONTROL OUT transfers, which
1887                          * halt on a NAK to allow rewinding the buffer pointer.
1888                          */
1889                         dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1890                 } else if ((chan->hcint & HCINTMSK_ACK) &&
1891                            !(hcintmsk & HCINTMSK_ACK)) {
1892                         /*
1893                          * If ack is not masked, it's because a non-split IN
1894                          * transfer is in an error state. In that case, the ack
1895                          * is handled by the ack interrupt handler, not here.
1896                          * Handle ack here for split transfers. Start splits
1897                          * halt on ACK.
1898                          */
1899                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1900                 } else {
1901                         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1902                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1903                                 /*
1904                                  * A periodic transfer halted with no other
1905                                  * channel interrupts set. Assume it was halted
1906                                  * by the core because it could not be completed
1907                                  * in its scheduled (micro)frame.
1908                                  */
1909                                 dev_dbg(hsotg->dev,
1910                                         "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1911                                         __func__, chnum);
1912                                 dwc2_halt_channel(hsotg, chan, qtd,
1913                                         DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1914                         } else {
1915                                 dev_err(hsotg->dev,
1916                                         "%s: Channel %d - ChHltd set, but reason is unknown\n",
1917                                         __func__, chnum);
1918                                 dev_err(hsotg->dev,
1919                                         "hcint 0x%08x, intsts 0x%08x\n",
1920                                         chan->hcint,
1921                                         dwc2_readl(hsotg->regs + GINTSTS));
1922                                 goto error;
1923                         }
1924                 }
1925         } else {
1926                 dev_info(hsotg->dev,
1927                          "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1928                          chan->hcint);
1929 error:
1930                 /* Failthrough: use 3-strikes rule */
1931                 qtd->error_count++;
1932                 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1933                                           qtd, DWC2_HC_XFER_XACT_ERR);
1934                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1935                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1936         }
1937 }
1938
1939 /*
1940  * Handles a host channel Channel Halted interrupt
1941  *
1942  * In slave mode, this handler is called only when the driver specifically
1943  * requests a halt. This occurs during handling other host channel interrupts
1944  * (e.g. nak, xacterr, stall, nyet, etc.).
1945  *
1946  * In DMA mode, this is the interrupt that occurs when the core has finished
1947  * processing a transfer on a channel. Other host channel interrupts (except
1948  * ahberr) are disabled in DMA mode.
1949  */
1950 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1951                                 struct dwc2_host_chan *chan, int chnum,
1952                                 struct dwc2_qtd *qtd)
1953 {
1954         if (dbg_hc(chan))
1955                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1956                          chnum);
1957
1958         if (hsotg->params.host_dma) {
1959                 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1960         } else {
1961                 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1962                         return;
1963                 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1964         }
1965 }
1966
1967 /*
1968  * Check if the given qtd is still the top of the list (and thus valid).
1969  *
1970  * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1971  * the qtd from the top of the list, this will return false (otherwise true).
1972  */
1973 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1974 {
1975         struct dwc2_qtd *cur_head;
1976
1977         if (!qh)
1978                 return false;
1979
1980         cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1981                                     qtd_list_entry);
1982         return (cur_head == qtd);
1983 }
1984
1985 /* Handles interrupt for a specific Host Channel */
1986 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1987 {
1988         struct dwc2_qtd *qtd;
1989         struct dwc2_host_chan *chan;
1990         u32 hcint, hcintmsk;
1991
1992         chan = hsotg->hc_ptr_array[chnum];
1993
1994         hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1995         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1996         if (!chan) {
1997                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1998                 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
1999                 return;
2000         }
2001
2002         if (dbg_hc(chan)) {
2003                 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2004                          chnum);
2005                 dev_vdbg(hsotg->dev,
2006                          "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2007                          hcint, hcintmsk, hcint & hcintmsk);
2008         }
2009
2010         dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2011
2012         /*
2013          * If we got an interrupt after someone called
2014          * dwc2_hcd_endpoint_disable() we don't want to crash below
2015          */
2016         if (!chan->qh) {
2017                 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2018                 return;
2019         }
2020
2021         chan->hcint = hcint;
2022         hcint &= hcintmsk;
2023
2024         /*
2025          * If the channel was halted due to a dequeue, the qtd list might
2026          * be empty or at least the first entry will not be the active qtd.
2027          * In this case, take a shortcut and just release the channel.
2028          */
2029         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2030                 /*
2031                  * If the channel was halted, this should be the only
2032                  * interrupt unmasked
2033                  */
2034                 WARN_ON(hcint != HCINTMSK_CHHLTD);
2035                 if (hsotg->params.dma_desc_enable)
2036                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2037                                                     chan->halt_status);
2038                 else
2039                         dwc2_release_channel(hsotg, chan, NULL,
2040                                              chan->halt_status);
2041                 return;
2042         }
2043
2044         if (list_empty(&chan->qh->qtd_list)) {
2045                 /*
2046                  * TODO: Will this ever happen with the
2047                  * DWC2_HC_XFER_URB_DEQUEUE handling above?
2048                  */
2049                 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2050                         chnum);
2051                 dev_dbg(hsotg->dev,
2052                         "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2053                         chan->hcint, hcintmsk, hcint);
2054                 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2055                 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2056                 chan->hcint = 0;
2057                 return;
2058         }
2059
2060         qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2061                                qtd_list_entry);
2062
2063         if (!hsotg->params.host_dma) {
2064                 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2065                         hcint &= ~HCINTMSK_CHHLTD;
2066         }
2067
2068         if (hcint & HCINTMSK_XFERCOMPL) {
2069                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2070                 /*
2071                  * If NYET occurred at same time as Xfer Complete, the NYET is
2072                  * handled by the Xfer Complete interrupt handler. Don't want
2073                  * to call the NYET interrupt handler in this case.
2074                  */
2075                 hcint &= ~HCINTMSK_NYET;
2076         }
2077
2078         if (hcint & HCINTMSK_CHHLTD) {
2079                 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2080                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2081                         goto exit;
2082         }
2083         if (hcint & HCINTMSK_AHBERR) {
2084                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2085                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2086                         goto exit;
2087         }
2088         if (hcint & HCINTMSK_STALL) {
2089                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2090                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2091                         goto exit;
2092         }
2093         if (hcint & HCINTMSK_NAK) {
2094                 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2095                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2096                         goto exit;
2097         }
2098         if (hcint & HCINTMSK_ACK) {
2099                 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2100                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2101                         goto exit;
2102         }
2103         if (hcint & HCINTMSK_NYET) {
2104                 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2105                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2106                         goto exit;
2107         }
2108         if (hcint & HCINTMSK_XACTERR) {
2109                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2110                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2111                         goto exit;
2112         }
2113         if (hcint & HCINTMSK_BBLERR) {
2114                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2115                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2116                         goto exit;
2117         }
2118         if (hcint & HCINTMSK_FRMOVRUN) {
2119                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2120                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2121                         goto exit;
2122         }
2123         if (hcint & HCINTMSK_DATATGLERR) {
2124                 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2125                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2126                         goto exit;
2127         }
2128
2129 exit:
2130         chan->hcint = 0;
2131 }
2132
2133 /*
2134  * This interrupt indicates that one or more host channels has a pending
2135  * interrupt. There are multiple conditions that can cause each host channel
2136  * interrupt. This function determines which conditions have occurred for each
2137  * host channel interrupt and handles them appropriately.
2138  */
2139 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2140 {
2141         u32 haint;
2142         int i;
2143         struct dwc2_host_chan *chan, *chan_tmp;
2144
2145         haint = dwc2_readl(hsotg->regs + HAINT);
2146         if (dbg_perio()) {
2147                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2148
2149                 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2150         }
2151
2152         /*
2153          * According to USB 2.0 spec section 11.18.8, a host must
2154          * issue complete-split transactions in a microframe for a
2155          * set of full-/low-speed endpoints in the same relative
2156          * order as the start-splits were issued in a microframe for.
2157          */
2158         list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2159                                  split_order_list_entry) {
2160                 int hc_num = chan->hc_num;
2161
2162                 if (haint & (1 << hc_num)) {
2163                         dwc2_hc_n_intr(hsotg, hc_num);
2164                         haint &= ~(1 << hc_num);
2165                 }
2166         }
2167
2168         for (i = 0; i < hsotg->params.host_channels; i++) {
2169                 if (haint & (1 << i))
2170                         dwc2_hc_n_intr(hsotg, i);
2171         }
2172 }
2173
2174 /* This function handles interrupts for the HCD */
2175 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2176 {
2177         u32 gintsts, dbg_gintsts;
2178         irqreturn_t retval = IRQ_NONE;
2179
2180         if (!dwc2_is_controller_alive(hsotg)) {
2181                 dev_warn(hsotg->dev, "Controller is dead\n");
2182                 return retval;
2183         }
2184
2185         spin_lock(&hsotg->lock);
2186
2187         /* Check if HOST Mode */
2188         if (dwc2_is_host_mode(hsotg)) {
2189                 gintsts = dwc2_read_core_intr(hsotg);
2190                 if (!gintsts) {
2191                         spin_unlock(&hsotg->lock);
2192                         return retval;
2193                 }
2194
2195                 retval = IRQ_HANDLED;
2196
2197                 dbg_gintsts = gintsts;
2198 #ifndef DEBUG_SOF
2199                 dbg_gintsts &= ~GINTSTS_SOF;
2200 #endif
2201                 if (!dbg_perio())
2202                         dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2203                                          GINTSTS_PTXFEMP);
2204
2205                 /* Only print if there are any non-suppressed interrupts left */
2206                 if (dbg_gintsts)
2207                         dev_vdbg(hsotg->dev,
2208                                  "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2209                                  gintsts);
2210
2211                 if (gintsts & GINTSTS_SOF)
2212                         dwc2_sof_intr(hsotg);
2213                 if (gintsts & GINTSTS_RXFLVL)
2214                         dwc2_rx_fifo_level_intr(hsotg);
2215                 if (gintsts & GINTSTS_NPTXFEMP)
2216                         dwc2_np_tx_fifo_empty_intr(hsotg);
2217                 if (gintsts & GINTSTS_PRTINT)
2218                         dwc2_port_intr(hsotg);
2219                 if (gintsts & GINTSTS_HCHINT)
2220                         dwc2_hc_intr(hsotg);
2221                 if (gintsts & GINTSTS_PTXFEMP)
2222                         dwc2_perio_tx_fifo_empty_intr(hsotg);
2223
2224                 if (dbg_gintsts) {
2225                         dev_vdbg(hsotg->dev,
2226                                  "DWC OTG HCD Finished Servicing Interrupts\n");
2227                         dev_vdbg(hsotg->dev,
2228                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2229                                  dwc2_readl(hsotg->regs + GINTSTS),
2230                                  dwc2_readl(hsotg->regs + GINTMSK));
2231                 }
2232         }
2233
2234         spin_unlock(&hsotg->lock);
2235
2236         return retval;
2237 }