drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <[email protected]>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include "intel_frontbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                              int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 #define VBLANK_EVASION_TIME_US 100
  69
  70 /**
  71  * intel_pipe_update_start() - start update of a set of display registers
  72  * @crtc: the crtc of which the registers are going to be updated
  73  * @start_vbl_count: vblank counter return pointer used for error checking
  74  *
  75  * Mark the start of an update to pipe registers that should be updated
  76  * atomically regarding vblank. If the next vblank will happens within
  77  * the next 100 us, this function waits until the vblank passes.
  78  *
  79  * After a successful call to this function, interrupts will be disabled
  80  * until a subsequent call to intel_pipe_update_end(). That is done to
  81  * avoid random delays. The value written to @start_vbl_count should be
  82  * supplied to intel_pipe_update_end() for error checking.
  83  */
  84 void intel_pipe_update_start(struct intel_crtc *crtc)
  85 {
  86         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  87         long timeout = msecs_to_jiffies_timeout(1);
  88         int scanline, min, max, vblank_start;
  89         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  90         DEFINE_WAIT(wait);
  91
  92         vblank_start = adjusted_mode->crtc_vblank_start;
  93         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  94                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  95
  96         /* FIXME needs to be calibrated sensibly */
  97         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
  98                                                       VBLANK_EVASION_TIME_US);
  99         max = vblank_start - 1;
 100
 101         local_irq_disable();
 102
 103         if (min <= 0 || max <= 0)
 104                 return;
 105
 106         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 107                 return;
 108
 109         crtc->debug.min_vbl = min;
 110         crtc->debug.max_vbl = max;
 111         trace_i915_pipe_update_start(crtc);
 112
 113         for (;;) {
 114                 /*
 115                  * prepare_to_wait() has a memory barrier, which guarantees
 116                  * other CPUs can see the task state update by the time we
 117                  * read the scanline.
 118                  */
 119                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 120
 121                 scanline = intel_get_crtc_scanline(crtc);
 122                 if (scanline < min || scanline > max)
 123                         break;
 124
 125                 if (timeout <= 0) {
 126                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 127                                   pipe_name(crtc->pipe));
 128                         break;
 129                 }
 130
 131                 local_irq_enable();
 132
 133                 timeout = schedule_timeout(timeout);
 134
 135                 local_irq_disable();
 136         }
 137
 138         finish_wait(wq, &wait);
 139
 140         drm_crtc_vblank_put(&crtc->base);
 141
 142         crtc->debug.scanline_start = scanline;
 143         crtc->debug.start_vbl_time = ktime_get();
 144         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 145
 146         trace_i915_pipe_update_vblank_evaded(crtc);
 147 }
 148
 149 /**
 150  * intel_pipe_update_end() - end update of a set of display registers
 151  * @crtc: the crtc of which the registers were updated
 152  * @start_vbl_count: start vblank counter (used for error checking)
 153  *
 154  * Mark the end of an update started with intel_pipe_update_start(). This
 155  * re-enables interrupts and verifies the update was actually completed
 156  * before a vblank using the value of @start_vbl_count.
 157  */
 158 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
 159 {
 160         enum pipe pipe = crtc->pipe;
 161         int scanline_end = intel_get_crtc_scanline(crtc);
 162         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 163         ktime_t end_vbl_time = ktime_get();
 164         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 165
 166         if (work) {
 167                 work->flip_queued_vblank = end_vbl_count;
 168                 smp_mb__before_atomic();
 169                 atomic_set(&work->pending, 1);
 170         }
 171
 172         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 173
 174         /* We're still in the vblank-evade critical section, this can't race.
 175          * Would be slightly nice to just grab the vblank count and arm the
 176          * event outside of the critical section - the spinlock might spin for a
 177          * while ... */
 178         if (crtc->base.state->event) {
 179                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 180
 181                 spin_lock(&crtc->base.dev->event_lock);
 182                 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
 183                 spin_unlock(&crtc->base.dev->event_lock);
 184
 185                 crtc->base.state->event = NULL;
 186         }
 187
 188         local_irq_enable();
 189
 190         if (intel_vgpu_active(dev_priv))
 191                 return;
 192
 193         if (crtc->debug.start_vbl_count &&
 194             crtc->debug.start_vbl_count != end_vbl_count) {
 195                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 196                           pipe_name(pipe), crtc->debug.start_vbl_count,
 197                           end_vbl_count,
 198                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 199                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 200                           crtc->debug.scanline_start, scanline_end);
 201         }
 202 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 203         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 204                  VBLANK_EVASION_TIME_US)
 205                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 206                          pipe_name(pipe),
 207                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 208                          VBLANK_EVASION_TIME_US);
 209 #endif
 210 }
 211
 212 static void
 213 skl_update_plane(struct intel_plane *plane,
 214                  const struct intel_crtc_state *crtc_state,
 215                  const struct intel_plane_state *plane_state)
 216 {
 217         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 218         const struct drm_framebuffer *fb = plane_state->base.fb;
 219         enum plane_id plane_id = plane->id;
 220         enum pipe pipe = plane->pipe;
 221         u32 plane_ctl = plane_state->ctl;
 222         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 223         u32 surf_addr = plane_state->main.offset;
 224         unsigned int rotation = plane_state->base.rotation;
 225         u32 stride = skl_plane_stride(fb, 0, rotation);
 226         int crtc_x = plane_state->base.dst.x1;
 227         int crtc_y = plane_state->base.dst.y1;
 228         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 229         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 230         uint32_t x = plane_state->main.x;
 231         uint32_t y = plane_state->main.y;
 232         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 233         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 234         unsigned long irqflags;
 235
 236         /* Sizes are 0 based */
 237         src_w--;
 238         src_h--;
 239         crtc_w--;
 240         crtc_h--;
 241
 242         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 243
 244         if (IS_GEMINILAKE(dev_priv)) {
 245                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 246                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
 247                               PLANE_COLOR_PIPE_CSC_ENABLE |
 248                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
 249         }
 250
 251         if (key->flags) {
 252                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 253                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 254                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 255         }
 256
 257         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 258         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 259         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 260
 261         /* program plane scaler */
 262         if (plane_state->scaler_id >= 0) {
 263                 int scaler_id = plane_state->scaler_id;
 264                 const struct intel_scaler *scaler;
 265
 266                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 267
 268                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 269                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 270                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 271                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 272                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 273                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 274
 275                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 276         } else {
 277                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 278         }
 279
 280         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 281         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 282                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 283         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 284
 285         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 286 }
 287
 288 static void
 289 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 290 {
 291         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 292         enum plane_id plane_id = plane->id;
 293         enum pipe pipe = plane->pipe;
 294         unsigned long irqflags;
 295
 296         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 297
 298         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 299
 300         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 301         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 302
 303         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 304 }
 305
 306 static void
 307 chv_update_csc(struct intel_plane *plane, uint32_t format)
 308 {
 309         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 310         enum plane_id plane_id = plane->id;
 311
 312         /* Seems RGB data bypasses the CSC always */
 313         if (!format_is_yuv(format))
 314                 return;
 315
 316         /*
 317          * BT.601 limited range YCbCr -> full range RGB
 318          *
 319          * |r|   | 6537 4769     0|   |cr  |
 320          * |g| = |-3330 4769 -1605| x |y-64|
 321          * |b|   |    0 4769  8263|   |cb  |
 322          *
 323          * Cb and Cr apparently come in as signed already, so no
 324          * need for any offset. For Y we need to remove the offset.
 325          */
 326         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 327         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 328         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 329
 330         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
 331         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
 332         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
 333         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
 334         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
 335
 336         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 337         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 338         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 339
 340         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 341         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 342         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 343 }
 344
 345 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 346                           const struct intel_plane_state *plane_state)
 347 {
 348         const struct drm_framebuffer *fb = plane_state->base.fb;
 349         unsigned int rotation = plane_state->base.rotation;
 350         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 351         u32 sprctl;
 352
 353         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 354
 355         switch (fb->format->format) {
 356         case DRM_FORMAT_YUYV:
 357                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 358                 break;
 359         case DRM_FORMAT_YVYU:
 360                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 361                 break;
 362         case DRM_FORMAT_UYVY:
 363                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 364                 break;
 365         case DRM_FORMAT_VYUY:
 366                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 367                 break;
 368         case DRM_FORMAT_RGB565:
 369                 sprctl |= SP_FORMAT_BGR565;
 370                 break;
 371         case DRM_FORMAT_XRGB8888:
 372                 sprctl |= SP_FORMAT_BGRX8888;
 373                 break;
 374         case DRM_FORMAT_ARGB8888:
 375                 sprctl |= SP_FORMAT_BGRA8888;
 376                 break;
 377         case DRM_FORMAT_XBGR2101010:
 378                 sprctl |= SP_FORMAT_RGBX1010102;
 379                 break;
 380         case DRM_FORMAT_ABGR2101010:
 381                 sprctl |= SP_FORMAT_RGBA1010102;
 382                 break;
 383         case DRM_FORMAT_XBGR8888:
 384                 sprctl |= SP_FORMAT_RGBX8888;
 385                 break;
 386         case DRM_FORMAT_ABGR8888:
 387                 sprctl |= SP_FORMAT_RGBA8888;
 388                 break;
 389         default:
 390                 MISSING_CASE(fb->format->format);
 391                 return 0;
 392         }
 393
 394         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 395                 sprctl |= SP_TILED;
 396
 397         if (rotation & DRM_MODE_ROTATE_180)
 398                 sprctl |= SP_ROTATE_180;
 399
 400         if (rotation & DRM_MODE_REFLECT_X)
 401                 sprctl |= SP_MIRROR;
 402
 403         if (key->flags & I915_SET_COLORKEY_SOURCE)
 404                 sprctl |= SP_SOURCE_KEY;
 405
 406         return sprctl;
 407 }
 408
 409 static void
 410 vlv_update_plane(struct intel_plane *plane,
 411                  const struct intel_crtc_state *crtc_state,
 412                  const struct intel_plane_state *plane_state)
 413 {
 414         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 415         const struct drm_framebuffer *fb = plane_state->base.fb;
 416         enum pipe pipe = plane->pipe;
 417         enum plane_id plane_id = plane->id;
 418         u32 sprctl = plane_state->ctl;
 419         u32 sprsurf_offset = plane_state->main.offset;
 420         u32 linear_offset;
 421         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 422         int crtc_x = plane_state->base.dst.x1;
 423         int crtc_y = plane_state->base.dst.y1;
 424         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 425         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 426         uint32_t x = plane_state->main.x;
 427         uint32_t y = plane_state->main.y;
 428         unsigned long irqflags;
 429
 430         /* Sizes are 0 based */
 431         crtc_w--;
 432         crtc_h--;
 433
 434         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 435
 436         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 437
 438         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 439                 chv_update_csc(plane, fb->format->format);
 440
 441         if (key->flags) {
 442                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 443                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 444                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 445         }
 446         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 447         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 448
 449         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 450                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 451         else
 452                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 453
 454         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 455
 456         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 457         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 458         I915_WRITE_FW(SPSURF(pipe, plane_id),
 459                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 460         POSTING_READ_FW(SPSURF(pipe, plane_id));
 461
 462         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 463 }
 464
 465 static void
 466 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 467 {
 468         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 469         enum pipe pipe = plane->pipe;
 470         enum plane_id plane_id = plane->id;
 471         unsigned long irqflags;
 472
 473         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 474
 475         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 476
 477         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 478         POSTING_READ_FW(SPSURF(pipe, plane_id));
 479
 480         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 481 }
 482
 483 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 484                           const struct intel_plane_state *plane_state)
 485 {
 486         struct drm_i915_private *dev_priv =
 487                 to_i915(plane_state->base.plane->dev);
 488         const struct drm_framebuffer *fb = plane_state->base.fb;
 489         unsigned int rotation = plane_state->base.rotation;
 490         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 491         u32 sprctl;
 492
 493         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 494
 495         if (IS_IVYBRIDGE(dev_priv))
 496                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 497
 498         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 499                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 500
 501         switch (fb->format->format) {
 502         case DRM_FORMAT_XBGR8888:
 503                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 504                 break;
 505         case DRM_FORMAT_XRGB8888:
 506                 sprctl |= SPRITE_FORMAT_RGBX888;
 507                 break;
 508         case DRM_FORMAT_YUYV:
 509                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 510                 break;
 511         case DRM_FORMAT_YVYU:
 512                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 513                 break;
 514         case DRM_FORMAT_UYVY:
 515                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 516                 break;
 517         case DRM_FORMAT_VYUY:
 518                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 519                 break;
 520         default:
 521                 MISSING_CASE(fb->format->format);
 522                 return 0;
 523         }
 524
 525         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 526                 sprctl |= SPRITE_TILED;
 527
 528         if (rotation & DRM_MODE_ROTATE_180)
 529                 sprctl |= SPRITE_ROTATE_180;
 530
 531         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 532                 sprctl |= SPRITE_DEST_KEY;
 533         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 534                 sprctl |= SPRITE_SOURCE_KEY;
 535
 536         return sprctl;
 537 }
 538
 539 static void
 540 ivb_update_plane(struct intel_plane *plane,
 541                  const struct intel_crtc_state *crtc_state,
 542                  const struct intel_plane_state *plane_state)
 543 {
 544         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 545         const struct drm_framebuffer *fb = plane_state->base.fb;
 546         enum pipe pipe = plane->pipe;
 547         u32 sprctl = plane_state->ctl, sprscale = 0;
 548         u32 sprsurf_offset = plane_state->main.offset;
 549         u32 linear_offset;
 550         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 551         int crtc_x = plane_state->base.dst.x1;
 552         int crtc_y = plane_state->base.dst.y1;
 553         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 554         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 555         uint32_t x = plane_state->main.x;
 556         uint32_t y = plane_state->main.y;
 557         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 558         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 559         unsigned long irqflags;
 560
 561         /* Sizes are 0 based */
 562         src_w--;
 563         src_h--;
 564         crtc_w--;
 565         crtc_h--;
 566
 567         if (crtc_w != src_w || crtc_h != src_h)
 568                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 569
 570         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 571
 572         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 573
 574         if (key->flags) {
 575                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 576                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 577                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 578         }
 579
 580         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 581         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 582
 583         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 584          * register */
 585         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 586                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 587         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 588                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 589         else
 590                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 591
 592         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 593         if (plane->can_scale)
 594                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 595         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 596         I915_WRITE_FW(SPRSURF(pipe),
 597                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 598         POSTING_READ_FW(SPRSURF(pipe));
 599
 600         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 601 }
 602
 603 static void
 604 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 605 {
 606         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 607         enum pipe pipe = plane->pipe;
 608         unsigned long irqflags;
 609
 610         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 611
 612         I915_WRITE_FW(SPRCTL(pipe), 0);
 613         /* Can't leave the scaler enabled... */
 614         if (plane->can_scale)
 615                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 616
 617         I915_WRITE_FW(SPRSURF(pipe), 0);
 618         POSTING_READ_FW(SPRSURF(pipe));
 619
 620         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 621 }
 622
 623 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 624                           const struct intel_plane_state *plane_state)
 625 {
 626         struct drm_i915_private *dev_priv =
 627                 to_i915(plane_state->base.plane->dev);
 628         const struct drm_framebuffer *fb = plane_state->base.fb;
 629         unsigned int rotation = plane_state->base.rotation;
 630         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 631         u32 dvscntr;
 632
 633         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 634
 635         if (IS_GEN6(dev_priv))
 636                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 637
 638         switch (fb->format->format) {
 639         case DRM_FORMAT_XBGR8888:
 640                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 641                 break;
 642         case DRM_FORMAT_XRGB8888:
 643                 dvscntr |= DVS_FORMAT_RGBX888;
 644                 break;
 645         case DRM_FORMAT_YUYV:
 646                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 647                 break;
 648         case DRM_FORMAT_YVYU:
 649                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 650                 break;
 651         case DRM_FORMAT_UYVY:
 652                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 653                 break;
 654         case DRM_FORMAT_VYUY:
 655                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 656                 break;
 657         default:
 658                 MISSING_CASE(fb->format->format);
 659                 return 0;
 660         }
 661
 662         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 663                 dvscntr |= DVS_TILED;
 664
 665         if (rotation & DRM_MODE_ROTATE_180)
 666                 dvscntr |= DVS_ROTATE_180;
 667
 668         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 669                 dvscntr |= DVS_DEST_KEY;
 670         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 671                 dvscntr |= DVS_SOURCE_KEY;
 672
 673         return dvscntr;
 674 }
 675
 676 static void
 677 g4x_update_plane(struct intel_plane *plane,
 678                  const struct intel_crtc_state *crtc_state,
 679                  const struct intel_plane_state *plane_state)
 680 {
 681         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 682         const struct drm_framebuffer *fb = plane_state->base.fb;
 683         enum pipe pipe = plane->pipe;
 684         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 685         u32 dvssurf_offset = plane_state->main.offset;
 686         u32 linear_offset;
 687         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 688         int crtc_x = plane_state->base.dst.x1;
 689         int crtc_y = plane_state->base.dst.y1;
 690         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 691         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 692         uint32_t x = plane_state->main.x;
 693         uint32_t y = plane_state->main.y;
 694         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 695         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 696         unsigned long irqflags;
 697
 698         /* Sizes are 0 based */
 699         src_w--;
 700         src_h--;
 701         crtc_w--;
 702         crtc_h--;
 703
 704         if (crtc_w != src_w || crtc_h != src_h)
 705                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 706
 707         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 708
 709         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 710
 711         if (key->flags) {
 712                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 713                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 714                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 715         }
 716
 717         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 718         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 719
 720         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 721                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 722         else
 723                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 724
 725         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 726         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 727         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 728         I915_WRITE_FW(DVSSURF(pipe),
 729                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 730         POSTING_READ_FW(DVSSURF(pipe));
 731
 732         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 733 }
 734
 735 static void
 736 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 737 {
 738         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 739         enum pipe pipe = plane->pipe;
 740         unsigned long irqflags;
 741
 742         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 743
 744         I915_WRITE_FW(DVSCNTR(pipe), 0);
 745         /* Disable the scaler */
 746         I915_WRITE_FW(DVSSCALE(pipe), 0);
 747
 748         I915_WRITE_FW(DVSSURF(pipe), 0);
 749         POSTING_READ_FW(DVSSURF(pipe));
 750
 751         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 752 }
 753
 754 static int
 755 intel_check_sprite_plane(struct intel_plane *plane,
 756                          struct intel_crtc_state *crtc_state,
 757                          struct intel_plane_state *state)
 758 {
 759         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 760         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 761         struct drm_framebuffer *fb = state->base.fb;
 762         int crtc_x, crtc_y;
 763         unsigned int crtc_w, crtc_h;
 764         uint32_t src_x, src_y, src_w, src_h;
 765         struct drm_rect *src = &state->base.src;
 766         struct drm_rect *dst = &state->base.dst;
 767         const struct drm_rect *clip = &state->clip;
 768         int hscale, vscale;
 769         int max_scale, min_scale;
 770         bool can_scale;
 771         int ret;
 772
 773         *src = drm_plane_state_src(&state->base);
 774         *dst = drm_plane_state_dest(&state->base);
 775
 776         if (!fb) {
 777                 state->base.visible = false;
 778                 return 0;
 779         }
 780
 781         /* Don't modify another pipe's plane */
 782         if (plane->pipe != crtc->pipe) {
 783                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 784                 return -EINVAL;
 785         }
 786
 787         /* FIXME check all gen limits */
 788         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 789                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 790                 return -EINVAL;
 791         }
 792
 793         /* setup can_scale, min_scale, max_scale */
 794         if (INTEL_GEN(dev_priv) >= 9) {
 795                 /* use scaler when colorkey is not required */
 796                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 797                         can_scale = 1;
 798                         min_scale = 1;
 799                         max_scale = skl_max_scale(crtc, crtc_state);
 800                 } else {
 801                         can_scale = 0;
 802                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 803                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 804                 }
 805         } else {
 806                 can_scale = plane->can_scale;
 807                 max_scale = plane->max_downscale << 16;
 808                 min_scale = plane->can_scale ? 1 : (1 << 16);
 809         }
 810
 811         /*
 812          * FIXME the following code does a bunch of fuzzy adjustments to the
 813          * coordinates and sizes. We probably need some way to decide whether
 814          * more strict checking should be done instead.
 815          */
 816         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 817                         state->base.rotation);
 818
 819         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 820         BUG_ON(hscale < 0);
 821
 822         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 823         BUG_ON(vscale < 0);
 824
 825         state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 826
 827         crtc_x = dst->x1;
 828         crtc_y = dst->y1;
 829         crtc_w = drm_rect_width(dst);
 830         crtc_h = drm_rect_height(dst);
 831
 832         if (state->base.visible) {
 833                 /* check again in case clipping clamped the results */
 834                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 835                 if (hscale < 0) {
 836                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 837                         drm_rect_debug_print("src: ", src, true);
 838                         drm_rect_debug_print("dst: ", dst, false);
 839
 840                         return hscale;
 841                 }
 842
 843                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 844                 if (vscale < 0) {
 845                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 846                         drm_rect_debug_print("src: ", src, true);
 847                         drm_rect_debug_print("dst: ", dst, false);
 848
 849                         return vscale;
 850                 }
 851
 852                 /* Make the source viewport size an exact multiple of the scaling factors. */
 853                 drm_rect_adjust_size(src,
 854                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 855                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 856
 857                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 858                                     state->base.rotation);
 859
 860                 /* sanity check to make sure the src viewport wasn't enlarged */
 861                 WARN_ON(src->x1 < (int) state->base.src_x ||
 862                         src->y1 < (int) state->base.src_y ||
 863                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 864                         src->y2 > (int) state->base.src_y + state->base.src_h);
 865
 866                 /*
 867                  * Hardware doesn't handle subpixel coordinates.
 868                  * Adjust to (macro)pixel boundary, but be careful not to
 869                  * increase the source viewport size, because that could
 870                  * push the downscaling factor out of bounds.
 871                  */
 872                 src_x = src->x1 >> 16;
 873                 src_w = drm_rect_width(src) >> 16;
 874                 src_y = src->y1 >> 16;
 875                 src_h = drm_rect_height(src) >> 16;
 876
 877                 if (format_is_yuv(fb->format->format)) {
 878                         src_x &= ~1;
 879                         src_w &= ~1;
 880
 881                         /*
 882                          * Must keep src and dst the
 883                          * same if we can't scale.
 884                          */
 885                         if (!can_scale)
 886                                 crtc_w &= ~1;
 887
 888                         if (crtc_w == 0)
 889                                 state->base.visible = false;
 890                 }
 891         }
 892
 893         /* Check size restrictions when scaling */
 894         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
 895                 unsigned int width_bytes;
 896                 int cpp = fb->format->cpp[0];
 897
 898                 WARN_ON(!can_scale);
 899
 900                 /* FIXME interlacing min height is 6 */
 901
 902                 if (crtc_w < 3 || crtc_h < 3)
 903                         state->base.visible = false;
 904
 905                 if (src_w < 3 || src_h < 3)
 906                         state->base.visible = false;
 907
 908                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 909
 910                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
 911                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 912                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 913                         return -EINVAL;
 914                 }
 915         }
 916
 917         if (state->base.visible) {
 918                 src->x1 = src_x << 16;
 919                 src->x2 = (src_x + src_w) << 16;
 920                 src->y1 = src_y << 16;
 921                 src->y2 = (src_y + src_h) << 16;
 922         }
 923
 924         dst->x1 = crtc_x;
 925         dst->x2 = crtc_x + crtc_w;
 926         dst->y1 = crtc_y;
 927         dst->y2 = crtc_y + crtc_h;
 928
 929         if (INTEL_GEN(dev_priv) >= 9) {
 930                 ret = skl_check_plane_surface(state);
 931                 if (ret)
 932                         return ret;
 933
 934                 state->ctl = skl_plane_ctl(crtc_state, state);
 935         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 936                 ret = i9xx_check_plane_surface(state);
 937                 if (ret)
 938                         return ret;
 939
 940                 state->ctl = vlv_sprite_ctl(crtc_state, state);
 941         } else if (INTEL_GEN(dev_priv) >= 7) {
 942                 ret = i9xx_check_plane_surface(state);
 943                 if (ret)
 944                         return ret;
 945
 946                 state->ctl = ivb_sprite_ctl(crtc_state, state);
 947         } else {
 948                 ret = i9xx_check_plane_surface(state);
 949                 if (ret)
 950                         return ret;
 951
 952                 state->ctl = g4x_sprite_ctl(crtc_state, state);
 953         }
 954
 955         return 0;
 956 }
 957
 958 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 959                               struct drm_file *file_priv)
 960 {
 961         struct drm_i915_private *dev_priv = to_i915(dev);
 962         struct drm_intel_sprite_colorkey *set = data;
 963         struct drm_plane *plane;
 964         struct drm_plane_state *plane_state;
 965         struct drm_atomic_state *state;
 966         struct drm_modeset_acquire_ctx ctx;
 967         int ret = 0;
 968
 969         /* Make sure we don't try to enable both src & dest simultaneously */
 970         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 971                 return -EINVAL;
 972
 973         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 974             set->flags & I915_SET_COLORKEY_DESTINATION)
 975                 return -EINVAL;
 976
 977         plane = drm_plane_find(dev, set->plane_id);
 978         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 979                 return -ENOENT;
 980
 981         drm_modeset_acquire_init(&ctx, 0);
 982
 983         state = drm_atomic_state_alloc(plane->dev);
 984         if (!state) {
 985                 ret = -ENOMEM;
 986                 goto out;
 987         }
 988         state->acquire_ctx = &ctx;
 989
 990         while (1) {
 991                 plane_state = drm_atomic_get_plane_state(state, plane);
 992                 ret = PTR_ERR_OR_ZERO(plane_state);
 993                 if (!ret) {
 994                         to_intel_plane_state(plane_state)->ckey = *set;
 995                         ret = drm_atomic_commit(state);
 996                 }
 997
 998                 if (ret != -EDEADLK)
 999                         break;
1000
1001                 drm_atomic_state_clear(state);
1002                 drm_modeset_backoff(&ctx);
1003         }
1004
1005         drm_atomic_state_put(state);
1006 out:
1007         drm_modeset_drop_locks(&ctx);
1008         drm_modeset_acquire_fini(&ctx);
1009         return ret;
1010 }
1011
1012 static const uint32_t g4x_plane_formats[] = {
1013         DRM_FORMAT_XRGB8888,
1014         DRM_FORMAT_YUYV,
1015         DRM_FORMAT_YVYU,
1016         DRM_FORMAT_UYVY,
1017         DRM_FORMAT_VYUY,
1018 };
1019
1020 static const uint32_t snb_plane_formats[] = {
1021         DRM_FORMAT_XBGR8888,
1022         DRM_FORMAT_XRGB8888,
1023         DRM_FORMAT_YUYV,
1024         DRM_FORMAT_YVYU,
1025         DRM_FORMAT_UYVY,
1026         DRM_FORMAT_VYUY,
1027 };
1028
1029 static const uint32_t vlv_plane_formats[] = {
1030         DRM_FORMAT_RGB565,
1031         DRM_FORMAT_ABGR8888,
1032         DRM_FORMAT_ARGB8888,
1033         DRM_FORMAT_XBGR8888,
1034         DRM_FORMAT_XRGB8888,
1035         DRM_FORMAT_XBGR2101010,
1036         DRM_FORMAT_ABGR2101010,
1037         DRM_FORMAT_YUYV,
1038         DRM_FORMAT_YVYU,
1039         DRM_FORMAT_UYVY,
1040         DRM_FORMAT_VYUY,
1041 };
1042
1043 static uint32_t skl_plane_formats[] = {
1044         DRM_FORMAT_RGB565,
1045         DRM_FORMAT_ABGR8888,
1046         DRM_FORMAT_ARGB8888,
1047         DRM_FORMAT_XBGR8888,
1048         DRM_FORMAT_XRGB8888,
1049         DRM_FORMAT_YUYV,
1050         DRM_FORMAT_YVYU,
1051         DRM_FORMAT_UYVY,
1052         DRM_FORMAT_VYUY,
1053 };
1054
1055 struct intel_plane *
1056 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1057                           enum pipe pipe, int plane)
1058 {
1059         struct intel_plane *intel_plane = NULL;
1060         struct intel_plane_state *state = NULL;
1061         unsigned long possible_crtcs;
1062         const uint32_t *plane_formats;
1063         unsigned int supported_rotations;
1064         int num_plane_formats;
1065         int ret;
1066
1067         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1068         if (!intel_plane) {
1069                 ret = -ENOMEM;
1070                 goto fail;
1071         }
1072
1073         state = intel_create_plane_state(&intel_plane->base);
1074         if (!state) {
1075                 ret = -ENOMEM;
1076                 goto fail;
1077         }
1078         intel_plane->base.state = &state->base;
1079
1080         if (INTEL_GEN(dev_priv) >= 9) {
1081                 intel_plane->can_scale = true;
1082                 state->scaler_id = -1;
1083
1084                 intel_plane->update_plane = skl_update_plane;
1085                 intel_plane->disable_plane = skl_disable_plane;
1086
1087                 plane_formats = skl_plane_formats;
1088                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1089         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1090                 intel_plane->can_scale = false;
1091                 intel_plane->max_downscale = 1;
1092
1093                 intel_plane->update_plane = vlv_update_plane;
1094                 intel_plane->disable_plane = vlv_disable_plane;
1095
1096                 plane_formats = vlv_plane_formats;
1097                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1098         } else if (INTEL_GEN(dev_priv) >= 7) {
1099                 if (IS_IVYBRIDGE(dev_priv)) {
1100                         intel_plane->can_scale = true;
1101                         intel_plane->max_downscale = 2;
1102                 } else {
1103                         intel_plane->can_scale = false;
1104                         intel_plane->max_downscale = 1;
1105                 }
1106
1107                 intel_plane->update_plane = ivb_update_plane;
1108                 intel_plane->disable_plane = ivb_disable_plane;
1109
1110                 plane_formats = snb_plane_formats;
1111                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1112         } else {
1113                 intel_plane->can_scale = true;
1114                 intel_plane->max_downscale = 16;
1115
1116                 intel_plane->update_plane = g4x_update_plane;
1117                 intel_plane->disable_plane = g4x_disable_plane;
1118
1119                 if (IS_GEN6(dev_priv)) {
1120                         plane_formats = snb_plane_formats;
1121                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1122                 } else {
1123                         plane_formats = g4x_plane_formats;
1124                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1125                 }
1126         }
1127
1128         if (INTEL_GEN(dev_priv) >= 9) {
1129                 supported_rotations =
1130                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1131                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1132         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1133                 supported_rotations =
1134                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1135                         DRM_MODE_REFLECT_X;
1136         } else {
1137                 supported_rotations =
1138                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1139         }
1140
1141         intel_plane->pipe = pipe;
1142         intel_plane->plane = plane;
1143         intel_plane->id = PLANE_SPRITE0 + plane;
1144         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1145         intel_plane->check_plane = intel_check_sprite_plane;
1146
1147         possible_crtcs = (1 << pipe);
1148
1149         if (INTEL_GEN(dev_priv) >= 9)
1150                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1151                                                possible_crtcs, &intel_plane_funcs,
1152                                                plane_formats, num_plane_formats,
1153                                                DRM_PLANE_TYPE_OVERLAY,
1154                                                "plane %d%c", plane + 2, pipe_name(pipe));
1155         else
1156                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1157                                                possible_crtcs, &intel_plane_funcs,
1158                                                plane_formats, num_plane_formats,
1159                                                DRM_PLANE_TYPE_OVERLAY,
1160                                                "sprite %c", sprite_name(pipe, plane));
1161         if (ret)
1162                 goto fail;
1163
1164         drm_plane_create_rotation_property(&intel_plane->base,
1165                                            DRM_MODE_ROTATE_0,
1166                                            supported_rotations);
1167
1168         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1169
1170         return intel_plane;
1171
1172 fail:
1173         kfree(state);
1174         kfree(intel_plane);
1175
1176         return ERR_PTR(ret);
1177 }