drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.ac_power = true;
  72                 else
  73                         adev->pm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 /**
  81  * DOC: power_dpm_state
  82  *
  83  * The power_dpm_state file is a legacy interface and is only provided for
  84  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  85  * certain power related parameters.  The file power_dpm_state is used for this.
  86  * It accepts the following arguments:
  87  *
  88  * - battery
  89  *
  90  * - balanced
  91  *
  92  * - performance
  93  *
  94  * battery
  95  *
  96  * On older GPUs, the vbios provided a special power state for battery
  97  * operation.  Selecting battery switched to this state.  This is no
  98  * longer provided on newer GPUs so the option does nothing in that case.
  99  *
 100  * balanced
 101  *
 102  * On older GPUs, the vbios provided a special power state for balanced
 103  * operation.  Selecting balanced switched to this state.  This is no
 104  * longer provided on newer GPUs so the option does nothing in that case.
 105  *
 106  * performance
 107  *
 108  * On older GPUs, the vbios provided a special power state for performance
 109  * operation.  Selecting performance switched to this state.  This is no
 110  * longer provided on newer GPUs so the option does nothing in that case.
 111  *
 112  */
 113
 114 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 115                                     struct device_attribute *attr,
 116                                     char *buf)
 117 {
 118         struct drm_device *ddev = dev_get_drvdata(dev);
 119         struct amdgpu_device *adev = ddev->dev_private;
 120         enum amd_pm_state_type pm;
 121
 122         if (adev->powerplay.pp_funcs->get_current_power_state)
 123                 pm = amdgpu_dpm_get_current_power_state(adev);
 124         else
 125                 pm = adev->pm.dpm.user_state;
 126
 127         return snprintf(buf, PAGE_SIZE, "%s\n",
 128                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 129                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 130 }
 131
 132 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 133                                     struct device_attribute *attr,
 134                                     const char *buf,
 135                                     size_t count)
 136 {
 137         struct drm_device *ddev = dev_get_drvdata(dev);
 138         struct amdgpu_device *adev = ddev->dev_private;
 139         enum amd_pm_state_type  state;
 140
 141         if (strncmp("battery", buf, strlen("battery")) == 0)
 142                 state = POWER_STATE_TYPE_BATTERY;
 143         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 144                 state = POWER_STATE_TYPE_BALANCED;
 145         else if (strncmp("performance", buf, strlen("performance")) == 0)
 146                 state = POWER_STATE_TYPE_PERFORMANCE;
 147         else {
 148                 count = -EINVAL;
 149                 goto fail;
 150         }
 151
 152         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 153                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 154         } else {
 155                 mutex_lock(&adev->pm.mutex);
 156                 adev->pm.dpm.user_state = state;
 157                 mutex_unlock(&adev->pm.mutex);
 158
 159                 /* Can't set dpm state when the card is off */
 160                 if (!(adev->flags & AMD_IS_PX) ||
 161                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 162                         amdgpu_pm_compute_clocks(adev);
 163         }
 164 fail:
 165         return count;
 166 }
 167
 168
 169 /**
 170  * DOC: power_dpm_force_performance_level
 171  *
 172  * The amdgpu driver provides a sysfs API for adjusting certain power
 173  * related parameters.  The file power_dpm_force_performance_level is
 174  * used for this.  It accepts the following arguments:
 175  *
 176  * - auto
 177  *
 178  * - low
 179  *
 180  * - high
 181  *
 182  * - manual
 183  *
 184  * - profile_standard
 185  *
 186  * - profile_min_sclk
 187  *
 188  * - profile_min_mclk
 189  *
 190  * - profile_peak
 191  *
 192  * auto
 193  *
 194  * When auto is selected, the driver will attempt to dynamically select
 195  * the optimal power profile for current conditions in the driver.
 196  *
 197  * low
 198  *
 199  * When low is selected, the clocks are forced to the lowest power state.
 200  *
 201  * high
 202  *
 203  * When high is selected, the clocks are forced to the highest power state.
 204  *
 205  * manual
 206  *
 207  * When manual is selected, the user can manually adjust which power states
 208  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 209  * and pp_dpm_pcie files and adjust the power state transition heuristics
 210  * via the pp_power_profile_mode sysfs file.
 211  *
 212  * profile_standard
 213  * profile_min_sclk
 214  * profile_min_mclk
 215  * profile_peak
 216  *
 217  * When the profiling modes are selected, clock and power gating are
 218  * disabled and the clocks are set for different profiling cases. This
 219  * mode is recommended for profiling specific work loads where you do
 220  * not want clock or power gating for clock fluctuation to interfere
 221  * with your results. profile_standard sets the clocks to a fixed clock
 222  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 223  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 224  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 225  *
 226  */
 227
 228 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 229                                                 struct device_attribute *attr,
 230                                                                 char *buf)
 231 {
 232         struct drm_device *ddev = dev_get_drvdata(dev);
 233         struct amdgpu_device *adev = ddev->dev_private;
 234         enum amd_dpm_forced_level level = 0xff;
 235
 236         if  ((adev->flags & AMD_IS_PX) &&
 237              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 238                 return snprintf(buf, PAGE_SIZE, "off\n");
 239
 240         if (adev->powerplay.pp_funcs->get_performance_level)
 241                 level = amdgpu_dpm_get_performance_level(adev);
 242         else
 243                 level = adev->pm.dpm.forced_level;
 244
 245         return snprintf(buf, PAGE_SIZE, "%s\n",
 246                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 247                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 248                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 249                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 250                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 251                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 252                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 253                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 254                         "unknown");
 255 }
 256
 257 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 258                                                        struct device_attribute *attr,
 259                                                        const char *buf,
 260                                                        size_t count)
 261 {
 262         struct drm_device *ddev = dev_get_drvdata(dev);
 263         struct amdgpu_device *adev = ddev->dev_private;
 264         enum amd_dpm_forced_level level;
 265         enum amd_dpm_forced_level current_level = 0xff;
 266         int ret = 0;
 267
 268         /* Can't force performance level when the card is off */
 269         if  ((adev->flags & AMD_IS_PX) &&
 270              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 271                 return -EINVAL;
 272
 273         if (adev->powerplay.pp_funcs->get_performance_level)
 274                 current_level = amdgpu_dpm_get_performance_level(adev);
 275
 276         if (strncmp("low", buf, strlen("low")) == 0) {
 277                 level = AMD_DPM_FORCED_LEVEL_LOW;
 278         } else if (strncmp("high", buf, strlen("high")) == 0) {
 279                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 280         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 281                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 282         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 283                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 284         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 285                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 286         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 287                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 288         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 289                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 290         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 291                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 292         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 293                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 294         }  else {
 295                 count = -EINVAL;
 296                 goto fail;
 297         }
 298
 299         if (current_level == level)
 300                 return count;
 301
 302         if (adev->powerplay.pp_funcs->force_performance_level) {
 303                 mutex_lock(&adev->pm.mutex);
 304                 if (adev->pm.dpm.thermal_active) {
 305                         count = -EINVAL;
 306                         mutex_unlock(&adev->pm.mutex);
 307                         goto fail;
 308                 }
 309                 ret = amdgpu_dpm_force_performance_level(adev, level);
 310                 if (ret)
 311                         count = -EINVAL;
 312                 else
 313                         adev->pm.dpm.forced_level = level;
 314                 mutex_unlock(&adev->pm.mutex);
 315         }
 316
 317 fail:
 318         return count;
 319 }
 320
 321 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 322                 struct device_attribute *attr,
 323                 char *buf)
 324 {
 325         struct drm_device *ddev = dev_get_drvdata(dev);
 326         struct amdgpu_device *adev = ddev->dev_private;
 327         struct pp_states_info data;
 328         int i, buf_len;
 329
 330         if (adev->powerplay.pp_funcs->get_pp_num_states)
 331                 amdgpu_dpm_get_pp_num_states(adev, &data);
 332
 333         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 334         for (i = 0; i < data.nums; i++)
 335                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 336                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 337                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 338                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 339                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 340
 341         return buf_len;
 342 }
 343
 344 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 345                 struct device_attribute *attr,
 346                 char *buf)
 347 {
 348         struct drm_device *ddev = dev_get_drvdata(dev);
 349         struct amdgpu_device *adev = ddev->dev_private;
 350         struct pp_states_info data;
 351         enum amd_pm_state_type pm = 0;
 352         int i = 0;
 353
 354         if (adev->powerplay.pp_funcs->get_current_power_state
 355                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 356                 pm = amdgpu_dpm_get_current_power_state(adev);
 357                 amdgpu_dpm_get_pp_num_states(adev, &data);
 358
 359                 for (i = 0; i < data.nums; i++) {
 360                         if (pm == data.states[i])
 361                                 break;
 362                 }
 363
 364                 if (i == data.nums)
 365                         i = -EINVAL;
 366         }
 367
 368         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 369 }
 370
 371 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 372                 struct device_attribute *attr,
 373                 char *buf)
 374 {
 375         struct drm_device *ddev = dev_get_drvdata(dev);
 376         struct amdgpu_device *adev = ddev->dev_private;
 377
 378         if (adev->pp_force_state_enabled)
 379                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 380         else
 381                 return snprintf(buf, PAGE_SIZE, "\n");
 382 }
 383
 384 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 385                 struct device_attribute *attr,
 386                 const char *buf,
 387                 size_t count)
 388 {
 389         struct drm_device *ddev = dev_get_drvdata(dev);
 390         struct amdgpu_device *adev = ddev->dev_private;
 391         enum amd_pm_state_type state = 0;
 392         unsigned long idx;
 393         int ret;
 394
 395         if (strlen(buf) == 1)
 396                 adev->pp_force_state_enabled = false;
 397         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 398                         adev->powerplay.pp_funcs->get_pp_num_states) {
 399                 struct pp_states_info data;
 400
 401                 ret = kstrtoul(buf, 0, &idx);
 402                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 403                         count = -EINVAL;
 404                         goto fail;
 405                 }
 406
 407                 amdgpu_dpm_get_pp_num_states(adev, &data);
 408                 state = data.states[idx];
 409                 /* only set user selected power states */
 410                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 411                     state != POWER_STATE_TYPE_DEFAULT) {
 412                         amdgpu_dpm_dispatch_task(adev,
 413                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 414                         adev->pp_force_state_enabled = true;
 415                 }
 416         }
 417 fail:
 418         return count;
 419 }
 420
 421 /**
 422  * DOC: pp_table
 423  *
 424  * The amdgpu driver provides a sysfs API for uploading new powerplay
 425  * tables.  The file pp_table is used for this.  Reading the file
 426  * will dump the current power play table.  Writing to the file
 427  * will attempt to upload a new powerplay table and re-initialize
 428  * powerplay using that new table.
 429  *
 430  */
 431
 432 static ssize_t amdgpu_get_pp_table(struct device *dev,
 433                 struct device_attribute *attr,
 434                 char *buf)
 435 {
 436         struct drm_device *ddev = dev_get_drvdata(dev);
 437         struct amdgpu_device *adev = ddev->dev_private;
 438         char *table = NULL;
 439         int size;
 440
 441         if (adev->powerplay.pp_funcs->get_pp_table)
 442                 size = amdgpu_dpm_get_pp_table(adev, &table);
 443         else
 444                 return 0;
 445
 446         if (size >= PAGE_SIZE)
 447                 size = PAGE_SIZE - 1;
 448
 449         memcpy(buf, table, size);
 450
 451         return size;
 452 }
 453
 454 static ssize_t amdgpu_set_pp_table(struct device *dev,
 455                 struct device_attribute *attr,
 456                 const char *buf,
 457                 size_t count)
 458 {
 459         struct drm_device *ddev = dev_get_drvdata(dev);
 460         struct amdgpu_device *adev = ddev->dev_private;
 461
 462         if (adev->powerplay.pp_funcs->set_pp_table)
 463                 amdgpu_dpm_set_pp_table(adev, buf, count);
 464
 465         return count;
 466 }
 467
 468 /**
 469  * DOC: pp_od_clk_voltage
 470  *
 471  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 472  * in each power level within a power state.  The pp_od_clk_voltage is used for
 473  * this.
 474  *
 475  * Reading the file will display:
 476  *
 477  * - a list of engine clock levels and voltages labeled OD_SCLK
 478  *
 479  * - a list of memory clock levels and voltages labeled OD_MCLK
 480  *
 481  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 482  *
 483  * To manually adjust these settings, first select manual using
 484  * power_dpm_force_performance_level. Enter a new value for each
 485  * level by writing a string that contains "s/m level clock voltage" to
 486  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 487  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 488  * 810 mV.  When you have edited all of the states as needed, write
 489  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 490  * default power levels, write "r" (reset) to the file to reset them.
 491  *
 492  */
 493
 494 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 495                 struct device_attribute *attr,
 496                 const char *buf,
 497                 size_t count)
 498 {
 499         struct drm_device *ddev = dev_get_drvdata(dev);
 500         struct amdgpu_device *adev = ddev->dev_private;
 501         int ret;
 502         uint32_t parameter_size = 0;
 503         long parameter[64];
 504         char buf_cpy[128];
 505         char *tmp_str;
 506         char *sub_str;
 507         const char delimiter[3] = {' ', '\n', '\0'};
 508         uint32_t type;
 509
 510         if (count > 127)
 511                 return -EINVAL;
 512
 513         if (*buf == 's')
 514                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 515         else if (*buf == 'm')
 516                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 517         else if(*buf == 'r')
 518                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 519         else if (*buf == 'c')
 520                 type = PP_OD_COMMIT_DPM_TABLE;
 521         else
 522                 return -EINVAL;
 523
 524         memcpy(buf_cpy, buf, count+1);
 525
 526         tmp_str = buf_cpy;
 527
 528         while (isspace(*++tmp_str));
 529
 530         while (tmp_str[0]) {
 531                 sub_str = strsep(&tmp_str, delimiter);
 532                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 533                 if (ret)
 534                         return -EINVAL;
 535                 parameter_size++;
 536
 537                 while (isspace(*tmp_str))
 538                         tmp_str++;
 539         }
 540
 541         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 542                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 543                                                 parameter, parameter_size);
 544
 545         if (ret)
 546                 return -EINVAL;
 547
 548         if (type == PP_OD_COMMIT_DPM_TABLE) {
 549                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 550                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 551                         return count;
 552                 } else {
 553                         return -EINVAL;
 554                 }
 555         }
 556
 557         return count;
 558 }
 559
 560 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 561                 struct device_attribute *attr,
 562                 char *buf)
 563 {
 564         struct drm_device *ddev = dev_get_drvdata(dev);
 565         struct amdgpu_device *adev = ddev->dev_private;
 566         uint32_t size = 0;
 567
 568         if (adev->powerplay.pp_funcs->print_clock_levels) {
 569                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 570                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 571                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 572                 return size;
 573         } else {
 574                 return snprintf(buf, PAGE_SIZE, "\n");
 575         }
 576
 577 }
 578
 579 /**
 580  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
 581  *
 582  * The amdgpu driver provides a sysfs API for adjusting what power levels
 583  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 584  * and pp_dpm_pcie are used for this.
 585  *
 586  * Reading back the files will show you the available power levels within
 587  * the power state and the clock information for those levels.
 588  *
 589  * To manually adjust these states, first select manual using
 590  * power_dpm_force_performance_level.
 591  * Secondly,Enter a new value for each level by inputing a string that
 592  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 593  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 594  */
 595
 596 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 597                 struct device_attribute *attr,
 598                 char *buf)
 599 {
 600         struct drm_device *ddev = dev_get_drvdata(dev);
 601         struct amdgpu_device *adev = ddev->dev_private;
 602
 603         if (adev->powerplay.pp_funcs->print_clock_levels)
 604                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 605         else
 606                 return snprintf(buf, PAGE_SIZE, "\n");
 607 }
 608
 609 /*
 610  * Worst case: 32 bits individually specified, in octal at 12 characters
 611  * per line (+1 for \n).
 612  */
 613 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 614
 615 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 616 {
 617         int ret;
 618         long level;
 619         char *sub_str = NULL;
 620         char *tmp;
 621         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 622         const char delimiter[3] = {' ', '\n', '\0'};
 623         size_t bytes;
 624
 625         *mask = 0;
 626
 627         bytes = min(count, sizeof(buf_cpy) - 1);
 628         memcpy(buf_cpy, buf, bytes);
 629         buf_cpy[bytes] = '\0';
 630         tmp = buf_cpy;
 631         while (tmp[0]) {
 632                 sub_str = strsep(&tmp, delimiter);
 633                 if (strlen(sub_str)) {
 634                         ret = kstrtol(sub_str, 0, &level);
 635                         if (ret)
 636                                 return -EINVAL;
 637                         *mask |= 1 << level;
 638                 } else
 639                         break;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 646                 struct device_attribute *attr,
 647                 const char *buf,
 648                 size_t count)
 649 {
 650         struct drm_device *ddev = dev_get_drvdata(dev);
 651         struct amdgpu_device *adev = ddev->dev_private;
 652         int ret;
 653         uint32_t mask = 0;
 654
 655         ret = amdgpu_read_mask(buf, count, &mask);
 656         if (ret)
 657                 return ret;
 658
 659         if (adev->powerplay.pp_funcs->force_clock_level)
 660                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 661
 662         return count;
 663 }
 664
 665 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 666                 struct device_attribute *attr,
 667                 char *buf)
 668 {
 669         struct drm_device *ddev = dev_get_drvdata(dev);
 670         struct amdgpu_device *adev = ddev->dev_private;
 671
 672         if (adev->powerplay.pp_funcs->print_clock_levels)
 673                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 674         else
 675                 return snprintf(buf, PAGE_SIZE, "\n");
 676 }
 677
 678 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 679                 struct device_attribute *attr,
 680                 const char *buf,
 681                 size_t count)
 682 {
 683         struct drm_device *ddev = dev_get_drvdata(dev);
 684         struct amdgpu_device *adev = ddev->dev_private;
 685         int ret;
 686         uint32_t mask = 0;
 687
 688         ret = amdgpu_read_mask(buf, count, &mask);
 689         if (ret)
 690                 return ret;
 691
 692         if (adev->powerplay.pp_funcs->force_clock_level)
 693                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 694
 695         return count;
 696 }
 697
 698 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 699                 struct device_attribute *attr,
 700                 char *buf)
 701 {
 702         struct drm_device *ddev = dev_get_drvdata(dev);
 703         struct amdgpu_device *adev = ddev->dev_private;
 704
 705         if (adev->powerplay.pp_funcs->print_clock_levels)
 706                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 707         else
 708                 return snprintf(buf, PAGE_SIZE, "\n");
 709 }
 710
 711 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 712                 struct device_attribute *attr,
 713                 const char *buf,
 714                 size_t count)
 715 {
 716         struct drm_device *ddev = dev_get_drvdata(dev);
 717         struct amdgpu_device *adev = ddev->dev_private;
 718         int ret;
 719         uint32_t mask = 0;
 720
 721         ret = amdgpu_read_mask(buf, count, &mask);
 722         if (ret)
 723                 return ret;
 724
 725         if (adev->powerplay.pp_funcs->force_clock_level)
 726                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 727
 728         return count;
 729 }
 730
 731 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 732                 struct device_attribute *attr,
 733                 char *buf)
 734 {
 735         struct drm_device *ddev = dev_get_drvdata(dev);
 736         struct amdgpu_device *adev = ddev->dev_private;
 737         uint32_t value = 0;
 738
 739         if (adev->powerplay.pp_funcs->get_sclk_od)
 740                 value = amdgpu_dpm_get_sclk_od(adev);
 741
 742         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 743 }
 744
 745 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 746                 struct device_attribute *attr,
 747                 const char *buf,
 748                 size_t count)
 749 {
 750         struct drm_device *ddev = dev_get_drvdata(dev);
 751         struct amdgpu_device *adev = ddev->dev_private;
 752         int ret;
 753         long int value;
 754
 755         ret = kstrtol(buf, 0, &value);
 756
 757         if (ret) {
 758                 count = -EINVAL;
 759                 goto fail;
 760         }
 761         if (adev->powerplay.pp_funcs->set_sclk_od)
 762                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 763
 764         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 765                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 766         } else {
 767                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 768                 amdgpu_pm_compute_clocks(adev);
 769         }
 770
 771 fail:
 772         return count;
 773 }
 774
 775 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 776                 struct device_attribute *attr,
 777                 char *buf)
 778 {
 779         struct drm_device *ddev = dev_get_drvdata(dev);
 780         struct amdgpu_device *adev = ddev->dev_private;
 781         uint32_t value = 0;
 782
 783         if (adev->powerplay.pp_funcs->get_mclk_od)
 784                 value = amdgpu_dpm_get_mclk_od(adev);
 785
 786         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 787 }
 788
 789 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 790                 struct device_attribute *attr,
 791                 const char *buf,
 792                 size_t count)
 793 {
 794         struct drm_device *ddev = dev_get_drvdata(dev);
 795         struct amdgpu_device *adev = ddev->dev_private;
 796         int ret;
 797         long int value;
 798
 799         ret = kstrtol(buf, 0, &value);
 800
 801         if (ret) {
 802                 count = -EINVAL;
 803                 goto fail;
 804         }
 805         if (adev->powerplay.pp_funcs->set_mclk_od)
 806                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 807
 808         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 809                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 810         } else {
 811                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 812                 amdgpu_pm_compute_clocks(adev);
 813         }
 814
 815 fail:
 816         return count;
 817 }
 818
 819 /**
 820  * DOC: pp_power_profile_mode
 821  *
 822  * The amdgpu driver provides a sysfs API for adjusting the heuristics
 823  * related to switching between power levels in a power state.  The file
 824  * pp_power_profile_mode is used for this.
 825  *
 826  * Reading this file outputs a list of all of the predefined power profiles
 827  * and the relevant heuristics settings for that profile.
 828  *
 829  * To select a profile or create a custom profile, first select manual using
 830  * power_dpm_force_performance_level.  Writing the number of a predefined
 831  * profile to pp_power_profile_mode will enable those heuristics.  To
 832  * create a custom set of heuristics, write a string of numbers to the file
 833  * starting with the number of the custom profile along with a setting
 834  * for each heuristic parameter.  Due to differences across asic families
 835  * the heuristic parameters vary from family to family.
 836  *
 837  */
 838
 839 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 840                 struct device_attribute *attr,
 841                 char *buf)
 842 {
 843         struct drm_device *ddev = dev_get_drvdata(dev);
 844         struct amdgpu_device *adev = ddev->dev_private;
 845
 846         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 847                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 848
 849         return snprintf(buf, PAGE_SIZE, "\n");
 850 }
 851
 852
 853 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 854                 struct device_attribute *attr,
 855                 const char *buf,
 856                 size_t count)
 857 {
 858         int ret = 0xff;
 859         struct drm_device *ddev = dev_get_drvdata(dev);
 860         struct amdgpu_device *adev = ddev->dev_private;
 861         uint32_t parameter_size = 0;
 862         long parameter[64];
 863         char *sub_str, buf_cpy[128];
 864         char *tmp_str;
 865         uint32_t i = 0;
 866         char tmp[2];
 867         long int profile_mode = 0;
 868         const char delimiter[3] = {' ', '\n', '\0'};
 869
 870         tmp[0] = *(buf);
 871         tmp[1] = '\0';
 872         ret = kstrtol(tmp, 0, &profile_mode);
 873         if (ret)
 874                 goto fail;
 875
 876         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 877                 if (count < 2 || count > 127)
 878                         return -EINVAL;
 879                 while (isspace(*++buf))
 880                         i++;
 881                 memcpy(buf_cpy, buf, count-i);
 882                 tmp_str = buf_cpy;
 883                 while (tmp_str[0]) {
 884                         sub_str = strsep(&tmp_str, delimiter);
 885                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 886                         if (ret) {
 887                                 count = -EINVAL;
 888                                 goto fail;
 889                         }
 890                         parameter_size++;
 891                         while (isspace(*tmp_str))
 892                                 tmp_str++;
 893                 }
 894         }
 895         parameter[parameter_size] = profile_mode;
 896         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 897                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 898
 899         if (!ret)
 900                 return count;
 901 fail:
 902         return -EINVAL;
 903 }
 904
 905 /**
 906  * DOC: busy_percent
 907  *
 908  * The amdgpu driver provides a sysfs API for reading how busy the GPU
 909  * is as a percentage.  The file gpu_busy_percent is used for this.
 910  * The SMU firmware computes a percentage of load based on the
 911  * aggregate activity level in the IP cores.
 912  */
 913 static ssize_t amdgpu_get_busy_percent(struct device *dev,
 914                 struct device_attribute *attr,
 915                 char *buf)
 916 {
 917         struct drm_device *ddev = dev_get_drvdata(dev);
 918         struct amdgpu_device *adev = ddev->dev_private;
 919         int r, value, size = sizeof(value);
 920
 921         /* sanity check PP is enabled */
 922         if (!(adev->powerplay.pp_funcs &&
 923               adev->powerplay.pp_funcs->read_sensor))
 924                 return -EINVAL;
 925
 926         /* read the IP busy sensor */
 927         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
 928                                    (void *)&value, &size);
 929         if (r)
 930                 return r;
 931
 932         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 933 }
 934
 935 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 936 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 937                    amdgpu_get_dpm_forced_performance_level,
 938                    amdgpu_set_dpm_forced_performance_level);
 939 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 940 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 941 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 942                 amdgpu_get_pp_force_state,
 943                 amdgpu_set_pp_force_state);
 944 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 945                 amdgpu_get_pp_table,
 946                 amdgpu_set_pp_table);
 947 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 948                 amdgpu_get_pp_dpm_sclk,
 949                 amdgpu_set_pp_dpm_sclk);
 950 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 951                 amdgpu_get_pp_dpm_mclk,
 952                 amdgpu_set_pp_dpm_mclk);
 953 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 954                 amdgpu_get_pp_dpm_pcie,
 955                 amdgpu_set_pp_dpm_pcie);
 956 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 957                 amdgpu_get_pp_sclk_od,
 958                 amdgpu_set_pp_sclk_od);
 959 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 960                 amdgpu_get_pp_mclk_od,
 961                 amdgpu_set_pp_mclk_od);
 962 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 963                 amdgpu_get_pp_power_profile_mode,
 964                 amdgpu_set_pp_power_profile_mode);
 965 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 966                 amdgpu_get_pp_od_clk_voltage,
 967                 amdgpu_set_pp_od_clk_voltage);
 968 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 969                 amdgpu_get_busy_percent, NULL);
 970
 971 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 972                                       struct device_attribute *attr,
 973                                       char *buf)
 974 {
 975         struct amdgpu_device *adev = dev_get_drvdata(dev);
 976         struct drm_device *ddev = adev->ddev;
 977         int r, temp, size = sizeof(temp);
 978
 979         /* Can't get temperature when the card is off */
 980         if  ((adev->flags & AMD_IS_PX) &&
 981              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 982                 return -EINVAL;
 983
 984         /* sanity check PP is enabled */
 985         if (!(adev->powerplay.pp_funcs &&
 986               adev->powerplay.pp_funcs->read_sensor))
 987                 return -EINVAL;
 988
 989         /* get the temperature */
 990         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 991                                    (void *)&temp, &size);
 992         if (r)
 993                 return r;
 994
 995         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 996 }
 997
 998 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 999                                              struct device_attribute *attr,
1000                                              char *buf)
1001 {
1002         struct amdgpu_device *adev = dev_get_drvdata(dev);
1003         int hyst = to_sensor_dev_attr(attr)->index;
1004         int temp;
1005
1006         if (hyst)
1007                 temp = adev->pm.dpm.thermal.min_temp;
1008         else
1009                 temp = adev->pm.dpm.thermal.max_temp;
1010
1011         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1012 }
1013
1014 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1015                                             struct device_attribute *attr,
1016                                             char *buf)
1017 {
1018         struct amdgpu_device *adev = dev_get_drvdata(dev);
1019         u32 pwm_mode = 0;
1020
1021         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1022                 return -EINVAL;
1023
1024         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1025
1026         return sprintf(buf, "%i\n", pwm_mode);
1027 }
1028
1029 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1030                                             struct device_attribute *attr,
1031                                             const char *buf,
1032                                             size_t count)
1033 {
1034         struct amdgpu_device *adev = dev_get_drvdata(dev);
1035         int err;
1036         int value;
1037
1038         /* Can't adjust fan when the card is off */
1039         if  ((adev->flags & AMD_IS_PX) &&
1040              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1041                 return -EINVAL;
1042
1043         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1044                 return -EINVAL;
1045
1046         err = kstrtoint(buf, 10, &value);
1047         if (err)
1048                 return err;
1049
1050         amdgpu_dpm_set_fan_control_mode(adev, value);
1051
1052         return count;
1053 }
1054
1055 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1056                                          struct device_attribute *attr,
1057                                          char *buf)
1058 {
1059         return sprintf(buf, "%i\n", 0);
1060 }
1061
1062 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1063                                          struct device_attribute *attr,
1064                                          char *buf)
1065 {
1066         return sprintf(buf, "%i\n", 255);
1067 }
1068
1069 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1070                                      struct device_attribute *attr,
1071                                      const char *buf, size_t count)
1072 {
1073         struct amdgpu_device *adev = dev_get_drvdata(dev);
1074         int err;
1075         u32 value;
1076
1077         /* Can't adjust fan when the card is off */
1078         if  ((adev->flags & AMD_IS_PX) &&
1079              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1080                 return -EINVAL;
1081
1082         err = kstrtou32(buf, 10, &value);
1083         if (err)
1084                 return err;
1085
1086         value = (value * 100) / 255;
1087
1088         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1089                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1090                 if (err)
1091                         return err;
1092         }
1093
1094         return count;
1095 }
1096
1097 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1098                                      struct device_attribute *attr,
1099                                      char *buf)
1100 {
1101         struct amdgpu_device *adev = dev_get_drvdata(dev);
1102         int err;
1103         u32 speed = 0;
1104
1105         /* Can't adjust fan when the card is off */
1106         if  ((adev->flags & AMD_IS_PX) &&
1107              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1108                 return -EINVAL;
1109
1110         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1111                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1112                 if (err)
1113                         return err;
1114         }
1115
1116         speed = (speed * 255) / 100;
1117
1118         return sprintf(buf, "%i\n", speed);
1119 }
1120
1121 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1122                                            struct device_attribute *attr,
1123                                            char *buf)
1124 {
1125         struct amdgpu_device *adev = dev_get_drvdata(dev);
1126         int err;
1127         u32 speed = 0;
1128
1129         /* Can't adjust fan when the card is off */
1130         if  ((adev->flags & AMD_IS_PX) &&
1131              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1132                 return -EINVAL;
1133
1134         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1135                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1136                 if (err)
1137                         return err;
1138         }
1139
1140         return sprintf(buf, "%i\n", speed);
1141 }
1142
1143 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1144                                         struct device_attribute *attr,
1145                                         char *buf)
1146 {
1147         struct amdgpu_device *adev = dev_get_drvdata(dev);
1148         struct drm_device *ddev = adev->ddev;
1149         u32 vddgfx;
1150         int r, size = sizeof(vddgfx);
1151
1152         /* Can't get voltage when the card is off */
1153         if  ((adev->flags & AMD_IS_PX) &&
1154              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1155                 return -EINVAL;
1156
1157         /* sanity check PP is enabled */
1158         if (!(adev->powerplay.pp_funcs &&
1159               adev->powerplay.pp_funcs->read_sensor))
1160               return -EINVAL;
1161
1162         /* get the voltage */
1163         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1164                                    (void *)&vddgfx, &size);
1165         if (r)
1166                 return r;
1167
1168         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1169 }
1170
1171 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1172                                               struct device_attribute *attr,
1173                                               char *buf)
1174 {
1175         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1176 }
1177
1178 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1179                                        struct device_attribute *attr,
1180                                        char *buf)
1181 {
1182         struct amdgpu_device *adev = dev_get_drvdata(dev);
1183         struct drm_device *ddev = adev->ddev;
1184         u32 vddnb;
1185         int r, size = sizeof(vddnb);
1186
1187         /* only APUs have vddnb */
1188         if  (adev->flags & AMD_IS_APU)
1189                 return -EINVAL;
1190
1191         /* Can't get voltage when the card is off */
1192         if  ((adev->flags & AMD_IS_PX) &&
1193              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1194                 return -EINVAL;
1195
1196         /* sanity check PP is enabled */
1197         if (!(adev->powerplay.pp_funcs &&
1198               adev->powerplay.pp_funcs->read_sensor))
1199               return -EINVAL;
1200
1201         /* get the voltage */
1202         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1203                                    (void *)&vddnb, &size);
1204         if (r)
1205                 return r;
1206
1207         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1208 }
1209
1210 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1211                                               struct device_attribute *attr,
1212                                               char *buf)
1213 {
1214         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1215 }
1216
1217 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1218                                            struct device_attribute *attr,
1219                                            char *buf)
1220 {
1221         struct amdgpu_device *adev = dev_get_drvdata(dev);
1222         struct drm_device *ddev = adev->ddev;
1223         u32 query = 0;
1224         int r, size = sizeof(u32);
1225         unsigned uw;
1226
1227         /* Can't get power when the card is off */
1228         if  ((adev->flags & AMD_IS_PX) &&
1229              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1230                 return -EINVAL;
1231
1232         /* sanity check PP is enabled */
1233         if (!(adev->powerplay.pp_funcs &&
1234               adev->powerplay.pp_funcs->read_sensor))
1235               return -EINVAL;
1236
1237         /* get the voltage */
1238         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1239                                    (void *)&query, &size);
1240         if (r)
1241                 return r;
1242
1243         /* convert to microwatts */
1244         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1245
1246         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1247 }
1248
1249 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1250                                          struct device_attribute *attr,
1251                                          char *buf)
1252 {
1253         return sprintf(buf, "%i\n", 0);
1254 }
1255
1256 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1257                                          struct device_attribute *attr,
1258                                          char *buf)
1259 {
1260         struct amdgpu_device *adev = dev_get_drvdata(dev);
1261         uint32_t limit = 0;
1262
1263         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1264                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1265                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1266         } else {
1267                 return snprintf(buf, PAGE_SIZE, "\n");
1268         }
1269 }
1270
1271 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1272                                          struct device_attribute *attr,
1273                                          char *buf)
1274 {
1275         struct amdgpu_device *adev = dev_get_drvdata(dev);
1276         uint32_t limit = 0;
1277
1278         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1279                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1280                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1281         } else {
1282                 return snprintf(buf, PAGE_SIZE, "\n");
1283         }
1284 }
1285
1286
1287 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1288                 struct device_attribute *attr,
1289                 const char *buf,
1290                 size_t count)
1291 {
1292         struct amdgpu_device *adev = dev_get_drvdata(dev);
1293         int err;
1294         u32 value;
1295
1296         err = kstrtou32(buf, 10, &value);
1297         if (err)
1298                 return err;
1299
1300         value = value / 1000000; /* convert to Watt */
1301         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1302                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1303                 if (err)
1304                         return err;
1305         } else {
1306                 return -EINVAL;
1307         }
1308
1309         return count;
1310 }
1311
1312
1313 /**
1314  * DOC: hwmon
1315  *
1316  * The amdgpu driver exposes the following sensor interfaces:
1317  *
1318  * - GPU temperature (via the on-die sensor)
1319  *
1320  * - GPU voltage
1321  *
1322  * - Northbridge voltage (APUs only)
1323  *
1324  * - GPU power
1325  *
1326  * - GPU fan
1327  *
1328  * hwmon interfaces for GPU temperature:
1329  *
1330  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1331  *
1332  * - temp1_crit: temperature critical max value in millidegrees Celsius
1333  *
1334  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1335  *
1336  * hwmon interfaces for GPU voltage:
1337  *
1338  * - in0_input: the voltage on the GPU in millivolts
1339  *
1340  * - in1_input: the voltage on the Northbridge in millivolts
1341  *
1342  * hwmon interfaces for GPU power:
1343  *
1344  * - power1_average: average power used by the GPU in microWatts
1345  *
1346  * - power1_cap_min: minimum cap supported in microWatts
1347  *
1348  * - power1_cap_max: maximum cap supported in microWatts
1349  *
1350  * - power1_cap: selected power cap in microWatts
1351  *
1352  * hwmon interfaces for GPU fan:
1353  *
1354  * - pwm1: pulse width modulation fan level (0-255)
1355  *
1356  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1357  *
1358  * - pwm1_min: pulse width modulation fan control minimum level (0)
1359  *
1360  * - pwm1_max: pulse width modulation fan control maximum level (255)
1361  *
1362  * - fan1_input: fan speed in RPM
1363  *
1364  * You can use hwmon tools like sensors to view this information on your system.
1365  *
1366  */
1367
1368 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1369 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1370 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1371 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1372 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1373 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1374 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1375 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1376 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1377 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1378 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1379 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1380 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1381 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1382 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1383 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1384
1385 static struct attribute *hwmon_attributes[] = {
1386         &sensor_dev_attr_temp1_input.dev_attr.attr,
1387         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1388         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1389         &sensor_dev_attr_pwm1.dev_attr.attr,
1390         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1391         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1392         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1393         &sensor_dev_attr_fan1_input.dev_attr.attr,
1394         &sensor_dev_attr_in0_input.dev_attr.attr,
1395         &sensor_dev_attr_in0_label.dev_attr.attr,
1396         &sensor_dev_attr_in1_input.dev_attr.attr,
1397         &sensor_dev_attr_in1_label.dev_attr.attr,
1398         &sensor_dev_attr_power1_average.dev_attr.attr,
1399         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1400         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1401         &sensor_dev_attr_power1_cap.dev_attr.attr,
1402         NULL
1403 };
1404
1405 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1406                                         struct attribute *attr, int index)
1407 {
1408         struct device *dev = kobj_to_dev(kobj);
1409         struct amdgpu_device *adev = dev_get_drvdata(dev);
1410         umode_t effective_mode = attr->mode;
1411
1412
1413         /* Skip fan attributes if fan is not present */
1414         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1415             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1416             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1417             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1418             attr == &sensor_dev_attr_fan1_input.dev_attr.attr))
1419                 return 0;
1420
1421         /* Skip limit attributes if DPM is not enabled */
1422         if (!adev->pm.dpm_enabled &&
1423             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1424              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1425              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1426              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1427              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1428              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1429                 return 0;
1430
1431         /* mask fan attributes if we have no bindings for this asic to expose */
1432         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1433              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1434             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1435              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1436                 effective_mode &= ~S_IRUGO;
1437
1438         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1439              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1440             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1441              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1442                 effective_mode &= ~S_IWUSR;
1443
1444         if ((adev->flags & AMD_IS_APU) &&
1445             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1446              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1447              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1448                 return 0;
1449
1450         /* hide max/min values if we can't both query and manage the fan */
1451         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1452              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1453             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1454              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1455                 return 0;
1456
1457         /* only APUs have vddnb */
1458         if (!(adev->flags & AMD_IS_APU) &&
1459             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1460              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1461                 return 0;
1462
1463         return effective_mode;
1464 }
1465
1466 static const struct attribute_group hwmon_attrgroup = {
1467         .attrs = hwmon_attributes,
1468         .is_visible = hwmon_attributes_visible,
1469 };
1470
1471 static const struct attribute_group *hwmon_groups[] = {
1472         &hwmon_attrgroup,
1473         NULL
1474 };
1475
1476 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1477 {
1478         struct amdgpu_device *adev =
1479                 container_of(work, struct amdgpu_device,
1480                              pm.dpm.thermal.work);
1481         /* switch to the thermal state */
1482         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1483         int temp, size = sizeof(temp);
1484
1485         if (!adev->pm.dpm_enabled)
1486                 return;
1487
1488         if (adev->powerplay.pp_funcs &&
1489             adev->powerplay.pp_funcs->read_sensor &&
1490             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1491                                     (void *)&temp, &size)) {
1492                 if (temp < adev->pm.dpm.thermal.min_temp)
1493                         /* switch back the user state */
1494                         dpm_state = adev->pm.dpm.user_state;
1495         } else {
1496                 if (adev->pm.dpm.thermal.high_to_low)
1497                         /* switch back the user state */
1498                         dpm_state = adev->pm.dpm.user_state;
1499         }
1500         mutex_lock(&adev->pm.mutex);
1501         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1502                 adev->pm.dpm.thermal_active = true;
1503         else
1504                 adev->pm.dpm.thermal_active = false;
1505         adev->pm.dpm.state = dpm_state;
1506         mutex_unlock(&adev->pm.mutex);
1507
1508         amdgpu_pm_compute_clocks(adev);
1509 }
1510
1511 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1512                                                      enum amd_pm_state_type dpm_state)
1513 {
1514         int i;
1515         struct amdgpu_ps *ps;
1516         u32 ui_class;
1517         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1518                 true : false;
1519
1520         /* check if the vblank period is too short to adjust the mclk */
1521         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1522                 if (amdgpu_dpm_vblank_too_short(adev))
1523                         single_display = false;
1524         }
1525
1526         /* certain older asics have a separare 3D performance state,
1527          * so try that first if the user selected performance
1528          */
1529         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1530                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1531         /* balanced states don't exist at the moment */
1532         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1533                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1534
1535 restart_search:
1536         /* Pick the best power state based on current conditions */
1537         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1538                 ps = &adev->pm.dpm.ps[i];
1539                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1540                 switch (dpm_state) {
1541                 /* user states */
1542                 case POWER_STATE_TYPE_BATTERY:
1543                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1544                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1545                                         if (single_display)
1546                                                 return ps;
1547                                 } else
1548                                         return ps;
1549                         }
1550                         break;
1551                 case POWER_STATE_TYPE_BALANCED:
1552                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1553                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1554                                         if (single_display)
1555                                                 return ps;
1556                                 } else
1557                                         return ps;
1558                         }
1559                         break;
1560                 case POWER_STATE_TYPE_PERFORMANCE:
1561                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1562                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1563                                         if (single_display)
1564                                                 return ps;
1565                                 } else
1566                                         return ps;
1567                         }
1568                         break;
1569                 /* internal states */
1570                 case POWER_STATE_TYPE_INTERNAL_UVD:
1571                         if (adev->pm.dpm.uvd_ps)
1572                                 return adev->pm.dpm.uvd_ps;
1573                         else
1574                                 break;
1575                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1576                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1577                                 return ps;
1578                         break;
1579                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1580                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1581                                 return ps;
1582                         break;
1583                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1584                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1585                                 return ps;
1586                         break;
1587                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1588                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1589                                 return ps;
1590                         break;
1591                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1592                         return adev->pm.dpm.boot_ps;
1593                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1594                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1595                                 return ps;
1596                         break;
1597                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1598                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1599                                 return ps;
1600                         break;
1601                 case POWER_STATE_TYPE_INTERNAL_ULV:
1602                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1603                                 return ps;
1604                         break;
1605                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1606                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1607                                 return ps;
1608                         break;
1609                 default:
1610                         break;
1611                 }
1612         }
1613         /* use a fallback state if we didn't match */
1614         switch (dpm_state) {
1615         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1616                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1617                 goto restart_search;
1618         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1619         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1620         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1621                 if (adev->pm.dpm.uvd_ps) {
1622                         return adev->pm.dpm.uvd_ps;
1623                 } else {
1624                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1625                         goto restart_search;
1626                 }
1627         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1628                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1629                 goto restart_search;
1630         case POWER_STATE_TYPE_INTERNAL_ACPI:
1631                 dpm_state = POWER_STATE_TYPE_BATTERY;
1632                 goto restart_search;
1633         case POWER_STATE_TYPE_BATTERY:
1634         case POWER_STATE_TYPE_BALANCED:
1635         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1636                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1637                 goto restart_search;
1638         default:
1639                 break;
1640         }
1641
1642         return NULL;
1643 }
1644
1645 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1646 {
1647         struct amdgpu_ps *ps;
1648         enum amd_pm_state_type dpm_state;
1649         int ret;
1650         bool equal = false;
1651
1652         /* if dpm init failed */
1653         if (!adev->pm.dpm_enabled)
1654                 return;
1655
1656         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1657                 /* add other state override checks here */
1658                 if ((!adev->pm.dpm.thermal_active) &&
1659                     (!adev->pm.dpm.uvd_active))
1660                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1661         }
1662         dpm_state = adev->pm.dpm.state;
1663
1664         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1665         if (ps)
1666                 adev->pm.dpm.requested_ps = ps;
1667         else
1668                 return;
1669
1670         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1671                 printk("switching from power state:\n");
1672                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1673                 printk("switching to power state:\n");
1674                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1675         }
1676
1677         /* update whether vce is active */
1678         ps->vce_active = adev->pm.dpm.vce_active;
1679         if (adev->powerplay.pp_funcs->display_configuration_changed)
1680                 amdgpu_dpm_display_configuration_changed(adev);
1681
1682         ret = amdgpu_dpm_pre_set_power_state(adev);
1683         if (ret)
1684                 return;
1685
1686         if (adev->powerplay.pp_funcs->check_state_equal) {
1687                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1688                         equal = false;
1689         }
1690
1691         if (equal)
1692                 return;
1693
1694         amdgpu_dpm_set_power_state(adev);
1695         amdgpu_dpm_post_set_power_state(adev);
1696
1697         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1698         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1699
1700         if (adev->powerplay.pp_funcs->force_performance_level) {
1701                 if (adev->pm.dpm.thermal_active) {
1702                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1703                         /* force low perf level for thermal */
1704                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1705                         /* save the user's level */
1706                         adev->pm.dpm.forced_level = level;
1707                 } else {
1708                         /* otherwise, user selected level */
1709                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1710                 }
1711         }
1712 }
1713
1714 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1715 {
1716         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
1717                 /* enable/disable UVD */
1718                 mutex_lock(&adev->pm.mutex);
1719                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
1720                 mutex_unlock(&adev->pm.mutex);
1721         } else {
1722                 if (enable) {
1723                         mutex_lock(&adev->pm.mutex);
1724                         adev->pm.dpm.uvd_active = true;
1725                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1726                         mutex_unlock(&adev->pm.mutex);
1727                 } else {
1728                         mutex_lock(&adev->pm.mutex);
1729                         adev->pm.dpm.uvd_active = false;
1730                         mutex_unlock(&adev->pm.mutex);
1731                 }
1732                 amdgpu_pm_compute_clocks(adev);
1733         }
1734 }
1735
1736 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1737 {
1738         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
1739                 /* enable/disable VCE */
1740                 mutex_lock(&adev->pm.mutex);
1741                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
1742                 mutex_unlock(&adev->pm.mutex);
1743         } else {
1744                 if (enable) {
1745                         mutex_lock(&adev->pm.mutex);
1746                         adev->pm.dpm.vce_active = true;
1747                         /* XXX select vce level based on ring/task */
1748                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1749                         mutex_unlock(&adev->pm.mutex);
1750                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1751                                                                AMD_CG_STATE_UNGATE);
1752                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1753                                                                AMD_PG_STATE_UNGATE);
1754                         amdgpu_pm_compute_clocks(adev);
1755                 } else {
1756                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1757                                                                AMD_PG_STATE_GATE);
1758                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1759                                                                AMD_CG_STATE_GATE);
1760                         mutex_lock(&adev->pm.mutex);
1761                         adev->pm.dpm.vce_active = false;
1762                         mutex_unlock(&adev->pm.mutex);
1763                         amdgpu_pm_compute_clocks(adev);
1764                 }
1765
1766         }
1767 }
1768
1769 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1770 {
1771         int i;
1772
1773         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1774                 return;
1775
1776         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1777                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1778
1779 }
1780
1781 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1782 {
1783         int ret;
1784
1785         if (adev->pm.sysfs_initialized)
1786                 return 0;
1787
1788         if (adev->pm.dpm_enabled == 0)
1789                 return 0;
1790
1791         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1792                                                                    DRIVER_NAME, adev,
1793                                                                    hwmon_groups);
1794         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1795                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1796                 dev_err(adev->dev,
1797                         "Unable to register hwmon device: %d\n", ret);
1798                 return ret;
1799         }
1800
1801         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1802         if (ret) {
1803                 DRM_ERROR("failed to create device file for dpm state\n");
1804                 return ret;
1805         }
1806         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1807         if (ret) {
1808                 DRM_ERROR("failed to create device file for dpm state\n");
1809                 return ret;
1810         }
1811
1812
1813         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1814         if (ret) {
1815                 DRM_ERROR("failed to create device file pp_num_states\n");
1816                 return ret;
1817         }
1818         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1819         if (ret) {
1820                 DRM_ERROR("failed to create device file pp_cur_state\n");
1821                 return ret;
1822         }
1823         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1824         if (ret) {
1825                 DRM_ERROR("failed to create device file pp_force_state\n");
1826                 return ret;
1827         }
1828         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1829         if (ret) {
1830                 DRM_ERROR("failed to create device file pp_table\n");
1831                 return ret;
1832         }
1833
1834         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1835         if (ret) {
1836                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1837                 return ret;
1838         }
1839         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1840         if (ret) {
1841                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1842                 return ret;
1843         }
1844         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1845         if (ret) {
1846                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1847                 return ret;
1848         }
1849         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1850         if (ret) {
1851                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1852                 return ret;
1853         }
1854         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1855         if (ret) {
1856                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1857                 return ret;
1858         }
1859         ret = device_create_file(adev->dev,
1860                         &dev_attr_pp_power_profile_mode);
1861         if (ret) {
1862                 DRM_ERROR("failed to create device file "
1863                                 "pp_power_profile_mode\n");
1864                 return ret;
1865         }
1866         ret = device_create_file(adev->dev,
1867                         &dev_attr_pp_od_clk_voltage);
1868         if (ret) {
1869                 DRM_ERROR("failed to create device file "
1870                                 "pp_od_clk_voltage\n");
1871                 return ret;
1872         }
1873         ret = device_create_file(adev->dev,
1874                         &dev_attr_gpu_busy_percent);
1875         if (ret) {
1876                 DRM_ERROR("failed to create device file "
1877                                 "gpu_busy_level\n");
1878                 return ret;
1879         }
1880         ret = amdgpu_debugfs_pm_init(adev);
1881         if (ret) {
1882                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1883                 return ret;
1884         }
1885
1886         adev->pm.sysfs_initialized = true;
1887
1888         return 0;
1889 }
1890
1891 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1892 {
1893         if (adev->pm.dpm_enabled == 0)
1894                 return;
1895
1896         if (adev->pm.int_hwmon_dev)
1897                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1898         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1899         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1900
1901         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1902         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1903         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1904         device_remove_file(adev->dev, &dev_attr_pp_table);
1905
1906         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1907         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1908         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1909         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1910         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1911         device_remove_file(adev->dev,
1912                         &dev_attr_pp_power_profile_mode);
1913         device_remove_file(adev->dev,
1914                         &dev_attr_pp_od_clk_voltage);
1915         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
1916 }
1917
1918 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1919 {
1920         int i = 0;
1921
1922         if (!adev->pm.dpm_enabled)
1923                 return;
1924
1925         if (adev->mode_info.num_crtc)
1926                 amdgpu_display_bandwidth_update(adev);
1927
1928         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1929                 struct amdgpu_ring *ring = adev->rings[i];
1930                 if (ring && ring->ready)
1931                         amdgpu_fence_wait_empty(ring);
1932         }
1933
1934         mutex_lock(&adev->pm.mutex);
1935         /* update battery/ac status */
1936         if (power_supply_is_system_supplied() > 0)
1937                 adev->pm.ac_power = true;
1938         else
1939                 adev->pm.ac_power = false;
1940         mutex_unlock(&adev->pm.mutex);
1941
1942         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1943                 if (!amdgpu_device_has_dc_support(adev)) {
1944                         mutex_lock(&adev->pm.mutex);
1945                         amdgpu_dpm_get_active_displays(adev);
1946                         adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
1947                         adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1948                         adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1949                         /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1950                         if (adev->pm.pm_display_cfg.vrefresh > 120)
1951                                 adev->pm.pm_display_cfg.min_vblank_time = 0;
1952                         if (adev->powerplay.pp_funcs->display_configuration_change)
1953                                 adev->powerplay.pp_funcs->display_configuration_change(
1954                                                                 adev->powerplay.pp_handle,
1955                                                                 &adev->pm.pm_display_cfg);
1956                         mutex_unlock(&adev->pm.mutex);
1957                 }
1958                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1959         } else {
1960                 mutex_lock(&adev->pm.mutex);
1961                 amdgpu_dpm_get_active_displays(adev);
1962                 amdgpu_dpm_change_power_state_locked(adev);
1963                 mutex_unlock(&adev->pm.mutex);
1964         }
1965 }
1966
1967 /*
1968  * Debugfs info
1969  */
1970 #if defined(CONFIG_DEBUG_FS)
1971
1972 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1973 {
1974         uint32_t value;
1975         uint32_t query = 0;
1976         int size;
1977
1978         /* sanity check PP is enabled */
1979         if (!(adev->powerplay.pp_funcs &&
1980               adev->powerplay.pp_funcs->read_sensor))
1981               return -EINVAL;
1982
1983         /* GPU Clocks */
1984         size = sizeof(value);
1985         seq_printf(m, "GFX Clocks and Power:\n");
1986         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1987                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1988         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1989                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1990         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1991                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1992         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1993                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1994         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1995                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1996         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1997                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1998         size = sizeof(uint32_t);
1999         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2000                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2001         size = sizeof(value);
2002         seq_printf(m, "\n");
2003
2004         /* GPU Temp */
2005         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2006                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2007
2008         /* GPU Load */
2009         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2010                 seq_printf(m, "GPU Load: %u %%\n", value);
2011         seq_printf(m, "\n");
2012
2013         /* UVD clocks */
2014         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2015                 if (!value) {
2016                         seq_printf(m, "UVD: Disabled\n");
2017                 } else {
2018                         seq_printf(m, "UVD: Enabled\n");
2019                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2020                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2021                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2022                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2023                 }
2024         }
2025         seq_printf(m, "\n");
2026
2027         /* VCE clocks */
2028         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2029                 if (!value) {
2030                         seq_printf(m, "VCE: Disabled\n");
2031                 } else {
2032                         seq_printf(m, "VCE: Enabled\n");
2033                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2034                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2035                 }
2036         }
2037
2038         return 0;
2039 }
2040
2041 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2042 {
2043         int i;
2044
2045         for (i = 0; clocks[i].flag; i++)
2046                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2047                            (flags & clocks[i].flag) ? "On" : "Off");
2048 }
2049
2050 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2051 {
2052         struct drm_info_node *node = (struct drm_info_node *) m->private;
2053         struct drm_device *dev = node->minor->dev;
2054         struct amdgpu_device *adev = dev->dev_private;
2055         struct drm_device *ddev = adev->ddev;
2056         u32 flags = 0;
2057
2058         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2059         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2060         amdgpu_parse_cg_state(m, flags);
2061         seq_printf(m, "\n");
2062
2063         if (!adev->pm.dpm_enabled) {
2064                 seq_printf(m, "dpm not enabled\n");
2065                 return 0;
2066         }
2067         if  ((adev->flags & AMD_IS_PX) &&
2068              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2069                 seq_printf(m, "PX asic powered off\n");
2070         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2071                 mutex_lock(&adev->pm.mutex);
2072                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2073                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2074                 else
2075                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2076                 mutex_unlock(&adev->pm.mutex);
2077         } else {
2078                 return amdgpu_debugfs_pm_info_pp(m, adev);
2079         }
2080
2081         return 0;
2082 }
2083
2084 static const struct drm_info_list amdgpu_pm_info_list[] = {
2085         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2086 };
2087 #endif
2088
2089 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2090 {
2091 #if defined(CONFIG_DEBUG_FS)
2092         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2093 #else
2094         return 0;
2095 #endif
2096 }