drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34 #include "amdgpu_gmc.h"
  35
  36 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  37                                       struct drm_amdgpu_cs_chunk_fence *data,
  38                                       uint32_t *offset)
  39 {
  40         struct drm_gem_object *gobj;
  41         unsigned long size;
  42
  43         gobj = drm_gem_object_lookup(p->filp, data->handle);
  44         if (gobj == NULL)
  45                 return -EINVAL;
  46
  47         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  48         p->uf_entry.priority = 0;
  49         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  50         p->uf_entry.tv.shared = true;
  51         p->uf_entry.user_pages = NULL;
  52
  53         size = amdgpu_bo_size(p->uf_entry.robj);
  54         if (size != PAGE_SIZE || (data->offset + 8) > size)
  55                 return -EINVAL;
  56
  57         *offset = data->offset;
  58
  59         drm_gem_object_put_unlocked(gobj);
  60
  61         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  62                 amdgpu_bo_unref(&p->uf_entry.robj);
  63                 return -EINVAL;
  64         }
  65
  66         return 0;
  67 }
  68
  69 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  70                                       struct drm_amdgpu_bo_list_in *data)
  71 {
  72         int r;
  73         struct drm_amdgpu_bo_list_entry *info = NULL;
  74
  75         r = amdgpu_bo_create_list_entry_array(data, &info);
  76         if (r)
  77                 return r;
  78
  79         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  80                                   &p->bo_list);
  81         if (r)
  82                 goto error_free;
  83
  84         kvfree(info);
  85         return 0;
  86
  87 error_free:
  88         if (info)
  89                 kvfree(info);
  90
  91         return r;
  92 }
  93
  94 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
  95 {
  96         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  97         struct amdgpu_vm *vm = &fpriv->vm;
  98         uint64_t *chunk_array_user;
  99         uint64_t *chunk_array;
 100         unsigned size, num_ibs = 0;
 101         uint32_t uf_offset = 0;
 102         int i;
 103         int ret;
 104
 105         if (cs->in.num_chunks == 0)
 106                 return 0;
 107
 108         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 109         if (!chunk_array)
 110                 return -ENOMEM;
 111
 112         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 113         if (!p->ctx) {
 114                 ret = -EINVAL;
 115                 goto free_chunk;
 116         }
 117
 118         /* skip guilty context job */
 119         if (atomic_read(&p->ctx->guilty) == 1) {
 120                 ret = -ECANCELED;
 121                 goto free_chunk;
 122         }
 123
 124         mutex_lock(&p->ctx->lock);
 125
 126         /* get chunks */
 127         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 128         if (copy_from_user(chunk_array, chunk_array_user,
 129                            sizeof(uint64_t)*cs->in.num_chunks)) {
 130                 ret = -EFAULT;
 131                 goto free_chunk;
 132         }
 133
 134         p->nchunks = cs->in.num_chunks;
 135         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 136                             GFP_KERNEL);
 137         if (!p->chunks) {
 138                 ret = -ENOMEM;
 139                 goto free_chunk;
 140         }
 141
 142         for (i = 0; i < p->nchunks; i++) {
 143                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 144                 struct drm_amdgpu_cs_chunk user_chunk;
 145                 uint32_t __user *cdata;
 146
 147                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 148                 if (copy_from_user(&user_chunk, chunk_ptr,
 149                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 150                         ret = -EFAULT;
 151                         i--;
 152                         goto free_partial_kdata;
 153                 }
 154                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 155                 p->chunks[i].length_dw = user_chunk.length_dw;
 156
 157                 size = p->chunks[i].length_dw;
 158                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 159
 160                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 161                 if (p->chunks[i].kdata == NULL) {
 162                         ret = -ENOMEM;
 163                         i--;
 164                         goto free_partial_kdata;
 165                 }
 166                 size *= sizeof(uint32_t);
 167                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 168                         ret = -EFAULT;
 169                         goto free_partial_kdata;
 170                 }
 171
 172                 switch (p->chunks[i].chunk_id) {
 173                 case AMDGPU_CHUNK_ID_IB:
 174                         ++num_ibs;
 175                         break;
 176
 177                 case AMDGPU_CHUNK_ID_FENCE:
 178                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 179                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 180                                 ret = -EINVAL;
 181                                 goto free_partial_kdata;
 182                         }
 183
 184                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 185                                                          &uf_offset);
 186                         if (ret)
 187                                 goto free_partial_kdata;
 188
 189                         break;
 190
 191                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 192                         size = sizeof(struct drm_amdgpu_bo_list_in);
 193                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 194                                 ret = -EINVAL;
 195                                 goto free_partial_kdata;
 196                         }
 197
 198                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 199                         if (ret)
 200                                 goto free_partial_kdata;
 201
 202                         break;
 203
 204                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 205                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 206                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 207                         break;
 208
 209                 default:
 210                         ret = -EINVAL;
 211                         goto free_partial_kdata;
 212                 }
 213         }
 214
 215         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 216         if (ret)
 217                 goto free_all_kdata;
 218
 219         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 220                 ret = -ECANCELED;
 221                 goto free_all_kdata;
 222         }
 223
 224         if (p->uf_entry.robj)
 225                 p->job->uf_addr = uf_offset;
 226         kfree(chunk_array);
 227
 228         /* Use this opportunity to fill in task info for the vm */
 229         amdgpu_vm_set_task_info(vm);
 230
 231         return 0;
 232
 233 free_all_kdata:
 234         i = p->nchunks - 1;
 235 free_partial_kdata:
 236         for (; i >= 0; i--)
 237                 kvfree(p->chunks[i].kdata);
 238         kfree(p->chunks);
 239         p->chunks = NULL;
 240         p->nchunks = 0;
 241 free_chunk:
 242         kfree(chunk_array);
 243
 244         return ret;
 245 }
 246
 247 /* Convert microseconds to bytes. */
 248 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 249 {
 250         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 251                 return 0;
 252
 253         /* Since accum_us is incremented by a million per second, just
 254          * multiply it by the number of MB/s to get the number of bytes.
 255          */
 256         return us << adev->mm_stats.log2_max_MBps;
 257 }
 258
 259 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 260 {
 261         if (!adev->mm_stats.log2_max_MBps)
 262                 return 0;
 263
 264         return bytes >> adev->mm_stats.log2_max_MBps;
 265 }
 266
 267 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 268  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 269  * which means it can go over the threshold once. If that happens, the driver
 270  * will be in debt and no other buffer migrations can be done until that debt
 271  * is repaid.
 272  *
 273  * This approach allows moving a buffer of any size (it's important to allow
 274  * that).
 275  *
 276  * The currency is simply time in microseconds and it increases as the clock
 277  * ticks. The accumulated microseconds (us) are converted to bytes and
 278  * returned.
 279  */
 280 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 281                                               u64 *max_bytes,
 282                                               u64 *max_vis_bytes)
 283 {
 284         s64 time_us, increment_us;
 285         u64 free_vram, total_vram, used_vram;
 286
 287         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 288          * throttling.
 289          *
 290          * It means that in order to get full max MBps, at least 5 IBs per
 291          * second must be submitted and not more than 200ms apart from each
 292          * other.
 293          */
 294         const s64 us_upper_bound = 200000;
 295
 296         if (!adev->mm_stats.log2_max_MBps) {
 297                 *max_bytes = 0;
 298                 *max_vis_bytes = 0;
 299                 return;
 300         }
 301
 302         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 303         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 304         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 305
 306         spin_lock(&adev->mm_stats.lock);
 307
 308         /* Increase the amount of accumulated us. */
 309         time_us = ktime_to_us(ktime_get());
 310         increment_us = time_us - adev->mm_stats.last_update_us;
 311         adev->mm_stats.last_update_us = time_us;
 312         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 313                                       us_upper_bound);
 314
 315         /* This prevents the short period of low performance when the VRAM
 316          * usage is low and the driver is in debt or doesn't have enough
 317          * accumulated us to fill VRAM quickly.
 318          *
 319          * The situation can occur in these cases:
 320          * - a lot of VRAM is freed by userspace
 321          * - the presence of a big buffer causes a lot of evictions
 322          *   (solution: split buffers into smaller ones)
 323          *
 324          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 325          * accum_us to a positive number.
 326          */
 327         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 328                 s64 min_us;
 329
 330                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 331                  * VRAM now.
 332                  */
 333                 if (!(adev->flags & AMD_IS_APU))
 334                         min_us = bytes_to_us(adev, free_vram / 4);
 335                 else
 336                         min_us = 0; /* Reset accum_us on APUs. */
 337
 338                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 339         }
 340
 341         /* This is set to 0 if the driver is in debt to disallow (optional)
 342          * buffer moves.
 343          */
 344         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 345
 346         /* Do the same for visible VRAM if half of it is free */
 347         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 348                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 349                 u64 used_vis_vram =
 350                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 351
 352                 if (used_vis_vram < total_vis_vram) {
 353                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 354                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 355                                                           increment_us, us_upper_bound);
 356
 357                         if (free_vis_vram >= total_vis_vram / 2)
 358                                 adev->mm_stats.accum_us_vis =
 359                                         max(bytes_to_us(adev, free_vis_vram / 2),
 360                                             adev->mm_stats.accum_us_vis);
 361                 }
 362
 363                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 364         } else {
 365                 *max_vis_bytes = 0;
 366         }
 367
 368         spin_unlock(&adev->mm_stats.lock);
 369 }
 370
 371 /* Report how many bytes have really been moved for the last command
 372  * submission. This can result in a debt that can stop buffer migrations
 373  * temporarily.
 374  */
 375 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 376                                   u64 num_vis_bytes)
 377 {
 378         spin_lock(&adev->mm_stats.lock);
 379         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 380         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 381         spin_unlock(&adev->mm_stats.lock);
 382 }
 383
 384 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 385                                  struct amdgpu_bo *bo)
 386 {
 387         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 388         struct ttm_operation_ctx ctx = {
 389                 .interruptible = true,
 390                 .no_wait_gpu = false,
 391                 .resv = bo->tbo.resv,
 392                 .flags = 0
 393         };
 394         uint32_t domain;
 395         int r;
 396
 397         if (bo->pin_count)
 398                 return 0;
 399
 400         /* Don't move this buffer if we have depleted our allowance
 401          * to move it. Don't move anything if the threshold is zero.
 402          */
 403         if (p->bytes_moved < p->bytes_moved_threshold) {
 404                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 405                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 406                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 407                          * visible VRAM if we've depleted our allowance to do
 408                          * that.
 409                          */
 410                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 411                                 domain = bo->preferred_domains;
 412                         else
 413                                 domain = bo->allowed_domains;
 414                 } else {
 415                         domain = bo->preferred_domains;
 416                 }
 417         } else {
 418                 domain = bo->allowed_domains;
 419         }
 420
 421 retry:
 422         amdgpu_bo_placement_from_domain(bo, domain);
 423         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 424
 425         p->bytes_moved += ctx.bytes_moved;
 426         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 427             amdgpu_bo_in_cpu_visible_vram(bo))
 428                 p->bytes_moved_vis += ctx.bytes_moved;
 429
 430         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 431                 domain = bo->allowed_domains;
 432                 goto retry;
 433         }
 434
 435         return r;
 436 }
 437
 438 /* Last resort, try to evict something from the current working set */
 439 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 440                                 struct amdgpu_bo *validated)
 441 {
 442         uint32_t domain = validated->allowed_domains;
 443         struct ttm_operation_ctx ctx = { true, false };
 444         int r;
 445
 446         if (!p->evictable)
 447                 return false;
 448
 449         for (;&p->evictable->tv.head != &p->validated;
 450              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 451
 452                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 453                 struct amdgpu_bo *bo = candidate->robj;
 454                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 455                 bool update_bytes_moved_vis;
 456                 uint32_t other;
 457
 458                 /* If we reached our current BO we can forget it */
 459                 if (candidate->robj == validated)
 460                         break;
 461
 462                 /* We can't move pinned BOs here */
 463                 if (bo->pin_count)
 464                         continue;
 465
 466                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 467
 468                 /* Check if this BO is in one of the domains we need space for */
 469                 if (!(other & domain))
 470                         continue;
 471
 472                 /* Check if we can move this BO somewhere else */
 473                 other = bo->allowed_domains & ~domain;
 474                 if (!other)
 475                         continue;
 476
 477                 /* Good we can try to move this BO somewhere else */
 478                 update_bytes_moved_vis =
 479                                 !amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 480                                 amdgpu_bo_in_cpu_visible_vram(bo);
 481                 amdgpu_bo_placement_from_domain(bo, other);
 482                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 483                 p->bytes_moved += ctx.bytes_moved;
 484                 if (update_bytes_moved_vis)
 485                         p->bytes_moved_vis += ctx.bytes_moved;
 486
 487                 if (unlikely(r))
 488                         break;
 489
 490                 p->evictable = list_prev_entry(p->evictable, tv.head);
 491                 list_move(&candidate->tv.head, &p->validated);
 492
 493                 return true;
 494         }
 495
 496         return false;
 497 }
 498
 499 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 500 {
 501         struct amdgpu_cs_parser *p = param;
 502         int r;
 503
 504         do {
 505                 r = amdgpu_cs_bo_validate(p, bo);
 506         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 507         if (r)
 508                 return r;
 509
 510         if (bo->shadow)
 511                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 512
 513         return r;
 514 }
 515
 516 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 517                             struct list_head *validated)
 518 {
 519         struct ttm_operation_ctx ctx = { true, false };
 520         struct amdgpu_bo_list_entry *lobj;
 521         int r;
 522
 523         list_for_each_entry(lobj, validated, tv.head) {
 524                 struct amdgpu_bo *bo = lobj->robj;
 525                 bool binding_userptr = false;
 526                 struct mm_struct *usermm;
 527
 528                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 529                 if (usermm && usermm != current->mm)
 530                         return -EPERM;
 531
 532                 /* Check if we have user pages and nobody bound the BO already */
 533                 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 534                     lobj->user_pages) {
 535                         amdgpu_bo_placement_from_domain(bo,
 536                                                         AMDGPU_GEM_DOMAIN_CPU);
 537                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 538                         if (r)
 539                                 return r;
 540                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 541                                                      lobj->user_pages);
 542                         binding_userptr = true;
 543                 }
 544
 545                 if (p->evictable == lobj)
 546                         p->evictable = NULL;
 547
 548                 r = amdgpu_cs_validate(p, bo);
 549                 if (r)
 550                         return r;
 551
 552                 if (binding_userptr) {
 553                         kvfree(lobj->user_pages);
 554                         lobj->user_pages = NULL;
 555                 }
 556         }
 557         return 0;
 558 }
 559
 560 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 561                                 union drm_amdgpu_cs *cs)
 562 {
 563         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 564         struct amdgpu_bo_list_entry *e;
 565         struct list_head duplicates;
 566         unsigned i, tries = 10;
 567         struct amdgpu_bo *gds;
 568         struct amdgpu_bo *gws;
 569         struct amdgpu_bo *oa;
 570         int r;
 571
 572         INIT_LIST_HEAD(&p->validated);
 573
 574         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 575         if (!p->bo_list)
 576                 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 577         else
 578                 mutex_lock(&p->bo_list->lock);
 579
 580         if (p->bo_list) {
 581                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 582                 if (p->bo_list->first_userptr != p->bo_list->num_entries)
 583                         p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
 584         }
 585
 586         INIT_LIST_HEAD(&duplicates);
 587         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 588
 589         if (p->uf_entry.robj && !p->uf_entry.robj->parent)
 590                 list_add(&p->uf_entry.tv.head, &p->validated);
 591
 592         while (1) {
 593                 struct list_head need_pages;
 594                 unsigned i;
 595
 596                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 597                                            &duplicates);
 598                 if (unlikely(r != 0)) {
 599                         if (r != -ERESTARTSYS)
 600                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 601                         goto error_free_pages;
 602                 }
 603
 604                 /* Without a BO list we don't have userptr BOs */
 605                 if (!p->bo_list)
 606                         break;
 607
 608                 INIT_LIST_HEAD(&need_pages);
 609                 for (i = p->bo_list->first_userptr;
 610                      i < p->bo_list->num_entries; ++i) {
 611                         struct amdgpu_bo *bo;
 612
 613                         e = &p->bo_list->array[i];
 614                         bo = e->robj;
 615
 616                         if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
 617                                  &e->user_invalidated) && e->user_pages) {
 618
 619                                 /* We acquired a page array, but somebody
 620                                  * invalidated it. Free it and try again
 621                                  */
 622                                 release_pages(e->user_pages,
 623                                               bo->tbo.ttm->num_pages);
 624                                 kvfree(e->user_pages);
 625                                 e->user_pages = NULL;
 626                         }
 627
 628                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 629                             !e->user_pages) {
 630                                 list_del(&e->tv.head);
 631                                 list_add(&e->tv.head, &need_pages);
 632
 633                                 amdgpu_bo_unreserve(e->robj);
 634                         }
 635                 }
 636
 637                 if (list_empty(&need_pages))
 638                         break;
 639
 640                 /* Unreserve everything again. */
 641                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 642
 643                 /* We tried too many times, just abort */
 644                 if (!--tries) {
 645                         r = -EDEADLK;
 646                         DRM_ERROR("deadlock in %s\n", __func__);
 647                         goto error_free_pages;
 648                 }
 649
 650                 /* Fill the page arrays for all userptrs. */
 651                 list_for_each_entry(e, &need_pages, tv.head) {
 652                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 653
 654                         e->user_pages = kvmalloc_array(ttm->num_pages,
 655                                                          sizeof(struct page*),
 656                                                          GFP_KERNEL | __GFP_ZERO);
 657                         if (!e->user_pages) {
 658                                 r = -ENOMEM;
 659                                 DRM_ERROR("calloc failure in %s\n", __func__);
 660                                 goto error_free_pages;
 661                         }
 662
 663                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 664                         if (r) {
 665                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 666                                 kvfree(e->user_pages);
 667                                 e->user_pages = NULL;
 668                                 goto error_free_pages;
 669                         }
 670                 }
 671
 672                 /* And try again. */
 673                 list_splice(&need_pages, &p->validated);
 674         }
 675
 676         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 677                                           &p->bytes_moved_vis_threshold);
 678         p->bytes_moved = 0;
 679         p->bytes_moved_vis = 0;
 680         p->evictable = list_last_entry(&p->validated,
 681                                        struct amdgpu_bo_list_entry,
 682                                        tv.head);
 683
 684         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 685                                       amdgpu_cs_validate, p);
 686         if (r) {
 687                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 688                 goto error_validate;
 689         }
 690
 691         r = amdgpu_cs_list_validate(p, &duplicates);
 692         if (r) {
 693                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 694                 goto error_validate;
 695         }
 696
 697         r = amdgpu_cs_list_validate(p, &p->validated);
 698         if (r) {
 699                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 700                 goto error_validate;
 701         }
 702
 703         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 704                                      p->bytes_moved_vis);
 705
 706         if (p->bo_list) {
 707                 struct amdgpu_vm *vm = &fpriv->vm;
 708                 unsigned i;
 709
 710                 gds = p->bo_list->gds_obj;
 711                 gws = p->bo_list->gws_obj;
 712                 oa = p->bo_list->oa_obj;
 713                 for (i = 0; i < p->bo_list->num_entries; i++) {
 714                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 715
 716                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 717                 }
 718         } else {
 719                 gds = p->adev->gds.gds_gfx_bo;
 720                 gws = p->adev->gds.gws_gfx_bo;
 721                 oa = p->adev->gds.oa_gfx_bo;
 722         }
 723
 724         if (gds) {
 725                 p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 726                 p->job->gds_size = amdgpu_bo_size(gds);
 727         }
 728         if (gws) {
 729                 p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 730                 p->job->gws_size = amdgpu_bo_size(gws);
 731         }
 732         if (oa) {
 733                 p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 734                 p->job->oa_size = amdgpu_bo_size(oa);
 735         }
 736
 737         if (!r && p->uf_entry.robj) {
 738                 struct amdgpu_bo *uf = p->uf_entry.robj;
 739
 740                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 741                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 742         }
 743
 744 error_validate:
 745         if (r)
 746                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 747
 748 error_free_pages:
 749
 750         if (p->bo_list) {
 751                 for (i = p->bo_list->first_userptr;
 752                      i < p->bo_list->num_entries; ++i) {
 753                         e = &p->bo_list->array[i];
 754
 755                         if (!e->user_pages)
 756                                 continue;
 757
 758                         release_pages(e->user_pages,
 759                                       e->robj->tbo.ttm->num_pages);
 760                         kvfree(e->user_pages);
 761                 }
 762         }
 763
 764         return r;
 765 }
 766
 767 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 768 {
 769         struct amdgpu_bo_list_entry *e;
 770         int r;
 771
 772         list_for_each_entry(e, &p->validated, tv.head) {
 773                 struct reservation_object *resv = e->robj->tbo.resv;
 774                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 775                                      amdgpu_bo_explicit_sync(e->robj));
 776
 777                 if (r)
 778                         return r;
 779         }
 780         return 0;
 781 }
 782
 783 /**
 784  * cs_parser_fini() - clean parser states
 785  * @parser:     parser structure holding parsing context.
 786  * @error:      error number
 787  *
 788  * If error is set than unvalidate buffer, otherwise just free memory
 789  * used by parsing context.
 790  **/
 791 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 792                                   bool backoff)
 793 {
 794         unsigned i;
 795
 796         if (error && backoff)
 797                 ttm_eu_backoff_reservation(&parser->ticket,
 798                                            &parser->validated);
 799
 800         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 801                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 802         kfree(parser->post_dep_syncobjs);
 803
 804         dma_fence_put(parser->fence);
 805
 806         if (parser->ctx) {
 807                 mutex_unlock(&parser->ctx->lock);
 808                 amdgpu_ctx_put(parser->ctx);
 809         }
 810         if (parser->bo_list)
 811                 amdgpu_bo_list_put(parser->bo_list);
 812
 813         for (i = 0; i < parser->nchunks; i++)
 814                 kvfree(parser->chunks[i].kdata);
 815         kfree(parser->chunks);
 816         if (parser->job)
 817                 amdgpu_job_free(parser->job);
 818         amdgpu_bo_unref(&parser->uf_entry.robj);
 819 }
 820
 821 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 822 {
 823         struct amdgpu_device *adev = p->adev;
 824         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 825         struct amdgpu_vm *vm = &fpriv->vm;
 826         struct amdgpu_bo_va *bo_va;
 827         struct amdgpu_bo *bo;
 828         int i, r;
 829
 830         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 831         if (r)
 832                 return r;
 833
 834         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 835         if (r)
 836                 return r;
 837
 838         r = amdgpu_sync_fence(adev, &p->job->sync,
 839                               fpriv->prt_va->last_pt_update, false);
 840         if (r)
 841                 return r;
 842
 843         if (amdgpu_sriov_vf(adev)) {
 844                 struct dma_fence *f;
 845
 846                 bo_va = fpriv->csa_va;
 847                 BUG_ON(!bo_va);
 848                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 849                 if (r)
 850                         return r;
 851
 852                 f = bo_va->last_pt_update;
 853                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 854                 if (r)
 855                         return r;
 856         }
 857
 858         if (p->bo_list) {
 859                 for (i = 0; i < p->bo_list->num_entries; i++) {
 860                         struct dma_fence *f;
 861
 862                         /* ignore duplicates */
 863                         bo = p->bo_list->array[i].robj;
 864                         if (!bo)
 865                                 continue;
 866
 867                         bo_va = p->bo_list->array[i].bo_va;
 868                         if (bo_va == NULL)
 869                                 continue;
 870
 871                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 872                         if (r)
 873                                 return r;
 874
 875                         f = bo_va->last_pt_update;
 876                         r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 877                         if (r)
 878                                 return r;
 879                 }
 880
 881         }
 882
 883         r = amdgpu_vm_handle_moved(adev, vm);
 884         if (r)
 885                 return r;
 886
 887         r = amdgpu_vm_update_directories(adev, vm);
 888         if (r)
 889                 return r;
 890
 891         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
 892         if (r)
 893                 return r;
 894
 895         if (amdgpu_vm_debug && p->bo_list) {
 896                 /* Invalidate all BOs to test for userspace bugs */
 897                 for (i = 0; i < p->bo_list->num_entries; i++) {
 898                         /* ignore duplicates */
 899                         bo = p->bo_list->array[i].robj;
 900                         if (!bo)
 901                                 continue;
 902
 903                         amdgpu_vm_bo_invalidate(adev, bo, false);
 904                 }
 905         }
 906
 907         return r;
 908 }
 909
 910 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 911                                  struct amdgpu_cs_parser *p)
 912 {
 913         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 914         struct amdgpu_vm *vm = &fpriv->vm;
 915         struct amdgpu_ring *ring = p->ring;
 916         int r;
 917
 918         /* Only for UVD/VCE VM emulation */
 919         if (p->ring->funcs->parse_cs) {
 920                 unsigned i, j;
 921
 922                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 923                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 924                         struct amdgpu_bo_va_mapping *m;
 925                         struct amdgpu_bo *aobj = NULL;
 926                         struct amdgpu_cs_chunk *chunk;
 927                         uint64_t offset, va_start;
 928                         struct amdgpu_ib *ib;
 929                         uint8_t *kptr;
 930
 931                         chunk = &p->chunks[i];
 932                         ib = &p->job->ibs[j];
 933                         chunk_ib = chunk->kdata;
 934
 935                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 936                                 continue;
 937
 938                         va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
 939                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 940                         if (r) {
 941                                 DRM_ERROR("IB va_start is invalid\n");
 942                                 return r;
 943                         }
 944
 945                         if ((va_start + chunk_ib->ib_bytes) >
 946                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 947                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 948                                 return -EINVAL;
 949                         }
 950
 951                         /* the IB should be reserved at this point */
 952                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 953                         if (r) {
 954                                 return r;
 955                         }
 956
 957                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 958                         kptr += va_start - offset;
 959
 960                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 961                         amdgpu_bo_kunmap(aobj);
 962
 963                         r = amdgpu_ring_parse_cs(ring, p, j);
 964                         if (r)
 965                                 return r;
 966
 967                         j++;
 968                 }
 969         }
 970
 971         if (p->job->vm) {
 972                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
 973
 974                 r = amdgpu_bo_vm_update_pte(p);
 975                 if (r)
 976                         return r;
 977
 978                 r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
 979                 if (r)
 980                         return r;
 981         }
 982
 983         return amdgpu_cs_sync_rings(p);
 984 }
 985
 986 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 987                              struct amdgpu_cs_parser *parser)
 988 {
 989         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 990         struct amdgpu_vm *vm = &fpriv->vm;
 991         int i, j;
 992         int r, ce_preempt = 0, de_preempt = 0;
 993
 994         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 995                 struct amdgpu_cs_chunk *chunk;
 996                 struct amdgpu_ib *ib;
 997                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 998                 struct amdgpu_ring *ring;
 999
1000                 chunk = &parser->chunks[i];
1001                 ib = &parser->job->ibs[j];
1002                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
1003
1004                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
1005                         continue;
1006
1007                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
1008                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
1009                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
1010                                         ce_preempt++;
1011                                 else
1012                                         de_preempt++;
1013                         }
1014
1015                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
1016                         if (ce_preempt > 1 || de_preempt > 1)
1017                                 return -EINVAL;
1018                 }
1019
1020                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
1021                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
1022                 if (r)
1023                         return r;
1024
1025                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
1026                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
1027                         if (!parser->ctx->preamble_presented) {
1028                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1029                                 parser->ctx->preamble_presented = true;
1030                         }
1031                 }
1032
1033                 if (parser->ring && parser->ring != ring)
1034                         return -EINVAL;
1035
1036                 parser->ring = ring;
1037
1038                 r =  amdgpu_ib_get(adev, vm,
1039                                         ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
1040                                         ib);
1041                 if (r) {
1042                         DRM_ERROR("Failed to get ib !\n");
1043                         return r;
1044                 }
1045
1046                 ib->gpu_addr = chunk_ib->va_start;
1047                 ib->length_dw = chunk_ib->ib_bytes / 4;
1048                 ib->flags = chunk_ib->flags;
1049
1050                 j++;
1051         }
1052
1053         /* UVD & VCE fw doesn't support user fences */
1054         if (parser->job->uf_addr && (
1055             parser->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
1056             parser->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1057                 return -EINVAL;
1058
1059         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->ring->idx);
1060 }
1061
1062 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1063                                        struct amdgpu_cs_chunk *chunk)
1064 {
1065         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1066         unsigned num_deps;
1067         int i, r;
1068         struct drm_amdgpu_cs_chunk_dep *deps;
1069
1070         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1071         num_deps = chunk->length_dw * 4 /
1072                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1073
1074         for (i = 0; i < num_deps; ++i) {
1075                 struct amdgpu_ring *ring;
1076                 struct amdgpu_ctx *ctx;
1077                 struct dma_fence *fence;
1078
1079                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1080                 if (ctx == NULL)
1081                         return -EINVAL;
1082
1083                 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1084                                          deps[i].ip_type,
1085                                          deps[i].ip_instance,
1086                                          deps[i].ring, &ring);
1087                 if (r) {
1088                         amdgpu_ctx_put(ctx);
1089                         return r;
1090                 }
1091
1092                 fence = amdgpu_ctx_get_fence(ctx, ring,
1093                                              deps[i].handle);
1094                 if (IS_ERR(fence)) {
1095                         r = PTR_ERR(fence);
1096                         amdgpu_ctx_put(ctx);
1097                         return r;
1098                 } else if (fence) {
1099                         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1100                                         true);
1101                         dma_fence_put(fence);
1102                         amdgpu_ctx_put(ctx);
1103                         if (r)
1104                                 return r;
1105                 }
1106         }
1107         return 0;
1108 }
1109
1110 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1111                                                  uint32_t handle)
1112 {
1113         int r;
1114         struct dma_fence *fence;
1115         r = drm_syncobj_find_fence(p->filp, handle, &fence);
1116         if (r)
1117                 return r;
1118
1119         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1120         dma_fence_put(fence);
1121
1122         return r;
1123 }
1124
1125 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1126                                             struct amdgpu_cs_chunk *chunk)
1127 {
1128         unsigned num_deps;
1129         int i, r;
1130         struct drm_amdgpu_cs_chunk_sem *deps;
1131
1132         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1133         num_deps = chunk->length_dw * 4 /
1134                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1135
1136         for (i = 0; i < num_deps; ++i) {
1137                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1138                 if (r)
1139                         return r;
1140         }
1141         return 0;
1142 }
1143
1144 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1145                                              struct amdgpu_cs_chunk *chunk)
1146 {
1147         unsigned num_deps;
1148         int i;
1149         struct drm_amdgpu_cs_chunk_sem *deps;
1150         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1151         num_deps = chunk->length_dw * 4 /
1152                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1153
1154         p->post_dep_syncobjs = kmalloc_array(num_deps,
1155                                              sizeof(struct drm_syncobj *),
1156                                              GFP_KERNEL);
1157         p->num_post_dep_syncobjs = 0;
1158
1159         if (!p->post_dep_syncobjs)
1160                 return -ENOMEM;
1161
1162         for (i = 0; i < num_deps; ++i) {
1163                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1164                 if (!p->post_dep_syncobjs[i])
1165                         return -EINVAL;
1166                 p->num_post_dep_syncobjs++;
1167         }
1168         return 0;
1169 }
1170
1171 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1172                                   struct amdgpu_cs_parser *p)
1173 {
1174         int i, r;
1175
1176         for (i = 0; i < p->nchunks; ++i) {
1177                 struct amdgpu_cs_chunk *chunk;
1178
1179                 chunk = &p->chunks[i];
1180
1181                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1182                         r = amdgpu_cs_process_fence_dep(p, chunk);
1183                         if (r)
1184                                 return r;
1185                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1186                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1187                         if (r)
1188                                 return r;
1189                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1190                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1191                         if (r)
1192                                 return r;
1193                 }
1194         }
1195
1196         return 0;
1197 }
1198
1199 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1200 {
1201         int i;
1202
1203         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1204                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1205 }
1206
1207 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1208                             union drm_amdgpu_cs *cs)
1209 {
1210         struct amdgpu_ring *ring = p->ring;
1211         struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1212         enum drm_sched_priority priority;
1213         struct amdgpu_job *job;
1214         unsigned i;
1215         uint64_t seq;
1216
1217         int r;
1218
1219         amdgpu_mn_lock(p->mn);
1220         if (p->bo_list) {
1221                 for (i = p->bo_list->first_userptr;
1222                      i < p->bo_list->num_entries; ++i) {
1223                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
1224
1225                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1226                                 amdgpu_mn_unlock(p->mn);
1227                                 return -ERESTARTSYS;
1228                         }
1229                 }
1230         }
1231
1232         job = p->job;
1233         p->job = NULL;
1234
1235         r = drm_sched_job_init(&job->base, entity, p->filp);
1236         if (r) {
1237                 amdgpu_job_free(job);
1238                 amdgpu_mn_unlock(p->mn);
1239                 return r;
1240         }
1241
1242         job->owner = p->filp;
1243         p->fence = dma_fence_get(&job->base.s_fence->finished);
1244
1245         r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
1246         if (r) {
1247                 dma_fence_put(p->fence);
1248                 dma_fence_put(&job->base.s_fence->finished);
1249                 amdgpu_job_free(job);
1250                 amdgpu_mn_unlock(p->mn);
1251                 return r;
1252         }
1253
1254         amdgpu_cs_post_dependencies(p);
1255
1256         cs->out.handle = seq;
1257         job->uf_sequence = seq;
1258
1259         amdgpu_job_free_resources(job);
1260
1261         trace_amdgpu_cs_ioctl(job);
1262         priority = job->base.s_priority;
1263         drm_sched_entity_push_job(&job->base, entity);
1264
1265         ring = to_amdgpu_ring(entity->rq->sched);
1266         amdgpu_ring_priority_get(ring, priority);
1267
1268         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1269         amdgpu_mn_unlock(p->mn);
1270
1271         return 0;
1272 }
1273
1274 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1275 {
1276         struct amdgpu_device *adev = dev->dev_private;
1277         union drm_amdgpu_cs *cs = data;
1278         struct amdgpu_cs_parser parser = {};
1279         bool reserved_buffers = false;
1280         int i, r;
1281
1282         if (!adev->accel_working)
1283                 return -EBUSY;
1284
1285         parser.adev = adev;
1286         parser.filp = filp;
1287
1288         r = amdgpu_cs_parser_init(&parser, data);
1289         if (r) {
1290                 DRM_ERROR("Failed to initialize parser !\n");
1291                 goto out;
1292         }
1293
1294         r = amdgpu_cs_ib_fill(adev, &parser);
1295         if (r)
1296                 goto out;
1297
1298         r = amdgpu_cs_parser_bos(&parser, data);
1299         if (r) {
1300                 if (r == -ENOMEM)
1301                         DRM_ERROR("Not enough memory for command submission!\n");
1302                 else if (r != -ERESTARTSYS)
1303                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1304                 goto out;
1305         }
1306
1307         reserved_buffers = true;
1308
1309         r = amdgpu_cs_dependencies(adev, &parser);
1310         if (r) {
1311                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1312                 goto out;
1313         }
1314
1315         for (i = 0; i < parser.job->num_ibs; i++)
1316                 trace_amdgpu_cs(&parser, i);
1317
1318         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1319         if (r)
1320                 goto out;
1321
1322         r = amdgpu_cs_submit(&parser, cs);
1323
1324 out:
1325         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1326         return r;
1327 }
1328
1329 /**
1330  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1331  *
1332  * @dev: drm device
1333  * @data: data from userspace
1334  * @filp: file private
1335  *
1336  * Wait for the command submission identified by handle to finish.
1337  */
1338 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1339                          struct drm_file *filp)
1340 {
1341         union drm_amdgpu_wait_cs *wait = data;
1342         struct amdgpu_device *adev = dev->dev_private;
1343         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1344         struct amdgpu_ring *ring = NULL;
1345         struct amdgpu_ctx *ctx;
1346         struct dma_fence *fence;
1347         long r;
1348
1349         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1350         if (ctx == NULL)
1351                 return -EINVAL;
1352
1353         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1354                                  wait->in.ip_type, wait->in.ip_instance,
1355                                  wait->in.ring, &ring);
1356         if (r) {
1357                 amdgpu_ctx_put(ctx);
1358                 return r;
1359         }
1360
1361         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1362         if (IS_ERR(fence))
1363                 r = PTR_ERR(fence);
1364         else if (fence) {
1365                 r = dma_fence_wait_timeout(fence, true, timeout);
1366                 if (r > 0 && fence->error)
1367                         r = fence->error;
1368                 dma_fence_put(fence);
1369         } else
1370                 r = 1;
1371
1372         amdgpu_ctx_put(ctx);
1373         if (r < 0)
1374                 return r;
1375
1376         memset(wait, 0, sizeof(*wait));
1377         wait->out.status = (r == 0);
1378
1379         return 0;
1380 }
1381
1382 /**
1383  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1384  *
1385  * @adev: amdgpu device
1386  * @filp: file private
1387  * @user: drm_amdgpu_fence copied from user space
1388  */
1389 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1390                                              struct drm_file *filp,
1391                                              struct drm_amdgpu_fence *user)
1392 {
1393         struct amdgpu_ring *ring;
1394         struct amdgpu_ctx *ctx;
1395         struct dma_fence *fence;
1396         int r;
1397
1398         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1399         if (ctx == NULL)
1400                 return ERR_PTR(-EINVAL);
1401
1402         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1403                                  user->ip_instance, user->ring, &ring);
1404         if (r) {
1405                 amdgpu_ctx_put(ctx);
1406                 return ERR_PTR(r);
1407         }
1408
1409         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1410         amdgpu_ctx_put(ctx);
1411
1412         return fence;
1413 }
1414
1415 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1416                                     struct drm_file *filp)
1417 {
1418         struct amdgpu_device *adev = dev->dev_private;
1419         union drm_amdgpu_fence_to_handle *info = data;
1420         struct dma_fence *fence;
1421         struct drm_syncobj *syncobj;
1422         struct sync_file *sync_file;
1423         int fd, r;
1424
1425         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1426         if (IS_ERR(fence))
1427                 return PTR_ERR(fence);
1428
1429         switch (info->in.what) {
1430         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1431                 r = drm_syncobj_create(&syncobj, 0, fence);
1432                 dma_fence_put(fence);
1433                 if (r)
1434                         return r;
1435                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1436                 drm_syncobj_put(syncobj);
1437                 return r;
1438
1439         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1440                 r = drm_syncobj_create(&syncobj, 0, fence);
1441                 dma_fence_put(fence);
1442                 if (r)
1443                         return r;
1444                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1445                 drm_syncobj_put(syncobj);
1446                 return r;
1447
1448         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1449                 fd = get_unused_fd_flags(O_CLOEXEC);
1450                 if (fd < 0) {
1451                         dma_fence_put(fence);
1452                         return fd;
1453                 }
1454
1455                 sync_file = sync_file_create(fence);
1456                 dma_fence_put(fence);
1457                 if (!sync_file) {
1458                         put_unused_fd(fd);
1459                         return -ENOMEM;
1460                 }
1461
1462                 fd_install(fd, sync_file->file);
1463                 info->out.handle = fd;
1464                 return 0;
1465
1466         default:
1467                 return -EINVAL;
1468         }
1469 }
1470
1471 /**
1472  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1473  *
1474  * @adev: amdgpu device
1475  * @filp: file private
1476  * @wait: wait parameters
1477  * @fences: array of drm_amdgpu_fence
1478  */
1479 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1480                                      struct drm_file *filp,
1481                                      union drm_amdgpu_wait_fences *wait,
1482                                      struct drm_amdgpu_fence *fences)
1483 {
1484         uint32_t fence_count = wait->in.fence_count;
1485         unsigned int i;
1486         long r = 1;
1487
1488         for (i = 0; i < fence_count; i++) {
1489                 struct dma_fence *fence;
1490                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1491
1492                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1493                 if (IS_ERR(fence))
1494                         return PTR_ERR(fence);
1495                 else if (!fence)
1496                         continue;
1497
1498                 r = dma_fence_wait_timeout(fence, true, timeout);
1499                 dma_fence_put(fence);
1500                 if (r < 0)
1501                         return r;
1502
1503                 if (r == 0)
1504                         break;
1505
1506                 if (fence->error)
1507                         return fence->error;
1508         }
1509
1510         memset(wait, 0, sizeof(*wait));
1511         wait->out.status = (r > 0);
1512
1513         return 0;
1514 }
1515
1516 /**
1517  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1518  *
1519  * @adev: amdgpu device
1520  * @filp: file private
1521  * @wait: wait parameters
1522  * @fences: array of drm_amdgpu_fence
1523  */
1524 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1525                                     struct drm_file *filp,
1526                                     union drm_amdgpu_wait_fences *wait,
1527                                     struct drm_amdgpu_fence *fences)
1528 {
1529         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1530         uint32_t fence_count = wait->in.fence_count;
1531         uint32_t first = ~0;
1532         struct dma_fence **array;
1533         unsigned int i;
1534         long r;
1535
1536         /* Prepare the fence array */
1537         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1538
1539         if (array == NULL)
1540                 return -ENOMEM;
1541
1542         for (i = 0; i < fence_count; i++) {
1543                 struct dma_fence *fence;
1544
1545                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1546                 if (IS_ERR(fence)) {
1547                         r = PTR_ERR(fence);
1548                         goto err_free_fence_array;
1549                 } else if (fence) {
1550                         array[i] = fence;
1551                 } else { /* NULL, the fence has been already signaled */
1552                         r = 1;
1553                         first = i;
1554                         goto out;
1555                 }
1556         }
1557
1558         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1559                                        &first);
1560         if (r < 0)
1561                 goto err_free_fence_array;
1562
1563 out:
1564         memset(wait, 0, sizeof(*wait));
1565         wait->out.status = (r > 0);
1566         wait->out.first_signaled = first;
1567
1568         if (first < fence_count && array[first])
1569                 r = array[first]->error;
1570         else
1571                 r = 0;
1572
1573 err_free_fence_array:
1574         for (i = 0; i < fence_count; i++)
1575                 dma_fence_put(array[i]);
1576         kfree(array);
1577
1578         return r;
1579 }
1580
1581 /**
1582  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1583  *
1584  * @dev: drm device
1585  * @data: data from userspace
1586  * @filp: file private
1587  */
1588 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1589                                 struct drm_file *filp)
1590 {
1591         struct amdgpu_device *adev = dev->dev_private;
1592         union drm_amdgpu_wait_fences *wait = data;
1593         uint32_t fence_count = wait->in.fence_count;
1594         struct drm_amdgpu_fence *fences_user;
1595         struct drm_amdgpu_fence *fences;
1596         int r;
1597
1598         /* Get the fences from userspace */
1599         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1600                         GFP_KERNEL);
1601         if (fences == NULL)
1602                 return -ENOMEM;
1603
1604         fences_user = u64_to_user_ptr(wait->in.fences);
1605         if (copy_from_user(fences, fences_user,
1606                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1607                 r = -EFAULT;
1608                 goto err_free_fences;
1609         }
1610
1611         if (wait->in.wait_all)
1612                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1613         else
1614                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1615
1616 err_free_fences:
1617         kfree(fences);
1618
1619         return r;
1620 }
1621
1622 /**
1623  * amdgpu_cs_find_bo_va - find bo_va for VM address
1624  *
1625  * @parser: command submission parser context
1626  * @addr: VM address
1627  * @bo: resulting BO of the mapping found
1628  *
1629  * Search the buffer objects in the command submission context for a certain
1630  * virtual memory address. Returns allocation structure when found, NULL
1631  * otherwise.
1632  */
1633 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1634                            uint64_t addr, struct amdgpu_bo **bo,
1635                            struct amdgpu_bo_va_mapping **map)
1636 {
1637         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1638         struct ttm_operation_ctx ctx = { false, false };
1639         struct amdgpu_vm *vm = &fpriv->vm;
1640         struct amdgpu_bo_va_mapping *mapping;
1641         int r;
1642
1643         addr /= AMDGPU_GPU_PAGE_SIZE;
1644
1645         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1646         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1647                 return -EINVAL;
1648
1649         *bo = mapping->bo_va->base.bo;
1650         *map = mapping;
1651
1652         /* Double check that the BO is reserved by this CS */
1653         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1654                 return -EINVAL;
1655
1656         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1657                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1658                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1659                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1660                 if (r)
1661                         return r;
1662         }
1663
1664         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1665 }