1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_CPU_CACHE_ALIASING
6 select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A)
7 select ARCH_HAS_BINFMT_FLAT if !MMU
8 select ARCH_HAS_CPU_FINALIZE_INIT
9 select ARCH_HAS_CURRENT_STACK_POINTER
10 select ARCH_HAS_GIGANTIC_PAGE
11 select ARCH_HAS_GCOV_PROFILE_ALL
12 select ARCH_HAS_PTE_SPECIAL
13 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
14 select ARCH_HIBERNATION_POSSIBLE if MMU
15 select ARCH_MIGHT_HAVE_PC_PARPORT
16 select ARCH_WANT_IPC_PARSE_VERSION
17 select CPU_NO_EFFICIENT_FFS
18 select DMA_DECLARE_COHERENT
19 select GENERIC_ATOMIC64
20 select GENERIC_CMOS_UPDATE if SH_SH03 || SH_DREAMCAST
21 select GENERIC_IDLE_POLL_SETUP
22 select GENERIC_IRQ_SHOW
23 select GENERIC_LIB_ASHLDI3
24 select GENERIC_LIB_ASHRDI3
25 select GENERIC_LIB_LSHRDI3
26 select GENERIC_PCI_IOMAP if PCI
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
29 select GUP_GET_PXX_LOW_HIGH if X2TLB
30 select HAS_IOPORT if HAS_IOPORT_MAP
31 select GENERIC_IOREMAP if MMU
32 select HAVE_ARCH_AUDITSYSCALL
34 select HAVE_ARCH_SECCOMP_FILTER
35 select HAVE_ARCH_TRACEHOOK
36 select HAVE_DEBUG_BUGVERBOSE
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DYNAMIC_FTRACE
39 select HAVE_GUP_FAST if MMU
40 select HAVE_FUNCTION_GRAPH_TRACER
41 select HAVE_FUNCTION_TRACER
42 select HAVE_FTRACE_MCOUNT_RECORD
43 select HAVE_HW_BREAKPOINT
44 select HAVE_IOREMAP_PROT if MMU && !X2TLB
45 select HAVE_KERNEL_BZIP2
46 select HAVE_KERNEL_GZIP
47 select HAVE_KERNEL_LZMA
48 select HAVE_KERNEL_LZO
51 select HAVE_KRETPROBES
52 select HAVE_MIXED_BREAKPOINTS_REGS
53 select HAVE_MOD_ARCH_SPECIFIC if DWARF_UNWINDER
55 select HAVE_PATA_PLATFORM
56 select HAVE_PERF_EVENTS
57 select HAVE_REGS_AND_STACK_ACCESS_API
59 select HAVE_SOFTIRQ_ON_OWN_STACK if IRQSTACKS
60 select HAVE_STACKPROTECTOR
61 select HAVE_SYSCALL_TRACEPOINTS
62 select IRQ_FORCED_THREADING
63 select LOCK_MM_AND_FIND_VMA
64 select MODULES_USE_ELF_RELA
65 select NEED_SG_DMA_LENGTH
66 select NO_DMA if !MMU && !DMA_COHERENT
67 select NO_GENERIC_PCI_IOPORT_MAP if PCI
70 select PCI_DOMAINS if PCI
72 select PERF_USE_VMALLOC
75 select TRACE_IRQFLAGS_SUPPORT
77 The SuperH is a RISC processor targeted for use in embedded systems
78 and consumer electronics; it was also used in the Sega Dreamcast
79 gaming console. The SuperH port has a home page at
80 <http://www.linux-sh.org/>.
86 config GENERIC_HWEIGHT
89 config GENERIC_CALIBRATE_DELAY
92 config GENERIC_LOCKBREAK
94 depends on SMP && PREEMPTION
96 config ARCH_SUSPEND_POSSIBLE
99 config ARCH_HIBERNATION_POSSIBLE
102 config SYS_SUPPORTS_APM_EMULATION
104 select ARCH_SUSPEND_POSSIBLE
106 config SYS_SUPPORTS_SMP
109 config SYS_SUPPORTS_NUMA
112 config STACKTRACE_SUPPORT
115 config LOCKDEP_SUPPORT
118 config ARCH_HAS_ILOG2_U32
121 config ARCH_HAS_ILOG2_U64
126 depends on !SH_SHMIN && !SH_HP6XX && !SH_SOLUTION_ENGINE && \
138 config DMA_NONCOHERENT
139 def_bool !NO_DMA && !DMA_COHERENT
140 select ARCH_HAS_DMA_PREP_COHERENT
141 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
142 select DMA_DIRECT_REMAP
144 config PGTABLE_LEVELS
160 select UNCACHED_MAPPING
166 select OF_EARLY_FLATTREE
170 select CPU_HAS_INTEVT
173 select SYS_SUPPORTS_SH_TMU
177 select ARCH_SUPPORTS_HUGETLBFS if MMU
178 select CPU_HAS_INTEVT
180 select CPU_HAS_FPU if !CPU_SH4AL_DSP
182 select SYS_SUPPORTS_SH_TMU
199 select SYS_SUPPORTS_SMP
200 select SYS_SUPPORTS_NUMA
204 select ARCH_SUSPEND_POSSIBLE
208 depends on CPU_SH4 || CPU_SH4A
213 prompt "Processor sub-type selection"
219 # SH-2 Processor Support
221 config CPU_SUBTYPE_SH7619
222 bool "Support SH7619 processor"
224 select SYS_SUPPORTS_SH_CMT
226 config CPU_SUBTYPE_J2
227 bool "Support J2 processor"
229 select SYS_SUPPORTS_SMP
230 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
232 # SH-2A Processor Support
234 config CPU_SUBTYPE_SH7201
235 bool "Support SH7201 processor"
238 select SYS_SUPPORTS_SH_MTU2
240 config CPU_SUBTYPE_SH7203
241 bool "Support SH7203 processor"
244 select SYS_SUPPORTS_SH_CMT
245 select SYS_SUPPORTS_SH_MTU2
248 config CPU_SUBTYPE_SH7206
249 bool "Support SH7206 processor"
251 select SYS_SUPPORTS_SH_CMT
252 select SYS_SUPPORTS_SH_MTU2
254 config CPU_SUBTYPE_SH7263
255 bool "Support SH7263 processor"
258 select SYS_SUPPORTS_SH_CMT
259 select SYS_SUPPORTS_SH_MTU2
261 config CPU_SUBTYPE_SH7264
262 bool "Support SH7264 processor"
265 select SYS_SUPPORTS_SH_CMT
266 select SYS_SUPPORTS_SH_MTU2
269 config CPU_SUBTYPE_SH7269
270 bool "Support SH7269 processor"
273 select SYS_SUPPORTS_SH_CMT
274 select SYS_SUPPORTS_SH_MTU2
277 config CPU_SUBTYPE_MXG
278 bool "Support MX-G processor"
280 select SYS_SUPPORTS_SH_MTU2
282 Select MX-G if running on an R8A03022BG part.
284 # SH-3 Processor Support
286 config CPU_SUBTYPE_SH7705
287 bool "Support SH7705 processor"
290 config CPU_SUBTYPE_SH7706
291 bool "Support SH7706 processor"
294 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
296 config CPU_SUBTYPE_SH7707
297 bool "Support SH7707 processor"
300 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
302 config CPU_SUBTYPE_SH7708
303 bool "Support SH7708 processor"
306 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
307 if you have a 100 Mhz SH-3 HD6417708R CPU.
309 config CPU_SUBTYPE_SH7709
310 bool "Support SH7709 processor"
313 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
315 config CPU_SUBTYPE_SH7710
316 bool "Support SH7710 processor"
320 Select SH7710 if you have a SH3-DSP SH7710 CPU.
322 config CPU_SUBTYPE_SH7712
323 bool "Support SH7712 processor"
327 Select SH7712 if you have a SH3-DSP SH7712 CPU.
329 config CPU_SUBTYPE_SH7720
330 bool "Support SH7720 processor"
333 select SYS_SUPPORTS_SH_CMT
334 select USB_OHCI_SH if USB_OHCI_HCD
337 Select SH7720 if you have a SH3-DSP SH7720 CPU.
339 config CPU_SUBTYPE_SH7721
340 bool "Support SH7721 processor"
343 select SYS_SUPPORTS_SH_CMT
344 select USB_OHCI_SH if USB_OHCI_HCD
346 Select SH7721 if you have a SH3-DSP SH7721 CPU.
348 # SH-4 Processor Support
350 config CPU_SUBTYPE_SH7750
351 bool "Support SH7750 processor"
354 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
356 config CPU_SUBTYPE_SH7091
357 bool "Support SH7091 processor"
360 Select SH7091 if you have an SH-4 based Sega device (such as
361 the Dreamcast, Naomi, and Naomi 2).
363 config CPU_SUBTYPE_SH7750R
364 bool "Support SH7750R processor"
367 config CPU_SUBTYPE_SH7750S
368 bool "Support SH7750S processor"
371 config CPU_SUBTYPE_SH7751
372 bool "Support SH7751 processor"
375 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
376 or if you have a HD6417751R CPU.
378 config CPU_SUBTYPE_SH7751R
379 bool "Support SH7751R processor"
382 config CPU_SUBTYPE_SH7760
383 bool "Support SH7760 processor"
386 # SH-4A Processor Support
388 config CPU_SUBTYPE_SH7723
389 bool "Support SH7723 processor"
393 select ARCH_SPARSEMEM_ENABLE
394 select SYS_SUPPORTS_SH_CMT
397 Select SH7723 if you have an SH-MobileR2 CPU.
399 config CPU_SUBTYPE_SH7724
400 bool "Support SH7724 processor"
404 select ARCH_SPARSEMEM_ENABLE
405 select SYS_SUPPORTS_SH_CMT
408 Select SH7724 if you have an SH-MobileR2R CPU.
410 config CPU_SUBTYPE_SH7734
411 bool "Support SH7734 processor"
416 Select SH7734 if you have a SH4A SH7734 CPU.
418 config CPU_SUBTYPE_SH7757
419 bool "Support SH7757 processor"
424 Select SH7757 if you have a SH4A SH7757 CPU.
426 config CPU_SUBTYPE_SH7763
427 bool "Support SH7763 processor"
429 select USB_OHCI_SH if USB_OHCI_HCD
431 Select SH7763 if you have a SH4A SH7763(R5S77631) CPU.
433 config CPU_SUBTYPE_SH7770
434 bool "Support SH7770 processor"
437 config CPU_SUBTYPE_SH7780
438 bool "Support SH7780 processor"
441 config CPU_SUBTYPE_SH7785
442 bool "Support SH7785 processor"
445 select ARCH_SPARSEMEM_ENABLE
446 select SYS_SUPPORTS_NUMA
449 config CPU_SUBTYPE_SH7786
450 bool "Support SH7786 processor"
453 select CPU_HAS_PTEAEX
454 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
455 select USB_OHCI_SH if USB_OHCI_HCD
456 select USB_EHCI_SH if USB_EHCI_HCD
459 config CPU_SUBTYPE_SHX3
460 bool "Support SH-X3 processor"
463 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
467 # SH4AL-DSP Processor Support
469 config CPU_SUBTYPE_SH7343
470 bool "Support SH7343 processor"
473 select SYS_SUPPORTS_SH_CMT
475 config CPU_SUBTYPE_SH7722
476 bool "Support SH7722 processor"
480 select ARCH_SPARSEMEM_ENABLE
481 select SYS_SUPPORTS_NUMA
482 select SYS_SUPPORTS_SH_CMT
485 config CPU_SUBTYPE_SH7366
486 bool "Support SH7366 processor"
490 select ARCH_SPARSEMEM_ENABLE
491 select SYS_SUPPORTS_NUMA
492 select SYS_SUPPORTS_SH_CMT
496 source "arch/sh/mm/Kconfig"
498 source "arch/sh/Kconfig.cpu"
500 source "arch/sh/boards/Kconfig"
502 menu "Timer and clock configuration"
505 int "Peripheral clock frequency (in Hz)"
506 depends on SH_CLK_CPG_LEGACY
507 default "31250000" if CPU_SUBTYPE_SH7619
508 default "33333333" if CPU_SUBTYPE_SH7770 || \
509 CPU_SUBTYPE_SH7760 || \
510 CPU_SUBTYPE_SH7705 || \
511 CPU_SUBTYPE_SH7203 || \
512 CPU_SUBTYPE_SH7206 || \
513 CPU_SUBTYPE_SH7263 || \
515 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
518 This option is used to specify the peripheral clock frequency.
519 This is necessary for determining the reference clock value on
520 platforms lacking an RTC.
525 config SH_CLK_CPG_LEGACY
526 depends on SH_CLK_CPG
527 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
528 !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \
529 !CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 && \
534 menu "CPU Frequency scaling"
535 source "drivers/cpufreq/Kconfig"
538 source "arch/sh/drivers/Kconfig"
542 menu "Kernel features"
544 source "kernel/Kconfig.hz"
546 config ARCH_SUPPORTS_KEXEC
549 config ARCH_SUPPORTS_CRASH_DUMP
550 def_bool BROKEN_ON_SMP
552 config ARCH_SUPPORTS_KEXEC_JUMP
555 config PHYSICAL_START
556 hex "Physical address where the kernel is loaded" if (EXPERT || CRASH_DUMP)
559 This gives the physical address where the kernel is loaded
560 and is ordinarily the same as MEMORY_START.
562 Different values are primarily used in the case of kexec on panic
563 where the fail safe kernel needs to run at a different address
564 than the panic-ed kernel.
567 bool "Symmetric multi-processing support"
568 depends on SYS_SUPPORTS_SMP
570 This enables support for systems with more than one CPU. If you have
571 a system with only one CPU, say N. If you have a system with more
574 If you say N here, the kernel will run on uni- and multiprocessor
575 machines, but will use only one CPU of a multiprocessor machine. If
576 you say Y here, the kernel will run on many, but not all,
577 uniprocessor machines. On a uniprocessor machine, the kernel
578 will run faster if you say N here.
580 People using multiprocessor machines who say Y here should also say
581 Y to "Enhanced Real Time Clock Support", below.
583 See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO
584 available at <https://www.tldp.org/docs.html#howto>.
586 If you don't know what to do here, say N.
589 int "Maximum number of CPUs (2-32)"
592 default "4" if CPU_SUBTYPE_SHX3
595 This allows you to specify the maximum number of CPUs which this
596 kernel will support. The maximum supported value is 32 and the
597 minimum value which makes sense is 2.
599 This is purely to save memory - each supported CPU adds
600 approximately eight kilobytes to the kernel image.
603 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
606 Say Y here to experiment with turning CPUs off and on. CPUs
607 can be controlled through /sys/devices/system/cpu.
613 This enables support for gUSA (general UserSpace Atomicity).
614 This is the default implementation for both UP and non-ll/sc
615 CPUs, and is used by the libc, amongst others.
617 For additional information, design information can be found
618 in <http://lc.linux.or.jp/lc2002/papers/niibe0919p.pdf>.
620 This should only be disabled for special cases where alternate
621 atomicity implementations exist.
624 bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)"
625 depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A)
627 Enabling this option will allow the kernel to implement some
628 atomic operations using a software implementation of load-locked/
629 store-conditional (LLSC). On machines which do not have hardware
630 LLSC, this should be more efficient than the other alternative of
631 disabling interrupts around the atomic sequence.
633 config HW_PERF_EVENTS
634 bool "Enable hardware performance counter support for perf events"
635 depends on PERF_EVENTS && CPU_HAS_PMU
638 Enable hardware performance counter support for perf events. If
639 disabled, perf events will use software events only.
641 source "drivers/sh/Kconfig"
647 config USE_BUILTIN_DTB
648 bool "Use builtin DTB"
650 depends on SH_DEVICE_TREE
652 Link a device tree blob for particular hardware into the kernel,
653 suppressing use of the DTB pointer provided by the bootloader.
654 This option should only be used with legacy bootloaders that are
655 not capable of providing a DTB to the kernel, or for experimental
656 hardware without stable device tree bindings.
658 config BUILTIN_DTB_SOURCE
659 string "Source file for builtin DTB"
661 depends on USE_BUILTIN_DTB
663 Base name (without suffix, relative to arch/sh/boot/dts) for the
664 a DTS file that will be used to produce the DTB linked into the
667 config ZERO_PAGE_OFFSET
669 default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \
670 SH_7751_SOLUTION_ENGINE
671 default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
672 default "0x00002000" if PAGE_SIZE_8KB
675 This sets the default offset of zero page.
677 config BOOT_LINK_OFFSET
679 default "0x00210000" if SH_SHMIN
680 default "0x00810000" if SH_7780_SOLUTION_ENGINE
681 default "0x009e0000" if SH_TITAN
682 default "0x01800000" if SH_SDK7780
683 default "0x02000000" if SH_EDOSK7760
686 This option allows you to set the link address offset of the zImage.
687 This can be useful if you are on a board which has a small amount of
692 default "0x00001000" if PAGE_SIZE_4KB
693 default "0x00002000" if PAGE_SIZE_8KB
694 default "0x00004000" if PAGE_SIZE_16KB
695 default "0x00010000" if PAGE_SIZE_64KB
698 config ROMIMAGE_MMCIF
699 bool "Include MMCIF loader in romImage (EXPERIMENTAL)"
700 depends on CPU_SUBTYPE_SH7724
702 Say Y here to include experimental MMCIF loading code in
703 romImage. With this enabled it is possible to write the romImage
704 kernel image to an MMC card and boot the kernel straight from
705 the reset vector. At reset the processor Mask ROM will load the
706 first part of the romImage which in turn loads the rest the kernel
707 image to RAM using the MMCIF hardware block.
710 prompt "Kernel command line"
711 default CMDLINE_OVERWRITE
713 Setting this option allows the kernel command line arguments
716 config CMDLINE_OVERWRITE
717 bool "Overwrite bootloader kernel arguments"
719 Given string will overwrite any arguments passed in by
722 config CMDLINE_EXTEND
723 bool "Extend bootloader kernel arguments"
725 Given string will be concatenated with arguments passed in
728 config CMDLINE_FROM_BOOTLOADER
729 bool "Use bootloader kernel arguments"
731 Uses the command-line options passed by the boot loader.
736 string "Kernel command line arguments string"
737 depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND
738 default "console=ttySC1,115200"
745 bool "Maple Bus support"
746 depends on SH_DREAMCAST
748 The Maple Bus is SEGA's serial communication bus for peripherals
749 on the Dreamcast. Without this bus support you won't be able to
750 get your Dreamcast keyboard etc to work, so most users
751 probably want to say 'Y' here, unless you are only using the
752 Dreamcast with a serial line terminal or a remote network
757 menu "Power management options (EXPERIMENTAL)"
759 source "kernel/power/Kconfig"
761 source "drivers/cpuidle/Kconfig"