drivers/gpu/drm/bridge/ite-it66121.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2020 BayLibre, SAS
   4  * Author: Phong LE <[email protected]>
   5  * Copyright (C) 2018-2019, Artem Mygaiev
   6  * Copyright (C) 2017, Fresco Logic, Incorporated.
   7  *
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/device.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/i2c.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/property.h>
  16 #include <linux/regmap.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/pinctrl/consumer.h>
  20 #include <linux/regulator/consumer.h>
  21
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_bridge.h>
  24 #include <drm/drm_crtc_helper.h>
  25 #include <drm/drm_edid.h>
  26 #include <drm/drm_modes.h>
  27 #include <drm/drm_print.h>
  28 #include <drm/drm_probe_helper.h>
  29
  30 #include <sound/hdmi-codec.h>
  31
  32 #define IT66121_VENDOR_ID0_REG                  0x00
  33 #define IT66121_VENDOR_ID1_REG                  0x01
  34 #define IT66121_DEVICE_ID0_REG                  0x02
  35 #define IT66121_DEVICE_ID1_REG                  0x03
  36
  37 #define IT66121_VENDOR_ID0                      0x54
  38 #define IT66121_VENDOR_ID1                      0x49
  39 #define IT66121_DEVICE_ID0                      0x12
  40 #define IT66121_DEVICE_ID1                      0x06
  41 #define IT66121_REVISION_MASK                   GENMASK(7, 4)
  42 #define IT66121_DEVICE_ID1_MASK                 GENMASK(3, 0)
  43
  44 #define IT66121_MASTER_SEL_REG                  0x10
  45 #define IT66121_MASTER_SEL_HOST                 BIT(0)
  46
  47 #define IT66121_AFE_DRV_REG                     0x61
  48 #define IT66121_AFE_DRV_RST                     BIT(4)
  49 #define IT66121_AFE_DRV_PWD                     BIT(5)
  50
  51 #define IT66121_INPUT_MODE_REG                  0x70
  52 #define IT66121_INPUT_MODE_RGB                  (0 << 6)
  53 #define IT66121_INPUT_MODE_YUV422               BIT(6)
  54 #define IT66121_INPUT_MODE_YUV444               (2 << 6)
  55 #define IT66121_INPUT_MODE_CCIR656              BIT(4)
  56 #define IT66121_INPUT_MODE_SYNCEMB              BIT(3)
  57 #define IT66121_INPUT_MODE_DDR                  BIT(2)
  58
  59 #define IT66121_INPUT_CSC_REG                   0x72
  60 #define IT66121_INPUT_CSC_ENDITHER              BIT(7)
  61 #define IT66121_INPUT_CSC_ENUDFILTER            BIT(6)
  62 #define IT66121_INPUT_CSC_DNFREE_GO             BIT(5)
  63 #define IT66121_INPUT_CSC_RGB_TO_YUV            0x02
  64 #define IT66121_INPUT_CSC_YUV_TO_RGB            0x03
  65 #define IT66121_INPUT_CSC_NO_CONV               0x00
  66
  67 #define IT66121_AFE_XP_REG                      0x62
  68 #define IT66121_AFE_XP_GAINBIT                  BIT(7)
  69 #define IT66121_AFE_XP_PWDPLL                   BIT(6)
  70 #define IT66121_AFE_XP_ENI                      BIT(5)
  71 #define IT66121_AFE_XP_ENO                      BIT(4)
  72 #define IT66121_AFE_XP_RESETB                   BIT(3)
  73 #define IT66121_AFE_XP_PWDI                     BIT(2)
  74
  75 #define IT66121_AFE_IP_REG                      0x64
  76 #define IT66121_AFE_IP_GAINBIT                  BIT(7)
  77 #define IT66121_AFE_IP_PWDPLL                   BIT(6)
  78 #define IT66121_AFE_IP_CKSEL_05                 (0 << 4)
  79 #define IT66121_AFE_IP_CKSEL_1                  BIT(4)
  80 #define IT66121_AFE_IP_CKSEL_2                  (2 << 4)
  81 #define IT66121_AFE_IP_CKSEL_2OR4               (3 << 4)
  82 #define IT66121_AFE_IP_ER0                      BIT(3)
  83 #define IT66121_AFE_IP_RESETB                   BIT(2)
  84 #define IT66121_AFE_IP_ENC                      BIT(1)
  85 #define IT66121_AFE_IP_EC1                      BIT(0)
  86
  87 #define IT66121_AFE_XP_EC1_REG                  0x68
  88 #define IT66121_AFE_XP_EC1_LOWCLK               BIT(4)
  89
  90 #define IT66121_SW_RST_REG                      0x04
  91 #define IT66121_SW_RST_REF                      BIT(5)
  92 #define IT66121_SW_RST_AREF                     BIT(4)
  93 #define IT66121_SW_RST_VID                      BIT(3)
  94 #define IT66121_SW_RST_AUD                      BIT(2)
  95 #define IT66121_SW_RST_HDCP                     BIT(0)
  96
  97 #define IT66121_DDC_COMMAND_REG                 0x15
  98 #define IT66121_DDC_COMMAND_BURST_READ          0x0
  99 #define IT66121_DDC_COMMAND_EDID_READ           0x3
 100 #define IT66121_DDC_COMMAND_FIFO_CLR            0x9
 101 #define IT66121_DDC_COMMAND_SCL_PULSE           0xA
 102 #define IT66121_DDC_COMMAND_ABORT               0xF
 103
 104 #define IT66121_HDCP_REG                        0x20
 105 #define IT66121_HDCP_CPDESIRED                  BIT(0)
 106 #define IT66121_HDCP_EN1P1FEAT                  BIT(1)
 107
 108 #define IT66121_INT_STATUS1_REG                 0x06
 109 #define IT66121_INT_STATUS1_AUD_OVF             BIT(7)
 110 #define IT66121_INT_STATUS1_DDC_NOACK           BIT(5)
 111 #define IT66121_INT_STATUS1_DDC_FIFOERR         BIT(4)
 112 #define IT66121_INT_STATUS1_DDC_BUSHANG         BIT(2)
 113 #define IT66121_INT_STATUS1_RX_SENS_STATUS      BIT(1)
 114 #define IT66121_INT_STATUS1_HPD_STATUS          BIT(0)
 115
 116 #define IT66121_DDC_HEADER_REG                  0x11
 117 #define IT66121_DDC_HEADER_HDCP                 0x74
 118 #define IT66121_DDC_HEADER_EDID                 0xA0
 119
 120 #define IT66121_DDC_OFFSET_REG                  0x12
 121 #define IT66121_DDC_BYTE_REG                    0x13
 122 #define IT66121_DDC_SEGMENT_REG                 0x14
 123 #define IT66121_DDC_RD_FIFO_REG                 0x17
 124
 125 #define IT66121_CLK_BANK_REG                    0x0F
 126 #define IT66121_CLK_BANK_PWROFF_RCLK            BIT(6)
 127 #define IT66121_CLK_BANK_PWROFF_ACLK            BIT(5)
 128 #define IT66121_CLK_BANK_PWROFF_TXCLK           BIT(4)
 129 #define IT66121_CLK_BANK_PWROFF_CRCLK           BIT(3)
 130 #define IT66121_CLK_BANK_0                      0
 131 #define IT66121_CLK_BANK_1                      1
 132
 133 #define IT66121_INT_REG                         0x05
 134 #define IT66121_INT_ACTIVE_HIGH                 BIT(7)
 135 #define IT66121_INT_OPEN_DRAIN                  BIT(6)
 136 #define IT66121_INT_TX_CLK_OFF                  BIT(0)
 137
 138 #define IT66121_INT_MASK1_REG                   0x09
 139 #define IT66121_INT_MASK1_AUD_OVF               BIT(7)
 140 #define IT66121_INT_MASK1_DDC_NOACK             BIT(5)
 141 #define IT66121_INT_MASK1_DDC_FIFOERR           BIT(4)
 142 #define IT66121_INT_MASK1_DDC_BUSHANG           BIT(2)
 143 #define IT66121_INT_MASK1_RX_SENS               BIT(1)
 144 #define IT66121_INT_MASK1_HPD                   BIT(0)
 145
 146 #define IT66121_INT_CLR1_REG                    0x0C
 147 #define IT66121_INT_CLR1_PKTACP                 BIT(7)
 148 #define IT66121_INT_CLR1_PKTNULL                BIT(6)
 149 #define IT66121_INT_CLR1_PKTGEN                 BIT(5)
 150 #define IT66121_INT_CLR1_KSVLISTCHK             BIT(4)
 151 #define IT66121_INT_CLR1_AUTHDONE               BIT(3)
 152 #define IT66121_INT_CLR1_AUTHFAIL               BIT(2)
 153 #define IT66121_INT_CLR1_RX_SENS                BIT(1)
 154 #define IT66121_INT_CLR1_HPD                    BIT(0)
 155
 156 #define IT66121_AV_MUTE_REG                     0xC1
 157 #define IT66121_AV_MUTE_ON                      BIT(0)
 158 #define IT66121_AV_MUTE_BLUESCR                 BIT(1)
 159
 160 #define IT66121_PKT_CTS_CTRL_REG                0xC5
 161 #define IT66121_PKT_CTS_CTRL_SEL                BIT(1)
 162
 163 #define IT66121_PKT_GEN_CTRL_REG                0xC6
 164 #define IT66121_PKT_GEN_CTRL_ON                 BIT(0)
 165 #define IT66121_PKT_GEN_CTRL_RPT                BIT(1)
 166
 167 #define IT66121_AVIINFO_DB1_REG                 0x158
 168 #define IT66121_AVIINFO_DB2_REG                 0x159
 169 #define IT66121_AVIINFO_DB3_REG                 0x15A
 170 #define IT66121_AVIINFO_DB4_REG                 0x15B
 171 #define IT66121_AVIINFO_DB5_REG                 0x15C
 172 #define IT66121_AVIINFO_CSUM_REG                0x15D
 173 #define IT66121_AVIINFO_DB6_REG                 0x15E
 174 #define IT66121_AVIINFO_DB7_REG                 0x15F
 175 #define IT66121_AVIINFO_DB8_REG                 0x160
 176 #define IT66121_AVIINFO_DB9_REG                 0x161
 177 #define IT66121_AVIINFO_DB10_REG                0x162
 178 #define IT66121_AVIINFO_DB11_REG                0x163
 179 #define IT66121_AVIINFO_DB12_REG                0x164
 180 #define IT66121_AVIINFO_DB13_REG                0x165
 181
 182 #define IT66121_AVI_INFO_PKT_REG                0xCD
 183 #define IT66121_AVI_INFO_PKT_ON                 BIT(0)
 184 #define IT66121_AVI_INFO_PKT_RPT                BIT(1)
 185
 186 #define IT66121_HDMI_MODE_REG                   0xC0
 187 #define IT66121_HDMI_MODE_HDMI                  BIT(0)
 188
 189 #define IT66121_SYS_STATUS_REG                  0x0E
 190 #define IT66121_SYS_STATUS_ACTIVE_IRQ           BIT(7)
 191 #define IT66121_SYS_STATUS_HPDETECT             BIT(6)
 192 #define IT66121_SYS_STATUS_SENDECTECT           BIT(5)
 193 #define IT66121_SYS_STATUS_VID_STABLE           BIT(4)
 194 #define IT66121_SYS_STATUS_AUD_CTS_CLR          BIT(1)
 195 #define IT66121_SYS_STATUS_CLEAR_IRQ            BIT(0)
 196
 197 #define IT66121_DDC_STATUS_REG                  0x16
 198 #define IT66121_DDC_STATUS_TX_DONE              BIT(7)
 199 #define IT66121_DDC_STATUS_ACTIVE               BIT(6)
 200 #define IT66121_DDC_STATUS_NOACK                BIT(5)
 201 #define IT66121_DDC_STATUS_WAIT_BUS             BIT(4)
 202 #define IT66121_DDC_STATUS_ARBI_LOSE            BIT(3)
 203 #define IT66121_DDC_STATUS_FIFO_FULL            BIT(2)
 204 #define IT66121_DDC_STATUS_FIFO_EMPTY           BIT(1)
 205 #define IT66121_DDC_STATUS_FIFO_VALID           BIT(0)
 206
 207 #define IT66121_EDID_SLEEP_US                   20000
 208 #define IT66121_EDID_TIMEOUT_US                 200000
 209 #define IT66121_EDID_FIFO_SIZE                  32
 210
 211 #define IT66121_CLK_CTRL0_REG                   0x58
 212 #define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING    BIT(4)
 213 #define IT66121_CLK_CTRL0_EXT_MCLK_MASK         GENMASK(3, 2)
 214 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS        (0 << 2)
 215 #define IT66121_CLK_CTRL0_EXT_MCLK_256FS        BIT(2)
 216 #define IT66121_CLK_CTRL0_EXT_MCLK_512FS        (2 << 2)
 217 #define IT66121_CLK_CTRL0_EXT_MCLK_1024FS       (3 << 2)
 218 #define IT66121_CLK_CTRL0_AUTO_IPCLK            BIT(0)
 219 #define IT66121_CLK_STATUS1_REG                 0x5E
 220 #define IT66121_CLK_STATUS2_REG                 0x5F
 221
 222 #define IT66121_AUD_CTRL0_REG                   0xE0
 223 #define IT66121_AUD_SWL                         (3 << 6)
 224 #define IT66121_AUD_16BIT                       (0 << 6)
 225 #define IT66121_AUD_18BIT                       BIT(6)
 226 #define IT66121_AUD_20BIT                       (2 << 6)
 227 #define IT66121_AUD_24BIT                       (3 << 6)
 228 #define IT66121_AUD_SPDIFTC                     BIT(5)
 229 #define IT66121_AUD_SPDIF                       BIT(4)
 230 #define IT66121_AUD_I2S                         (0 << 4)
 231 #define IT66121_AUD_EN_I2S3                     BIT(3)
 232 #define IT66121_AUD_EN_I2S2                     BIT(2)
 233 #define IT66121_AUD_EN_I2S1                     BIT(1)
 234 #define IT66121_AUD_EN_I2S0                     BIT(0)
 235 #define IT66121_AUD_CTRL0_AUD_SEL               BIT(4)
 236
 237 #define IT66121_AUD_CTRL1_REG                   0xE1
 238 #define IT66121_AUD_FIFOMAP_REG                 0xE2
 239 #define IT66121_AUD_CTRL3_REG                   0xE3
 240 #define IT66121_AUD_SRCVALID_FLAT_REG           0xE4
 241 #define IT66121_AUD_FLAT_SRC0                   BIT(4)
 242 #define IT66121_AUD_FLAT_SRC1                   BIT(5)
 243 #define IT66121_AUD_FLAT_SRC2                   BIT(6)
 244 #define IT66121_AUD_FLAT_SRC3                   BIT(7)
 245 #define IT66121_AUD_HDAUDIO_REG                 0xE5
 246
 247 #define IT66121_AUD_PKT_CTS0_REG                0x130
 248 #define IT66121_AUD_PKT_CTS1_REG                0x131
 249 #define IT66121_AUD_PKT_CTS2_REG                0x132
 250 #define IT66121_AUD_PKT_N0_REG                  0x133
 251 #define IT66121_AUD_PKT_N1_REG                  0x134
 252 #define IT66121_AUD_PKT_N2_REG                  0x135
 253
 254 #define IT66121_AUD_CHST_MODE_REG               0x191
 255 #define IT66121_AUD_CHST_CAT_REG                0x192
 256 #define IT66121_AUD_CHST_SRCNUM_REG             0x193
 257 #define IT66121_AUD_CHST_CHTNUM_REG             0x194
 258 #define IT66121_AUD_CHST_CA_FS_REG              0x198
 259 #define IT66121_AUD_CHST_OFS_WL_REG             0x199
 260
 261 #define IT66121_AUD_PKT_CTS_CNT0_REG            0x1A0
 262 #define IT66121_AUD_PKT_CTS_CNT1_REG            0x1A1
 263 #define IT66121_AUD_PKT_CTS_CNT2_REG            0x1A2
 264
 265 #define IT66121_AUD_FS_22P05K                   0x4
 266 #define IT66121_AUD_FS_44P1K                    0x0
 267 #define IT66121_AUD_FS_88P2K                    0x8
 268 #define IT66121_AUD_FS_176P4K                   0xC
 269 #define IT66121_AUD_FS_24K                      0x6
 270 #define IT66121_AUD_FS_48K                      0x2
 271 #define IT66121_AUD_FS_96K                      0xA
 272 #define IT66121_AUD_FS_192K                     0xE
 273 #define IT66121_AUD_FS_768K                     0x9
 274 #define IT66121_AUD_FS_32K                      0x3
 275 #define IT66121_AUD_FS_OTHER                    0x1
 276
 277 #define IT66121_AUD_SWL_21BIT                   0xD
 278 #define IT66121_AUD_SWL_24BIT                   0xB
 279 #define IT66121_AUD_SWL_23BIT                   0x9
 280 #define IT66121_AUD_SWL_22BIT                   0x5
 281 #define IT66121_AUD_SWL_20BIT                   0x3
 282 #define IT66121_AUD_SWL_17BIT                   0xC
 283 #define IT66121_AUD_SWL_19BIT                   0x8
 284 #define IT66121_AUD_SWL_18BIT                   0x4
 285 #define IT66121_AUD_SWL_16BIT                   0x2
 286 #define IT66121_AUD_SWL_NOT_INDICATED           0x0
 287
 288 #define IT66121_VENDOR_ID0                      0x54
 289 #define IT66121_VENDOR_ID1                      0x49
 290 #define IT66121_DEVICE_ID0                      0x12
 291 #define IT66121_DEVICE_ID1                      0x06
 292 #define IT66121_DEVICE_MASK                     0x0F
 293 #define IT66121_AFE_CLK_HIGH                    80000 /* Khz */
 294
 295 struct it66121_ctx {
 296         struct regmap *regmap;
 297         struct drm_bridge bridge;
 298         struct drm_bridge *next_bridge;
 299         struct drm_connector *connector;
 300         struct device *dev;
 301         struct gpio_desc *gpio_reset;
 302         struct i2c_client *client;
 303         struct regulator_bulk_data supplies[3];
 304         u32 bus_width;
 305         struct mutex lock; /* Protects fields below and device registers */
 306         struct hdmi_avi_infoframe hdmi_avi_infoframe;
 307         struct {
 308                 struct platform_device *pdev;
 309                 u8 ch_enable;
 310                 u8 fs;
 311                 u8 swl;
 312                 bool auto_cts;
 313         } audio;
 314 };
 315
 316 static const struct regmap_range_cfg it66121_regmap_banks[] = {
 317         {
 318                 .name = "it66121",
 319                 .range_min = 0x00,
 320                 .range_max = 0x1FF,
 321                 .selector_reg = IT66121_CLK_BANK_REG,
 322                 .selector_mask = 0x1,
 323                 .selector_shift = 0,
 324                 .window_start = 0x00,
 325                 .window_len = 0x100,
 326         },
 327 };
 328
 329 static const struct regmap_config it66121_regmap_config = {
 330         .val_bits = 8,
 331         .reg_bits = 8,
 332         .max_register = 0x1FF,
 333         .ranges = it66121_regmap_banks,
 334         .num_ranges = ARRAY_SIZE(it66121_regmap_banks),
 335 };
 336
 337 static void it66121_hw_reset(struct it66121_ctx *ctx)
 338 {
 339         gpiod_set_value(ctx->gpio_reset, 1);
 340         msleep(20);
 341         gpiod_set_value(ctx->gpio_reset, 0);
 342 }
 343
 344 static inline int ite66121_power_on(struct it66121_ctx *ctx)
 345 {
 346         return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 347 }
 348
 349 static inline int ite66121_power_off(struct it66121_ctx *ctx)
 350 {
 351         return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 352 }
 353
 354 static inline int it66121_preamble_ddc(struct it66121_ctx *ctx)
 355 {
 356         return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST);
 357 }
 358
 359 static inline int it66121_fire_afe(struct it66121_ctx *ctx)
 360 {
 361         return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0);
 362 }
 363
 364 /* TOFIX: Handle YCbCr Input & Output */
 365 static int it66121_configure_input(struct it66121_ctx *ctx)
 366 {
 367         int ret;
 368         u8 mode = IT66121_INPUT_MODE_RGB;
 369
 370         if (ctx->bus_width == 12)
 371                 mode |= IT66121_INPUT_MODE_DDR;
 372
 373         ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode);
 374         if (ret)
 375                 return ret;
 376
 377         return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV);
 378 }
 379
 380 /**
 381  * it66121_configure_afe() - Configure the analog front end
 382  * @ctx: it66121_ctx object
 383  * @mode: mode to configure
 384  *
 385  * RETURNS:
 386  * zero if success, a negative error code otherwise.
 387  */
 388 static int it66121_configure_afe(struct it66121_ctx *ctx,
 389                                  const struct drm_display_mode *mode)
 390 {
 391         int ret;
 392
 393         ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG,
 394                            IT66121_AFE_DRV_RST);
 395         if (ret)
 396                 return ret;
 397
 398         if (mode->clock > IT66121_AFE_CLK_HIGH) {
 399                 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 400                                         IT66121_AFE_XP_GAINBIT |
 401                                         IT66121_AFE_XP_ENO,
 402                                         IT66121_AFE_XP_GAINBIT);
 403                 if (ret)
 404                         return ret;
 405
 406                 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 407                                         IT66121_AFE_IP_GAINBIT |
 408                                         IT66121_AFE_IP_ER0 |
 409                                         IT66121_AFE_IP_EC1,
 410                                         IT66121_AFE_IP_GAINBIT);
 411                 if (ret)
 412                         return ret;
 413
 414                 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
 415                                         IT66121_AFE_XP_EC1_LOWCLK, 0x80);
 416                 if (ret)
 417                         return ret;
 418         } else {
 419                 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 420                                         IT66121_AFE_XP_GAINBIT |
 421                                         IT66121_AFE_XP_ENO,
 422                                         IT66121_AFE_XP_ENO);
 423                 if (ret)
 424                         return ret;
 425
 426                 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 427                                         IT66121_AFE_IP_GAINBIT |
 428                                         IT66121_AFE_IP_ER0 |
 429                                         IT66121_AFE_IP_EC1, IT66121_AFE_IP_ER0 |
 430                                         IT66121_AFE_IP_EC1);
 431                 if (ret)
 432                         return ret;
 433
 434                 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
 435                                         IT66121_AFE_XP_EC1_LOWCLK,
 436                                         IT66121_AFE_XP_EC1_LOWCLK);
 437                 if (ret)
 438                         return ret;
 439         }
 440
 441         /* Clear reset flags */
 442         ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
 443                                 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0);
 444         if (ret)
 445                 return ret;
 446
 447         return it66121_fire_afe(ctx);
 448 }
 449
 450 static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx)
 451 {
 452         int ret, val;
 453         u32 busy = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS |
 454                    IT66121_DDC_STATUS_ARBI_LOSE;
 455
 456         ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, true,
 457                                        IT66121_EDID_SLEEP_US, IT66121_EDID_TIMEOUT_US);
 458         if (ret)
 459                 return ret;
 460
 461         if (val & busy)
 462                 return -EAGAIN;
 463
 464         return 0;
 465 }
 466
 467 static int it66121_clear_ddc_fifo(struct it66121_ctx *ctx)
 468 {
 469         int ret;
 470
 471         ret = it66121_preamble_ddc(ctx);
 472         if (ret)
 473                 return ret;
 474
 475         return regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
 476                             IT66121_DDC_COMMAND_FIFO_CLR);
 477 }
 478
 479 static int it66121_abort_ddc_ops(struct it66121_ctx *ctx)
 480 {
 481         int ret;
 482         unsigned int swreset, cpdesire;
 483
 484         ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset);
 485         if (ret)
 486                 return ret;
 487
 488         ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire);
 489         if (ret)
 490                 return ret;
 491
 492         ret = regmap_write(ctx->regmap, IT66121_HDCP_REG,
 493                            cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF));
 494         if (ret)
 495                 return ret;
 496
 497         ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG,
 498                            (swreset | IT66121_SW_RST_HDCP));
 499         if (ret)
 500                 return ret;
 501
 502         ret = it66121_preamble_ddc(ctx);
 503         if (ret)
 504                 return ret;
 505
 506         ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
 507                            IT66121_DDC_COMMAND_ABORT);
 508         if (ret)
 509                 return ret;
 510
 511         return it66121_wait_ddc_ready(ctx);
 512 }
 513
 514 static int it66121_get_edid_block(void *context, u8 *buf,
 515                                   unsigned int block, size_t len)
 516 {
 517         struct it66121_ctx *ctx = context;
 518         unsigned int val;
 519         int remain = len;
 520         int offset = 0;
 521         int ret, cnt;
 522
 523         offset = (block % 2) * len;
 524         block = block / 2;
 525
 526         ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
 527         if (ret)
 528                 return ret;
 529
 530         if (val & IT66121_INT_STATUS1_DDC_BUSHANG) {
 531                 ret = it66121_abort_ddc_ops(ctx);
 532                 if (ret)
 533                         return ret;
 534         }
 535
 536         ret = it66121_clear_ddc_fifo(ctx);
 537         if (ret)
 538                 return ret;
 539
 540         while (remain > 0) {
 541                 cnt = (remain > IT66121_EDID_FIFO_SIZE) ?
 542                                 IT66121_EDID_FIFO_SIZE : remain;
 543                 ret = it66121_preamble_ddc(ctx);
 544                 if (ret)
 545                         return ret;
 546
 547                 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
 548                                    IT66121_DDC_COMMAND_FIFO_CLR);
 549                 if (ret)
 550                         return ret;
 551
 552                 ret = it66121_wait_ddc_ready(ctx);
 553                 if (ret)
 554                         return ret;
 555
 556                 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
 557                 if (ret)
 558                         return ret;
 559
 560                 if (val & IT66121_INT_STATUS1_DDC_BUSHANG) {
 561                         ret = it66121_abort_ddc_ops(ctx);
 562                         if (ret)
 563                                 return ret;
 564                 }
 565
 566                 ret = it66121_preamble_ddc(ctx);
 567                 if (ret)
 568                         return ret;
 569
 570                 ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG,
 571                                    IT66121_DDC_HEADER_EDID);
 572                 if (ret)
 573                         return ret;
 574
 575                 ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset);
 576                 if (ret)
 577                         return ret;
 578
 579                 ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt);
 580                 if (ret)
 581                         return ret;
 582
 583                 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block);
 584                 if (ret)
 585                         return ret;
 586
 587                 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
 588                                    IT66121_DDC_COMMAND_EDID_READ);
 589                 if (ret)
 590                         return ret;
 591
 592                 offset += cnt;
 593                 remain -= cnt;
 594
 595                 /* Per programming manual, sleep here before emptying the FIFO */
 596                 msleep(20);
 597
 598                 ret = it66121_wait_ddc_ready(ctx);
 599                 if (ret)
 600                         return ret;
 601
 602                 do {
 603                         ret = regmap_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, &val);
 604                         if (ret)
 605                                 return ret;
 606                         *(buf++) = val;
 607                         cnt--;
 608                 } while (cnt > 0);
 609         }
 610
 611         return 0;
 612 }
 613
 614 static bool it66121_is_hpd_detect(struct it66121_ctx *ctx)
 615 {
 616         int val;
 617
 618         if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val))
 619                 return false;
 620
 621         return val & IT66121_SYS_STATUS_HPDETECT;
 622 }
 623
 624 static int it66121_bridge_attach(struct drm_bridge *bridge,
 625                                  enum drm_bridge_attach_flags flags)
 626 {
 627         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 628         int ret;
 629
 630         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
 631                 return -EINVAL;
 632
 633         ret = drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags);
 634         if (ret)
 635                 return ret;
 636
 637         ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
 638                                 IT66121_CLK_BANK_PWROFF_RCLK, 0);
 639         if (ret)
 640                 return ret;
 641
 642         ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG,
 643                                 IT66121_INT_TX_CLK_OFF, 0);
 644         if (ret)
 645                 return ret;
 646
 647         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
 648                                 IT66121_AFE_DRV_PWD, 0);
 649         if (ret)
 650                 return ret;
 651
 652         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 653                                 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0);
 654         if (ret)
 655                 return ret;
 656
 657         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 658                                 IT66121_AFE_IP_PWDPLL, 0);
 659         if (ret)
 660                 return ret;
 661
 662         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
 663                                 IT66121_AFE_DRV_RST, 0);
 664         if (ret)
 665                 return ret;
 666
 667         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 668                                 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB);
 669         if (ret)
 670                 return ret;
 671
 672         ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 673                                 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB);
 674         if (ret)
 675                 return ret;
 676
 677         ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
 678                                 IT66121_SW_RST_REF,
 679                                 IT66121_SW_RST_REF);
 680         if (ret)
 681                 return ret;
 682
 683         /* Per programming manual, sleep here for bridge to settle */
 684         msleep(50);
 685
 686         /* Start interrupts */
 687         return regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
 688                                  IT66121_INT_MASK1_DDC_NOACK |
 689                                  IT66121_INT_MASK1_DDC_FIFOERR |
 690                                  IT66121_INT_MASK1_DDC_BUSHANG, 0);
 691 }
 692
 693 static int it66121_set_mute(struct it66121_ctx *ctx, bool mute)
 694 {
 695         int ret;
 696         unsigned int val = 0;
 697
 698         if (mute)
 699                 val = IT66121_AV_MUTE_ON;
 700
 701         ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val);
 702         if (ret)
 703                 return ret;
 704
 705         return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG,
 706                             IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT);
 707 }
 708
 709 #define MAX_OUTPUT_SEL_FORMATS  1
 710
 711 static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
 712                                                       struct drm_bridge_state *bridge_state,
 713                                                       struct drm_crtc_state *crtc_state,
 714                                                       struct drm_connector_state *conn_state,
 715                                                       unsigned int *num_output_fmts)
 716 {
 717         u32 *output_fmts;
 718
 719         output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
 720                               GFP_KERNEL);
 721         if (!output_fmts)
 722                 return NULL;
 723
 724         /* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */
 725         output_fmts[0] =  MEDIA_BUS_FMT_RGB888_1X24;
 726         *num_output_fmts = 1;
 727
 728         return output_fmts;
 729 }
 730
 731 #define MAX_INPUT_SEL_FORMATS   1
 732
 733 static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 734                                                      struct drm_bridge_state *bridge_state,
 735                                                      struct drm_crtc_state *crtc_state,
 736                                                      struct drm_connector_state *conn_state,
 737                                                      u32 output_fmt,
 738                                                      unsigned int *num_input_fmts)
 739 {
 740         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 741         u32 *input_fmts;
 742
 743         *num_input_fmts = 0;
 744
 745         input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
 746                              GFP_KERNEL);
 747         if (!input_fmts)
 748                 return NULL;
 749
 750         if (ctx->bus_width == 12)
 751                 /* IT66121FN Datasheet specifies Little-Endian ordering */
 752                 input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
 753         else
 754                 /* TOFIX support more input bus formats in 24bit width */
 755                 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
 756         *num_input_fmts = 1;
 757
 758         return input_fmts;
 759 }
 760
 761 static void it66121_bridge_enable(struct drm_bridge *bridge,
 762                                   struct drm_bridge_state *bridge_state)
 763 {
 764         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 765         struct drm_atomic_state *state = bridge_state->base.state;
 766
 767         ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
 768
 769         it66121_set_mute(ctx, false);
 770 }
 771
 772 static void it66121_bridge_disable(struct drm_bridge *bridge,
 773                                    struct drm_bridge_state *bridge_state)
 774 {
 775         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 776
 777         it66121_set_mute(ctx, true);
 778
 779         ctx->connector = NULL;
 780 }
 781
 782 static
 783 void it66121_bridge_mode_set(struct drm_bridge *bridge,
 784                              const struct drm_display_mode *mode,
 785                              const struct drm_display_mode *adjusted_mode)
 786 {
 787         int ret, i;
 788         u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
 789         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 790         const u16 aviinfo_reg[HDMI_AVI_INFOFRAME_SIZE] = {
 791                 IT66121_AVIINFO_DB1_REG,
 792                 IT66121_AVIINFO_DB2_REG,
 793                 IT66121_AVIINFO_DB3_REG,
 794                 IT66121_AVIINFO_DB4_REG,
 795                 IT66121_AVIINFO_DB5_REG,
 796                 IT66121_AVIINFO_DB6_REG,
 797                 IT66121_AVIINFO_DB7_REG,
 798                 IT66121_AVIINFO_DB8_REG,
 799                 IT66121_AVIINFO_DB9_REG,
 800                 IT66121_AVIINFO_DB10_REG,
 801                 IT66121_AVIINFO_DB11_REG,
 802                 IT66121_AVIINFO_DB12_REG,
 803                 IT66121_AVIINFO_DB13_REG
 804         };
 805
 806         mutex_lock(&ctx->lock);
 807
 808         hdmi_avi_infoframe_init(&ctx->hdmi_avi_infoframe);
 809
 810         ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector,
 811                                                        adjusted_mode);
 812         if (ret) {
 813                 DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret);
 814                 goto unlock;
 815         }
 816
 817         ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf));
 818         if (ret < 0) {
 819                 DRM_ERROR("Failed to pack infoframe: %d\n", ret);
 820                 goto unlock;
 821         }
 822
 823         /* Write new AVI infoframe packet */
 824         for (i = 0; i < HDMI_AVI_INFOFRAME_SIZE; i++) {
 825                 if (regmap_write(ctx->regmap, aviinfo_reg[i], buf[i + HDMI_INFOFRAME_HEADER_SIZE]))
 826                         goto unlock;
 827         }
 828         if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3]))
 829                 goto unlock;
 830
 831         /* Enable AVI infoframe */
 832         if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG,
 833                          IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT))
 834                 goto unlock;
 835
 836         /* Set TX mode to HDMI */
 837         if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI))
 838                 goto unlock;
 839
 840         if (regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
 841                               IT66121_CLK_BANK_PWROFF_TXCLK, IT66121_CLK_BANK_PWROFF_TXCLK))
 842                 goto unlock;
 843
 844         if (it66121_configure_input(ctx))
 845                 goto unlock;
 846
 847         if (it66121_configure_afe(ctx, adjusted_mode))
 848                 goto unlock;
 849
 850         regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, IT66121_CLK_BANK_PWROFF_TXCLK, 0);
 851
 852 unlock:
 853         mutex_unlock(&ctx->lock);
 854 }
 855
 856 static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge,
 857                                                       const struct drm_display_info *info,
 858                                                       const struct drm_display_mode *mode)
 859 {
 860         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 861         unsigned long max_clock;
 862
 863         max_clock = (ctx->bus_width == 12) ? 74250 : 148500;
 864
 865         if (mode->clock > max_clock)
 866                 return MODE_CLOCK_HIGH;
 867
 868         if (mode->clock < 25000)
 869                 return MODE_CLOCK_LOW;
 870
 871         return MODE_OK;
 872 }
 873
 874 static enum drm_connector_status it66121_bridge_detect(struct drm_bridge *bridge)
 875 {
 876         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 877
 878         return it66121_is_hpd_detect(ctx) ? connector_status_connected
 879                                           : connector_status_disconnected;
 880 }
 881
 882 static void it66121_bridge_hpd_enable(struct drm_bridge *bridge)
 883 {
 884         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 885         int ret;
 886
 887         ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0);
 888         if (ret)
 889                 dev_err(ctx->dev, "failed to enable HPD IRQ\n");
 890 }
 891
 892 static void it66121_bridge_hpd_disable(struct drm_bridge *bridge)
 893 {
 894         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 895         int ret;
 896
 897         ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
 898                                 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD);
 899         if (ret)
 900                 dev_err(ctx->dev, "failed to disable HPD IRQ\n");
 901 }
 902
 903 static struct edid *it66121_bridge_get_edid(struct drm_bridge *bridge,
 904                                             struct drm_connector *connector)
 905 {
 906         struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 907         struct edid *edid;
 908
 909         mutex_lock(&ctx->lock);
 910         edid = drm_do_get_edid(connector, it66121_get_edid_block, ctx);
 911         mutex_unlock(&ctx->lock);
 912
 913         return edid;
 914 }
 915
 916 static const struct drm_bridge_funcs it66121_bridge_funcs = {
 917         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 918         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 919         .atomic_reset = drm_atomic_helper_bridge_reset,
 920         .attach = it66121_bridge_attach,
 921         .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts,
 922         .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts,
 923         .atomic_enable = it66121_bridge_enable,
 924         .atomic_disable = it66121_bridge_disable,
 925         .mode_set = it66121_bridge_mode_set,
 926         .mode_valid = it66121_bridge_mode_valid,
 927         .detect = it66121_bridge_detect,
 928         .get_edid = it66121_bridge_get_edid,
 929         .hpd_enable = it66121_bridge_hpd_enable,
 930         .hpd_disable = it66121_bridge_hpd_disable,
 931 };
 932
 933 static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id)
 934 {
 935         int ret;
 936         unsigned int val;
 937         struct it66121_ctx *ctx = dev_id;
 938         struct device *dev = ctx->dev;
 939         enum drm_connector_status status;
 940         bool event = false;
 941
 942         mutex_lock(&ctx->lock);
 943
 944         ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val);
 945         if (ret)
 946                 goto unlock;
 947
 948         if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ))
 949                 goto unlock;
 950
 951         ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
 952         if (ret) {
 953                 dev_err(dev, "Cannot read STATUS1_REG %d\n", ret);
 954         } else {
 955                 if (val & IT66121_INT_STATUS1_DDC_FIFOERR)
 956                         it66121_clear_ddc_fifo(ctx);
 957                 if (val & (IT66121_INT_STATUS1_DDC_BUSHANG |
 958                            IT66121_INT_STATUS1_DDC_NOACK))
 959                         it66121_abort_ddc_ops(ctx);
 960                 if (val & IT66121_INT_STATUS1_HPD_STATUS) {
 961                         regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG,
 962                                           IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD);
 963
 964                         status = it66121_is_hpd_detect(ctx) ? connector_status_connected
 965                                                             : connector_status_disconnected;
 966
 967                         event = true;
 968                 }
 969         }
 970
 971         regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG,
 972                           IT66121_SYS_STATUS_CLEAR_IRQ,
 973                           IT66121_SYS_STATUS_CLEAR_IRQ);
 974
 975 unlock:
 976         mutex_unlock(&ctx->lock);
 977
 978         if (event)
 979                 drm_bridge_hpd_notify(&ctx->bridge, status);
 980
 981         return IRQ_HANDLED;
 982 }
 983
 984 static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[])
 985 {
 986         int ret;
 987
 988         ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C);
 989         if (ret)
 990                 return ret;
 991
 992         ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]);
 993         if (ret)
 994                 return ret;
 995
 996         ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F);
 997         if (ret)
 998                 return ret;
 999
1000         ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG,
1001                            (iec60958_chstat[2] >> 4) & 0x0F);
1002         if (ret)
1003                 return ret;
1004
1005         ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]);
1006         if (ret)
1007                 return ret;
1008
1009         return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]);
1010 }
1011
1012 static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl)
1013 {
1014         int ret;
1015         unsigned int audio_enable = 0;
1016         unsigned int audio_format = 0;
1017
1018         switch (audio_swl) {
1019         case 16:
1020                 audio_enable |= IT66121_AUD_16BIT;
1021                 break;
1022         case 18:
1023                 audio_enable |= IT66121_AUD_18BIT;
1024                 break;
1025         case 20:
1026                 audio_enable |= IT66121_AUD_20BIT;
1027                 break;
1028         case 24:
1029         default:
1030                 audio_enable |= IT66121_AUD_24BIT;
1031                 break;
1032         }
1033
1034         audio_format |= 0x40;
1035         switch (audio_src_num) {
1036         case 4:
1037                 audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1038                                 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0;
1039                 break;
1040         case 3:
1041                 audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 |
1042                                 IT66121_AUD_EN_I2S0;
1043                 break;
1044         case 2:
1045                 audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0;
1046                 break;
1047         case 1:
1048         default:
1049                 audio_format &= ~0x40;
1050                 audio_enable |= IT66121_AUD_EN_I2S0;
1051                 break;
1052         }
1053
1054         audio_format |= 0x01;
1055         ctx->audio.ch_enable = audio_enable;
1056
1057         ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0);
1058         if (ret)
1059                 return ret;
1060
1061         ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format);
1062         if (ret)
1063                 return ret;
1064
1065         ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4);
1066         if (ret)
1067                 return ret;
1068
1069         ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00);
1070         if (ret)
1071                 return ret;
1072
1073         ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00);
1074         if (ret)
1075                 return ret;
1076
1077         return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00);
1078 }
1079
1080 static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs)
1081 {
1082         int ret;
1083         unsigned int n;
1084
1085         switch (fs) {
1086         case IT66121_AUD_FS_32K:
1087                 n = 4096;
1088                 break;
1089         case IT66121_AUD_FS_44P1K:
1090                 n = 6272;
1091                 break;
1092         case IT66121_AUD_FS_48K:
1093                 n = 6144;
1094                 break;
1095         case IT66121_AUD_FS_88P2K:
1096                 n = 12544;
1097                 break;
1098         case IT66121_AUD_FS_96K:
1099                 n = 12288;
1100                 break;
1101         case IT66121_AUD_FS_176P4K:
1102                 n = 25088;
1103                 break;
1104         case IT66121_AUD_FS_192K:
1105                 n = 24576;
1106                 break;
1107         case IT66121_AUD_FS_768K:
1108                 n = 24576;
1109                 break;
1110         default:
1111                 n = 6144;
1112                 break;
1113         }
1114
1115         ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF));
1116         if (ret)
1117                 return ret;
1118
1119         ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF));
1120         if (ret)
1121                 return ret;
1122
1123         ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF));
1124         if (ret)
1125                 return ret;
1126
1127         if (ctx->audio.auto_cts) {
1128                 u8 loop_cnt = 255;
1129                 u8 cts_stable_cnt = 0;
1130                 unsigned int sum_cts = 0;
1131                 unsigned int cts = 0;
1132                 unsigned int last_cts = 0;
1133                 unsigned int diff;
1134                 unsigned int val;
1135
1136                 while (loop_cnt--) {
1137                         msleep(30);
1138                         regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val);
1139                         cts = val << 12;
1140                         regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val);
1141                         cts |= val << 4;
1142                         regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val);
1143                         cts |= val >> 4;
1144                         if (cts == 0) {
1145                                 continue;
1146                         } else {
1147                                 if (last_cts > cts)
1148                                         diff = last_cts - cts;
1149                                 else
1150                                         diff = cts - last_cts;
1151                                 last_cts = cts;
1152                                 if (diff < 5) {
1153                                         cts_stable_cnt++;
1154                                         sum_cts += cts;
1155                                 } else {
1156                                         cts_stable_cnt = 0;
1157                                         sum_cts = 0;
1158                                         continue;
1159                                 }
1160
1161                                 if (cts_stable_cnt >= 32) {
1162                                         last_cts = (sum_cts >> 5);
1163                                         break;
1164                                 }
1165                         }
1166                 }
1167
1168                 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF));
1169                 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF));
1170                 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F));
1171         }
1172
1173         ret = regmap_write(ctx->regmap, 0xF8, 0xC3);
1174         if (ret)
1175                 return ret;
1176
1177         ret = regmap_write(ctx->regmap, 0xF8, 0xA5);
1178         if (ret)
1179                 return ret;
1180
1181         if (ctx->audio.auto_cts) {
1182                 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG,
1183                                         IT66121_PKT_CTS_CTRL_SEL,
1184                                         1);
1185         } else {
1186                 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG,
1187                                         IT66121_PKT_CTS_CTRL_SEL,
1188                                         0);
1189         }
1190
1191         if (ret)
1192                 return ret;
1193
1194         return regmap_write(ctx->regmap, 0xF8, 0xFF);
1195 }
1196
1197 static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable)
1198 {
1199         int ret;
1200
1201         if (enable) {
1202                 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
1203                                         IT66121_SW_RST_AUD | IT66121_SW_RST_AREF,
1204                                         0);
1205                 if (ret)
1206                         return ret;
1207
1208                 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1209                                         IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1210                                         IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0,
1211                                         ctx->audio.ch_enable);
1212         } else {
1213                 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1214                                         IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1215                                         IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0,
1216                                         ctx->audio.ch_enable & 0xF0);
1217                 if (ret)
1218                         return ret;
1219
1220                 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
1221                                         IT66121_SW_RST_AUD | IT66121_SW_RST_AREF,
1222                                         IT66121_SW_RST_AUD | IT66121_SW_RST_AREF);
1223         }
1224
1225         return ret;
1226 }
1227
1228 static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable)
1229 {
1230         int ret;
1231
1232         if (enable) {
1233                 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0);
1234                 if (ret)
1235                         return ret;
1236
1237                 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable);
1238         } else {
1239                 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0);
1240         }
1241
1242         return ret;
1243 }
1244
1245 static int it66121_audio_hw_params(struct device *dev, void *data,
1246                                    struct hdmi_codec_daifmt *daifmt,
1247                                    struct hdmi_codec_params *params)
1248 {
1249         u8 fs;
1250         u8 swl;
1251         int ret;
1252         struct it66121_ctx *ctx = dev_get_drvdata(dev);
1253         static u8 iec60958_chstat[5];
1254         unsigned int channels = params->channels;
1255         unsigned int sample_rate = params->sample_rate;
1256         unsigned int sample_width = params->sample_width;
1257
1258         mutex_lock(&ctx->lock);
1259         dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__,
1260                 daifmt->fmt, sample_rate, sample_width, channels);
1261
1262         switch (daifmt->fmt) {
1263         case HDMI_I2S:
1264                 dev_dbg(dev, "Using HDMI I2S\n");
1265                 break;
1266         default:
1267                 dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt);
1268                 ret = -EINVAL;
1269                 goto out;
1270         }
1271
1272         // Set audio clock recovery (N/CTS)
1273         ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG,
1274                            IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING |
1275                            IT66121_CLK_CTRL0_EXT_MCLK_256FS |
1276                            IT66121_CLK_CTRL0_AUTO_IPCLK);
1277         if (ret)
1278                 goto out;
1279
1280         ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1281                                 IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection
1282         if (ret)
1283                 goto out;
1284
1285         switch (sample_rate) {
1286         case 44100L:
1287                 fs = IT66121_AUD_FS_44P1K;
1288                 break;
1289         case 88200L:
1290                 fs = IT66121_AUD_FS_88P2K;
1291                 break;
1292         case 176400L:
1293                 fs = IT66121_AUD_FS_176P4K;
1294                 break;
1295         case 32000L:
1296                 fs = IT66121_AUD_FS_32K;
1297                 break;
1298         case 48000L:
1299                 fs = IT66121_AUD_FS_48K;
1300                 break;
1301         case 96000L:
1302                 fs = IT66121_AUD_FS_96K;
1303                 break;
1304         case 192000L:
1305                 fs = IT66121_AUD_FS_192K;
1306                 break;
1307         case 768000L:
1308                 fs = IT66121_AUD_FS_768K;
1309                 break;
1310         default:
1311                 fs = IT66121_AUD_FS_48K;
1312                 break;
1313         }
1314
1315         ctx->audio.fs = fs;
1316         ret = it661221_set_ncts(ctx, fs);
1317         if (ret) {
1318                 dev_err(dev, "Failed to set N/CTS: %d\n", ret);
1319                 goto out;
1320         }
1321
1322         // Set audio format register (except audio channel enable)
1323         ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width);
1324         if (ret) {
1325                 dev_err(dev, "Failed to set LPCM audio: %d\n", ret);
1326                 goto out;
1327         }
1328
1329         // Set audio channel status
1330         iec60958_chstat[0] = 0;
1331         if ((channels + 1) / 2 == 1)
1332                 iec60958_chstat[0] |= 0x1;
1333         iec60958_chstat[0] &= ~(1 << 1);
1334         iec60958_chstat[1] = 0;
1335         iec60958_chstat[2] = (channels + 1) / 2;
1336         iec60958_chstat[2] |= (channels << 4) & 0xF0;
1337         iec60958_chstat[3] = fs;
1338
1339         switch (sample_width) {
1340         case 21L:
1341                 swl = IT66121_AUD_SWL_21BIT;
1342                 break;
1343         case 24L:
1344                 swl = IT66121_AUD_SWL_24BIT;
1345                 break;
1346         case 23L:
1347                 swl = IT66121_AUD_SWL_23BIT;
1348                 break;
1349         case 22L:
1350                 swl = IT66121_AUD_SWL_22BIT;
1351                 break;
1352         case 20L:
1353                 swl = IT66121_AUD_SWL_20BIT;
1354                 break;
1355         case 17L:
1356                 swl = IT66121_AUD_SWL_17BIT;
1357                 break;
1358         case 19L:
1359                 swl = IT66121_AUD_SWL_19BIT;
1360                 break;
1361         case 18L:
1362                 swl = IT66121_AUD_SWL_18BIT;
1363                 break;
1364         case 16L:
1365                 swl = IT66121_AUD_SWL_16BIT;
1366                 break;
1367         default:
1368                 swl = IT66121_AUD_SWL_NOT_INDICATED;
1369                 break;
1370         }
1371
1372         iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl;
1373         ret = it661221_set_chstat(ctx, iec60958_chstat);
1374         if (ret) {
1375                 dev_err(dev, "Failed to set channel status: %d\n", ret);
1376                 goto out;
1377         }
1378
1379         // Enable audio channel enable while input clock stable (if SPDIF).
1380         ret = it661221_audio_ch_enable(ctx, true);
1381         if (ret) {
1382                 dev_err(dev, "Failed to enable audio channel: %d\n", ret);
1383                 goto out;
1384         }
1385
1386         ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
1387                                 IT66121_INT_MASK1_AUD_OVF,
1388                                 0);
1389         if (ret)
1390                 goto out;
1391
1392         dev_dbg(dev, "HDMI audio enabled.\n");
1393 out:
1394         mutex_unlock(&ctx->lock);
1395
1396         return ret;
1397 }
1398
1399 static int it66121_audio_startup(struct device *dev, void *data)
1400 {
1401         int ret;
1402         struct it66121_ctx *ctx = dev_get_drvdata(dev);
1403
1404         dev_dbg(dev, "%s\n", __func__);
1405
1406         mutex_lock(&ctx->lock);
1407         ret = it661221_audio_output_enable(ctx, true);
1408         if (ret)
1409                 dev_err(dev, "Failed to enable audio output: %d\n", ret);
1410
1411         mutex_unlock(&ctx->lock);
1412
1413         return ret;
1414 }
1415
1416 static void it66121_audio_shutdown(struct device *dev, void *data)
1417 {
1418         int ret;
1419         struct it66121_ctx *ctx = dev_get_drvdata(dev);
1420
1421         dev_dbg(dev, "%s\n", __func__);
1422
1423         mutex_lock(&ctx->lock);
1424         ret = it661221_audio_output_enable(ctx, false);
1425         if (ret)
1426                 dev_err(dev, "Failed to disable audio output: %d\n", ret);
1427
1428         mutex_unlock(&ctx->lock);
1429 }
1430
1431 static int it66121_audio_mute(struct device *dev, void *data,
1432                               bool enable, int direction)
1433 {
1434         int ret;
1435         struct it66121_ctx *ctx = dev_get_drvdata(dev);
1436
1437         dev_dbg(dev, "%s: enable=%s, direction=%d\n",
1438                 __func__, enable ? "true" : "false", direction);
1439
1440         mutex_lock(&ctx->lock);
1441
1442         if (enable) {
1443                 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG,
1444                                         IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1445                                         IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3,
1446                                         IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1447                                         IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3);
1448         } else {
1449                 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG,
1450                                         IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1451                                         IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3,
1452                                         0);
1453         }
1454
1455         mutex_unlock(&ctx->lock);
1456
1457         return ret;
1458 }
1459
1460 static int it66121_audio_get_eld(struct device *dev, void *data,
1461                                  u8 *buf, size_t len)
1462 {
1463         struct it66121_ctx *ctx = dev_get_drvdata(dev);
1464
1465         mutex_lock(&ctx->lock);
1466
1467         memcpy(buf, ctx->connector->eld,
1468                min(sizeof(ctx->connector->eld), len));
1469
1470         mutex_unlock(&ctx->lock);
1471
1472         return 0;
1473 }
1474
1475 static const struct hdmi_codec_ops it66121_audio_codec_ops = {
1476         .hw_params = it66121_audio_hw_params,
1477         .audio_startup = it66121_audio_startup,
1478         .audio_shutdown = it66121_audio_shutdown,
1479         .mute_stream = it66121_audio_mute,
1480         .get_eld = it66121_audio_get_eld,
1481         .no_capture_mute = 1,
1482 };
1483
1484 static int it66121_audio_codec_init(struct it66121_ctx *ctx, struct device *dev)
1485 {
1486         struct hdmi_codec_pdata codec_data = {
1487                 .ops = &it66121_audio_codec_ops,
1488                 .i2s = 1, /* Only i2s support for now */
1489                 .spdif = 0,
1490                 .max_i2s_channels = 8,
1491         };
1492
1493         dev_dbg(dev, "%s\n", __func__);
1494
1495         if (!of_property_read_bool(dev->of_node, "#sound-dai-cells")) {
1496                 dev_info(dev, "No \"#sound-dai-cells\", no audio\n");
1497                 return 0;
1498         }
1499
1500         ctx->audio.pdev = platform_device_register_data(dev,
1501                                                         HDMI_CODEC_DRV_NAME,
1502                                                         PLATFORM_DEVID_AUTO,
1503                                                         &codec_data,
1504                                                         sizeof(codec_data));
1505
1506         if (IS_ERR(ctx->audio.pdev)) {
1507                 dev_err(dev, "Failed to initialize HDMI audio codec: %d\n",
1508                         PTR_ERR_OR_ZERO(ctx->audio.pdev));
1509         }
1510
1511         return PTR_ERR_OR_ZERO(ctx->audio.pdev);
1512 }
1513
1514 static int it66121_probe(struct i2c_client *client,
1515                          const struct i2c_device_id *id)
1516 {
1517         u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 };
1518         struct device_node *ep;
1519         int ret;
1520         struct it66121_ctx *ctx;
1521         struct device *dev = &client->dev;
1522
1523         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1524                 dev_err(dev, "I2C check functionality failed.\n");
1525                 return -ENXIO;
1526         }
1527
1528         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1529         if (!ctx)
1530                 return -ENOMEM;
1531
1532         ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
1533         if (!ep)
1534                 return -EINVAL;
1535
1536         ctx->dev = dev;
1537         ctx->client = client;
1538
1539         of_property_read_u32(ep, "bus-width", &ctx->bus_width);
1540         of_node_put(ep);
1541
1542         if (ctx->bus_width != 12 && ctx->bus_width != 24)
1543                 return -EINVAL;
1544
1545         ep = of_graph_get_remote_node(dev->of_node, 1, -1);
1546         if (!ep) {
1547                 dev_err(ctx->dev, "The endpoint is unconnected\n");
1548                 return -EINVAL;
1549         }
1550
1551         if (!of_device_is_available(ep)) {
1552                 of_node_put(ep);
1553                 dev_err(ctx->dev, "The remote device is disabled\n");
1554                 return -ENODEV;
1555         }
1556
1557         ctx->next_bridge = of_drm_find_bridge(ep);
1558         of_node_put(ep);
1559         if (!ctx->next_bridge) {
1560                 dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n");
1561                 return -EPROBE_DEFER;
1562         }
1563
1564         i2c_set_clientdata(client, ctx);
1565         mutex_init(&ctx->lock);
1566
1567         ctx->supplies[0].supply = "vcn33";
1568         ctx->supplies[1].supply = "vcn18";
1569         ctx->supplies[2].supply = "vrf12";
1570         ret = devm_regulator_bulk_get(ctx->dev, 3, ctx->supplies);
1571         if (ret) {
1572                 dev_err(ctx->dev, "regulator_bulk failed\n");
1573                 return ret;
1574         }
1575
1576         ret = ite66121_power_on(ctx);
1577         if (ret)
1578                 return ret;
1579
1580         it66121_hw_reset(ctx);
1581
1582         ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config);
1583         if (IS_ERR(ctx->regmap)) {
1584                 ite66121_power_off(ctx);
1585                 return PTR_ERR(ctx->regmap);
1586         }
1587
1588         regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]);
1589         regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]);
1590         regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]);
1591         regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]);
1592
1593         /* Revision is shared with DEVICE_ID1 */
1594         revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]);
1595         device_ids[1] &= IT66121_DEVICE_ID1_MASK;
1596
1597         if (vendor_ids[0] != IT66121_VENDOR_ID0 || vendor_ids[1] != IT66121_VENDOR_ID1 ||
1598             device_ids[0] != IT66121_DEVICE_ID0 || device_ids[1] != IT66121_DEVICE_ID1) {
1599                 ite66121_power_off(ctx);
1600                 return -ENODEV;
1601         }
1602
1603         ctx->bridge.funcs = &it66121_bridge_funcs;
1604         ctx->bridge.of_node = dev->of_node;
1605         ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1606         ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
1607
1608         ret = devm_request_threaded_irq(dev, client->irq, NULL, it66121_irq_threaded_handler,
1609                                         IRQF_ONESHOT, dev_name(dev), ctx);
1610         if (ret < 0) {
1611                 dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret);
1612                 ite66121_power_off(ctx);
1613                 return ret;
1614         }
1615
1616         it66121_audio_codec_init(ctx, dev);
1617
1618         drm_bridge_add(&ctx->bridge);
1619
1620         dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id);
1621
1622         return 0;
1623 }
1624
1625 static int it66121_remove(struct i2c_client *client)
1626 {
1627         struct it66121_ctx *ctx = i2c_get_clientdata(client);
1628
1629         ite66121_power_off(ctx);
1630         drm_bridge_remove(&ctx->bridge);
1631         mutex_destroy(&ctx->lock);
1632
1633         return 0;
1634 }
1635
1636 static const struct of_device_id it66121_dt_match[] = {
1637         { .compatible = "ite,it66121" },
1638         { }
1639 };
1640 MODULE_DEVICE_TABLE(of, it66121_dt_match);
1641
1642 static const struct i2c_device_id it66121_id[] = {
1643         { "it66121", 0 },
1644         { }
1645 };
1646 MODULE_DEVICE_TABLE(i2c, it66121_id);
1647
1648 static struct i2c_driver it66121_driver = {
1649         .driver = {
1650                 .name   = "it66121",
1651                 .of_match_table = it66121_dt_match,
1652         },
1653         .probe = it66121_probe,
1654         .remove = it66121_remove,
1655         .id_table = it66121_id,
1656 };
1657
1658 module_i2c_driver(it66121_driver);
1659
1660 MODULE_AUTHOR("Phong LE");
1661 MODULE_DESCRIPTION("IT66121 HDMI transmitter driver");
1662 MODULE_LICENSE("GPL v2");