drivers/mmc/host/sunxi-mmc.c

   1 /*
   2  * Driver for sunxi SD/MMC host controllers
   3  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
   4  * (C) Copyright 2007-2011 Aaron Maoye <[email protected]>
   5  * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
   6  * (C) Copyright 2013-2014 David Lanzendörfer <[email protected]>
   7  * (C) Copyright 2013-2014 Hans de Goede <[email protected]>
   8  * (C) Copyright 2017 Sootech SA
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/io.h>
  19 #include <linux/device.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23
  24 #include <linux/clk.h>
  25 #include <linux/clk/sunxi-ng.h>
  26 #include <linux/gpio.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/slab.h>
  32 #include <linux/reset.h>
  33 #include <linux/regulator/consumer.h>
  34
  35 #include <linux/of_address.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/of_platform.h>
  38
  39 #include <linux/mmc/host.h>
  40 #include <linux/mmc/sd.h>
  41 #include <linux/mmc/sdio.h>
  42 #include <linux/mmc/mmc.h>
  43 #include <linux/mmc/core.h>
  44 #include <linux/mmc/card.h>
  45 #include <linux/mmc/slot-gpio.h>
  46
  47 /* register offset definitions */
  48 #define SDXC_REG_GCTRL  (0x00) /* SMC Global Control Register */
  49 #define SDXC_REG_CLKCR  (0x04) /* SMC Clock Control Register */
  50 #define SDXC_REG_TMOUT  (0x08) /* SMC Time Out Register */
  51 #define SDXC_REG_WIDTH  (0x0C) /* SMC Bus Width Register */
  52 #define SDXC_REG_BLKSZ  (0x10) /* SMC Block Size Register */
  53 #define SDXC_REG_BCNTR  (0x14) /* SMC Byte Count Register */
  54 #define SDXC_REG_CMDR   (0x18) /* SMC Command Register */
  55 #define SDXC_REG_CARG   (0x1C) /* SMC Argument Register */
  56 #define SDXC_REG_RESP0  (0x20) /* SMC Response Register 0 */
  57 #define SDXC_REG_RESP1  (0x24) /* SMC Response Register 1 */
  58 #define SDXC_REG_RESP2  (0x28) /* SMC Response Register 2 */
  59 #define SDXC_REG_RESP3  (0x2C) /* SMC Response Register 3 */
  60 #define SDXC_REG_IMASK  (0x30) /* SMC Interrupt Mask Register */
  61 #define SDXC_REG_MISTA  (0x34) /* SMC Masked Interrupt Status Register */
  62 #define SDXC_REG_RINTR  (0x38) /* SMC Raw Interrupt Status Register */
  63 #define SDXC_REG_STAS   (0x3C) /* SMC Status Register */
  64 #define SDXC_REG_FTRGL  (0x40) /* SMC FIFO Threshold Watermark Registe */
  65 #define SDXC_REG_FUNS   (0x44) /* SMC Function Select Register */
  66 #define SDXC_REG_CBCR   (0x48) /* SMC CIU Byte Count Register */
  67 #define SDXC_REG_BBCR   (0x4C) /* SMC BIU Byte Count Register */
  68 #define SDXC_REG_DBGC   (0x50) /* SMC Debug Enable Register */
  69 #define SDXC_REG_HWRST  (0x78) /* SMC Card Hardware Reset for Register */
  70 #define SDXC_REG_DMAC   (0x80) /* SMC IDMAC Control Register */
  71 #define SDXC_REG_DLBA   (0x84) /* SMC IDMAC Descriptor List Base Addre */
  72 #define SDXC_REG_IDST   (0x88) /* SMC IDMAC Status Register */
  73 #define SDXC_REG_IDIE   (0x8C) /* SMC IDMAC Interrupt Enable Register */
  74 #define SDXC_REG_CHDA   (0x90)
  75 #define SDXC_REG_CBDA   (0x94)
  76
  77 /* New registers introduced in A64 */
  78 #define SDXC_REG_A12A           0x058 /* SMC Auto Command 12 Register */
  79 #define SDXC_REG_SD_NTSR        0x05C /* SMC New Timing Set Register */
  80 #define SDXC_REG_DRV_DL         0x140 /* Drive Delay Control Register */
  81 #define SDXC_REG_SAMP_DL_REG    0x144 /* SMC sample delay control */
  82 #define SDXC_REG_DS_DL_REG      0x148 /* SMC data strobe delay control */
  83
  84 #define mmc_readl(host, reg) \
  85         readl((host)->reg_base + SDXC_##reg)
  86 #define mmc_writel(host, reg, value) \
  87         writel((value), (host)->reg_base + SDXC_##reg)
  88
  89 /* global control register bits */
  90 #define SDXC_SOFT_RESET                 BIT(0)
  91 #define SDXC_FIFO_RESET                 BIT(1)
  92 #define SDXC_DMA_RESET                  BIT(2)
  93 #define SDXC_INTERRUPT_ENABLE_BIT       BIT(4)
  94 #define SDXC_DMA_ENABLE_BIT             BIT(5)
  95 #define SDXC_DEBOUNCE_ENABLE_BIT        BIT(8)
  96 #define SDXC_POSEDGE_LATCH_DATA         BIT(9)
  97 #define SDXC_DDR_MODE                   BIT(10)
  98 #define SDXC_MEMORY_ACCESS_DONE         BIT(29)
  99 #define SDXC_ACCESS_DONE_DIRECT         BIT(30)
 100 #define SDXC_ACCESS_BY_AHB              BIT(31)
 101 #define SDXC_ACCESS_BY_DMA              (0 << 31)
 102 #define SDXC_HARDWARE_RESET \
 103         (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
 104
 105 /* clock control bits */
 106 #define SDXC_MASK_DATA0                 BIT(31)
 107 #define SDXC_CARD_CLOCK_ON              BIT(16)
 108 #define SDXC_LOW_POWER_ON               BIT(17)
 109
 110 /* bus width */
 111 #define SDXC_WIDTH1                     0
 112 #define SDXC_WIDTH4                     1
 113 #define SDXC_WIDTH8                     2
 114
 115 /* smc command bits */
 116 #define SDXC_RESP_EXPIRE                BIT(6)
 117 #define SDXC_LONG_RESPONSE              BIT(7)
 118 #define SDXC_CHECK_RESPONSE_CRC         BIT(8)
 119 #define SDXC_DATA_EXPIRE                BIT(9)
 120 #define SDXC_WRITE                      BIT(10)
 121 #define SDXC_SEQUENCE_MODE              BIT(11)
 122 #define SDXC_SEND_AUTO_STOP             BIT(12)
 123 #define SDXC_WAIT_PRE_OVER              BIT(13)
 124 #define SDXC_STOP_ABORT_CMD             BIT(14)
 125 #define SDXC_SEND_INIT_SEQUENCE         BIT(15)
 126 #define SDXC_UPCLK_ONLY                 BIT(21)
 127 #define SDXC_READ_CEATA_DEV             BIT(22)
 128 #define SDXC_CCS_EXPIRE                 BIT(23)
 129 #define SDXC_ENABLE_BIT_BOOT            BIT(24)
 130 #define SDXC_ALT_BOOT_OPTIONS           BIT(25)
 131 #define SDXC_BOOT_ACK_EXPIRE            BIT(26)
 132 #define SDXC_BOOT_ABORT                 BIT(27)
 133 #define SDXC_VOLTAGE_SWITCH             BIT(28)
 134 #define SDXC_USE_HOLD_REGISTER          BIT(29)
 135 #define SDXC_START                      BIT(31)
 136
 137 /* interrupt bits */
 138 #define SDXC_RESP_ERROR                 BIT(1)
 139 #define SDXC_COMMAND_DONE               BIT(2)
 140 #define SDXC_DATA_OVER                  BIT(3)
 141 #define SDXC_TX_DATA_REQUEST            BIT(4)
 142 #define SDXC_RX_DATA_REQUEST            BIT(5)
 143 #define SDXC_RESP_CRC_ERROR             BIT(6)
 144 #define SDXC_DATA_CRC_ERROR             BIT(7)
 145 #define SDXC_RESP_TIMEOUT               BIT(8)
 146 #define SDXC_DATA_TIMEOUT               BIT(9)
 147 #define SDXC_VOLTAGE_CHANGE_DONE        BIT(10)
 148 #define SDXC_FIFO_RUN_ERROR             BIT(11)
 149 #define SDXC_HARD_WARE_LOCKED           BIT(12)
 150 #define SDXC_START_BIT_ERROR            BIT(13)
 151 #define SDXC_AUTO_COMMAND_DONE          BIT(14)
 152 #define SDXC_END_BIT_ERROR              BIT(15)
 153 #define SDXC_SDIO_INTERRUPT             BIT(16)
 154 #define SDXC_CARD_INSERT                BIT(30)
 155 #define SDXC_CARD_REMOVE                BIT(31)
 156 #define SDXC_INTERRUPT_ERROR_BIT \
 157         (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
 158          SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
 159          SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
 160 #define SDXC_INTERRUPT_DONE_BIT \
 161         (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
 162          SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
 163
 164 /* status */
 165 #define SDXC_RXWL_FLAG                  BIT(0)
 166 #define SDXC_TXWL_FLAG                  BIT(1)
 167 #define SDXC_FIFO_EMPTY                 BIT(2)
 168 #define SDXC_FIFO_FULL                  BIT(3)
 169 #define SDXC_CARD_PRESENT               BIT(8)
 170 #define SDXC_CARD_DATA_BUSY             BIT(9)
 171 #define SDXC_DATA_FSM_BUSY              BIT(10)
 172 #define SDXC_DMA_REQUEST                BIT(31)
 173 #define SDXC_FIFO_SIZE                  16
 174
 175 /* Function select */
 176 #define SDXC_CEATA_ON                   (0xceaa << 16)
 177 #define SDXC_SEND_IRQ_RESPONSE          BIT(0)
 178 #define SDXC_SDIO_READ_WAIT             BIT(1)
 179 #define SDXC_ABORT_READ_DATA            BIT(2)
 180 #define SDXC_SEND_CCSD                  BIT(8)
 181 #define SDXC_SEND_AUTO_STOPCCSD         BIT(9)
 182 #define SDXC_CEATA_DEV_IRQ_ENABLE       BIT(10)
 183
 184 /* IDMA controller bus mod bit field */
 185 #define SDXC_IDMAC_SOFT_RESET           BIT(0)
 186 #define SDXC_IDMAC_FIX_BURST            BIT(1)
 187 #define SDXC_IDMAC_IDMA_ON              BIT(7)
 188 #define SDXC_IDMAC_REFETCH_DES          BIT(31)
 189
 190 /* IDMA status bit field */
 191 #define SDXC_IDMAC_TRANSMIT_INTERRUPT           BIT(0)
 192 #define SDXC_IDMAC_RECEIVE_INTERRUPT            BIT(1)
 193 #define SDXC_IDMAC_FATAL_BUS_ERROR              BIT(2)
 194 #define SDXC_IDMAC_DESTINATION_INVALID          BIT(4)
 195 #define SDXC_IDMAC_CARD_ERROR_SUM               BIT(5)
 196 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM         BIT(8)
 197 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM       BIT(9)
 198 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT         BIT(10)
 199 #define SDXC_IDMAC_IDLE                         (0 << 13)
 200 #define SDXC_IDMAC_SUSPEND                      (1 << 13)
 201 #define SDXC_IDMAC_DESC_READ                    (2 << 13)
 202 #define SDXC_IDMAC_DESC_CHECK                   (3 << 13)
 203 #define SDXC_IDMAC_READ_REQUEST_WAIT            (4 << 13)
 204 #define SDXC_IDMAC_WRITE_REQUEST_WAIT           (5 << 13)
 205 #define SDXC_IDMAC_READ                         (6 << 13)
 206 #define SDXC_IDMAC_WRITE                        (7 << 13)
 207 #define SDXC_IDMAC_DESC_CLOSE                   (8 << 13)
 208
 209 /*
 210 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
 211 *  Bits  0-12: buf1 size
 212 *  Bits 13-25: buf2 size
 213 *  Bits 26-31: not used
 214 * Since we only ever set buf1 size, we can simply store it directly.
 215 */
 216 #define SDXC_IDMAC_DES0_DIC     BIT(1)  /* disable interrupt on completion */
 217 #define SDXC_IDMAC_DES0_LD      BIT(2)  /* last descriptor */
 218 #define SDXC_IDMAC_DES0_FD      BIT(3)  /* first descriptor */
 219 #define SDXC_IDMAC_DES0_CH      BIT(4)  /* chain mode */
 220 #define SDXC_IDMAC_DES0_ER      BIT(5)  /* end of ring */
 221 #define SDXC_IDMAC_DES0_CES     BIT(30) /* card error summary */
 222 #define SDXC_IDMAC_DES0_OWN     BIT(31) /* 1-idma owns it, 0-host owns it */
 223
 224 #define SDXC_CLK_400K           0
 225 #define SDXC_CLK_25M            1
 226 #define SDXC_CLK_50M            2
 227 #define SDXC_CLK_50M_DDR        3
 228 #define SDXC_CLK_50M_DDR_8BIT   4
 229
 230 #define SDXC_2X_TIMING_MODE     BIT(31)
 231
 232 #define SDXC_CAL_START          BIT(15)
 233 #define SDXC_CAL_DONE           BIT(14)
 234 #define SDXC_CAL_DL_SHIFT       8
 235 #define SDXC_CAL_DL_SW_EN       BIT(7)
 236 #define SDXC_CAL_DL_SW_SHIFT    0
 237 #define SDXC_CAL_DL_MASK        0x3f
 238
 239 #define SDXC_CAL_TIMEOUT        3       /* in seconds, 3s is enough*/
 240
 241 struct sunxi_mmc_clk_delay {
 242         u32 output;
 243         u32 sample;
 244 };
 245
 246 struct sunxi_idma_des {
 247         __le32 config;
 248         __le32 buf_size;
 249         __le32 buf_addr_ptr1;
 250         __le32 buf_addr_ptr2;
 251 };
 252
 253 struct sunxi_mmc_cfg {
 254         u32 idma_des_size_bits;
 255         const struct sunxi_mmc_clk_delay *clk_delays;
 256
 257         /* does the IP block support autocalibration? */
 258         bool can_calibrate;
 259
 260         /* Does DATA0 needs to be masked while the clock is updated */
 261         bool mask_data0;
 262
 263         /* hardware only supports new timing mode */
 264         bool needs_new_timings;
 265
 266         /* hardware can switch between old and new timing modes */
 267         bool has_timings_switch;
 268 };
 269
 270 struct sunxi_mmc_host {
 271         struct device *dev;
 272         struct mmc_host *mmc;
 273         struct reset_control *reset;
 274         const struct sunxi_mmc_cfg *cfg;
 275
 276         /* IO mapping base */
 277         void __iomem    *reg_base;
 278
 279         /* clock management */
 280         struct clk      *clk_ahb;
 281         struct clk      *clk_mmc;
 282         struct clk      *clk_sample;
 283         struct clk      *clk_output;
 284
 285         /* irq */
 286         spinlock_t      lock;
 287         int             irq;
 288         u32             int_sum;
 289         u32             sdio_imask;
 290
 291         /* dma */
 292         dma_addr_t      sg_dma;
 293         void            *sg_cpu;
 294         bool            wait_dma;
 295
 296         struct mmc_request *mrq;
 297         struct mmc_request *manual_stop_mrq;
 298         int             ferror;
 299
 300         /* vqmmc */
 301         bool            vqmmc_enabled;
 302
 303         /* timings */
 304         bool            use_new_timings;
 305 };
 306
 307 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
 308 {
 309         unsigned long expire = jiffies + msecs_to_jiffies(250);
 310         u32 rval;
 311
 312         mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
 313         do {
 314                 rval = mmc_readl(host, REG_GCTRL);
 315         } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
 316
 317         if (rval & SDXC_HARDWARE_RESET) {
 318                 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
 319                 return -EIO;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static int sunxi_mmc_init_host(struct mmc_host *mmc)
 326 {
 327         u32 rval;
 328         struct sunxi_mmc_host *host = mmc_priv(mmc);
 329
 330         if (sunxi_mmc_reset_host(host))
 331                 return -EIO;
 332
 333         /*
 334          * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
 335          *
 336          * TODO: sun9i has a larger FIFO and supports higher trigger values
 337          */
 338         mmc_writel(host, REG_FTRGL, 0x20070008);
 339         /* Maximum timeout value */
 340         mmc_writel(host, REG_TMOUT, 0xffffffff);
 341         /* Unmask SDIO interrupt if needed */
 342         mmc_writel(host, REG_IMASK, host->sdio_imask);
 343         /* Clear all pending interrupts */
 344         mmc_writel(host, REG_RINTR, 0xffffffff);
 345         /* Debug register? undocumented */
 346         mmc_writel(host, REG_DBGC, 0xdeb);
 347         /* Enable CEATA support */
 348         mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
 349         /* Set DMA descriptor list base address */
 350         mmc_writel(host, REG_DLBA, host->sg_dma);
 351
 352         rval = mmc_readl(host, REG_GCTRL);
 353         rval |= SDXC_INTERRUPT_ENABLE_BIT;
 354         /* Undocumented, but found in Allwinner code */
 355         rval &= ~SDXC_ACCESS_DONE_DIRECT;
 356         mmc_writel(host, REG_GCTRL, rval);
 357
 358         return 0;
 359 }
 360
 361 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 362                                     struct mmc_data *data)
 363 {
 364         struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
 365         dma_addr_t next_desc = host->sg_dma;
 366         int i, max_len = (1 << host->cfg->idma_des_size_bits);
 367
 368         for (i = 0; i < data->sg_len; i++) {
 369                 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
 370                                              SDXC_IDMAC_DES0_OWN |
 371                                              SDXC_IDMAC_DES0_DIC);
 372
 373                 if (data->sg[i].length == max_len)
 374                         pdes[i].buf_size = 0; /* 0 == max_len */
 375                 else
 376                         pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
 377
 378                 next_desc += sizeof(struct sunxi_idma_des);
 379                 pdes[i].buf_addr_ptr1 =
 380                         cpu_to_le32(sg_dma_address(&data->sg[i]));
 381                 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
 382         }
 383
 384         pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
 385         pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
 386                                           SDXC_IDMAC_DES0_ER);
 387         pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
 388         pdes[i - 1].buf_addr_ptr2 = 0;
 389
 390         /*
 391          * Avoid the io-store starting the idmac hitting io-mem before the
 392          * descriptors hit the main-mem.
 393          */
 394         wmb();
 395 }
 396
 397 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
 398                              struct mmc_data *data)
 399 {
 400         u32 i, dma_len;
 401         struct scatterlist *sg;
 402
 403         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 404                              mmc_get_dma_dir(data));
 405         if (dma_len == 0) {
 406                 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
 407                 return -ENOMEM;
 408         }
 409
 410         for_each_sg(data->sg, sg, data->sg_len, i) {
 411                 if (sg->offset & 3 || sg->length & 3) {
 412                         dev_err(mmc_dev(host->mmc),
 413                                 "unaligned scatterlist: os %x length %d\n",
 414                                 sg->offset, sg->length);
 415                         return -EINVAL;
 416                 }
 417         }
 418
 419         return 0;
 420 }
 421
 422 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
 423                                 struct mmc_data *data)
 424 {
 425         u32 rval;
 426
 427         sunxi_mmc_init_idma_des(host, data);
 428
 429         rval = mmc_readl(host, REG_GCTRL);
 430         rval |= SDXC_DMA_ENABLE_BIT;
 431         mmc_writel(host, REG_GCTRL, rval);
 432         rval |= SDXC_DMA_RESET;
 433         mmc_writel(host, REG_GCTRL, rval);
 434
 435         mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
 436
 437         if (!(data->flags & MMC_DATA_WRITE))
 438                 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
 439
 440         mmc_writel(host, REG_DMAC,
 441                    SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
 442 }
 443
 444 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
 445                                        struct mmc_request *req)
 446 {
 447         u32 arg, cmd_val, ri;
 448         unsigned long expire = jiffies + msecs_to_jiffies(1000);
 449
 450         cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
 451                   SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
 452
 453         if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
 454                 cmd_val |= SD_IO_RW_DIRECT;
 455                 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 456                       ((req->cmd->arg >> 28) & 0x7);
 457         } else {
 458                 cmd_val |= MMC_STOP_TRANSMISSION;
 459                 arg = 0;
 460         }
 461
 462         mmc_writel(host, REG_CARG, arg);
 463         mmc_writel(host, REG_CMDR, cmd_val);
 464
 465         do {
 466                 ri = mmc_readl(host, REG_RINTR);
 467         } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
 468                  time_before(jiffies, expire));
 469
 470         if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
 471                 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
 472                 if (req->stop)
 473                         req->stop->resp[0] = -ETIMEDOUT;
 474         } else {
 475                 if (req->stop)
 476                         req->stop->resp[0] = mmc_readl(host, REG_RESP0);
 477         }
 478
 479         mmc_writel(host, REG_RINTR, 0xffff);
 480 }
 481
 482 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
 483 {
 484         struct mmc_command *cmd = host->mrq->cmd;
 485         struct mmc_data *data = host->mrq->data;
 486
 487         /* For some cmds timeout is normal with sd/mmc cards */
 488         if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
 489                 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
 490                                       cmd->opcode == SD_IO_RW_DIRECT))
 491                 return;
 492
 493         dev_dbg(mmc_dev(host->mmc),
 494                 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
 495                 host->mmc->index, cmd->opcode,
 496                 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
 497                 host->int_sum & SDXC_RESP_ERROR     ? " RE"     : "",
 498                 host->int_sum & SDXC_RESP_CRC_ERROR  ? " RCE"    : "",
 499                 host->int_sum & SDXC_DATA_CRC_ERROR  ? " DCE"    : "",
 500                 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO"    : "",
 501                 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO"    : "",
 502                 host->int_sum & SDXC_FIFO_RUN_ERROR  ? " FE"     : "",
 503                 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL"     : "",
 504                 host->int_sum & SDXC_START_BIT_ERROR ? " SBE"    : "",
 505                 host->int_sum & SDXC_END_BIT_ERROR   ? " EBE"    : ""
 506                 );
 507 }
 508
 509 /* Called in interrupt context! */
 510 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
 511 {
 512         struct mmc_request *mrq = host->mrq;
 513         struct mmc_data *data = mrq->data;
 514         u32 rval;
 515
 516         mmc_writel(host, REG_IMASK, host->sdio_imask);
 517         mmc_writel(host, REG_IDIE, 0);
 518
 519         if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
 520                 sunxi_mmc_dump_errinfo(host);
 521                 mrq->cmd->error = -ETIMEDOUT;
 522
 523                 if (data) {
 524                         data->error = -ETIMEDOUT;
 525                         host->manual_stop_mrq = mrq;
 526                 }
 527
 528                 if (mrq->stop)
 529                         mrq->stop->error = -ETIMEDOUT;
 530         } else {
 531                 if (mrq->cmd->flags & MMC_RSP_136) {
 532                         mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
 533                         mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
 534                         mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
 535                         mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
 536                 } else {
 537                         mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
 538                 }
 539
 540                 if (data)
 541                         data->bytes_xfered = data->blocks * data->blksz;
 542         }
 543
 544         if (data) {
 545                 mmc_writel(host, REG_IDST, 0x337);
 546                 mmc_writel(host, REG_DMAC, 0);
 547                 rval = mmc_readl(host, REG_GCTRL);
 548                 rval |= SDXC_DMA_RESET;
 549                 mmc_writel(host, REG_GCTRL, rval);
 550                 rval &= ~SDXC_DMA_ENABLE_BIT;
 551                 mmc_writel(host, REG_GCTRL, rval);
 552                 rval |= SDXC_FIFO_RESET;
 553                 mmc_writel(host, REG_GCTRL, rval);
 554                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 555                              mmc_get_dma_dir(data));
 556         }
 557
 558         mmc_writel(host, REG_RINTR, 0xffff);
 559
 560         host->mrq = NULL;
 561         host->int_sum = 0;
 562         host->wait_dma = false;
 563
 564         return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
 565 }
 566
 567 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
 568 {
 569         struct sunxi_mmc_host *host = dev_id;
 570         struct mmc_request *mrq;
 571         u32 msk_int, idma_int;
 572         bool finalize = false;
 573         bool sdio_int = false;
 574         irqreturn_t ret = IRQ_HANDLED;
 575
 576         spin_lock(&host->lock);
 577
 578         idma_int  = mmc_readl(host, REG_IDST);
 579         msk_int   = mmc_readl(host, REG_MISTA);
 580
 581         dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
 582                 host->mrq, msk_int, idma_int);
 583
 584         mrq = host->mrq;
 585         if (mrq) {
 586                 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
 587                         host->wait_dma = false;
 588
 589                 host->int_sum |= msk_int;
 590
 591                 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
 592                 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
 593                                 !(host->int_sum & SDXC_COMMAND_DONE))
 594                         mmc_writel(host, REG_IMASK,
 595                                    host->sdio_imask | SDXC_COMMAND_DONE);
 596                 /* Don't wait for dma on error */
 597                 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
 598                         finalize = true;
 599                 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
 600                                 !host->wait_dma)
 601                         finalize = true;
 602         }
 603
 604         if (msk_int & SDXC_SDIO_INTERRUPT)
 605                 sdio_int = true;
 606
 607         mmc_writel(host, REG_RINTR, msk_int);
 608         mmc_writel(host, REG_IDST, idma_int);
 609
 610         if (finalize)
 611                 ret = sunxi_mmc_finalize_request(host);
 612
 613         spin_unlock(&host->lock);
 614
 615         if (finalize && ret == IRQ_HANDLED)
 616                 mmc_request_done(host->mmc, mrq);
 617
 618         if (sdio_int)
 619                 mmc_signal_sdio_irq(host->mmc);
 620
 621         return ret;
 622 }
 623
 624 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
 625 {
 626         struct sunxi_mmc_host *host = dev_id;
 627         struct mmc_request *mrq;
 628         unsigned long iflags;
 629
 630         spin_lock_irqsave(&host->lock, iflags);
 631         mrq = host->manual_stop_mrq;
 632         spin_unlock_irqrestore(&host->lock, iflags);
 633
 634         if (!mrq) {
 635                 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
 636                 return IRQ_HANDLED;
 637         }
 638
 639         dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
 640
 641         /*
 642          * We will never have more than one outstanding request,
 643          * and we do not complete the request until after
 644          * we've cleared host->manual_stop_mrq so we do not need to
 645          * spin lock this function.
 646          * Additionally we have wait states within this function
 647          * so having it in a lock is a very bad idea.
 648          */
 649         sunxi_mmc_send_manual_stop(host, mrq);
 650
 651         spin_lock_irqsave(&host->lock, iflags);
 652         host->manual_stop_mrq = NULL;
 653         spin_unlock_irqrestore(&host->lock, iflags);
 654
 655         mmc_request_done(host->mmc, mrq);
 656
 657         return IRQ_HANDLED;
 658 }
 659
 660 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
 661 {
 662         unsigned long expire = jiffies + msecs_to_jiffies(750);
 663         u32 rval;
 664
 665         dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
 666                 oclk_en ? "en" : "dis");
 667
 668         rval = mmc_readl(host, REG_CLKCR);
 669         rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
 670
 671         if (oclk_en)
 672                 rval |= SDXC_CARD_CLOCK_ON;
 673         if (host->cfg->mask_data0)
 674                 rval |= SDXC_MASK_DATA0;
 675
 676         mmc_writel(host, REG_CLKCR, rval);
 677
 678         rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
 679         mmc_writel(host, REG_CMDR, rval);
 680
 681         do {
 682                 rval = mmc_readl(host, REG_CMDR);
 683         } while (time_before(jiffies, expire) && (rval & SDXC_START));
 684
 685         /* clear irq status bits set by the command */
 686         mmc_writel(host, REG_RINTR,
 687                    mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
 688
 689         if (rval & SDXC_START) {
 690                 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
 691                 return -EIO;
 692         }
 693
 694         if (host->cfg->mask_data0) {
 695                 rval = mmc_readl(host, REG_CLKCR);
 696                 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
 703 {
 704         if (!host->cfg->can_calibrate)
 705                 return 0;
 706
 707         /*
 708          * FIXME:
 709          * This is not clear how the calibration is supposed to work
 710          * yet. The best rate have been obtained by simply setting the
 711          * delay to 0, as Allwinner does in its BSP.
 712          *
 713          * The only mode that doesn't have such a delay is HS400, that
 714          * is in itself a TODO.
 715          */
 716         writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
 717
 718         return 0;
 719 }
 720
 721 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
 722                                    struct mmc_ios *ios, u32 rate)
 723 {
 724         int index;
 725
 726         /* clk controller delays not used under new timings mode */
 727         if (host->use_new_timings)
 728                 return 0;
 729
 730         /* some old controllers don't support delays */
 731         if (!host->cfg->clk_delays)
 732                 return 0;
 733
 734         /* determine delays */
 735         if (rate <= 400000) {
 736                 index = SDXC_CLK_400K;
 737         } else if (rate <= 25000000) {
 738                 index = SDXC_CLK_25M;
 739         } else if (rate <= 52000000) {
 740                 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
 741                     ios->timing != MMC_TIMING_MMC_DDR52) {
 742                         index = SDXC_CLK_50M;
 743                 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
 744                         index = SDXC_CLK_50M_DDR_8BIT;
 745                 } else {
 746                         index = SDXC_CLK_50M_DDR;
 747                 }
 748         } else {
 749                 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
 750                 return -EINVAL;
 751         }
 752
 753         clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
 754         clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
 755
 756         return 0;
 757 }
 758
 759 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 760                                   struct mmc_ios *ios)
 761 {
 762         struct mmc_host *mmc = host->mmc;
 763         long rate;
 764         u32 rval, clock = ios->clock, div = 1;
 765         int ret;
 766
 767         ret = sunxi_mmc_oclk_onoff(host, 0);
 768         if (ret)
 769                 return ret;
 770
 771         /* Our clock is gated now */
 772         mmc->actual_clock = 0;
 773
 774         if (!ios->clock)
 775                 return 0;
 776
 777         /*
 778          * Under the old timing mode, 8 bit DDR requires the module
 779          * clock to be double the card clock. Under the new timing
 780          * mode, all DDR modes require a doubled module clock.
 781          *
 782          * We currently only support the standard MMC DDR52 mode.
 783          * This block should be updated once support for other DDR
 784          * modes is added.
 785          */
 786         if (ios->timing == MMC_TIMING_MMC_DDR52 &&
 787             (host->use_new_timings ||
 788              ios->bus_width == MMC_BUS_WIDTH_8)) {
 789                 div = 2;
 790                 clock <<= 1;
 791         }
 792
 793         if (host->use_new_timings && host->cfg->has_timings_switch) {
 794                 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
 795                 if (ret) {
 796                         dev_err(mmc_dev(mmc),
 797                                 "error setting new timing mode\n");
 798                         return ret;
 799                 }
 800         }
 801
 802         rate = clk_round_rate(host->clk_mmc, clock);
 803         if (rate < 0) {
 804                 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
 805                         clock, rate);
 806                 return rate;
 807         }
 808         dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
 809                 clock, rate);
 810
 811         /* setting clock rate */
 812         ret = clk_set_rate(host->clk_mmc, rate);
 813         if (ret) {
 814                 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
 815                         rate, ret);
 816                 return ret;
 817         }
 818
 819         /* set internal divider */
 820         rval = mmc_readl(host, REG_CLKCR);
 821         rval &= ~0xff;
 822         rval |= div - 1;
 823         mmc_writel(host, REG_CLKCR, rval);
 824
 825         /* update card clock rate to account for internal divider */
 826         rate /= div;
 827
 828         if (host->use_new_timings) {
 829                 /* Don't touch the delay bits */
 830                 rval = mmc_readl(host, REG_SD_NTSR);
 831                 rval |= SDXC_2X_TIMING_MODE;
 832                 mmc_writel(host, REG_SD_NTSR, rval);
 833         }
 834
 835         /* sunxi_mmc_clk_set_phase expects the actual card clock rate */
 836         ret = sunxi_mmc_clk_set_phase(host, ios, rate);
 837         if (ret)
 838                 return ret;
 839
 840         ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
 841         if (ret)
 842                 return ret;
 843
 844         /*
 845          * FIXME:
 846          *
 847          * In HS400 we'll also need to calibrate the data strobe
 848          * signal. This should only happen on the MMC2 controller (at
 849          * least on the A64).
 850          */
 851
 852         ret = sunxi_mmc_oclk_onoff(host, 1);
 853         if (ret)
 854                 return ret;
 855
 856         /* And we just enabled our clock back */
 857         mmc->actual_clock = rate;
 858
 859         return 0;
 860 }
 861
 862 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 863 {
 864         struct sunxi_mmc_host *host = mmc_priv(mmc);
 865         u32 rval;
 866
 867         /* Set the power state */
 868         switch (ios->power_mode) {
 869         case MMC_POWER_ON:
 870                 break;
 871
 872         case MMC_POWER_UP:
 873                 if (!IS_ERR(mmc->supply.vmmc)) {
 874                         host->ferror = mmc_regulator_set_ocr(mmc,
 875                                                              mmc->supply.vmmc,
 876                                                              ios->vdd);
 877                         if (host->ferror)
 878                                 return;
 879                 }
 880
 881                 if (!IS_ERR(mmc->supply.vqmmc)) {
 882                         host->ferror = regulator_enable(mmc->supply.vqmmc);
 883                         if (host->ferror) {
 884                                 dev_err(mmc_dev(mmc),
 885                                         "failed to enable vqmmc\n");
 886                                 return;
 887                         }
 888                         host->vqmmc_enabled = true;
 889                 }
 890
 891                 host->ferror = sunxi_mmc_init_host(mmc);
 892                 if (host->ferror)
 893                         return;
 894
 895                 dev_dbg(mmc_dev(mmc), "power on!\n");
 896                 break;
 897
 898         case MMC_POWER_OFF:
 899                 dev_dbg(mmc_dev(mmc), "power off!\n");
 900                 sunxi_mmc_reset_host(host);
 901                 if (!IS_ERR(mmc->supply.vmmc))
 902                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 903
 904                 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
 905                         regulator_disable(mmc->supply.vqmmc);
 906                 host->vqmmc_enabled = false;
 907                 break;
 908         }
 909
 910         /* set bus width */
 911         switch (ios->bus_width) {
 912         case MMC_BUS_WIDTH_1:
 913                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
 914                 break;
 915         case MMC_BUS_WIDTH_4:
 916                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
 917                 break;
 918         case MMC_BUS_WIDTH_8:
 919                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
 920                 break;
 921         }
 922
 923         /* set ddr mode */
 924         rval = mmc_readl(host, REG_GCTRL);
 925         if (ios->timing == MMC_TIMING_UHS_DDR50 ||
 926             ios->timing == MMC_TIMING_MMC_DDR52)
 927                 rval |= SDXC_DDR_MODE;
 928         else
 929                 rval &= ~SDXC_DDR_MODE;
 930         mmc_writel(host, REG_GCTRL, rval);
 931
 932         /* set up clock */
 933         if (ios->power_mode) {
 934                 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
 935                 /* Android code had a usleep_range(50000, 55000); here */
 936         }
 937 }
 938
 939 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
 940 {
 941         /* vqmmc regulator is available */
 942         if (!IS_ERR(mmc->supply.vqmmc))
 943                 return mmc_regulator_set_vqmmc(mmc, ios);
 944
 945         /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
 946         if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 947                 return 0;
 948
 949         return -EINVAL;
 950 }
 951
 952 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 953 {
 954         struct sunxi_mmc_host *host = mmc_priv(mmc);
 955         unsigned long flags;
 956         u32 imask;
 957
 958         spin_lock_irqsave(&host->lock, flags);
 959
 960         imask = mmc_readl(host, REG_IMASK);
 961         if (enable) {
 962                 host->sdio_imask = SDXC_SDIO_INTERRUPT;
 963                 imask |= SDXC_SDIO_INTERRUPT;
 964         } else {
 965                 host->sdio_imask = 0;
 966                 imask &= ~SDXC_SDIO_INTERRUPT;
 967         }
 968         mmc_writel(host, REG_IMASK, imask);
 969         spin_unlock_irqrestore(&host->lock, flags);
 970 }
 971
 972 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
 973 {
 974         struct sunxi_mmc_host *host = mmc_priv(mmc);
 975         mmc_writel(host, REG_HWRST, 0);
 976         udelay(10);
 977         mmc_writel(host, REG_HWRST, 1);
 978         udelay(300);
 979 }
 980
 981 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 982 {
 983         struct sunxi_mmc_host *host = mmc_priv(mmc);
 984         struct mmc_command *cmd = mrq->cmd;
 985         struct mmc_data *data = mrq->data;
 986         unsigned long iflags;
 987         u32 imask = SDXC_INTERRUPT_ERROR_BIT;
 988         u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
 989         bool wait_dma = host->wait_dma;
 990         int ret;
 991
 992         /* Check for set_ios errors (should never happen) */
 993         if (host->ferror) {
 994                 mrq->cmd->error = host->ferror;
 995                 mmc_request_done(mmc, mrq);
 996                 return;
 997         }
 998
 999         if (data) {
1000                 ret = sunxi_mmc_map_dma(host, data);
1001                 if (ret < 0) {
1002                         dev_err(mmc_dev(mmc), "map DMA failed\n");
1003                         cmd->error = ret;
1004                         data->error = ret;
1005                         mmc_request_done(mmc, mrq);
1006                         return;
1007                 }
1008         }
1009
1010         if (cmd->opcode == MMC_GO_IDLE_STATE) {
1011                 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
1012                 imask |= SDXC_COMMAND_DONE;
1013         }
1014
1015         if (cmd->flags & MMC_RSP_PRESENT) {
1016                 cmd_val |= SDXC_RESP_EXPIRE;
1017                 if (cmd->flags & MMC_RSP_136)
1018                         cmd_val |= SDXC_LONG_RESPONSE;
1019                 if (cmd->flags & MMC_RSP_CRC)
1020                         cmd_val |= SDXC_CHECK_RESPONSE_CRC;
1021
1022                 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
1023                         cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
1024
1025                         if (cmd->data->stop) {
1026                                 imask |= SDXC_AUTO_COMMAND_DONE;
1027                                 cmd_val |= SDXC_SEND_AUTO_STOP;
1028                         } else {
1029                                 imask |= SDXC_DATA_OVER;
1030                         }
1031
1032                         if (cmd->data->flags & MMC_DATA_WRITE)
1033                                 cmd_val |= SDXC_WRITE;
1034                         else
1035                                 wait_dma = true;
1036                 } else {
1037                         imask |= SDXC_COMMAND_DONE;
1038                 }
1039         } else {
1040                 imask |= SDXC_COMMAND_DONE;
1041         }
1042
1043         dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1044                 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1045                 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1046
1047         spin_lock_irqsave(&host->lock, iflags);
1048
1049         if (host->mrq || host->manual_stop_mrq) {
1050                 spin_unlock_irqrestore(&host->lock, iflags);
1051
1052                 if (data)
1053                         dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1054                                      mmc_get_dma_dir(data));
1055
1056                 dev_err(mmc_dev(mmc), "request already pending\n");
1057                 mrq->cmd->error = -EBUSY;
1058                 mmc_request_done(mmc, mrq);
1059                 return;
1060         }
1061
1062         if (data) {
1063                 mmc_writel(host, REG_BLKSZ, data->blksz);
1064                 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1065                 sunxi_mmc_start_dma(host, data);
1066         }
1067
1068         host->mrq = mrq;
1069         host->wait_dma = wait_dma;
1070         mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1071         mmc_writel(host, REG_CARG, cmd->arg);
1072         mmc_writel(host, REG_CMDR, cmd_val);
1073
1074         spin_unlock_irqrestore(&host->lock, iflags);
1075 }
1076
1077 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1078 {
1079         struct sunxi_mmc_host *host = mmc_priv(mmc);
1080
1081         return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1082 }
1083
1084 static const struct mmc_host_ops sunxi_mmc_ops = {
1085         .request         = sunxi_mmc_request,
1086         .set_ios         = sunxi_mmc_set_ios,
1087         .get_ro          = mmc_gpio_get_ro,
1088         .get_cd          = mmc_gpio_get_cd,
1089         .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1090         .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1091         .hw_reset        = sunxi_mmc_hw_reset,
1092         .card_busy       = sunxi_mmc_card_busy,
1093 };
1094
1095 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1096         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
1097         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
1098         [SDXC_CLK_50M]          = { .output =  90, .sample = 120 },
1099         [SDXC_CLK_50M_DDR]      = { .output =  60, .sample = 120 },
1100         /* Value from A83T "new timing mode". Works but might not be right. */
1101         [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 180 },
1102 };
1103
1104 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1105         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
1106         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
1107         [SDXC_CLK_50M]          = { .output = 150, .sample = 120 },
1108         [SDXC_CLK_50M_DDR]      = { .output =  54, .sample =  36 },
1109         [SDXC_CLK_50M_DDR_8BIT] = { .output =  72, .sample =  72 },
1110 };
1111
1112 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1113         .idma_des_size_bits = 13,
1114         .clk_delays = NULL,
1115         .can_calibrate = false,
1116 };
1117
1118 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1119         .idma_des_size_bits = 16,
1120         .clk_delays = NULL,
1121         .can_calibrate = false,
1122 };
1123
1124 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1125         .idma_des_size_bits = 16,
1126         .clk_delays = sunxi_mmc_clk_delays,
1127         .can_calibrate = false,
1128 };
1129
1130 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
1131         .idma_des_size_bits = 16,
1132         .clk_delays = sunxi_mmc_clk_delays,
1133         .can_calibrate = false,
1134         .has_timings_switch = true,
1135 };
1136
1137 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1138         .idma_des_size_bits = 16,
1139         .clk_delays = sun9i_mmc_clk_delays,
1140         .can_calibrate = false,
1141 };
1142
1143 static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1144         .idma_des_size_bits = 16,
1145         .clk_delays = NULL,
1146         .can_calibrate = true,
1147         .mask_data0 = true,
1148         .needs_new_timings = true,
1149 };
1150
1151 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1152         .idma_des_size_bits = 13,
1153         .clk_delays = NULL,
1154         .can_calibrate = true,
1155 };
1156
1157 static const struct of_device_id sunxi_mmc_of_match[] = {
1158         { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1159         { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1160         { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1161         { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
1162         { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1163         { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1164         { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1165         { /* sentinel */ }
1166 };
1167 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1168
1169 static int sunxi_mmc_enable(struct sunxi_mmc_host *host)
1170 {
1171         int ret;
1172
1173         if (!IS_ERR(host->reset)) {
1174                 ret = reset_control_reset(host->reset);
1175                 if (ret) {
1176                         dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",
1177                                 ret);
1178                         return ret;
1179                 }
1180         }
1181
1182         ret = clk_prepare_enable(host->clk_ahb);
1183         if (ret) {
1184                 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);
1185                 goto error_assert_reset;
1186         }
1187
1188         ret = clk_prepare_enable(host->clk_mmc);
1189         if (ret) {
1190                 dev_err(host->dev, "Enable mmc clk err %d\n", ret);
1191                 goto error_disable_clk_ahb;
1192         }
1193
1194         ret = clk_prepare_enable(host->clk_output);
1195         if (ret) {
1196                 dev_err(host->dev, "Enable output clk err %d\n", ret);
1197                 goto error_disable_clk_mmc;
1198         }
1199
1200         ret = clk_prepare_enable(host->clk_sample);
1201         if (ret) {
1202                 dev_err(host->dev, "Enable sample clk err %d\n", ret);
1203                 goto error_disable_clk_output;
1204         }
1205
1206         /*
1207          * Sometimes the controller asserts the irq on boot for some reason,
1208          * make sure the controller is in a sane state before enabling irqs.
1209          */
1210         ret = sunxi_mmc_reset_host(host);
1211         if (ret)
1212                 goto error_disable_clk_sample;
1213
1214         return 0;
1215
1216 error_disable_clk_sample:
1217         clk_disable_unprepare(host->clk_sample);
1218 error_disable_clk_output:
1219         clk_disable_unprepare(host->clk_output);
1220 error_disable_clk_mmc:
1221         clk_disable_unprepare(host->clk_mmc);
1222 error_disable_clk_ahb:
1223         clk_disable_unprepare(host->clk_ahb);
1224 error_assert_reset:
1225         if (!IS_ERR(host->reset))
1226                 reset_control_assert(host->reset);
1227         return ret;
1228 }
1229
1230 static void sunxi_mmc_disable(struct sunxi_mmc_host *host)
1231 {
1232         sunxi_mmc_reset_host(host);
1233
1234         clk_disable_unprepare(host->clk_sample);
1235         clk_disable_unprepare(host->clk_output);
1236         clk_disable_unprepare(host->clk_mmc);
1237         clk_disable_unprepare(host->clk_ahb);
1238
1239         if (!IS_ERR(host->reset))
1240                 reset_control_assert(host->reset);
1241 }
1242
1243 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1244                                       struct platform_device *pdev)
1245 {
1246         int ret;
1247
1248         host->cfg = of_device_get_match_data(&pdev->dev);
1249         if (!host->cfg)
1250                 return -EINVAL;
1251
1252         ret = mmc_regulator_get_supply(host->mmc);
1253         if (ret)
1254                 return ret;
1255
1256         host->reg_base = devm_ioremap_resource(&pdev->dev,
1257                               platform_get_resource(pdev, IORESOURCE_MEM, 0));
1258         if (IS_ERR(host->reg_base))
1259                 return PTR_ERR(host->reg_base);
1260
1261         host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1262         if (IS_ERR(host->clk_ahb)) {
1263                 dev_err(&pdev->dev, "Could not get ahb clock\n");
1264                 return PTR_ERR(host->clk_ahb);
1265         }
1266
1267         host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1268         if (IS_ERR(host->clk_mmc)) {
1269                 dev_err(&pdev->dev, "Could not get mmc clock\n");
1270                 return PTR_ERR(host->clk_mmc);
1271         }
1272
1273         if (host->cfg->clk_delays) {
1274                 host->clk_output = devm_clk_get(&pdev->dev, "output");
1275                 if (IS_ERR(host->clk_output)) {
1276                         dev_err(&pdev->dev, "Could not get output clock\n");
1277                         return PTR_ERR(host->clk_output);
1278                 }
1279
1280                 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1281                 if (IS_ERR(host->clk_sample)) {
1282                         dev_err(&pdev->dev, "Could not get sample clock\n");
1283                         return PTR_ERR(host->clk_sample);
1284                 }
1285         }
1286
1287         host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1288                                                                 "ahb");
1289         if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1290                 return PTR_ERR(host->reset);
1291
1292         ret = sunxi_mmc_enable(host);
1293         if (ret)
1294                 return ret;
1295
1296         host->irq = platform_get_irq(pdev, 0);
1297         if (host->irq <= 0) {
1298                 ret = -EINVAL;
1299                 goto error_disable_mmc;
1300         }
1301
1302         return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1303                         sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1304
1305 error_disable_mmc:
1306         sunxi_mmc_disable(host);
1307         return ret;
1308 }
1309
1310 static int sunxi_mmc_probe(struct platform_device *pdev)
1311 {
1312         struct sunxi_mmc_host *host;
1313         struct mmc_host *mmc;
1314         int ret;
1315
1316         mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1317         if (!mmc) {
1318                 dev_err(&pdev->dev, "mmc alloc host failed\n");
1319                 return -ENOMEM;
1320         }
1321         platform_set_drvdata(pdev, mmc);
1322
1323         host = mmc_priv(mmc);
1324         host->dev = &pdev->dev;
1325         host->mmc = mmc;
1326         spin_lock_init(&host->lock);
1327
1328         ret = sunxi_mmc_resource_request(host, pdev);
1329         if (ret)
1330                 goto error_free_host;
1331
1332         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1333                                           &host->sg_dma, GFP_KERNEL);
1334         if (!host->sg_cpu) {
1335                 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1336                 ret = -ENOMEM;
1337                 goto error_free_host;
1338         }
1339
1340         if (host->cfg->has_timings_switch) {
1341                 /*
1342                  * Supports both old and new timing modes.
1343                  * Try setting the clk to new timing mode.
1344                  */
1345                 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
1346
1347                 /* And check the result */
1348                 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
1349                 if (ret < 0) {
1350                         /*
1351                          * For whatever reason we were not able to get
1352                          * the current active mode. Default to old mode.
1353                          */
1354                         dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
1355                         host->use_new_timings = false;
1356                 } else {
1357                         host->use_new_timings = !!ret;
1358                 }
1359         } else if (host->cfg->needs_new_timings) {
1360                 /* Supports new timing mode only */
1361                 host->use_new_timings = true;
1362         }
1363
1364         mmc->ops                = &sunxi_mmc_ops;
1365         mmc->max_blk_count      = 8192;
1366         mmc->max_blk_size       = 4096;
1367         mmc->max_segs           = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1368         mmc->max_seg_size       = (1 << host->cfg->idma_des_size_bits);
1369         mmc->max_req_size       = mmc->max_seg_size * mmc->max_segs;
1370         /* 400kHz ~ 52MHz */
1371         mmc->f_min              =   400000;
1372         mmc->f_max              = 52000000;
1373         mmc->caps              |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1374                                   MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1375
1376         if (host->cfg->clk_delays || host->use_new_timings)
1377                 mmc->caps      |= MMC_CAP_1_8V_DDR;
1378
1379         ret = mmc_of_parse(mmc);
1380         if (ret)
1381                 goto error_free_dma;
1382
1383         ret = mmc_add_host(mmc);
1384         if (ret)
1385                 goto error_free_dma;
1386
1387         dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1388         return 0;
1389
1390 error_free_dma:
1391         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1392 error_free_host:
1393         mmc_free_host(mmc);
1394         return ret;
1395 }
1396
1397 static int sunxi_mmc_remove(struct platform_device *pdev)
1398 {
1399         struct mmc_host *mmc = platform_get_drvdata(pdev);
1400         struct sunxi_mmc_host *host = mmc_priv(mmc);
1401
1402         mmc_remove_host(mmc);
1403         disable_irq(host->irq);
1404         sunxi_mmc_disable(host);
1405         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1406         mmc_free_host(mmc);
1407
1408         return 0;
1409 }
1410
1411 static struct platform_driver sunxi_mmc_driver = {
1412         .driver = {
1413                 .name   = "sunxi-mmc",
1414                 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1415         },
1416         .probe          = sunxi_mmc_probe,
1417         .remove         = sunxi_mmc_remove,
1418 };
1419 module_platform_driver(sunxi_mmc_driver);
1420
1421 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1422 MODULE_LICENSE("GPL v2");
1423 MODULE_AUTHOR("David Lanzendörfer <[email protected]>");
1424 MODULE_ALIAS("platform:sunxi-mmc");