drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_i2c.h"
  31
  32 #include "atom.h"
  33 #include "atom-bits.h"
  34 #include "atombios_encoders.h"
  35 #include "bif/bif_4_1_d.h"
  36
  37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
  38                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  39                                           u8 index)
  40 {
  41
  42 }
  43
  44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  45 {
  46         struct amdgpu_i2c_bus_rec i2c;
  47
  48         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  49
  50         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
  51         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
  52         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
  53         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
  54         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
  55         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
  56         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
  57         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
  58         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  59         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  60         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  61         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  62         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
  63         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
  64         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
  65         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
  66
  67         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
  68                 i2c.hw_capable = true;
  69         else
  70                 i2c.hw_capable = false;
  71
  72         if (gpio->sucI2cId.ucAccess == 0xa0)
  73                 i2c.mm_i2c = true;
  74         else
  75                 i2c.mm_i2c = false;
  76
  77         i2c.i2c_id = gpio->sucI2cId.ucAccess;
  78
  79         if (i2c.mask_clk_reg)
  80                 i2c.valid = true;
  81         else
  82                 i2c.valid = false;
  83
  84         return i2c;
  85 }
  86
  87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
  88                                                           uint8_t id)
  89 {
  90         struct atom_context *ctx = adev->mode_info.atom_context;
  91         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  92         struct amdgpu_i2c_bus_rec i2c;
  93         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  94         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  95         uint16_t data_offset, size;
  96         int i, num_indices;
  97
  98         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  99         i2c.valid = false;
 100
 101         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 102                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 103
 104                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 105                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 106
 107                 gpio = &i2c_info->asGPIO_Info[0];
 108                 for (i = 0; i < num_indices; i++) {
 109
 110                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 111
 112                         if (gpio->sucI2cId.ucAccess == id) {
 113                                 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 114                                 break;
 115                         }
 116                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 117                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
 125 {
 126         struct atom_context *ctx = adev->mode_info.atom_context;
 127         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 128         struct amdgpu_i2c_bus_rec i2c;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 130         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 131         uint16_t data_offset, size;
 132         int i, num_indices;
 133         char stmp[32];
 134
 135         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 136                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 137
 138                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 139                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 140
 141                 gpio = &i2c_info->asGPIO_Info[0];
 142                 for (i = 0; i < num_indices; i++) {
 143                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 144
 145                         i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 146
 147                         if (i2c.valid) {
 148                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 149                                 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
 150                         }
 151                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 152                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 153                 }
 154         }
 155 }
 156
 157 struct amdgpu_gpio_rec
 158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
 159                             u8 id)
 160 {
 161         struct atom_context *ctx = adev->mode_info.atom_context;
 162         struct amdgpu_gpio_rec gpio;
 163         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 164         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 165         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 166         u16 data_offset, size;
 167         int i, num_indices;
 168
 169         memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
 170         gpio.valid = false;
 171
 172         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 173                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 174
 175                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 176                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 177
 178                 pin = gpio_info->asGPIO_Pin;
 179                 for (i = 0; i < num_indices; i++) {
 180                         if (id == pin->ucGPIO_ID) {
 181                                 gpio.id = pin->ucGPIO_ID;
 182                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
 183                                 gpio.shift = pin->ucGpioPinBitShift;
 184                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 185                                 gpio.valid = true;
 186                                 break;
 187                         }
 188                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 189                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 190                 }
 191         }
 192
 193         return gpio;
 194 }
 195
 196 static struct amdgpu_hpd
 197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 198                                        struct amdgpu_gpio_rec *gpio)
 199 {
 200         struct amdgpu_hpd hpd;
 201         u32 reg;
 202
 203         memset(&hpd, 0, sizeof(struct amdgpu_hpd));
 204
 205         reg = amdgpu_display_hpd_get_gpio_reg(adev);
 206
 207         hpd.gpio = *gpio;
 208         if (gpio->reg == reg) {
 209                 switch(gpio->mask) {
 210                 case (1 << 0):
 211                         hpd.hpd = AMDGPU_HPD_1;
 212                         break;
 213                 case (1 << 8):
 214                         hpd.hpd = AMDGPU_HPD_2;
 215                         break;
 216                 case (1 << 16):
 217                         hpd.hpd = AMDGPU_HPD_3;
 218                         break;
 219                 case (1 << 24):
 220                         hpd.hpd = AMDGPU_HPD_4;
 221                         break;
 222                 case (1 << 26):
 223                         hpd.hpd = AMDGPU_HPD_5;
 224                         break;
 225                 case (1 << 28):
 226                         hpd.hpd = AMDGPU_HPD_6;
 227                         break;
 228                 default:
 229                         hpd.hpd = AMDGPU_HPD_NONE;
 230                         break;
 231                 }
 232         } else
 233                 hpd.hpd = AMDGPU_HPD_NONE;
 234         return hpd;
 235 }
 236
 237 static const int object_connector_convert[] = {
 238         DRM_MODE_CONNECTOR_Unknown,
 239         DRM_MODE_CONNECTOR_DVII,
 240         DRM_MODE_CONNECTOR_DVII,
 241         DRM_MODE_CONNECTOR_DVID,
 242         DRM_MODE_CONNECTOR_DVID,
 243         DRM_MODE_CONNECTOR_VGA,
 244         DRM_MODE_CONNECTOR_Composite,
 245         DRM_MODE_CONNECTOR_SVIDEO,
 246         DRM_MODE_CONNECTOR_Unknown,
 247         DRM_MODE_CONNECTOR_Unknown,
 248         DRM_MODE_CONNECTOR_9PinDIN,
 249         DRM_MODE_CONNECTOR_Unknown,
 250         DRM_MODE_CONNECTOR_HDMIA,
 251         DRM_MODE_CONNECTOR_HDMIB,
 252         DRM_MODE_CONNECTOR_LVDS,
 253         DRM_MODE_CONNECTOR_9PinDIN,
 254         DRM_MODE_CONNECTOR_Unknown,
 255         DRM_MODE_CONNECTOR_Unknown,
 256         DRM_MODE_CONNECTOR_Unknown,
 257         DRM_MODE_CONNECTOR_DisplayPort,
 258         DRM_MODE_CONNECTOR_eDP,
 259         DRM_MODE_CONNECTOR_Unknown
 260 };
 261
 262 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
 263 {
 264         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 265         struct atom_context *ctx = mode_info->atom_context;
 266         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 267         u16 size, data_offset;
 268         u8 frev, crev;
 269         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 270         ATOM_OBJECT_HEADER *obj_header;
 271
 272         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 273                 return false;
 274
 275         if (crev < 2)
 276                 return false;
 277
 278         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 279         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 280             (ctx->bios + data_offset +
 281              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 282
 283         if (path_obj->ucNumOfDispPath)
 284                 return true;
 285         else
 286                 return false;
 287 }
 288
 289 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
 290 {
 291         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 292         struct atom_context *ctx = mode_info->atom_context;
 293         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 294         u16 size, data_offset;
 295         u8 frev, crev;
 296         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 297         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 298         ATOM_OBJECT_TABLE *router_obj;
 299         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 300         ATOM_OBJECT_HEADER *obj_header;
 301         int i, j, k, path_size, device_support;
 302         int connector_type;
 303         u16 conn_id, connector_object_id;
 304         struct amdgpu_i2c_bus_rec ddc_bus;
 305         struct amdgpu_router router;
 306         struct amdgpu_gpio_rec gpio;
 307         struct amdgpu_hpd hpd;
 308
 309         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 310                 return false;
 311
 312         if (crev < 2)
 313                 return false;
 314
 315         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 316         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 317             (ctx->bios + data_offset +
 318              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 319         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 320             (ctx->bios + data_offset +
 321              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 322         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 323             (ctx->bios + data_offset +
 324              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 325         router_obj = (ATOM_OBJECT_TABLE *)
 326                 (ctx->bios + data_offset +
 327                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 328         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 329
 330         path_size = 0;
 331         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 332                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 333                 ATOM_DISPLAY_OBJECT_PATH *path;
 334                 addr += path_size;
 335                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 336                 path_size += le16_to_cpu(path->usSize);
 337
 338                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 339                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 340
 341                         con_obj_id =
 342                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 343                             >> OBJECT_ID_SHIFT;
 344                         con_obj_num =
 345                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 346                             >> ENUM_ID_SHIFT;
 347                         con_obj_type =
 348                             (le16_to_cpu(path->usConnObjectId) &
 349                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 350
 351                         connector_type =
 352                                 object_connector_convert[con_obj_id];
 353                         connector_object_id = con_obj_id;
 354
 355                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 356                                 continue;
 357
 358                         router.ddc_valid = false;
 359                         router.cd_valid = false;
 360                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 361                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 362
 363                                 grph_obj_id =
 364                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 365                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 366                                 grph_obj_num =
 367                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 368                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 369                                 grph_obj_type =
 370                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 371                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 372
 373                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 374                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 375                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 376                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 377                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 378                                                                 (ctx->bios + data_offset +
 379                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 380                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 381                                                         u16 caps = 0;
 382
 383                                                         while (record->ucRecordSize > 0 &&
 384                                                                record->ucRecordType > 0 &&
 385                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 386                                                                 switch (record->ucRecordType) {
 387                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 388                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 389                                                                                 record;
 390                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 391                                                                         break;
 392                                                                 }
 393                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 394                                                                         ((char *)record + record->ucRecordSize);
 395                                                         }
 396                                                         amdgpu_display_add_encoder(adev, encoder_obj,
 397                                                                                     le16_to_cpu(path->usDeviceTag),
 398                                                                                     caps);
 399                                                 }
 400                                         }
 401                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 402                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 403                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 404                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 405                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 406                                                                 (ctx->bios + data_offset +
 407                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 408                                                         ATOM_I2C_RECORD *i2c_record;
 409                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 410                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 411                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 412                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 413                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 414                                                                 (ctx->bios + data_offset +
 415                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 416                                                         u8 *num_dst_objs = (u8 *)
 417                                                                 ((u8 *)router_src_dst_table + 1 +
 418                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 419                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 420                                                         int enum_id;
 421
 422                                                         router.router_id = router_obj_id;
 423                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 424                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 425                                                                     le16_to_cpu(dst_objs[enum_id]))
 426                                                                         break;
 427                                                         }
 428
 429                                                         while (record->ucRecordSize > 0 &&
 430                                                                record->ucRecordType > 0 &&
 431                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 432                                                                 switch (record->ucRecordType) {
 433                                                                 case ATOM_I2C_RECORD_TYPE:
 434                                                                         i2c_record =
 435                                                                                 (ATOM_I2C_RECORD *)
 436                                                                                 record;
 437                                                                         i2c_config =
 438                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 439                                                                                 &i2c_record->sucI2cId;
 440                                                                         router.i2c_info =
 441                                                                                 amdgpu_atombios_lookup_i2c_gpio(adev,
 442                                                                                                        i2c_config->
 443                                                                                                        ucAccess);
 444                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 445                                                                         break;
 446                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 447                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 448                                                                                 record;
 449                                                                         router.ddc_valid = true;
 450                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 451                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 452                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 453                                                                         break;
 454                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 455                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 456                                                                                 record;
 457                                                                         router.cd_valid = true;
 458                                                                         router.cd_mux_type = cd_path->ucMuxType;
 459                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 460                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 461                                                                         break;
 462                                                                 }
 463                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 464                                                                         ((char *)record + record->ucRecordSize);
 465                                                         }
 466                                                 }
 467                                         }
 468                                 }
 469                         }
 470
 471                         /* look up gpio for ddc, hpd */
 472                         ddc_bus.valid = false;
 473                         hpd.hpd = AMDGPU_HPD_NONE;
 474                         if ((le16_to_cpu(path->usDeviceTag) &
 475                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 476                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 477                                         if (le16_to_cpu(path->usConnObjectId) ==
 478                                             le16_to_cpu(con_obj->asObjects[j].
 479                                                         usObjectID)) {
 480                                                 ATOM_COMMON_RECORD_HEADER
 481                                                     *record =
 482                                                     (ATOM_COMMON_RECORD_HEADER
 483                                                      *)
 484                                                     (ctx->bios + data_offset +
 485                                                      le16_to_cpu(con_obj->
 486                                                                  asObjects[j].
 487                                                                  usRecordOffset));
 488                                                 ATOM_I2C_RECORD *i2c_record;
 489                                                 ATOM_HPD_INT_RECORD *hpd_record;
 490                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 491
 492                                                 while (record->ucRecordSize > 0 &&
 493                                                        record->ucRecordType > 0 &&
 494                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 495                                                         switch (record->ucRecordType) {
 496                                                         case ATOM_I2C_RECORD_TYPE:
 497                                                                 i2c_record =
 498                                                                     (ATOM_I2C_RECORD *)
 499                                                                         record;
 500                                                                 i2c_config =
 501                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 502                                                                         &i2c_record->sucI2cId;
 503                                                                 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
 504                                                                                                  i2c_config->
 505                                                                                                  ucAccess);
 506                                                                 break;
 507                                                         case ATOM_HPD_INT_RECORD_TYPE:
 508                                                                 hpd_record =
 509                                                                         (ATOM_HPD_INT_RECORD *)
 510                                                                         record;
 511                                                                 gpio = amdgpu_atombios_lookup_gpio(adev,
 512                                                                                           hpd_record->ucHPDIntGPIOID);
 513                                                                 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
 514                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 515                                                                 break;
 516                                                         }
 517                                                         record =
 518                                                             (ATOM_COMMON_RECORD_HEADER
 519                                                              *) ((char *)record
 520                                                                  +
 521                                                                  record->
 522                                                                  ucRecordSize);
 523                                                 }
 524                                                 break;
 525                                         }
 526                                 }
 527                         }
 528
 529                         /* needed for aux chan transactions */
 530                         ddc_bus.hpd = hpd.hpd;
 531
 532                         conn_id = le16_to_cpu(path->usConnObjectId);
 533
 534                         amdgpu_display_add_connector(adev,
 535                                                       conn_id,
 536                                                       le16_to_cpu(path->usDeviceTag),
 537                                                       connector_type, &ddc_bus,
 538                                                       connector_object_id,
 539                                                       &hpd,
 540                                                       &router);
 541
 542                 }
 543         }
 544
 545         amdgpu_link_encoder_connector(adev->ddev);
 546
 547         return true;
 548 }
 549
 550 union firmware_info {
 551         ATOM_FIRMWARE_INFO info;
 552         ATOM_FIRMWARE_INFO_V1_2 info_12;
 553         ATOM_FIRMWARE_INFO_V1_3 info_13;
 554         ATOM_FIRMWARE_INFO_V1_4 info_14;
 555         ATOM_FIRMWARE_INFO_V2_1 info_21;
 556         ATOM_FIRMWARE_INFO_V2_2 info_22;
 557 };
 558
 559 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 560 {
 561         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 562         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 563         uint8_t frev, crev;
 564         uint16_t data_offset;
 565         int ret = -EINVAL;
 566
 567         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 568                                    &frev, &crev, &data_offset)) {
 569                 int i;
 570                 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
 571                 struct amdgpu_pll *spll = &adev->clock.spll;
 572                 struct amdgpu_pll *mpll = &adev->clock.mpll;
 573                 union firmware_info *firmware_info =
 574                         (union firmware_info *)(mode_info->atom_context->bios +
 575                                                 data_offset);
 576                 /* pixel clocks */
 577                 ppll->reference_freq =
 578                     le16_to_cpu(firmware_info->info.usReferenceClock);
 579                 ppll->reference_div = 0;
 580
 581                 ppll->pll_out_min =
 582                         le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 583                 ppll->pll_out_max =
 584                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 585
 586                 ppll->lcd_pll_out_min =
 587                         le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 588                 if (ppll->lcd_pll_out_min == 0)
 589                         ppll->lcd_pll_out_min = ppll->pll_out_min;
 590                 ppll->lcd_pll_out_max =
 591                         le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 592                 if (ppll->lcd_pll_out_max == 0)
 593                         ppll->lcd_pll_out_max = ppll->pll_out_max;
 594
 595                 if (ppll->pll_out_min == 0)
 596                         ppll->pll_out_min = 64800;
 597
 598                 ppll->pll_in_min =
 599                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 600                 ppll->pll_in_max =
 601                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 602
 603                 ppll->min_post_div = 2;
 604                 ppll->max_post_div = 0x7f;
 605                 ppll->min_frac_feedback_div = 0;
 606                 ppll->max_frac_feedback_div = 9;
 607                 ppll->min_ref_div = 2;
 608                 ppll->max_ref_div = 0x3ff;
 609                 ppll->min_feedback_div = 4;
 610                 ppll->max_feedback_div = 0xfff;
 611                 ppll->best_vco = 0;
 612
 613                 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
 614                         adev->clock.ppll[i] = *ppll;
 615
 616                 /* system clock */
 617                 spll->reference_freq =
 618                         le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
 619                 spll->reference_div = 0;
 620
 621                 spll->pll_out_min =
 622                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 623                 spll->pll_out_max =
 624                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 625
 626                 /* ??? */
 627                 if (spll->pll_out_min == 0)
 628                         spll->pll_out_min = 64800;
 629
 630                 spll->pll_in_min =
 631                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 632                 spll->pll_in_max =
 633                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 634
 635                 spll->min_post_div = 1;
 636                 spll->max_post_div = 1;
 637                 spll->min_ref_div = 2;
 638                 spll->max_ref_div = 0xff;
 639                 spll->min_feedback_div = 4;
 640                 spll->max_feedback_div = 0xff;
 641                 spll->best_vco = 0;
 642
 643                 /* memory clock */
 644                 mpll->reference_freq =
 645                         le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
 646                 mpll->reference_div = 0;
 647
 648                 mpll->pll_out_min =
 649                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 650                 mpll->pll_out_max =
 651                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 652
 653                 /* ??? */
 654                 if (mpll->pll_out_min == 0)
 655                         mpll->pll_out_min = 64800;
 656
 657                 mpll->pll_in_min =
 658                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 659                 mpll->pll_in_max =
 660                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 661
 662                 adev->clock.default_sclk =
 663                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 664                 adev->clock.default_mclk =
 665                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 666
 667                 mpll->min_post_div = 1;
 668                 mpll->max_post_div = 1;
 669                 mpll->min_ref_div = 2;
 670                 mpll->max_ref_div = 0xff;
 671                 mpll->min_feedback_div = 4;
 672                 mpll->max_feedback_div = 0xff;
 673                 mpll->best_vco = 0;
 674
 675                 /* disp clock */
 676                 adev->clock.default_dispclk =
 677                         le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 678                 /* set a reasonable default for DP */
 679                 if (adev->clock.default_dispclk < 53900) {
 680                         DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
 681                                  adev->clock.default_dispclk / 100);
 682                         adev->clock.default_dispclk = 60000;
 683                 }
 684                 adev->clock.dp_extclk =
 685                         le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 686                 adev->clock.current_dispclk = adev->clock.default_dispclk;
 687
 688                 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 689                 if (adev->clock.max_pixel_clock == 0)
 690                         adev->clock.max_pixel_clock = 40000;
 691
 692                 /* not technically a clock, but... */
 693                 adev->mode_info.firmware_flags =
 694                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 695
 696                 ret = 0;
 697         }
 698
 699         adev->pm.current_sclk = adev->clock.default_sclk;
 700         adev->pm.current_mclk = adev->clock.default_mclk;
 701
 702         return ret;
 703 }
 704
 705 union gfx_info {
 706         ATOM_GFX_INFO_V2_1 info;
 707 };
 708
 709 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
 710 {
 711         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 712         int index = GetIndexIntoMasterTable(DATA, GFX_Info);
 713         uint8_t frev, crev;
 714         uint16_t data_offset;
 715         int ret = -EINVAL;
 716
 717         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 718                                    &frev, &crev, &data_offset)) {
 719                 union gfx_info *gfx_info = (union gfx_info *)
 720                         (mode_info->atom_context->bios + data_offset);
 721
 722                 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
 723                 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
 724                 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
 725                 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
 726                 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
 727                 adev->gfx.config.max_texture_channel_caches =
 728                         gfx_info->info.max_texture_channel_caches;
 729
 730                 ret = 0;
 731         }
 732         return ret;
 733 }
 734
 735 union igp_info {
 736         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 737         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 738         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
 739         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
 740         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
 741         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
 742 };
 743
 744 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
 745                                                  struct amdgpu_atom_ss *ss,
 746                                                  int id)
 747 {
 748         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 749         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 750         u16 data_offset, size;
 751         union igp_info *igp_info;
 752         u8 frev, crev;
 753         u16 percentage = 0, rate = 0;
 754
 755         /* get any igp specific overrides */
 756         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 757                                    &frev, &crev, &data_offset)) {
 758                 igp_info = (union igp_info *)
 759                         (mode_info->atom_context->bios + data_offset);
 760                 switch (crev) {
 761                 case 6:
 762                         switch (id) {
 763                         case ASIC_INTERNAL_SS_ON_TMDS:
 764                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
 765                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
 766                                 break;
 767                         case ASIC_INTERNAL_SS_ON_HDMI:
 768                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
 769                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
 770                                 break;
 771                         case ASIC_INTERNAL_SS_ON_LVDS:
 772                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
 773                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
 774                                 break;
 775                         }
 776                         break;
 777                 case 7:
 778                         switch (id) {
 779                         case ASIC_INTERNAL_SS_ON_TMDS:
 780                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
 781                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
 782                                 break;
 783                         case ASIC_INTERNAL_SS_ON_HDMI:
 784                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
 785                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
 786                                 break;
 787                         case ASIC_INTERNAL_SS_ON_LVDS:
 788                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
 789                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
 790                                 break;
 791                         }
 792                         break;
 793                 case 8:
 794                         switch (id) {
 795                         case ASIC_INTERNAL_SS_ON_TMDS:
 796                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
 797                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
 798                                 break;
 799                         case ASIC_INTERNAL_SS_ON_HDMI:
 800                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
 801                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
 802                                 break;
 803                         case ASIC_INTERNAL_SS_ON_LVDS:
 804                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
 805                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
 806                                 break;
 807                         }
 808                         break;
 809                 case 9:
 810                         switch (id) {
 811                         case ASIC_INTERNAL_SS_ON_TMDS:
 812                                 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
 813                                 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
 814                                 break;
 815                         case ASIC_INTERNAL_SS_ON_HDMI:
 816                                 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
 817                                 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
 818                                 break;
 819                         case ASIC_INTERNAL_SS_ON_LVDS:
 820                                 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
 821                                 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
 822                                 break;
 823                         }
 824                         break;
 825                 default:
 826                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 827                         break;
 828                 }
 829                 if (percentage)
 830                         ss->percentage = percentage;
 831                 if (rate)
 832                         ss->rate = rate;
 833         }
 834 }
 835
 836 union asic_ss_info {
 837         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
 838         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
 839         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
 840 };
 841
 842 union asic_ss_assignment {
 843         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
 844         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
 845         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
 846 };
 847
 848 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
 849                                       struct amdgpu_atom_ss *ss,
 850                                       int id, u32 clock)
 851 {
 852         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 853         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
 854         uint16_t data_offset, size;
 855         union asic_ss_info *ss_info;
 856         union asic_ss_assignment *ss_assign;
 857         uint8_t frev, crev;
 858         int i, num_indices;
 859
 860         if (id == ASIC_INTERNAL_MEMORY_SS) {
 861                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
 862                         return false;
 863         }
 864         if (id == ASIC_INTERNAL_ENGINE_SS) {
 865                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
 866                         return false;
 867         }
 868
 869         memset(ss, 0, sizeof(struct amdgpu_atom_ss));
 870         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 871                                    &frev, &crev, &data_offset)) {
 872
 873                 ss_info =
 874                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
 875
 876                 switch (frev) {
 877                 case 1:
 878                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 879                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
 880
 881                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
 882                         for (i = 0; i < num_indices; i++) {
 883                                 if ((ss_assign->v1.ucClockIndication == id) &&
 884                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
 885                                         ss->percentage =
 886                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
 887                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
 888                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
 889                                         ss->percentage_divider = 100;
 890                                         return true;
 891                                 }
 892                                 ss_assign = (union asic_ss_assignment *)
 893                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
 894                         }
 895                         break;
 896                 case 2:
 897                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 898                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
 899                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
 900                         for (i = 0; i < num_indices; i++) {
 901                                 if ((ss_assign->v2.ucClockIndication == id) &&
 902                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
 903                                         ss->percentage =
 904                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
 905                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
 906                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
 907                                         ss->percentage_divider = 100;
 908                                         if ((crev == 2) &&
 909                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
 910                                              (id == ASIC_INTERNAL_MEMORY_SS)))
 911                                                 ss->rate /= 100;
 912                                         return true;
 913                                 }
 914                                 ss_assign = (union asic_ss_assignment *)
 915                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
 916                         }
 917                         break;
 918                 case 3:
 919                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 920                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
 921                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
 922                         for (i = 0; i < num_indices; i++) {
 923                                 if ((ss_assign->v3.ucClockIndication == id) &&
 924                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
 925                                         ss->percentage =
 926                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
 927                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
 928                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
 929                                         if (ss_assign->v3.ucSpreadSpectrumMode &
 930                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
 931                                                 ss->percentage_divider = 1000;
 932                                         else
 933                                                 ss->percentage_divider = 100;
 934                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
 935                                             (id == ASIC_INTERNAL_MEMORY_SS))
 936                                                 ss->rate /= 100;
 937                                         if (adev->flags & AMD_IS_APU)
 938                                                 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
 939                                         return true;
 940                                 }
 941                                 ss_assign = (union asic_ss_assignment *)
 942                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
 943                         }
 944                         break;
 945                 default:
 946                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
 947                         break;
 948                 }
 949
 950         }
 951         return false;
 952 }
 953
 954 union get_clock_dividers {
 955         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
 956         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
 957         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
 958         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
 959         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
 960         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
 961         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
 962 };
 963
 964 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
 965                                        u8 clock_type,
 966                                        u32 clock,
 967                                        bool strobe_mode,
 968                                        struct atom_clock_dividers *dividers)
 969 {
 970         union get_clock_dividers args;
 971         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
 972         u8 frev, crev;
 973
 974         memset(&args, 0, sizeof(args));
 975         memset(dividers, 0, sizeof(struct atom_clock_dividers));
 976
 977         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 978                 return -EINVAL;
 979
 980         switch (crev) {
 981         case 2:
 982         case 3:
 983         case 5:
 984                 /* r6xx, r7xx, evergreen, ni, si.
 985                  * TODO: add support for asic_type <= CHIP_RV770*/
 986                 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
 987                         args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
 988
 989                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 990
 991                         dividers->post_div = args.v3.ucPostDiv;
 992                         dividers->enable_post_div = (args.v3.ucCntlFlag &
 993                                                      ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
 994                         dividers->enable_dithen = (args.v3.ucCntlFlag &
 995                                                    ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
 996                         dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
 997                         dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
 998                         dividers->ref_div = args.v3.ucRefDiv;
 999                         dividers->vco_mode = (args.v3.ucCntlFlag &
1000                                               ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1001                 } else {
1002                         /* for SI we use ComputeMemoryClockParam for memory plls */
1003                         if (adev->asic_type >= CHIP_TAHITI)
1004                                 return -EINVAL;
1005                         args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1006                         if (strobe_mode)
1007                                 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1008
1009                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1010
1011                         dividers->post_div = args.v5.ucPostDiv;
1012                         dividers->enable_post_div = (args.v5.ucCntlFlag &
1013                                                      ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1014                         dividers->enable_dithen = (args.v5.ucCntlFlag &
1015                                                    ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1016                         dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1017                         dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1018                         dividers->ref_div = args.v5.ucRefDiv;
1019                         dividers->vco_mode = (args.v5.ucCntlFlag &
1020                                               ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1021                 }
1022                 break;
1023         case 4:
1024                 /* fusion */
1025                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
1026
1027                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1028
1029                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1030                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1031                 break;
1032         case 6:
1033                 /* CI */
1034                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1035                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1036                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
1037
1038                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1039
1040                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1041                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1042                 dividers->ref_div = args.v6_out.ucPllRefDiv;
1043                 dividers->post_div = args.v6_out.ucPllPostDiv;
1044                 dividers->flags = args.v6_out.ucPllCntlFlag;
1045                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1046                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1047                 break;
1048         default:
1049                 return -EINVAL;
1050         }
1051         return 0;
1052 }
1053
1054 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1055                                             u32 clock,
1056                                             bool strobe_mode,
1057                                             struct atom_mpll_param *mpll_param)
1058 {
1059         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1060         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1061         u8 frev, crev;
1062
1063         memset(&args, 0, sizeof(args));
1064         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1065
1066         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1067                 return -EINVAL;
1068
1069         switch (frev) {
1070         case 2:
1071                 switch (crev) {
1072                 case 1:
1073                         /* SI */
1074                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
1075                         args.ucInputFlag = 0;
1076                         if (strobe_mode)
1077                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1078
1079                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1080
1081                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1082                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1083                         mpll_param->post_div = args.ucPostDiv;
1084                         mpll_param->dll_speed = args.ucDllSpeed;
1085                         mpll_param->bwcntl = args.ucBWCntl;
1086                         mpll_param->vco_mode =
1087                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1088                         mpll_param->yclk_sel =
1089                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1090                         mpll_param->qdr =
1091                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1092                         mpll_param->half_rate =
1093                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1094                         break;
1095                 default:
1096                         return -EINVAL;
1097                 }
1098                 break;
1099         default:
1100                 return -EINVAL;
1101         }
1102         return 0;
1103 }
1104
1105 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
1106 {
1107         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1108         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1109
1110         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1111         return le32_to_cpu(args.ulReturnEngineClock);
1112 }
1113
1114 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
1115 {
1116         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1117         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1118
1119         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1120         return le32_to_cpu(args.ulReturnMemoryClock);
1121 }
1122
1123 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
1124                                       uint32_t eng_clock)
1125 {
1126         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1127         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1128
1129         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
1130
1131         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1132 }
1133
1134 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1135                                       uint32_t mem_clock)
1136 {
1137         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1138         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1139
1140         if (adev->flags & AMD_IS_APU)
1141                 return;
1142
1143         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
1144
1145         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1146 }
1147
1148 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1149                                              u32 eng_clock, u32 mem_clock)
1150 {
1151         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1152         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1153         u32 tmp;
1154
1155         memset(&args, 0, sizeof(args));
1156
1157         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1158         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1159
1160         args.ulTargetEngineClock = cpu_to_le32(tmp);
1161         if (mem_clock)
1162                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1163
1164         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1165 }
1166
1167 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1168                                           u16 *vddc, u16 *vddci, u16 *mvdd)
1169 {
1170         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1171         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1172         u8 frev, crev;
1173         u16 data_offset;
1174         union firmware_info *firmware_info;
1175
1176         *vddc = 0;
1177         *vddci = 0;
1178         *mvdd = 0;
1179
1180         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1181                                    &frev, &crev, &data_offset)) {
1182                 firmware_info =
1183                         (union firmware_info *)(mode_info->atom_context->bios +
1184                                                 data_offset);
1185                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1186                 if ((frev == 2) && (crev >= 2)) {
1187                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1188                         *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1189                 }
1190         }
1191 }
1192
1193 union set_voltage {
1194         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1195         struct _SET_VOLTAGE_PARAMETERS v1;
1196         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1197         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1198 };
1199
1200 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1201                              u16 voltage_id, u16 *voltage)
1202 {
1203         union set_voltage args;
1204         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1205         u8 frev, crev;
1206
1207         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1208                 return -EINVAL;
1209
1210         switch (crev) {
1211         case 1:
1212                 return -EINVAL;
1213         case 2:
1214                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1215                 args.v2.ucVoltageMode = 0;
1216                 args.v2.usVoltageLevel = 0;
1217
1218                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1219
1220                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1221                 break;
1222         case 3:
1223                 args.v3.ucVoltageType = voltage_type;
1224                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1225                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1226
1227                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1228
1229                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1230                 break;
1231         default:
1232                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1233                 return -EINVAL;
1234         }
1235
1236         return 0;
1237 }
1238
1239 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1240                                                       u16 *voltage,
1241                                                       u16 leakage_idx)
1242 {
1243         return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1244 }
1245
1246 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
1247                                  u16 voltage_level,
1248                                  u8 voltage_type)
1249 {
1250         union set_voltage args;
1251         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1252         u8 frev, crev, volt_index = voltage_level;
1253
1254         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1255                 return;
1256
1257         /* 0xff01 is a flag rather then an actual voltage */
1258         if (voltage_level == 0xff01)
1259                 return;
1260
1261         switch (crev) {
1262         case 1:
1263                 args.v1.ucVoltageType = voltage_type;
1264                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
1265                 args.v1.ucVoltageIndex = volt_index;
1266                 break;
1267         case 2:
1268                 args.v2.ucVoltageType = voltage_type;
1269                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
1270                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
1271                 break;
1272         case 3:
1273                 args.v3.ucVoltageType = voltage_type;
1274                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
1275                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
1276                 break;
1277         default:
1278                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1279                 return;
1280         }
1281
1282         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1283 }
1284
1285 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1286                                               u16 *leakage_id)
1287 {
1288         union set_voltage args;
1289         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1290         u8 frev, crev;
1291
1292         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1293                 return -EINVAL;
1294
1295         switch (crev) {
1296         case 3:
1297         case 4:
1298                 args.v3.ucVoltageType = 0;
1299                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1300                 args.v3.usVoltageLevel = 0;
1301
1302                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1303
1304                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1305                 break;
1306         default:
1307                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1308                 return -EINVAL;
1309         }
1310
1311         return 0;
1312 }
1313
1314 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1315                                                              u16 *vddc, u16 *vddci,
1316                                                              u16 virtual_voltage_id,
1317                                                              u16 vbios_voltage_id)
1318 {
1319         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1320         u8 frev, crev;
1321         u16 data_offset, size;
1322         int i, j;
1323         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1324         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1325
1326         *vddc = 0;
1327         *vddci = 0;
1328
1329         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1330                                     &frev, &crev, &data_offset))
1331                 return -EINVAL;
1332
1333         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1334                 (adev->mode_info.atom_context->bios + data_offset);
1335
1336         switch (frev) {
1337         case 1:
1338                 return -EINVAL;
1339         case 2:
1340                 switch (crev) {
1341                 case 1:
1342                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1343                                 return -EINVAL;
1344                         leakage_bin = (u16 *)
1345                                 (adev->mode_info.atom_context->bios + data_offset +
1346                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
1347                         vddc_id_buf = (u16 *)
1348                                 (adev->mode_info.atom_context->bios + data_offset +
1349                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1350                         vddc_buf = (u16 *)
1351                                 (adev->mode_info.atom_context->bios + data_offset +
1352                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1353                         vddci_id_buf = (u16 *)
1354                                 (adev->mode_info.atom_context->bios + data_offset +
1355                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1356                         vddci_buf = (u16 *)
1357                                 (adev->mode_info.atom_context->bios + data_offset +
1358                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1359
1360                         if (profile->ucElbVDDC_Num > 0) {
1361                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1362                                         if (vddc_id_buf[i] == virtual_voltage_id) {
1363                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1364                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1365                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1366                                                                 break;
1367                                                         }
1368                                                 }
1369                                                 break;
1370                                         }
1371                                 }
1372                         }
1373                         if (profile->ucElbVDDCI_Num > 0) {
1374                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1375                                         if (vddci_id_buf[i] == virtual_voltage_id) {
1376                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1377                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1378                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1379                                                                 break;
1380                                                         }
1381                                                 }
1382                                                 break;
1383                                         }
1384                                 }
1385                         }
1386                         break;
1387                 default:
1388                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1389                         return -EINVAL;
1390                 }
1391                 break;
1392         default:
1393                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1394                 return -EINVAL;
1395         }
1396
1397         return 0;
1398 }
1399
1400 union get_voltage_info {
1401         struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1402         struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1403 };
1404
1405 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1406                                     u16 virtual_voltage_id,
1407                                     u16 *voltage)
1408 {
1409         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1410         u32 entry_id;
1411         u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1412         union get_voltage_info args;
1413
1414         for (entry_id = 0; entry_id < count; entry_id++) {
1415                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1416                     virtual_voltage_id)
1417                         break;
1418         }
1419
1420         if (entry_id >= count)
1421                 return -EINVAL;
1422
1423         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1424         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1425         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1426         args.in.ulSCLKFreq =
1427                 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1428
1429         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1430
1431         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1432
1433         return 0;
1434 }
1435
1436 union voltage_object_info {
1437         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1438         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1439         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1440 };
1441
1442 union voltage_object {
1443         struct _ATOM_VOLTAGE_OBJECT v1;
1444         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1445         union _ATOM_VOLTAGE_OBJECT_V3 v3;
1446 };
1447
1448
1449 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1450                                                                         u8 voltage_type, u8 voltage_mode)
1451 {
1452         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1453         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1454         u8 *start = (u8*)v3;
1455
1456         while (offset < size) {
1457                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1458                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1459                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1460                         return vo;
1461                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1462         }
1463         return NULL;
1464 }
1465
1466 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1467                               u8 voltage_type,
1468                               u8 *svd_gpio_id, u8 *svc_gpio_id)
1469 {
1470         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1471         u8 frev, crev;
1472         u16 data_offset, size;
1473         union voltage_object_info *voltage_info;
1474         union voltage_object *voltage_object = NULL;
1475
1476         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1477                                    &frev, &crev, &data_offset)) {
1478                 voltage_info = (union voltage_object_info *)
1479                         (adev->mode_info.atom_context->bios + data_offset);
1480
1481                 switch (frev) {
1482                 case 3:
1483                         switch (crev) {
1484                         case 1:
1485                                 voltage_object = (union voltage_object *)
1486                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1487                                                                       voltage_type,
1488                                                                       VOLTAGE_OBJ_SVID2);
1489                                 if (voltage_object) {
1490                                         *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1491                                         *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1492                                 } else {
1493                                         return -EINVAL;
1494                                 }
1495                                 break;
1496                         default:
1497                                 DRM_ERROR("unknown voltage object table\n");
1498                                 return -EINVAL;
1499                         }
1500                         break;
1501                 default:
1502                         DRM_ERROR("unknown voltage object table\n");
1503                         return -EINVAL;
1504                 }
1505
1506         }
1507         return 0;
1508 }
1509
1510 bool
1511 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1512                                 u8 voltage_type, u8 voltage_mode)
1513 {
1514         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1515         u8 frev, crev;
1516         u16 data_offset, size;
1517         union voltage_object_info *voltage_info;
1518
1519         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1520                                    &frev, &crev, &data_offset)) {
1521                 voltage_info = (union voltage_object_info *)
1522                         (adev->mode_info.atom_context->bios + data_offset);
1523
1524                 switch (frev) {
1525                 case 3:
1526                         switch (crev) {
1527                         case 1:
1528                                 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1529                                                                   voltage_type, voltage_mode))
1530                                         return true;
1531                                 break;
1532                         default:
1533                                 DRM_ERROR("unknown voltage object table\n");
1534                                 return false;
1535                         }
1536                         break;
1537                 default:
1538                         DRM_ERROR("unknown voltage object table\n");
1539                         return false;
1540                 }
1541
1542         }
1543         return false;
1544 }
1545
1546 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1547                                       u8 voltage_type, u8 voltage_mode,
1548                                       struct atom_voltage_table *voltage_table)
1549 {
1550         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1551         u8 frev, crev;
1552         u16 data_offset, size;
1553         int i;
1554         union voltage_object_info *voltage_info;
1555         union voltage_object *voltage_object = NULL;
1556
1557         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1558                                    &frev, &crev, &data_offset)) {
1559                 voltage_info = (union voltage_object_info *)
1560                         (adev->mode_info.atom_context->bios + data_offset);
1561
1562                 switch (frev) {
1563                 case 3:
1564                         switch (crev) {
1565                         case 1:
1566                                 voltage_object = (union voltage_object *)
1567                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1568                                                                       voltage_type, voltage_mode);
1569                                 if (voltage_object) {
1570                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1571                                                 &voltage_object->v3.asGpioVoltageObj;
1572                                         VOLTAGE_LUT_ENTRY_V2 *lut;
1573                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1574                                                 return -EINVAL;
1575                                         lut = &gpio->asVolGpioLut[0];
1576                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1577                                                 voltage_table->entries[i].value =
1578                                                         le16_to_cpu(lut->usVoltageValue);
1579                                                 voltage_table->entries[i].smio_low =
1580                                                         le32_to_cpu(lut->ulVoltageId);
1581                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1582                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1583                                         }
1584                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1585                                         voltage_table->count = gpio->ucGpioEntryNum;
1586                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
1587                                         return 0;
1588                                 }
1589                                 break;
1590                         default:
1591                                 DRM_ERROR("unknown voltage object table\n");
1592                                 return -EINVAL;
1593                         }
1594                         break;
1595                 default:
1596                         DRM_ERROR("unknown voltage object table\n");
1597                         return -EINVAL;
1598                 }
1599         }
1600         return -EINVAL;
1601 }
1602
1603 union vram_info {
1604         struct _ATOM_VRAM_INFO_V3 v1_3;
1605         struct _ATOM_VRAM_INFO_V4 v1_4;
1606         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1607 };
1608
1609 #define MEM_ID_MASK           0xff000000
1610 #define MEM_ID_SHIFT          24
1611 #define CLOCK_RANGE_MASK      0x00ffffff
1612 #define CLOCK_RANGE_SHIFT     0
1613 #define LOW_NIBBLE_MASK       0xf
1614 #define DATA_EQU_PREV         0
1615 #define DATA_FROM_TABLE       4
1616
1617 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1618                                       u8 module_index,
1619                                       struct atom_mc_reg_table *reg_table)
1620 {
1621         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1622         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1623         u32 i = 0, j;
1624         u16 data_offset, size;
1625         union vram_info *vram_info;
1626
1627         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1628
1629         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1630                                    &frev, &crev, &data_offset)) {
1631                 vram_info = (union vram_info *)
1632                         (adev->mode_info.atom_context->bios + data_offset);
1633                 switch (frev) {
1634                 case 1:
1635                         DRM_ERROR("old table version %d, %d\n", frev, crev);
1636                         return -EINVAL;
1637                 case 2:
1638                         switch (crev) {
1639                         case 1:
1640                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1641                                         ATOM_INIT_REG_BLOCK *reg_block =
1642                                                 (ATOM_INIT_REG_BLOCK *)
1643                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1644                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1645                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1646                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
1647                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
1648                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1649                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1650                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1651                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1652                                                 return -EINVAL;
1653                                         while (i < num_entries) {
1654                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1655                                                         break;
1656                                                 reg_table->mc_reg_address[i].s1 =
1657                                                         (u16)(le16_to_cpu(format->usRegIndex));
1658                                                 reg_table->mc_reg_address[i].pre_reg_data =
1659                                                         (u8)(format->ucPreRegDataLength);
1660                                                 i++;
1661                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1662                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1663                                         }
1664                                         reg_table->last = i;
1665                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1666                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1667                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1668                                                                 >> MEM_ID_SHIFT);
1669                                                 if (module_index == t_mem_id) {
1670                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1671                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1672                                                                       >> CLOCK_RANGE_SHIFT);
1673                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
1674                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1675                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1676                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1677                                                                         j++;
1678                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1679                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1680                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1681                                                                 }
1682                                                         }
1683                                                         num_ranges++;
1684                                                 }
1685                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1686                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1687                                         }
1688                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1689                                                 return -EINVAL;
1690                                         reg_table->num_entries = num_ranges;
1691                                 } else
1692                                         return -EINVAL;
1693                                 break;
1694                         default:
1695                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1696                                 return -EINVAL;
1697                         }
1698                         break;
1699                 default:
1700                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1701                         return -EINVAL;
1702                 }
1703                 return 0;
1704         }
1705         return -EINVAL;
1706 }
1707
1708 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1709 {
1710         int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1711         u8 frev, crev;
1712         u16 data_offset, size;
1713
1714         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1715                                           &frev, &crev, &data_offset))
1716                 return true;
1717
1718         return false;
1719 }
1720
1721 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1722 {
1723         uint32_t bios_6_scratch;
1724
1725         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1726
1727         if (lock) {
1728                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1729                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1730         } else {
1731                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1732                 bios_6_scratch |= ATOM_S6_ACC_MODE;
1733         }
1734
1735         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1736 }
1737
1738 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1739 {
1740         uint32_t bios_2_scratch, bios_6_scratch;
1741
1742         bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1743         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1744
1745         /* let the bios control the backlight */
1746         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1747
1748         /* tell the bios not to handle mode switching */
1749         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1750
1751         /* clear the vbios dpms state */
1752         bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1753
1754         WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1755         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1756 }
1757
1758 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1759 {
1760         int i;
1761
1762         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1763                 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1764 }
1765
1766 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1767 {
1768         int i;
1769
1770         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1771                 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1772 }
1773
1774 /* Atom needs data in little endian format
1775  * so swap as appropriate when copying data to
1776  * or from atom. Note that atom operates on
1777  * dw units.
1778  */
1779 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1780 {
1781 #ifdef __BIG_ENDIAN
1782         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
1783         u32 *dst32, *src32;
1784         int i;
1785
1786         memcpy(src_tmp, src, num_bytes);
1787         src32 = (u32 *)src_tmp;
1788         dst32 = (u32 *)dst_tmp;
1789         if (to_le) {
1790                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1791                         dst32[i] = cpu_to_le32(src32[i]);
1792                 memcpy(dst, dst_tmp, num_bytes);
1793         } else {
1794                 u8 dws = num_bytes & ~3;
1795                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1796                         dst32[i] = le32_to_cpu(src32[i]);
1797                 memcpy(dst, dst_tmp, dws);
1798                 if (num_bytes % 4) {
1799                         for (i = 0; i < (num_bytes % 4); i++)
1800                                 dst[dws+i] = dst_tmp[dws+i];
1801                 }
1802         }
1803 #else
1804         memcpy(dst, src, num_bytes);
1805 #endif
1806 }