drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "amdgpu_amdkfd.h"
  50 #include "bif/bif_4_1_d.h"
  51
  52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  53
  54 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  55                              struct ttm_mem_reg *mem, unsigned num_pages,
  56                              uint64_t offset, unsigned window,
  57                              struct amdgpu_ring *ring,
  58                              uint64_t *addr);
  59
  60 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  61 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  62
  63 /*
  64  * Global memory.
  65  */
  66 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  67 {
  68         return ttm_mem_global_init(ref->object);
  69 }
  70
  71 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  72 {
  73         ttm_mem_global_release(ref->object);
  74 }
  75
  76 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  77 {
  78         struct drm_global_reference *global_ref;
  79         struct amdgpu_ring *ring;
  80         struct drm_sched_rq *rq;
  81         int r;
  82
  83         adev->mman.mem_global_referenced = false;
  84         global_ref = &adev->mman.mem_global_ref;
  85         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  86         global_ref->size = sizeof(struct ttm_mem_global);
  87         global_ref->init = &amdgpu_ttm_mem_global_init;
  88         global_ref->release = &amdgpu_ttm_mem_global_release;
  89         r = drm_global_item_ref(global_ref);
  90         if (r) {
  91                 DRM_ERROR("Failed setting up TTM memory accounting "
  92                           "subsystem.\n");
  93                 goto error_mem;
  94         }
  95
  96         adev->mman.bo_global_ref.mem_glob =
  97                 adev->mman.mem_global_ref.object;
  98         global_ref = &adev->mman.bo_global_ref.ref;
  99         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 100         global_ref->size = sizeof(struct ttm_bo_global);
 101         global_ref->init = &ttm_bo_global_init;
 102         global_ref->release = &ttm_bo_global_release;
 103         r = drm_global_item_ref(global_ref);
 104         if (r) {
 105                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 106                 goto error_bo;
 107         }
 108
 109         mutex_init(&adev->mman.gtt_window_lock);
 110
 111         ring = adev->mman.buffer_funcs_ring;
 112         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
 113         r = drm_sched_entity_init(&ring->sched, &adev->mman.entity,
 114                                   rq, amdgpu_sched_jobs, NULL);
 115         if (r) {
 116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 117                 goto error_entity;
 118         }
 119
 120         adev->mman.mem_global_referenced = true;
 121
 122         return 0;
 123
 124 error_entity:
 125         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 126 error_bo:
 127         drm_global_item_unref(&adev->mman.mem_global_ref);
 128 error_mem:
 129         return r;
 130 }
 131
 132 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 133 {
 134         if (adev->mman.mem_global_referenced) {
 135                 drm_sched_entity_fini(adev->mman.entity.sched,
 136                                       &adev->mman.entity);
 137                 mutex_destroy(&adev->mman.gtt_window_lock);
 138                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 139                 drm_global_item_unref(&adev->mman.mem_global_ref);
 140                 adev->mman.mem_global_referenced = false;
 141         }
 142 }
 143
 144 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 145 {
 146         return 0;
 147 }
 148
 149 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 150                                 struct ttm_mem_type_manager *man)
 151 {
 152         struct amdgpu_device *adev;
 153
 154         adev = amdgpu_ttm_adev(bdev);
 155
 156         switch (type) {
 157         case TTM_PL_SYSTEM:
 158                 /* System memory */
 159                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 160                 man->available_caching = TTM_PL_MASK_CACHING;
 161                 man->default_caching = TTM_PL_FLAG_CACHED;
 162                 break;
 163         case TTM_PL_TT:
 164                 man->func = &amdgpu_gtt_mgr_func;
 165                 man->gpu_offset = adev->gmc.gart_start;
 166                 man->available_caching = TTM_PL_MASK_CACHING;
 167                 man->default_caching = TTM_PL_FLAG_CACHED;
 168                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 169                 break;
 170         case TTM_PL_VRAM:
 171                 /* "On-card" video ram */
 172                 man->func = &amdgpu_vram_mgr_func;
 173                 man->gpu_offset = adev->gmc.vram_start;
 174                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 175                              TTM_MEMTYPE_FLAG_MAPPABLE;
 176                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 177                 man->default_caching = TTM_PL_FLAG_WC;
 178                 break;
 179         case AMDGPU_PL_GDS:
 180         case AMDGPU_PL_GWS:
 181         case AMDGPU_PL_OA:
 182                 /* On-chip GDS memory*/
 183                 man->func = &ttm_bo_manager_func;
 184                 man->gpu_offset = 0;
 185                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 186                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 187                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 188                 break;
 189         default:
 190                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 191                 return -EINVAL;
 192         }
 193         return 0;
 194 }
 195
 196 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 197                                 struct ttm_placement *placement)
 198 {
 199         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 200         struct amdgpu_bo *abo;
 201         static const struct ttm_place placements = {
 202                 .fpfn = 0,
 203                 .lpfn = 0,
 204                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 205         };
 206
 207         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 208                 placement->placement = &placements;
 209                 placement->busy_placement = &placements;
 210                 placement->num_placement = 1;
 211                 placement->num_busy_placement = 1;
 212                 return;
 213         }
 214         abo = ttm_to_amdgpu_bo(bo);
 215         switch (bo->mem.mem_type) {
 216         case TTM_PL_VRAM:
 217                 if (!adev->mman.buffer_funcs_enabled) {
 218                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 219                 } else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 220                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 221                         unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 222                         struct drm_mm_node *node = bo->mem.mm_node;
 223                         unsigned long pages_left;
 224
 225                         for (pages_left = bo->mem.num_pages;
 226                              pages_left;
 227                              pages_left -= node->size, node++) {
 228                                 if (node->start < fpfn)
 229                                         break;
 230                         }
 231
 232                         if (!pages_left)
 233                                 goto gtt;
 234
 235                         /* Try evicting to the CPU inaccessible part of VRAM
 236                          * first, but only set GTT as busy placement, so this
 237                          * BO will be evicted to GTT rather than causing other
 238                          * BOs to be evicted from VRAM
 239                          */
 240                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 241                                                          AMDGPU_GEM_DOMAIN_GTT);
 242                         abo->placements[0].fpfn = fpfn;
 243                         abo->placements[0].lpfn = 0;
 244                         abo->placement.busy_placement = &abo->placements[1];
 245                         abo->placement.num_busy_placement = 1;
 246                 } else {
 247 gtt:
 248                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 249                 }
 250                 break;
 251         case TTM_PL_TT:
 252         default:
 253                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 254         }
 255         *placement = abo->placement;
 256 }
 257
 258 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 259 {
 260         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 261
 262         /*
 263          * Don't verify access for KFD BOs. They don't have a GEM
 264          * object associated with them.
 265          */
 266         if (abo->kfd_bo)
 267                 return 0;
 268
 269         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 270                 return -EPERM;
 271         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 272                                           filp->private_data);
 273 }
 274
 275 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 276                              struct ttm_mem_reg *new_mem)
 277 {
 278         struct ttm_mem_reg *old_mem = &bo->mem;
 279
 280         BUG_ON(old_mem->mm_node != NULL);
 281         *old_mem = *new_mem;
 282         new_mem->mm_node = NULL;
 283 }
 284
 285 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 286                                     struct drm_mm_node *mm_node,
 287                                     struct ttm_mem_reg *mem)
 288 {
 289         uint64_t addr = 0;
 290
 291         if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
 292                 addr = mm_node->start << PAGE_SHIFT;
 293                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 294         }
 295         return addr;
 296 }
 297
 298 /**
 299  * amdgpu_find_mm_node - Helper function finds the drm_mm_node
 300  *  corresponding to @offset. It also modifies the offset to be
 301  *  within the drm_mm_node returned
 302  */
 303 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 304                                                unsigned long *offset)
 305 {
 306         struct drm_mm_node *mm_node = mem->mm_node;
 307
 308         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 309                 *offset -= (mm_node->size << PAGE_SHIFT);
 310                 ++mm_node;
 311         }
 312         return mm_node;
 313 }
 314
 315 /**
 316  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 317  *
 318  * The function copies @size bytes from {src->mem + src->offset} to
 319  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 320  * move and different for a BO to BO copy.
 321  *
 322  * @f: Returns the last fence if multiple jobs are submitted.
 323  */
 324 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 325                                struct amdgpu_copy_mem *src,
 326                                struct amdgpu_copy_mem *dst,
 327                                uint64_t size,
 328                                struct reservation_object *resv,
 329                                struct dma_fence **f)
 330 {
 331         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 332         struct drm_mm_node *src_mm, *dst_mm;
 333         uint64_t src_node_start, dst_node_start, src_node_size,
 334                  dst_node_size, src_page_offset, dst_page_offset;
 335         struct dma_fence *fence = NULL;
 336         int r = 0;
 337         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 338                                         AMDGPU_GPU_PAGE_SIZE);
 339
 340         if (!adev->mman.buffer_funcs_enabled) {
 341                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 342                 return -EINVAL;
 343         }
 344
 345         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 346         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 347                                              src->offset;
 348         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 349         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 350
 351         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 352         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 353                                              dst->offset;
 354         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 355         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 356
 357         mutex_lock(&adev->mman.gtt_window_lock);
 358
 359         while (size) {
 360                 unsigned long cur_size;
 361                 uint64_t from = src_node_start, to = dst_node_start;
 362                 struct dma_fence *next;
 363
 364                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 365                  * begins at an offset, then adjust the size accordingly
 366                  */
 367                 cur_size = min3(min(src_node_size, dst_node_size), size,
 368                                 GTT_MAX_BYTES);
 369                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 370                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 371                         cur_size -= max(src_page_offset, dst_page_offset);
 372
 373                 /* Map only what needs to be accessed. Map src to window 0 and
 374                  * dst to window 1
 375                  */
 376                 if (src->mem->mem_type == TTM_PL_TT &&
 377                     !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
 378                         r = amdgpu_map_buffer(src->bo, src->mem,
 379                                         PFN_UP(cur_size + src_page_offset),
 380                                         src_node_start, 0, ring,
 381                                         &from);
 382                         if (r)
 383                                 goto error;
 384                         /* Adjust the offset because amdgpu_map_buffer returns
 385                          * start of mapped page
 386                          */
 387                         from += src_page_offset;
 388                 }
 389
 390                 if (dst->mem->mem_type == TTM_PL_TT &&
 391                     !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
 392                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 393                                         PFN_UP(cur_size + dst_page_offset),
 394                                         dst_node_start, 1, ring,
 395                                         &to);
 396                         if (r)
 397                                 goto error;
 398                         to += dst_page_offset;
 399                 }
 400
 401                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 402                                        resv, &next, false, true);
 403                 if (r)
 404                         goto error;
 405
 406                 dma_fence_put(fence);
 407                 fence = next;
 408
 409                 size -= cur_size;
 410                 if (!size)
 411                         break;
 412
 413                 src_node_size -= cur_size;
 414                 if (!src_node_size) {
 415                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 416                                                              src->mem);
 417                         src_node_size = (src_mm->size << PAGE_SHIFT);
 418                 } else {
 419                         src_node_start += cur_size;
 420                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 421                 }
 422                 dst_node_size -= cur_size;
 423                 if (!dst_node_size) {
 424                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 425                                                              dst->mem);
 426                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 427                 } else {
 428                         dst_node_start += cur_size;
 429                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 430                 }
 431         }
 432 error:
 433         mutex_unlock(&adev->mman.gtt_window_lock);
 434         if (f)
 435                 *f = dma_fence_get(fence);
 436         dma_fence_put(fence);
 437         return r;
 438 }
 439
 440
 441 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 442                             bool evict, bool no_wait_gpu,
 443                             struct ttm_mem_reg *new_mem,
 444                             struct ttm_mem_reg *old_mem)
 445 {
 446         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 447         struct amdgpu_copy_mem src, dst;
 448         struct dma_fence *fence = NULL;
 449         int r;
 450
 451         src.bo = bo;
 452         dst.bo = bo;
 453         src.mem = old_mem;
 454         dst.mem = new_mem;
 455         src.offset = 0;
 456         dst.offset = 0;
 457
 458         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 459                                        new_mem->num_pages << PAGE_SHIFT,
 460                                        bo->resv, &fence);
 461         if (r)
 462                 goto error;
 463
 464         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 465         dma_fence_put(fence);
 466         return r;
 467
 468 error:
 469         if (fence)
 470                 dma_fence_wait(fence, false);
 471         dma_fence_put(fence);
 472         return r;
 473 }
 474
 475 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 476                                 struct ttm_operation_ctx *ctx,
 477                                 struct ttm_mem_reg *new_mem)
 478 {
 479         struct amdgpu_device *adev;
 480         struct ttm_mem_reg *old_mem = &bo->mem;
 481         struct ttm_mem_reg tmp_mem;
 482         struct ttm_place placements;
 483         struct ttm_placement placement;
 484         int r;
 485
 486         adev = amdgpu_ttm_adev(bo->bdev);
 487         tmp_mem = *new_mem;
 488         tmp_mem.mm_node = NULL;
 489         placement.num_placement = 1;
 490         placement.placement = &placements;
 491         placement.num_busy_placement = 1;
 492         placement.busy_placement = &placements;
 493         placements.fpfn = 0;
 494         placements.lpfn = 0;
 495         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 496         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 497         if (unlikely(r)) {
 498                 return r;
 499         }
 500
 501         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 502         if (unlikely(r)) {
 503                 goto out_cleanup;
 504         }
 505
 506         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 507         if (unlikely(r)) {
 508                 goto out_cleanup;
 509         }
 510         r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, &tmp_mem, old_mem);
 511         if (unlikely(r)) {
 512                 goto out_cleanup;
 513         }
 514         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 515 out_cleanup:
 516         ttm_bo_mem_put(bo, &tmp_mem);
 517         return r;
 518 }
 519
 520 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 521                                 struct ttm_operation_ctx *ctx,
 522                                 struct ttm_mem_reg *new_mem)
 523 {
 524         struct amdgpu_device *adev;
 525         struct ttm_mem_reg *old_mem = &bo->mem;
 526         struct ttm_mem_reg tmp_mem;
 527         struct ttm_placement placement;
 528         struct ttm_place placements;
 529         int r;
 530
 531         adev = amdgpu_ttm_adev(bo->bdev);
 532         tmp_mem = *new_mem;
 533         tmp_mem.mm_node = NULL;
 534         placement.num_placement = 1;
 535         placement.placement = &placements;
 536         placement.num_busy_placement = 1;
 537         placement.busy_placement = &placements;
 538         placements.fpfn = 0;
 539         placements.lpfn = 0;
 540         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 541         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 542         if (unlikely(r)) {
 543                 return r;
 544         }
 545         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 546         if (unlikely(r)) {
 547                 goto out_cleanup;
 548         }
 549         r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem);
 550         if (unlikely(r)) {
 551                 goto out_cleanup;
 552         }
 553 out_cleanup:
 554         ttm_bo_mem_put(bo, &tmp_mem);
 555         return r;
 556 }
 557
 558 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 559                           struct ttm_operation_ctx *ctx,
 560                           struct ttm_mem_reg *new_mem)
 561 {
 562         struct amdgpu_device *adev;
 563         struct amdgpu_bo *abo;
 564         struct ttm_mem_reg *old_mem = &bo->mem;
 565         int r;
 566
 567         /* Can't move a pinned BO */
 568         abo = ttm_to_amdgpu_bo(bo);
 569         if (WARN_ON_ONCE(abo->pin_count > 0))
 570                 return -EINVAL;
 571
 572         adev = amdgpu_ttm_adev(bo->bdev);
 573
 574         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 575                 amdgpu_move_null(bo, new_mem);
 576                 return 0;
 577         }
 578         if ((old_mem->mem_type == TTM_PL_TT &&
 579              new_mem->mem_type == TTM_PL_SYSTEM) ||
 580             (old_mem->mem_type == TTM_PL_SYSTEM &&
 581              new_mem->mem_type == TTM_PL_TT)) {
 582                 /* bind is enough */
 583                 amdgpu_move_null(bo, new_mem);
 584                 return 0;
 585         }
 586
 587         if (!adev->mman.buffer_funcs_enabled)
 588                 goto memcpy;
 589
 590         if (old_mem->mem_type == TTM_PL_VRAM &&
 591             new_mem->mem_type == TTM_PL_SYSTEM) {
 592                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 593         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 594                    new_mem->mem_type == TTM_PL_VRAM) {
 595                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 596         } else {
 597                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 598                                      new_mem, old_mem);
 599         }
 600
 601         if (r) {
 602 memcpy:
 603                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 604                 if (r) {
 605                         return r;
 606                 }
 607         }
 608
 609         if (bo->type == ttm_bo_type_device &&
 610             new_mem->mem_type == TTM_PL_VRAM &&
 611             old_mem->mem_type != TTM_PL_VRAM) {
 612                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 613                  * accesses the BO after it's moved.
 614                  */
 615                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 616         }
 617
 618         /* update statistics */
 619         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 620         return 0;
 621 }
 622
 623 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 624 {
 625         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 626         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 627         struct drm_mm_node *mm_node = mem->mm_node;
 628
 629         mem->bus.addr = NULL;
 630         mem->bus.offset = 0;
 631         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 632         mem->bus.base = 0;
 633         mem->bus.is_iomem = false;
 634         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 635                 return -EINVAL;
 636         switch (mem->mem_type) {
 637         case TTM_PL_SYSTEM:
 638                 /* system memory */
 639                 return 0;
 640         case TTM_PL_TT:
 641                 break;
 642         case TTM_PL_VRAM:
 643                 mem->bus.offset = mem->start << PAGE_SHIFT;
 644                 /* check if it's visible */
 645                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 646                         return -EINVAL;
 647                 /* Only physically contiguous buffers apply. In a contiguous
 648                  * buffer, size of the first mm_node would match the number of
 649                  * pages in ttm_mem_reg.
 650                  */
 651                 if (adev->mman.aper_base_kaddr &&
 652                     (mm_node->size == mem->num_pages))
 653                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 654                                         mem->bus.offset;
 655
 656                 mem->bus.base = adev->gmc.aper_base;
 657                 mem->bus.is_iomem = true;
 658                 break;
 659         default:
 660                 return -EINVAL;
 661         }
 662         return 0;
 663 }
 664
 665 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 666 {
 667 }
 668
 669 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 670                                            unsigned long page_offset)
 671 {
 672         struct drm_mm_node *mm;
 673         unsigned long offset = (page_offset << PAGE_SHIFT);
 674
 675         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 676         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 677                 (offset >> PAGE_SHIFT);
 678 }
 679
 680 /*
 681  * TTM backend functions.
 682  */
 683 struct amdgpu_ttm_gup_task_list {
 684         struct list_head        list;
 685         struct task_struct      *task;
 686 };
 687
 688 struct amdgpu_ttm_tt {
 689         struct ttm_dma_tt       ttm;
 690         u64                     offset;
 691         uint64_t                userptr;
 692         struct mm_struct        *usermm;
 693         uint32_t                userflags;
 694         spinlock_t              guptasklock;
 695         struct list_head        guptasks;
 696         atomic_t                mmu_invalidations;
 697         uint32_t                last_set_pages;
 698 };
 699
 700 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 701 {
 702         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 703         unsigned int flags = 0;
 704         unsigned pinned = 0;
 705         int r;
 706
 707         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 708                 flags |= FOLL_WRITE;
 709
 710         down_read(&current->mm->mmap_sem);
 711
 712         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 713                 /* check that we only use anonymous memory
 714                    to prevent problems with writeback */
 715                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 716                 struct vm_area_struct *vma;
 717
 718                 vma = find_vma(gtt->usermm, gtt->userptr);
 719                 if (!vma || vma->vm_file || vma->vm_end < end) {
 720                         up_read(&current->mm->mmap_sem);
 721                         return -EPERM;
 722                 }
 723         }
 724
 725         do {
 726                 unsigned num_pages = ttm->num_pages - pinned;
 727                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 728                 struct page **p = pages + pinned;
 729                 struct amdgpu_ttm_gup_task_list guptask;
 730
 731                 guptask.task = current;
 732                 spin_lock(&gtt->guptasklock);
 733                 list_add(&guptask.list, &gtt->guptasks);
 734                 spin_unlock(&gtt->guptasklock);
 735
 736                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 737
 738                 spin_lock(&gtt->guptasklock);
 739                 list_del(&guptask.list);
 740                 spin_unlock(&gtt->guptasklock);
 741
 742                 if (r < 0)
 743                         goto release_pages;
 744
 745                 pinned += r;
 746
 747         } while (pinned < ttm->num_pages);
 748
 749         up_read(&current->mm->mmap_sem);
 750         return 0;
 751
 752 release_pages:
 753         release_pages(pages, pinned);
 754         up_read(&current->mm->mmap_sem);
 755         return r;
 756 }
 757
 758 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 759 {
 760         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 761         unsigned i;
 762
 763         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 764         for (i = 0; i < ttm->num_pages; ++i) {
 765                 if (ttm->pages[i])
 766                         put_page(ttm->pages[i]);
 767
 768                 ttm->pages[i] = pages ? pages[i] : NULL;
 769         }
 770 }
 771
 772 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 773 {
 774         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 775         unsigned i;
 776
 777         for (i = 0; i < ttm->num_pages; ++i) {
 778                 struct page *page = ttm->pages[i];
 779
 780                 if (!page)
 781                         continue;
 782
 783                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 784                         set_page_dirty(page);
 785
 786                 mark_page_accessed(page);
 787         }
 788 }
 789
 790 /* prepare the sg table with the user pages */
 791 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 792 {
 793         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 794         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 795         unsigned nents;
 796         int r;
 797
 798         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 799         enum dma_data_direction direction = write ?
 800                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 801
 802         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 803                                       ttm->num_pages << PAGE_SHIFT,
 804                                       GFP_KERNEL);
 805         if (r)
 806                 goto release_sg;
 807
 808         r = -ENOMEM;
 809         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 810         if (nents != ttm->sg->nents)
 811                 goto release_sg;
 812
 813         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 814                                          gtt->ttm.dma_address, ttm->num_pages);
 815
 816         return 0;
 817
 818 release_sg:
 819         kfree(ttm->sg);
 820         return r;
 821 }
 822
 823 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 824 {
 825         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 826         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 827
 828         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 829         enum dma_data_direction direction = write ?
 830                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 831
 832         /* double check that we don't free the table twice */
 833         if (!ttm->sg->sgl)
 834                 return;
 835
 836         /* free the sg table and pages again */
 837         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 838
 839         amdgpu_ttm_tt_mark_user_pages(ttm);
 840
 841         sg_free_table(ttm->sg);
 842 }
 843
 844 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 845                                    struct ttm_mem_reg *bo_mem)
 846 {
 847         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 848         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 849         uint64_t flags;
 850         int r = 0;
 851
 852         if (gtt->userptr) {
 853                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 854                 if (r) {
 855                         DRM_ERROR("failed to pin userptr\n");
 856                         return r;
 857                 }
 858         }
 859         if (!ttm->num_pages) {
 860                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 861                      ttm->num_pages, bo_mem, ttm);
 862         }
 863
 864         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 865             bo_mem->mem_type == AMDGPU_PL_GWS ||
 866             bo_mem->mem_type == AMDGPU_PL_OA)
 867                 return -EINVAL;
 868
 869         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 870                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 871                 return 0;
 872         }
 873
 874         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 875         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 876         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 877                 ttm->pages, gtt->ttm.dma_address, flags);
 878
 879         if (r)
 880                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 881                           ttm->num_pages, gtt->offset);
 882         return r;
 883 }
 884
 885 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 886 {
 887         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 888         struct ttm_operation_ctx ctx = { false, false };
 889         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
 890         struct ttm_mem_reg tmp;
 891         struct ttm_placement placement;
 892         struct ttm_place placements;
 893         uint64_t flags;
 894         int r;
 895
 896         if (bo->mem.mem_type != TTM_PL_TT ||
 897             amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
 898                 return 0;
 899
 900         tmp = bo->mem;
 901         tmp.mm_node = NULL;
 902         placement.num_placement = 1;
 903         placement.placement = &placements;
 904         placement.num_busy_placement = 1;
 905         placement.busy_placement = &placements;
 906         placements.fpfn = 0;
 907         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 908         placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
 909                 TTM_PL_FLAG_TT;
 910
 911         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 912         if (unlikely(r))
 913                 return r;
 914
 915         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
 916         gtt->offset = (u64)tmp.start << PAGE_SHIFT;
 917         r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages,
 918                              bo->ttm->pages, gtt->ttm.dma_address, flags);
 919         if (unlikely(r)) {
 920                 ttm_bo_mem_put(bo, &tmp);
 921                 return r;
 922         }
 923
 924         ttm_bo_mem_put(bo, &bo->mem);
 925         bo->mem = tmp;
 926         bo->offset = (bo->mem.start << PAGE_SHIFT) +
 927                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
 928
 929         return 0;
 930 }
 931
 932 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 933 {
 934         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
 935         struct amdgpu_ttm_tt *gtt = (void *)tbo->ttm;
 936         uint64_t flags;
 937         int r;
 938
 939         if (!gtt)
 940                 return 0;
 941
 942         flags = amdgpu_ttm_tt_pte_flags(adev, &gtt->ttm.ttm, &tbo->mem);
 943         r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 944                              gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags);
 945         if (r)
 946                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 947                           gtt->ttm.ttm.num_pages, gtt->offset);
 948         return r;
 949 }
 950
 951 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 952 {
 953         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 954         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 955         int r;
 956
 957         if (gtt->userptr)
 958                 amdgpu_ttm_tt_unpin_userptr(ttm);
 959
 960         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
 961                 return 0;
 962
 963         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 964         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
 965         if (r)
 966                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 967                           gtt->ttm.ttm.num_pages, gtt->offset);
 968         return r;
 969 }
 970
 971 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 972 {
 973         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 974
 975         ttm_dma_tt_fini(&gtt->ttm);
 976         kfree(gtt);
 977 }
 978
 979 static struct ttm_backend_func amdgpu_backend_func = {
 980         .bind = &amdgpu_ttm_backend_bind,
 981         .unbind = &amdgpu_ttm_backend_unbind,
 982         .destroy = &amdgpu_ttm_backend_destroy,
 983 };
 984
 985 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 986                                     unsigned long size, uint32_t page_flags)
 987 {
 988         struct amdgpu_device *adev;
 989         struct amdgpu_ttm_tt *gtt;
 990
 991         adev = amdgpu_ttm_adev(bdev);
 992
 993         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 994         if (gtt == NULL) {
 995                 return NULL;
 996         }
 997         gtt->ttm.ttm.func = &amdgpu_backend_func;
 998         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags)) {
 999                 kfree(gtt);
1000                 return NULL;
1001         }
1002         return &gtt->ttm.ttm;
1003 }
1004
1005 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1006                         struct ttm_operation_ctx *ctx)
1007 {
1008         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1009         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1010         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1011
1012         if (gtt && gtt->userptr) {
1013                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1014                 if (!ttm->sg)
1015                         return -ENOMEM;
1016
1017                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1018                 ttm->state = tt_unbound;
1019                 return 0;
1020         }
1021
1022         if (slave && ttm->sg) {
1023                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1024                                                  gtt->ttm.dma_address, ttm->num_pages);
1025                 ttm->state = tt_unbound;
1026                 return 0;
1027         }
1028
1029 #ifdef CONFIG_SWIOTLB
1030         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1031                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1032         }
1033 #endif
1034
1035         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1036 }
1037
1038 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1039 {
1040         struct amdgpu_device *adev;
1041         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1042         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1043
1044         if (gtt && gtt->userptr) {
1045                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1046                 kfree(ttm->sg);
1047                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1048                 return;
1049         }
1050
1051         if (slave)
1052                 return;
1053
1054         adev = amdgpu_ttm_adev(ttm->bdev);
1055
1056 #ifdef CONFIG_SWIOTLB
1057         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1058                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1059                 return;
1060         }
1061 #endif
1062
1063         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1064 }
1065
1066 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1067                               uint32_t flags)
1068 {
1069         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1070
1071         if (gtt == NULL)
1072                 return -EINVAL;
1073
1074         gtt->userptr = addr;
1075         gtt->usermm = current->mm;
1076         gtt->userflags = flags;
1077         spin_lock_init(&gtt->guptasklock);
1078         INIT_LIST_HEAD(&gtt->guptasks);
1079         atomic_set(&gtt->mmu_invalidations, 0);
1080         gtt->last_set_pages = 0;
1081
1082         return 0;
1083 }
1084
1085 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1086 {
1087         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1088
1089         if (gtt == NULL)
1090                 return NULL;
1091
1092         return gtt->usermm;
1093 }
1094
1095 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1096                                   unsigned long end)
1097 {
1098         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1099         struct amdgpu_ttm_gup_task_list *entry;
1100         unsigned long size;
1101
1102         if (gtt == NULL || !gtt->userptr)
1103                 return false;
1104
1105         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1106         if (gtt->userptr > end || gtt->userptr + size <= start)
1107                 return false;
1108
1109         spin_lock(&gtt->guptasklock);
1110         list_for_each_entry(entry, &gtt->guptasks, list) {
1111                 if (entry->task == current) {
1112                         spin_unlock(&gtt->guptasklock);
1113                         return false;
1114                 }
1115         }
1116         spin_unlock(&gtt->guptasklock);
1117
1118         atomic_inc(&gtt->mmu_invalidations);
1119
1120         return true;
1121 }
1122
1123 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1124                                        int *last_invalidated)
1125 {
1126         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1127         int prev_invalidated = *last_invalidated;
1128
1129         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1130         return prev_invalidated != *last_invalidated;
1131 }
1132
1133 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1134 {
1135         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1136
1137         if (gtt == NULL || !gtt->userptr)
1138                 return false;
1139
1140         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1141 }
1142
1143 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1144 {
1145         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1146
1147         if (gtt == NULL)
1148                 return false;
1149
1150         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1151 }
1152
1153 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1154                                  struct ttm_mem_reg *mem)
1155 {
1156         uint64_t flags = 0;
1157
1158         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1159                 flags |= AMDGPU_PTE_VALID;
1160
1161         if (mem && mem->mem_type == TTM_PL_TT) {
1162                 flags |= AMDGPU_PTE_SYSTEM;
1163
1164                 if (ttm->caching_state == tt_cached)
1165                         flags |= AMDGPU_PTE_SNOOPED;
1166         }
1167
1168         flags |= adev->gart.gart_pte_flags;
1169         flags |= AMDGPU_PTE_READABLE;
1170
1171         if (!amdgpu_ttm_tt_is_readonly(ttm))
1172                 flags |= AMDGPU_PTE_WRITEABLE;
1173
1174         return flags;
1175 }
1176
1177 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1178                                             const struct ttm_place *place)
1179 {
1180         unsigned long num_pages = bo->mem.num_pages;
1181         struct drm_mm_node *node = bo->mem.mm_node;
1182         struct reservation_object_list *flist;
1183         struct dma_fence *f;
1184         int i;
1185
1186         /* If bo is a KFD BO, check if the bo belongs to the current process.
1187          * If true, then return false as any KFD process needs all its BOs to
1188          * be resident to run successfully
1189          */
1190         flist = reservation_object_get_list(bo->resv);
1191         if (flist) {
1192                 for (i = 0; i < flist->shared_count; ++i) {
1193                         f = rcu_dereference_protected(flist->shared[i],
1194                                 reservation_object_held(bo->resv));
1195                         if (amdkfd_fence_check_mm(f, current->mm))
1196                                 return false;
1197                 }
1198         }
1199
1200         switch (bo->mem.mem_type) {
1201         case TTM_PL_TT:
1202                 return true;
1203
1204         case TTM_PL_VRAM:
1205                 /* Check each drm MM node individually */
1206                 while (num_pages) {
1207                         if (place->fpfn < (node->start + node->size) &&
1208                             !(place->lpfn && place->lpfn <= node->start))
1209                                 return true;
1210
1211                         num_pages -= node->size;
1212                         ++node;
1213                 }
1214                 return false;
1215
1216         default:
1217                 break;
1218         }
1219
1220         return ttm_bo_eviction_valuable(bo, place);
1221 }
1222
1223 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1224                                     unsigned long offset,
1225                                     void *buf, int len, int write)
1226 {
1227         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1228         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1229         struct drm_mm_node *nodes;
1230         uint32_t value = 0;
1231         int ret = 0;
1232         uint64_t pos;
1233         unsigned long flags;
1234
1235         if (bo->mem.mem_type != TTM_PL_VRAM)
1236                 return -EIO;
1237
1238         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1239         pos = (nodes->start << PAGE_SHIFT) + offset;
1240
1241         while (len && pos < adev->gmc.mc_vram_size) {
1242                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1243                 uint32_t bytes = 4 - (pos & 3);
1244                 uint32_t shift = (pos & 3) * 8;
1245                 uint32_t mask = 0xffffffff << shift;
1246
1247                 if (len < bytes) {
1248                         mask &= 0xffffffff >> (bytes - len) * 8;
1249                         bytes = len;
1250                 }
1251
1252                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1253                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1254                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1255                 if (!write || mask != 0xffffffff)
1256                         value = RREG32_NO_KIQ(mmMM_DATA);
1257                 if (write) {
1258                         value &= ~mask;
1259                         value |= (*(uint32_t *)buf << shift) & mask;
1260                         WREG32_NO_KIQ(mmMM_DATA, value);
1261                 }
1262                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1263                 if (!write) {
1264                         value = (value & mask) >> shift;
1265                         memcpy(buf, &value, bytes);
1266                 }
1267
1268                 ret += bytes;
1269                 buf = (uint8_t *)buf + bytes;
1270                 pos += bytes;
1271                 len -= bytes;
1272                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1273                         ++nodes;
1274                         pos = (nodes->start << PAGE_SHIFT);
1275                 }
1276         }
1277
1278         return ret;
1279 }
1280
1281 static struct ttm_bo_driver amdgpu_bo_driver = {
1282         .ttm_tt_create = &amdgpu_ttm_tt_create,
1283         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1284         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1285         .invalidate_caches = &amdgpu_invalidate_caches,
1286         .init_mem_type = &amdgpu_init_mem_type,
1287         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1288         .evict_flags = &amdgpu_evict_flags,
1289         .move = &amdgpu_bo_move,
1290         .verify_access = &amdgpu_verify_access,
1291         .move_notify = &amdgpu_bo_move_notify,
1292         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1293         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1294         .io_mem_free = &amdgpu_ttm_io_mem_free,
1295         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1296         .access_memory = &amdgpu_ttm_access_memory
1297 };
1298
1299 /*
1300  * Firmware Reservation functions
1301  */
1302 /**
1303  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1304  *
1305  * @adev: amdgpu_device pointer
1306  *
1307  * free fw reserved vram if it has been reserved.
1308  */
1309 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1310 {
1311         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1312                 NULL, &adev->fw_vram_usage.va);
1313 }
1314
1315 /**
1316  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1317  *
1318  * @adev: amdgpu_device pointer
1319  *
1320  * create bo vram reservation from fw.
1321  */
1322 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1323 {
1324         struct ttm_operation_ctx ctx = { false, false };
1325         int r = 0;
1326         int i;
1327         u64 vram_size = adev->gmc.visible_vram_size;
1328         u64 offset = adev->fw_vram_usage.start_offset;
1329         u64 size = adev->fw_vram_usage.size;
1330         struct amdgpu_bo *bo;
1331
1332         adev->fw_vram_usage.va = NULL;
1333         adev->fw_vram_usage.reserved_bo = NULL;
1334
1335         if (adev->fw_vram_usage.size > 0 &&
1336                 adev->fw_vram_usage.size <= vram_size) {
1337
1338                 r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
1339                         PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
1340                         AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1341                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL,
1342                         &adev->fw_vram_usage.reserved_bo);
1343                 if (r)
1344                         goto error_create;
1345
1346                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1347                 if (r)
1348                         goto error_reserve;
1349
1350                 /* remove the original mem node and create a new one at the
1351                  * request position
1352                  */
1353                 bo = adev->fw_vram_usage.reserved_bo;
1354                 offset = ALIGN(offset, PAGE_SIZE);
1355                 for (i = 0; i < bo->placement.num_placement; ++i) {
1356                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1357                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1358                 }
1359
1360                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1361                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1362                                      &bo->tbo.mem, &ctx);
1363                 if (r)
1364                         goto error_pin;
1365
1366                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1367                         AMDGPU_GEM_DOMAIN_VRAM,
1368                         adev->fw_vram_usage.start_offset,
1369                         (adev->fw_vram_usage.start_offset +
1370                         adev->fw_vram_usage.size), NULL);
1371                 if (r)
1372                         goto error_pin;
1373                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1374                         &adev->fw_vram_usage.va);
1375                 if (r)
1376                         goto error_kmap;
1377
1378                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1379         }
1380         return r;
1381
1382 error_kmap:
1383         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1384 error_pin:
1385         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1386 error_reserve:
1387         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1388 error_create:
1389         adev->fw_vram_usage.va = NULL;
1390         adev->fw_vram_usage.reserved_bo = NULL;
1391         return r;
1392 }
1393
1394 int amdgpu_ttm_init(struct amdgpu_device *adev)
1395 {
1396         uint64_t gtt_size;
1397         int r;
1398         u64 vis_vram_limit;
1399
1400         r = amdgpu_ttm_global_init(adev);
1401         if (r) {
1402                 return r;
1403         }
1404         /* No others user of address space so set it to 0 */
1405         r = ttm_bo_device_init(&adev->mman.bdev,
1406                                adev->mman.bo_global_ref.ref.object,
1407                                &amdgpu_bo_driver,
1408                                adev->ddev->anon_inode->i_mapping,
1409                                DRM_FILE_PAGE_OFFSET,
1410                                adev->need_dma32);
1411         if (r) {
1412                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1413                 return r;
1414         }
1415         adev->mman.initialized = true;
1416
1417         /* We opt to avoid OOM on system pages allocations */
1418         adev->mman.bdev.no_retry = true;
1419
1420         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1421                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1422         if (r) {
1423                 DRM_ERROR("Failed initializing VRAM heap.\n");
1424                 return r;
1425         }
1426
1427         /* Reduce size of CPU-visible VRAM if requested */
1428         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1429         if (amdgpu_vis_vram_limit > 0 &&
1430             vis_vram_limit <= adev->gmc.visible_vram_size)
1431                 adev->gmc.visible_vram_size = vis_vram_limit;
1432
1433         /* Change the size here instead of the init above so only lpfn is affected */
1434         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1435 #ifdef CONFIG_64BIT
1436         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1437                                                 adev->gmc.visible_vram_size);
1438 #endif
1439
1440         /*
1441          *The reserved vram for firmware must be pinned to the specified
1442          *place on the VRAM, so reserve it early.
1443          */
1444         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1445         if (r) {
1446                 return r;
1447         }
1448
1449         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1450                                     AMDGPU_GEM_DOMAIN_VRAM,
1451                                     &adev->stolen_vga_memory,
1452                                     NULL, NULL);
1453         if (r)
1454                 return r;
1455         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1456                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1457
1458         if (amdgpu_gtt_size == -1) {
1459                 struct sysinfo si;
1460
1461                 si_meminfo(&si);
1462                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1463                                adev->gmc.mc_vram_size),
1464                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1465         }
1466         else
1467                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1468         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1469         if (r) {
1470                 DRM_ERROR("Failed initializing GTT heap.\n");
1471                 return r;
1472         }
1473         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1474                  (unsigned)(gtt_size / (1024 * 1024)));
1475
1476         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1477         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1478         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1479         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1480         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1481         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1482         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1483         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1484         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1485         /* GDS Memory */
1486         if (adev->gds.mem.total_size) {
1487                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1488                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1489                 if (r) {
1490                         DRM_ERROR("Failed initializing GDS heap.\n");
1491                         return r;
1492                 }
1493         }
1494
1495         /* GWS */
1496         if (adev->gds.gws.total_size) {
1497                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1498                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1499                 if (r) {
1500                         DRM_ERROR("Failed initializing gws heap.\n");
1501                         return r;
1502                 }
1503         }
1504
1505         /* OA */
1506         if (adev->gds.oa.total_size) {
1507                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1508                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1509                 if (r) {
1510                         DRM_ERROR("Failed initializing oa heap.\n");
1511                         return r;
1512                 }
1513         }
1514
1515         r = amdgpu_ttm_debugfs_init(adev);
1516         if (r) {
1517                 DRM_ERROR("Failed to init debugfs\n");
1518                 return r;
1519         }
1520         return 0;
1521 }
1522
1523 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1524 {
1525         if (!adev->mman.initialized)
1526                 return;
1527
1528         amdgpu_ttm_debugfs_fini(adev);
1529         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1530         amdgpu_ttm_fw_reserve_vram_fini(adev);
1531         if (adev->mman.aper_base_kaddr)
1532                 iounmap(adev->mman.aper_base_kaddr);
1533         adev->mman.aper_base_kaddr = NULL;
1534
1535         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1536         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1537         if (adev->gds.mem.total_size)
1538                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1539         if (adev->gds.gws.total_size)
1540                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1541         if (adev->gds.oa.total_size)
1542                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1543         ttm_bo_device_release(&adev->mman.bdev);
1544         amdgpu_ttm_global_fini(adev);
1545         adev->mman.initialized = false;
1546         DRM_INFO("amdgpu: ttm finalized\n");
1547 }
1548
1549 /**
1550  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1551  *
1552  * @adev: amdgpu_device pointer
1553  * @enable: true when we can use buffer functions.
1554  *
1555  * Enable/disable use of buffer functions during suspend/resume. This should
1556  * only be called at bootup or when userspace isn't running.
1557  */
1558 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1559 {
1560         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1561         uint64_t size;
1562
1563         if (!adev->mman.initialized || adev->in_gpu_reset)
1564                 return;
1565
1566         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1567         if (enable)
1568                 size = adev->gmc.real_vram_size;
1569         else
1570                 size = adev->gmc.visible_vram_size;
1571         man->size = size >> PAGE_SHIFT;
1572         adev->mman.buffer_funcs_enabled = enable;
1573 }
1574
1575 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1576 {
1577         struct drm_file *file_priv;
1578         struct amdgpu_device *adev;
1579
1580         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1581                 return -EINVAL;
1582
1583         file_priv = filp->private_data;
1584         adev = file_priv->minor->dev->dev_private;
1585         if (adev == NULL)
1586                 return -EINVAL;
1587
1588         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1589 }
1590
1591 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1592                              struct ttm_mem_reg *mem, unsigned num_pages,
1593                              uint64_t offset, unsigned window,
1594                              struct amdgpu_ring *ring,
1595                              uint64_t *addr)
1596 {
1597         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1598         struct amdgpu_device *adev = ring->adev;
1599         struct ttm_tt *ttm = bo->ttm;
1600         struct amdgpu_job *job;
1601         unsigned num_dw, num_bytes;
1602         dma_addr_t *dma_address;
1603         struct dma_fence *fence;
1604         uint64_t src_addr, dst_addr;
1605         uint64_t flags;
1606         int r;
1607
1608         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1609                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1610
1611         *addr = adev->gmc.gart_start;
1612         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1613                 AMDGPU_GPU_PAGE_SIZE;
1614
1615         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1616         while (num_dw & 0x7)
1617                 num_dw++;
1618
1619         num_bytes = num_pages * 8;
1620
1621         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1622         if (r)
1623                 return r;
1624
1625         src_addr = num_dw * 4;
1626         src_addr += job->ibs[0].gpu_addr;
1627
1628         dst_addr = adev->gart.table_addr;
1629         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1630         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1631                                 dst_addr, num_bytes);
1632
1633         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1634         WARN_ON(job->ibs[0].length_dw > num_dw);
1635
1636         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1637         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1638         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1639                             &job->ibs[0].ptr[num_dw]);
1640         if (r)
1641                 goto error_free;
1642
1643         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1644                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1645         if (r)
1646                 goto error_free;
1647
1648         dma_fence_put(fence);
1649
1650         return r;
1651
1652 error_free:
1653         amdgpu_job_free(job);
1654         return r;
1655 }
1656
1657 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1658                        uint64_t dst_offset, uint32_t byte_count,
1659                        struct reservation_object *resv,
1660                        struct dma_fence **fence, bool direct_submit,
1661                        bool vm_needs_flush)
1662 {
1663         struct amdgpu_device *adev = ring->adev;
1664         struct amdgpu_job *job;
1665
1666         uint32_t max_bytes;
1667         unsigned num_loops, num_dw;
1668         unsigned i;
1669         int r;
1670
1671         if (direct_submit && !ring->ready) {
1672                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1673                 return -EINVAL;
1674         }
1675
1676         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1677         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1678         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1679
1680         /* for IB padding */
1681         while (num_dw & 0x7)
1682                 num_dw++;
1683
1684         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1685         if (r)
1686                 return r;
1687
1688         job->vm_needs_flush = vm_needs_flush;
1689         if (resv) {
1690                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1691                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1692                                      false);
1693                 if (r) {
1694                         DRM_ERROR("sync failed (%d).\n", r);
1695                         goto error_free;
1696                 }
1697         }
1698
1699         for (i = 0; i < num_loops; i++) {
1700                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1701
1702                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1703                                         dst_offset, cur_size_in_bytes);
1704
1705                 src_offset += cur_size_in_bytes;
1706                 dst_offset += cur_size_in_bytes;
1707                 byte_count -= cur_size_in_bytes;
1708         }
1709
1710         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1711         WARN_ON(job->ibs[0].length_dw > num_dw);
1712         if (direct_submit) {
1713                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1714                                        NULL, fence);
1715                 job->fence = dma_fence_get(*fence);
1716                 if (r)
1717                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1718                 amdgpu_job_free(job);
1719         } else {
1720                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1721                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1722                 if (r)
1723                         goto error_free;
1724         }
1725
1726         return r;
1727
1728 error_free:
1729         amdgpu_job_free(job);
1730         return r;
1731 }
1732
1733 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1734                        uint32_t src_data,
1735                        struct reservation_object *resv,
1736                        struct dma_fence **fence)
1737 {
1738         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1739         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1740         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1741
1742         struct drm_mm_node *mm_node;
1743         unsigned long num_pages;
1744         unsigned int num_loops, num_dw;
1745
1746         struct amdgpu_job *job;
1747         int r;
1748
1749         if (!adev->mman.buffer_funcs_enabled) {
1750                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1751                 return -EINVAL;
1752         }
1753
1754         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1755                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1756                 if (r)
1757                         return r;
1758         }
1759
1760         num_pages = bo->tbo.num_pages;
1761         mm_node = bo->tbo.mem.mm_node;
1762         num_loops = 0;
1763         while (num_pages) {
1764                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1765
1766                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1767                 num_pages -= mm_node->size;
1768                 ++mm_node;
1769         }
1770         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1771
1772         /* for IB padding */
1773         num_dw += 64;
1774
1775         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1776         if (r)
1777                 return r;
1778
1779         if (resv) {
1780                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1781                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1782                 if (r) {
1783                         DRM_ERROR("sync failed (%d).\n", r);
1784                         goto error_free;
1785                 }
1786         }
1787
1788         num_pages = bo->tbo.num_pages;
1789         mm_node = bo->tbo.mem.mm_node;
1790
1791         while (num_pages) {
1792                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1793                 uint64_t dst_addr;
1794
1795                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1796                 while (byte_count) {
1797                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1798
1799                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1800                                                 dst_addr, cur_size_in_bytes);
1801
1802                         dst_addr += cur_size_in_bytes;
1803                         byte_count -= cur_size_in_bytes;
1804                 }
1805
1806                 num_pages -= mm_node->size;
1807                 ++mm_node;
1808         }
1809
1810         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1811         WARN_ON(job->ibs[0].length_dw > num_dw);
1812         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1813                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1814         if (r)
1815                 goto error_free;
1816
1817         return 0;
1818
1819 error_free:
1820         amdgpu_job_free(job);
1821         return r;
1822 }
1823
1824 #if defined(CONFIG_DEBUG_FS)
1825
1826 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1827 {
1828         struct drm_info_node *node = (struct drm_info_node *)m->private;
1829         unsigned ttm_pl = *(int *)node->info_ent->data;
1830         struct drm_device *dev = node->minor->dev;
1831         struct amdgpu_device *adev = dev->dev_private;
1832         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1833         struct drm_printer p = drm_seq_file_printer(m);
1834
1835         man->func->debug(man, &p);
1836         return 0;
1837 }
1838
1839 static int ttm_pl_vram = TTM_PL_VRAM;
1840 static int ttm_pl_tt = TTM_PL_TT;
1841
1842 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1843         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1844         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1845         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1846 #ifdef CONFIG_SWIOTLB
1847         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1848 #endif
1849 };
1850
1851 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1852                                     size_t size, loff_t *pos)
1853 {
1854         struct amdgpu_device *adev = file_inode(f)->i_private;
1855         ssize_t result = 0;
1856         int r;
1857
1858         if (size & 0x3 || *pos & 0x3)
1859                 return -EINVAL;
1860
1861         if (*pos >= adev->gmc.mc_vram_size)
1862                 return -ENXIO;
1863
1864         while (size) {
1865                 unsigned long flags;
1866                 uint32_t value;
1867
1868                 if (*pos >= adev->gmc.mc_vram_size)
1869                         return result;
1870
1871                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1872                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1873                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1874                 value = RREG32_NO_KIQ(mmMM_DATA);
1875                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1876
1877                 r = put_user(value, (uint32_t *)buf);
1878                 if (r)
1879                         return r;
1880
1881                 result += 4;
1882                 buf += 4;
1883                 *pos += 4;
1884                 size -= 4;
1885         }
1886
1887         return result;
1888 }
1889
1890 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
1891                                     size_t size, loff_t *pos)
1892 {
1893         struct amdgpu_device *adev = file_inode(f)->i_private;
1894         ssize_t result = 0;
1895         int r;
1896
1897         if (size & 0x3 || *pos & 0x3)
1898                 return -EINVAL;
1899
1900         if (*pos >= adev->gmc.mc_vram_size)
1901                 return -ENXIO;
1902
1903         while (size) {
1904                 unsigned long flags;
1905                 uint32_t value;
1906
1907                 if (*pos >= adev->gmc.mc_vram_size)
1908                         return result;
1909
1910                 r = get_user(value, (uint32_t *)buf);
1911                 if (r)
1912                         return r;
1913
1914                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1915                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1916                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
1917                 WREG32_NO_KIQ(mmMM_DATA, value);
1918                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1919
1920                 result += 4;
1921                 buf += 4;
1922                 *pos += 4;
1923                 size -= 4;
1924         }
1925
1926         return result;
1927 }
1928
1929 static const struct file_operations amdgpu_ttm_vram_fops = {
1930         .owner = THIS_MODULE,
1931         .read = amdgpu_ttm_vram_read,
1932         .write = amdgpu_ttm_vram_write,
1933         .llseek = default_llseek,
1934 };
1935
1936 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1937
1938 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1939                                    size_t size, loff_t *pos)
1940 {
1941         struct amdgpu_device *adev = file_inode(f)->i_private;
1942         ssize_t result = 0;
1943         int r;
1944
1945         while (size) {
1946                 loff_t p = *pos / PAGE_SIZE;
1947                 unsigned off = *pos & ~PAGE_MASK;
1948                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1949                 struct page *page;
1950                 void *ptr;
1951
1952                 if (p >= adev->gart.num_cpu_pages)
1953                         return result;
1954
1955                 page = adev->gart.pages[p];
1956                 if (page) {
1957                         ptr = kmap(page);
1958                         ptr += off;
1959
1960                         r = copy_to_user(buf, ptr, cur_size);
1961                         kunmap(adev->gart.pages[p]);
1962                 } else
1963                         r = clear_user(buf, cur_size);
1964
1965                 if (r)
1966                         return -EFAULT;
1967
1968                 result += cur_size;
1969                 buf += cur_size;
1970                 *pos += cur_size;
1971                 size -= cur_size;
1972         }
1973
1974         return result;
1975 }
1976
1977 static const struct file_operations amdgpu_ttm_gtt_fops = {
1978         .owner = THIS_MODULE,
1979         .read = amdgpu_ttm_gtt_read,
1980         .llseek = default_llseek
1981 };
1982
1983 #endif
1984
1985 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
1986                                  size_t size, loff_t *pos)
1987 {
1988         struct amdgpu_device *adev = file_inode(f)->i_private;
1989         struct iommu_domain *dom;
1990         ssize_t result = 0;
1991         int r;
1992
1993         dom = iommu_get_domain_for_dev(adev->dev);
1994
1995         while (size) {
1996                 phys_addr_t addr = *pos & PAGE_MASK;
1997                 loff_t off = *pos & ~PAGE_MASK;
1998                 size_t bytes = PAGE_SIZE - off;
1999                 unsigned long pfn;
2000                 struct page *p;
2001                 void *ptr;
2002
2003                 bytes = bytes < size ? bytes : size;
2004
2005                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2006
2007                 pfn = addr >> PAGE_SHIFT;
2008                 if (!pfn_valid(pfn))
2009                         return -EPERM;
2010
2011                 p = pfn_to_page(pfn);
2012                 if (p->mapping != adev->mman.bdev.dev_mapping)
2013                         return -EPERM;
2014
2015                 ptr = kmap(p);
2016                 r = copy_to_user(buf, ptr, bytes);
2017                 kunmap(p);
2018                 if (r)
2019                         return -EFAULT;
2020
2021                 size -= bytes;
2022                 *pos += bytes;
2023                 result += bytes;
2024         }
2025
2026         return result;
2027 }
2028
2029 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2030                                  size_t size, loff_t *pos)
2031 {
2032         struct amdgpu_device *adev = file_inode(f)->i_private;
2033         struct iommu_domain *dom;
2034         ssize_t result = 0;
2035         int r;
2036
2037         dom = iommu_get_domain_for_dev(adev->dev);
2038
2039         while (size) {
2040                 phys_addr_t addr = *pos & PAGE_MASK;
2041                 loff_t off = *pos & ~PAGE_MASK;
2042                 size_t bytes = PAGE_SIZE - off;
2043                 unsigned long pfn;
2044                 struct page *p;
2045                 void *ptr;
2046
2047                 bytes = bytes < size ? bytes : size;
2048
2049                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2050
2051                 pfn = addr >> PAGE_SHIFT;
2052                 if (!pfn_valid(pfn))
2053                         return -EPERM;
2054
2055                 p = pfn_to_page(pfn);
2056                 if (p->mapping != adev->mman.bdev.dev_mapping)
2057                         return -EPERM;
2058
2059                 ptr = kmap(p);
2060                 r = copy_from_user(ptr, buf, bytes);
2061                 kunmap(p);
2062                 if (r)
2063                         return -EFAULT;
2064
2065                 size -= bytes;
2066                 *pos += bytes;
2067                 result += bytes;
2068         }
2069
2070         return result;
2071 }
2072
2073 static const struct file_operations amdgpu_ttm_iomem_fops = {
2074         .owner = THIS_MODULE,
2075         .read = amdgpu_iomem_read,
2076         .write = amdgpu_iomem_write,
2077         .llseek = default_llseek
2078 };
2079
2080 static const struct {
2081         char *name;
2082         const struct file_operations *fops;
2083         int domain;
2084 } ttm_debugfs_entries[] = {
2085         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2086 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2087         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2088 #endif
2089         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2090 };
2091
2092 #endif
2093
2094 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2095 {
2096 #if defined(CONFIG_DEBUG_FS)
2097         unsigned count;
2098
2099         struct drm_minor *minor = adev->ddev->primary;
2100         struct dentry *ent, *root = minor->debugfs_root;
2101
2102         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2103                 ent = debugfs_create_file(
2104                                 ttm_debugfs_entries[count].name,
2105                                 S_IFREG | S_IRUGO, root,
2106                                 adev,
2107                                 ttm_debugfs_entries[count].fops);
2108                 if (IS_ERR(ent))
2109                         return PTR_ERR(ent);
2110                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2111                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2112                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2113                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2114                 adev->mman.debugfs_entries[count] = ent;
2115         }
2116
2117         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2118
2119 #ifdef CONFIG_SWIOTLB
2120         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2121                 --count;
2122 #endif
2123
2124         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2125 #else
2126         return 0;
2127 #endif
2128 }
2129
2130 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2131 {
2132 #if defined(CONFIG_DEBUG_FS)
2133         unsigned i;
2134
2135         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2136                 debugfs_remove(adev->mman.debugfs_entries[i]);
2137 #endif
2138 }