drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "amdgpu_jpeg.h"
  26 #include "amdgpu_pm.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29 #include "jpeg_v2_0.h"
  30
  31 #include "vcn/vcn_2_0_0_offset.h"
  32 #include "vcn/vcn_2_0_0_sh_mask.h"
  33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  34
  35 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  36 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
  37 static int jpeg_v2_0_set_powergating_state(void *handle,
  38                                 enum amd_powergating_state state);
  39
  40 /**
  41  * jpeg_v2_0_early_init - set function pointers
  42  *
  43  * @handle: amdgpu_device pointer
  44  *
  45  * Set ring and irq function pointers
  46  */
  47 static int jpeg_v2_0_early_init(void *handle)
  48 {
  49         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  50
  51         adev->jpeg.num_jpeg_inst = 1;
  52         adev->jpeg.num_jpeg_rings = 1;
  53
  54         jpeg_v2_0_set_dec_ring_funcs(adev);
  55         jpeg_v2_0_set_irq_funcs(adev);
  56
  57         return 0;
  58 }
  59
  60 /**
  61  * jpeg_v2_0_sw_init - sw init for JPEG block
  62  *
  63  * @handle: amdgpu_device pointer
  64  *
  65  * Load firmware and sw initialization
  66  */
  67 static int jpeg_v2_0_sw_init(void *handle)
  68 {
  69         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  70         struct amdgpu_ring *ring;
  71         int r;
  72
  73         /* JPEG TRAP */
  74         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  75                 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
  76         if (r)
  77                 return r;
  78
  79         r = amdgpu_jpeg_sw_init(adev);
  80         if (r)
  81                 return r;
  82
  83         r = amdgpu_jpeg_resume(adev);
  84         if (r)
  85                 return r;
  86
  87         ring = adev->jpeg.inst->ring_dec;
  88         ring->use_doorbell = true;
  89         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
  90         ring->vm_hub = AMDGPU_MMHUB0(0);
  91         sprintf(ring->name, "jpeg_dec");
  92         r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
  93                              0, AMDGPU_RING_PRIO_DEFAULT, NULL);
  94         if (r)
  95                 return r;
  96
  97         adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
  98         adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
  99
 100         return 0;
 101 }
 102
 103 /**
 104  * jpeg_v2_0_sw_fini - sw fini for JPEG block
 105  *
 106  * @handle: amdgpu_device pointer
 107  *
 108  * JPEG suspend and free up sw allocation
 109  */
 110 static int jpeg_v2_0_sw_fini(void *handle)
 111 {
 112         int r;
 113         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 114
 115         r = amdgpu_jpeg_suspend(adev);
 116         if (r)
 117                 return r;
 118
 119         r = amdgpu_jpeg_sw_fini(adev);
 120
 121         return r;
 122 }
 123
 124 /**
 125  * jpeg_v2_0_hw_init - start and test JPEG block
 126  *
 127  * @handle: amdgpu_device pointer
 128  *
 129  */
 130 static int jpeg_v2_0_hw_init(void *handle)
 131 {
 132         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 133         struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
 134
 135         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 136                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
 137
 138         return amdgpu_ring_test_helper(ring);
 139 }
 140
 141 /**
 142  * jpeg_v2_0_hw_fini - stop the hardware block
 143  *
 144  * @handle: amdgpu_device pointer
 145  *
 146  * Stop the JPEG block, mark ring as not ready any more
 147  */
 148 static int jpeg_v2_0_hw_fini(void *handle)
 149 {
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151
 152         cancel_delayed_work_sync(&adev->vcn.idle_work);
 153
 154         if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
 155               RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
 156                 jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * jpeg_v2_0_suspend - suspend JPEG block
 163  *
 164  * @handle: amdgpu_device pointer
 165  *
 166  * HW fini and suspend JPEG block
 167  */
 168 static int jpeg_v2_0_suspend(void *handle)
 169 {
 170         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 171         int r;
 172
 173         r = jpeg_v2_0_hw_fini(adev);
 174         if (r)
 175                 return r;
 176
 177         r = amdgpu_jpeg_suspend(adev);
 178
 179         return r;
 180 }
 181
 182 /**
 183  * jpeg_v2_0_resume - resume JPEG block
 184  *
 185  * @handle: amdgpu_device pointer
 186  *
 187  * Resume firmware and hw init JPEG block
 188  */
 189 static int jpeg_v2_0_resume(void *handle)
 190 {
 191         int r;
 192         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 193
 194         r = amdgpu_jpeg_resume(adev);
 195         if (r)
 196                 return r;
 197
 198         r = jpeg_v2_0_hw_init(adev);
 199
 200         return r;
 201 }
 202
 203 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
 204 {
 205         uint32_t data;
 206         int r = 0;
 207
 208         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 209                 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 210                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
 211
 212                 r = SOC15_WAIT_ON_RREG(JPEG, 0,
 213                         mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
 214                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
 215
 216                 if (r) {
 217                         DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
 218                         return r;
 219                 }
 220         }
 221
 222         /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
 223         data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
 224         WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
 225
 226         return 0;
 227 }
 228
 229 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev)
 230 {
 231         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 232                 uint32_t data;
 233                 int r = 0;
 234
 235                 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
 236                 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
 237                 data |=  0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
 238                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
 239
 240                 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 241                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
 242
 243                 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
 244                         (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
 245                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
 246
 247                 if (r) {
 248                         DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
 249                         return r;
 250                 }
 251         }
 252
 253         return 0;
 254 }
 255
 256 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev)
 257 {
 258         uint32_t data;
 259
 260         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
 261         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
 262                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 263         else
 264                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 265
 266         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 267         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 268         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 269
 270         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
 271         data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
 272                 | JPEG_CGC_GATE__JPEG2_DEC_MASK
 273                 | JPEG_CGC_GATE__JPEG_ENC_MASK
 274                 | JPEG_CGC_GATE__JMCIF_MASK
 275                 | JPEG_CGC_GATE__JRBBM_MASK);
 276         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 277 }
 278
 279 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev)
 280 {
 281         uint32_t data;
 282
 283         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
 284         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
 285                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 286         else
 287                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 288
 289         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 290         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 291         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 292
 293         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
 294         data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
 295                 |JPEG_CGC_GATE__JPEG2_DEC_MASK
 296                 |JPEG_CGC_GATE__JPEG_ENC_MASK
 297                 |JPEG_CGC_GATE__JMCIF_MASK
 298                 |JPEG_CGC_GATE__JRBBM_MASK);
 299         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 300 }
 301
 302 /**
 303  * jpeg_v2_0_start - start JPEG block
 304  *
 305  * @adev: amdgpu_device pointer
 306  *
 307  * Setup and start the JPEG block
 308  */
 309 static int jpeg_v2_0_start(struct amdgpu_device *adev)
 310 {
 311         struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
 312         int r;
 313
 314         if (adev->pm.dpm_enabled)
 315                 amdgpu_dpm_enable_jpeg(adev, true);
 316
 317         /* disable power gating */
 318         r = jpeg_v2_0_disable_power_gating(adev);
 319         if (r)
 320                 return r;
 321
 322         /* JPEG disable CGC */
 323         jpeg_v2_0_disable_clock_gating(adev);
 324
 325         WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 326
 327         /* enable JMI channel */
 328         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
 329                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 330
 331         /* enable System Interrupt for JRBC */
 332         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
 333                 JPEG_SYS_INT_EN__DJRBC_MASK,
 334                 ~JPEG_SYS_INT_EN__DJRBC_MASK);
 335
 336         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 337         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
 338         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
 339                 lower_32_bits(ring->gpu_addr));
 340         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
 341                 upper_32_bits(ring->gpu_addr));
 342         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
 343         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
 344         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
 345         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
 346         ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 347
 348         return 0;
 349 }
 350
 351 /**
 352  * jpeg_v2_0_stop - stop JPEG block
 353  *
 354  * @adev: amdgpu_device pointer
 355  *
 356  * stop the JPEG block
 357  */
 358 static int jpeg_v2_0_stop(struct amdgpu_device *adev)
 359 {
 360         int r;
 361
 362         /* reset JMI */
 363         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
 364                 UVD_JMI_CNTL__SOFT_RESET_MASK,
 365                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 366
 367         /* enable JPEG CGC */
 368         jpeg_v2_0_enable_clock_gating(adev);
 369
 370         /* enable power gating */
 371         r = jpeg_v2_0_enable_power_gating(adev);
 372         if (r)
 373                 return r;
 374
 375         if (adev->pm.dpm_enabled)
 376                 amdgpu_dpm_enable_jpeg(adev, false);
 377
 378         return 0;
 379 }
 380
 381 /**
 382  * jpeg_v2_0_dec_ring_get_rptr - get read pointer
 383  *
 384  * @ring: amdgpu_ring pointer
 385  *
 386  * Returns the current hardware read pointer
 387  */
 388 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
 389 {
 390         struct amdgpu_device *adev = ring->adev;
 391
 392         return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
 393 }
 394
 395 /**
 396  * jpeg_v2_0_dec_ring_get_wptr - get write pointer
 397  *
 398  * @ring: amdgpu_ring pointer
 399  *
 400  * Returns the current hardware write pointer
 401  */
 402 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
 403 {
 404         struct amdgpu_device *adev = ring->adev;
 405
 406         if (ring->use_doorbell)
 407                 return *ring->wptr_cpu_addr;
 408         else
 409                 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 410 }
 411
 412 /**
 413  * jpeg_v2_0_dec_ring_set_wptr - set write pointer
 414  *
 415  * @ring: amdgpu_ring pointer
 416  *
 417  * Commits the write pointer to the hardware
 418  */
 419 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 420 {
 421         struct amdgpu_device *adev = ring->adev;
 422
 423         if (ring->use_doorbell) {
 424                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
 425                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 426         } else {
 427                 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
 428         }
 429 }
 430
 431 /**
 432  * jpeg_v2_0_dec_ring_insert_start - insert a start command
 433  *
 434  * @ring: amdgpu_ring pointer
 435  *
 436  * Write a start command to the ring.
 437  */
 438 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
 439 {
 440         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 441                 0, 0, PACKETJ_TYPE0));
 442         amdgpu_ring_write(ring, 0x68e04);
 443
 444         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 445                 0, 0, PACKETJ_TYPE0));
 446         amdgpu_ring_write(ring, 0x80010000);
 447 }
 448
 449 /**
 450  * jpeg_v2_0_dec_ring_insert_end - insert a end command
 451  *
 452  * @ring: amdgpu_ring pointer
 453  *
 454  * Write a end command to the ring.
 455  */
 456 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
 457 {
 458         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 459                 0, 0, PACKETJ_TYPE0));
 460         amdgpu_ring_write(ring, 0x68e04);
 461
 462         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 463                 0, 0, PACKETJ_TYPE0));
 464         amdgpu_ring_write(ring, 0x00010000);
 465 }
 466
 467 /**
 468  * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
 469  *
 470  * @ring: amdgpu_ring pointer
 471  * @addr: address
 472  * @seq: sequence number
 473  * @flags: fence related flags
 474  *
 475  * Write a fence and a trap command to the ring.
 476  */
 477 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 478                                 unsigned flags)
 479 {
 480         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 481
 482         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
 483                 0, 0, PACKETJ_TYPE0));
 484         amdgpu_ring_write(ring, seq);
 485
 486         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
 487                 0, 0, PACKETJ_TYPE0));
 488         amdgpu_ring_write(ring, seq);
 489
 490         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
 491                 0, 0, PACKETJ_TYPE0));
 492         amdgpu_ring_write(ring, lower_32_bits(addr));
 493
 494         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
 495                 0, 0, PACKETJ_TYPE0));
 496         amdgpu_ring_write(ring, upper_32_bits(addr));
 497
 498         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
 499                 0, 0, PACKETJ_TYPE0));
 500         amdgpu_ring_write(ring, 0x8);
 501
 502         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
 503                 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
 504         amdgpu_ring_write(ring, 0);
 505
 506         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 507                 0, 0, PACKETJ_TYPE0));
 508         amdgpu_ring_write(ring, 0x3fbc);
 509
 510         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 511                 0, 0, PACKETJ_TYPE0));
 512         amdgpu_ring_write(ring, 0x1);
 513
 514         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
 515         amdgpu_ring_write(ring, 0);
 516 }
 517
 518 /**
 519  * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
 520  *
 521  * @ring: amdgpu_ring pointer
 522  * @job: job to retrieve vmid from
 523  * @ib: indirect buffer to execute
 524  * @flags: unused
 525  *
 526  * Write ring commands to execute the indirect buffer.
 527  */
 528 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
 529                                 struct amdgpu_job *job,
 530                                 struct amdgpu_ib *ib,
 531                                 uint32_t flags)
 532 {
 533         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 534
 535         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET,
 536                 0, 0, PACKETJ_TYPE0));
 537         amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT));
 538
 539         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
 540                 0, 0, PACKETJ_TYPE0));
 541         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
 542
 543         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
 544                 0, 0, PACKETJ_TYPE0));
 545         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
 546
 547         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
 548                 0, 0, PACKETJ_TYPE0));
 549         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 550
 551         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
 552                 0, 0, PACKETJ_TYPE0));
 553         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 554
 555         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
 556                 0, 0, PACKETJ_TYPE0));
 557         amdgpu_ring_write(ring, ib->length_dw);
 558
 559         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
 560                 0, 0, PACKETJ_TYPE0));
 561         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
 562
 563         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
 564                 0, 0, PACKETJ_TYPE0));
 565         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
 566
 567         amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
 568         amdgpu_ring_write(ring, 0);
 569
 570         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
 571                 0, 0, PACKETJ_TYPE0));
 572         amdgpu_ring_write(ring, 0x01400200);
 573
 574         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
 575                 0, 0, PACKETJ_TYPE0));
 576         amdgpu_ring_write(ring, 0x2);
 577
 578         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
 579                 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
 580         amdgpu_ring_write(ring, 0x2);
 581 }
 582
 583 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
 584                                 uint32_t val, uint32_t mask)
 585 {
 586         uint32_t reg_offset = (reg << 2);
 587
 588         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
 589                 0, 0, PACKETJ_TYPE0));
 590         amdgpu_ring_write(ring, 0x01400200);
 591
 592         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
 593                 0, 0, PACKETJ_TYPE0));
 594         amdgpu_ring_write(ring, val);
 595
 596         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 597                 0, 0, PACKETJ_TYPE0));
 598         if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
 599                 amdgpu_ring_write(ring, 0);
 600                 amdgpu_ring_write(ring,
 601                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
 602         } else {
 603                 amdgpu_ring_write(ring, reg_offset);
 604                 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 605                         0, 0, PACKETJ_TYPE3));
 606         }
 607         amdgpu_ring_write(ring, mask);
 608 }
 609
 610 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
 611                                 unsigned vmid, uint64_t pd_addr)
 612 {
 613         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
 614         uint32_t data0, data1, mask;
 615
 616         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 617
 618         /* wait for register write */
 619         data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
 620         data1 = lower_32_bits(pd_addr);
 621         mask = 0xffffffff;
 622         jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
 623 }
 624
 625 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
 626 {
 627         uint32_t reg_offset = (reg << 2);
 628
 629         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 630                 0, 0, PACKETJ_TYPE0));
 631         if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
 632                 amdgpu_ring_write(ring, 0);
 633                 amdgpu_ring_write(ring,
 634                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
 635         } else {
 636                 amdgpu_ring_write(ring, reg_offset);
 637                 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 638                         0, 0, PACKETJ_TYPE0));
 639         }
 640         amdgpu_ring_write(ring, val);
 641 }
 642
 643 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
 644 {
 645         int i;
 646
 647         WARN_ON(ring->wptr % 2 || count % 2);
 648
 649         for (i = 0; i < count / 2; i++) {
 650                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
 651                 amdgpu_ring_write(ring, 0);
 652         }
 653 }
 654
 655 static bool jpeg_v2_0_is_idle(void *handle)
 656 {
 657         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 658
 659         return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
 660                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
 661                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
 662 }
 663
 664 static int jpeg_v2_0_wait_for_idle(void *handle)
 665 {
 666         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 667         int ret;
 668
 669         ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
 670                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
 671
 672         return ret;
 673 }
 674
 675 static int jpeg_v2_0_set_clockgating_state(void *handle,
 676                                           enum amd_clockgating_state state)
 677 {
 678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 679         bool enable = (state == AMD_CG_STATE_GATE);
 680
 681         if (enable) {
 682                 if (!jpeg_v2_0_is_idle(handle))
 683                         return -EBUSY;
 684                 jpeg_v2_0_enable_clock_gating(adev);
 685         } else {
 686                 jpeg_v2_0_disable_clock_gating(adev);
 687         }
 688
 689         return 0;
 690 }
 691
 692 static int jpeg_v2_0_set_powergating_state(void *handle,
 693                                         enum amd_powergating_state state)
 694 {
 695         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 696         int ret;
 697
 698         if (state == adev->jpeg.cur_state)
 699                 return 0;
 700
 701         if (state == AMD_PG_STATE_GATE)
 702                 ret = jpeg_v2_0_stop(adev);
 703         else
 704                 ret = jpeg_v2_0_start(adev);
 705
 706         if (!ret)
 707                 adev->jpeg.cur_state = state;
 708
 709         return ret;
 710 }
 711
 712 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
 713                                         struct amdgpu_irq_src *source,
 714                                         unsigned type,
 715                                         enum amdgpu_interrupt_state state)
 716 {
 717         return 0;
 718 }
 719
 720 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
 721                                       struct amdgpu_irq_src *source,
 722                                       struct amdgpu_iv_entry *entry)
 723 {
 724         DRM_DEBUG("IH: JPEG TRAP\n");
 725
 726         switch (entry->src_id) {
 727         case VCN_2_0__SRCID__JPEG_DECODE:
 728                 amdgpu_fence_process(adev->jpeg.inst->ring_dec);
 729                 break;
 730         default:
 731                 DRM_ERROR("Unhandled interrupt: %d %d\n",
 732                           entry->src_id, entry->src_data[0]);
 733                 break;
 734         }
 735
 736         return 0;
 737 }
 738
 739 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
 740         .name = "jpeg_v2_0",
 741         .early_init = jpeg_v2_0_early_init,
 742         .late_init = NULL,
 743         .sw_init = jpeg_v2_0_sw_init,
 744         .sw_fini = jpeg_v2_0_sw_fini,
 745         .hw_init = jpeg_v2_0_hw_init,
 746         .hw_fini = jpeg_v2_0_hw_fini,
 747         .suspend = jpeg_v2_0_suspend,
 748         .resume = jpeg_v2_0_resume,
 749         .is_idle = jpeg_v2_0_is_idle,
 750         .wait_for_idle = jpeg_v2_0_wait_for_idle,
 751         .check_soft_reset = NULL,
 752         .pre_soft_reset = NULL,
 753         .soft_reset = NULL,
 754         .post_soft_reset = NULL,
 755         .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
 756         .set_powergating_state = jpeg_v2_0_set_powergating_state,
 757         .dump_ip_state = NULL,
 758         .print_ip_state = NULL,
 759 };
 760
 761 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
 762         .type = AMDGPU_RING_TYPE_VCN_JPEG,
 763         .align_mask = 0xf,
 764         .get_rptr = jpeg_v2_0_dec_ring_get_rptr,
 765         .get_wptr = jpeg_v2_0_dec_ring_get_wptr,
 766         .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
 767         .emit_frame_size =
 768                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 769                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 770                 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
 771                 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
 772                 8 + 16,
 773         .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */
 774         .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 775         .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 776         .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
 777         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
 778         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 779         .insert_nop = jpeg_v2_0_dec_ring_nop,
 780         .insert_start = jpeg_v2_0_dec_ring_insert_start,
 781         .insert_end = jpeg_v2_0_dec_ring_insert_end,
 782         .pad_ib = amdgpu_ring_generic_pad_ib,
 783         .begin_use = amdgpu_jpeg_ring_begin_use,
 784         .end_use = amdgpu_jpeg_ring_end_use,
 785         .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
 786         .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
 787         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 788 };
 789
 790 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 791 {
 792         adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;
 793 }
 794
 795 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
 796         .set = jpeg_v2_0_set_interrupt_state,
 797         .process = jpeg_v2_0_process_interrupt,
 798 };
 799
 800 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
 801 {
 802         adev->jpeg.inst->irq.num_types = 1;
 803         adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
 804 }
 805
 806 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = {
 807                 .type = AMD_IP_BLOCK_TYPE_JPEG,
 808                 .major = 2,
 809                 .minor = 0,
 810                 .rev = 0,
 811                 .funcs = &jpeg_v2_0_ip_funcs,
 812 };