drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_11_0_0_offset.h"
  30 #include "gc/gc_11_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v11_structs.h"
  33 #include "mes_v11_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
  41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
  42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin");
  43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
  44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
  45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin");
  46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
  47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
  48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin");
  49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
  50
  51 static int mes_v11_0_hw_fini(void *handle);
  52 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
  53 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
  54
  55 #define MES_EOP_SIZE   2048
  56
  57 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
  58 {
  59         struct amdgpu_device *adev = ring->adev;
  60
  61         if (ring->use_doorbell) {
  62                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  63                              ring->wptr);
  64                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  65         } else {
  66                 BUG();
  67         }
  68 }
  69
  70 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
  71 {
  72         return *ring->rptr_cpu_addr;
  73 }
  74
  75 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
  76 {
  77         u64 wptr;
  78
  79         if (ring->use_doorbell)
  80                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  81         else
  82                 BUG();
  83         return wptr;
  84 }
  85
  86 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
  87         .type = AMDGPU_RING_TYPE_MES,
  88         .align_mask = 1,
  89         .nop = 0,
  90         .support_64bit_ptrs = true,
  91         .get_rptr = mes_v11_0_ring_get_rptr,
  92         .get_wptr = mes_v11_0_ring_get_wptr,
  93         .set_wptr = mes_v11_0_ring_set_wptr,
  94         .insert_nop = amdgpu_ring_insert_nop,
  95 };
  96
  97 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
  98                                                     void *pkt, int size,
  99                                                     int api_status_off)
 100 {
 101         int ndw = size / 4;
 102         signed long r;
 103         union MESAPI__ADD_QUEUE *x_pkt = pkt;
 104         struct MES_API_STATUS *api_status;
 105         struct amdgpu_device *adev = mes->adev;
 106         struct amdgpu_ring *ring = &mes->ring;
 107         unsigned long flags;
 108         signed long timeout = adev->usec_timeout;
 109
 110         if (amdgpu_emu_mode) {
 111                 timeout *= 100;
 112         } else if (amdgpu_sriov_vf(adev)) {
 113                 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
 114                 timeout = 15 * 600 * 1000;
 115         }
 116         BUG_ON(size % 4 != 0);
 117
 118         spin_lock_irqsave(&mes->ring_lock, flags);
 119         if (amdgpu_ring_alloc(ring, ndw)) {
 120                 spin_unlock_irqrestore(&mes->ring_lock, flags);
 121                 return -ENOMEM;
 122         }
 123
 124         api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
 125         api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr;
 126         api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq;
 127
 128         amdgpu_ring_write_multiple(ring, pkt, ndw);
 129         amdgpu_ring_commit(ring);
 130         spin_unlock_irqrestore(&mes->ring_lock, flags);
 131
 132         DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
 133
 134         r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
 135                       timeout);
 136         if (r < 1) {
 137                 DRM_ERROR("MES failed to response msg=%d\n",
 138                           x_pkt->header.opcode);
 139
 140                 while (halt_if_hws_hang)
 141                         schedule();
 142
 143                 return -ETIMEDOUT;
 144         }
 145
 146         return 0;
 147 }
 148
 149 static int convert_to_mes_queue_type(int queue_type)
 150 {
 151         if (queue_type == AMDGPU_RING_TYPE_GFX)
 152                 return MES_QUEUE_TYPE_GFX;
 153         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 154                 return MES_QUEUE_TYPE_COMPUTE;
 155         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 156                 return MES_QUEUE_TYPE_SDMA;
 157         else
 158                 BUG();
 159         return -1;
 160 }
 161
 162 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 163                                   struct mes_add_queue_input *input)
 164 {
 165         struct amdgpu_device *adev = mes->adev;
 166         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 167         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
 168         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 169
 170         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 171
 172         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 173         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 174         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 175
 176         mes_add_queue_pkt.process_id = input->process_id;
 177         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 178         mes_add_queue_pkt.process_va_start = input->process_va_start;
 179         mes_add_queue_pkt.process_va_end = input->process_va_end;
 180         mes_add_queue_pkt.process_quantum = input->process_quantum;
 181         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 182         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 183         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 184         mes_add_queue_pkt.inprocess_gang_priority =
 185                 input->inprocess_gang_priority;
 186         mes_add_queue_pkt.gang_global_priority_level =
 187                 input->gang_global_priority_level;
 188         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 189         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 190
 191         if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
 192                         AMDGPU_MES_API_VERSION_SHIFT) >= 2)
 193                 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
 194         else
 195                 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 196
 197         mes_add_queue_pkt.queue_type =
 198                 convert_to_mes_queue_type(input->queue_type);
 199         mes_add_queue_pkt.paging = input->paging;
 200         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 201         mes_add_queue_pkt.gws_base = input->gws_base;
 202         mes_add_queue_pkt.gws_size = input->gws_size;
 203         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 204         mes_add_queue_pkt.tma_addr = input->tma_addr;
 205         mes_add_queue_pkt.trap_en = input->trap_en;
 206         mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
 207         mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 208
 209         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 210         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 211         mes_add_queue_pkt.gds_size = input->queue_size;
 212
 213         mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled;
 214
 215         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 216                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 217                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 218 }
 219
 220 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
 221                                      struct mes_remove_queue_input *input)
 222 {
 223         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 224
 225         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 226
 227         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 228         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 229         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 230
 231         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 232         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 233
 234         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 235                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 236                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 237 }
 238
 239 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 240                         struct mes_unmap_legacy_queue_input *input)
 241 {
 242         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 243
 244         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 245
 246         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 247         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 248         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 249
 250         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 251         mes_remove_queue_pkt.gang_context_addr = 0;
 252
 253         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 254         mes_remove_queue_pkt.queue_id = input->queue_id;
 255
 256         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 257                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 258                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 259                 mes_remove_queue_pkt.tf_data =
 260                         lower_32_bits(input->trail_fence_data);
 261         } else {
 262                 mes_remove_queue_pkt.unmap_legacy_queue = 1;
 263                 mes_remove_queue_pkt.queue_type =
 264                         convert_to_mes_queue_type(input->queue_type);
 265         }
 266
 267         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 268                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 269                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 270 }
 271
 272 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
 273                                   struct mes_suspend_gang_input *input)
 274 {
 275         return 0;
 276 }
 277
 278 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
 279                                  struct mes_resume_gang_input *input)
 280 {
 281         return 0;
 282 }
 283
 284 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
 285 {
 286         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 287
 288         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 289
 290         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 291         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 292         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 293
 294         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 295                         &mes_status_pkt, sizeof(mes_status_pkt),
 296                         offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
 297 }
 298
 299 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
 300                              struct mes_misc_op_input *input)
 301 {
 302         union MESAPI__MISC misc_pkt;
 303
 304         memset(&misc_pkt, 0, sizeof(misc_pkt));
 305
 306         misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
 307         misc_pkt.header.opcode = MES_SCH_API_MISC;
 308         misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 309
 310         switch (input->op) {
 311         case MES_MISC_OP_READ_REG:
 312                 misc_pkt.opcode = MESAPI_MISC__READ_REG;
 313                 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
 314                 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
 315                 break;
 316         case MES_MISC_OP_WRITE_REG:
 317                 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
 318                 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
 319                 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
 320                 break;
 321         case MES_MISC_OP_WRM_REG_WAIT:
 322                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 323                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
 324                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 325                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 326                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 327                 misc_pkt.wait_reg_mem.reg_offset2 = 0;
 328                 break;
 329         case MES_MISC_OP_WRM_REG_WR_WAIT:
 330                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 331                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
 332                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 333                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 334                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 335                 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
 336                 break;
 337         case MES_MISC_OP_SET_SHADER_DEBUGGER:
 338                 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
 339                 misc_pkt.set_shader_debugger.process_context_addr =
 340                                 input->set_shader_debugger.process_context_addr;
 341                 misc_pkt.set_shader_debugger.flags.u32all =
 342                                 input->set_shader_debugger.flags.u32all;
 343                 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
 344                                 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
 345                 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
 346                                 input->set_shader_debugger.tcp_watch_cntl,
 347                                 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
 348                 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
 349                 break;
 350         default:
 351                 DRM_ERROR("unsupported misc op (%d) \n", input->op);
 352                 return -EINVAL;
 353         }
 354
 355         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 356                         &misc_pkt, sizeof(misc_pkt),
 357                         offsetof(union MESAPI__MISC, api_status));
 358 }
 359
 360 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 361 {
 362         int i;
 363         struct amdgpu_device *adev = mes->adev;
 364         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 365
 366         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 367
 368         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 369         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 370         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 371
 372         mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 373         mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 374         mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 375         mes_set_hw_res_pkt.paging_vmid = 0;
 376         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
 377         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 378                 mes->query_status_fence_gpu_addr;
 379
 380         for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 381                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
 382                         mes->compute_hqd_mask[i];
 383
 384         for (i = 0; i < MAX_GFX_PIPES; i++)
 385                 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
 386
 387         for (i = 0; i < MAX_SDMA_PIPES; i++)
 388                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
 389
 390         for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 391                 mes_set_hw_res_pkt.aggregated_doorbells[i] =
 392                         mes->aggregated_doorbells[i];
 393
 394         for (i = 0; i < 5; i++) {
 395                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 396                 mes_set_hw_res_pkt.mmhub_base[i] =
 397                                 adev->reg_offset[MMHUB_HWIP][0][i];
 398                 mes_set_hw_res_pkt.osssys_base[i] =
 399                 adev->reg_offset[OSSSYS_HWIP][0][i];
 400         }
 401
 402         mes_set_hw_res_pkt.disable_reset = 1;
 403         mes_set_hw_res_pkt.disable_mes_log = 1;
 404         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 405         mes_set_hw_res_pkt.enable_reg_active_poll = 1;
 406         mes_set_hw_res_pkt.oversubscription_timer = 50;
 407
 408         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 409                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 410                         offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
 411 }
 412
 413 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
 414 {
 415         struct amdgpu_device *adev = mes->adev;
 416         uint32_t data;
 417
 418         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
 419         data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
 420                   CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
 421                   CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
 422         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
 423                 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
 424         data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
 425         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
 426
 427         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
 428         data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
 429                   CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
 430                   CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
 431         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
 432                 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
 433         data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
 434         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
 435
 436         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
 437         data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
 438                   CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
 439                   CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
 440         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
 441                 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
 442         data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
 443         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
 444
 445         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
 446         data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
 447                   CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
 448                   CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
 449         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
 450                 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
 451         data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
 452         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
 453
 454         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
 455         data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
 456                   CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
 457                   CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
 458         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
 459                 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
 460         data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
 461         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
 462
 463         data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
 464         WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
 465 }
 466
 467 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
 468         .add_hw_queue = mes_v11_0_add_hw_queue,
 469         .remove_hw_queue = mes_v11_0_remove_hw_queue,
 470         .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
 471         .suspend_gang = mes_v11_0_suspend_gang,
 472         .resume_gang = mes_v11_0_resume_gang,
 473         .misc_op = mes_v11_0_misc_op,
 474 };
 475
 476 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 477                                            enum admgpu_mes_pipe pipe)
 478 {
 479         int r;
 480         const struct mes_firmware_header_v1_0 *mes_hdr;
 481         const __le32 *fw_data;
 482         unsigned fw_size;
 483
 484         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 485                 adev->mes.fw[pipe]->data;
 486
 487         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 488                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 489         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 490
 491         r = amdgpu_bo_create_reserved(adev, fw_size,
 492                                       PAGE_SIZE,
 493                                       AMDGPU_GEM_DOMAIN_VRAM |
 494                                       AMDGPU_GEM_DOMAIN_GTT,
 495                                       &adev->mes.ucode_fw_obj[pipe],
 496                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 497                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 498         if (r) {
 499                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 500                 return r;
 501         }
 502
 503         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 504
 505         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 506         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 507
 508         return 0;
 509 }
 510
 511 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 512                                                 enum admgpu_mes_pipe pipe)
 513 {
 514         int r;
 515         const struct mes_firmware_header_v1_0 *mes_hdr;
 516         const __le32 *fw_data;
 517         unsigned fw_size;
 518
 519         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 520                 adev->mes.fw[pipe]->data;
 521
 522         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 523                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 524         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 525
 526         r = amdgpu_bo_create_reserved(adev, fw_size,
 527                                       64 * 1024,
 528                                       AMDGPU_GEM_DOMAIN_VRAM |
 529                                       AMDGPU_GEM_DOMAIN_GTT,
 530                                       &adev->mes.data_fw_obj[pipe],
 531                                       &adev->mes.data_fw_gpu_addr[pipe],
 532                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 533         if (r) {
 534                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 535                 return r;
 536         }
 537
 538         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 539
 540         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 541         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 542
 543         return 0;
 544 }
 545
 546 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
 547                                          enum admgpu_mes_pipe pipe)
 548 {
 549         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 550                               &adev->mes.data_fw_gpu_addr[pipe],
 551                               (void **)&adev->mes.data_fw_ptr[pipe]);
 552
 553         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 554                               &adev->mes.ucode_fw_gpu_addr[pipe],
 555                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 556 }
 557
 558 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 559 {
 560         uint64_t ucode_addr;
 561         uint32_t pipe, data = 0;
 562
 563         if (enable) {
 564                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 565                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 566                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 567                              MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
 568                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 569
 570                 mutex_lock(&adev->srbm_mutex);
 571                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 572                         if (!adev->enable_mes_kiq &&
 573                             pipe == AMDGPU_MES_KIQ_PIPE)
 574                                 continue;
 575
 576                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 577
 578                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 579                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 580                                      lower_32_bits(ucode_addr));
 581                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 582                                      upper_32_bits(ucode_addr));
 583                 }
 584                 soc21_grbm_select(adev, 0, 0, 0, 0);
 585                 mutex_unlock(&adev->srbm_mutex);
 586
 587                 /* unhalt MES and activate pipe0 */
 588                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 589                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 590                                      adev->enable_mes_kiq ? 1 : 0);
 591                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 592
 593                 if (amdgpu_emu_mode)
 594                         msleep(100);
 595                 else
 596                         udelay(50);
 597         } else {
 598                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 599                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 600                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 601                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 602                                      MES_INVALIDATE_ICACHE, 1);
 603                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 604                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 605                                      adev->enable_mes_kiq ? 1 : 0);
 606                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 607                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 608         }
 609 }
 610
 611 /* This function is for backdoor MES firmware */
 612 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
 613                                     enum admgpu_mes_pipe pipe, bool prime_icache)
 614 {
 615         int r;
 616         uint32_t data;
 617         uint64_t ucode_addr;
 618
 619         mes_v11_0_enable(adev, false);
 620
 621         if (!adev->mes.fw[pipe])
 622                 return -EINVAL;
 623
 624         r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
 625         if (r)
 626                 return r;
 627
 628         r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
 629         if (r) {
 630                 mes_v11_0_free_ucode_buffers(adev, pipe);
 631                 return r;
 632         }
 633
 634         mutex_lock(&adev->srbm_mutex);
 635         /* me=3, pipe=0, queue=0 */
 636         soc21_grbm_select(adev, 3, pipe, 0, 0);
 637
 638         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 639
 640         /* set ucode start address */
 641         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 642         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 643                      lower_32_bits(ucode_addr));
 644         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 645                      upper_32_bits(ucode_addr));
 646
 647         /* set ucode fimrware address */
 648         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 649                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 650         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 651                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 652
 653         /* set ucode instruction cache boundary to 2M-1 */
 654         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 655
 656         /* set ucode data firmware address */
 657         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 658                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 659         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 660                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 661
 662         /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
 663         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
 664
 665         if (prime_icache) {
 666                 /* invalidate ICACHE */
 667                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 668                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 669                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 670                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 671
 672                 /* prime the ICACHE. */
 673                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 674                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 675                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 676         }
 677
 678         soc21_grbm_select(adev, 0, 0, 0, 0);
 679         mutex_unlock(&adev->srbm_mutex);
 680
 681         return 0;
 682 }
 683
 684 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
 685                                       enum admgpu_mes_pipe pipe)
 686 {
 687         int r;
 688         u32 *eop;
 689
 690         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 691                               AMDGPU_GEM_DOMAIN_GTT,
 692                               &adev->mes.eop_gpu_obj[pipe],
 693                               &adev->mes.eop_gpu_addr[pipe],
 694                               (void **)&eop);
 695         if (r) {
 696                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 697                 return r;
 698         }
 699
 700         memset(eop, 0,
 701                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 702
 703         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 704         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 705
 706         return 0;
 707 }
 708
 709 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
 710 {
 711         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 712         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 713         uint32_t tmp;
 714
 715         memset(mqd, 0, sizeof(*mqd));
 716
 717         mqd->header = 0xC0310800;
 718         mqd->compute_pipelinestat_enable = 0x00000001;
 719         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 720         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 721         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 722         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 723         mqd->compute_misc_reserved = 0x00000007;
 724
 725         eop_base_addr = ring->eop_gpu_addr >> 8;
 726
 727         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 728         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 729         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 730                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 731
 732         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 733         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 734         mqd->cp_hqd_eop_control = tmp;
 735
 736         /* disable the queue if it's active */
 737         ring->wptr = 0;
 738         mqd->cp_hqd_pq_rptr = 0;
 739         mqd->cp_hqd_pq_wptr_lo = 0;
 740         mqd->cp_hqd_pq_wptr_hi = 0;
 741
 742         /* set the pointer to the MQD */
 743         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 744         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 745
 746         /* set MQD vmid to 0 */
 747         tmp = regCP_MQD_CONTROL_DEFAULT;
 748         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 749         mqd->cp_mqd_control = tmp;
 750
 751         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 752         hqd_gpu_addr = ring->gpu_addr >> 8;
 753         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 754         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 755
 756         /* set the wb address whether it's enabled or not */
 757         wb_gpu_addr = ring->rptr_gpu_addr;
 758         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 759         mqd->cp_hqd_pq_rptr_report_addr_hi =
 760                 upper_32_bits(wb_gpu_addr) & 0xffff;
 761
 762         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 763         wb_gpu_addr = ring->wptr_gpu_addr;
 764         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 765         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 766
 767         /* set up the HQD, this is similar to CP_RB0_CNTL */
 768         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 769         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 770                             (order_base_2(ring->ring_size / 4) - 1));
 771         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 772                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 773         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 774         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 775         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 776         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 777         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 778         mqd->cp_hqd_pq_control = tmp;
 779
 780         /* enable doorbell */
 781         tmp = 0;
 782         if (ring->use_doorbell) {
 783                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 784                                     DOORBELL_OFFSET, ring->doorbell_index);
 785                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 786                                     DOORBELL_EN, 1);
 787                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 788                                     DOORBELL_SOURCE, 0);
 789                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 790                                     DOORBELL_HIT, 0);
 791         } else
 792                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 793                                     DOORBELL_EN, 0);
 794         mqd->cp_hqd_pq_doorbell_control = tmp;
 795
 796         mqd->cp_hqd_vmid = 0;
 797         /* activate the queue */
 798         mqd->cp_hqd_active = 1;
 799
 800         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
 801         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
 802                             PRELOAD_SIZE, 0x55);
 803         mqd->cp_hqd_persistent_state = tmp;
 804
 805         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
 806         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
 807         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
 808
 809         amdgpu_device_flush_hdp(ring->adev, NULL);
 810         return 0;
 811 }
 812
 813 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
 814 {
 815         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 816         struct amdgpu_device *adev = ring->adev;
 817         uint32_t data = 0;
 818
 819         mutex_lock(&adev->srbm_mutex);
 820         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 821
 822         /* set CP_HQD_VMID.VMID = 0. */
 823         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
 824         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
 825         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
 826
 827         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
 828         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
 829         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
 830                              DOORBELL_EN, 0);
 831         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
 832
 833         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
 834         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
 835         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
 836
 837         /* set CP_MQD_CONTROL.VMID=0 */
 838         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
 839         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
 840         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
 841
 842         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
 843         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
 844         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
 845
 846         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
 847         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
 848                      mqd->cp_hqd_pq_rptr_report_addr_lo);
 849         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 850                      mqd->cp_hqd_pq_rptr_report_addr_hi);
 851
 852         /* set CP_HQD_PQ_CONTROL */
 853         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
 854
 855         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
 856         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
 857                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
 858         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 859                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
 860
 861         /* set CP_HQD_PQ_DOORBELL_CONTROL */
 862         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
 863                      mqd->cp_hqd_pq_doorbell_control);
 864
 865         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
 866         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
 867
 868         /* set CP_HQD_ACTIVE.ACTIVE=1 */
 869         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
 870
 871         soc21_grbm_select(adev, 0, 0, 0, 0);
 872         mutex_unlock(&adev->srbm_mutex);
 873 }
 874
 875 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
 876 {
 877         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 878         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
 879         int r;
 880
 881         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 882                 return -EINVAL;
 883
 884         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
 885         if (r) {
 886                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 887                 return r;
 888         }
 889
 890         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
 891
 892         return amdgpu_ring_test_helper(kiq_ring);
 893 }
 894
 895 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
 896                                 enum admgpu_mes_pipe pipe)
 897 {
 898         struct amdgpu_ring *ring;
 899         int r;
 900
 901         if (pipe == AMDGPU_MES_KIQ_PIPE)
 902                 ring = &adev->gfx.kiq[0].ring;
 903         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 904                 ring = &adev->mes.ring;
 905         else
 906                 BUG();
 907
 908         if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
 909             (amdgpu_in_reset(adev) || adev->in_suspend)) {
 910                 *(ring->wptr_cpu_addr) = 0;
 911                 *(ring->rptr_cpu_addr) = 0;
 912                 amdgpu_ring_clear_ring(ring);
 913         }
 914
 915         r = mes_v11_0_mqd_init(ring);
 916         if (r)
 917                 return r;
 918
 919         if (pipe == AMDGPU_MES_SCHED_PIPE) {
 920                 r = mes_v11_0_kiq_enable_queue(adev);
 921                 if (r)
 922                         return r;
 923         } else {
 924                 mes_v11_0_queue_init_register(ring);
 925         }
 926
 927         /* get MES scheduler/KIQ versions */
 928         mutex_lock(&adev->srbm_mutex);
 929         soc21_grbm_select(adev, 3, pipe, 0, 0);
 930
 931         if (pipe == AMDGPU_MES_SCHED_PIPE)
 932                 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
 933         else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
 934                 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
 935
 936         soc21_grbm_select(adev, 0, 0, 0, 0);
 937         mutex_unlock(&adev->srbm_mutex);
 938
 939         return 0;
 940 }
 941
 942 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
 943 {
 944         struct amdgpu_ring *ring;
 945
 946         ring = &adev->mes.ring;
 947
 948         ring->funcs = &mes_v11_0_ring_funcs;
 949
 950         ring->me = 3;
 951         ring->pipe = 0;
 952         ring->queue = 0;
 953
 954         ring->ring_obj = NULL;
 955         ring->use_doorbell = true;
 956         ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
 957         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
 958         ring->no_scheduler = true;
 959         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 960
 961         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
 962                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
 963 }
 964
 965 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
 966 {
 967         struct amdgpu_ring *ring;
 968
 969         spin_lock_init(&adev->gfx.kiq[0].ring_lock);
 970
 971         ring = &adev->gfx.kiq[0].ring;
 972
 973         ring->me = 3;
 974         ring->pipe = 1;
 975         ring->queue = 0;
 976
 977         ring->adev = NULL;
 978         ring->ring_obj = NULL;
 979         ring->use_doorbell = true;
 980         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
 981         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
 982         ring->no_scheduler = true;
 983         sprintf(ring->name, "mes_kiq_%d.%d.%d",
 984                 ring->me, ring->pipe, ring->queue);
 985
 986         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
 987                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
 988 }
 989
 990 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
 991                                  enum admgpu_mes_pipe pipe)
 992 {
 993         int r, mqd_size = sizeof(struct v11_compute_mqd);
 994         struct amdgpu_ring *ring;
 995
 996         if (pipe == AMDGPU_MES_KIQ_PIPE)
 997                 ring = &adev->gfx.kiq[0].ring;
 998         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 999                 ring = &adev->mes.ring;
1000         else
1001                 BUG();
1002
1003         if (ring->mqd_obj)
1004                 return 0;
1005
1006         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1007                                     AMDGPU_GEM_DOMAIN_VRAM |
1008                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1009                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
1010         if (r) {
1011                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1012                 return r;
1013         }
1014
1015         memset(ring->mqd_ptr, 0, mqd_size);
1016
1017         /* prepare MQD backup */
1018         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1019         if (!adev->mes.mqd_backup[pipe]) {
1020                 dev_warn(adev->dev,
1021                          "no memory to create MQD backup for ring %s\n",
1022                          ring->name);
1023                 return -ENOMEM;
1024         }
1025
1026         return 0;
1027 }
1028
1029 static int mes_v11_0_sw_init(void *handle)
1030 {
1031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032         int pipe, r;
1033
1034         adev->mes.funcs = &mes_v11_0_funcs;
1035         adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1036         adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1037
1038         r = amdgpu_mes_init(adev);
1039         if (r)
1040                 return r;
1041
1042         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1043                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1044                         continue;
1045
1046                 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1047                 if (r)
1048                         return r;
1049
1050                 r = mes_v11_0_mqd_sw_init(adev, pipe);
1051                 if (r)
1052                         return r;
1053         }
1054
1055         if (adev->enable_mes_kiq) {
1056                 r = mes_v11_0_kiq_ring_init(adev);
1057                 if (r)
1058                         return r;
1059         }
1060
1061         r = mes_v11_0_ring_init(adev);
1062         if (r)
1063                 return r;
1064
1065         return 0;
1066 }
1067
1068 static int mes_v11_0_sw_fini(void *handle)
1069 {
1070         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1071         int pipe;
1072
1073         amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1074         amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1075
1076         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1077                 kfree(adev->mes.mqd_backup[pipe]);
1078
1079                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1080                                       &adev->mes.eop_gpu_addr[pipe],
1081                                       NULL);
1082                 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1083         }
1084
1085         amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1086                               &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1087                               &adev->gfx.kiq[0].ring.mqd_ptr);
1088
1089         amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1090                               &adev->mes.ring.mqd_gpu_addr,
1091                               &adev->mes.ring.mqd_ptr);
1092
1093         amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1094         amdgpu_ring_fini(&adev->mes.ring);
1095
1096         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1097                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1098                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1099         }
1100
1101         amdgpu_mes_fini(adev);
1102         return 0;
1103 }
1104
1105 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring)
1106 {
1107         uint32_t data;
1108         int i;
1109         struct amdgpu_device *adev = ring->adev;
1110
1111         mutex_lock(&adev->srbm_mutex);
1112         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1113
1114         /* disable the queue if it's active */
1115         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1116                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1117                 for (i = 0; i < adev->usec_timeout; i++) {
1118                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1119                                 break;
1120                         udelay(1);
1121                 }
1122         }
1123         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1124         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1125                                 DOORBELL_EN, 0);
1126         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1127                                 DOORBELL_HIT, 1);
1128         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1129
1130         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1131
1132         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1133         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1134         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1135
1136         soc21_grbm_select(adev, 0, 0, 0, 0);
1137         mutex_unlock(&adev->srbm_mutex);
1138 }
1139
1140 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1141 {
1142         uint32_t tmp;
1143         struct amdgpu_device *adev = ring->adev;
1144
1145         /* tell RLC which is KIQ queue */
1146         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1147         tmp &= 0xffffff00;
1148         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1149         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1150         tmp |= 0x80;
1151         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1152 }
1153
1154 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
1155 {
1156         uint32_t tmp;
1157
1158         /* tell RLC which is KIQ dequeue */
1159         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1160         tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
1161         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1162 }
1163
1164 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1165 {
1166         int r = 0;
1167
1168         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1169
1170                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1171                 if (r) {
1172                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1173                         return r;
1174                 }
1175
1176                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1177                 if (r) {
1178                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1179                         return r;
1180                 }
1181
1182         }
1183
1184         mes_v11_0_enable(adev, true);
1185
1186         mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
1187
1188         r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1189         if (r)
1190                 goto failure;
1191
1192         return r;
1193
1194 failure:
1195         mes_v11_0_hw_fini(adev);
1196         return r;
1197 }
1198
1199 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1200 {
1201         if (adev->mes.ring.sched.ready) {
1202                 mes_v11_0_kiq_dequeue(&adev->mes.ring);
1203                 adev->mes.ring.sched.ready = false;
1204         }
1205
1206         if (amdgpu_sriov_vf(adev)) {
1207                 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring);
1208                 mes_v11_0_kiq_clear(adev);
1209         }
1210
1211         mes_v11_0_enable(adev, false);
1212
1213         return 0;
1214 }
1215
1216 static int mes_v11_0_hw_init(void *handle)
1217 {
1218         int r;
1219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
1221         if (!adev->enable_mes_kiq) {
1222                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1223                         r = mes_v11_0_load_microcode(adev,
1224                                              AMDGPU_MES_SCHED_PIPE, true);
1225                         if (r) {
1226                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1227                                 return r;
1228                         }
1229                 }
1230
1231                 mes_v11_0_enable(adev, true);
1232         }
1233
1234         r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1235         if (r)
1236                 goto failure;
1237
1238         r = mes_v11_0_set_hw_resources(&adev->mes);
1239         if (r)
1240                 goto failure;
1241
1242         mes_v11_0_init_aggregated_doorbell(&adev->mes);
1243
1244         r = mes_v11_0_query_sched_status(&adev->mes);
1245         if (r) {
1246                 DRM_ERROR("MES is busy\n");
1247                 goto failure;
1248         }
1249
1250         /*
1251          * Disable KIQ ring usage from the driver once MES is enabled.
1252          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1253          * with MES enabled.
1254          */
1255         adev->gfx.kiq[0].ring.sched.ready = false;
1256         adev->mes.ring.sched.ready = true;
1257
1258         return 0;
1259
1260 failure:
1261         mes_v11_0_hw_fini(adev);
1262         return r;
1263 }
1264
1265 static int mes_v11_0_hw_fini(void *handle)
1266 {
1267         return 0;
1268 }
1269
1270 static int mes_v11_0_suspend(void *handle)
1271 {
1272         int r;
1273         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1274
1275         r = amdgpu_mes_suspend(adev);
1276         if (r)
1277                 return r;
1278
1279         return mes_v11_0_hw_fini(adev);
1280 }
1281
1282 static int mes_v11_0_resume(void *handle)
1283 {
1284         int r;
1285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1286
1287         r = mes_v11_0_hw_init(adev);
1288         if (r)
1289                 return r;
1290
1291         return amdgpu_mes_resume(adev);
1292 }
1293
1294 static int mes_v11_0_early_init(void *handle)
1295 {
1296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297         int pipe, r;
1298
1299         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1300                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1301                         continue;
1302                 r = amdgpu_mes_init_microcode(adev, pipe);
1303                 if (r)
1304                         return r;
1305         }
1306
1307         return 0;
1308 }
1309
1310 static int mes_v11_0_late_init(void *handle)
1311 {
1312         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313
1314         /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1315         if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
1316             (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
1317                 amdgpu_mes_self_test(adev);
1318
1319         return 0;
1320 }
1321
1322 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1323         .name = "mes_v11_0",
1324         .early_init = mes_v11_0_early_init,
1325         .late_init = mes_v11_0_late_init,
1326         .sw_init = mes_v11_0_sw_init,
1327         .sw_fini = mes_v11_0_sw_fini,
1328         .hw_init = mes_v11_0_hw_init,
1329         .hw_fini = mes_v11_0_hw_fini,
1330         .suspend = mes_v11_0_suspend,
1331         .resume = mes_v11_0_resume,
1332 };
1333
1334 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1335         .type = AMD_IP_BLOCK_TYPE_MES,
1336         .major = 11,
1337         .minor = 0,
1338         .rev = 0,
1339         .funcs = &mes_v11_0_ip_funcs,
1340 };