drivers/gpu/drm/omapdrm/omap_irq.c

   1 /*
   2  * drivers/gpu/drm/omapdrm/omap_irq.c
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  * Author: Rob Clark <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "omap_drv.h"
  21
  22 struct omap_irq_wait {
  23         struct list_head node;
  24         wait_queue_head_t wq;
  25         uint32_t irqmask;
  26         int count;
  27 };
  28
  29 /* call with wait_lock and dispc runtime held */
  30 static void omap_irq_update(struct drm_device *dev)
  31 {
  32         struct omap_drm_private *priv = dev->dev_private;
  33         struct omap_irq_wait *wait;
  34         uint32_t irqmask = priv->irq_mask;
  35
  36         assert_spin_locked(&priv->wait_lock);
  37
  38         list_for_each_entry(wait, &priv->wait_list, node)
  39                 irqmask |= wait->irqmask;
  40
  41         DBG("irqmask=%08x", irqmask);
  42
  43         dispc_write_irqenable(irqmask);
  44         dispc_read_irqenable();        /* flush posted write */
  45 }
  46
  47 static void omap_irq_wait_handler(struct omap_irq_wait *wait)
  48 {
  49         wait->count--;
  50         wake_up(&wait->wq);
  51 }
  52
  53 struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
  54                 uint32_t irqmask, int count)
  55 {
  56         struct omap_drm_private *priv = dev->dev_private;
  57         struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
  58         unsigned long flags;
  59
  60         init_waitqueue_head(&wait->wq);
  61         wait->irqmask = irqmask;
  62         wait->count = count;
  63
  64         spin_lock_irqsave(&priv->wait_lock, flags);
  65         list_add(&wait->node, &priv->wait_list);
  66         omap_irq_update(dev);
  67         spin_unlock_irqrestore(&priv->wait_lock, flags);
  68
  69         return wait;
  70 }
  71
  72 int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
  73                 unsigned long timeout)
  74 {
  75         struct omap_drm_private *priv = dev->dev_private;
  76         unsigned long flags;
  77         int ret;
  78
  79         ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout);
  80
  81         spin_lock_irqsave(&priv->wait_lock, flags);
  82         list_del(&wait->node);
  83         omap_irq_update(dev);
  84         spin_unlock_irqrestore(&priv->wait_lock, flags);
  85
  86         kfree(wait);
  87
  88         return ret == 0 ? -1 : 0;
  89 }
  90
  91 /**
  92  * enable_vblank - enable vblank interrupt events
  93  * @dev: DRM device
  94  * @pipe: which irq to enable
  95  *
  96  * Enable vblank interrupts for @crtc.  If the device doesn't have
  97  * a hardware vblank counter, this routine should be a no-op, since
  98  * interrupts will have to stay on to keep the count accurate.
  99  *
 100  * RETURNS
 101  * Zero on success, appropriate errno if the given @crtc's vblank
 102  * interrupt cannot be enabled.
 103  */
 104 int omap_irq_enable_vblank(struct drm_device *dev, unsigned int pipe)
 105 {
 106         struct omap_drm_private *priv = dev->dev_private;
 107         struct drm_crtc *crtc = priv->crtcs[pipe];
 108         unsigned long flags;
 109
 110         DBG("dev=%p, crtc=%u", dev, pipe);
 111
 112         spin_lock_irqsave(&priv->wait_lock, flags);
 113         priv->irq_mask |= dispc_mgr_get_vsync_irq(omap_crtc_channel(crtc));
 114         omap_irq_update(dev);
 115         spin_unlock_irqrestore(&priv->wait_lock, flags);
 116
 117         return 0;
 118 }
 119
 120 /**
 121  * disable_vblank - disable vblank interrupt events
 122  * @dev: DRM device
 123  * @pipe: which irq to enable
 124  *
 125  * Disable vblank interrupts for @crtc.  If the device doesn't have
 126  * a hardware vblank counter, this routine should be a no-op, since
 127  * interrupts will have to stay on to keep the count accurate.
 128  */
 129 void omap_irq_disable_vblank(struct drm_device *dev, unsigned int pipe)
 130 {
 131         struct omap_drm_private *priv = dev->dev_private;
 132         struct drm_crtc *crtc = priv->crtcs[pipe];
 133         unsigned long flags;
 134
 135         DBG("dev=%p, crtc=%u", dev, pipe);
 136
 137         spin_lock_irqsave(&priv->wait_lock, flags);
 138         priv->irq_mask &= ~dispc_mgr_get_vsync_irq(omap_crtc_channel(crtc));
 139         omap_irq_update(dev);
 140         spin_unlock_irqrestore(&priv->wait_lock, flags);
 141 }
 142
 143 static void omap_irq_fifo_underflow(struct omap_drm_private *priv,
 144                                     u32 irqstatus)
 145 {
 146         static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL,
 147                                       DEFAULT_RATELIMIT_BURST);
 148         static const struct {
 149                 const char *name;
 150                 u32 mask;
 151         } sources[] = {
 152                 { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW },
 153                 { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW },
 154                 { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW },
 155                 { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW },
 156         };
 157
 158         const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW
 159                        | DISPC_IRQ_VID1_FIFO_UNDERFLOW
 160                        | DISPC_IRQ_VID2_FIFO_UNDERFLOW
 161                        | DISPC_IRQ_VID3_FIFO_UNDERFLOW;
 162         unsigned int i;
 163
 164         spin_lock(&priv->wait_lock);
 165         irqstatus &= priv->irq_mask & mask;
 166         spin_unlock(&priv->wait_lock);
 167
 168         if (!irqstatus)
 169                 return;
 170
 171         if (!__ratelimit(&_rs))
 172                 return;
 173
 174         DRM_ERROR("FIFO underflow on ");
 175
 176         for (i = 0; i < ARRAY_SIZE(sources); ++i) {
 177                 if (sources[i].mask & irqstatus)
 178                         pr_cont("%s ", sources[i].name);
 179         }
 180
 181         pr_cont("(0x%08x)\n", irqstatus);
 182 }
 183
 184 static void omap_irq_ocp_error_handler(u32 irqstatus)
 185 {
 186         if (!(irqstatus & DISPC_IRQ_OCP_ERR))
 187                 return;
 188
 189         DRM_ERROR("OCP error\n");
 190 }
 191
 192 static irqreturn_t omap_irq_handler(int irq, void *arg)
 193 {
 194         struct drm_device *dev = (struct drm_device *) arg;
 195         struct omap_drm_private *priv = dev->dev_private;
 196         struct omap_irq_wait *wait, *n;
 197         unsigned long flags;
 198         unsigned int id;
 199         u32 irqstatus;
 200
 201         irqstatus = dispc_read_irqstatus();
 202         dispc_clear_irqstatus(irqstatus);
 203         dispc_read_irqstatus();        /* flush posted write */
 204
 205         VERB("irqs: %08x", irqstatus);
 206
 207         for (id = 0; id < priv->num_crtcs; id++) {
 208                 struct drm_crtc *crtc = priv->crtcs[id];
 209                 enum omap_channel channel = omap_crtc_channel(crtc);
 210
 211                 if (irqstatus & dispc_mgr_get_vsync_irq(channel)) {
 212                         drm_handle_vblank(dev, id);
 213                         omap_crtc_vblank_irq(crtc);
 214                 }
 215
 216                 if (irqstatus & dispc_mgr_get_sync_lost_irq(channel))
 217                         omap_crtc_error_irq(crtc, irqstatus);
 218         }
 219
 220         omap_irq_ocp_error_handler(irqstatus);
 221         omap_irq_fifo_underflow(priv, irqstatus);
 222
 223         spin_lock_irqsave(&priv->wait_lock, flags);
 224         list_for_each_entry_safe(wait, n, &priv->wait_list, node) {
 225                 if (wait->irqmask & irqstatus)
 226                         omap_irq_wait_handler(wait);
 227         }
 228         spin_unlock_irqrestore(&priv->wait_lock, flags);
 229
 230         return IRQ_HANDLED;
 231 }
 232
 233 static const u32 omap_underflow_irqs[] = {
 234         [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW,
 235         [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW,
 236         [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW,
 237         [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW,
 238 };
 239
 240 /*
 241  * We need a special version, instead of just using drm_irq_install(),
 242  * because we need to register the irq via omapdss.  Once omapdss and
 243  * omapdrm are merged together we can assign the dispc hwmod data to
 244  * ourselves and drop these and just use drm_irq_{install,uninstall}()
 245  */
 246
 247 int omap_drm_irq_install(struct drm_device *dev)
 248 {
 249         struct omap_drm_private *priv = dev->dev_private;
 250         unsigned int num_mgrs = dss_feat_get_num_mgrs();
 251         unsigned int max_planes;
 252         unsigned int i;
 253         int ret;
 254
 255         spin_lock_init(&priv->wait_lock);
 256         INIT_LIST_HEAD(&priv->wait_list);
 257
 258         priv->irq_mask = DISPC_IRQ_OCP_ERR;
 259
 260         max_planes = min(ARRAY_SIZE(priv->planes),
 261                          ARRAY_SIZE(omap_underflow_irqs));
 262         for (i = 0; i < max_planes; ++i) {
 263                 if (priv->planes[i])
 264                         priv->irq_mask |= omap_underflow_irqs[i];
 265         }
 266
 267         for (i = 0; i < num_mgrs; ++i)
 268                 priv->irq_mask |= dispc_mgr_get_sync_lost_irq(i);
 269
 270         dispc_runtime_get();
 271         dispc_clear_irqstatus(0xffffffff);
 272         dispc_runtime_put();
 273
 274         ret = dispc_request_irq(omap_irq_handler, dev);
 275         if (ret < 0)
 276                 return ret;
 277
 278         dev->irq_enabled = true;
 279
 280         return 0;
 281 }
 282
 283 void omap_drm_irq_uninstall(struct drm_device *dev)
 284 {
 285         unsigned long irqflags;
 286         int i;
 287
 288         if (!dev->irq_enabled)
 289                 return;
 290
 291         dev->irq_enabled = false;
 292
 293         /* Wake up any waiters so they don't hang. */
 294         if (dev->num_crtcs) {
 295                 spin_lock_irqsave(&dev->vbl_lock, irqflags);
 296                 for (i = 0; i < dev->num_crtcs; i++) {
 297                         wake_up(&dev->vblank[i].queue);
 298                         dev->vblank[i].enabled = false;
 299                         dev->vblank[i].last =
 300                                 dev->driver->get_vblank_counter(dev, i);
 301                 }
 302                 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
 303         }
 304
 305         dispc_free_irq(dev);
 306 }